* [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map
@ 2022-03-22 8:44 Mullati Siva
2022-03-22 8:44 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva
` (4 more replies)
0 siblings, 5 replies; 7+ messages in thread
From: Mullati Siva @ 2022-03-22 8:44 UTC (permalink / raw)
To: intel-gfx, siva.mullati; +Cc: lucas.demarchi
From: Siva Mullati <siva.mullati@intel.com>
This is continuation to the below patch series to use iosys map
APIs, to use CT commands and descriptors.
https://patchwork.freedesktop.org/series/99711/
Siva Mullati (1):
drm/i915/guc: Convert ct buffer to iosys_map
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 200 +++++++++++++---------
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +-
2 files changed, 127 insertions(+), 82 deletions(-)
--
2.33.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map 2022-03-22 8:44 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map Mullati Siva @ 2022-03-22 8:44 ` Mullati Siva 2022-04-02 4:13 ` Lucas De Marchi 2022-03-22 9:25 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Refactor CT access to use iosys_map (rev2) Patchwork ` (3 subsequent siblings) 4 siblings, 1 reply; 7+ messages in thread From: Mullati Siva @ 2022-03-22 8:44 UTC (permalink / raw) To: intel-gfx, siva.mullati; +Cc: lucas.demarchi From: Siva Mullati <siva.mullati@intel.com> Convert CT commands and descriptors to use iosys_map rather than plain pointer and save it in the intel_guc_ct_buffer struct. This will help with ct_write and ct_read for cmd send and receive after the initialization by abstracting the IO vs system memory. Signed-off-by: Siva Mullati <siva.mullati@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 200 +++++++++++++--------- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +- 2 files changed, 127 insertions(+), 82 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c index f01325cd1b62..1c21ced44106 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c @@ -44,6 +44,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) #define CT_PROBE_ERROR(_ct, _fmt, ...) \ i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__) +#define ct_desc_read(desc_map_, field_) \ + iosys_map_rd_field(desc_map_, 0, struct guc_ct_buffer_desc, field_) +#define ct_desc_write(desc_map_, field_, val_) \ + iosys_map_wr_field(desc_map_, 0, struct guc_ct_buffer_desc, field_, val_) + /** * DOC: CTB Blob * @@ -76,6 +81,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) #define CTB_G2H_BUFFER_SIZE (4 * CTB_H2G_BUFFER_SIZE) #define G2H_ROOM_BUFFER_SIZE (CTB_G2H_BUFFER_SIZE / 4) +#define CTB_SEND_DESC_OFFSET (0X0000) +#define CTB_RECV_DESC_OFFSET (CTB_DESC_SIZE) +#define CTB_SEND_CMDS_OFFSET (2 * CTB_DESC_SIZE) +#define CTB_RECV_CMDS_OFFSET (2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE) + struct ct_request { struct list_head link; u32 fence; @@ -113,9 +123,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct) init_waitqueue_head(&ct->wq); } -static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc) +static void guc_ct_buffer_desc_init(struct iosys_map *desc) { - memset(desc, 0, sizeof(*desc)); + iosys_map_memset(desc, 0, 0, sizeof(struct guc_ct_buffer_desc)); } static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) @@ -128,17 +138,18 @@ static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space; atomic_set(&ctb->space, space); - guc_ct_buffer_desc_init(ctb->desc); + guc_ct_buffer_desc_init(&ctb->desc_map); } static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb, - struct guc_ct_buffer_desc *desc, - u32 *cmds, u32 size_in_bytes, u32 resv_space) + struct iosys_map *desc, + struct iosys_map *cmds, + u32 size_in_bytes, u32 resv_space) { GEM_BUG_ON(size_in_bytes % 4); - ctb->desc = desc; - ctb->cmds = cmds; + ctb->desc_map = *desc; + ctb->cmds_map = *cmds; ctb->size = size_in_bytes / 4; ctb->resv_space = resv_space / 4; @@ -218,12 +229,13 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send, int intel_guc_ct_init(struct intel_guc_ct *ct) { struct intel_guc *guc = ct_to_guc(ct); - struct guc_ct_buffer_desc *desc; + struct iosys_map blob_map; + struct iosys_map desc_map; + struct iosys_map cmds_map; u32 blob_size; u32 cmds_size; u32 resv_space; void *blob; - u32 *cmds; int err; err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO); @@ -242,27 +254,35 @@ int intel_guc_ct_init(struct intel_guc_ct *ct) CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size); - /* store pointers to desc and cmds for send ctb */ - desc = blob; - cmds = blob + 2 * CTB_DESC_SIZE; + if (i915_gem_object_is_lmem(ct->vma->obj)) + iosys_map_set_vaddr_iomem(&blob_map, + (void __iomem *)blob); + else + iosys_map_set_vaddr(&blob_map, blob); + + /* store sysmap to desc_map and cmds_map for send ctb */ + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_DESC_OFFSET); + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_CMDS_OFFSET); cmds_size = CTB_H2G_BUFFER_SIZE; resv_space = 0; - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send", - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, - resv_space); + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "send", + (u32)CTB_SEND_DESC_OFFSET, (u32)CTB_SEND_CMDS_OFFSET, + cmds_size, resv_space); - guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space); + guc_ct_buffer_init(&ct->ctbs.send, + &desc_map, &cmds_map, cmds_size, resv_space); - /* store pointers to desc and cmds for recv ctb */ - desc = blob + CTB_DESC_SIZE; - cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE; + /* store sysmap to desc_map and cmds_map for recv ctb */ + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_DESC_OFFSET); + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_CMDS_OFFSET); cmds_size = CTB_G2H_BUFFER_SIZE; resv_space = G2H_ROOM_BUFFER_SIZE; - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv", - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, - resv_space); + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "recv", + (u32)CTB_RECV_DESC_OFFSET, (u32)CTB_RECV_CMDS_OFFSET, + cmds_size, resv_space); - guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space); + guc_ct_buffer_init(&ct->ctbs.recv, + &desc_map, &cmds_map, cmds_size, resv_space); return 0; } @@ -279,6 +299,10 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct) tasklet_kill(&ct->receive_tasklet); i915_vma_unpin_and_release(&ct->vma, I915_VMA_RELEASE_MAP); + iosys_map_clear(&ct->ctbs.send.desc_map); + iosys_map_clear(&ct->ctbs.send.cmds_map); + iosys_map_clear(&ct->ctbs.recv.desc_map); + iosys_map_clear(&ct->ctbs.recv.cmds_map); memset(ct, 0, sizeof(*ct)); } @@ -291,8 +315,8 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct) int intel_guc_ct_enable(struct intel_guc_ct *ct) { struct intel_guc *guc = ct_to_guc(ct); + struct iosys_map blob_map; u32 base, desc, cmds, size; - void *blob; int err; GEM_BUG_ON(ct->enabled); @@ -302,9 +326,14 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj)); base = intel_guc_ggtt_offset(guc, ct->vma); + if (i915_gem_object_is_lmem(ct->vma->obj)) + iosys_map_set_vaddr_iomem(&blob_map, (void __iomem *) + __px_vaddr(ct->vma->obj)); + else + iosys_map_set_vaddr(&blob_map, __px_vaddr(ct->vma->obj)); + /* blob should start with send descriptor */ - blob = __px_vaddr(ct->vma->obj); - GEM_BUG_ON(blob != ct->ctbs.send.desc); + GEM_BUG_ON(!iosys_map_is_equal(&blob_map, &ct->ctbs.send.desc_map)); /* (re)initialize descriptors */ guc_ct_buffer_reset(&ct->ctbs.send); @@ -314,15 +343,15 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) * Register both CT buffers starting with RECV buffer. * Descriptors are in first half of the blob. */ - desc = base + ptrdiff(ct->ctbs.recv.desc, blob); - cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob); + desc = base + CTB_RECV_DESC_OFFSET; + cmds = base + CTB_RECV_CMDS_OFFSET; size = ct->ctbs.recv.size * 4; err = ct_register_buffer(ct, false, desc, cmds, size); if (unlikely(err)) goto err_out; - desc = base + ptrdiff(ct->ctbs.send.desc, blob); - cmds = base + ptrdiff(ct->ctbs.send.cmds, blob); + desc = base + CTB_SEND_DESC_OFFSET; + cmds = base + CTB_SEND_CMDS_OFFSET; size = ct->ctbs.send.size * 4; err = ct_register_buffer(ct, true, desc, cmds, size); if (unlikely(err)) @@ -371,31 +400,33 @@ static int ct_write(struct intel_guc_ct *ct, u32 fence, u32 flags) { struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; - struct guc_ct_buffer_desc *desc = ctb->desc; u32 tail = ctb->tail; u32 size = ctb->size; u32 header; u32 hxg; u32 type; - u32 *cmds = ctb->cmds; + u32 status = ct_desc_read(&ctb->desc_map, status); unsigned int i; - if (unlikely(desc->status)) + if (unlikely(status)) goto corrupted; GEM_BUG_ON(tail > size); #ifdef CONFIG_DRM_I915_DEBUG_GUC - if (unlikely(tail != READ_ONCE(desc->tail))) { + if (unlikely(tail != ct_desc_read(&ctb->desc_map, tail))) { CT_ERROR(ct, "Tail was modified %u != %u\n", - desc->tail, tail); - desc->status |= GUC_CTB_STATUS_MISMATCH; + ct_desc_read(&ctb->desc_map, tail), tail); + status |= GUC_CTB_STATUS_MISMATCH; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } - if (unlikely(READ_ONCE(desc->head) >= size)) { + if (unlikely(ct_desc_read(&ctb->desc_map, head) >= size)) { CT_ERROR(ct, "Invalid head offset %u >= %u)\n", - desc->head, size); - desc->status |= GUC_CTB_STATUS_OVERFLOW; + ct_desc_read(&ctb->desc_map, head), size); + status = ct_desc_read(&ctb->desc_map, status) | + GUC_CTB_STATUS_OVERFLOW; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } #endif @@ -418,14 +449,14 @@ static int ct_write(struct intel_guc_ct *ct, CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n", tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]); - cmds[tail] = header; + iosys_map_wr(&ctb->cmds_map, (4 * tail), u32, header); tail = (tail + 1) % size; - cmds[tail] = hxg; + iosys_map_wr(&ctb->cmds_map, (4 * tail), u32, hxg); tail = (tail + 1) % size; for (i = 1; i < len; i++) { - cmds[tail] = action[i]; + iosys_map_wr(&ctb->cmds_map, (4 * tail), u32, action[i]); tail = (tail + 1) % size; } GEM_BUG_ON(tail > size); @@ -442,13 +473,14 @@ static int ct_write(struct intel_guc_ct *ct, atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space); /* now update descriptor */ - WRITE_ONCE(desc->tail, tail); + ct_desc_write(&ctb->desc_map, tail, tail); return 0; corrupted: CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", - desc->head, desc->tail, desc->status); + ct_desc_read(&ctb->desc_map, head), ct_desc_read(&ctb->desc_map, tail), + ct_desc_read(&ctb->desc_map, status)); ctb->broken = true; return -EPIPE; } @@ -499,20 +531,22 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct) bool ret = ktime_ms_delta(ktime_get(), ct->stall_time) > timeout; if (unlikely(ret)) { - struct guc_ct_buffer_desc *send = ct->ctbs.send.desc; - struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc; - CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n", ktime_ms_delta(ktime_get(), ct->stall_time), - send->status, recv->status); + ct_desc_read(&ct->ctbs.send.desc_map, status), + ct_desc_read(&ct->ctbs.recv.desc_map, status)); CT_ERROR(ct, "H2G Space: %u (Bytes)\n", atomic_read(&ct->ctbs.send.space) * 4); - CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head); - CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail); + CT_ERROR(ct, "Head: %u (Dwords)\n", + ct_desc_read(&ct->ctbs.send.desc_map, head)); + CT_ERROR(ct, "Tail: %u (Dwords)\n", + ct_desc_read(&ct->ctbs.send.desc_map, tail)); CT_ERROR(ct, "G2H Space: %u (Bytes)\n", atomic_read(&ct->ctbs.recv.space) * 4); - CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head); - CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail); + CT_ERROR(ct, "Head: %u\n (Dwords)", + ct_desc_read(&ct->ctbs.recv.desc_map, head)); + CT_ERROR(ct, "Tail: %u\n (Dwords)", + ct_desc_read(&ct->ctbs.recv.desc_map, tail)); ct->ctbs.send.broken = true; } @@ -549,18 +583,19 @@ static inline void g2h_release_space(struct intel_guc_ct *ct, u32 g2h_len_dw) static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw) { struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; - struct guc_ct_buffer_desc *desc = ctb->desc; u32 head; u32 space; + u32 status = ct_desc_read(&ctb->desc_map, status); if (atomic_read(&ctb->space) >= len_dw) return true; - head = READ_ONCE(desc->head); + head = ct_desc_read(&ctb->desc_map, head); if (unlikely(head > ctb->size)) { CT_ERROR(ct, "Invalid head offset %u >= %u)\n", head, ctb->size); - desc->status |= GUC_CTB_STATUS_OVERFLOW; + status |= GUC_CTB_STATUS_OVERFLOW; + ct_desc_write(&ctb->desc_map, status, status); ctb->broken = true; return false; } @@ -803,11 +838,10 @@ static void ct_free_msg(struct ct_incoming_msg *msg) static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) { struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv; - struct guc_ct_buffer_desc *desc = ctb->desc; u32 head = ctb->head; - u32 tail = READ_ONCE(desc->tail); + u32 tail = ct_desc_read(&ctb->desc_map, tail); u32 size = ctb->size; - u32 *cmds = ctb->cmds; + u32 status = ct_desc_read(&ctb->desc_map, status); s32 available; unsigned int len; unsigned int i; @@ -816,23 +850,26 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) if (unlikely(ctb->broken)) return -EPIPE; - if (unlikely(desc->status)) + if (unlikely(status)) goto corrupted; GEM_BUG_ON(head > size); #ifdef CONFIG_DRM_I915_DEBUG_GUC - if (unlikely(head != READ_ONCE(desc->head))) { + if (unlikely(head != ct_desc_read(&ctb->desc_map, head))) { CT_ERROR(ct, "Head was modified %u != %u\n", - desc->head, head); - desc->status |= GUC_CTB_STATUS_MISMATCH; + ct_desc_read(&ctb->desc_map, head), head); + status |= GUC_CTB_STATUS_MISMATCH; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } #endif if (unlikely(tail >= size)) { CT_ERROR(ct, "Invalid tail offset %u >= %u)\n", tail, size); - desc->status |= GUC_CTB_STATUS_OVERFLOW; + status = ct_desc_read(&ctb->desc_map, status) | + GUC_CTB_STATUS_OVERFLOW; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } @@ -849,7 +886,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size); GEM_BUG_ON(available < 0); - header = cmds[head]; + header = iosys_map_rd(&ctb->cmds_map, (4 * head), u32); head = (head + 1) % size; /* message len with header */ @@ -857,11 +894,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) if (unlikely(len > (u32)available)) { CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n", 4, &header, + 4 * (head + available - 1 > size ? size - head : + available - 1), ((__px_vaddr(ct->vma->obj) + + CTB_RECV_CMDS_OFFSET) + (4 * head)), 4 * (head + available - 1 > size ? - size - head : available - 1), &cmds[head], - 4 * (head + available - 1 > size ? - available - 1 - size + head : 0), &cmds[0]); - desc->status |= GUC_CTB_STATUS_UNDERFLOW; + available - 1 - size + head : 0), + (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET)); + status = ct_desc_read(&ctb->desc_map, status) | + GUC_CTB_STATUS_UNDERFLOW; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } @@ -869,17 +910,18 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) if (!*msg) { CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n", 4, &header, + 4 * (head + available - 1 > size ? size - head : + available - 1), (ctb->cmds_map.vaddr + (4 * head)), 4 * (head + available - 1 > size ? - size - head : available - 1), &cmds[head], - 4 * (head + available - 1 > size ? - available - 1 - size + head : 0), &cmds[0]); + available - 1 - size + head : 0), ctb->cmds_map.vaddr); return available; } (*msg)->msg[0] = header; for (i = 1; i < len; i++) { - (*msg)->msg[i] = cmds[head]; + (*msg)->msg[i] = iosys_map_rd(&ctb->cmds_map, + (4 * head), u32); head = (head + 1) % size; } CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg); @@ -888,13 +930,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) ctb->head = head; /* now update descriptor */ - WRITE_ONCE(desc->head, head); + ct_desc_write(&ctb->desc_map, head, head); return available - len; corrupted: CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", - desc->head, desc->tail, desc->status); + ct_desc_read(&ctb->desc_map, head), + ct_desc_read(&ctb->desc_map, tail), + ct_desc_read(&ctb->desc_map, status)); ctb->broken = true; return -EPIPE; } @@ -1211,13 +1255,13 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct, drm_printf(p, "H2G Space: %u\n", atomic_read(&ct->ctbs.send.space) * 4); drm_printf(p, "Head: %u\n", - ct->ctbs.send.desc->head); + ct_desc_read(&ct->ctbs.send.desc_map, head)); drm_printf(p, "Tail: %u\n", - ct->ctbs.send.desc->tail); + ct_desc_read(&ct->ctbs.send.desc_map, tail)); drm_printf(p, "G2H Space: %u\n", atomic_read(&ct->ctbs.recv.space) * 4); drm_printf(p, "Head: %u\n", - ct->ctbs.recv.desc->head); + ct_desc_read(&ct->ctbs.recv.desc_map, head)); drm_printf(p, "Tail: %u\n", - ct->ctbs.recv.desc->tail); + ct_desc_read(&ct->ctbs.recv.desc_map, tail)); } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h index f709a19c7e21..867fe13fb47d 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h @@ -7,6 +7,7 @@ #define _INTEL_GUC_CT_H_ #include <linux/interrupt.h> +#include <linux/iosys-map.h> #include <linux/spinlock.h> #include <linux/workqueue.h> #include <linux/ktime.h> @@ -32,8 +33,8 @@ struct drm_printer; * holds the commands. * * @lock: protects access to the commands buffer and buffer descriptor - * @desc: pointer to the buffer descriptor - * @cmds: pointer to the commands buffer + * @desc: iosys map to the buffer descriptor + * @cmds: iosys map to the commands buffer * @size: size of the commands buffer in dwords * @resv_space: reserved space in buffer in dwords * @head: local shadow copy of head in dwords @@ -43,8 +44,8 @@ struct drm_printer; */ struct intel_guc_ct_buffer { spinlock_t lock; - struct guc_ct_buffer_desc *desc; - u32 *cmds; + struct iosys_map desc_map; + struct iosys_map cmds_map; u32 size; u32 resv_space; u32 tail; -- 2.33.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map 2022-03-22 8:44 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva @ 2022-04-02 4:13 ` Lucas De Marchi 0 siblings, 0 replies; 7+ messages in thread From: Lucas De Marchi @ 2022-04-02 4:13 UTC (permalink / raw) To: Mullati Siva; +Cc: intel-gfx On Tue, Mar 22, 2022 at 02:14:37PM +0530, Mullati Siva wrote: >From: Siva Mullati <siva.mullati@intel.com> > >Convert CT commands and descriptors to use iosys_map rather >than plain pointer and save it in the intel_guc_ct_buffer struct. >This will help with ct_write and ct_read for cmd send and receive >after the initialization by abstracting the IO vs system memory. > >Signed-off-by: Siva Mullati <siva.mullati@intel.com> >--- > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 200 +++++++++++++--------- > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +- > 2 files changed, 127 insertions(+), 82 deletions(-) > >diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c >index f01325cd1b62..1c21ced44106 100644 >--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c >+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c >@@ -44,6 +44,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) > #define CT_PROBE_ERROR(_ct, _fmt, ...) \ > i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__) > >+#define ct_desc_read(desc_map_, field_) \ >+ iosys_map_rd_field(desc_map_, 0, struct guc_ct_buffer_desc, field_) >+#define ct_desc_write(desc_map_, field_, val_) \ >+ iosys_map_wr_field(desc_map_, 0, struct guc_ct_buffer_desc, field_, val_) >+ > /** > * DOC: CTB Blob > * >@@ -76,6 +81,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) > #define CTB_G2H_BUFFER_SIZE (4 * CTB_H2G_BUFFER_SIZE) > #define G2H_ROOM_BUFFER_SIZE (CTB_G2H_BUFFER_SIZE / 4) > >+#define CTB_SEND_DESC_OFFSET (0X0000) 0, or even better... 0u, so you don't have to cast to unsigned in other places >+#define CTB_RECV_DESC_OFFSET (CTB_DESC_SIZE) >+#define CTB_SEND_CMDS_OFFSET (2 * CTB_DESC_SIZE) >+#define CTB_RECV_CMDS_OFFSET (2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE) >+ > struct ct_request { > struct list_head link; > u32 fence; >@@ -113,9 +123,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct) > init_waitqueue_head(&ct->wq); > } > >-static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc) >+static void guc_ct_buffer_desc_init(struct iosys_map *desc) > { >- memset(desc, 0, sizeof(*desc)); >+ iosys_map_memset(desc, 0, 0, sizeof(struct guc_ct_buffer_desc)); > } > > static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) >@@ -128,17 +138,18 @@ static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) > space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space; > atomic_set(&ctb->space, space); > >- guc_ct_buffer_desc_init(ctb->desc); >+ guc_ct_buffer_desc_init(&ctb->desc_map); > } > > static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb, >- struct guc_ct_buffer_desc *desc, >- u32 *cmds, u32 size_in_bytes, u32 resv_space) >+ struct iosys_map *desc, >+ struct iosys_map *cmds, >+ u32 size_in_bytes, u32 resv_space) > { > GEM_BUG_ON(size_in_bytes % 4); > >- ctb->desc = desc; >- ctb->cmds = cmds; >+ ctb->desc_map = *desc; >+ ctb->cmds_map = *cmds; > ctb->size = size_in_bytes / 4; > ctb->resv_space = resv_space / 4; > >@@ -218,12 +229,13 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send, > int intel_guc_ct_init(struct intel_guc_ct *ct) > { > struct intel_guc *guc = ct_to_guc(ct); >- struct guc_ct_buffer_desc *desc; >+ struct iosys_map blob_map; >+ struct iosys_map desc_map; >+ struct iosys_map cmds_map; > u32 blob_size; > u32 cmds_size; > u32 resv_space; > void *blob; >- u32 *cmds; > int err; > > err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO); >@@ -242,27 +254,35 @@ int intel_guc_ct_init(struct intel_guc_ct *ct) > > CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size); > >- /* store pointers to desc and cmds for send ctb */ >- desc = blob; >- cmds = blob + 2 * CTB_DESC_SIZE; >+ if (i915_gem_object_is_lmem(ct->vma->obj)) >+ iosys_map_set_vaddr_iomem(&blob_map, >+ (void __iomem *)blob); >+ else >+ iosys_map_set_vaddr(&blob_map, blob); >+ >+ /* store sysmap to desc_map and cmds_map for send ctb */ >+ desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_DESC_OFFSET); >+ cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_CMDS_OFFSET); > cmds_size = CTB_H2G_BUFFER_SIZE; > resv_space = 0; >- CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send", >- ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, >- resv_space); >+ CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "send", >+ (u32)CTB_SEND_DESC_OFFSET, (u32)CTB_SEND_CMDS_OFFSET, >+ cmds_size, resv_space); > >- guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space); >+ guc_ct_buffer_init(&ct->ctbs.send, >+ &desc_map, &cmds_map, cmds_size, resv_space); > >- /* store pointers to desc and cmds for recv ctb */ >- desc = blob + CTB_DESC_SIZE; >- cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE; >+ /* store sysmap to desc_map and cmds_map for recv ctb */ >+ desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_DESC_OFFSET); >+ cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_CMDS_OFFSET); > cmds_size = CTB_G2H_BUFFER_SIZE; > resv_space = G2H_ROOM_BUFFER_SIZE; >- CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv", >- ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, >- resv_space); >+ CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "recv", >+ (u32)CTB_RECV_DESC_OFFSET, (u32)CTB_RECV_CMDS_OFFSET, >+ cmds_size, resv_space); > >- guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space); >+ guc_ct_buffer_init(&ct->ctbs.recv, >+ &desc_map, &cmds_map, cmds_size, resv_space); > > return 0; > } >@@ -279,6 +299,10 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct) > > tasklet_kill(&ct->receive_tasklet); > i915_vma_unpin_and_release(&ct->vma, I915_VMA_RELEASE_MAP); >+ iosys_map_clear(&ct->ctbs.send.desc_map); >+ iosys_map_clear(&ct->ctbs.send.cmds_map); >+ iosys_map_clear(&ct->ctbs.recv.desc_map); >+ iosys_map_clear(&ct->ctbs.recv.cmds_map); > memset(ct, 0, sizeof(*ct)); > } > >@@ -291,8 +315,8 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct) > int intel_guc_ct_enable(struct intel_guc_ct *ct) > { > struct intel_guc *guc = ct_to_guc(ct); >+ struct iosys_map blob_map; > u32 base, desc, cmds, size; >- void *blob; > int err; > > GEM_BUG_ON(ct->enabled); >@@ -302,9 +326,14 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) > GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj)); > base = intel_guc_ggtt_offset(guc, ct->vma); > >+ if (i915_gem_object_is_lmem(ct->vma->obj)) >+ iosys_map_set_vaddr_iomem(&blob_map, (void __iomem *) >+ __px_vaddr(ct->vma->obj)); >+ else >+ iosys_map_set_vaddr(&blob_map, __px_vaddr(ct->vma->obj)); >+ > /* blob should start with send descriptor */ >- blob = __px_vaddr(ct->vma->obj); >- GEM_BUG_ON(blob != ct->ctbs.send.desc); >+ GEM_BUG_ON(!iosys_map_is_equal(&blob_map, &ct->ctbs.send.desc_map)); > > /* (re)initialize descriptors */ > guc_ct_buffer_reset(&ct->ctbs.send); >@@ -314,15 +343,15 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) > * Register both CT buffers starting with RECV buffer. > * Descriptors are in first half of the blob. > */ >- desc = base + ptrdiff(ct->ctbs.recv.desc, blob); >- cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob); >+ desc = base + CTB_RECV_DESC_OFFSET; >+ cmds = base + CTB_RECV_CMDS_OFFSET; > size = ct->ctbs.recv.size * 4; > err = ct_register_buffer(ct, false, desc, cmds, size); > if (unlikely(err)) > goto err_out; > >- desc = base + ptrdiff(ct->ctbs.send.desc, blob); >- cmds = base + ptrdiff(ct->ctbs.send.cmds, blob); >+ desc = base + CTB_SEND_DESC_OFFSET; >+ cmds = base + CTB_SEND_CMDS_OFFSET; > size = ct->ctbs.send.size * 4; > err = ct_register_buffer(ct, true, desc, cmds, size); > if (unlikely(err)) >@@ -371,31 +400,33 @@ static int ct_write(struct intel_guc_ct *ct, > u32 fence, u32 flags) > { > struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; >- struct guc_ct_buffer_desc *desc = ctb->desc; > u32 tail = ctb->tail; > u32 size = ctb->size; > u32 header; > u32 hxg; > u32 type; >- u32 *cmds = ctb->cmds; >+ u32 status = ct_desc_read(&ctb->desc_map, status); > unsigned int i; > >- if (unlikely(desc->status)) >+ if (unlikely(status)) > goto corrupted; > > GEM_BUG_ON(tail > size); > > #ifdef CONFIG_DRM_I915_DEBUG_GUC >- if (unlikely(tail != READ_ONCE(desc->tail))) { >+ if (unlikely(tail != ct_desc_read(&ctb->desc_map, tail))) { > CT_ERROR(ct, "Tail was modified %u != %u\n", >- desc->tail, tail); >- desc->status |= GUC_CTB_STATUS_MISMATCH; >+ ct_desc_read(&ctb->desc_map, tail), tail); >+ status |= GUC_CTB_STATUS_MISMATCH; >+ ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } >- if (unlikely(READ_ONCE(desc->head) >= size)) { >+ if (unlikely(ct_desc_read(&ctb->desc_map, head) >= size)) { > CT_ERROR(ct, "Invalid head offset %u >= %u)\n", >- desc->head, size); >- desc->status |= GUC_CTB_STATUS_OVERFLOW; >+ ct_desc_read(&ctb->desc_map, head), size); >+ status = ct_desc_read(&ctb->desc_map, status) | >+ GUC_CTB_STATUS_OVERFLOW; >+ ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } > #endif >@@ -418,14 +449,14 @@ static int ct_write(struct intel_guc_ct *ct, > CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n", > tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]); > >- cmds[tail] = header; >+ iosys_map_wr(&ctb->cmds_map, (4 * tail), u32, header); excess parenthesis -------------^ > tail = (tail + 1) % size; > >- cmds[tail] = hxg; >+ iosys_map_wr(&ctb->cmds_map, (4 * tail), u32, hxg); and in other places like here > tail = (tail + 1) % size; > > for (i = 1; i < len; i++) { >- cmds[tail] = action[i]; >+ iosys_map_wr(&ctb->cmds_map, (4 * tail), u32, action[i]); > tail = (tail + 1) % size; > } > GEM_BUG_ON(tail > size); >@@ -442,13 +473,14 @@ static int ct_write(struct intel_guc_ct *ct, > atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space); > > /* now update descriptor */ >- WRITE_ONCE(desc->tail, tail); >+ ct_desc_write(&ctb->desc_map, tail, tail); too bad we will lose the _ONCE annotations. Eventually we may want to remove the memcpy[_fromio()] function call, but then we will need to pay attention to these. Not something to do here though, just thinking out loud. ... lots of changes in a single patch, but apparently it's ok. with above changes Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> thanks Lucas De Marchi > > return 0; > > corrupted: > CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", >- desc->head, desc->tail, desc->status); >+ ct_desc_read(&ctb->desc_map, head), ct_desc_read(&ctb->desc_map, tail), >+ ct_desc_read(&ctb->desc_map, status)); > ctb->broken = true; > return -EPIPE; > } >@@ -499,20 +531,22 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct) > bool ret = ktime_ms_delta(ktime_get(), ct->stall_time) > timeout; > > if (unlikely(ret)) { >- struct guc_ct_buffer_desc *send = ct->ctbs.send.desc; >- struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc; >- > CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n", > ktime_ms_delta(ktime_get(), ct->stall_time), >- send->status, recv->status); >+ ct_desc_read(&ct->ctbs.send.desc_map, status), >+ ct_desc_read(&ct->ctbs.recv.desc_map, status)); > CT_ERROR(ct, "H2G Space: %u (Bytes)\n", > atomic_read(&ct->ctbs.send.space) * 4); >- CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head); >- CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail); >+ CT_ERROR(ct, "Head: %u (Dwords)\n", >+ ct_desc_read(&ct->ctbs.send.desc_map, head)); >+ CT_ERROR(ct, "Tail: %u (Dwords)\n", >+ ct_desc_read(&ct->ctbs.send.desc_map, tail)); > CT_ERROR(ct, "G2H Space: %u (Bytes)\n", > atomic_read(&ct->ctbs.recv.space) * 4); >- CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head); >- CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail); >+ CT_ERROR(ct, "Head: %u\n (Dwords)", >+ ct_desc_read(&ct->ctbs.recv.desc_map, head)); >+ CT_ERROR(ct, "Tail: %u\n (Dwords)", >+ ct_desc_read(&ct->ctbs.recv.desc_map, tail)); > > ct->ctbs.send.broken = true; > } >@@ -549,18 +583,19 @@ static inline void g2h_release_space(struct intel_guc_ct *ct, u32 g2h_len_dw) > static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw) > { > struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; >- struct guc_ct_buffer_desc *desc = ctb->desc; > u32 head; > u32 space; >+ u32 status = ct_desc_read(&ctb->desc_map, status); > > if (atomic_read(&ctb->space) >= len_dw) > return true; > >- head = READ_ONCE(desc->head); >+ head = ct_desc_read(&ctb->desc_map, head); > if (unlikely(head > ctb->size)) { > CT_ERROR(ct, "Invalid head offset %u >= %u)\n", > head, ctb->size); >- desc->status |= GUC_CTB_STATUS_OVERFLOW; >+ status |= GUC_CTB_STATUS_OVERFLOW; >+ ct_desc_write(&ctb->desc_map, status, status); > ctb->broken = true; > return false; > } >@@ -803,11 +838,10 @@ static void ct_free_msg(struct ct_incoming_msg *msg) > static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > { > struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv; >- struct guc_ct_buffer_desc *desc = ctb->desc; > u32 head = ctb->head; >- u32 tail = READ_ONCE(desc->tail); >+ u32 tail = ct_desc_read(&ctb->desc_map, tail); > u32 size = ctb->size; >- u32 *cmds = ctb->cmds; >+ u32 status = ct_desc_read(&ctb->desc_map, status); > s32 available; > unsigned int len; > unsigned int i; >@@ -816,23 +850,26 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > if (unlikely(ctb->broken)) > return -EPIPE; > >- if (unlikely(desc->status)) >+ if (unlikely(status)) > goto corrupted; > > GEM_BUG_ON(head > size); > > #ifdef CONFIG_DRM_I915_DEBUG_GUC >- if (unlikely(head != READ_ONCE(desc->head))) { >+ if (unlikely(head != ct_desc_read(&ctb->desc_map, head))) { > CT_ERROR(ct, "Head was modified %u != %u\n", >- desc->head, head); >- desc->status |= GUC_CTB_STATUS_MISMATCH; >+ ct_desc_read(&ctb->desc_map, head), head); >+ status |= GUC_CTB_STATUS_MISMATCH; >+ ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } > #endif > if (unlikely(tail >= size)) { > CT_ERROR(ct, "Invalid tail offset %u >= %u)\n", > tail, size); >- desc->status |= GUC_CTB_STATUS_OVERFLOW; >+ status = ct_desc_read(&ctb->desc_map, status) | >+ GUC_CTB_STATUS_OVERFLOW; >+ ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } > >@@ -849,7 +886,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size); > GEM_BUG_ON(available < 0); > >- header = cmds[head]; >+ header = iosys_map_rd(&ctb->cmds_map, (4 * head), u32); > head = (head + 1) % size; > > /* message len with header */ >@@ -857,11 +894,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > if (unlikely(len > (u32)available)) { > CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n", > 4, &header, >+ 4 * (head + available - 1 > size ? size - head : >+ available - 1), ((__px_vaddr(ct->vma->obj) + >+ CTB_RECV_CMDS_OFFSET) + (4 * head)), > 4 * (head + available - 1 > size ? >- size - head : available - 1), &cmds[head], >- 4 * (head + available - 1 > size ? >- available - 1 - size + head : 0), &cmds[0]); >- desc->status |= GUC_CTB_STATUS_UNDERFLOW; >+ available - 1 - size + head : 0), >+ (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET)); >+ status = ct_desc_read(&ctb->desc_map, status) | >+ GUC_CTB_STATUS_UNDERFLOW; >+ ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } > >@@ -869,17 +910,18 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > if (!*msg) { > CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n", > 4, &header, >+ 4 * (head + available - 1 > size ? size - head : >+ available - 1), (ctb->cmds_map.vaddr + (4 * head)), > 4 * (head + available - 1 > size ? >- size - head : available - 1), &cmds[head], >- 4 * (head + available - 1 > size ? >- available - 1 - size + head : 0), &cmds[0]); >+ available - 1 - size + head : 0), ctb->cmds_map.vaddr); > return available; > } > > (*msg)->msg[0] = header; > > for (i = 1; i < len; i++) { >- (*msg)->msg[i] = cmds[head]; >+ (*msg)->msg[i] = iosys_map_rd(&ctb->cmds_map, >+ (4 * head), u32); > head = (head + 1) % size; > } > CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg); >@@ -888,13 +930,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > ctb->head = head; > > /* now update descriptor */ >- WRITE_ONCE(desc->head, head); >+ ct_desc_write(&ctb->desc_map, head, head); > > return available - len; > > corrupted: > CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", >- desc->head, desc->tail, desc->status); >+ ct_desc_read(&ctb->desc_map, head), >+ ct_desc_read(&ctb->desc_map, tail), >+ ct_desc_read(&ctb->desc_map, status)); > ctb->broken = true; > return -EPIPE; > } >@@ -1211,13 +1255,13 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct, > drm_printf(p, "H2G Space: %u\n", > atomic_read(&ct->ctbs.send.space) * 4); > drm_printf(p, "Head: %u\n", >- ct->ctbs.send.desc->head); >+ ct_desc_read(&ct->ctbs.send.desc_map, head)); > drm_printf(p, "Tail: %u\n", >- ct->ctbs.send.desc->tail); >+ ct_desc_read(&ct->ctbs.send.desc_map, tail)); > drm_printf(p, "G2H Space: %u\n", > atomic_read(&ct->ctbs.recv.space) * 4); > drm_printf(p, "Head: %u\n", >- ct->ctbs.recv.desc->head); >+ ct_desc_read(&ct->ctbs.recv.desc_map, head)); > drm_printf(p, "Tail: %u\n", >- ct->ctbs.recv.desc->tail); >+ ct_desc_read(&ct->ctbs.recv.desc_map, tail)); > } >diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h >index f709a19c7e21..867fe13fb47d 100644 >--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h >+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h >@@ -7,6 +7,7 @@ > #define _INTEL_GUC_CT_H_ > > #include <linux/interrupt.h> >+#include <linux/iosys-map.h> > #include <linux/spinlock.h> > #include <linux/workqueue.h> > #include <linux/ktime.h> >@@ -32,8 +33,8 @@ struct drm_printer; > * holds the commands. > * > * @lock: protects access to the commands buffer and buffer descriptor >- * @desc: pointer to the buffer descriptor >- * @cmds: pointer to the commands buffer >+ * @desc: iosys map to the buffer descriptor >+ * @cmds: iosys map to the commands buffer > * @size: size of the commands buffer in dwords > * @resv_space: reserved space in buffer in dwords > * @head: local shadow copy of head in dwords >@@ -43,8 +44,8 @@ struct drm_printer; > */ > struct intel_guc_ct_buffer { > spinlock_t lock; >- struct guc_ct_buffer_desc *desc; >- u32 *cmds; >+ struct iosys_map desc_map; >+ struct iosys_map cmds_map; > u32 size; > u32 resv_space; > u32 tail; >-- >2.33.0 > ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Refactor CT access to use iosys_map (rev2) 2022-03-22 8:44 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map Mullati Siva 2022-03-22 8:44 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva @ 2022-03-22 9:25 ` Patchwork 2022-03-22 9:29 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork ` (2 subsequent siblings) 4 siblings, 0 replies; 7+ messages in thread From: Patchwork @ 2022-03-22 9:25 UTC (permalink / raw) To: Mullati Siva; +Cc: intel-gfx == Series Details == Series: drm/i915/guc: Refactor CT access to use iosys_map (rev2) URL : https://patchwork.freedesktop.org/series/101148/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915/guc: Refactor CT access to use iosys_map (rev2) 2022-03-22 8:44 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map Mullati Siva 2022-03-22 8:44 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva 2022-03-22 9:25 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Refactor CT access to use iosys_map (rev2) Patchwork @ 2022-03-22 9:29 ` Patchwork 2022-03-22 9:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-03-22 17:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 4 siblings, 0 replies; 7+ messages in thread From: Patchwork @ 2022-03-22 9:29 UTC (permalink / raw) To: Mullati Siva; +Cc: intel-gfx == Series Details == Series: drm/i915/guc: Refactor CT access to use iosys_map (rev2) URL : https://patchwork.freedesktop.org/series/101148/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found ./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' not found ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Refactor CT access to use iosys_map (rev2) 2022-03-22 8:44 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map Mullati Siva ` (2 preceding siblings ...) 2022-03-22 9:29 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork @ 2022-03-22 9:58 ` Patchwork 2022-03-22 17:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 4 siblings, 0 replies; 7+ messages in thread From: Patchwork @ 2022-03-22 9:58 UTC (permalink / raw) To: Mullati Siva; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 5752 bytes --] == Series Details == Series: drm/i915/guc: Refactor CT access to use iosys_map (rev2) URL : https://patchwork.freedesktop.org/series/101148/ State : success == Summary == CI Bug Log - changes from CI_DRM_11395 -> Patchwork_22639 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/index.html Participating hosts (49 -> 43) ------------------------------ Additional (2): bat-adlm-1 bat-jsl-2 Missing (8): shard-tglu fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 shard-rkl shard-dg1 fi-bdw-samus Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_22639: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@i915_selftest@live@gt_mocs: - {bat-rpls-2}: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/bat-rpls-2/igt@i915_selftest@live@gt_mocs.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/bat-rpls-2/igt@i915_selftest@live@gt_mocs.html * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic: - {bat-adlm-1}: NOTRUN -> [INCOMPLETE][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/bat-adlm-1/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html Known issues ------------ Here are the changes found in Patchwork_22639 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@amdgpu/amd_cs_nop@fork-compute0: - fi-blb-e6850: NOTRUN -> [SKIP][4] ([fdo#109271]) +17 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/fi-blb-e6850/igt@amdgpu/amd_cs_nop@fork-compute0.html * igt@i915_selftest@live@gt_engines: - bat-dg1-6: [PASS][5] -> [INCOMPLETE][6] ([i915#4418]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/bat-dg1-6/igt@i915_selftest@live@gt_engines.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/bat-dg1-6/igt@i915_selftest@live@gt_engines.html * igt@runner@aborted: - bat-dg1-6: NOTRUN -> [FAIL][7] ([i915#4312] / [i915#5257]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/bat-dg1-6/igt@runner@aborted.html #### Possible fixes #### * igt@i915_selftest@live@gem: - fi-blb-e6850: [DMESG-FAIL][8] ([i915#4528]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/fi-blb-e6850/igt@i915_selftest@live@gem.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/fi-blb-e6850/igt@i915_selftest@live@gem.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391 [i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418 [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785 [i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897 [i915#5195]: https://gitlab.freedesktop.org/drm/intel/issues/5195 [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#5338]: https://gitlab.freedesktop.org/drm/intel/issues/5338 [i915#5339]: https://gitlab.freedesktop.org/drm/intel/issues/5339 [i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341 [i915#5342]: https://gitlab.freedesktop.org/drm/intel/issues/5342 Build changes ------------- * Linux: CI_DRM_11395 -> Patchwork_22639 CI-20190529: 20190529 CI_DRM_11395: a678f97326454b60ffbbde6abf52d23997d71a27 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6387: 04d012b18355b53798af5a55a8915afb1a421bba @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_22639: 6b6d540ea831c79b4cb551faac44c75bee75ae23 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 6b6d540ea831 drm/i915/guc: Convert ct buffer to iosys_map == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/index.html [-- Attachment #2: Type: text/html, Size: 4618 bytes --] ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/guc: Refactor CT access to use iosys_map (rev2) 2022-03-22 8:44 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map Mullati Siva ` (3 preceding siblings ...) 2022-03-22 9:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2022-03-22 17:08 ` Patchwork 4 siblings, 0 replies; 7+ messages in thread From: Patchwork @ 2022-03-22 17:08 UTC (permalink / raw) To: Mullati Siva; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 30280 bytes --] == Series Details == Series: drm/i915/guc: Refactor CT access to use iosys_map (rev2) URL : https://patchwork.freedesktop.org/series/101148/ State : success == Summary == CI Bug Log - changes from CI_DRM_11395_full -> Patchwork_22639_full ==================================================== Summary ------- **SUCCESS** No regressions found. Participating hosts (13 -> 12) ------------------------------ Missing (1): shard-dg1 Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_22639_full: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@i915_pm_rpm@system-suspend-devices: - {shard-rkl}: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-rkl-1/igt@i915_pm_rpm@system-suspend-devices.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-3/igt@i915_pm_rpm@system-suspend-devices.html * igt@kms_color@pipe-c-deep-color: - {shard-rkl}: [SKIP][3] ([i915#4070]) -> [SKIP][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-rkl-2/igt@kms_color@pipe-c-deep-color.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-3/igt@kms_color@pipe-c-deep-color.html * igt@kms_color@pipe-c-legacy-gamma-reset: - {shard-rkl}: [SKIP][5] ([i915#4070]) -> ([SKIP][6], [SKIP][7]) ([i915#1849] / [i915#4098]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-rkl-1/igt@kms_color@pipe-c-legacy-gamma-reset.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-5/igt@kms_color@pipe-c-legacy-gamma-reset.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-3/igt@kms_color@pipe-c-legacy-gamma-reset.html * igt@kms_cursor_crc@pipe-a-cursor-256x256-rapid-movement: - {shard-rkl}: [SKIP][8] ([fdo#112022] / [i915#4070]) -> ([PASS][9], [SKIP][10]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-rkl-1/igt@kms_cursor_crc@pipe-a-cursor-256x256-rapid-movement.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-256x256-rapid-movement.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-3/igt@kms_cursor_crc@pipe-a-cursor-256x256-rapid-movement.html * igt@kms_cursor_crc@pipe-a-cursor-32x32-onscreen: - {shard-rkl}: NOTRUN -> [SKIP][11] +38 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-3/igt@kms_cursor_crc@pipe-a-cursor-32x32-onscreen.html * igt@kms_cursor_crc@pipe-b-cursor-64x21-random: - {shard-rkl}: [SKIP][12] ([fdo#112022]) -> [SKIP][13] +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-rkl-5/igt@kms_cursor_crc@pipe-b-cursor-64x21-random.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-3/igt@kms_cursor_crc@pipe-b-cursor-64x21-random.html * igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque: - {shard-rkl}: [SKIP][14] ([fdo#112022] / [i915#4070]) -> [SKIP][15] +3 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-rkl-2/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-3/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html * igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen: - {shard-rkl}: NOTRUN -> ([SKIP][16], [SKIP][17]) ([fdo#112022] / [i915#4070]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-1/igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-3/igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html * igt@kms_cursor_crc@pipe-c-cursor-512x170-random: - {shard-rkl}: [SKIP][18] ([i915#4070]) -> ([SKIP][19], [SKIP][20]) ([fdo#112022] / [i915#4070]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-rkl-6/igt@kms_cursor_crc@pipe-c-cursor-512x170-random.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-2/igt@kms_cursor_crc@pipe-c-cursor-512x170-random.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-3/igt@kms_cursor_crc@pipe-c-cursor-512x170-random.html * igt@kms_cursor_crc@pipe-c-cursor-max-size-rapid-movement: - {shard-rkl}: [SKIP][21] ([fdo#112022]) -> ([SKIP][22], [SKIP][23]) ([fdo#112022] / [i915#4070]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-rkl-5/igt@kms_cursor_crc@pipe-c-cursor-max-size-rapid-movement.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-3/igt@kms_cursor_crc@pipe-c-cursor-max-size-rapid-movement.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-1/igt@kms_cursor_crc@pipe-c-cursor-max-size-rapid-movement.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt: - {shard-rkl}: [SKIP][24] ([i915#1849]) -> [SKIP][25] +20 similar issues [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt: - {shard-rkl}: [SKIP][26] ([fdo#111825] / [i915#1825]) -> ([SKIP][27], [SKIP][28]) ([i915#1849]) +1 similar issue [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt: - {shard-rkl}: [SKIP][29] ([i915#1849]) -> ([SKIP][30], [SKIP][31]) ([fdo#111825] / [i915#1825]) +3 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff: - {shard-rkl}: ([SKIP][32], [SKIP][33]) ([i915#1849] / [i915#4098]) -> [SKIP][34] [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html * igt@kms_frontbuffer_tracking@fbc-tiling-linear: - {shard-rkl}: [PASS][35] -> ([SKIP][36], [SKIP][37]) ([i915#1849]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-3/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu: - {shard-rkl}: [SKIP][38] ([i915#1849]) -> ([PASS][39], [SKIP][40]) +2 similar issues [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-pgflip-blt: - {shard-rkl}: NOTRUN -> ([SKIP][41], [SKIP][42]) ([i915#1849]) +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-pgflip-blt.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-pgflip-blt.html * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render: - {shard-rkl}: [PASS][43] -> ([SKIP][44], [PASS][45]) +4 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render.html * igt@kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant: - {shard-rkl}: [SKIP][46] ([i915#1849] / [i915#4070] / [i915#4098]) -> [SKIP][47] +2 similar issues [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-rkl-2/igt@kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-3/igt@kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - {shard-rkl}: ([SKIP][48], [SKIP][49]) ([i915#1849] / [i915#4098]) -> ([SKIP][50], [SKIP][51]) ([i915#4070]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-rkl-4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-rkl-5/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-3/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-rkl-1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html Known issues ------------ Here are the changes found in Patchwork_22639_full that come from known issues: ### CI changes ### #### Issues hit #### * boot: - shard-skl: ([PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65]) -> ([PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [PASS][77], [PASS][78], [PASS][79], [FAIL][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88]) ([i915#5032]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-skl8/boot.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-skl9/boot.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-skl9/boot.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-skl9/boot.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-skl8/boot.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-skl7/boot.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-skl7/boot.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-skl4/boot.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-skl4/boot.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-skl1/boot.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-skl1/boot.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-skl10/boot.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-skl10/boot.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-skl10/boot.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl9/boot.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl9/boot.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl8/boot.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl8/boot.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl7/boot.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl7/boot.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl6/boot.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl6/boot.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl5/boot.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl5/boot.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl5/boot.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl4/boot.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl4/boot.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl3/boot.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl3/boot.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl2/boot.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl2/boot.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl1/boot.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl1/boot.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl10/boot.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl10/boot.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl10/boot.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl10/boot.html #### Possible fixes #### * boot: - shard-glk: ([PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [FAIL][109], [PASS][110], [PASS][111], [PASS][112]) ([i915#4392]) -> ([PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127], [PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132], [PASS][133], [PASS][134], [PASS][135], [PASS][136], [PASS][137]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk9/boot.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk9/boot.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk8/boot.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk8/boot.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk8/boot.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk7/boot.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk7/boot.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk6/boot.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk6/boot.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk6/boot.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk5/boot.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk5/boot.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk4/boot.html [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk4/boot.html [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk3/boot.html [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk3/boot.html [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk3/boot.html [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk2/boot.html [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk2/boot.html [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk2/boot.html [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk2/boot.html [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk1/boot.html [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk1/boot.html [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk1/boot.html [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk9/boot.html [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk9/boot.html [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk9/boot.html [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk8/boot.html [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk8/boot.html [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk8/boot.html [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk7/boot.html [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk7/boot.html [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk6/boot.html [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk6/boot.html [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk6/boot.html [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk6/boot.html [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk5/boot.html [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk5/boot.html [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk5/boot.html [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk4/boot.html [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk4/boot.html [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk3/boot.html [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk3/boot.html [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk2/boot.html [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk2/boot.html [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk2/boot.html [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk1/boot.html [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk1/boot.html [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk1/boot.html ### IGT changes ### #### Issues hit #### * igt@gem_create@create-massive: - shard-skl: NOTRUN -> [DMESG-WARN][138] ([i915#4991]) [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl6/igt@gem_create@create-massive.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][139] -> [FAIL][140] ([i915#232]) [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-tglb7/igt@gem_eio@unwedge-stress.html [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-tglb8/igt@gem_eio@unwedge-stress.html * igt@gem_exec_capture@pi@vcs0: - shard-skl: NOTRUN -> [INCOMPLETE][141] ([i915#4547]) [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl10/igt@gem_exec_capture@pi@vcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-kbl: [PASS][142] -> [FAIL][143] ([i915#2842]) +1 similar issue [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-kbl3/igt@gem_exec_fair@basic-none@rcs0.html [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-kbl1/igt@gem_exec_fair@basic-none@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-apl: [PASS][144] -> [FAIL][145] ([i915#2842]) [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-apl1/igt@gem_exec_fair@basic-none@vcs0.html [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-apl7/igt@gem_exec_fair@basic-none@vcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: NOTRUN -> [FAIL][146] ([i915#2842]) +1 similar issue [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk8/igt@gem_exec_fair@basic-throttle@rcs0.html - shard-iclb: [PASS][147] -> [FAIL][148] ([i915#2849]) [147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@gem_huc_copy@huc-copy: - shard-skl: NOTRUN -> [SKIP][149] ([fdo#109271] / [i915#2190]) [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl1/igt@gem_huc_copy@huc-copy.html * igt@gem_lmem_swapping@parallel-multi: - shard-iclb: NOTRUN -> [SKIP][150] ([i915#4613]) [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-iclb5/igt@gem_lmem_swapping@parallel-multi.html * igt@gem_lmem_swapping@parallel-random-engines: - shard-glk: NOTRUN -> [SKIP][151] ([fdo#109271] / [i915#4613]) [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk4/igt@gem_lmem_swapping@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - shard-skl: NOTRUN -> [SKIP][152] ([fdo#109271] / [i915#4613]) +4 similar issues [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl6/igt@gem_lmem_swapping@verify-random.html * igt@gem_pwrite@basic-exhaustion: - shard-skl: NOTRUN -> [WARN][153] ([i915#2658]) [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl10/igt@gem_pwrite@basic-exhaustion.html * igt@gem_userptr_blits@input-checking: - shard-glk: NOTRUN -> [DMESG-WARN][154] ([i915#4991]) [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk8/igt@gem_userptr_blits@input-checking.html * igt@i915_pm_rpm@basic-pci-d3-state: - shard-skl: [PASS][155] -> [FAIL][156] ([i915#5290]) [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-skl1/igt@i915_pm_rpm@basic-pci-d3-state.html [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl10/igt@i915_pm_rpm@basic-pci-d3-state.html * igt@i915_suspend@fence-restore-untiled: - shard-apl: [PASS][157] -> [DMESG-WARN][158] ([i915#180]) +1 similar issue [157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-apl7/igt@i915_suspend@fence-restore-untiled.html [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-apl1/igt@i915_suspend@fence-restore-untiled.html * igt@kms_big_fb@linear-16bpp-rotate-270: - shard-iclb: NOTRUN -> [SKIP][159] ([fdo#110725] / [fdo#111614]) [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-iclb5/igt@kms_big_fb@linear-16bpp-rotate-270.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip: - shard-glk: NOTRUN -> [SKIP][160] ([fdo#109271] / [i915#3777]) [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip: - shard-skl: NOTRUN -> [FAIL][161] ([i915#3743]) +3 similar issues [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl9/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip: - shard-skl: NOTRUN -> [SKIP][162] ([fdo#109271] / [i915#3777]) +5 similar issues [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl6/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc: - shard-skl: NOTRUN -> [SKIP][163] ([fdo#109271] / [i915#3886]) +19 similar issues [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl9/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs: - shard-glk: NOTRUN -> [SKIP][164] ([fdo#109271]) +52 similar issues [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk8/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs.html * igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc: - shard-glk: NOTRUN -> [SKIP][165] ([fdo#109271] / [i915#3886]) +3 similar issues [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk4/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs: - shard-kbl: NOTRUN -> [SKIP][166] ([fdo#109271] / [i915#3886]) [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-kbl1/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs.html * igt@kms_chamelium@dp-hpd-after-suspend: - shard-kbl: NOTRUN -> [SKIP][167] ([fdo#109271] / [fdo#111827]) [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-kbl1/igt@kms_chamelium@dp-hpd-after-suspend.html * igt@kms_chamelium@hdmi-aspect-ratio: - shard-skl: NOTRUN -> [SKIP][168] ([fdo#109271] / [fdo#111827]) +31 similar issues [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl6/igt@kms_chamelium@hdmi-aspect-ratio.html * igt@kms_chamelium@vga-hpd-enable-disable-mode: - shard-glk: NOTRUN -> [SKIP][169] ([fdo#109271] / [fdo#111827]) +4 similar issues [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk4/igt@kms_chamelium@vga-hpd-enable-disable-mode.html * igt@kms_color_chamelium@pipe-a-degamma: - shard-iclb: NOTRUN -> [SKIP][170] ([fdo#109284] / [fdo#111827]) +1 similar issue [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-iclb5/igt@kms_color_chamelium@pipe-a-degamma.html * igt@kms_cursor_crc@pipe-d-cursor-64x64-rapid-movement: - shard-iclb: NOTRUN -> [SKIP][171] ([fdo#109278]) +2 similar issues [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-iclb5/igt@kms_cursor_crc@pipe-d-cursor-64x64-rapid-movement.html * igt@kms_cursor_legacy@cursor-vs-flip-toggle: - shard-iclb: [PASS][172] -> [FAIL][173] ([i915#5072]) [172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-iclb3/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-iclb7/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions: - shard-iclb: NOTRUN -> [SKIP][174] ([fdo#109274] / [fdo#109278]) [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-iclb5/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-glk: [PASS][175] -> [FAIL][176] ([i915#2346]) [175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: NOTRUN -> [INCOMPLETE][177] ([i915#4939]) [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl10/igt@kms_fbcon_fbt@psr-suspend.html * igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2: - shard-glk: [PASS][178] -> [FAIL][179] ([i915#2122]) [178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-glk1/igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2.html [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-glk6/igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2.html * igt@kms_flip@flip-vs-expired-vblank@b-edp1: - shard-skl: [PASS][180] -> [FAIL][181] ([i915#79]) [180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl8/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html * igt@kms_flip@plain-flip-fb-recreate@c-edp1: - shard-skl: NOTRUN -> [FAIL][182] ([i915#2122]) [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl9/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html * igt@kms_flip@plain-flip-ts-check@c-edp1: - shard-skl: [PASS][183] -> [FAIL][184] ([i915#2122]) +1 similar issue [183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11395/shard-skl9/igt@kms_flip@plain-flip-ts-check@c-edp1.html [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/shard-skl2/igt@kms_flip@plain-flip-ts-check@c-edp1.html * igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt: - shard-skl: NOTRUN -> [SKIP][185] ([fdo#109271]) +405 similar issues [185]: ht == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22639/index.html [-- Attachment #2: Type: text/html, Size: 32635 bytes --] ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-04-02 4:13 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-03-22 8:44 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map Mullati Siva 2022-03-22 8:44 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva 2022-04-02 4:13 ` Lucas De Marchi 2022-03-22 9:25 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Refactor CT access to use iosys_map (rev2) Patchwork 2022-03-22 9:29 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork 2022-03-22 9:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-03-22 17:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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