From: ~eopxd <eopxd@git.sr.ht> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: WeiWei Li <liweiwei@iscas.ac.cn>, Frank Chang <frank.chang@sifive.com>, eop Chen <eop.chen@sifive.com>, Bin Meng <bin.meng@windriver.com>, Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com> Subject: [PATCH qemu v5 00/14] Add tail agnostic behavior for rvv instructions Date: Mon, 28 Mar 2022 07:20:42 +0000 [thread overview] Message-ID: <164845204233.25323.14607469451359734000-0@git.sr.ht> (raw) According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s". An option 'rvv_ta_all_1s' is added to enable the behavior, it is default as disabled. There are multiple possibility for agnostic elements according to v-spec. The main intent of this patch-set tries to add option that can distinguish between tail policies. Setting agnostic elements to all 1s makes things simple and allow QEMU to express this. We may explore other possibility of agnostic behavior by adding other options in the future. Please understand that this patch-set is limited. v2 updates: - Addressed comments from Weiwei Li - Added commit tail agnostic on load / store instructions (which I forgot to include into the patch-set) v3 updates: - Missed the very 1st commit, adding it back v4 updates: - Renamed vlmax to total_elems - Deal with tail element when vl_eq_vlmax == true v5 updates: - Let `vext_get_total_elems` take `desc` and `esz` - Utilize `simd_maxsz(desc)` to get `vlenb` - Fix alignments to code eopXD (14): target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed target/riscv: rvv: Rename ambiguous esz target/riscv: rvv: Early exit when vstart >= vl target/riscv: rvv: Add tail agnostic for vv instructions target/riscv: rvv: Add tail agnostic for vector load / store instructions target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions target/riscv: rvv: Add tail agnostic for vector integer shift instructions target/riscv: rvv: Add tail agnostic for vector integer comparison instructions target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions target/riscv: rvv: Add tail agnostic for vector floating-point instructions target/riscv: rvv: Add tail agnostic for vector reduction instructions target/riscv: rvv: Add tail agnostic for vector mask instructions target/riscv: rvv: Add tail agnostic for vector permutation instructions target/riscv/cpu.c | 1 + target/riscv/cpu.h | 2 + target/riscv/cpu_helper.c | 2 + target/riscv/insn_trans/trans_rvv.c.inc | 164 +++ target/riscv/internals.h | 5 +- target/riscv/translate.c | 2 + target/riscv/vector_helper.c | 1566 ++++++++++++++--------- 7 files changed, 1125 insertions(+), 617 deletions(-) -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: ~eopxd <eopxd@git.sr.ht> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Frank Chang <frank.chang@sifive.com>, WeiWei Li <liweiwei@iscas.ac.cn>, eop Chen <eop.chen@sifive.com> Subject: [PATCH qemu v5 00/14] Add tail agnostic behavior for rvv instructions Date: Mon, 28 Mar 2022 07:20:42 +0000 [thread overview] Message-ID: <164845204233.25323.14607469451359734000-0@git.sr.ht> (raw) According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s". An option 'rvv_ta_all_1s' is added to enable the behavior, it is default as disabled. There are multiple possibility for agnostic elements according to v-spec. The main intent of this patch-set tries to add option that can distinguish between tail policies. Setting agnostic elements to all 1s makes things simple and allow QEMU to express this. We may explore other possibility of agnostic behavior by adding other options in the future. Please understand that this patch-set is limited. v2 updates: - Addressed comments from Weiwei Li - Added commit tail agnostic on load / store instructions (which I forgot to include into the patch-set) v3 updates: - Missed the very 1st commit, adding it back v4 updates: - Renamed vlmax to total_elems - Deal with tail element when vl_eq_vlmax == true v5 updates: - Let `vext_get_total_elems` take `desc` and `esz` - Utilize `simd_maxsz(desc)` to get `vlenb` - Fix alignments to code eopXD (14): target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed target/riscv: rvv: Rename ambiguous esz target/riscv: rvv: Early exit when vstart >= vl target/riscv: rvv: Add tail agnostic for vv instructions target/riscv: rvv: Add tail agnostic for vector load / store instructions target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions target/riscv: rvv: Add tail agnostic for vector integer shift instructions target/riscv: rvv: Add tail agnostic for vector integer comparison instructions target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions target/riscv: rvv: Add tail agnostic for vector floating-point instructions target/riscv: rvv: Add tail agnostic for vector reduction instructions target/riscv: rvv: Add tail agnostic for vector mask instructions target/riscv: rvv: Add tail agnostic for vector permutation instructions target/riscv/cpu.c | 1 + target/riscv/cpu.h | 2 + target/riscv/cpu_helper.c | 2 + target/riscv/insn_trans/trans_rvv.c.inc | 164 +++ target/riscv/internals.h | 5 +- target/riscv/translate.c | 2 + target/riscv/vector_helper.c | 1566 ++++++++++++++--------- 7 files changed, 1125 insertions(+), 617 deletions(-) -- 2.34.1
next reply other threads:[~2022-03-28 7:23 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-03-28 7:20 ~eopxd [this message] 2022-03-28 7:20 ` [PATCH qemu v5 00/14] Add tail agnostic behavior for rvv instructions ~eopxd 2022-03-01 9:07 ` [PATCH qemu v5 04/14] target/riscv: rvv: Add tail agnostic for vv instructions ~eopxd 2022-03-28 7:20 ` ~eopxd 2022-03-28 11:23 ` Weiwei Li 2022-03-28 11:23 ` Weiwei Li 2022-03-07 7:10 ` [PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions ~eopxd 2022-03-28 7:20 ` ~eopxd 2022-03-28 11:56 ` Weiwei Li 2022-03-28 11:56 ` Weiwei Li 2022-03-30 7:42 ` 陳約廷 2022-03-30 8:27 ` Weiwei Li 2022-03-30 10:02 ` eop Chen 2022-03-30 15:13 ` Weiwei Li 2022-03-07 7:32 ` [PATCH qemu v5 06/14] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions ~eopxd 2022-03-28 7:20 ` ~eopxd 2022-03-07 9:38 ` [PATCH qemu v5 07/14] target/riscv: rvv: Add tail agnostic for vector integer shift instructions ~eopxd 2022-03-28 7:20 ` ~eopxd 2022-03-07 9:43 ` [PATCH qemu v5 08/14] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions ~eopxd 2022-03-28 7:20 ` ~eopxd 2022-03-07 9:53 ` [PATCH qemu v5 09/14] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions ~eopxd 2022-03-28 7:21 ` ~eopxd 2022-03-07 10:04 ` [PATCH qemu v5 10/14] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions ~eopxd 2022-03-28 7:20 ` ~eopxd 2022-03-07 10:05 ` [PATCH qemu v5 11/14] target/riscv: rvv: Add tail agnostic for vector floating-point instructions ~eopxd 2022-03-28 7:21 ` ~eopxd 2022-03-07 12:21 ` [PATCH qemu v5 12/14] target/riscv: rvv: Add tail agnostic for vector reduction instructions ~eopxd 2022-03-28 7:21 ` ~eopxd 2022-03-07 15:26 ` [PATCH qemu v5 13/14] target/riscv: rvv: Add tail agnostic for vector mask instructions ~eopxd 2022-03-28 7:21 ` ~eopxd 2022-03-07 15:59 ` [PATCH qemu v5 14/14] target/riscv: rvv: Add tail agnostic for vector permutation instructions ~eopxd 2022-03-28 7:21 ` ~eopxd 2022-03-09 8:34 ` [PATCH qemu v5 02/14] target/riscv: rvv: Rename ambiguous esz ~eopxd 2022-03-28 7:20 ` ~eopxd 2022-03-12 6:28 ` [PATCH qemu v5 03/14] target/riscv: rvv: Early exit when vstart >= vl ~eopxd 2022-03-28 7:20 ` ~eopxd 2022-03-14 7:38 ` [PATCH qemu v5 01/14] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed ~eopxd 2022-03-14 7:38 ` ~eopxd
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