* [Intel-gfx] [PATCH 0/6] Enable WAs related to DG2
@ 2022-04-15 22:40 Umesh Nerlige Ramappa
2022-04-15 22:40 ` [Intel-gfx] [PATCH 1/6] drm/i915: Add Wa_22011802037 force cs halt Umesh Nerlige Ramappa
` (9 more replies)
0 siblings, 10 replies; 13+ messages in thread
From: Umesh Nerlige Ramappa @ 2022-04-15 22:40 UTC (permalink / raw)
To: intel-gfx, daniele.ceraolospurio, john.c.harrison
Enable work arounds related to DG2.
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Tilak Tangudu <tilak.tangudu@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
John Harrison (2):
drm/i915/guc: Enable GuC based workarounds for DG2
drm/i915/dg2: Enable Wa_22012727170/Wa_22012727685
Matthew Brost (1):
drm/i915/dg2: Enable Wa_14014475959 - RCS / CCS context exit
Tilak Tangudu (1):
drm/i915: Add Wa_22011802037 force cs halt
Umesh Nerlige Ramappa (1):
drm/i915/guc: Enable Wa_22011802037 for gen12 GuC based platforms
Vinay Belgaumkar (1):
drm/i915/guc: Apply Wa_16011777198
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 41 +++++++++
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 ++
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 8 ++
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 7 ++
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 9 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 18 ++++
drivers/gpu/drm/i915/gt/intel_reset.c | 5 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 35 ++++++++
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 8 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 89 ++++++++++++++++++-
11 files changed, 222 insertions(+), 8 deletions(-)
--
2.35.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 1/6] drm/i915: Add Wa_22011802037 force cs halt
2022-04-15 22:40 [Intel-gfx] [PATCH 0/6] Enable WAs related to DG2 Umesh Nerlige Ramappa
@ 2022-04-15 22:40 ` Umesh Nerlige Ramappa
2022-04-15 22:40 ` [Intel-gfx] [PATCH 2/6] drm/i915/guc: Enable Wa_22011802037 for gen12 GuC based platforms Umesh Nerlige Ramappa
` (8 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Umesh Nerlige Ramappa @ 2022-04-15 22:40 UTC (permalink / raw)
To: intel-gfx, daniele.ceraolospurio, john.c.harrison
From: Tilak Tangudu <tilak.tangudu@intel.com>
Prior to doing a reset, SW must ensure command streamer is stopped,
as a workaround, to eliminate a race condition in GPM flow.
Setting both the ring stop and prefetch disable bits, will cause the
command streamer to halt.
Signed-off-by: Tilak Tangudu <tilak.tangudu@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 +++++++++
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 98b61ff13c95..14c6ddbbfde8 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1280,6 +1280,15 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
int err;
intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
+
+ /*
+ * Wa_22011802037 : gen12, Prior to doing a reset, ensure CS is
+ * stopped, set ring stop bit and prefetch disable bit to halt CS
+ */
+ if (GRAPHICS_VER(engine->i915) == 12)
+ intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
+ _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
+
err = __intel_wait_for_register_fw(engine->uncore, mode,
MODE_IDLE, MODE_IDLE,
fast_timeout_us,
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
index 0bf8b45c9319..594a629cb28f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -181,6 +181,7 @@
#define GFX_SURFACE_FAULT_ENABLE (1 << 12)
#define GFX_REPLAY_MODE (1 << 11)
#define GFX_PSMI_GRANULARITY (1 << 10)
+#define GEN12_GFX_PREFETCH_DISABLE REG_BIT(10)
#define GFX_PPGTT_ENABLE (1 << 9)
#define GEN8_GFX_PPGTT_48B (1 << 7)
#define GFX_FORWARD_VBLANK_MASK (3 << 5)
--
2.35.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 2/6] drm/i915/guc: Enable Wa_22011802037 for gen12 GuC based platforms
2022-04-15 22:40 [Intel-gfx] [PATCH 0/6] Enable WAs related to DG2 Umesh Nerlige Ramappa
2022-04-15 22:40 ` [Intel-gfx] [PATCH 1/6] drm/i915: Add Wa_22011802037 force cs halt Umesh Nerlige Ramappa
@ 2022-04-15 22:40 ` Umesh Nerlige Ramappa
2022-04-19 0:57 ` Ceraolo Spurio, Daniele
2022-04-15 22:40 ` [Intel-gfx] [PATCH 3/6] drm/i915/guc: Enable GuC based workarounds for DG2 Umesh Nerlige Ramappa
` (7 subsequent siblings)
9 siblings, 1 reply; 13+ messages in thread
From: Umesh Nerlige Ramappa @ 2022-04-15 22:40 UTC (permalink / raw)
To: intel-gfx, daniele.ceraolospurio, john.c.harrison
Initiating a reset when the command streamer is not idle or in the
middle of executing an MI_FORCE_WAKE can result in a hang. Multiple
command streamers can be part of a single reset domain, so resetting one
would mean resetting all command streamers in that domain.
To workaround this, before initiating a reset, ensure that all command
streamers within that reset domain are either IDLE or are not executing
a MI_FORCE_WAKE.
Enable GuC PRE_PARSER WA bit so that GuC follows the WA sequence when
initiating engine-resets.
For gt-resets, ensure that i915 applies the WA sequence.
Opens to address in future patches:
- The part of the WA to wait for pending forcewakes is also applicable
to execlists backend.
- The WA also needs to be applied for gen11
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 9 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 18 ++++
drivers/gpu/drm/i915/gt/intel_reset.c | 5 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 +
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 3 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 85 ++++++++++++++++++-
6 files changed, 116 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index eeead40485fb..f553e2173bda 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -182,15 +182,16 @@ static void gt_sanitize(struct intel_gt *gt, bool force)
if (intel_gt_is_wedged(gt))
intel_gt_unset_wedged(gt);
- for_each_engine(engine, gt, id)
+ /* For GuC mode, ensure submission is disabled before stopping ring */
+ intel_uc_reset_prepare(>->uc);
+
+ for_each_engine(engine, gt, id) {
if (engine->reset.prepare)
engine->reset.prepare(engine);
- intel_uc_reset_prepare(>->uc);
-
- for_each_engine(engine, gt, id)
if (engine->sanitize)
engine->sanitize(engine);
+ }
if (reset_engines(gt) || force) {
for_each_engine(engine, gt, id)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 0a5c2648aaf0..12d892851684 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -841,6 +841,24 @@
#define CTC_SHIFT_PARAMETER_SHIFT 1
#define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
+/* GPM MSG_IDLE */
+#define MSG_IDLE_CS _MMIO(0x8000)
+#define MSG_IDLE_VCS0 _MMIO(0x8004)
+#define MSG_IDLE_VCS1 _MMIO(0x8008)
+#define MSG_IDLE_BCS _MMIO(0x800C)
+#define MSG_IDLE_VECS0 _MMIO(0x8010)
+#define MSG_IDLE_VCS2 _MMIO(0x80C0)
+#define MSG_IDLE_VCS3 _MMIO(0x80C4)
+#define MSG_IDLE_VCS4 _MMIO(0x80C8)
+#define MSG_IDLE_VCS5 _MMIO(0x80CC)
+#define MSG_IDLE_VCS6 _MMIO(0x80D0)
+#define MSG_IDLE_VCS7 _MMIO(0x80D4)
+#define MSG_IDLE_VECS1 _MMIO(0x80D8)
+#define MSG_IDLE_VECS2 _MMIO(0x80DC)
+#define MSG_IDLE_VECS3 _MMIO(0x80E0)
+#define MSG_IDLE_FW_MASK REG_GENMASK(13, 9)
+#define MSG_IDLE_FW_SHIFT 9
+
#define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
#define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index f52015e79fdf..5422a3b84bd4 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -772,14 +772,15 @@ static intel_engine_mask_t reset_prepare(struct intel_gt *gt)
intel_engine_mask_t awake = 0;
enum intel_engine_id id;
+ /* For GuC mode, ensure submission is disabled before stopping ring */
+ intel_uc_reset_prepare(>->uc);
+
for_each_engine(engine, gt, id) {
if (intel_engine_pm_get_if_awake(engine))
awake |= engine->mask;
reset_prepare_engine(engine);
}
- intel_uc_reset_prepare(>->uc);
-
return awake;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index cda7e4bb8bac..185fb4d59791 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -292,6 +292,10 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 50))
flags |= GUC_WA_POLLCS;
+ /* Wa_22011802037: graphics version 12 */
+ if (GRAPHICS_VER(gt->i915) == 12)
+ flags |= GUC_WA_PRE_PARSER;
+
return flags;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index c154b5efccde..b136d6528fbf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -98,7 +98,8 @@
#define GUC_LOG_BUF_ADDR_SHIFT 12
#define GUC_CTL_WA 1
-#define GUC_WA_POLLCS BIT(18)
+#define GUC_WA_PRE_PARSER BIT(14)
+#define GUC_WA_POLLCS BIT(18)
#define GUC_CTL_FEATURE 2
#define GUC_CTL_ENABLE_SLPC BIT(2)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index ee45fdb67f32..172819cd1a0a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1540,6 +1540,89 @@ static void guc_reset_state(struct intel_context *ce, u32 head, bool scrub)
lrc_update_regs(ce, engine, head);
}
+static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
+{
+ static const i915_reg_t _reg[I915_NUM_ENGINES] = {
+ [RCS0] = MSG_IDLE_CS,
+ [BCS0] = MSG_IDLE_BCS,
+ [VCS0] = MSG_IDLE_VCS0,
+ [VCS1] = MSG_IDLE_VCS1,
+ [VCS2] = MSG_IDLE_VCS2,
+ [VCS3] = MSG_IDLE_VCS3,
+ [VCS4] = MSG_IDLE_VCS4,
+ [VCS5] = MSG_IDLE_VCS5,
+ [VCS6] = MSG_IDLE_VCS6,
+ [VCS7] = MSG_IDLE_VCS7,
+ [VECS0] = MSG_IDLE_VECS0,
+ [VECS1] = MSG_IDLE_VECS1,
+ [VECS2] = MSG_IDLE_VECS2,
+ [VECS3] = MSG_IDLE_VECS3,
+ [CCS0] = MSG_IDLE_CS,
+ [CCS1] = MSG_IDLE_CS,
+ [CCS2] = MSG_IDLE_CS,
+ [CCS3] = MSG_IDLE_CS,
+ };
+ u32 val;
+
+ if (!_reg[engine->id].reg)
+ return 0;
+
+ val = intel_uncore_read(engine->uncore, _reg[engine->id]);
+
+ /* bits[29:25] & bits[13:9] >> shift */
+ return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT;
+}
+
+static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)
+{
+ int ret;
+
+ /* Ensure GPM receives fw up/down after CS is stopped */
+ udelay(1);
+
+ /* Wait for forcewake request to complete in GPM */
+ ret = __intel_wait_for_register_fw(gt->uncore,
+ GEN9_PWRGT_DOMAIN_STATUS,
+ fw_mask, fw_mask, 5000, 0, NULL);
+
+ /* Ensure CS receives fw ack from GPM */
+ udelay(1);
+
+ if (ret)
+ GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret);
+}
+
+/*
+ * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any
+ * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The
+ * pending status is indicated by bits[13:9] (masked by bits[ 29:25]) in the
+ * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we
+ * are concerned only with the gt reset here, we use a logical OR of pending
+ * forcewakeups from all reset domains and then wait for them to complete by
+ * querying PWRGT_DOMAIN_STATUS.
+ */
+static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
+{
+ u32 fw_pending;
+
+ if (GRAPHICS_VER(engine->i915) != 12)
+ return;
+
+ /*
+ * Wa_22011802037
+ * TODO: Occassionally trying to stop the cs times out, but does not
+ * adversely affect functionality. The timeout is set as a config
+ * parameter that defaults to 100ms. Assuming that this timeout is
+ * sufficient for any pending MI_FORCEWAKEs to complete, ignore the
+ * timeout returned here until it is root caused.
+ */
+ intel_engine_stop_cs(engine);
+
+ fw_pending = __cs_pending_mi_force_wakes(engine);
+ if (fw_pending)
+ __gpm_wait_for_fw_complete(engine->gt, fw_pending);
+}
+
static void guc_reset_nop(struct intel_engine_cs *engine)
{
}
@@ -3795,7 +3878,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
engine->sched_engine->schedule = i915_schedule;
- engine->reset.prepare = guc_reset_nop;
+ engine->reset.prepare = guc_engine_reset_prepare;
engine->reset.rewind = guc_rewind_nop;
engine->reset.cancel = guc_reset_nop;
engine->reset.finish = guc_reset_nop;
--
2.35.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 3/6] drm/i915/guc: Enable GuC based workarounds for DG2
2022-04-15 22:40 [Intel-gfx] [PATCH 0/6] Enable WAs related to DG2 Umesh Nerlige Ramappa
2022-04-15 22:40 ` [Intel-gfx] [PATCH 1/6] drm/i915: Add Wa_22011802037 force cs halt Umesh Nerlige Ramappa
2022-04-15 22:40 ` [Intel-gfx] [PATCH 2/6] drm/i915/guc: Enable Wa_22011802037 for gen12 GuC based platforms Umesh Nerlige Ramappa
@ 2022-04-15 22:40 ` Umesh Nerlige Ramappa
2022-04-18 22:37 ` Ceraolo Spurio, Daniele
2022-04-15 22:40 ` [Intel-gfx] [PATCH 4/6] drm/i915/guc: Apply Wa_16011777198 Umesh Nerlige Ramappa
` (6 subsequent siblings)
9 siblings, 1 reply; 13+ messages in thread
From: Umesh Nerlige Ramappa @ 2022-04-15 22:40 UTC (permalink / raw)
To: intel-gfx, daniele.ceraolospurio, john.c.harrison
From: John Harrison <John.C.Harrison@Intel.com>
There are some workarounds for DG2 that are implemented in the GuC
firmware. However, the KMD is required to enable these by setting the
appropriate flag as GuC does not know what platform it is running on.
Wa_16011759253
Wa_14012630569
Wa_14013746162
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
CC: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 14 ++++++++++++++
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 2 ++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 185fb4d59791..fd04c4cd9d44 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -292,6 +292,20 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 50))
flags |= GUC_WA_POLLCS;
+ /* Wa_16011759253:dg2_g10:a0 */
+ if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0))
+ flags |= GUC_WA_GAM_CREDITS;
+
+ /*
+ * Wa_14012197797:dg2_g10:a0,dg2_g11:a0
+ * Wa_22011391025:dg2_g10,dg2_g11,dg2_g12
+ *
+ * The same WA bit is used for both and 22011391025 is applicable to
+ * all DG2.
+ */
+ if (IS_DG2(gt->i915))
+ flags |= GUC_WA_DUAL_QUEUE;
+
/* Wa_22011802037: graphics version 12 */
if (GRAPHICS_VER(gt->i915) == 12)
flags |= GUC_WA_PRE_PARSER;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index b136d6528fbf..fe5751f67b19 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -98,6 +98,8 @@
#define GUC_LOG_BUF_ADDR_SHIFT 12
#define GUC_CTL_WA 1
+#define GUC_WA_GAM_CREDITS BIT(10)
+#define GUC_WA_DUAL_QUEUE BIT(11)
#define GUC_WA_PRE_PARSER BIT(14)
#define GUC_WA_POLLCS BIT(18)
--
2.35.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 4/6] drm/i915/guc: Apply Wa_16011777198
2022-04-15 22:40 [Intel-gfx] [PATCH 0/6] Enable WAs related to DG2 Umesh Nerlige Ramappa
` (2 preceding siblings ...)
2022-04-15 22:40 ` [Intel-gfx] [PATCH 3/6] drm/i915/guc: Enable GuC based workarounds for DG2 Umesh Nerlige Ramappa
@ 2022-04-15 22:40 ` Umesh Nerlige Ramappa
2022-04-15 22:40 ` [Intel-gfx] [PATCH 5/6] drm/i915/dg2: Enable Wa_14014475959 - RCS / CCS context exit Umesh Nerlige Ramappa
` (5 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Umesh Nerlige Ramappa @ 2022-04-15 22:40 UTC (permalink / raw)
To: intel-gfx, daniele.ceraolospurio, john.c.harrison
From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Enable GuC Wa to reset RCS/CCS before it goes into RC6.
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 5 +++++
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index fd04c4cd9d44..830889349756 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -310,6 +310,11 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
if (GRAPHICS_VER(gt->i915) == 12)
flags |= GUC_WA_PRE_PARSER;
+ /* Wa_16011777198:dg2 */
+ if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
+ IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))
+ flags |= GUC_WA_RCS_RESET_BEFORE_RC6;
+
return flags;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index fe5751f67b19..126e67ea1619 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -100,6 +100,7 @@
#define GUC_CTL_WA 1
#define GUC_WA_GAM_CREDITS BIT(10)
#define GUC_WA_DUAL_QUEUE BIT(11)
+#define GUC_WA_RCS_RESET_BEFORE_RC6 BIT(13)
#define GUC_WA_PRE_PARSER BIT(14)
#define GUC_WA_POLLCS BIT(18)
--
2.35.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 5/6] drm/i915/dg2: Enable Wa_14014475959 - RCS / CCS context exit
2022-04-15 22:40 [Intel-gfx] [PATCH 0/6] Enable WAs related to DG2 Umesh Nerlige Ramappa
` (3 preceding siblings ...)
2022-04-15 22:40 ` [Intel-gfx] [PATCH 4/6] drm/i915/guc: Apply Wa_16011777198 Umesh Nerlige Ramappa
@ 2022-04-15 22:40 ` Umesh Nerlige Ramappa
2022-04-15 22:40 ` [Intel-gfx] [PATCH 6/6] drm/i915/dg2: Enable Wa_22012727170/Wa_22012727685 Umesh Nerlige Ramappa
` (4 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Umesh Nerlige Ramappa @ 2022-04-15 22:40 UTC (permalink / raw)
To: intel-gfx, daniele.ceraolospurio, john.c.harrison
From: Matthew Brost <matthew.brost@intel.com>
There is bug in DG2 where if the CCS contexts switches out while the RCS
is running it can cause memory corruption. To workaround this add an
atomic to a memory address with a value 1 and semaphore wait to the same
address for a value of 0. The GuC firmware is responsible for writing 0
to the memory address when it is safe for the context to switch out.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 41 +++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 8 ++++
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 7 ++++
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 ++
6 files changed, 65 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 047b5a710149..9529c5455bc3 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -583,6 +583,43 @@ static u32 *gen12_emit_preempt_busywait(struct i915_request *rq, u32 *cs)
return cs;
}
+/* Wa_14014475959:dg2 */
+#define CCS_SEMAPHORE_PPHWSP_OFFSET 0x540
+static u32 ccs_semaphore_offset(struct i915_request *rq)
+{
+ return i915_ggtt_offset(rq->context->state) +
+ (LRC_PPHWSP_PN * PAGE_SIZE) + CCS_SEMAPHORE_PPHWSP_OFFSET;
+}
+
+/* Wa_14014475959:dg2 */
+static u32 *ccs_emit_wa_busywait(struct i915_request *rq, u32 *cs)
+{
+ int i;
+
+ *cs++ = MI_ATOMIC_INLINE | MI_ATOMIC_GLOBAL_GTT | MI_ATOMIC_CS_STALL |
+ MI_ATOMIC_MOVE;
+ *cs++ = ccs_semaphore_offset(rq);
+ *cs++ = 0;
+ *cs++ = 1;
+
+ /*
+ * When MI_ATOMIC_INLINE_DATA set this command must be 11 DW + (1 NOP)
+ * to align. 4 DWs above + 8 filler DWs here.
+ */
+ for (i = 0; i < 8; ++i)
+ *cs++ = 0;
+
+ *cs++ = MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_GLOBAL_GTT |
+ MI_SEMAPHORE_POLL |
+ MI_SEMAPHORE_SAD_EQ_SDD;
+ *cs++ = 0;
+ *cs++ = ccs_semaphore_offset(rq);
+ *cs++ = 0;
+
+ return cs;
+}
+
static __always_inline u32*
gen12_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs)
{
@@ -593,6 +630,10 @@ gen12_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs)
!intel_uc_uses_guc_submission(&rq->engine->gt->uc))
cs = gen12_emit_preempt_busywait(rq, cs);
+ /* Wa_14014475959:dg2 */
+ if (intel_engine_uses_wa_hold_ccs_switchout(rq->engine))
+ cs = ccs_emit_wa_busywait(rq, cs);
+
rq->tail = intel_ring_offset(rq, cs);
assert_ring_tail_valid(rq->ring, rq->tail);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index eac20112709c..298f2cc7a879 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -529,6 +529,7 @@ struct intel_engine_cs {
#define I915_ENGINE_HAS_RCS_REG_STATE BIT(9)
#define I915_ENGINE_HAS_EU_PRIORITY BIT(10)
#define I915_ENGINE_FIRST_RENDER_COMPUTE BIT(11)
+#define I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT BIT(12)
unsigned int flags;
/*
@@ -629,6 +630,13 @@ intel_engine_has_relative_mmio(const struct intel_engine_cs * const engine)
return engine->flags & I915_ENGINE_HAS_RELATIVE_MMIO;
}
+/* Wa_14014475959:dg2 */
+static inline bool
+intel_engine_uses_wa_hold_ccs_switchout(struct intel_engine_cs *engine)
+{
+ return engine->flags & I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
+}
+
#define instdone_has_slice(dev_priv___, sseu___, slice___) \
((GRAPHICS_VER(dev_priv___) == 7 ? 1 : ((sseu___)->slice_mask)) & BIT(slice___))
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 724ab069ddb6..e52718a87f14 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -134,6 +134,13 @@
#define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */
#define MI_USE_GGTT (1 << 22) /* g4x+ */
#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
+#define MI_ATOMIC MI_INSTR(0x2f, 1)
+#define MI_ATOMIC_INLINE (MI_INSTR(0x2f, 9) | MI_ATOMIC_INLINE_DATA)
+#define MI_ATOMIC_GLOBAL_GTT (1 << 22)
+#define MI_ATOMIC_INLINE_DATA (1 << 18)
+#define MI_ATOMIC_CS_STALL (1 << 17)
+#define MI_ATOMIC_MOVE (0x4 << 8)
+
/*
* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
* - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 830889349756..228070e31ef0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -296,6 +296,10 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0))
flags |= GUC_WA_GAM_CREDITS;
+ /* Wa_14014475959:dg2 */
+ if (IS_DG2(gt->i915))
+ flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
+
/*
* Wa_14012197797:dg2_g10:a0,dg2_g11:a0
* Wa_22011391025:dg2_g10,dg2_g11,dg2_g12
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 126e67ea1619..e389a3a041a2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -102,6 +102,7 @@
#define GUC_WA_DUAL_QUEUE BIT(11)
#define GUC_WA_RCS_RESET_BEFORE_RC6 BIT(13)
#define GUC_WA_PRE_PARSER BIT(14)
+#define GUC_WA_HOLD_CCS_SWITCHOUT BIT(17)
#define GUC_WA_POLLCS BIT(18)
#define GUC_CTL_FEATURE 2
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 172819cd1a0a..75491f5f450a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -3897,6 +3897,10 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
engine->flags |= I915_ENGINE_HAS_PREEMPTION;
engine->flags |= I915_ENGINE_HAS_TIMESLICES;
+ /* Wa_14014475959:dg2 */
+ if (IS_DG2(engine->i915) && engine->class == COMPUTE_CLASS)
+ engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
+
/*
* TODO: GuC supports timeslicing and semaphores as well, but they're
* handled by the firmware so some minor tweaks are required before
--
2.35.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] [PATCH 6/6] drm/i915/dg2: Enable Wa_22012727170/Wa_22012727685
2022-04-15 22:40 [Intel-gfx] [PATCH 0/6] Enable WAs related to DG2 Umesh Nerlige Ramappa
` (4 preceding siblings ...)
2022-04-15 22:40 ` [Intel-gfx] [PATCH 5/6] drm/i915/dg2: Enable Wa_14014475959 - RCS / CCS context exit Umesh Nerlige Ramappa
@ 2022-04-15 22:40 ` Umesh Nerlige Ramappa
2022-04-15 23:55 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable WAs related to DG2 Patchwork
` (3 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Umesh Nerlige Ramappa @ 2022-04-15 22:40 UTC (permalink / raw)
To: intel-gfx, daniele.ceraolospurio, john.c.harrison
From: John Harrison <John.C.Harrison@Intel.com>
The above two workaronuds regarding context isolation are implemented
by GuC. The KMD just needs to enable them.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 8 ++++++++
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 228070e31ef0..2c4ad4a65089 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -319,6 +319,14 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))
flags |= GUC_WA_RCS_RESET_BEFORE_RC6;
+ /*
+ * Wa_22012727170:dg2_g10[a0-c0), dg2_g11[a0..)
+ * Wa_22012727685:dg2_g11[a0..)
+ */
+ if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
+ IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_FOREVER))
+ flags |= GUC_WA_CONTEXT_ISOLATION;
+
return flags;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index e389a3a041a2..42cb7a9a6199 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -101,6 +101,7 @@
#define GUC_WA_GAM_CREDITS BIT(10)
#define GUC_WA_DUAL_QUEUE BIT(11)
#define GUC_WA_RCS_RESET_BEFORE_RC6 BIT(13)
+#define GUC_WA_CONTEXT_ISOLATION BIT(15)
#define GUC_WA_PRE_PARSER BIT(14)
#define GUC_WA_HOLD_CCS_SWITCHOUT BIT(17)
#define GUC_WA_POLLCS BIT(18)
--
2.35.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable WAs related to DG2
2022-04-15 22:40 [Intel-gfx] [PATCH 0/6] Enable WAs related to DG2 Umesh Nerlige Ramappa
` (5 preceding siblings ...)
2022-04-15 22:40 ` [Intel-gfx] [PATCH 6/6] drm/i915/dg2: Enable Wa_22012727170/Wa_22012727685 Umesh Nerlige Ramappa
@ 2022-04-15 23:55 ` Patchwork
2022-04-15 23:56 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2022-04-15 23:55 UTC (permalink / raw)
To: Umesh Nerlige Ramappa; +Cc: intel-gfx
== Series Details ==
Series: Enable WAs related to DG2
URL : https://patchwork.freedesktop.org/series/102745/
State : warning
== Summary ==
Error: dim checkpatch failed
a2294a0f7061 drm/i915: Add Wa_22011802037 force cs halt
aa0a5cf41d1b drm/i915/guc: Enable Wa_22011802037 for gen12 GuC based platforms
-:211: WARNING:TYPO_SPELLING: 'Occassionally' may be misspelled - perhaps 'Occasionally'?
#211: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1613:
+ * TODO: Occassionally trying to stop the cs times out, but does not
^^^^^^^^^^^^^
total: 0 errors, 1 warnings, 0 checks, 177 lines checked
3ce8deac12b9 drm/i915/guc: Enable GuC based workarounds for DG2
d186afb68580 drm/i915/guc: Apply Wa_16011777198
bd3b93449d59 drm/i915/dg2: Enable Wa_14014475959 - RCS / CCS context exit
0ff3947e3b70 drm/i915/dg2: Enable Wa_22012727170/Wa_22012727685
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable WAs related to DG2
2022-04-15 22:40 [Intel-gfx] [PATCH 0/6] Enable WAs related to DG2 Umesh Nerlige Ramappa
` (6 preceding siblings ...)
2022-04-15 23:55 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable WAs related to DG2 Patchwork
@ 2022-04-15 23:56 ` Patchwork
2022-04-16 0:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-04-16 2:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
9 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2022-04-15 23:56 UTC (permalink / raw)
To: Umesh Nerlige Ramappa; +Cc: intel-gfx
== Series Details ==
Series: Enable WAs related to DG2
URL : https://patchwork.freedesktop.org/series/102745/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Enable WAs related to DG2
2022-04-15 22:40 [Intel-gfx] [PATCH 0/6] Enable WAs related to DG2 Umesh Nerlige Ramappa
` (7 preceding siblings ...)
2022-04-15 23:56 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-04-16 0:19 ` Patchwork
2022-04-16 2:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
9 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2022-04-16 0:19 UTC (permalink / raw)
To: Umesh Nerlige Ramappa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 7419 bytes --]
== Series Details ==
Series: Enable WAs related to DG2
URL : https://patchwork.freedesktop.org/series/102745/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11507 -> Patchwork_102745v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/index.html
Participating hosts (47 -> 46)
------------------------------
Additional (1): bat-adls-5
Missing (2): fi-bsw-cyan fi-bdw-samus
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_102745v1:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@hangcheck:
- {bat-adls-5}: NOTRUN -> [DMESG-WARN][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/bat-adls-5/igt@i915_selftest@live@hangcheck.html
Known issues
------------
Here are the changes found in Patchwork_102745v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [PASS][2] -> [INCOMPLETE][3] ([i915#4785])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
- fi-hsw-g3258: [PASS][4] -> [INCOMPLETE][5] ([i915#4785])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
- fi-snb-2600: [PASS][6] -> [INCOMPLETE][7] ([i915#3921])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@mman:
- fi-bdw-5557u: NOTRUN -> [INCOMPLETE][8] ([i915#5704])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/fi-bdw-5557u/igt@i915_selftest@live@mman.html
* igt@i915_selftest@live@vma:
- fi-bdw-5557u: NOTRUN -> [INCOMPLETE][9] ([i915#5681])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/fi-bdw-5557u/igt@i915_selftest@live@vma.html
* igt@kms_chamelium@dp-crc-fast:
- fi-bdw-5557u: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/fi-bdw-5557u/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-bdw-5557u: NOTRUN -> [SKIP][11] ([fdo#109271]) +14 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/fi-bdw-5557u/igt@kms_setmode@basic-clone-single-crtc.html
* igt@runner@aborted:
- fi-hsw-g3258: NOTRUN -> [FAIL][12] ([fdo#109271] / [i915#4312])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/fi-hsw-g3258/igt@runner@aborted.html
- fi-hsw-4770: NOTRUN -> [FAIL][13] ([fdo#109271] / [i915#4312] / [i915#5594])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/fi-hsw-4770/igt@runner@aborted.html
#### Possible fixes ####
* igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- {bat-adlp-6}: [DMESG-WARN][14] ([i915#3576]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u: [DMESG-FAIL][16] ([i915#62]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [DMESG-WARN][18] ([i915#62]) -> [PASS][19] +9 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-cfl-8109u: [DMESG-WARN][20] ([i915#5341] / [i915#62]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
[i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
[i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594
[i915#5681]: https://gitlab.freedesktop.org/drm/intel/issues/5681
[i915#5704]: https://gitlab.freedesktop.org/drm/intel/issues/5704
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
Build changes
-------------
* Linux: CI_DRM_11507 -> Patchwork_102745v1
CI-20190529: 20190529
CI_DRM_11507: 5d53713002150b7e3efb6e86985ba8d5caecf5b4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6438: 205a47d8f70e659df620573ce409d228c5762d11 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_102745v1: 5d53713002150b7e3efb6e86985ba8d5caecf5b4 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
53e81db354c0 drm/i915/dg2: Enable Wa_22012727170/Wa_22012727685
3077c9b66e7d drm/i915/dg2: Enable Wa_14014475959 - RCS / CCS context exit
a77ac791ee14 drm/i915/guc: Apply Wa_16011777198
5bf9d706f2a8 drm/i915/guc: Enable GuC based workarounds for DG2
28c69a6ff80b drm/i915/guc: Enable Wa_22011802037 for gen12 GuC based platforms
23760b3964c9 drm/i915: Add Wa_22011802037 force cs halt
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/index.html
[-- Attachment #2: Type: text/html, Size: 8308 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Enable WAs related to DG2
2022-04-15 22:40 [Intel-gfx] [PATCH 0/6] Enable WAs related to DG2 Umesh Nerlige Ramappa
` (8 preceding siblings ...)
2022-04-16 0:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-04-16 2:12 ` Patchwork
9 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2022-04-16 2:12 UTC (permalink / raw)
To: Umesh Nerlige Ramappa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 53559 bytes --]
== Series Details ==
Series: Enable WAs related to DG2
URL : https://patchwork.freedesktop.org/series/102745/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11507_full -> Patchwork_102745v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_102745v1_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_eio@unwedge-stress:
- {shard-dg1}: [PASS][1] -> [FAIL][2] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-dg1-12/igt@gem_eio@unwedge-stress.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-dg1-17/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_schedule@wide@vecs0:
- {shard-rkl}: [PASS][3] -> [INCOMPLETE][4] +4 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-rkl-1/igt@gem_exec_schedule@wide@vecs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-rkl-5/igt@gem_exec_schedule@wide@vecs0.html
Known issues
------------
Here are the changes found in Patchwork_102745v1_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-skl: ([PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28]) -> ([PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [FAIL][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) ([i915#5032])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl9/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl9/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl8/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl8/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl7/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl7/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl7/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl6/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl6/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl6/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl5/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl4/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl4/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl3/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl3/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl2/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl2/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl2/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl1/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl1/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl1/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl10/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl10/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl10/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl9/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl9/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl9/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl8/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl8/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl7/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl7/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl6/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl6/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl6/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl5/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl5/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl5/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl4/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl4/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl2/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl2/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl2/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl1/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl1/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl10/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl10/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-apl: [PASS][51] -> [DMESG-WARN][52] ([i915#180]) +4 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-apl8/igt@gem_ctx_isolation@preservation-s3@rcs0.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl2/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* igt@gem_ctx_persistence@legacy-engines-queued@vebox:
- shard-skl: [PASS][53] -> [DMESG-WARN][54] ([i915#1982])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl5/igt@gem_ctx_persistence@legacy-engines-queued@vebox.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl8/igt@gem_ctx_persistence@legacy-engines-queued@vebox.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-glk: [PASS][55] -> [FAIL][56] ([i915#2842]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-glk5/igt@gem_exec_fair@basic-none-solo@rcs0.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-glk7/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: [PASS][57] -> [FAIL][58] ([i915#2842]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-apl8/igt@gem_exec_fair@basic-none@vcs0.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl3/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][59] -> [FAIL][60] ([i915#2842]) +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [PASS][61] -> [FAIL][62] ([i915#2842]) +2 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-kbl6/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_flush@basic-uc-rw-default:
- shard-snb: [PASS][63] -> [SKIP][64] ([fdo#109271]) +3 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-snb5/igt@gem_exec_flush@basic-uc-rw-default.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-snb6/igt@gem_exec_flush@basic-uc-rw-default.html
* igt@gem_exec_parallel@engines@basic:
- shard-glk: [PASS][65] -> [DMESG-WARN][66] ([i915#118]) +2 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-glk6/igt@gem_exec_parallel@engines@basic.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-glk9/igt@gem_exec_parallel@engines@basic.html
* igt@gem_huc_copy@huc-copy:
- shard-iclb: NOTRUN -> [SKIP][67] ([i915#2190])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-iclb8/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@heavy-verify-multi:
- shard-skl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#4613])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl7/igt@gem_lmem_swapping@heavy-verify-multi.html
* igt@gem_lmem_swapping@parallel-multi:
- shard-kbl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#4613])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-kbl6/igt@gem_lmem_swapping@parallel-multi.html
* igt@gem_lmem_swapping@smem-oom:
- shard-apl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#4613])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl7/igt@gem_lmem_swapping@smem-oom.html
* igt@gem_pxp@create-valid-protected-context:
- shard-iclb: NOTRUN -> [SKIP][71] ([i915#4270])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-iclb8/igt@gem_pxp@create-valid-protected-context.html
* igt@gen3_render_mixed_blits:
- shard-iclb: NOTRUN -> [SKIP][72] ([fdo#109289])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-iclb6/igt@gen3_render_mixed_blits.html
* igt@gen7_exec_parse@basic-offset:
- shard-apl: NOTRUN -> [SKIP][73] ([fdo#109271]) +40 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl7/igt@gen7_exec_parse@basic-offset.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][74] -> [DMESG-WARN][75] ([i915#5566] / [i915#716])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-apl7/igt@gen9_exec_parse@allowed-single.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl2/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@unaligned-access:
- shard-tglb: NOTRUN -> [SKIP][76] ([i915#2527] / [i915#2856])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-tglb7/igt@gen9_exec_parse@unaligned-access.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][77] -> [FAIL][78] ([i915#454])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-iclb4/igt@i915_pm_dc@dc6-dpms.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: NOTRUN -> [DMESG-WARN][79] ([i915#180])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl4/igt@i915_suspend@sysfs-reader.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-0:
- shard-iclb: NOTRUN -> [SKIP][80] ([i915#5286]) +2 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-iclb6/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@linear-64bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][81] ([fdo#110725] / [fdo#111614])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-iclb8/igt@kms_big_fb@linear-64bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][82] ([i915#3743])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#3886]) +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl7/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][84] ([fdo#109278] / [i915#3886]) +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-iclb8/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#3886]) +4 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-kbl4/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#3886]) +3 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl4/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
- shard-iclb: NOTRUN -> [SKIP][87] ([fdo#109284] / [fdo#111827]) +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-iclb8/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
* igt@kms_color@pipe-d-ctm-0-5:
- shard-skl: NOTRUN -> [SKIP][88] ([fdo#109271]) +51 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl7/igt@kms_color@pipe-d-ctm-0-5.html
* igt@kms_color@pipe-d-ctm-red-to-blue:
- shard-iclb: NOTRUN -> [SKIP][89] ([fdo#109278] / [i915#1149])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-iclb8/igt@kms_color@pipe-d-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-b-ctm-max:
- shard-skl: NOTRUN -> [SKIP][90] ([fdo#109271] / [fdo#111827]) +2 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl7/igt@kms_color_chamelium@pipe-b-ctm-max.html
* igt@kms_color_chamelium@pipe-d-ctm-0-5:
- shard-kbl: NOTRUN -> [SKIP][91] ([fdo#109271] / [fdo#111827]) +3 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-kbl6/igt@kms_color_chamelium@pipe-d-ctm-0-5.html
* igt@kms_color_chamelium@pipe-d-ctm-max:
- shard-apl: NOTRUN -> [SKIP][92] ([fdo#109271] / [fdo#111827]) +1 similar issue
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl7/igt@kms_color_chamelium@pipe-d-ctm-max.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: NOTRUN -> [TIMEOUT][93] ([i915#1319])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl4/igt@kms_content_protection@atomic-dpms.html
- shard-kbl: NOTRUN -> [TIMEOUT][94] ([i915#1319])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-kbl6/igt@kms_content_protection@atomic-dpms.html
* igt@kms_cursor_edge_walk@pipe-d-64x64-left-edge:
- shard-kbl: NOTRUN -> [SKIP][95] ([fdo#109271]) +44 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-kbl6/igt@kms_cursor_edge_walk@pipe-d-64x64-left-edge.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [PASS][96] -> [FAIL][97] ([i915#72])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][98] -> [FAIL][99] ([i915#2346])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@wf_vblank-ts-check-interruptible@b-edp1:
- shard-skl: [PASS][100] -> [FAIL][101] ([i915#2122])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl4/igt@kms_flip@wf_vblank-ts-check-interruptible@b-edp1.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl5/igt@kms_flip@wf_vblank-ts-check-interruptible@b-edp1.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt:
- shard-iclb: NOTRUN -> [SKIP][102] ([fdo#109280]) +3 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch-dpms@bpc-switch-dpms-edp-1-pipe-a:
- shard-skl: [PASS][103] -> [FAIL][104] ([i915#1188])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl8/igt@kms_hdr@bpc-switch-dpms@bpc-switch-dpms-edp-1-pipe-a.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl4/igt@kms_hdr@bpc-switch-dpms@bpc-switch-dpms-edp-1-pipe-a.html
* igt@kms_invalid_mode@clock-too-high:
- shard-iclb: NOTRUN -> [SKIP][105] ([i915#4278])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-iclb8/igt@kms_invalid_mode@clock-too-high.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][106] ([fdo#109271] / [i915#533])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl7/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][107] ([fdo#109271] / [i915#533])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl7/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
- shard-iclb: NOTRUN -> [SKIP][108] ([fdo#109278]) +5 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-iclb8/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-skl: [PASS][109] -> [INCOMPLETE][110] ([i915#4939])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-kbl: NOTRUN -> [FAIL][111] ([fdo#108145] / [i915#265])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-kbl6/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-apl: NOTRUN -> [SKIP][112] ([fdo#109271] / [i915#658])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl7/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-skl: NOTRUN -> [SKIP][113] ([fdo#109271] / [i915#658])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl7/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@psr2_cursor_mmap_gtt:
- shard-iclb: NOTRUN -> [SKIP][114] ([fdo#109441])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_gtt.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-iclb: [PASS][115] -> [SKIP][116] ([i915#5519])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-iclb1/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-iclb6/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_setmode@basic-clone-single-crtc:
- shard-iclb: NOTRUN -> [SKIP][117] ([i915#3555])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-iclb8/igt@kms_setmode@basic-clone-single-crtc.html
* igt@kms_writeback@writeback-fb-id:
- shard-iclb: NOTRUN -> [SKIP][118] ([i915#2437])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-iclb8/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-apl: NOTRUN -> [SKIP][119] ([fdo#109271] / [i915#2437])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl7/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf@blocking:
- shard-skl: [PASS][120] -> [FAIL][121] ([i915#1542])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl4/igt@perf@blocking.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl2/igt@perf@blocking.html
* igt@sysfs_clients@sema-25:
- shard-skl: NOTRUN -> [SKIP][122] ([fdo#109271] / [i915#2994])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl7/igt@sysfs_clients@sema-25.html
#### Possible fixes ####
* igt@gem_eio@unwedge-stress:
- shard-tglb: [FAIL][123] ([i915#232]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-tglb5/igt@gem_eio@unwedge-stress.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-tglb6/igt@gem_eio@unwedge-stress.html
- {shard-tglu}: [TIMEOUT][125] ([i915#3063] / [i915#3648]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-tglu-2/igt@gem_eio@unwedge-stress.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-tglu-2/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-pace@rcs0:
- {shard-tglu}: [FAIL][127] ([i915#2842]) -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-tglu-6/igt@gem_exec_fair@basic-pace@rcs0.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-tglu-6/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [FAIL][129] ([i915#2842]) -> [PASS][130] +1 similar issue
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs1.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fence@expired-history:
- {shard-rkl}: [INCOMPLETE][131] -> [PASS][132] +2 similar issues
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-rkl-5/igt@gem_exec_fence@expired-history.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-rkl-4/igt@gem_exec_fence@expired-history.html
* igt@gem_exec_flush@basic-wb-prw-default:
- {shard-rkl}: [INCOMPLETE][133] ([i915#5080]) -> [PASS][134]
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-rkl-5/igt@gem_exec_flush@basic-wb-prw-default.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-rkl-2/igt@gem_exec_flush@basic-wb-prw-default.html
* igt@i915_pm_backlight@fade_with_dpms:
- {shard-rkl}: [SKIP][135] ([i915#3012]) -> [PASS][136]
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-rkl-4/igt@i915_pm_backlight@fade_with_dpms.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-rkl-6/igt@i915_pm_backlight@fade_with_dpms.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][137] ([i915#454]) -> [PASS][138]
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@basic-rte:
- {shard-rkl}: [SKIP][139] ([fdo#109308]) -> [PASS][140]
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-rkl-1/igt@i915_pm_rpm@basic-rte.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-rkl-6/igt@i915_pm_rpm@basic-rte.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- {shard-rkl}: [SKIP][141] ([i915#1845] / [i915#4098]) -> [PASS][142] +25 similar issues
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-rkl-1/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-rkl-6/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_color@pipe-b-degamma:
- {shard-rkl}: [SKIP][143] ([i915#1149] / [i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][144]
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-rkl-1/igt@kms_color@pipe-b-degamma.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-rkl-6/igt@kms_color@pipe-b-degamma.html
* igt@kms_cursor_crc@pipe-b-cursor-64x64-onscreen:
- {shard-rkl}: [SKIP][145] ([fdo#112022] / [i915#4070]) -> [PASS][146] +6 similar issues
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-rkl-5/igt@kms_cursor_crc@pipe-b-cursor-64x64-onscreen.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-64x64-onscreen.html
* igt@kms_cursor_edge_walk@pipe-a-256x256-left-edge:
- {shard-rkl}: [SKIP][147] ([i915#4070] / [i915#4098]) -> [PASS][148] +1 similar issue
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-rkl-4/igt@kms_cursor_edge_walk@pipe-a-256x256-left-edge.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-a-256x256-left-edge.html
* igt@kms_cursor_edge_walk@pipe-b-64x64-left-edge:
- {shard-rkl}: [SKIP][149] ([i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][150] +1 similar issue
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-rkl-1/igt@kms_cursor_edge_walk@pipe-b-64x64-left-edge.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-b-64x64-left-edge.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
- shard-iclb: [FAIL][151] ([i915#5072]) -> [PASS][152]
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-iclb7/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-iclb3/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [FAIL][153] ([i915#2346] / [i915#533]) -> [PASS][154]
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- {shard-rkl}: [SKIP][155] ([fdo#111825] / [i915#4070]) -> [PASS][156] +5 similar issues
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-rkl-4/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-rkl-6/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@pipe-c-forked-move:
- {shard-rkl}: [SKIP][157] ([i915#4070]) -> [PASS][158]
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-rkl-1/igt@kms_cursor_legacy@pipe-c-forked-move.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-rkl-5/igt@kms_cursor_legacy@pipe-c-forked-move.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled:
- {shard-rkl}: [SKIP][159] ([fdo#111314] / [i915#4098] / [i915#4369]) -> [PASS][160] +3 similar issues
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-rkl-1/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-rkl-6/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled:
- {shard-rkl}: [SKIP][161] ([i915#4098] / [i915#4369]) -> [PASS][162]
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-rkl-4/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-untiled.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [INCOMPLETE][163] ([i915#180]) -> [PASS][164]
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-apl4/igt@kms_fbcon_fbt@fbc-suspend.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][165] ([i915#180]) -> [PASS][166] +3 similar issues
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
- shard-apl: [DMESG-WARN][167] ([i915#180]) -> [PASS][168] +1 similar issue
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-suspend@b-edp1:
- shard-tglb: [DMESG-WARN][169] ([i915#2411] / [i915#2867]) -> [PASS][170]
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-tglb5/igt@kms_flip@flip-vs-suspend@b-edp1.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-tglb1/igt@kms_flip@flip-vs-suspend@b-edp1.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc:
- {shard-rkl}: [SKIP][171] ([i915#1849] / [i915#4098]) -> [PASS][172] +29 similar issues
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc.html
* igt@kms_invalid_mode@bad-vsync-start:
- {shard-rkl}: [SKIP][173] ([i915#4278]) -> [PASS][174]
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-rkl-1/igt@kms_invalid_mode@bad-vsync-start.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-rkl-6/igt@kms_invalid_mode@bad-vsync-start.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- {shard-rkl}: [SKIP][175] ([i915#4098]) -> [PASS][176] +1 similar issue
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-rkl-4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-rkl-6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
* igt@kms_plane@plane-position-hole@pipe-b-planes:
- {shard-rkl}: [SKIP][177] ([i915#1849] / [i915#3558]) -> [PASS][178] +1 similar issue
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-rkl-5/igt@kms_plane@plane-position-hole@pipe-b-planes.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-rkl-6/igt@kms_plane@plane-position-hole@pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][179] ([fdo#108145] / [i915#265]) -> [PASS][180] +1 similar issue
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
- shard-skl: [DMESG-WARN][181] ([i915#1982]) -> [PASS][182]
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl1/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl2/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html
* igt@kms_properties@plane-properties-legacy:
- {shard-rkl}: [SKIP][183] ([i915#1849]) -> [PASS][184]
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-rkl-1/igt@kms_properties@plane-properties-legacy.html
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-rkl-6/igt@kms_properties@plane-properties-legacy.html
* igt@kms_psr@primary_mmap_gtt:
- {shard-rkl}: [SKIP][185] ([i915#1072]) -> [PASS][186]
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-rkl-5/igt@kms_psr@primary_mmap_gtt.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-rkl-6/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][187] ([fdo#109441]) -> [PASS][188]
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_cpu.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- {shard-rkl}: [SKIP][189] ([i915#5461]) -> [PASS][190]
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-rkl-1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-rkl-6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_universal_plane@cursor-fb-leak-pipe-a:
- {shard-rkl}: [SKIP][191] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][192]
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-rkl-4/igt@kms_universal_plane@cursor-fb-leak-pipe-a.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-rkl-6/igt@kms_universal_plane@cursor-fb-leak-pipe-a.html
* igt@perf@polling-small-buf:
- shard-skl: [FAIL][193] ([i915#1722]) -> [PASS][194]
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl8/igt@perf@polling-small-buf.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl4/igt@perf@polling-small-buf.html
* igt@prime_vgem@basic-fence-flip:
- {shard-rkl}: [SKIP][195] ([i915#3708] / [i915#4098]) -> [PASS][196]
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-rkl-4/igt@prime_vgem@basic-fence-flip.html
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-rkl-6/igt@prime_vgem@basic-fence-flip.html
* igt@sysfs_heartbeat_interval@mixed@rcs0:
- shard-skl: [FAIL][197] ([i915#1731]) -> [PASS][198]
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl3/igt@sysfs_heartbeat_interval@mixed@rcs0.html
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl10/igt@sysfs_heartbeat_interval@mixed@rcs0.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-iclb: [DMESG-WARN][199] ([i915#5614]) -> [SKIP][200] ([i915#4525]) +1 similar issue
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-iclb1/igt@gem_exec_balancer@parallel-keep-submit-fence.html
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-iclb6/igt@gem_exec_balancer@parallel-keep-submit-fence.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [SKIP][201] ([i915#4525]) -> [DMESG-WARN][202] ([i915#5614]) +1 similar issue
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-iclb6/igt@gem_exec_balancer@parallel-out-fence.html
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-iclb4/igt@gem_exec_balancer@parallel-out-fence.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-render:
- shard-skl: [SKIP][203] ([fdo#109271]) -> [SKIP][204] ([fdo#109271] / [i915#1888])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-skl4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-render.html
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-skl2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-render.html
* igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-75@pipe-b-edp-1-downscale-with-pixel-format:
- shard-iclb: [INCOMPLETE][205] ([i915#1982] / [i915#5236]) -> [INCOMPLETE][206] ([i915#5293])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-iclb2/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-75@pipe-b-edp-1-downscale-with-pixel-format.html
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-iclb2/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-75@pipe-b-edp-1-downscale-with-pixel-format.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][207], [FAIL][208], [FAIL][209], [FAIL][210], [FAIL][211], [FAIL][212], [FAIL][213], [FAIL][214], [FAIL][215], [FAIL][216], [FAIL][217], [FAIL][218], [FAIL][219]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][220], [FAIL][221], [FAIL][222], [FAIL][223], [FAIL][224], [FAIL][225], [FAIL][226], [FAIL][227], [FAIL][228], [FAIL][229], [FAIL][230]) ([i915#3002] / [i915#4312] / [i915#5257])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-kbl7/igt@runner@aborted.html
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-kbl7/igt@runner@aborted.html
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-kbl7/igt@runner@aborted.html
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-kbl3/igt@runner@aborted.html
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-kbl1/igt@runner@aborted.html
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-kbl3/igt@runner@aborted.html
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-kbl4/igt@runner@aborted.html
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-kbl3/igt@runner@aborted.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-kbl7/igt@runner@aborted.html
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-kbl7/igt@runner@aborted.html
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-kbl3/igt@runner@aborted.html
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-kbl4/igt@runner@aborted.html
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-kbl6/igt@runner@aborted.html
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-kbl6/igt@runner@aborted.html
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-kbl3/igt@runner@aborted.html
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-kbl6/igt@runner@aborted.html
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-kbl6/igt@runner@aborted.html
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-kbl4/igt@runner@aborted.html
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-kbl1/igt@runner@aborted.html
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-kbl4/igt@runner@aborted.html
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-kbl7/igt@runner@aborted.html
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-kbl7/igt@runner@aborted.html
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-kbl7/igt@runner@aborted.html
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-kbl7/igt@runner@aborted.html
- shard-apl: ([FAIL][231], [FAIL][232], [FAIL][233], [FAIL][234], [FAIL][235], [FAIL][236], [FAIL][237], [FAIL][238]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][239], [FAIL][240], [FAIL][241], [FAIL][242], [FAIL][243], [FAIL][244], [FAIL][245], [FAIL][246], [FAIL][247], [FAIL][248], [FAIL][249], [FAIL][250]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-apl6/igt@runner@aborted.html
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-apl7/igt@runner@aborted.html
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-apl3/igt@runner@aborted.html
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-apl1/igt@runner@aborted.html
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-apl8/igt@runner@aborted.html
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-apl3/igt@runner@aborted.html
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-apl4/igt@runner@aborted.html
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11507/shard-apl4/igt@runner@aborted.html
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl4/igt@runner@aborted.html
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl4/igt@runner@aborted.html
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl2/igt@runner@aborted.html
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl2/igt@runner@aborted.html
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl4/igt@runner@aborted.html
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl8/igt@runner@aborted.html
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl4/igt@runner@aborted.html
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl8/igt@runner@aborted.html
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl6/igt@runner@aborted.html
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl1/igt@runner@aborted.html
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl7/igt@runner@aborted.html
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/shard-apl2/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#232]: https://gitlab.freedesktop.org/drm/intel/issues/232
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3376]: https://gitlab.freedesktop.org/drm/intel/issues/3376
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3648]: https://gitlab.freedesktop.org/drm/intel/issues/3648
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3736]: https://gitlab.freedesktop.org/drm/intel/issues/3736
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842
[i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4929]: https://gitlab.freedesktop.org/drm/intel/issues/4929
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#5032]: https://gitlab.freedesktop.org/drm/intel/issues/5032
[i915#5072]: https://gitlab.freedesktop.org/drm/intel/issues/5072
[i915#5080]: https://gitlab.freedesktop.org/drm/intel/issues/5080
[i915#5098]: https://gitlab.freedesktop.org/drm/intel/issues/5098
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5236]: https://gitlab.freedesktop.org/drm/intel/issues/5236
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5293]: https://gitlab.freedesktop.org/drm/intel/issues/5293
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5614]: https://gitlab.freedesktop.org/drm/intel/issues/5614
[i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
[i915#5675]: https://gitlab.freedesktop.org/drm/intel/issues/5675
[i915#5691]: https://gitlab.freedesktop.org/drm/intel/issues/5691
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
Build changes
-------------
* Linux: CI_DRM_11507 -> Patchwork_102745v1
CI-20190529: 20190529
CI_DRM_11507: 5d53713002150b7e3efb6e86985ba8d5caecf5b4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6438: 205a47d8f70e659df620573ce409d228c5762d11 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_102745v1: 5d53713002150b7e3efb6e86985ba8d5caecf5b4 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102745v1/index.html
[-- Attachment #2: Type: text/html, Size: 58907 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 3/6] drm/i915/guc: Enable GuC based workarounds for DG2
2022-04-15 22:40 ` [Intel-gfx] [PATCH 3/6] drm/i915/guc: Enable GuC based workarounds for DG2 Umesh Nerlige Ramappa
@ 2022-04-18 22:37 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 13+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-04-18 22:37 UTC (permalink / raw)
To: Umesh Nerlige Ramappa, intel-gfx, john.c.harrison
On 4/15/2022 3:40 PM, Umesh Nerlige Ramappa wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> There are some workarounds for DG2 that are implemented in the GuC
> firmware. However, the KMD is required to enable these by setting the
> appropriate flag as GuC does not know what platform it is running on.
> Wa_16011759253
> Wa_14012630569
> Wa_14013746162
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> CC: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 14 ++++++++++++++
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 2 ++
> 2 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 185fb4d59791..fd04c4cd9d44 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -292,6 +292,20 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
> GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 50))
> flags |= GUC_WA_POLLCS;
>
> + /* Wa_16011759253:dg2_g10:a0 */
> + if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0))
> + flags |= GUC_WA_GAM_CREDITS;
> +
> + /*
> + * Wa_14012197797:dg2_g10:a0,dg2_g11:a0
> + * Wa_22011391025:dg2_g10,dg2_g11,dg2_g12
> + *
> + * The same WA bit is used for both and 22011391025 is applicable to
> + * all DG2.
> + */
> + if (IS_DG2(gt->i915))
> + flags |= GUC_WA_DUAL_QUEUE;
> +
> /* Wa_22011802037: graphics version 12 */
> if (GRAPHICS_VER(gt->i915) == 12)
> flags |= GUC_WA_PRE_PARSER;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> index b136d6528fbf..fe5751f67b19 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> @@ -98,6 +98,8 @@
> #define GUC_LOG_BUF_ADDR_SHIFT 12
>
> #define GUC_CTL_WA 1
> +#define GUC_WA_GAM_CREDITS BIT(10)
> +#define GUC_WA_DUAL_QUEUE BIT(11)
> #define GUC_WA_PRE_PARSER BIT(14)
> #define GUC_WA_POLLCS BIT(18)
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Intel-gfx] [PATCH 2/6] drm/i915/guc: Enable Wa_22011802037 for gen12 GuC based platforms
2022-04-15 22:40 ` [Intel-gfx] [PATCH 2/6] drm/i915/guc: Enable Wa_22011802037 for gen12 GuC based platforms Umesh Nerlige Ramappa
@ 2022-04-19 0:57 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 13+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-04-19 0:57 UTC (permalink / raw)
To: Umesh Nerlige Ramappa, intel-gfx, john.c.harrison
On 4/15/2022 3:40 PM, Umesh Nerlige Ramappa wrote:
> Initiating a reset when the command streamer is not idle or in the
> middle of executing an MI_FORCE_WAKE can result in a hang. Multiple
> command streamers can be part of a single reset domain, so resetting one
> would mean resetting all command streamers in that domain.
>
> To workaround this, before initiating a reset, ensure that all command
> streamers within that reset domain are either IDLE or are not executing
> a MI_FORCE_WAKE.
>
> Enable GuC PRE_PARSER WA bit so that GuC follows the WA sequence when
> initiating engine-resets.
>
> For gt-resets, ensure that i915 applies the WA sequence.
>
> Opens to address in future patches:
> - The part of the WA to wait for pending forcewakes is also applicable
> to execlists backend.
> - The WA also needs to be applied for gen11
I would've preferred this patch to already include the gen11 checks, but
given that gen11 defaults to execlists submission and that we'd need to
specially enable GuC in CI to cover, I can see how making it a follow-up
makes things simpler, so not a blocker.
>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> ---
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 9 +-
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 18 ++++
> drivers/gpu/drm/i915/gt/intel_reset.c | 5 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 +
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 3 +-
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 85 ++++++++++++++++++-
> 6 files changed, 116 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> index eeead40485fb..f553e2173bda 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> @@ -182,15 +182,16 @@ static void gt_sanitize(struct intel_gt *gt, bool force)
> if (intel_gt_is_wedged(gt))
> intel_gt_unset_wedged(gt);
>
> - for_each_engine(engine, gt, id)
> + /* For GuC mode, ensure submission is disabled before stopping ring */
> + intel_uc_reset_prepare(>->uc);
> +
> + for_each_engine(engine, gt, id) {
> if (engine->reset.prepare)
> engine->reset.prepare(engine);
>
> - intel_uc_reset_prepare(>->uc);
> -
> - for_each_engine(engine, gt, id)
> if (engine->sanitize)
> engine->sanitize(engine);
> + }
>
> if (reset_engines(gt) || force) {
> for_each_engine(engine, gt, id)
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 0a5c2648aaf0..12d892851684 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -841,6 +841,24 @@
> #define CTC_SHIFT_PARAMETER_SHIFT 1
> #define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
>
> +/* GPM MSG_IDLE */
> +#define MSG_IDLE_CS _MMIO(0x8000)
> +#define MSG_IDLE_VCS0 _MMIO(0x8004)
> +#define MSG_IDLE_VCS1 _MMIO(0x8008)
> +#define MSG_IDLE_BCS _MMIO(0x800C)
> +#define MSG_IDLE_VECS0 _MMIO(0x8010)
> +#define MSG_IDLE_VCS2 _MMIO(0x80C0)
> +#define MSG_IDLE_VCS3 _MMIO(0x80C4)
> +#define MSG_IDLE_VCS4 _MMIO(0x80C8)
> +#define MSG_IDLE_VCS5 _MMIO(0x80CC)
> +#define MSG_IDLE_VCS6 _MMIO(0x80D0)
> +#define MSG_IDLE_VCS7 _MMIO(0x80D4)
> +#define MSG_IDLE_VECS1 _MMIO(0x80D8)
> +#define MSG_IDLE_VECS2 _MMIO(0x80DC)
> +#define MSG_IDLE_VECS3 _MMIO(0x80E0)
> +#define MSG_IDLE_FW_MASK REG_GENMASK(13, 9)
> +#define MSG_IDLE_FW_SHIFT 9
> +
> #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
> #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> index f52015e79fdf..5422a3b84bd4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -772,14 +772,15 @@ static intel_engine_mask_t reset_prepare(struct intel_gt *gt)
> intel_engine_mask_t awake = 0;
> enum intel_engine_id id;
>
> + /* For GuC mode, ensure submission is disabled before stopping ring */
> + intel_uc_reset_prepare(>->uc);
> +
> for_each_engine(engine, gt, id) {
> if (intel_engine_pm_get_if_awake(engine))
> awake |= engine->mask;
> reset_prepare_engine(engine);
> }
>
> - intel_uc_reset_prepare(>->uc);
> -
> return awake;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index cda7e4bb8bac..185fb4d59791 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -292,6 +292,10 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
> GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 50))
> flags |= GUC_WA_POLLCS;
>
> + /* Wa_22011802037: graphics version 12 */
> + if (GRAPHICS_VER(gt->i915) == 12)
> + flags |= GUC_WA_PRE_PARSER;
> +
> return flags;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> index c154b5efccde..b136d6528fbf 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> @@ -98,7 +98,8 @@
> #define GUC_LOG_BUF_ADDR_SHIFT 12
>
> #define GUC_CTL_WA 1
> -#define GUC_WA_POLLCS BIT(18)
> +#define GUC_WA_PRE_PARSER BIT(14)
> +#define GUC_WA_POLLCS BIT(18)
>
> #define GUC_CTL_FEATURE 2
> #define GUC_CTL_ENABLE_SLPC BIT(2)
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index ee45fdb67f32..172819cd1a0a 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1540,6 +1540,89 @@ static void guc_reset_state(struct intel_context *ce, u32 head, bool scrub)
> lrc_update_regs(ce, engine, head);
> }
>
> +static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
> +{
> + static const i915_reg_t _reg[I915_NUM_ENGINES] = {
> + [RCS0] = MSG_IDLE_CS,
> + [BCS0] = MSG_IDLE_BCS,
> + [VCS0] = MSG_IDLE_VCS0,
> + [VCS1] = MSG_IDLE_VCS1,
> + [VCS2] = MSG_IDLE_VCS2,
> + [VCS3] = MSG_IDLE_VCS3,
> + [VCS4] = MSG_IDLE_VCS4,
> + [VCS5] = MSG_IDLE_VCS5,
> + [VCS6] = MSG_IDLE_VCS6,
> + [VCS7] = MSG_IDLE_VCS7,
> + [VECS0] = MSG_IDLE_VECS0,
> + [VECS1] = MSG_IDLE_VECS1,
> + [VECS2] = MSG_IDLE_VECS2,
> + [VECS3] = MSG_IDLE_VECS3,
> + [CCS0] = MSG_IDLE_CS,
> + [CCS1] = MSG_IDLE_CS,
> + [CCS2] = MSG_IDLE_CS,
> + [CCS3] = MSG_IDLE_CS,
> + };
> + u32 val;
> +
> + if (!_reg[engine->id].reg)
> + return 0;
> +
> + val = intel_uncore_read(engine->uncore, _reg[engine->id]);
> +
> + /* bits[29:25] & bits[13:9] >> shift */
> + return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT;
> +}
> +
> +static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)
> +{
> + int ret;
> +
> + /* Ensure GPM receives fw up/down after CS is stopped */
> + udelay(1);
> +
> + /* Wait for forcewake request to complete in GPM */
> + ret = __intel_wait_for_register_fw(gt->uncore,
> + GEN9_PWRGT_DOMAIN_STATUS,
> + fw_mask, fw_mask, 5000, 0, NULL);
> +
> + /* Ensure CS receives fw ack from GPM */
> + udelay(1);
> +
> + if (ret)
> + GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret);
> +}
> +
> +/*
> + * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any
> + * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The
> + * pending status is indicated by bits[13:9] (masked by bits[ 29:25]) in the
> + * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we
> + * are concerned only with the gt reset here, we use a logical OR of pending
> + * forcewakeups from all reset domains and then wait for them to complete by
> + * querying PWRGT_DOMAIN_STATUS.
> + */
> +static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
> +{
> + u32 fw_pending;
> +
> + if (GRAPHICS_VER(engine->i915) != 12)
> + return;
> +
> + /*
> + * Wa_22011802037
> + * TODO: Occassionally trying to stop the cs times out, but does not
> + * adversely affect functionality. The timeout is set as a config
> + * parameter that defaults to 100ms. Assuming that this timeout is
> + * sufficient for any pending MI_FORCEWAKEs to complete, ignore the
> + * timeout returned here until it is root caused.
> + */
> + intel_engine_stop_cs(engine);
> +
> + fw_pending = __cs_pending_mi_force_wakes(engine);
> + if (fw_pending)
> + __gpm_wait_for_fw_complete(engine->gt, fw_pending);
> +}
> +
> static void guc_reset_nop(struct intel_engine_cs *engine)
> {
> }
> @@ -3795,7 +3878,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
>
> engine->sched_engine->schedule = i915_schedule;
>
> - engine->reset.prepare = guc_reset_nop;
> + engine->reset.prepare = guc_engine_reset_prepare;
> engine->reset.rewind = guc_rewind_nop;
> engine->reset.cancel = guc_reset_nop;
> engine->reset.finish = guc_reset_nop;
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2022-04-19 0:57 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-15 22:40 [Intel-gfx] [PATCH 0/6] Enable WAs related to DG2 Umesh Nerlige Ramappa
2022-04-15 22:40 ` [Intel-gfx] [PATCH 1/6] drm/i915: Add Wa_22011802037 force cs halt Umesh Nerlige Ramappa
2022-04-15 22:40 ` [Intel-gfx] [PATCH 2/6] drm/i915/guc: Enable Wa_22011802037 for gen12 GuC based platforms Umesh Nerlige Ramappa
2022-04-19 0:57 ` Ceraolo Spurio, Daniele
2022-04-15 22:40 ` [Intel-gfx] [PATCH 3/6] drm/i915/guc: Enable GuC based workarounds for DG2 Umesh Nerlige Ramappa
2022-04-18 22:37 ` Ceraolo Spurio, Daniele
2022-04-15 22:40 ` [Intel-gfx] [PATCH 4/6] drm/i915/guc: Apply Wa_16011777198 Umesh Nerlige Ramappa
2022-04-15 22:40 ` [Intel-gfx] [PATCH 5/6] drm/i915/dg2: Enable Wa_14014475959 - RCS / CCS context exit Umesh Nerlige Ramappa
2022-04-15 22:40 ` [Intel-gfx] [PATCH 6/6] drm/i915/dg2: Enable Wa_22012727170/Wa_22012727685 Umesh Nerlige Ramappa
2022-04-15 23:55 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable WAs related to DG2 Patchwork
2022-04-15 23:56 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-04-16 0:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-04-16 2:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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