[PATCH 1/4] ARM: dts: qcom: sdx55: do not use underscore in BCM node name

[PATCH 1/4] ARM: dts: qcom: sdx55: do not use underscore in BCM node name

[Krzysztof Kozlowski]

Align BCM voter node with DT schema by using hyphen instead of
underscore.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 arch/arm/boot/dts/qcom-sdx55.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi
index d455795da44c..4d45be049613 100644
--- a/arch/arm/boot/dts/qcom-sdx55.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx55.dtsi
@@ -770,7 +770,7 @@ rpmhpd_opp_turbo_l1: opp10 {
 				};
 			};
 
-			apps_bcm_voter: bcm_voter {
+			apps_bcm_voter: bcm-voter {
 				compatible = "qcom,bcm-voter";
 			};
 		};
-- 
2.32.0

[PATCH 2/4] ARM: dts: qcom: sdx55: remove wrong unit address from RPMH RSC clocks

[Krzysztof Kozlowski]

The clock controller of RPMH RSC does not have 'reg' property, so should
not have unit address.

Fixes: bae2f5979c6e ("ARM: dts: qcom: Add SDX65 platform and MTP board support")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 arch/arm/boot/dts/qcom-sdx65.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 796641d30e06..0c3f93603adc 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -202,7 +202,7 @@ apps_rsc: rsc@17830000 {
 				<WAKE_TCS    2>,
 				<CONTROL_TCS 1>;
 
-			rpmhcc: clock-controller@1 {
+			rpmhcc: clock-controller {
 				compatible = "qcom,sdx65-rpmh-clk";
 				#clock-cells = <1>;
 				clock-names = "xo";
-- 
2.32.0

[PATCH 3/4] arm64: dts: qcom: do not use underscore in BCM node name

[Krzysztof Kozlowski]

Align BCM voter node with DT schema by using hyphen instead of
underscore.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
 arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +-
 arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +-
 arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
 arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index e1c46b80f14a..86175d257b1e 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -3522,7 +3522,7 @@ rpmhpd_opp_turbo_l1: opp11 {
 				};
 			};
 
-			apps_bcm_voter: bcm_voter {
+			apps_bcm_voter: bcm-voter {
 				compatible = "qcom,bcm-voter";
 			};
 		};
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index d7c9edff19f7..443cd9c7f49f 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -1217,7 +1217,7 @@ rpmhpd_opp_turbo_l1: opp10 {
 				};
 			};
 
-			apps_bcm_voter: bcm_voter {
+			apps_bcm_voter: bcm-voter {
 				compatible = "qcom,bcm-voter";
 			};
 		};
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 15f3bf2e7ea0..b5c418d326b2 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -3744,7 +3744,7 @@ rpmhpd_opp_turbo_l1: opp11 {
 				};
 			};
 
-			apps_bcm_voter: bcm_voter {
+			apps_bcm_voter: bcm-voter {
 				compatible = "qcom,bcm-voter";
 			};
 		};
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index af8f22636436..56bf95b7f6ff 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -4654,7 +4654,7 @@ rpmhpd_opp_turbo_l1: opp10 {
 				};
 			};
 
-			apps_bcm_voter: bcm_voter {
+			apps_bcm_voter: bcm-voter {
 				compatible = "qcom,bcm-voter";
 			};
 		};
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 20f850b94158..008f6188c8b4 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1881,7 +1881,7 @@ rpmhpd_opp_turbo_l1: opp10 {
 				};
 			};
 
-			apps_bcm_voter: bcm_voter {
+			apps_bcm_voter: bcm-voter {
 				compatible = "qcom,bcm-voter";
 			};
 		};
-- 
2.32.0

[PATCH 4/4] dt-bindings: soc: qcom,rpmh-rsc: convert to dtschema

[Krzysztof Kozlowski]

Convert the Qualcomm RPMH RSC bindings to DT Schema.

Changes against original bindings:
1. Add qcom,tcs-offset as a property instead of one of reg (not used
   that way).
2. Add limits to interrupts.
3. Add child nodes (bcm-voter, clock-controller, power-controller).
4. Extend the example with more complex one.

The device description and DTS examples were copied from existing
sources, so keep the license as GPL-2.0-only.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 .../bindings/interconnect/qcom,bcm-voter.yaml |   8 +-
 .../bindings/soc/qcom/qcom,rpmh-rsc.yaml      | 272 ++++++++++++++++++
 .../devicetree/bindings/soc/qcom/rpmh-rsc.txt | 137 ---------
 3 files changed, 276 insertions(+), 141 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
 delete mode 100644 Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt

diff --git a/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml b/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml
index e23df4836c6f..eec987640b37 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml
@@ -45,20 +45,20 @@ additionalProperties: false
 
 examples:
   # Example 1: apps bcm_voter on SDM845 SoC should be defined inside &apps_rsc node
-  # as defined in Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt
+  # as defined in Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
   - |
 
-    apps_bcm_voter: bcm_voter {
+    apps_bcm_voter: bcm-voter {
         compatible = "qcom,bcm-voter";
     };
 
   # Example 2: disp bcm_voter on SDM845 should be defined inside &disp_rsc node
-  # as defined in Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt
+  # as defined in Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
   - |
 
     #include <dt-bindings/interconnect/qcom,icc.h>
 
-    disp_bcm_voter: bcm_voter {
+    disp_bcm_voter: bcm-voter {
         compatible = "qcom,bcm-voter";
         qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
     };
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
new file mode 100644
index 000000000000..f5ecf4a8c377
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
@@ -0,0 +1,272 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm RPMH RSC
+
+maintainers:
+  - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description: |
+  Resource Power Manager Hardened (RPMH) is the mechanism for communicating
+  with the hardened resource accelerators on Qualcomm SoCs. Requests to the
+  resources can be written to the Trigger Command Set (TCS)  registers and
+  using a (addr, val) pair and triggered. Messages in the TCS are then sent in
+  sequence over an internal bus.
+
+  The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity
+  (Resource State Coordinator a.k.a RSC) that can handle multiple sleep and
+  active/wake resource requests. Multiple such DRVs can exist in a SoC and can
+  be written to from Linux. The structure of each DRV follows the same template
+  with a few variations that are captured by the properties here.
+
+  A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
+  have powered off to facilitate idle power saving. TCS could be classified as::
+    ACTIVE  - Triggered by Linux
+    SLEEP   - Triggered by F/W
+    WAKE    - Triggered by F/W
+    CONTROL - Triggered by F/W
+  See also:: <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+  The order in which they are described in the DT, should match the hardware
+  configuration.
+
+  Requests can be made for the state of a resource, when the subsystem is
+  active or idle. When all subsystems like Modem, GPU, CPU are idle, the
+  resource state will be an aggregate of the sleep votes from each of those
+  subsystems. Clients may request a sleep value for their shared resources in
+  addition to the active mode requests.
+
+  Drivers that want to use the RSC to communicate with RPMH must specify their
+  bindings as child nodes of the RSC controllers they wish to communicate with.
+
+properties:
+  compatible:
+    const: qcom,rpmh-rsc
+
+  interrupts:
+    minItems: 1
+    maxItems: 4
+    description:
+      The interrupt that trips when a message complete/response is received for
+      this DRV from the accelerators.
+      Number of interrupts must match number of DRV blocks.
+
+  label:
+    description:
+      Name for the RSC. The name would be used in trace logs.
+
+  qcom,drv-id:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      The ID of the DRV in the RSC block that will be used by this controller.
+
+  qcom,tcs-config:
+    $ref: /schemas/types.yaml#/definitions/uint32-matrix
+    items:
+      - items:
+          - description: TCS type
+            enum: [ 0, 1, 2, 3 ]
+          - description: Number of TCS
+      - items:
+          - description: TCS type
+            enum: [ 0, 1, 2, 3 ]
+          - description: Number of TCS
+      - items:
+          - description: TCS type
+            enum: [ 0, 1, 2, 3]
+          - description: Numbe r of TCS
+      - items:
+          - description: TCS type
+            enum: [ 0, 1, 2, 3 ]
+          - description: Number of TCS
+    description: |
+      The tuple defining the configuration of TCS. Must have two cells which
+      describe each TCS type.  The order of the TCS must match the hardware
+      configuration.
+      Cell 1 (TCS Type):: TCS types to be specified::
+       - ACTIVE_TCS
+       - SLEEP_TCS
+       - WAKE_TCS
+       - CONTROL_TCS
+      Cell 2 (Number of TCS):: <u32>
+
+  qcom,tcs-offset:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      The offset of the TCS blocks.
+
+  reg:
+    minItems: 1
+    maxItems: 4
+
+  reg-names:
+    minItems: 1
+    items:
+      - const: drv-0
+      - const: drv-1
+      - const: drv-2
+      - const: drv-3
+
+  bcm-voter:
+    $ref: /schemas/interconnect/qcom,bcm-voter.yaml#
+
+  clock-controller:
+    $ref: /schemas/clock/qcom,rpmhcc.yaml#
+
+  power-controller:
+    $ref: /schemas/power/qcom,rpmpd.yaml#
+
+patternProperties:
+  '-regulators$':
+    $ref: /schemas/regulator/qcom,rpmh-regulator.yaml#
+
+required:
+  - compatible
+  - interrupts
+  - qcom,drv-id
+  - qcom,tcs-config
+  - qcom,tcs-offset
+  - reg
+  - reg-names
+
+additionalProperties: false
+
+examples:
+  - |
+    // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of
+    // 2, the register offsets for DRV2 start at 0D00, the register
+    // calculations are like this::
+    // DRV0: 0x179C0000
+    // DRV2: 0x179C0000 + 0x10000 = 0x179D0000
+    // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
+    // TCS-OFFSET: 0xD00
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+    rsc@179c0000 {
+        compatible = "qcom,rpmh-rsc";
+        reg = <0x179c0000 0x10000>,
+              <0x179d0000 0x10000>,
+              <0x179e0000 0x10000>;
+        reg-names = "drv-0", "drv-1", "drv-2";
+        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+        label = "apps_rsc";
+        qcom,tcs-offset = <0xd00>;
+        qcom,drv-id = <2>;
+        qcom,tcs-config = <ACTIVE_TCS  2>,
+                          <SLEEP_TCS   3>,
+                          <WAKE_TCS    3>,
+                          <CONTROL_TCS 1>;
+      };
+
+  - |
+    // For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the
+    // register offsets for DRV0 start at 01C00, the register calculations are
+    // like this::
+    // DRV0: 0xAF20000
+    // TCS-OFFSET: 0x1C00
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+    rsc@af20000 {
+        compatible = "qcom,rpmh-rsc";
+        reg = <0xaf20000 0x10000>;
+        reg-names = "drv-0";
+        interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+        label = "disp_rsc";
+        qcom,tcs-offset = <0x1c00>;
+        qcom,drv-id = <0>;
+        qcom,tcs-config = <ACTIVE_TCS  0>,
+                          <SLEEP_TCS   1>,
+                          <WAKE_TCS    1>,
+                          <CONTROL_TCS 0>;
+    };
+
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/soc/qcom,rpmh-rsc.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
+
+    rsc@18200000 {
+        compatible = "qcom,rpmh-rsc";
+        reg = <0x18200000 0x10000>,
+              <0x18210000 0x10000>,
+              <0x18220000 0x10000>;
+        reg-names = "drv-0", "drv-1", "drv-2";
+        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+        label = "apps_rsc";
+        qcom,tcs-offset = <0xd00>;
+        qcom,drv-id = <2>;
+        qcom,tcs-config = <ACTIVE_TCS  2>,
+                          <SLEEP_TCS   3>,
+                          <WAKE_TCS    3>,
+                          <CONTROL_TCS 0>;
+
+        clock-controller {
+            compatible = "qcom,sm8350-rpmh-clk";
+            #clock-cells = <1>;
+            clock-names = "xo";
+            clocks = <&xo_board>;
+        };
+
+        power-controller {
+            compatible = "qcom,sm8350-rpmhpd";
+            #power-domain-cells = <1>;
+            operating-points-v2 = <&rpmhpd_opp_table>;
+
+            rpmhpd_opp_table: opp-table {
+                compatible = "operating-points-v2";
+
+                rpmhpd_opp_ret: opp1 {
+                    opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+                };
+
+                rpmhpd_opp_min_svs: opp2 {
+                    opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+                };
+
+                rpmhpd_opp_low_svs: opp3 {
+                    opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+                };
+
+                rpmhpd_opp_svs: opp4 {
+                    opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+                };
+
+                rpmhpd_opp_svs_l1: opp5 {
+                    opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+                };
+
+                rpmhpd_opp_nom: opp6 {
+                    opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+                };
+
+                rpmhpd_opp_nom_l1: opp7 {
+                    opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+                };
+
+                rpmhpd_opp_nom_l2: opp8 {
+                    opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+                };
+
+                rpmhpd_opp_turbo: opp9 {
+                    opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+                };
+
+                rpmhpd_opp_turbo_l1: opp10 {
+                    opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+                };
+            };
+        };
+
+        bcm-voter {
+            compatible = "qcom,bcm-voter";
+        };
+    };
diff --git a/Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt b/Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt
deleted file mode 100644
index 9b86d1eff219..000000000000
--- a/Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt
+++ /dev/null
@@ -1,137 +0,0 @@
-RPMH RSC:
-------------
-
-Resource Power Manager Hardened (RPMH) is the mechanism for communicating with
-the hardened resource accelerators on Qualcomm SoCs. Requests to the resources
-can be written to the Trigger Command Set (TCS)  registers and using a (addr,
-val) pair and triggered. Messages in the TCS are then sent in sequence over an
-internal bus.
-
-The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity
-(Resource State Coordinator a.k.a RSC) that can handle multiple sleep and
-active/wake resource requests. Multiple such DRVs can exist in a SoC and can
-be written to from Linux. The structure of each DRV follows the same template
-with a few variations that are captured by the properties here.
-
-A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
-have powered off to facilitate idle power saving. TCS could be classified as -
-
-	ACTIVE  /* Triggered by Linux */
-	SLEEP   /* Triggered by F/W */
-	WAKE    /* Triggered by F/W */
-	CONTROL /* Triggered by F/W */
-
-The order in which they are described in the DT, should match the hardware
-configuration.
-
-Requests can be made for the state of a resource, when the subsystem is active
-or idle. When all subsystems like Modem, GPU, CPU are idle, the resource state
-will be an aggregate of the sleep votes from each of those subsystems. Clients
-may request a sleep value for their shared resources in addition to the active
-mode requests.
-
-Properties:
-
-- compatible:
-	Usage: required
-	Value type: <string>
-	Definition: Should be "qcom,rpmh-rsc".
-
-- reg:
-	Usage: required
-	Value type: <prop-encoded-array>
-	Definition: The first register specifies the base address of the
-		    DRV(s). The number of DRVs in the dependent on the RSC.
-	            The tcs-offset specifies the start address of the
-	            TCS in the DRVs.
-
-- reg-names:
-	Usage: required
-	Value type: <string>
-	Definition: Maps the register specified in the reg property. Must be
-	            "drv-0", "drv-1", "drv-2" etc and "tcs-offset". The
-
-- interrupts:
-	Usage: required
-	Value type: <prop-encoded-interrupt>
-	Definition: The interrupt that trips when a message complete/response
-	           is received for this DRV from the accelerators.
-
-- qcom,drv-id:
-	Usage: required
-	Value type: <u32>
-	Definition: The id of the DRV in the RSC block that will be used by
-		    this controller.
-
-- qcom,tcs-config:
-	Usage: required
-	Value type: <prop-encoded-array>
-	Definition: The tuple defining the configuration of TCS.
-	            Must have 2 cells which describe each TCS type.
-	            <type number_of_tcs>.
-	            The order of the TCS must match the hardware
-	            configuration.
-	- Cell #1 (TCS Type): TCS types to be specified -
-	            ACTIVE_TCS
-	            SLEEP_TCS
-	            WAKE_TCS
-	            CONTROL_TCS
-	- Cell #2 (Number of TCS): <u32>
-
-- label:
-	Usage: optional
-	Value type: <string>
-	Definition: Name for the RSC. The name would be used in trace logs.
-
-Drivers that want to use the RSC to communicate with RPMH must specify their
-bindings as child nodes of the RSC controllers they wish to communicate with.
-
-Example 1:
-
-For a TCS whose RSC base address is is 0x179C0000 and is at a DRV id of 2, the
-register offsets for DRV2 start at 0D00, the register calculations are like
-this -
-DRV0: 0x179C0000
-DRV2: 0x179C0000 + 0x10000 = 0x179D0000
-DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
-TCS-OFFSET: 0xD00
-
-	apps_rsc: rsc@179c0000 {
-		label = "apps_rsc";
-		compatible = "qcom,rpmh-rsc";
-		reg = <0x179c0000 0x10000>,
-		      <0x179d0000 0x10000>,
-		      <0x179e0000 0x10000>;
-		reg-names = "drv-0", "drv-1", "drv-2";
-		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
-		qcom,tcs-offset = <0xd00>;
-		qcom,drv-id = <2>;
-		qcom,tcs-config = <ACTIVE_TCS  2>,
-				  <SLEEP_TCS   3>,
-				  <WAKE_TCS    3>,
-				  <CONTROL_TCS 1>;
-	};
-
-Example 2:
-
-For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the
-register offsets for DRV0 start at 01C00, the register calculations are like
-this -
-DRV0: 0xAF20000
-TCS-OFFSET: 0x1C00
-
-	disp_rsc: rsc@af20000 {
-		label = "disp_rsc";
-		compatible = "qcom,rpmh-rsc";
-		reg = <0xaf20000 0x10000>;
-		reg-names = "drv-0";
-		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
-		qcom,tcs-offset = <0x1c00>;
-		qcom,drv-id = <0>;
-		qcom,tcs-config = <ACTIVE_TCS  0>,
-				  <SLEEP_TCS   1>,
-				  <WAKE_TCS    1>,
-				  <CONTROL_TCS 0>;
-	};
-- 
2.32.0

Re: [PATCH 4/4] dt-bindings: soc: qcom,rpmh-rsc: convert to dtschema

[Rob Herring]

On Mon, Apr 11, 2022 at 10:59:35AM +0200, Krzysztof Kozlowski wrote:
> Convert the Qualcomm RPMH RSC bindings to DT Schema.
> 
> Changes against original bindings:
> 1. Add qcom,tcs-offset as a property instead of one of reg (not used
>    that way).
> 2. Add limits to interrupts.
> 3. Add child nodes (bcm-voter, clock-controller, power-controller).
> 4. Extend the example with more complex one.
> 
> The device description and DTS examples were copied from existing
> sources, so keep the license as GPL-2.0-only.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
>  .../bindings/interconnect/qcom,bcm-voter.yaml |   8 +-
>  .../bindings/soc/qcom/qcom,rpmh-rsc.yaml      | 272 ++++++++++++++++++
>  .../devicetree/bindings/soc/qcom/rpmh-rsc.txt | 137 ---------
>  3 files changed, 276 insertions(+), 141 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
>  delete mode 100644 Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt
> 
> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml b/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml
> index e23df4836c6f..eec987640b37 100644
> --- a/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml
> @@ -45,20 +45,20 @@ additionalProperties: false
>  
>  examples:
>    # Example 1: apps bcm_voter on SDM845 SoC should be defined inside &apps_rsc node
> -  # as defined in Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt
> +  # as defined in Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
>    - |
>  
> -    apps_bcm_voter: bcm_voter {
> +    apps_bcm_voter: bcm-voter {
>          compatible = "qcom,bcm-voter";
>      };
>  
>    # Example 2: disp bcm_voter on SDM845 should be defined inside &disp_rsc node
> -  # as defined in Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt
> +  # as defined in Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
>    - |
>  
>      #include <dt-bindings/interconnect/qcom,icc.h>
>  
> -    disp_bcm_voter: bcm_voter {
> +    disp_bcm_voter: bcm-voter {
>          compatible = "qcom,bcm-voter";
>          qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
>      };
> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
> new file mode 100644
> index 000000000000..f5ecf4a8c377
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
> @@ -0,0 +1,272 @@
> +# SPDX-License-Identifier: GPL-2.0-only

Surely this file was all QCom or QCom LT authors and can be dual 
licensed. After all, it was QCom that complained to me about GPL only 
DT licensing...

> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm RPMH RSC
> +
> +maintainers:
> +  - Bjorn Andersson <bjorn.andersson@linaro.org>
> +
> +description: |
> +  Resource Power Manager Hardened (RPMH) is the mechanism for communicating
> +  with the hardened resource accelerators on Qualcomm SoCs. Requests to the
> +  resources can be written to the Trigger Command Set (TCS)  registers and
> +  using a (addr, val) pair and triggered. Messages in the TCS are then sent in
> +  sequence over an internal bus.
> +
> +  The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity
> +  (Resource State Coordinator a.k.a RSC) that can handle multiple sleep and
> +  active/wake resource requests. Multiple such DRVs can exist in a SoC and can
> +  be written to from Linux. The structure of each DRV follows the same template
> +  with a few variations that are captured by the properties here.
> +
> +  A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
> +  have powered off to facilitate idle power saving. TCS could be classified as::
> +    ACTIVE  - Triggered by Linux
> +    SLEEP   - Triggered by F/W
> +    WAKE    - Triggered by F/W
> +    CONTROL - Triggered by F/W
> +  See also:: <dt-bindings/soc/qcom,rpmh-rsc.h>
> +
> +  The order in which they are described in the DT, should match the hardware
> +  configuration.
> +
> +  Requests can be made for the state of a resource, when the subsystem is
> +  active or idle. When all subsystems like Modem, GPU, CPU are idle, the
> +  resource state will be an aggregate of the sleep votes from each of those
> +  subsystems. Clients may request a sleep value for their shared resources in
> +  addition to the active mode requests.
> +
> +  Drivers that want to use the RSC to communicate with RPMH must specify their
> +  bindings as child nodes of the RSC controllers they wish to communicate with.
> +
> +properties:
> +  compatible:
> +    const: qcom,rpmh-rsc
> +
> +  interrupts:
> +    minItems: 1
> +    maxItems: 4
> +    description:
> +      The interrupt that trips when a message complete/response is received for
> +      this DRV from the accelerators.
> +      Number of interrupts must match number of DRV blocks.
> +
> +  label:
> +    description:
> +      Name for the RSC. The name would be used in trace logs.
> +
> +  qcom,drv-id:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      The ID of the DRV in the RSC block that will be used by this controller.
> +
> +  qcom,tcs-config:
> +    $ref: /schemas/types.yaml#/definitions/uint32-matrix
> +    items:
> +      - items:

No need to repeat, use the schema form of 'items':

maxItems: 4
items:
  items:
    - ...
    - ...

> +          - description: TCS type
> +            enum: [ 0, 1, 2, 3 ]
> +          - description: Number of TCS
> +      - items:
> +          - description: TCS type
> +            enum: [ 0, 1, 2, 3 ]
> +          - description: Number of TCS
> +      - items:
> +          - description: TCS type
> +            enum: [ 0, 1, 2, 3]
> +          - description: Numbe r of TCS

Number

> +      - items:
> +          - description: TCS type
> +            enum: [ 0, 1, 2, 3 ]
> +          - description: Number of TCS
> +    description: |
> +      The tuple defining the configuration of TCS. Must have two cells which
> +      describe each TCS type.  The order of the TCS must match the hardware
> +      configuration.

> +      Cell 1 (TCS Type):: TCS types to be specified::
> +       - ACTIVE_TCS
> +       - SLEEP_TCS
> +       - WAKE_TCS
> +       - CONTROL_TCS
> +      Cell 2 (Number of TCS):: <u32>

All this should be in the per item descriptions.

> +
> +  qcom,tcs-offset:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      The offset of the TCS blocks.
> +
> +  reg:
> +    minItems: 1
> +    maxItems: 4
> +
> +  reg-names:
> +    minItems: 1
> +    items:
> +      - const: drv-0
> +      - const: drv-1
> +      - const: drv-2
> +      - const: drv-3
> +
> +  bcm-voter:
> +    $ref: /schemas/interconnect/qcom,bcm-voter.yaml#
> +
> +  clock-controller:
> +    $ref: /schemas/clock/qcom,rpmhcc.yaml#
> +
> +  power-controller:
> +    $ref: /schemas/power/qcom,rpmpd.yaml#
> +
> +patternProperties:
> +  '-regulators$':
> +    $ref: /schemas/regulator/qcom,rpmh-regulator.yaml#
> +
> +required:
> +  - compatible
> +  - interrupts
> +  - qcom,drv-id
> +  - qcom,tcs-config
> +  - qcom,tcs-offset
> +  - reg
> +  - reg-names
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of
> +    // 2, the register offsets for DRV2 start at 0D00, the register
> +    // calculations are like this::
> +    // DRV0: 0x179C0000
> +    // DRV2: 0x179C0000 + 0x10000 = 0x179D0000
> +    // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
> +    // TCS-OFFSET: 0xD00
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +
> +    rsc@179c0000 {
> +        compatible = "qcom,rpmh-rsc";
> +        reg = <0x179c0000 0x10000>,
> +              <0x179d0000 0x10000>,
> +              <0x179e0000 0x10000>;
> +        reg-names = "drv-0", "drv-1", "drv-2";
> +        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> +        label = "apps_rsc";
> +        qcom,tcs-offset = <0xd00>;
> +        qcom,drv-id = <2>;
> +        qcom,tcs-config = <ACTIVE_TCS  2>,
> +                          <SLEEP_TCS   3>,
> +                          <WAKE_TCS    3>,
> +                          <CONTROL_TCS 1>;
> +      };
> +
> +  - |
> +    // For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the
> +    // register offsets for DRV0 start at 01C00, the register calculations are
> +    // like this::
> +    // DRV0: 0xAF20000
> +    // TCS-OFFSET: 0x1C00
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +
> +    rsc@af20000 {
> +        compatible = "qcom,rpmh-rsc";
> +        reg = <0xaf20000 0x10000>;
> +        reg-names = "drv-0";
> +        interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
> +        label = "disp_rsc";
> +        qcom,tcs-offset = <0x1c00>;
> +        qcom,drv-id = <0>;
> +        qcom,tcs-config = <ACTIVE_TCS  0>,
> +                          <SLEEP_TCS   1>,
> +                          <WAKE_TCS    1>,
> +                          <CONTROL_TCS 0>;
> +    };
> +
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +    #include <dt-bindings/power/qcom-rpmpd.h>
> +
> +    rsc@18200000 {
> +        compatible = "qcom,rpmh-rsc";
> +        reg = <0x18200000 0x10000>,
> +              <0x18210000 0x10000>,
> +              <0x18220000 0x10000>;
> +        reg-names = "drv-0", "drv-1", "drv-2";
> +        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> +        label = "apps_rsc";
> +        qcom,tcs-offset = <0xd00>;
> +        qcom,drv-id = <2>;
> +        qcom,tcs-config = <ACTIVE_TCS  2>,
> +                          <SLEEP_TCS   3>,
> +                          <WAKE_TCS    3>,
> +                          <CONTROL_TCS 0>;
> +
> +        clock-controller {
> +            compatible = "qcom,sm8350-rpmh-clk";
> +            #clock-cells = <1>;
> +            clock-names = "xo";
> +            clocks = <&xo_board>;
> +        };
> +
> +        power-controller {
> +            compatible = "qcom,sm8350-rpmhpd";
> +            #power-domain-cells = <1>;
> +            operating-points-v2 = <&rpmhpd_opp_table>;
> +
> +            rpmhpd_opp_table: opp-table {
> +                compatible = "operating-points-v2";
> +
> +                rpmhpd_opp_ret: opp1 {
> +                    opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
> +                };
> +
> +                rpmhpd_opp_min_svs: opp2 {
> +                    opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> +                };
> +
> +                rpmhpd_opp_low_svs: opp3 {
> +                    opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> +                };
> +
> +                rpmhpd_opp_svs: opp4 {
> +                    opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> +                };
> +
> +                rpmhpd_opp_svs_l1: opp5 {
> +                    opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> +                };
> +
> +                rpmhpd_opp_nom: opp6 {
> +                    opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> +                };
> +
> +                rpmhpd_opp_nom_l1: opp7 {
> +                    opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> +                };
> +
> +                rpmhpd_opp_nom_l2: opp8 {
> +                    opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
> +                };
> +
> +                rpmhpd_opp_turbo: opp9 {
> +                    opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> +                };
> +
> +                rpmhpd_opp_turbo_l1: opp10 {
> +                    opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> +                };
> +            };
> +        };
> +
> +        bcm-voter {
> +            compatible = "qcom,bcm-voter";
> +        };
> +    };

Re: [PATCH 4/4] dt-bindings: soc: qcom,rpmh-rsc: convert to dtschema

[Krzysztof Kozlowski]

On 14/04/2022 03:01, Rob Herring wrote:
>> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
>> new file mode 100644
>> index 000000000000..f5ecf4a8c377
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml
>> @@ -0,0 +1,272 @@
>> +# SPDX-License-Identifier: GPL-2.0-only
> 
> Surely this file was all QCom or QCom LT authors and can be dual 
> licensed. After all, it was QCom that complained to me about GPL only 
> DT licensing...

I'll work on this.

Best regards,
Krzysztof

Re: (subset) [PATCH 1/4] ARM: dts: qcom: sdx55: do not use underscore in BCM node name

[Bjorn Andersson]

On Mon, 11 Apr 2022 10:59:32 +0200, Krzysztof Kozlowski wrote:
> Align BCM voter node with DT schema by using hyphen instead of
> underscore.
> 
> 

Applied, thanks!

[1/4] ARM: dts: qcom: sdx55: do not use underscore in BCM node name
      commit: 568cd3243331b6bf0702665f7bd90baa93e2b3ac

Best regards,
-- 
Bjorn Andersson <bjorn.andersson@linaro.org>

Re: (subset) [PATCH 2/4] ARM: dts: qcom: sdx55: remove wrong unit address from RPMH RSC clocks

[Bjorn Andersson]

On Mon, 11 Apr 2022 10:59:33 +0200, Krzysztof Kozlowski wrote:
> The clock controller of RPMH RSC does not have 'reg' property, so should
> not have unit address.
> 
> 

Applied, thanks!

[2/4] ARM: dts: qcom: sdx55: remove wrong unit address from RPMH RSC clocks
      commit: 97c246c825f73a018169834e56ffa9a89dea37a9

Best regards,
-- 
Bjorn Andersson <bjorn.andersson@linaro.org>

Re: (subset) [PATCH 3/4] arm64: dts: qcom: do not use underscore in BCM node name

[Bjorn Andersson]

On Mon, 11 Apr 2022 10:59:34 +0200, Krzysztof Kozlowski wrote:
> Align BCM voter node with DT schema by using hyphen instead of
> underscore.
> 
> 

Applied, thanks!

[3/4] arm64: dts: qcom: do not use underscore in BCM node name
      commit: fc0e7dd6d2e2c9f8b2c6497a190ee29d8f3aef3a

Best regards,
-- 
Bjorn Andersson <bjorn.andersson@linaro.org>

Re: (subset) [PATCH 4/4] dt-bindings: soc: qcom,rpmh-rsc: convert to dtschema

[Bjorn Andersson]

On Mon, 11 Apr 2022 10:59:35 +0200, Krzysztof Kozlowski wrote:
> Convert the Qualcomm RPMH RSC bindings to DT Schema.
> 
> Changes against original bindings:
> 1. Add qcom,tcs-offset as a property instead of one of reg (not used
>    that way).
> 2. Add limits to interrupts.
> 3. Add child nodes (bcm-voter, clock-controller, power-controller).
> 4. Extend the example with more complex one.
> 
> [...]

Applied, thanks!

[4/4] dt-bindings: soc: qcom,rpmh-rsc: convert to dtschema
      commit: 38d46b0f41ec57c734f1a647055644c2131c3d8f

Best regards,
-- 
Bjorn Andersson <bjorn.andersson@linaro.org>