From: ~eopxd <eopxd@git.sr.ht>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: WeiWei Li <liweiwei@iscas.ac.cn>,
Frank Chang <frank.chang@sifive.com>,
eop Chen <eop.chen@sifive.com>, Bin Meng <bin.meng@windriver.com>,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: [PATCH qemu v10 08/14] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
Date: Mon, 07 Mar 2022 01:43:53 -0800 [thread overview]
Message-ID: <165107198903.23549.13907705840662008250-8@git.sr.ht> (raw)
In-Reply-To: <165107198903.23549.13907705840662008250-0@git.sr.ht>
From: eopXD <eop.chen@sifive.com>
Compares write mask registers, and so always operate under a tail-
agnostic policy.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/vector_helper.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8755671449..6356b6b0ef 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1345,6 +1345,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(ETYPE); \
+ uint32_t total_elems = \
+ vext_get_total_elems(env, desc, esz); \
+ uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
@@ -1356,6 +1360,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
} \
env->vstart = 0; \
+ /* mask destination register are always tail-agnostic */ \
+ /* set tail elements to 1s */ \
+ if (vta_all_1s) { \
+ for (; i < total_elems; i++) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
+ } \
}
GEN_VEXT_CMP_VV(vmseq_vv_b, uint8_t, H1, DO_MSEQ)
@@ -1394,6 +1405,9 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(ETYPE); \
+ uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
+ uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
@@ -1405,6 +1419,13 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
DO_OP(s2, (ETYPE)(target_long)s1)); \
} \
env->vstart = 0; \
+ /* mask destination register are always tail-agnostic */ \
+ /* set tail elements to 1s */ \
+ if (vta_all_1s) { \
+ for (; i < total_elems; i++) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
+ } \
}
GEN_VEXT_CMP_VX(vmseq_vx_b, uint8_t, H1, DO_MSEQ)
--
2.34.2
WARNING: multiple messages have this Message-ID (diff)
From: ~eopxd <eopxd@git.sr.ht>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Frank Chang <frank.chang@sifive.com>,
WeiWei Li <liweiwei@iscas.ac.cn>, eop Chen <eop.chen@sifive.com>
Subject: [PATCH qemu v10 08/14] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
Date: Wed, 27 Apr 2022 15:06:41 -0000 [thread overview]
Message-ID: <165107198903.23549.13907705840662008250-8@git.sr.ht> (raw)
In-Reply-To: <165107198903.23549.13907705840662008250-0@git.sr.ht>
From: eopXD <eop.chen@sifive.com>
Compares write mask registers, and so always operate under a tail-
agnostic policy.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/vector_helper.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8755671449..6356b6b0ef 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1345,6 +1345,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(ETYPE); \
+ uint32_t total_elems = \
+ vext_get_total_elems(env, desc, esz); \
+ uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
@@ -1356,6 +1360,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
} \
env->vstart = 0; \
+ /* mask destination register are always tail-agnostic */ \
+ /* set tail elements to 1s */ \
+ if (vta_all_1s) { \
+ for (; i < total_elems; i++) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
+ } \
}
GEN_VEXT_CMP_VV(vmseq_vv_b, uint8_t, H1, DO_MSEQ)
@@ -1394,6 +1405,9 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(ETYPE); \
+ uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
+ uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
@@ -1405,6 +1419,13 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
DO_OP(s2, (ETYPE)(target_long)s1)); \
} \
env->vstart = 0; \
+ /* mask destination register are always tail-agnostic */ \
+ /* set tail elements to 1s */ \
+ if (vta_all_1s) { \
+ for (; i < total_elems; i++) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
+ } \
}
GEN_VEXT_CMP_VX(vmseq_vx_b, uint8_t, H1, DO_MSEQ)
--
2.34.2
next prev parent reply other threads:[~2022-04-27 15:09 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-27 15:06 [PATCH qemu v10 00/14] Add tail agnostic behavior for rvv instructions ~eopxd
2022-04-27 15:06 ` ~eopxd
2022-03-01 9:07 ` [PATCH qemu v10 04/14] target/riscv: rvv: Add tail agnostic for vv instructions ~eopxd
2022-04-27 15:06 ` ~eopxd
2022-04-27 23:11 ` Alistair Francis
2022-04-27 23:11 ` Alistair Francis
2022-04-27 23:13 ` Alistair Francis
2022-04-27 23:13 ` Alistair Francis
2022-04-27 23:14 ` Alistair Francis
2022-04-27 23:14 ` Alistair Francis
2022-03-07 7:10 ` [PATCH qemu v10 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions ~eopxd
2022-04-27 15:06 ` ~eopxd
2022-03-07 7:32 ` [PATCH qemu v10 06/14] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions ~eopxd
2022-04-27 15:06 ` ~eopxd
2022-03-07 9:38 ` [PATCH qemu v10 07/14] target/riscv: rvv: Add tail agnostic for vector integer shift instructions ~eopxd
2022-04-27 15:06 ` ~eopxd
2022-03-07 9:43 ` ~eopxd [this message]
2022-04-27 15:06 ` [PATCH qemu v10 08/14] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions ~eopxd
2022-03-07 9:53 ` [PATCH qemu v10 09/14] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions ~eopxd
2022-04-27 15:06 ` ~eopxd
2022-03-07 10:04 ` [PATCH qemu v10 10/14] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions ~eopxd
2022-04-27 15:06 ` ~eopxd
2022-03-07 10:05 ` [PATCH qemu v10 11/14] target/riscv: rvv: Add tail agnostic for vector floating-point instructions ~eopxd
2022-04-27 15:07 ` ~eopxd
2022-03-07 12:21 ` [PATCH qemu v10 12/14] target/riscv: rvv: Add tail agnostic for vector reduction instructions ~eopxd
2022-04-27 15:06 ` ~eopxd
2022-03-07 15:26 ` [PATCH qemu v10 13/14] target/riscv: rvv: Add tail agnostic for vector mask instructions ~eopxd
2022-04-27 15:06 ` ~eopxd
2022-03-07 15:59 ` [PATCH qemu v10 14/14] target/riscv: rvv: Add tail agnostic for vector permutation instructions ~eopxd
2022-04-27 15:07 ` ~eopxd
2022-03-09 8:34 ` [PATCH qemu v10 02/14] target/riscv: rvv: Rename ambiguous esz ~eopxd
2022-04-27 15:06 ` ~eopxd
2022-04-27 23:00 ` Alistair Francis
2022-04-27 23:00 ` Alistair Francis
2022-03-12 6:28 ` [PATCH qemu v10 03/14] target/riscv: rvv: Early exit when vstart >= vl ~eopxd
2022-04-27 15:06 ` ~eopxd
2022-04-27 23:02 ` Alistair Francis
2022-04-27 23:02 ` Alistair Francis
2022-03-14 7:38 ` [PATCH qemu v10 01/14] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed ~eopxd
2022-04-27 15:06 ` ~eopxd
2022-04-27 22:59 ` Alistair Francis
2022-04-27 22:59 ` Alistair Francis
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