[igt-dev] [PATCH 0/2] tests/dmabuf: Add tests for sync_file import/export

[igt-dev] [PATCH 0/2] tests/dmabuf: Add tests for sync_file import/export

[Jason Ekstrand]

This series adds tests for sync_file import/export as per this kernel
series on dri-devel:

https://patchwork.freedesktop.org/series/103602/
https://lists.freedesktop.org/archives/dri-devel/2022-May/354339.html

Jason Ekstrand (2):
  tests/dmabuf: Add tests for sync_file export (v4)
  tests/dmabuf: Add tests for sync_file import (v4)

 tests/dmabuf_sync_file.c | 513 +++++++++++++++++++++++++++++++++++++++
 tests/meson.build        |   1 +
 2 files changed, 514 insertions(+)
 create mode 100644 tests/dmabuf_sync_file.c

-- 
2.36.0

[igt-dev] [PATCH 1/2] tests/dmabuf: Add tests for sync_file export (v4)

[Jason Ekstrand]

From: Jason Ekstrand <jason@jlekstrand.net>

v2 (Jason Ekstrand):
 - Rename subtests to have "export" in the name

v3 (Jason Ekstrand):
 - Add an export-before-signal subtest

v4 (Jason Ekstrand):
 - Test both via sync_file and via poll to ensure the semantics match
   properly.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 tests/dmabuf_sync_file.c | 328 +++++++++++++++++++++++++++++++++++++++
 tests/meson.build        |   1 +
 2 files changed, 329 insertions(+)
 create mode 100644 tests/dmabuf_sync_file.c

diff --git a/tests/dmabuf_sync_file.c b/tests/dmabuf_sync_file.c
new file mode 100644
index 00000000..7fed60f8
--- /dev/null
+++ b/tests/dmabuf_sync_file.c
@@ -0,0 +1,328 @@
+/*
+ * Copyright © 2021 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include "igt_vgem.h"
+
+#include <linux/dma-buf.h>
+#include <sys/poll.h>
+
+IGT_TEST_DESCRIPTION("Tests for sync_file export from dma-buf");
+
+struct igt_dma_buf_sync_file {
+	__u32 flags;
+	__s32 fd;
+};
+
+#define IGT_DMA_BUF_IOCTL_EXPORT_SYNC_FILE _IOWR(DMA_BUF_BASE, 2, struct igt_dma_buf_sync_file)
+
+static bool has_dmabuf_export_sync_file(int fd)
+{
+	struct vgem_bo bo;
+	int dmabuf, ret;
+	struct igt_dma_buf_sync_file arg;
+
+	bo.width = 1;
+	bo.height = 1;
+	bo.bpp = 32;
+	vgem_create(fd, &bo);
+
+	dmabuf = prime_handle_to_fd(fd, bo.handle);
+	gem_close(fd, bo.handle);
+
+	arg.flags = DMA_BUF_SYNC_WRITE;
+	arg.fd = -1;
+
+	ret = igt_ioctl(dmabuf, IGT_DMA_BUF_IOCTL_EXPORT_SYNC_FILE, &arg);
+	close(dmabuf);
+	igt_assert(ret == 0 || errno == ENOTTY);
+
+	return ret == 0;
+}
+
+static int dmabuf_export_sync_file(int dmabuf, uint32_t flags)
+{
+	struct igt_dma_buf_sync_file arg;
+
+	arg.flags = flags;
+	arg.fd = -1;
+	do_ioctl(dmabuf, IGT_DMA_BUF_IOCTL_EXPORT_SYNC_FILE, &arg);
+
+	return arg.fd;
+}
+
+static bool dmabuf_busy(int dmabuf, uint32_t flags)
+{
+	struct pollfd pfd = { .fd = dmabuf };
+
+	/* If DMA_BUF_SYNC_WRITE is set, we don't want to set POLLIN or
+	 * else poll() may return a non-zero value if there are only read
+	 * fences because POLLIN is ready even if POLLOUT isn't.
+	 */
+	if (flags & DMA_BUF_SYNC_WRITE)
+		pfd.events |= POLLOUT;
+	else if (flags & DMA_BUF_SYNC_READ)
+		pfd.events |= POLLIN;
+
+	return poll(&pfd, 1, 0) == 0;
+}
+
+static bool sync_file_busy(int sync_file)
+{
+	struct pollfd pfd = { .fd = sync_file, .events = POLLIN };
+	return poll(&pfd, 1, 0) == 0;
+}
+
+static bool dmabuf_sync_file_busy(int dmabuf, uint32_t flags)
+{
+	int sync_file;
+	bool busy;
+
+	sync_file = dmabuf_export_sync_file(dmabuf, flags);
+	busy = sync_file_busy(sync_file);
+	close(sync_file);
+
+	return busy;
+}
+
+static void test_export_basic(int fd)
+{
+	struct vgem_bo bo;
+	int dmabuf;
+	uint32_t fence;
+
+	igt_require(has_dmabuf_export_sync_file(fd));
+
+	bo.width = 1;
+	bo.height = 1;
+	bo.bpp = 32;
+	vgem_create(fd, &bo);
+
+	dmabuf = prime_handle_to_fd(fd, bo.handle);
+
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+	igt_assert(!dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(!dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+
+	fence = vgem_fence_attach(fd, &bo, 0);
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(dmabuf_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+	igt_assert(dmabuf_busy(dmabuf, DMA_BUF_SYNC_RW));
+	igt_assert(!dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+	igt_assert(dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_RW));
+
+	vgem_fence_signal(fd, fence);
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_RW));
+	igt_assert(!dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(!dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+	igt_assert(!dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_RW));
+
+	fence = vgem_fence_attach(fd, &bo, VGEM_FENCE_WRITE);
+	igt_assert(dmabuf_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(dmabuf_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+	igt_assert(dmabuf_busy(dmabuf, DMA_BUF_SYNC_RW));
+	igt_assert(dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+	igt_assert(dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_RW));
+
+	vgem_fence_signal(fd, fence);
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_RW));
+	igt_assert(!dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(!dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+	igt_assert(!dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_RW));
+
+	close(dmabuf);
+	gem_close(fd, bo.handle);
+}
+
+static void test_export_before_signal(int fd)
+{
+	struct vgem_bo bo;
+	int dmabuf, read_fd, write_fd;
+	uint32_t fence;
+
+	igt_require(has_dmabuf_export_sync_file(fd));
+
+	bo.width = 1;
+	bo.height = 1;
+	bo.bpp = 32;
+	vgem_create(fd, &bo);
+
+	dmabuf = prime_handle_to_fd(fd, bo.handle);
+
+	igt_assert(!dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(!dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+
+	fence = vgem_fence_attach(fd, &bo, 0);
+
+	read_fd = dmabuf_export_sync_file(dmabuf, DMA_BUF_SYNC_READ);
+	write_fd = dmabuf_export_sync_file(dmabuf, DMA_BUF_SYNC_WRITE);
+
+	igt_assert(!sync_file_busy(read_fd));
+	igt_assert(sync_file_busy(write_fd));
+
+	vgem_fence_signal(fd, fence);
+
+	igt_assert(!sync_file_busy(read_fd));
+	igt_assert(!sync_file_busy(write_fd));
+
+	close(read_fd);
+	close(write_fd);
+
+	fence = vgem_fence_attach(fd, &bo, VGEM_FENCE_WRITE);
+
+	read_fd = dmabuf_export_sync_file(dmabuf, DMA_BUF_SYNC_READ);
+	write_fd = dmabuf_export_sync_file(dmabuf, DMA_BUF_SYNC_WRITE);
+
+	igt_assert(sync_file_busy(read_fd));
+	igt_assert(sync_file_busy(write_fd));
+
+	vgem_fence_signal(fd, fence);
+
+	igt_assert(!sync_file_busy(read_fd));
+	igt_assert(!sync_file_busy(write_fd));
+
+	close(read_fd);
+	close(write_fd);
+
+	close(dmabuf);
+	gem_close(fd, bo.handle);
+}
+
+static void test_export_multiwait(int fd)
+{
+	struct vgem_bo bo;
+	int dmabuf, sync_file;
+	uint32_t fence1, fence2, fence3;
+
+	igt_require(has_dmabuf_export_sync_file(fd));
+
+	bo.width = 1;
+	bo.height = 1;
+	bo.bpp = 32;
+	vgem_create(fd, &bo);
+
+	dmabuf = prime_handle_to_fd(fd, bo.handle);
+
+	fence1 = vgem_fence_attach(fd, &bo, 0);
+	fence2 = vgem_fence_attach(fd, &bo, 0);
+
+	sync_file = dmabuf_export_sync_file(dmabuf, DMA_BUF_SYNC_WRITE);
+
+	fence3 = vgem_fence_attach(fd, &bo, 0);
+
+	igt_assert(sync_file_busy(sync_file));
+
+	vgem_fence_signal(fd, fence1);
+
+	igt_assert(sync_file_busy(sync_file));
+
+	vgem_fence_signal(fd, fence2);
+
+	igt_assert(!sync_file_busy(sync_file));
+
+	vgem_fence_signal(fd, fence3);
+
+	close(sync_file);
+	close(dmabuf);
+	gem_close(fd, bo.handle);
+}
+
+static void test_export_wait_after_attach(int fd)
+{
+	struct vgem_bo bo;
+	int dmabuf, read_sync_file, write_sync_file;
+	uint32_t fence1, fence2;
+
+	igt_require(has_dmabuf_export_sync_file(fd));
+
+	bo.width = 1;
+	bo.height = 1;
+	bo.bpp = 32;
+	vgem_create(fd, &bo);
+
+	dmabuf = prime_handle_to_fd(fd, bo.handle);
+
+	read_sync_file = dmabuf_export_sync_file(dmabuf, DMA_BUF_SYNC_READ);
+	write_sync_file = dmabuf_export_sync_file(dmabuf, DMA_BUF_SYNC_WRITE);
+
+	fence1 = vgem_fence_attach(fd, &bo, VGEM_FENCE_WRITE);
+
+	igt_assert(!sync_file_busy(read_sync_file));
+	igt_assert(!sync_file_busy(write_sync_file));
+	close(read_sync_file);
+	close(write_sync_file);
+
+	/* These wait on fence1 */
+	read_sync_file = dmabuf_export_sync_file(dmabuf, DMA_BUF_SYNC_READ);
+	write_sync_file = dmabuf_export_sync_file(dmabuf, DMA_BUF_SYNC_WRITE);
+
+	igt_assert(sync_file_busy(read_sync_file));
+	igt_assert(sync_file_busy(write_sync_file));
+
+	vgem_fence_signal(fd, fence1);
+	fence2 = vgem_fence_attach(fd, &bo, VGEM_FENCE_WRITE);
+
+	/* fence1 has signaled */
+	igt_assert(!sync_file_busy(read_sync_file));
+	igt_assert(!sync_file_busy(write_sync_file));
+
+	/* fence2 has not */
+	igt_assert(dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+
+	vgem_fence_signal(fd, fence2);
+	close(read_sync_file);
+	close(write_sync_file);
+
+	close(dmabuf);
+	gem_close(fd, bo.handle);
+}
+
+igt_main
+{
+	int fd;
+
+	igt_fixture {
+		fd = drm_open_driver(DRIVER_VGEM);
+	}
+
+	igt_subtest_f("export-basic")
+		test_export_basic(fd);
+
+	igt_subtest_f("export-before-signal")
+		test_export_before_signal(fd);
+
+	igt_subtest_f("export-multiwait")
+		test_export_multiwait(fd);
+
+	igt_subtest_f("export-wait-after-attach")
+		test_export_wait_after_attach(fd);
+
+}
diff --git a/tests/meson.build b/tests/meson.build
index fb0f1e37..b548dc3b 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -7,6 +7,7 @@ test_progs = [
 	'core_setmaster_vs_auth',
 	'debugfs_test',
 	'dmabuf',
+	'dmabuf_sync_file',
 	'device_reset',
 	'drm_buddy',
 	'drm_import_export',
-- 
2.36.0

[igt-dev] [PATCH 2/2] tests/dmabuf: Add tests for sync_file import (v4)

[Jason Ekstrand]

From: Jason Ekstrand <jason@jlekstrand.net>

v2 (Jason Ekstrand):
 - Put the skip for igt_rwquire_sw_sync() in the subtests

v3 (Jason Ekstrand):
 - Use a separate igt_require(has_dmabuf_import_sync_file())
 - Tag as RFC because the kernel patches are RFC

v4 (Jason Ekstrand):
 - Rework the tests with the new semantics; import no longer tries to
   guarantee writes finish after reads.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 tests/dmabuf_sync_file.c | 185 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 185 insertions(+)

diff --git a/tests/dmabuf_sync_file.c b/tests/dmabuf_sync_file.c
index 7fed60f8..d29f569c 100644
--- a/tests/dmabuf_sync_file.c
+++ b/tests/dmabuf_sync_file.c
@@ -23,6 +23,7 @@
 
 #include "igt.h"
 #include "igt_vgem.h"
+#include "sw_sync.h"
 
 #include <linux/dma-buf.h>
 #include <sys/poll.h>
@@ -35,6 +36,7 @@ struct igt_dma_buf_sync_file {
 };
 
 #define IGT_DMA_BUF_IOCTL_EXPORT_SYNC_FILE _IOWR(DMA_BUF_BASE, 2, struct igt_dma_buf_sync_file)
+#define IGT_DMA_BUF_IOCTL_IMPORT_SYNC_FILE _IOW(DMA_BUF_BASE, 3, struct igt_dma_buf_sync_file)
 
 static bool has_dmabuf_export_sync_file(int fd)
 {
@@ -71,6 +73,55 @@ static int dmabuf_export_sync_file(int dmabuf, uint32_t flags)
 	return arg.fd;
 }
 
+static bool has_dmabuf_import_sync_file(int fd)
+{
+	struct vgem_bo bo;
+	int dmabuf, timeline, fence, ret;
+	struct igt_dma_buf_sync_file arg;
+
+	bo.width = 1;
+	bo.height = 1;
+	bo.bpp = 32;
+	vgem_create(fd, &bo);
+
+	dmabuf = prime_handle_to_fd(fd, bo.handle);
+	gem_close(fd, bo.handle);
+
+	timeline = sw_sync_timeline_create();
+	fence = sw_sync_timeline_create_fence(timeline, 1);
+	sw_sync_timeline_inc(timeline, 1);
+
+	arg.flags = DMA_BUF_SYNC_RW;
+	arg.fd = fence;
+
+	ret = igt_ioctl(dmabuf, IGT_DMA_BUF_IOCTL_IMPORT_SYNC_FILE, &arg);
+	close(dmabuf);
+	close(fence);
+	igt_assert(ret == 0 || errno == ENOTTY);
+
+	return ret == 0;
+}
+
+static void dmabuf_import_sync_file(int dmabuf, uint32_t flags, int sync_fd)
+{
+	struct igt_dma_buf_sync_file arg;
+
+	arg.flags = flags;
+	arg.fd = sync_fd;
+	do_ioctl(dmabuf, IGT_DMA_BUF_IOCTL_IMPORT_SYNC_FILE, &arg);
+}
+
+static void
+dmabuf_import_timeline_fence(int dmabuf, uint32_t flags,
+			     int timeline, uint32_t seqno)
+{
+	int fence;
+
+	fence = sw_sync_timeline_create_fence(timeline, seqno);
+	dmabuf_import_sync_file(dmabuf, flags, fence);
+	close(fence);
+}
+
 static bool dmabuf_busy(int dmabuf, uint32_t flags)
 {
 	struct pollfd pfd = { .fd = dmabuf };
@@ -305,6 +356,132 @@ static void test_export_wait_after_attach(int fd)
 	gem_close(fd, bo.handle);
 }
 
+static void test_import_basic(int fd)
+{
+	struct vgem_bo bo;
+	int dmabuf, timeline;
+
+	igt_require_sw_sync();
+	igt_require(has_dmabuf_import_sync_file(fd));
+
+	bo.width = 1;
+	bo.height = 1;
+	bo.bpp = 32;
+	vgem_create(fd, &bo);
+
+	dmabuf = prime_handle_to_fd(fd, bo.handle);
+
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+
+	timeline = sw_sync_timeline_create();
+
+	dmabuf_import_timeline_fence(dmabuf, DMA_BUF_SYNC_READ, timeline, 1);
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(dmabuf_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+	igt_assert(dmabuf_busy(dmabuf, DMA_BUF_SYNC_RW));
+	igt_assert(!dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+	igt_assert(dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_RW));
+
+	sw_sync_timeline_inc(timeline, 1);
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_RW));
+	igt_assert(!dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(!dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+	igt_assert(!dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_RW));
+
+	dmabuf_import_timeline_fence(dmabuf, DMA_BUF_SYNC_WRITE, timeline, 2);
+	igt_assert(dmabuf_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(dmabuf_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+	igt_assert(dmabuf_busy(dmabuf, DMA_BUF_SYNC_RW));
+	igt_assert(dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+	igt_assert(dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_RW));
+
+	sw_sync_timeline_inc(timeline, 1);
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_RW));
+	igt_assert(!dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(!dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+	igt_assert(!dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_RW));
+
+	dmabuf_import_timeline_fence(dmabuf, DMA_BUF_SYNC_RW, timeline, 3);
+	igt_assert(dmabuf_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(dmabuf_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+	igt_assert(dmabuf_busy(dmabuf, DMA_BUF_SYNC_RW));
+	igt_assert(dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+	igt_assert(dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_RW));
+
+	sw_sync_timeline_inc(timeline, 1);
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_RW));
+	igt_assert(!dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(!dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+	igt_assert(!dmabuf_sync_file_busy(dmabuf, DMA_BUF_SYNC_RW));
+}
+
+static void test_import_multiple(int fd, bool write)
+{
+	struct vgem_bo bo;
+	int i, dmabuf, read_sync_file, write_sync_file;
+	int write_timeline = -1, read_timelines[32];
+
+	igt_require_sw_sync();
+	igt_require(has_dmabuf_import_sync_file(fd));
+
+	bo.width = 1;
+	bo.height = 1;
+	bo.bpp = 32;
+	vgem_create(fd, &bo);
+
+	dmabuf = prime_handle_to_fd(fd, bo.handle);
+
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+
+	for (i = 0; i < ARRAY_SIZE(read_timelines); i++) {
+		read_timelines[i] = sw_sync_timeline_create();
+		dmabuf_import_timeline_fence(dmabuf, DMA_BUF_SYNC_READ,
+					     read_timelines[i], 1);
+	}
+
+	if (write) {
+		write_timeline = sw_sync_timeline_create();
+		dmabuf_import_timeline_fence(dmabuf, DMA_BUF_SYNC_WRITE,
+					     write_timeline, 1);
+	}
+
+	read_sync_file = dmabuf_export_sync_file(dmabuf, DMA_BUF_SYNC_READ);
+	write_sync_file = dmabuf_export_sync_file(dmabuf, DMA_BUF_SYNC_WRITE);
+
+	for (i = ARRAY_SIZE(read_timelines) - 1; i >= 0; i--) {
+		igt_assert_eq(dmabuf_busy(dmabuf, DMA_BUF_SYNC_READ), write);
+		igt_assert_eq(sync_file_busy(read_sync_file), write);
+		igt_assert(dmabuf_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+		igt_assert(sync_file_busy(write_sync_file));
+
+		sw_sync_timeline_inc(read_timelines[i], 1);
+	}
+
+	igt_assert_eq(dmabuf_busy(dmabuf, DMA_BUF_SYNC_READ), write);
+	igt_assert_eq(sync_file_busy(read_sync_file), write);
+	igt_assert_eq(dmabuf_busy(dmabuf, DMA_BUF_SYNC_WRITE), write);
+	igt_assert_eq(sync_file_busy(write_sync_file), write);
+
+	if (write)
+		sw_sync_timeline_inc(write_timeline, 1);
+
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_READ));
+	igt_assert(!sync_file_busy(read_sync_file));
+	igt_assert(!dmabuf_busy(dmabuf, DMA_BUF_SYNC_WRITE));
+	igt_assert(!sync_file_busy(write_sync_file));
+}
+
 igt_main
 {
 	int fd;
@@ -325,4 +502,12 @@ igt_main
 	igt_subtest_f("export-wait-after-attach")
 		test_export_wait_after_attach(fd);
 
+	igt_subtest_f("import-basic")
+		test_import_basic(fd);
+
+	igt_subtest_f("import-multiple-read-only")
+		test_import_multiple(fd, false);
+
+	igt_subtest_f("import-multiple-read-write")
+		test_import_multiple(fd, true);
 }
-- 
2.36.0

[igt-dev] ✓ Fi.CI.BAT: success for tests/dmabuf: Add tests for sync_file import/export (rev3)

[Patchwork]

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== Series Details ==

Series: tests/dmabuf: Add tests for sync_file import/export (rev3)
URL   : https://patchwork.freedesktop.org/series/90490/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11618 -> IGTPW_7056
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7056/index.html

Participating hosts (35 -> 33)
------------------------------

  Missing    (2): fi-bxt-dsi fi-bsw-cyan 

Known issues
------------

  Here are the changes found in IGTPW_7056 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@hangcheck:
    - fi-snb-2600:        [PASS][1] -> [INCOMPLETE][2] ([i915#3921])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7056/fi-snb-2600/igt@i915_selftest@live@hangcheck.html

  
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6468 -> IGTPW_7056

  CI-20190529: 20190529
  CI_DRM_11618: 07c7d578e3b8a85c79e9a7f8dace075192d5fd91 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_7056: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7056/index.html
  IGT_6468: cffa5fffe9acddf49565b4caeeb5e3355ff2ea44 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git


Testlist changes
----------------

+igt@dmabuf_sync_file@export-basic
+igt@dmabuf_sync_file@export-before-signal
+igt@dmabuf_sync_file@export-multiwait
+igt@dmabuf_sync_file@export-wait-after-attach
+igt@dmabuf_sync_file@import-basic
+igt@dmabuf_sync_file@import-multiple-read-only
+igt@dmabuf_sync_file@import-multiple-read-write

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7056/index.html

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[igt-dev] ✓ Fi.CI.IGT: success for tests/dmabuf: Add tests for sync_file import/export (rev3)

[Patchwork]

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== Series Details ==

Series: tests/dmabuf: Add tests for sync_file import/export (rev3)
URL   : https://patchwork.freedesktop.org/series/90490/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11618_full -> IGTPW_7056_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7056/index.html

Participating hosts (10 -> 7)
------------------------------

  Missing    (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005 

New tests
---------

  New tests have been introduced between CI_DRM_11618_full and IGTPW_7056_full:

### New IGT tests (7) ###

  * igt@dmabuf_sync_file@export-basic:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@dmabuf_sync_file@export-before-signal:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@dmabuf_sync_file@export-multiwait:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@dmabuf_sync_file@export-wait-after-attach:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@dmabuf_sync_file@import-basic:
    - Statuses : 1 skip(s)
    - Exec time: [0.00] s

  * igt@dmabuf_sync_file@import-multiple-read-only:
    - Statuses : 1 skip(s)
    - Exec time: [0.00] s

  * igt@dmabuf_sync_file@import-multiple-read-write:
    - Statuses : 1 skip(s)
    - Exec time: [0.00] s

  

Known issues
------------

  Here are the changes found in IGTPW_7056_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_persistence@engines-cleanup:
    - shard-snb:          NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7056/shard-snb7/igt@gem_ctx_persistence@engines-cleanup.html

  * igt@gem_exec_flush@basic-uc-ro-default:
    - shard-snb:          [PASS][2] -> [SKIP][3] ([fdo#109271]) +2 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-snb2/igt@gem_exec_flush@basic-uc-ro-default.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7056/shard-snb6/igt@gem_exec_flush@basic-uc-ro-default.html

  * igt@i915_hangman@engine-engine-hang:
    - shard-snb:          NOTRUN -> [SKIP][4] ([fdo#109271]) +117 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7056/shard-snb4/igt@i915_hangman@engine-engine-hang.html

  * igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
    - shard-snb:          NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +4 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7056/shard-snb4/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html

  * igt@syncobj_timeline@transfer-timeline-point:
    - shard-snb:          NOTRUN -> [DMESG-FAIL][6] ([i915#5098])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7056/shard-snb4/igt@syncobj_timeline@transfer-timeline-point.html

  
#### Possible fixes ####

  * igt@gem_exec_flush@basic-batch-kernel-default-wb:
    - shard-snb:          [SKIP][7] ([fdo#109271]) -> [PASS][8] +2 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11618/shard-snb6/igt@gem_exec_flush@basic-batch-kernel-default-wb.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7056/shard-snb2/igt@gem_exec_flush@basic-batch-kernel-default-wb.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
  [i915#5098]: https://gitlab.freedesktop.org/drm/intel/issues/5098


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6468 -> IGTPW_7056
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_11618: 07c7d578e3b8a85c79e9a7f8dace075192d5fd91 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_7056: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7056/index.html
  IGT_6468: cffa5fffe9acddf49565b4caeeb5e3355ff2ea44 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7056/index.html

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