* [Intel-gfx] [PATCH] drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend @ 2022-05-10 22:14 Nerlige Ramappa, Umesh 2022-05-10 22:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork ` (4 more replies) 0 siblings, 5 replies; 6+ messages in thread From: Nerlige Ramappa, Umesh @ 2022-05-10 22:14 UTC (permalink / raw) To: intel-gfx, Tvrtko Ursulin From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> For execlists backend, current implementation of Wa_22011802037 is to stop the CS before doing a reset of the engine. This WA was further extended to wait for any pending MI FORCE WAKEUPs before issuing a reset. Add the extended steps in the execlist path of reset. In addition, extend the WA to gen11. v2: (Tvrtko) - Clarify comments, commit message, fix typos - Use IS_GRAPHICS_VER for gen 11/12 checks Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Fixes: f6aa0d713c88 ("drm/i915: Add Wa_22011802037 force cs halt") --- drivers/gpu/drm/i915/gt/intel_engine.h | 2 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 85 ++++++++++++++++++- .../drm/i915/gt/intel_execlists_submission.c | 7 ++ .../gpu/drm/i915/gt/intel_ring_submission.c | 7 ++ drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 81 ++---------------- 6 files changed, 107 insertions(+), 79 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 1431f1e9dbee..04e435bce79b 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -201,6 +201,8 @@ int intel_ring_submission_setup(struct intel_engine_cs *engine); int intel_engine_stop_cs(struct intel_engine_cs *engine); void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine); +void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine); + void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask); u64 intel_engine_get_active_head(const struct intel_engine_cs *engine); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 14c6ddbbfde8..9943cf9655b2 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1282,10 +1282,10 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine, intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); /* - * Wa_22011802037 : gen12, Prior to doing a reset, ensure CS is + * Wa_22011802037 : gen11, gen12, Prior to doing a reset, ensure CS is * stopped, set ring stop bit and prefetch disable bit to halt CS */ - if (GRAPHICS_VER(engine->i915) == 12) + if (IS_GRAPHICS_VER(engine->i915, 11, 12)) intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base), _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE)); @@ -1308,6 +1308,18 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine) return -ENODEV; ENGINE_TRACE(engine, "\n"); + /* + * TODO: Find out why occasionally stopping the CS times out. Seen + * especially with gem_eio tests. + * + * Occasionally trying to stop the cs times out, but does not adversely + * affect functionality. The timeout is set as a config parameter that + * defaults to 100ms. In most cases the follow up operation is to wait + * for pending MI_FORCE_WAKES. The assumption is that this timeout is + * sufficient for any pending MI_FORCEWAKEs to complete. Once root + * caused, the caller must check and handle the return from this + * function. + */ if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) { ENGINE_TRACE(engine, "timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n", @@ -1334,6 +1346,75 @@ void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine) ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); } +static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine) +{ + static const i915_reg_t _reg[I915_NUM_ENGINES] = { + [RCS0] = MSG_IDLE_CS, + [BCS0] = MSG_IDLE_BCS, + [VCS0] = MSG_IDLE_VCS0, + [VCS1] = MSG_IDLE_VCS1, + [VCS2] = MSG_IDLE_VCS2, + [VCS3] = MSG_IDLE_VCS3, + [VCS4] = MSG_IDLE_VCS4, + [VCS5] = MSG_IDLE_VCS5, + [VCS6] = MSG_IDLE_VCS6, + [VCS7] = MSG_IDLE_VCS7, + [VECS0] = MSG_IDLE_VECS0, + [VECS1] = MSG_IDLE_VECS1, + [VECS2] = MSG_IDLE_VECS2, + [VECS3] = MSG_IDLE_VECS3, + [CCS0] = MSG_IDLE_CS, + [CCS1] = MSG_IDLE_CS, + [CCS2] = MSG_IDLE_CS, + [CCS3] = MSG_IDLE_CS, + }; + u32 val; + + if (!_reg[engine->id].reg) + return 0; + + val = intel_uncore_read(engine->uncore, _reg[engine->id]); + + /* bits[29:25] & bits[13:9] >> shift */ + return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT; +} + +static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask) +{ + int ret; + + /* Ensure GPM receives fw up/down after CS is stopped */ + udelay(1); + + /* Wait for forcewake request to complete in GPM */ + ret = __intel_wait_for_register_fw(gt->uncore, + GEN9_PWRGT_DOMAIN_STATUS, + fw_mask, fw_mask, 5000, 0, NULL); + + /* Ensure CS receives fw ack from GPM */ + udelay(1); + + if (ret) + GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret); +} + +/* + * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any + * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The + * pending status is indicated by bits[13:9] (masked by bits[29:25]) in the + * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we + * are concerned only with the gt reset here, we use a logical OR of pending + * forcewakeups from all reset domains and then wait for them to complete by + * querying PWRGT_DOMAIN_STATUS. + */ +void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine) +{ + u32 fw_pending = __cs_pending_mi_force_wakes(engine); + + if (fw_pending) + __gpm_wait_for_fw_complete(engine->gt, fw_pending); +} + static u32 read_subslice_reg(const struct intel_engine_cs *engine, int slice, int subslice, i915_reg_t reg) diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 86f7a9ac1c39..2caa1af77064 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -2958,6 +2958,13 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) ring_set_paused(engine, 1); intel_engine_stop_cs(engine); + /* + * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need + * to wait for any pending mi force wakeups + */ + if (IS_GRAPHICS_VER(engine->i915, 11, 12)) + intel_engine_wait_for_pending_mi_fw(engine); + engine->execlists.reset_ccid = active_ccid(engine); } diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 5423bfd301ad..a7808eff33c5 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -323,6 +323,13 @@ static void reset_prepare(struct intel_engine_cs *engine) ENGINE_TRACE(engine, "\n"); intel_engine_stop_cs(engine); + /* + * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need + * to wait for any pending mi force wakeups + */ + if (IS_GRAPHICS_VER(engine->i915, 11, 12)) + intel_engine_wait_for_pending_mi_fw(engine); + if (!stop_ring(engine)) { /* G45 ring initialization often fails to reset head to zero */ ENGINE_TRACE(engine, diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index 2c4ad4a65089..8c6885f43d1a 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -310,8 +310,8 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc) if (IS_DG2(gt->i915)) flags |= GUC_WA_DUAL_QUEUE; - /* Wa_22011802037: graphics version 12 */ - if (GRAPHICS_VER(gt->i915) == 12) + /* Wa_22011802037: graphics version 11/12 */ + if (IS_GRAPHICS_VER(gt->i915, 11, 12)) flags |= GUC_WA_PRE_PARSER; /* Wa_16011777198:dg2 */ diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 75291e9846c5..9b21c7345ffd 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -1527,87 +1527,18 @@ static void guc_reset_state(struct intel_context *ce, u32 head, bool scrub) lrc_update_regs(ce, engine, head); } -static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine) -{ - static const i915_reg_t _reg[I915_NUM_ENGINES] = { - [RCS0] = MSG_IDLE_CS, - [BCS0] = MSG_IDLE_BCS, - [VCS0] = MSG_IDLE_VCS0, - [VCS1] = MSG_IDLE_VCS1, - [VCS2] = MSG_IDLE_VCS2, - [VCS3] = MSG_IDLE_VCS3, - [VCS4] = MSG_IDLE_VCS4, - [VCS5] = MSG_IDLE_VCS5, - [VCS6] = MSG_IDLE_VCS6, - [VCS7] = MSG_IDLE_VCS7, - [VECS0] = MSG_IDLE_VECS0, - [VECS1] = MSG_IDLE_VECS1, - [VECS2] = MSG_IDLE_VECS2, - [VECS3] = MSG_IDLE_VECS3, - [CCS0] = MSG_IDLE_CS, - [CCS1] = MSG_IDLE_CS, - [CCS2] = MSG_IDLE_CS, - [CCS3] = MSG_IDLE_CS, - }; - u32 val; - - if (!_reg[engine->id].reg) - return 0; - - val = intel_uncore_read(engine->uncore, _reg[engine->id]); - - /* bits[29:25] & bits[13:9] >> shift */ - return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT; -} - -static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask) -{ - int ret; - - /* Ensure GPM receives fw up/down after CS is stopped */ - udelay(1); - - /* Wait for forcewake request to complete in GPM */ - ret = __intel_wait_for_register_fw(gt->uncore, - GEN9_PWRGT_DOMAIN_STATUS, - fw_mask, fw_mask, 5000, 0, NULL); - - /* Ensure CS receives fw ack from GPM */ - udelay(1); - - if (ret) - GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret); -} - -/* - * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any - * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The - * pending status is indicated by bits[13:9] (masked by bits[ 29:25]) in the - * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we - * are concerned only with the gt reset here, we use a logical OR of pending - * forcewakeups from all reset domains and then wait for them to complete by - * querying PWRGT_DOMAIN_STATUS. - */ static void guc_engine_reset_prepare(struct intel_engine_cs *engine) { - u32 fw_pending; - - if (GRAPHICS_VER(engine->i915) != 12) + if (!IS_GRAPHICS_VER(engine->i915, 11, 12)) return; - /* - * Wa_22011802037 - * TODO: Occasionally trying to stop the cs times out, but does not - * adversely affect functionality. The timeout is set as a config - * parameter that defaults to 100ms. Assuming that this timeout is - * sufficient for any pending MI_FORCEWAKEs to complete, ignore the - * timeout returned here until it is root caused. - */ intel_engine_stop_cs(engine); - fw_pending = __cs_pending_mi_force_wakes(engine); - if (fw_pending) - __gpm_wait_for_fw_complete(engine->gt, fw_pending); + /* + * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need + * to wait for any pending mi force wakeups + */ + intel_engine_wait_for_pending_mi_fw(engine); } static void guc_reset_nop(struct intel_engine_cs *engine) -- 2.35.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend 2022-05-10 22:14 [Intel-gfx] [PATCH] drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend Nerlige Ramappa, Umesh @ 2022-05-10 22:35 ` Patchwork 2022-05-10 22:54 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork ` (3 subsequent siblings) 4 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2022-05-10 22:35 UTC (permalink / raw) To: Nerlige Ramappa, Umesh; +Cc: intel-gfx == Series Details == Series: drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend URL : https://patchwork.freedesktop.org/series/103837/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend 2022-05-10 22:14 [Intel-gfx] [PATCH] drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend Nerlige Ramappa, Umesh 2022-05-10 22:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork @ 2022-05-10 22:54 ` Patchwork 2022-05-11 5:03 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork ` (2 subsequent siblings) 4 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2022-05-10 22:54 UTC (permalink / raw) To: Nerlige Ramappa, Umesh; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 5173 bytes --] == Series Details == Series: drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend URL : https://patchwork.freedesktop.org/series/103837/ State : success == Summary == CI Bug Log - changes from CI_DRM_11630 -> Patchwork_103837v1 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/index.html Participating hosts (44 -> 42) ------------------------------ Additional (2): fi-bdw-5557u bat-dg2-9 Missing (4): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus bat-dg1-5 Known issues ------------ Here are the changes found in Patchwork_103837v1 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live@gem: - fi-blb-e6850: NOTRUN -> [DMESG-FAIL][1] ([i915#4528]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/fi-blb-e6850/igt@i915_selftest@live@gem.html * igt@i915_selftest@live@hangcheck: - fi-bdw-5557u: NOTRUN -> [INCOMPLETE][2] ([i915#3921]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/fi-bdw-5557u/igt@i915_selftest@live@hangcheck.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-pnv-d510: NOTRUN -> [SKIP][3] ([fdo#109271]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/fi-pnv-d510/igt@kms_chamelium@common-hpd-after-suspend.html * igt@kms_chamelium@dp-crc-fast: - fi-bdw-5557u: NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +7 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/fi-bdw-5557u/igt@kms_chamelium@dp-crc-fast.html * igt@kms_setmode@basic-clone-single-crtc: - fi-bdw-5557u: NOTRUN -> [SKIP][5] ([fdo#109271]) +14 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/fi-bdw-5557u/igt@kms_setmode@basic-clone-single-crtc.html #### Possible fixes #### * igt@i915_selftest@live@requests: - fi-blb-e6850: [DMESG-FAIL][6] ([i915#4528]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/fi-blb-e6850/igt@i915_selftest@live@requests.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/fi-blb-e6850/igt@i915_selftest@live@requests.html - fi-pnv-d510: [DMESG-FAIL][8] ([i915#4528]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/fi-pnv-d510/igt@i915_selftest@live@requests.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/fi-pnv-d510/igt@i915_selftest@live@requests.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576 [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215 [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528 [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873 [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190 [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274 [i915#5275]: https://gitlab.freedesktop.org/drm/intel/issues/5275 [i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763 [i915#5879]: https://gitlab.freedesktop.org/drm/intel/issues/5879 [i915#5885]: https://gitlab.freedesktop.org/drm/intel/issues/5885 Build changes ------------- * Linux: CI_DRM_11630 -> Patchwork_103837v1 CI-20190529: 20190529 CI_DRM_11630: fa53ea1e866d739663dbcfab3afa4d0f5e3a12e1 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6471: 1d6816f1200520f936a799b7b0ef2e6f396abb16 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_103837v1: fa53ea1e866d739663dbcfab3afa4d0f5e3a12e1 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 0ad7b71680f6 drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/index.html [-- Attachment #2: Type: text/html, Size: 4731 bytes --] ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend 2022-05-10 22:14 [Intel-gfx] [PATCH] drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend Nerlige Ramappa, Umesh 2022-05-10 22:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork 2022-05-10 22:54 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2022-05-11 5:03 ` Patchwork 2022-05-11 15:26 ` [Intel-gfx] [PATCH] " Tvrtko Ursulin 2022-06-09 23:51 ` Ceraolo Spurio, Daniele 4 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2022-05-11 5:03 UTC (permalink / raw) To: Nerlige Ramappa, Umesh; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 43709 bytes --] == Series Details == Series: drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend URL : https://patchwork.freedesktop.org/series/103837/ State : success == Summary == CI Bug Log - changes from CI_DRM_11630_full -> Patchwork_103837v1_full ==================================================== Summary ------- **SUCCESS** No regressions found. Participating hosts (13 -> 12) ------------------------------ Missing (1): shard-dg1 Known issues ------------ Here are the changes found in Patchwork_103837v1_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [PASS][1] -> [FAIL][2] ([i915#2842]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-kbl6/igt@gem_exec_fair@basic-none@vcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][3] -> [FAIL][4] ([i915#2842]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-glk: [PASS][5] -> [FAIL][6] ([i915#2842]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-glk6/igt@gem_exec_fair@basic-pace@vcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-glk1/igt@gem_exec_fair@basic-pace@vcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][7] ([i915#2842]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs1.html * igt@gem_exec_fair@basic-sync@rcs0: - shard-tglb: [PASS][8] -> [SKIP][9] ([i915#2848]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-tglb5/igt@gem_exec_fair@basic-sync@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-tglb2/igt@gem_exec_fair@basic-sync@rcs0.html * igt@gem_exec_flush@basic-uc-set-default: - shard-snb: [PASS][10] -> [SKIP][11] ([fdo#109271]) +3 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-snb2/igt@gem_exec_flush@basic-uc-set-default.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-snb6/igt@gem_exec_flush@basic-uc-set-default.html * igt@gem_exec_params@no-vebox: - shard-iclb: NOTRUN -> [SKIP][12] ([fdo#109283]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@gem_exec_params@no-vebox.html * igt@gem_huc_copy@huc-copy: - shard-iclb: NOTRUN -> [SKIP][13] ([i915#2190]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@gem_huc_copy@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - shard-apl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-apl7/igt@gem_lmem_swapping@parallel-random-engines.html * igt@gem_pxp@reject-modify-context-protection-off-3: - shard-iclb: NOTRUN -> [SKIP][15] ([i915#4270]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@gem_pxp@reject-modify-context-protection-off-3.html * igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs: - shard-iclb: NOTRUN -> [SKIP][16] ([i915#768]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs.html * igt@gen3_render_linear_blits: - shard-iclb: NOTRUN -> [SKIP][17] ([fdo#109289]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@gen3_render_linear_blits.html * igt@gen9_exec_parse@allowed-single: - shard-glk: [PASS][18] -> [DMESG-WARN][19] ([i915#5566] / [i915#716]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-glk7/igt@gen9_exec_parse@allowed-single.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-glk1/igt@gen9_exec_parse@allowed-single.html * igt@gen9_exec_parse@cmd-crossing-page: - shard-iclb: NOTRUN -> [SKIP][20] ([i915#2856]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@gen9_exec_parse@cmd-crossing-page.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: NOTRUN -> [SKIP][21] ([i915#658]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb5/igt@i915_pm_dc@dc3co-vpb-simulation.html * igt@i915_pm_rpm@modeset-non-lpsp: - shard-iclb: NOTRUN -> [SKIP][22] ([fdo#110892]) +1 similar issue [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb5/igt@i915_pm_rpm@modeset-non-lpsp.html * igt@i915_pm_rpm@modeset-pc8-residency-stress: - shard-kbl: NOTRUN -> [SKIP][23] ([fdo#109271]) +15 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-kbl6/igt@i915_pm_rpm@modeset-pc8-residency-stress.html * igt@i915_pm_sseu@full-enable: - shard-iclb: NOTRUN -> [SKIP][24] ([i915#4387]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb5/igt@i915_pm_sseu@full-enable.html * igt@kms_async_flips@alternate-sync-async-flip: - shard-tglb: [PASS][25] -> [FAIL][26] ([i915#2521]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-tglb1/igt@kms_async_flips@alternate-sync-async-flip.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-tglb2/igt@kms_async_flips@alternate-sync-async-flip.html * igt@kms_atomic_transition@plane-all-modeset-transition-fencing: - shard-iclb: NOTRUN -> [SKIP][27] ([i915#1769]) +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html * igt@kms_big_fb@4-tiled-8bpp-rotate-90: - shard-iclb: NOTRUN -> [SKIP][28] ([i915#5286]) +1 similar issue [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html * igt@kms_big_fb@y-tiled-64bpp-rotate-90: - shard-iclb: NOTRUN -> [SKIP][29] ([fdo#110725] / [fdo#111614]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip: - shard-iclb: NOTRUN -> [SKIP][30] ([fdo#110723]) +2 similar issues [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb5/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html * igt@kms_big_joiner@invalid-modeset: - shard-iclb: NOTRUN -> [SKIP][31] ([i915#2705]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@kms_big_joiner@invalid-modeset.html * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc: - shard-kbl: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3886]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-kbl6/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs: - shard-apl: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3886]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-apl2/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs: - shard-iclb: NOTRUN -> [SKIP][34] ([fdo#109278] / [i915#3886]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html * igt@kms_chamelium@dp-hpd-storm-disable: - shard-apl: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +4 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-apl7/igt@kms_chamelium@dp-hpd-storm-disable.html * igt@kms_chamelium@vga-edid-read: - shard-kbl: NOTRUN -> [SKIP][36] ([fdo#109271] / [fdo#111827]) +1 similar issue [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-kbl6/igt@kms_chamelium@vga-edid-read.html * igt@kms_chamelium@vga-hpd-after-suspend: - shard-iclb: NOTRUN -> [SKIP][37] ([fdo#109284] / [fdo#111827]) +3 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb5/igt@kms_chamelium@vga-hpd-after-suspend.html * igt@kms_color_chamelium@pipe-b-ctm-0-5: - shard-skl: NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +1 similar issue [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-skl7/igt@kms_color_chamelium@pipe-b-ctm-0-5.html * igt@kms_content_protection@uevent: - shard-iclb: NOTRUN -> [SKIP][39] ([fdo#109300] / [fdo#111066]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@kms_content_protection@uevent.html * igt@kms_cursor_crc@pipe-b-cursor-512x512-sliding: - shard-iclb: NOTRUN -> [SKIP][40] ([fdo#109278] / [fdo#109279]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@kms_cursor_crc@pipe-b-cursor-512x512-sliding.html * igt@kms_cursor_legacy@flip-vs-cursor-legacy: - shard-iclb: [PASS][41] -> [FAIL][42] ([i915#2346]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-iclb4/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html - shard-skl: [PASS][43] -> [FAIL][44] ([i915#2346]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html * igt@kms_cursor_legacy@pipe-d-single-move: - shard-iclb: NOTRUN -> [SKIP][45] ([fdo#109278]) +20 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@kms_cursor_legacy@pipe-d-single-move.html * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-4tiled: - shard-iclb: NOTRUN -> [SKIP][46] ([i915#5287]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb5/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-4tiled.html * igt@kms_flip@2x-flip-vs-panning-vs-hang: - shard-skl: NOTRUN -> [SKIP][47] ([fdo#109271]) +4 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-skl7/igt@kms_flip@2x-flip-vs-panning-vs-hang.html * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible: - shard-iclb: NOTRUN -> [SKIP][48] ([fdo#109274]) +1 similar issue [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1: - shard-tglb: [PASS][49] -> [FAIL][50] ([i915#79]) +1 similar issue [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-tglb5/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-tglb2/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html * igt@kms_flip@flip-vs-suspend@a-dp1: - shard-apl: [PASS][51] -> [DMESG-WARN][52] ([i915#180]) +4 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-apl3/igt@kms_flip@flip-vs-suspend@a-dp1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-apl2/igt@kms_flip@flip-vs-suspend@a-dp1.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling: - shard-iclb: [PASS][53] -> [SKIP][54] ([i915#3701]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-iclb1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling: - shard-iclb: NOTRUN -> [SKIP][55] ([i915#2587]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt: - shard-iclb: NOTRUN -> [SKIP][56] ([fdo#109280]) +9 similar issues [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html * igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-edp-1-pipe-a: - shard-skl: [PASS][57] -> [FAIL][58] ([i915#1188]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-skl1/igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-edp-1-pipe-a.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-skl7/igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-edp-1-pipe-a.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - shard-apl: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#533]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-apl2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][60] -> [FAIL][61] ([fdo#108145] / [i915#265]) [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb: - shard-apl: NOTRUN -> [FAIL][62] ([i915#265]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-apl2/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html * igt@kms_plane_cursor@pipe-d-overlay-size-64: - shard-apl: NOTRUN -> [SKIP][63] ([fdo#109271]) +49 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-apl7/igt@kms_plane_cursor@pipe-d-overlay-size-64.html * igt@kms_plane_lowres@pipe-b-tiling-4: - shard-iclb: NOTRUN -> [SKIP][64] ([i915#5288]) [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@kms_plane_lowres@pipe-b-tiling-4.html * igt@kms_plane_lowres@pipe-b-tiling-none: - shard-iclb: NOTRUN -> [SKIP][65] ([i915#3536]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb5/igt@kms_plane_lowres@pipe-b-tiling-none.html * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale: - shard-iclb: [PASS][66] -> [SKIP][67] ([i915#5235]) +2 similar issues [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-iclb3/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area: - shard-iclb: NOTRUN -> [SKIP][68] ([fdo#111068] / [i915#658]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html * igt@kms_psr2_su@frontbuffer-xrgb8888: - shard-iclb: [PASS][69] -> [SKIP][70] ([fdo#109642] / [fdo#111068] / [i915#658]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-iclb2/igt@kms_psr2_su@frontbuffer-xrgb8888.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb8/igt@kms_psr2_su@frontbuffer-xrgb8888.html * igt@kms_psr@psr2_cursor_plane_move: - shard-iclb: [PASS][71] -> [SKIP][72] ([fdo#109441]) +3 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb4/igt@kms_psr@psr2_cursor_plane_move.html * igt@kms_psr@psr2_primary_mmap_gtt: - shard-iclb: NOTRUN -> [SKIP][73] ([fdo#109441]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@kms_psr@psr2_primary_mmap_gtt.html * igt@kms_setmode@basic-clone-single-crtc: - shard-iclb: NOTRUN -> [SKIP][74] ([i915#3555]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb5/igt@kms_setmode@basic-clone-single-crtc.html * igt@nouveau_crc@pipe-b-source-outp-inactive: - shard-iclb: NOTRUN -> [SKIP][75] ([i915#2530]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@nouveau_crc@pipe-b-source-outp-inactive.html * igt@perf@polling-small-buf: - shard-skl: [PASS][76] -> [FAIL][77] ([i915#1722]) [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-skl2/igt@perf@polling-small-buf.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-skl1/igt@perf@polling-small-buf.html * igt@prime_nv_pcopy@test3_1: - shard-iclb: NOTRUN -> [SKIP][78] ([fdo#109291]) +1 similar issue [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb5/igt@prime_nv_pcopy@test3_1.html * igt@prime_vgem@fence-write-hang: - shard-iclb: NOTRUN -> [SKIP][79] ([fdo#109295]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb5/igt@prime_vgem@fence-write-hang.html * igt@sysfs_clients@recycle: - shard-iclb: NOTRUN -> [SKIP][80] ([i915#2994]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@sysfs_clients@recycle.html * igt@tools_test@sysfs_l3_parity: - shard-iclb: NOTRUN -> [SKIP][81] ([fdo#109307]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@tools_test@sysfs_l3_parity.html #### Possible fixes #### * igt@drm_read@short-buffer-block: - {shard-rkl}: [SKIP][82] ([i915#4098]) -> [PASS][83] [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-rkl-1/igt@drm_read@short-buffer-block.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-rkl-6/igt@drm_read@short-buffer-block.html * igt@gem_eio@in-flight-contexts-10ms: - shard-tglb: [TIMEOUT][84] ([i915#3063]) -> [PASS][85] [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-tglb3/igt@gem_eio@in-flight-contexts-10ms.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-tglb1/igt@gem_eio@in-flight-contexts-10ms.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-apl: [FAIL][86] ([i915#2842]) -> [PASS][87] [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-apl4/igt@gem_exec_fair@basic-pace-solo@rcs0.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-apl3/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_exec_flush@basic-uc-rw-default: - shard-snb: [SKIP][88] ([fdo#109271]) -> [PASS][89] +1 similar issue [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-snb6/igt@gem_exec_flush@basic-uc-rw-default.html [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-snb2/igt@gem_exec_flush@basic-uc-rw-default.html * igt@gem_exec_whisper@basic-contexts-forked-all: - shard-glk: [DMESG-WARN][90] ([i915#118]) -> [PASS][91] [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-glk9/igt@gem_exec_whisper@basic-contexts-forked-all.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-glk6/igt@gem_exec_whisper@basic-contexts-forked-all.html * igt@i915_pm_dc@dc5-psr: - {shard-rkl}: [SKIP][92] ([i915#658]) -> [PASS][93] [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-rkl-1/igt@i915_pm_dc@dc5-psr.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-rkl-6/igt@i915_pm_dc@dc5-psr.html * igt@i915_pm_rpm@gem-mmap-type@uc: - {shard-rkl}: [SKIP][94] ([fdo#109308]) -> [PASS][95] +5 similar issues [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-rkl-1/igt@i915_pm_rpm@gem-mmap-type@uc.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-rkl-6/igt@i915_pm_rpm@gem-mmap-type@uc.html * igt@i915_selftest@mock@requests: - shard-skl: [INCOMPLETE][96] ([i915#5183]) -> [PASS][97] [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-skl1/igt@i915_selftest@mock@requests.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-skl7/igt@i915_selftest@mock@requests.html * igt@i915_suspend@debugfs-reader: - {shard-rkl}: [FAIL][98] ([fdo#103375]) -> [PASS][99] +1 similar issue [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-rkl-4/igt@i915_suspend@debugfs-reader.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-rkl-2/igt@i915_suspend@debugfs-reader.html - shard-apl: [DMESG-WARN][100] ([i915#180]) -> [PASS][101] +2 similar issues [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-apl4/igt@i915_suspend@debugfs-reader.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-apl7/igt@i915_suspend@debugfs-reader.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0: - {shard-rkl}: [SKIP][102] ([i915#1845] / [i915#4098]) -> [PASS][103] +23 similar issues [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-rkl-1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0.html [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-rkl-6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0.html * igt@kms_color@pipe-b-ctm-0-5: - {shard-rkl}: [SKIP][104] ([i915#1149] / [i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][105] +1 similar issue [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-rkl-1/igt@kms_color@pipe-b-ctm-0-5.html [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-rkl-6/igt@kms_color@pipe-b-ctm-0-5.html * igt@kms_color@pipe-c-invalid-gamma-lut-sizes: - {shard-rkl}: [SKIP][106] ([i915#4070]) -> [PASS][107] [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-rkl-6/igt@kms_color@pipe-c-invalid-gamma-lut-sizes.html [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-rkl-4/igt@kms_color@pipe-c-invalid-gamma-lut-sizes.html * igt@kms_cursor_crc@pipe-a-cursor-64x64-random: - {shard-rkl}: [SKIP][108] ([fdo#112022] / [i915#4070]) -> [PASS][109] +6 similar issues [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-rkl-1/igt@kms_cursor_crc@pipe-a-cursor-64x64-random.html [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-64x64-random.html * igt@kms_cursor_edge_walk@pipe-a-128x128-top-edge: - {shard-rkl}: [SKIP][110] ([i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][111] +2 similar issues [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-rkl-1/igt@kms_cursor_edge_walk@pipe-a-128x128-top-edge.html [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-a-128x128-top-edge.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-iclb: [FAIL][112] ([i915#2346]) -> [PASS][113] [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_cursor_legacy@flip-vs-cursor-varying-size: - {shard-rkl}: [SKIP][114] ([fdo#111825] / [i915#4070]) -> [PASS][115] +2 similar issues [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-rkl-1/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-rkl-6/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled: - {shard-rkl}: [SKIP][116] ([fdo#111314] / [i915#4098] / [i915#4369]) -> [PASS][117] +1 similar issue [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-rkl-1/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled.html [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled.html * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2: - shard-glk: [FAIL][118] ([i915#79]) -> [PASS][119] [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html * igt@kms_flip@2x-plain-flip-ts-check-interruptible@ac-hdmi-a1-hdmi-a2: - shard-glk: [FAIL][120] ([i915#2122]) -> [PASS][121] [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-glk9/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ac-hdmi-a1-hdmi-a2.html [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-glk6/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ac-hdmi-a1-hdmi-a2.html * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: - shard-kbl: [DMESG-WARN][122] ([i915#180]) -> [PASS][123] +3 similar issues [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt: - {shard-rkl}: [SKIP][124] ([i915#1849] / [i915#4098]) -> [PASS][125] +23 similar issues [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt.html [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt.html * igt@kms_invalid_mode@int-max-clock: - {shard-rkl}: [SKIP][126] ([i915#4278]) -> [PASS][127] +1 similar issue [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-rkl-1/igt@kms_invalid_mode@int-max-clock.html [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-rkl-6/igt@kms_invalid_mode@int-max-clock.html * igt@kms_plane@pixel-format@pipe-a-planes: - {shard-rkl}: [SKIP][128] ([i915#3558]) -> [PASS][129] +3 similar issues [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-rkl-1/igt@kms_plane@pixel-format@pipe-a-planes.html [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-rkl-6/igt@kms_plane@pixel-format@pipe-a-planes.html * igt@kms_prime@basic-crc@second-to-first: - {shard-rkl}: [SKIP][130] ([i915#1849]) -> [PASS][131] [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-rkl-1/igt@kms_prime@basic-crc@second-to-first.html [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-rkl-6/igt@kms_prime@basic-crc@second-to-first.html * igt@kms_psr@basic: - {shard-rkl}: [SKIP][132] ([i915#1072]) -> [PASS][133] +1 similar issue [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-rkl-1/igt@kms_psr@basic.html [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-rkl-6/igt@kms_psr@basic.html * igt@kms_psr@psr2_basic: - shard-iclb: [SKIP][134] ([fdo#109441]) -> [PASS][135] +1 similar issue [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-iclb1/igt@kms_psr@psr2_basic.html [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb2/igt@kms_psr@psr2_basic.html #### Warnings #### * igt@gem_exec_balancer@parallel: - shard-tglb: [DMESG-WARN][136] ([i915#5076] / [i915#5614]) -> [INCOMPLETE][137] ([i915#5076]) [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-tglb5/igt@gem_exec_balancer@parallel.html [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-tglb2/igt@gem_exec_balancer@parallel.html * igt@gem_exec_balancer@parallel-keep-submit-fence: - shard-iclb: [DMESG-WARN][138] ([i915#5614]) -> [SKIP][139] ([i915#4525]) +1 similar issue [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-iclb1/igt@gem_exec_balancer@parallel-keep-submit-fence.html [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb5/igt@gem_exec_balancer@parallel-keep-submit-fence.html * igt@gem_exec_balancer@parallel-ordering: - shard-iclb: [DMESG-FAIL][140] ([i915#5614]) -> [SKIP][141] ([i915#4525]) [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-iclb4/igt@gem_exec_balancer@parallel-ordering.html [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb7/igt@gem_exec_balancer@parallel-ordering.html * igt@gem_exec_balancer@parallel-out-fence: - shard-iclb: [SKIP][142] ([i915#4525]) -> [DMESG-WARN][143] ([i915#5614]) +2 similar issues [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-iclb6/igt@gem_exec_balancer@parallel-out-fence.html [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb4/igt@gem_exec_balancer@parallel-out-fence.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [FAIL][144] ([i915#2842]) -> [FAIL][145] ([i915#2849]) [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-iclb2/igt@gem_exec_fair@basic-throttle@rcs0.html [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb4/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@kms_flip@flip-vs-suspend@c-dp1: - shard-kbl: [DMESG-WARN][146] ([i915#180]) -> [INCOMPLETE][147] ([i915#3614]) [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-kbl1/igt@kms_flip@flip-vs-suspend@c-dp1.html [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-kbl3/igt@kms_flip@flip-vs-suspend@c-dp1.html * igt@kms_psr2_sf@cursor-plane-move-continuous-sf: - shard-iclb: [SKIP][148] ([i915#658]) -> [SKIP][149] ([i915#2920]) [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-iclb8/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html * igt@runner@aborted: - shard-kbl: ([FAIL][150], [FAIL][151], [FAIL][152], [FAIL][153], [FAIL][154], [FAIL][155], [FAIL][156], [FAIL][157], [FAIL][158], [FAIL][159], [FAIL][160], [FAIL][161], [FAIL][162], [FAIL][163]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][164], [FAIL][165], [FAIL][166], [FAIL][167], [FAIL][168], [FAIL][169], [FAIL][170], [FAIL][171], [FAIL][172], [FAIL][173], [FAIL][174], [FAIL][175]) ([i915#3002] / [i915#4312] / [i915#5257]) [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-kbl1/igt@runner@aborted.html [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-kbl1/igt@runner@aborted.html [152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-kbl7/igt@runner@aborted.html [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-kbl6/igt@runner@aborted.html [154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-kbl1/igt@runner@aborted.html [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-kbl1/igt@runner@aborted.html [156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-kbl7/igt@runner@aborted.html [157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-kbl7/igt@runner@aborted.html [158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-kbl6/igt@runner@aborted.html [159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-kbl3/igt@runner@aborted.html [160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-kbl1/igt@runner@aborted.html [161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-kbl1/igt@runner@aborted.html [162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-kbl3/igt@runner@aborted.html [163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11630/shard-kbl1/igt@runner@aborted.html [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-kbl6/igt@runner@aborted.html [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-kbl7/igt@runner@aborted.html [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-kbl7/igt@runner@aborted.html [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-kbl7/igt@runner@aborted.html [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-kbl6/igt@runner@aborted.html [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-kbl4/igt@runner@aborted.html [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-kbl3/igt@runner@aborted.html [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-kbl4/igt@runner@aborted.html [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-kbl1/igt@runner@aborted.html [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-kbl1/igt@runner@aborted.html [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-kbl3/igt@runner@aborted.html [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/shard-kbl3/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279 [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283 [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300 [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307 [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 [fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725 [fdo#110892]: https://bugs.freedesktop.org/show_bug.cgi?id=110892 [fdo#111066]: https://bugs.freedesktop.org/show_bug.cgi?id=111066 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722 [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825 [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849 [i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911 [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2232]: https://gitlab.freedesktop.org/drm/intel/issues/2232 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530 [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2848]: https://gitlab.freedesktop.org/drm/intel/issues/2848 [i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849 [i915#2851]: https://gitlab.freedesktop.org/drm/intel/issues/2851 [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856 [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002 [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012 [i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063 [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299 [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318 [i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319 [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 [i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558 [i915#3614]: https://gitlab.freedesktop.org/drm/intel/issues/3614 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955 [i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016 [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404 [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369 [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387 [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893 [i915#5076]: https://gitlab.freedesktop.org/drm/intel/issues/5076 [i915#5080]: https://gitlab.freedesktop.org/drm/intel/issues/5080 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5183]: https://gitlab.freedesktop.org/drm/intel/issues/5183 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287 [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288 [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439 [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461 [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566 [i915#5614]: https://gitlab.freedesktop.org/drm/intel/issues/5614 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 Build changes ------------- * Linux: CI_DRM_11630 -> Patchwork_103837v1 CI-20190529: 20190529 CI_DRM_11630: fa53ea1e866d739663dbcfab3afa4d0f5e3a12e1 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6471: 1d6816f1200520f936a799b7b0ef2e6f396abb16 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_103837v1: fa53ea1e866d739663dbcfab3afa4d0f5e3a12e1 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103837v1/index.html [-- Attachment #2: Type: text/html, Size: 48656 bytes --] ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend 2022-05-10 22:14 [Intel-gfx] [PATCH] drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend Nerlige Ramappa, Umesh ` (2 preceding siblings ...) 2022-05-11 5:03 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork @ 2022-05-11 15:26 ` Tvrtko Ursulin 2022-06-09 23:51 ` Ceraolo Spurio, Daniele 4 siblings, 0 replies; 6+ messages in thread From: Tvrtko Ursulin @ 2022-05-11 15:26 UTC (permalink / raw) To: Nerlige Ramappa, Umesh, intel-gfx On 10/05/2022 23:14, Nerlige Ramappa, Umesh wrote: > From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> > > For execlists backend, current implementation of Wa_22011802037 is to > stop the CS before doing a reset of the engine. This WA was further > extended to wait for any pending MI FORCE WAKEUPs before issuing a > reset. Add the extended steps in the execlist path of reset. > > In addition, extend the WA to gen11. > > v2: (Tvrtko) > - Clarify comments, commit message, fix typos > - Use IS_GRAPHICS_VER for gen 11/12 checks > > Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> > Fixes: f6aa0d713c88 ("drm/i915: Add Wa_22011802037 force cs halt") > --- > drivers/gpu/drm/i915/gt/intel_engine.h | 2 + > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 85 ++++++++++++++++++- > .../drm/i915/gt/intel_execlists_submission.c | 7 ++ > .../gpu/drm/i915/gt/intel_ring_submission.c | 7 ++ > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 +- > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 81 ++---------------- > 6 files changed, 107 insertions(+), 79 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h > index 1431f1e9dbee..04e435bce79b 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine.h > +++ b/drivers/gpu/drm/i915/gt/intel_engine.h > @@ -201,6 +201,8 @@ int intel_ring_submission_setup(struct intel_engine_cs *engine); > int intel_engine_stop_cs(struct intel_engine_cs *engine); > void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine); > > +void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine); > + > void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask); > > u64 intel_engine_get_active_head(const struct intel_engine_cs *engine); > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 14c6ddbbfde8..9943cf9655b2 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -1282,10 +1282,10 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine, > intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); > > /* > - * Wa_22011802037 : gen12, Prior to doing a reset, ensure CS is > + * Wa_22011802037 : gen11, gen12, Prior to doing a reset, ensure CS is > * stopped, set ring stop bit and prefetch disable bit to halt CS > */ > - if (GRAPHICS_VER(engine->i915) == 12) > + if (IS_GRAPHICS_VER(engine->i915, 11, 12)) > intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base), > _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE)); > > @@ -1308,6 +1308,18 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine) > return -ENODEV; > > ENGINE_TRACE(engine, "\n"); > + /* > + * TODO: Find out why occasionally stopping the CS times out. Seen > + * especially with gem_eio tests. > + * > + * Occasionally trying to stop the cs times out, but does not adversely > + * affect functionality. The timeout is set as a config parameter that > + * defaults to 100ms. In most cases the follow up operation is to wait > + * for pending MI_FORCE_WAKES. The assumption is that this timeout is > + * sufficient for any pending MI_FORCEWAKEs to complete. Once root > + * caused, the caller must check and handle the return from this > + * function. > + */ > if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) { > ENGINE_TRACE(engine, > "timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n", > @@ -1334,6 +1346,75 @@ void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine) > ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); > } > > +static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine) > +{ > + static const i915_reg_t _reg[I915_NUM_ENGINES] = { > + [RCS0] = MSG_IDLE_CS, > + [BCS0] = MSG_IDLE_BCS, > + [VCS0] = MSG_IDLE_VCS0, > + [VCS1] = MSG_IDLE_VCS1, > + [VCS2] = MSG_IDLE_VCS2, > + [VCS3] = MSG_IDLE_VCS3, > + [VCS4] = MSG_IDLE_VCS4, > + [VCS5] = MSG_IDLE_VCS5, > + [VCS6] = MSG_IDLE_VCS6, > + [VCS7] = MSG_IDLE_VCS7, > + [VECS0] = MSG_IDLE_VECS0, > + [VECS1] = MSG_IDLE_VECS1, > + [VECS2] = MSG_IDLE_VECS2, > + [VECS3] = MSG_IDLE_VECS3, > + [CCS0] = MSG_IDLE_CS, > + [CCS1] = MSG_IDLE_CS, > + [CCS2] = MSG_IDLE_CS, > + [CCS3] = MSG_IDLE_CS, > + }; > + u32 val; > + > + if (!_reg[engine->id].reg) > + return 0; Should this actually be a GEM_WARN_ON condition, to catch failures to update for new platforms? > + > + val = intel_uncore_read(engine->uncore, _reg[engine->id]); > + > + /* bits[29:25] & bits[13:9] >> shift */ > + return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT; > +} > + > +static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask) > +{ > + int ret; > + > + /* Ensure GPM receives fw up/down after CS is stopped */ > + udelay(1); > + > + /* Wait for forcewake request to complete in GPM */ > + ret = __intel_wait_for_register_fw(gt->uncore, > + GEN9_PWRGT_DOMAIN_STATUS, > + fw_mask, fw_mask, 5000, 0, NULL); No fast-slow split as discussed but okay, it's not making anything worse that it already is. Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Regards, Tvrtko > + > + /* Ensure CS receives fw ack from GPM */ > + udelay(1); > + > + if (ret) > + GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret); > +} > + > +/* > + * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any > + * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The > + * pending status is indicated by bits[13:9] (masked by bits[29:25]) in the > + * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we > + * are concerned only with the gt reset here, we use a logical OR of pending > + * forcewakeups from all reset domains and then wait for them to complete by > + * querying PWRGT_DOMAIN_STATUS. > + */ > +void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine) > +{ > + u32 fw_pending = __cs_pending_mi_force_wakes(engine); > + > + if (fw_pending) > + __gpm_wait_for_fw_complete(engine->gt, fw_pending); > +} > + > static u32 > read_subslice_reg(const struct intel_engine_cs *engine, > int slice, int subslice, i915_reg_t reg) > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c > index 86f7a9ac1c39..2caa1af77064 100644 > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c > @@ -2958,6 +2958,13 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) > ring_set_paused(engine, 1); > intel_engine_stop_cs(engine); > > + /* > + * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need > + * to wait for any pending mi force wakeups > + */ > + if (IS_GRAPHICS_VER(engine->i915, 11, 12)) > + intel_engine_wait_for_pending_mi_fw(engine); > + > engine->execlists.reset_ccid = active_ccid(engine); > } > > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > index 5423bfd301ad..a7808eff33c5 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > @@ -323,6 +323,13 @@ static void reset_prepare(struct intel_engine_cs *engine) > ENGINE_TRACE(engine, "\n"); > intel_engine_stop_cs(engine); > > + /* > + * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need > + * to wait for any pending mi force wakeups > + */ > + if (IS_GRAPHICS_VER(engine->i915, 11, 12)) > + intel_engine_wait_for_pending_mi_fw(engine); > + > if (!stop_ring(engine)) { > /* G45 ring initialization often fails to reset head to zero */ > ENGINE_TRACE(engine, > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c > index 2c4ad4a65089..8c6885f43d1a 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c > @@ -310,8 +310,8 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc) > if (IS_DG2(gt->i915)) > flags |= GUC_WA_DUAL_QUEUE; > > - /* Wa_22011802037: graphics version 12 */ > - if (GRAPHICS_VER(gt->i915) == 12) > + /* Wa_22011802037: graphics version 11/12 */ > + if (IS_GRAPHICS_VER(gt->i915, 11, 12)) > flags |= GUC_WA_PRE_PARSER; > > /* Wa_16011777198:dg2 */ > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > index 75291e9846c5..9b21c7345ffd 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > @@ -1527,87 +1527,18 @@ static void guc_reset_state(struct intel_context *ce, u32 head, bool scrub) > lrc_update_regs(ce, engine, head); > } > > -static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine) > -{ > - static const i915_reg_t _reg[I915_NUM_ENGINES] = { > - [RCS0] = MSG_IDLE_CS, > - [BCS0] = MSG_IDLE_BCS, > - [VCS0] = MSG_IDLE_VCS0, > - [VCS1] = MSG_IDLE_VCS1, > - [VCS2] = MSG_IDLE_VCS2, > - [VCS3] = MSG_IDLE_VCS3, > - [VCS4] = MSG_IDLE_VCS4, > - [VCS5] = MSG_IDLE_VCS5, > - [VCS6] = MSG_IDLE_VCS6, > - [VCS7] = MSG_IDLE_VCS7, > - [VECS0] = MSG_IDLE_VECS0, > - [VECS1] = MSG_IDLE_VECS1, > - [VECS2] = MSG_IDLE_VECS2, > - [VECS3] = MSG_IDLE_VECS3, > - [CCS0] = MSG_IDLE_CS, > - [CCS1] = MSG_IDLE_CS, > - [CCS2] = MSG_IDLE_CS, > - [CCS3] = MSG_IDLE_CS, > - }; > - u32 val; > - > - if (!_reg[engine->id].reg) > - return 0; > - > - val = intel_uncore_read(engine->uncore, _reg[engine->id]); > - > - /* bits[29:25] & bits[13:9] >> shift */ > - return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT; > -} > - > -static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask) > -{ > - int ret; > - > - /* Ensure GPM receives fw up/down after CS is stopped */ > - udelay(1); > - > - /* Wait for forcewake request to complete in GPM */ > - ret = __intel_wait_for_register_fw(gt->uncore, > - GEN9_PWRGT_DOMAIN_STATUS, > - fw_mask, fw_mask, 5000, 0, NULL); > - > - /* Ensure CS receives fw ack from GPM */ > - udelay(1); > - > - if (ret) > - GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret); > -} > - > -/* > - * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any > - * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The > - * pending status is indicated by bits[13:9] (masked by bits[ 29:25]) in the > - * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we > - * are concerned only with the gt reset here, we use a logical OR of pending > - * forcewakeups from all reset domains and then wait for them to complete by > - * querying PWRGT_DOMAIN_STATUS. > - */ > static void guc_engine_reset_prepare(struct intel_engine_cs *engine) > { > - u32 fw_pending; > - > - if (GRAPHICS_VER(engine->i915) != 12) > + if (!IS_GRAPHICS_VER(engine->i915, 11, 12)) > return; > > - /* > - * Wa_22011802037 > - * TODO: Occasionally trying to stop the cs times out, but does not > - * adversely affect functionality. The timeout is set as a config > - * parameter that defaults to 100ms. Assuming that this timeout is > - * sufficient for any pending MI_FORCEWAKEs to complete, ignore the > - * timeout returned here until it is root caused. > - */ > intel_engine_stop_cs(engine); > > - fw_pending = __cs_pending_mi_force_wakes(engine); > - if (fw_pending) > - __gpm_wait_for_fw_complete(engine->gt, fw_pending); > + /* > + * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need > + * to wait for any pending mi force wakeups > + */ > + intel_engine_wait_for_pending_mi_fw(engine); > } > > static void guc_reset_nop(struct intel_engine_cs *engine) ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend 2022-05-10 22:14 [Intel-gfx] [PATCH] drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend Nerlige Ramappa, Umesh ` (3 preceding siblings ...) 2022-05-11 15:26 ` [Intel-gfx] [PATCH] " Tvrtko Ursulin @ 2022-06-09 23:51 ` Ceraolo Spurio, Daniele 4 siblings, 0 replies; 6+ messages in thread From: Ceraolo Spurio, Daniele @ 2022-06-09 23:51 UTC (permalink / raw) To: Nerlige Ramappa, Umesh, intel-gfx, Tvrtko Ursulin On 5/10/2022 3:14 PM, Nerlige Ramappa, Umesh wrote: > From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> > > For execlists backend, current implementation of Wa_22011802037 is to > stop the CS before doing a reset of the engine. This WA was further > extended to wait for any pending MI FORCE WAKEUPs before issuing a > reset. Add the extended steps in the execlist path of reset. > > In addition, extend the WA to gen11. > > v2: (Tvrtko) > - Clarify comments, commit message, fix typos > - Use IS_GRAPHICS_VER for gen 11/12 checks > > Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> > Fixes: f6aa0d713c88 ("drm/i915: Add Wa_22011802037 force cs halt") > --- > drivers/gpu/drm/i915/gt/intel_engine.h | 2 + > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 85 ++++++++++++++++++- > .../drm/i915/gt/intel_execlists_submission.c | 7 ++ > .../gpu/drm/i915/gt/intel_ring_submission.c | 7 ++ > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 +- > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 81 ++---------------- > 6 files changed, 107 insertions(+), 79 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h > index 1431f1e9dbee..04e435bce79b 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine.h > +++ b/drivers/gpu/drm/i915/gt/intel_engine.h > @@ -201,6 +201,8 @@ int intel_ring_submission_setup(struct intel_engine_cs *engine); > int intel_engine_stop_cs(struct intel_engine_cs *engine); > void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine); > > +void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine); > + > void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask); > > u64 intel_engine_get_active_head(const struct intel_engine_cs *engine); > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 14c6ddbbfde8..9943cf9655b2 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -1282,10 +1282,10 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine, > intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); > > /* > - * Wa_22011802037 : gen12, Prior to doing a reset, ensure CS is > + * Wa_22011802037 : gen11, gen12, Prior to doing a reset, ensure CS is > * stopped, set ring stop bit and prefetch disable bit to halt CS > */ > - if (GRAPHICS_VER(engine->i915) == 12) > + if (IS_GRAPHICS_VER(engine->i915, 11, 12)) > intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base), > _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE)); > > @@ -1308,6 +1308,18 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine) > return -ENODEV; > > ENGINE_TRACE(engine, "\n"); > + /* > + * TODO: Find out why occasionally stopping the CS times out. Seen > + * especially with gem_eio tests. > + * > + * Occasionally trying to stop the cs times out, but does not adversely > + * affect functionality. The timeout is set as a config parameter that > + * defaults to 100ms. In most cases the follow up operation is to wait > + * for pending MI_FORCE_WAKES. The assumption is that this timeout is > + * sufficient for any pending MI_FORCEWAKEs to complete. Once root > + * caused, the caller must check and handle the return from this > + * function. > + */ > if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) { > ENGINE_TRACE(engine, > "timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n", > @@ -1334,6 +1346,75 @@ void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine) > ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); > } > > +static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine) > +{ > + static const i915_reg_t _reg[I915_NUM_ENGINES] = { > + [RCS0] = MSG_IDLE_CS, > + [BCS0] = MSG_IDLE_BCS, > + [VCS0] = MSG_IDLE_VCS0, > + [VCS1] = MSG_IDLE_VCS1, > + [VCS2] = MSG_IDLE_VCS2, > + [VCS3] = MSG_IDLE_VCS3, > + [VCS4] = MSG_IDLE_VCS4, > + [VCS5] = MSG_IDLE_VCS5, > + [VCS6] = MSG_IDLE_VCS6, > + [VCS7] = MSG_IDLE_VCS7, > + [VECS0] = MSG_IDLE_VECS0, > + [VECS1] = MSG_IDLE_VECS1, > + [VECS2] = MSG_IDLE_VECS2, > + [VECS3] = MSG_IDLE_VECS3, > + [CCS0] = MSG_IDLE_CS, > + [CCS1] = MSG_IDLE_CS, > + [CCS2] = MSG_IDLE_CS, > + [CCS3] = MSG_IDLE_CS, > + }; > + u32 val; > + > + if (!_reg[engine->id].reg) > + return 0; > + > + val = intel_uncore_read(engine->uncore, _reg[engine->id]); > + > + /* bits[29:25] & bits[13:9] >> shift */ > + return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT; > +} > + > +static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask) > +{ > + int ret; > + > + /* Ensure GPM receives fw up/down after CS is stopped */ > + udelay(1); > + > + /* Wait for forcewake request to complete in GPM */ > + ret = __intel_wait_for_register_fw(gt->uncore, > + GEN9_PWRGT_DOMAIN_STATUS, > + fw_mask, fw_mask, 5000, 0, NULL); > + > + /* Ensure CS receives fw ack from GPM */ > + udelay(1); > + > + if (ret) > + GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret); > +} > + > +/* > + * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any > + * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The > + * pending status is indicated by bits[13:9] (masked by bits[29:25]) in the > + * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we > + * are concerned only with the gt reset here, we use a logical OR of pending > + * forcewakeups from all reset domains and then wait for them to complete by > + * querying PWRGT_DOMAIN_STATUS. > + */ > +void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine) > +{ > + u32 fw_pending = __cs_pending_mi_force_wakes(engine); > + > + if (fw_pending) > + __gpm_wait_for_fw_complete(engine->gt, fw_pending); > +} > + > static u32 > read_subslice_reg(const struct intel_engine_cs *engine, > int slice, int subslice, i915_reg_t reg) > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c > index 86f7a9ac1c39..2caa1af77064 100644 > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c > @@ -2958,6 +2958,13 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) > ring_set_paused(engine, 1); > intel_engine_stop_cs(engine); > > + /* > + * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need > + * to wait for any pending mi force wakeups > + */ > + if (IS_GRAPHICS_VER(engine->i915, 11, 12)) > + intel_engine_wait_for_pending_mi_fw(engine); > + > engine->execlists.reset_ccid = active_ccid(engine); > } > > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > index 5423bfd301ad..a7808eff33c5 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > @@ -323,6 +323,13 @@ static void reset_prepare(struct intel_engine_cs *engine) > ENGINE_TRACE(engine, "\n"); > intel_engine_stop_cs(engine); > > + /* > + * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need > + * to wait for any pending mi force wakeups > + */ > + if (IS_GRAPHICS_VER(engine->i915, 11, 12)) > + intel_engine_wait_for_pending_mi_fw(engine); > + Ringbuffer submission is not supported on gen 11 and 12, so no need for this. With this removed: Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Daniele > if (!stop_ring(engine)) { > /* G45 ring initialization often fails to reset head to zero */ > ENGINE_TRACE(engine, > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c > index 2c4ad4a65089..8c6885f43d1a 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c > @@ -310,8 +310,8 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc) > if (IS_DG2(gt->i915)) > flags |= GUC_WA_DUAL_QUEUE; > > - /* Wa_22011802037: graphics version 12 */ > - if (GRAPHICS_VER(gt->i915) == 12) > + /* Wa_22011802037: graphics version 11/12 */ > + if (IS_GRAPHICS_VER(gt->i915, 11, 12)) > flags |= GUC_WA_PRE_PARSER; > > /* Wa_16011777198:dg2 */ > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > index 75291e9846c5..9b21c7345ffd 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > @@ -1527,87 +1527,18 @@ static void guc_reset_state(struct intel_context *ce, u32 head, bool scrub) > lrc_update_regs(ce, engine, head); > } > > -static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine) > -{ > - static const i915_reg_t _reg[I915_NUM_ENGINES] = { > - [RCS0] = MSG_IDLE_CS, > - [BCS0] = MSG_IDLE_BCS, > - [VCS0] = MSG_IDLE_VCS0, > - [VCS1] = MSG_IDLE_VCS1, > - [VCS2] = MSG_IDLE_VCS2, > - [VCS3] = MSG_IDLE_VCS3, > - [VCS4] = MSG_IDLE_VCS4, > - [VCS5] = MSG_IDLE_VCS5, > - [VCS6] = MSG_IDLE_VCS6, > - [VCS7] = MSG_IDLE_VCS7, > - [VECS0] = MSG_IDLE_VECS0, > - [VECS1] = MSG_IDLE_VECS1, > - [VECS2] = MSG_IDLE_VECS2, > - [VECS3] = MSG_IDLE_VECS3, > - [CCS0] = MSG_IDLE_CS, > - [CCS1] = MSG_IDLE_CS, > - [CCS2] = MSG_IDLE_CS, > - [CCS3] = MSG_IDLE_CS, > - }; > - u32 val; > - > - if (!_reg[engine->id].reg) > - return 0; > - > - val = intel_uncore_read(engine->uncore, _reg[engine->id]); > - > - /* bits[29:25] & bits[13:9] >> shift */ > - return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT; > -} > - > -static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask) > -{ > - int ret; > - > - /* Ensure GPM receives fw up/down after CS is stopped */ > - udelay(1); > - > - /* Wait for forcewake request to complete in GPM */ > - ret = __intel_wait_for_register_fw(gt->uncore, > - GEN9_PWRGT_DOMAIN_STATUS, > - fw_mask, fw_mask, 5000, 0, NULL); > - > - /* Ensure CS receives fw ack from GPM */ > - udelay(1); > - > - if (ret) > - GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret); > -} > - > -/* > - * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any > - * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The > - * pending status is indicated by bits[13:9] (masked by bits[ 29:25]) in the > - * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we > - * are concerned only with the gt reset here, we use a logical OR of pending > - * forcewakeups from all reset domains and then wait for them to complete by > - * querying PWRGT_DOMAIN_STATUS. > - */ > static void guc_engine_reset_prepare(struct intel_engine_cs *engine) > { > - u32 fw_pending; > - > - if (GRAPHICS_VER(engine->i915) != 12) > + if (!IS_GRAPHICS_VER(engine->i915, 11, 12)) > return; > > - /* > - * Wa_22011802037 > - * TODO: Occasionally trying to stop the cs times out, but does not > - * adversely affect functionality. The timeout is set as a config > - * parameter that defaults to 100ms. Assuming that this timeout is > - * sufficient for any pending MI_FORCEWAKEs to complete, ignore the > - * timeout returned here until it is root caused. > - */ > intel_engine_stop_cs(engine); > > - fw_pending = __cs_pending_mi_force_wakes(engine); > - if (fw_pending) > - __gpm_wait_for_fw_complete(engine->gt, fw_pending); > + /* > + * Wa_22011802037:gen11/gen12: In addition to stopping the cs, we need > + * to wait for any pending mi force wakeups > + */ > + intel_engine_wait_for_pending_mi_fw(engine); > } > > static void guc_reset_nop(struct intel_engine_cs *engine) ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-06-09 23:51 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-05-10 22:14 [Intel-gfx] [PATCH] drm/i915/reset: Add additional steps for Wa_22011802037 for execlist backend Nerlige Ramappa, Umesh 2022-05-10 22:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork 2022-05-10 22:54 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-05-11 5:03 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2022-05-11 15:26 ` [Intel-gfx] [PATCH] " Tvrtko Ursulin 2022-06-09 23:51 ` Ceraolo Spurio, Daniele
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.