* [Intel-gfx] [PATCH] drm/i915: Enable Tile4 tiling mode
@ 2022-05-12 13:26 Nirmoy Das
2022-05-12 17:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable Tile4 tiling mode (rev2) Patchwork
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Nirmoy Das @ 2022-05-12 13:26 UTC (permalink / raw)
To: intel-gfx; +Cc: krishnaiah.bommu, matthew.auld, chris.p.wilson
From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Enable Tile4 tiling mode on platform that supports
Tile4 but no TileY like DG2.
v2: disable X-tile for iGPU in fastblit
fix checkpath --strict warnings
Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Co-developed-by: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
---
.../i915/gem/selftests/i915_gem_client_blt.c | 235 ++++++++++++++----
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 22 ++
2 files changed, 212 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index ddd0772fd828..e16661029c78 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -6,6 +6,7 @@
#include "i915_selftest.h"
#include "gt/intel_context.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_engine_user.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_gt.h"
@@ -18,10 +19,71 @@
#include "huge_gem_object.h"
#include "mock_context.h"
+#define OW_SIZE 16 /* in bytes */
+#define F_SUBTILE_SIZE 64 /* in bytes */
+#define F_TILE_WIDTH 128 /* in bytes */
+#define F_TILE_HEIGHT 32 /* in pixels */
+#define F_SUBTILE_WIDTH OW_SIZE /* in bytes */
+#define F_SUBTILE_HEIGHT 4 /* in pixels */
+
+static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp)
+{
+ int tile_base;
+ int tile_x, tile_y;
+ int swizzle, subtile;
+ int pixel_size = bpp / 8;
+ int pos;
+
+ /*
+ * Subtile remapping for F tile. Note that map[a]==b implies map[b]==a
+ * so we can use the same table to tile and until.
+ */
+ static const u8 f_subtile_map[] = {
+ 0, 1, 2, 3, 8, 9, 10, 11,
+ 4, 5, 6, 7, 12, 13, 14, 15,
+ 16, 17, 18, 19, 24, 25, 26, 27,
+ 20, 21, 22, 23, 28, 29, 30, 31,
+ 32, 33, 34, 35, 40, 41, 42, 43,
+ 36, 37, 38, 39, 44, 45, 46, 47,
+ 48, 49, 50, 51, 56, 57, 58, 59,
+ 52, 53, 54, 55, 60, 61, 62, 63
+ };
+
+ x *= pixel_size;
+ /*
+ * Where does the 4k tile start (in bytes)? This is the same for Y and
+ * F so we can use the Y-tile algorithm to get to that point.
+ */
+ tile_base =
+ y / F_TILE_HEIGHT * stride * F_TILE_HEIGHT +
+ x / F_TILE_WIDTH * 4096;
+
+ /* Find pixel within tile */
+ tile_x = x % F_TILE_WIDTH;
+ tile_y = y % F_TILE_HEIGHT;
+
+ /* And figure out the subtile within the 4k tile */
+ subtile = tile_y / F_SUBTILE_HEIGHT * 8 + tile_x / F_SUBTILE_WIDTH;
+
+ /* Swizzle the subtile number according to the bspec diagram */
+ swizzle = f_subtile_map[subtile];
+
+ /* Calculate new position */
+ pos = tile_base +
+ swizzle * F_SUBTILE_SIZE +
+ tile_y % F_SUBTILE_HEIGHT * OW_SIZE +
+ tile_x % F_SUBTILE_WIDTH;
+
+ GEM_BUG_ON(!IS_ALIGNED(pos, pixel_size));
+
+ return pos / pixel_size * 4;
+}
+
enum client_tiling {
CLIENT_TILING_LINEAR,
CLIENT_TILING_X,
CLIENT_TILING_Y,
+ CLIENT_TILING_4,
CLIENT_NUM_TILING_TYPES
};
@@ -45,6 +107,21 @@ struct tiled_blits {
u32 height;
};
+static bool fast_blit_ok(struct blit_buffer *buf)
+{
+ int gen = GRAPHICS_VER(buf->vma->vm->i915);
+
+ if (gen < 9)
+ return false;
+
+ if (gen < 12)
+ return true;
+
+ /* filter out platforms with unsupported X-tile support(iGPUs and DG1) in fastblit */
+ return !((IS_DG1(buf->vma->vm->i915) || (gen == 12 && !HAS_LMEM(buf->vma->vm->i915))) &&
+ buf->tiling == CLIENT_TILING_X);
+}
+
static int prepare_blit(const struct tiled_blits *t,
struct blit_buffer *dst,
struct blit_buffer *src,
@@ -59,51 +136,103 @@ static int prepare_blit(const struct tiled_blits *t,
if (IS_ERR(cs))
return PTR_ERR(cs);
- *cs++ = MI_LOAD_REGISTER_IMM(1);
- *cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
- cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
- if (src->tiling == CLIENT_TILING_Y)
- cmd |= BCS_SRC_Y;
- if (dst->tiling == CLIENT_TILING_Y)
- cmd |= BCS_DST_Y;
- *cs++ = cmd;
-
- cmd = MI_FLUSH_DW;
- if (ver >= 8)
- cmd++;
- *cs++ = cmd;
- *cs++ = 0;
- *cs++ = 0;
- *cs++ = 0;
-
- cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2);
- if (ver >= 8)
- cmd += 2;
-
- src_pitch = t->width * 4;
- if (src->tiling) {
- cmd |= XY_SRC_COPY_BLT_SRC_TILED;
- src_pitch /= 4;
- }
+ if (fast_blit_ok(dst) && fast_blit_ok(src)) {
+ struct intel_gt *gt = t->ce->engine->gt;
+ u32 src_tiles = 0, dst_tiles = 0;
+ u32 src_4t = 0, dst_4t = 0;
+
+ /* Need to program BLIT_CCTL if it is not done previously
+ * before using XY_FAST_COPY_BLT
+ */
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base));
+ *cs++ = (BLIT_CCTL_SRC_MOCS(gt->mocs.uc_index) |
+ BLIT_CCTL_DST_MOCS(gt->mocs.uc_index));
+
+ src_pitch = t->width; /* in dwords */
+ if (src->tiling == CLIENT_TILING_4) {
+ src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
+ src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4;
+ } else if (src->tiling == CLIENT_TILING_Y) {
+ src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
+ } else if (src->tiling == CLIENT_TILING_X) {
+ src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X);
+ } else {
+ src_pitch *= 4; /* in bytes */
+ }
- dst_pitch = t->width * 4;
- if (dst->tiling) {
- cmd |= XY_SRC_COPY_BLT_DST_TILED;
- dst_pitch /= 4;
- }
+ dst_pitch = t->width; /* in dwords */
+ if (dst->tiling == CLIENT_TILING_4) {
+ dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
+ dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4;
+ } else if (dst->tiling == CLIENT_TILING_Y) {
+ dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
+ } else if (dst->tiling == CLIENT_TILING_X) {
+ dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X);
+ } else {
+ dst_pitch *= 4; /* in bytes */
+ }
- *cs++ = cmd;
- *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
- *cs++ = 0;
- *cs++ = t->height << 16 | t->width;
- *cs++ = lower_32_bits(dst->vma->node.start);
- if (use_64b_reloc)
+ *cs++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2) |
+ src_tiles | dst_tiles;
+ *cs++ = src_4t | dst_4t | BLT_DEPTH_32 | dst_pitch;
+ *cs++ = 0;
+ *cs++ = t->height << 16 | t->width;
+ *cs++ = lower_32_bits(dst->vma->node.start);
*cs++ = upper_32_bits(dst->vma->node.start);
- *cs++ = 0;
- *cs++ = src_pitch;
- *cs++ = lower_32_bits(src->vma->node.start);
- if (use_64b_reloc)
+ *cs++ = 0;
+ *cs++ = src_pitch;
+ *cs++ = lower_32_bits(src->vma->node.start);
*cs++ = upper_32_bits(src->vma->node.start);
+ } else {
+ if (ver >= 6) {
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
+ cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
+ if (src->tiling == CLIENT_TILING_Y)
+ cmd |= BCS_SRC_Y;
+ if (dst->tiling == CLIENT_TILING_Y)
+ cmd |= BCS_DST_Y;
+ *cs++ = cmd;
+
+ cmd = MI_FLUSH_DW;
+ if (ver >= 8)
+ cmd++;
+ *cs++ = cmd;
+ *cs++ = 0;
+ *cs++ = 0;
+ *cs++ = 0;
+ }
+
+ cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2);
+ if (ver >= 8)
+ cmd += 2;
+
+ src_pitch = t->width * 4;
+ if (src->tiling) {
+ cmd |= XY_SRC_COPY_BLT_SRC_TILED;
+ src_pitch /= 4;
+ }
+
+ dst_pitch = t->width * 4;
+ if (dst->tiling) {
+ cmd |= XY_SRC_COPY_BLT_DST_TILED;
+ dst_pitch /= 4;
+ }
+
+ *cs++ = cmd;
+ *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
+ *cs++ = 0;
+ *cs++ = t->height << 16 | t->width;
+ *cs++ = lower_32_bits(dst->vma->node.start);
+ if (use_64b_reloc)
+ *cs++ = upper_32_bits(dst->vma->node.start);
+ *cs++ = 0;
+ *cs++ = src_pitch;
+ *cs++ = lower_32_bits(src->vma->node.start);
+ if (use_64b_reloc)
+ *cs++ = upper_32_bits(src->vma->node.start);
+ }
*cs++ = MI_BATCH_BUFFER_END;
@@ -181,7 +310,13 @@ static int tiled_blits_create_buffers(struct tiled_blits *t,
t->buffers[i].vma = vma;
t->buffers[i].tiling =
- i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng);
+ i915_prandom_u32_max_state(CLIENT_NUM_TILING_TYPES, prng);
+
+ /* Platforms support either TileY or Tile4, not both */
+ if (HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_Y)
+ t->buffers[i].tiling = CLIENT_TILING_4;
+ else if (!HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_4)
+ t->buffers[i].tiling = CLIENT_TILING_Y;
}
return 0;
@@ -206,7 +341,8 @@ static u64 swizzle_bit(unsigned int bit, u64 offset)
static u64 tiled_offset(const struct intel_gt *gt,
u64 v,
unsigned int stride,
- enum client_tiling tiling)
+ enum client_tiling tiling,
+ int x_pos, int y_pos)
{
unsigned int swizzle;
u64 x, y;
@@ -216,7 +352,12 @@ static u64 tiled_offset(const struct intel_gt *gt,
y = div64_u64_rem(v, stride, &x);
- if (tiling == CLIENT_TILING_X) {
+ if (tiling == CLIENT_TILING_4) {
+ v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32);
+
+ /* no swizzling for f-tiling */
+ swizzle = I915_BIT_6_SWIZZLE_NONE;
+ } else if (tiling == CLIENT_TILING_X) {
v = div64_u64_rem(y, 8, &y) * stride * 8;
v += y * 512;
v += div64_u64_rem(x, 512, &x) << 12;
@@ -259,6 +400,7 @@ static const char *repr_tiling(enum client_tiling tiling)
case CLIENT_TILING_LINEAR: return "linear";
case CLIENT_TILING_X: return "X";
case CLIENT_TILING_Y: return "Y";
+ case CLIENT_TILING_4: return "F";
default: return "unknown";
}
}
@@ -284,7 +426,7 @@ static int verify_buffer(const struct tiled_blits *t,
} else {
u64 v = tiled_offset(buf->vma->vm->gt,
p * 4, t->width * 4,
- buf->tiling);
+ buf->tiling, x, y);
if (vaddr[v / sizeof(*vaddr)] != buf->start_val + p)
ret = -EINVAL;
@@ -504,6 +646,9 @@ static int tiled_blits_bounce(struct tiled_blits *t, struct rnd_state *prng)
if (err)
return err;
+ /* Simulating GTT eviction of the same buffer / layout */
+ t->buffers[2].tiling = t->buffers[0].tiling;
+
/* Reposition so that we overlap the old addresses, and slightly off */
err = tiled_blit(t,
&t->buffers[2], t->hole + t->align,
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 556bca3be804..246ab8f7bf57 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -236,6 +236,28 @@
#define XY_FAST_COLOR_BLT_DW 16
#define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21)
#define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31
+
+#define XY_FAST_COPY_BLT_D0_SRC_TILING_MASK REG_GENMASK(21, 20)
+#define XY_FAST_COPY_BLT_D0_DST_TILING_MASK REG_GENMASK(14, 13)
+#define XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(mode) \
+ REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_SRC_TILING_MASK, mode)
+#define XY_FAST_COPY_BLT_D0_DST_TILE_MODE(mode) \
+ REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_DST_TILING_MASK, mode)
+#define LINEAR 0
+#define TILE_X 0x1
+#define XMAJOR 0x1
+#define YMAJOR 0x2
+#define TILE_64 0x3
+#define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31)
+#define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30)
+#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
+#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
+/* Note: MOCS value = (index << 1) */
+#define BLIT_CCTL_SRC_MOCS(idx) \
+ REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (idx) << 1)
+#define BLIT_CCTL_DST_MOCS(idx) \
+ REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (idx) << 1)
+
#define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22)
#define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22)
#define XY_SRC_COPY_BLT_CMD (2 << 29 | 0x53 << 22)
--
2.35.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable Tile4 tiling mode (rev2)
2022-05-12 13:26 [Intel-gfx] [PATCH] drm/i915: Enable Tile4 tiling mode Nirmoy Das
@ 2022-05-12 17:23 ` Patchwork
2022-05-12 21:03 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-05-13 5:47 ` [Intel-gfx] [PATCH] drm/i915: Enable Tile4 tiling mode Zbigniew Kempczyński
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2022-05-12 17:23 UTC (permalink / raw)
To: Nirmoy Das; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 7425 bytes --]
== Series Details ==
Series: drm/i915: Enable Tile4 tiling mode (rev2)
URL : https://patchwork.freedesktop.org/series/103881/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11643 -> Patchwork_103881v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/index.html
Participating hosts (42 -> 40)
------------------------------
Additional (1): fi-kbl-soraka
Missing (3): fi-bsw-cyan bat-dg2-9 fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_103881v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +9 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][4] ([i915#1886])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [PASS][5] -> [INCOMPLETE][6] ([i915#3921])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510: [PASS][7] -> [DMESG-FAIL][8] ([i915#4528])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/fi-pnv-d510/igt@i915_selftest@live@requests.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/fi-pnv-d510/igt@i915_selftest@live@requests.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-bsw-nick: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/fi-bsw-nick/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +7 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/fi-kbl-soraka/igt@kms_chamelium@dp-edid-read.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#533])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-bsw-nick: NOTRUN -> [SKIP][12] ([fdo#109271])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/fi-bsw-nick/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@runner@aborted:
- fi-pnv-d510: NOTRUN -> [FAIL][13] ([fdo#109271] / [i915#2403] / [i915#4312])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/fi-pnv-d510/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-bsw-nick: [INCOMPLETE][14] ([i915#5801] / [i915#5847]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/fi-bsw-nick/igt@i915_selftest@live@execlists.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/fi-bsw-nick/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gtt:
- fi-bdw-5557u: [DMESG-FAIL][16] ([i915#3674]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/fi-bdw-5557u/igt@i915_selftest@live@gtt.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/fi-bdw-5557u/igt@i915_selftest@live@gtt.html
* igt@i915_selftest@live@hangcheck:
- {fi-jsl-1}: [INCOMPLETE][18] ([i915#3921] / [i915#5153]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/fi-jsl-1/igt@i915_selftest@live@hangcheck.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/fi-jsl-1/igt@i915_selftest@live@hangcheck.html
* igt@kms_busy@basic@modeset:
- bat-adlp-4: [DMESG-WARN][20] ([i915#3576]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/bat-adlp-4/igt@kms_busy@basic@modeset.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/bat-adlp-4/igt@kms_busy@basic@modeset.html
#### Warnings ####
* igt@kms_busy@basic@flip:
- bat-adlp-4: [DMESG-WARN][22] ([i915#3576]) -> [DMESG-WARN][23] ([i915#1982] / [i915#3576])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/bat-adlp-4/igt@kms_busy@basic@flip.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/bat-adlp-4/igt@kms_busy@basic@flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3674]: https://gitlab.freedesktop.org/drm/intel/issues/3674
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
[i915#5801]: https://gitlab.freedesktop.org/drm/intel/issues/5801
[i915#5847]: https://gitlab.freedesktop.org/drm/intel/issues/5847
[i915#5879]: https://gitlab.freedesktop.org/drm/intel/issues/5879
Build changes
-------------
* Linux: CI_DRM_11643 -> Patchwork_103881v2
CI-20190529: 20190529
CI_DRM_11643: 9133f71f560b3f78abf58425950e6a818cc3210d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6471: 1d6816f1200520f936a799b7b0ef2e6f396abb16 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103881v2: 9133f71f560b3f78abf58425950e6a818cc3210d @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
4d710747b8f8 drm/i915: Enable Tile4 tiling mode
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/index.html
[-- Attachment #2: Type: text/html, Size: 8880 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Enable Tile4 tiling mode (rev2)
2022-05-12 13:26 [Intel-gfx] [PATCH] drm/i915: Enable Tile4 tiling mode Nirmoy Das
2022-05-12 17:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable Tile4 tiling mode (rev2) Patchwork
@ 2022-05-12 21:03 ` Patchwork
2022-05-13 5:47 ` [Intel-gfx] [PATCH] drm/i915: Enable Tile4 tiling mode Zbigniew Kempczyński
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2022-05-12 21:03 UTC (permalink / raw)
To: Nirmoy Das; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 28215 bytes --]
== Series Details ==
Series: drm/i915: Enable Tile4 tiling mode (rev2)
URL : https://patchwork.freedesktop.org/series/103881/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11643_full -> Patchwork_103881v2_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_103881v2_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-kbl: NOTRUN -> [DMESG-WARN][1] ([i915#4991])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-kbl3/igt@gem_create@create-massive.html
* igt@gem_eio@in-flight-10ms:
- shard-skl: [PASS][2] -> [TIMEOUT][3] ([i915#3063])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-skl10/igt@gem_eio@in-flight-10ms.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-skl7/igt@gem_eio@in-flight-10ms.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][4] -> [FAIL][5] ([i915#2846])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-glk1/igt@gem_exec_fair@basic-deadline.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-glk5/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2842])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [PASS][8] -> [FAIL][9] ([i915#2842])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-apl4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-apl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][10] ([i915#2842]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-glk8/igt@gem_exec_fair@basic-pace@vecs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-glk7/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_flush@basic-wb-rw-before-default:
- shard-snb: [PASS][13] -> [SKIP][14] ([fdo#109271])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-snb7/igt@gem_exec_flush@basic-wb-rw-before-default.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-snb6/igt@gem_exec_flush@basic-wb-rw-before-default.html
* igt@gem_exec_whisper@basic-queues-all:
- shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#118])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-glk4/igt@gem_exec_whisper@basic-queues-all.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-glk4/igt@gem_exec_whisper@basic-queues-all.html
* igt@gem_lmem_swapping@random:
- shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-kbl1/igt@gem_lmem_swapping@random.html
* igt@gem_pwrite@basic-exhaustion:
- shard-kbl: NOTRUN -> [WARN][18] ([i915#2658])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-kbl3/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_pxp@fail-invalid-protected-context:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#4270])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-iclb2/igt@gem_pxp@fail-invalid-protected-context.html
* igt@gem_softpin@noreloc-s3:
- shard-skl: [PASS][20] -> [INCOMPLETE][21] ([i915#4939] / [i915#5230])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-skl2/igt@gem_softpin@noreloc-s3.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-skl10/igt@gem_softpin@noreloc-s3.html
* igt@gen7_exec_parse@basic-rejected:
- shard-iclb: NOTRUN -> [SKIP][22] ([fdo#109289])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-iclb8/igt@gen7_exec_parse@basic-rejected.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][23] ([i915#5286]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-iclb8/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
- shard-iclb: NOTRUN -> [SKIP][24] ([fdo#110723]) +1 similar issue
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-iclb8/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#3886])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-apl8/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3886]) +1 similar issue
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-kbl3/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@hdmi-mode-timings:
- shard-apl: NOTRUN -> [SKIP][27] ([fdo#109271] / [fdo#111827]) +4 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-apl3/igt@kms_chamelium@hdmi-mode-timings.html
* igt@kms_color_chamelium@pipe-a-ctm-negative:
- shard-kbl: NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111827]) +4 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-kbl3/igt@kms_color_chamelium@pipe-a-ctm-negative.html
* igt@kms_color_chamelium@pipe-b-ctm-0-25:
- shard-iclb: NOTRUN -> [SKIP][29] ([fdo#109284] / [fdo#111827])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-iclb8/igt@kms_color_chamelium@pipe-b-ctm-0-25.html
* igt@kms_content_protection@legacy:
- shard-kbl: NOTRUN -> [TIMEOUT][30] ([i915#1319])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-kbl7/igt@kms_content_protection@legacy.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][31] -> [DMESG-WARN][32] ([i915#180]) +4 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-d-cursor-64x21-onscreen:
- shard-iclb: NOTRUN -> [SKIP][33] ([fdo#109278])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-iclb2/igt@kms_cursor_crc@pipe-d-cursor-64x21-onscreen.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][34] -> [FAIL][35] ([i915#2346])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
- shard-iclb: [PASS][36] -> [FAIL][37] ([i915#2346])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-iclb3/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][38] -> [FAIL][39] ([i915#79])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-apl: [PASS][40] -> [DMESG-WARN][41] ([i915#180]) +3 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [PASS][42] -> [FAIL][43] ([i915#2122])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-skl4/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
- shard-glk: [PASS][44] -> [FAIL][45] ([i915#4911])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-glk7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-iclb: NOTRUN -> [SKIP][46] ([fdo#109280]) +1 similar issue
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-msflip-blt:
- shard-kbl: NOTRUN -> [SKIP][47] ([fdo#109271]) +78 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-kbl1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
- shard-apl: NOTRUN -> [SKIP][48] ([fdo#109271]) +47 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-apl6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html
* igt@kms_hdr@bpc-switch@bpc-switch-edp-1-pipe-a:
- shard-skl: [PASS][49] -> [FAIL][50] ([i915#1188])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-skl4/igt@kms_hdr@bpc-switch@bpc-switch-edp-1-pipe-a.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-skl2/igt@kms_hdr@bpc-switch@bpc-switch-edp-1-pipe-a.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#533])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-apl8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-kbl: NOTRUN -> [DMESG-WARN][52] ([i915#180])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][53] ([i915#265])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-apl8/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-kbl: NOTRUN -> [FAIL][54] ([fdo#108145] / [i915#265]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-kbl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-apl: [PASS][55] -> [FAIL][56] ([fdo#108145] / [i915#265])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-apl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-apl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale:
- shard-iclb: [PASS][57] -> [SKIP][58] ([i915#5235]) +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-iclb7/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
* igt@kms_psr2_su@page_flip-p010:
- shard-apl: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#658])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-apl6/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [PASS][60] -> [SKIP][61] ([fdo#109441])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-iclb1/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_scaling_modes@scaling-mode-none@edp-1-pipe-c:
- shard-iclb: NOTRUN -> [SKIP][62] ([i915#5030]) +2 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-iclb8/igt@kms_scaling_modes@scaling-mode-none@edp-1-pipe-c.html
* igt@perf@polling-small-buf:
- shard-skl: [PASS][63] -> [FAIL][64] ([i915#1722])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-skl8/igt@perf@polling-small-buf.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-skl6/igt@perf@polling-small-buf.html
* igt@sysfs_heartbeat_interval@mixed@vcs0:
- shard-skl: [PASS][65] -> [WARN][66] ([i915#4055])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-skl9/igt@sysfs_heartbeat_interval@mixed@vcs0.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-skl1/igt@sysfs_heartbeat_interval@mixed@vcs0.html
* igt@sysfs_heartbeat_interval@mixed@vecs0:
- shard-skl: [PASS][67] -> [FAIL][68] ([i915#1731])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-skl9/igt@sysfs_heartbeat_interval@mixed@vecs0.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-skl1/igt@sysfs_heartbeat_interval@mixed@vecs0.html
#### Possible fixes ####
* igt@gem_eio@unwedge-stress:
- {shard-tglu}: [TIMEOUT][69] ([i915#3063]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-tglu-4/igt@gem_eio@unwedge-stress.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-tglu-8/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: [FAIL][71] ([i915#2842]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-apl7/igt@gem_exec_fair@basic-none@vcs0.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-apl3/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][73] ([i915#2849]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-iclb4/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_flush@basic-uc-ro-default:
- shard-snb: [SKIP][75] ([fdo#109271]) -> [PASS][76] +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-snb6/igt@gem_exec_flush@basic-uc-ro-default.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-snb4/igt@gem_exec_flush@basic-uc-ro-default.html
* igt@gem_exec_whisper@basic-contexts-priority:
- shard-iclb: [INCOMPLETE][77] -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-iclb7/igt@gem_exec_whisper@basic-contexts-priority.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-iclb2/igt@gem_exec_whisper@basic-contexts-priority.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-glk: [SKIP][79] ([fdo#109271]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-glk3/igt@i915_suspend@fence-restore-tiled2untiled.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-glk5/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [DMESG-WARN][81] ([i915#180]) -> [PASS][82] +2 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-apl4/igt@i915_suspend@sysfs-reader.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-apl6/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [DMESG-WARN][83] ([i915#180]) -> [PASS][84] +3 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_flip@plain-flip-fb-recreate@b-edp1:
- shard-skl: [FAIL][85] ([i915#2122]) -> [PASS][86] +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-skl1/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-skl6/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
- shard-glk: [FAIL][87] ([i915#4911]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-glk7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][89] ([fdo#108145] / [i915#265]) -> [PASS][90] +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [SKIP][91] ([fdo#109441]) -> [PASS][92] +2 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-iclb7/igt@kms_psr@psr2_sprite_mmap_gtt.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-iclb: [SKIP][93] ([i915#5519]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-iclb5/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-iclb7/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
#### Warnings ####
* igt@gem_exec_balancer@parallel:
- shard-iclb: [DMESG-WARN][95] ([i915#5614]) -> [SKIP][96] ([i915#4525])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-iclb1/igt@gem_exec_balancer@parallel.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-iclb8/igt@gem_exec_balancer@parallel.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [SKIP][97] ([i915#4525]) -> [DMESG-WARN][98] ([i915#5614]) +2 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-iclb5/igt@gem_exec_balancer@parallel-out-fence.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-iclb4/igt@gem_exec_balancer@parallel-out-fence.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-kbl: [INCOMPLETE][99] ([i915#3614]) -> [DMESG-WARN][100] ([i915#180])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][101] ([fdo#111068] / [i915#658]) -> [SKIP][102] ([i915#2920])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-iclb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-iclb: [FAIL][103] ([i915#5939]) -> [SKIP][104] ([fdo#109642] / [fdo#111068] / [i915#658])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-iclb2/igt@kms_psr2_su@page_flip-nv12.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-iclb1/igt@kms_psr2_su@page_flip-nv12.html
* igt@runner@aborted:
- shard-apl: ([FAIL][105], [FAIL][106], [FAIL][107], [FAIL][108], [FAIL][109], [FAIL][110], [FAIL][111], [FAIL][112], [FAIL][113]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-apl4/igt@runner@aborted.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-apl6/igt@runner@aborted.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-apl3/igt@runner@aborted.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-apl1/igt@runner@aborted.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-apl1/igt@runner@aborted.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-apl7/igt@runner@aborted.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-apl1/igt@runner@aborted.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-apl3/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11643/shard-apl7/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-apl2/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-apl2/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-apl4/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-apl8/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-apl4/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-apl4/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-apl1/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/shard-apl7/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3614]: https://gitlab.freedesktop.org/drm/intel/issues/3614
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4055]: https://gitlab.freedesktop.org/drm/intel/issues/4055
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4911]: https://gitlab.freedesktop.org/drm/intel/issues/4911
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5030]: https://gitlab.freedesktop.org/drm/intel/issues/5030
[i915#5230]: https://gitlab.freedesktop.org/drm/intel/issues/5230
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5614]: https://gitlab.freedesktop.org/drm/intel/issues/5614
[i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_11643 -> Patchwork_103881v2
CI-20190529: 20190529
CI_DRM_11643: 9133f71f560b3f78abf58425950e6a818cc3210d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6471: 1d6816f1200520f936a799b7b0ef2e6f396abb16 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103881v2: 9133f71f560b3f78abf58425950e6a818cc3210d @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v2/index.html
[-- Attachment #2: Type: text/html, Size: 33732 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Enable Tile4 tiling mode
2022-05-12 13:26 [Intel-gfx] [PATCH] drm/i915: Enable Tile4 tiling mode Nirmoy Das
2022-05-12 17:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable Tile4 tiling mode (rev2) Patchwork
2022-05-12 21:03 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2022-05-13 5:47 ` Zbigniew Kempczyński
2022-05-13 7:50 ` Das, Nirmoy
2 siblings, 1 reply; 5+ messages in thread
From: Zbigniew Kempczyński @ 2022-05-13 5:47 UTC (permalink / raw)
To: Nirmoy Das; +Cc: krishnaiah.bommu, intel-gfx, matthew.auld, chris.p.wilson
On Thu, May 12, 2022 at 03:26:00PM +0200, Nirmoy Das wrote:
> From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>
> Enable Tile4 tiling mode on platform that supports
> Tile4 but no TileY like DG2.
>
> v2: disable X-tile for iGPU in fastblit
> fix checkpath --strict warnings
>
> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Co-developed-by: Nirmoy Das <nirmoy.das@intel.com>
> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
> .../i915/gem/selftests/i915_gem_client_blt.c | 235 ++++++++++++++----
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 22 ++
> 2 files changed, 212 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> index ddd0772fd828..e16661029c78 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> @@ -6,6 +6,7 @@
> #include "i915_selftest.h"
>
> #include "gt/intel_context.h"
> +#include "gt/intel_engine_regs.h"
> #include "gt/intel_engine_user.h"
> #include "gt/intel_gpu_commands.h"
> #include "gt/intel_gt.h"
> @@ -18,10 +19,71 @@
> #include "huge_gem_object.h"
> #include "mock_context.h"
>
> +#define OW_SIZE 16 /* in bytes */
> +#define F_SUBTILE_SIZE 64 /* in bytes */
> +#define F_TILE_WIDTH 128 /* in bytes */
> +#define F_TILE_HEIGHT 32 /* in pixels */
> +#define F_SUBTILE_WIDTH OW_SIZE /* in bytes */
> +#define F_SUBTILE_HEIGHT 4 /* in pixels */
> +
> +static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp)
> +{
> + int tile_base;
> + int tile_x, tile_y;
> + int swizzle, subtile;
> + int pixel_size = bpp / 8;
> + int pos;
> +
> + /*
> + * Subtile remapping for F tile. Note that map[a]==b implies map[b]==a
> + * so we can use the same table to tile and until.
> + */
> + static const u8 f_subtile_map[] = {
> + 0, 1, 2, 3, 8, 9, 10, 11,
> + 4, 5, 6, 7, 12, 13, 14, 15,
> + 16, 17, 18, 19, 24, 25, 26, 27,
> + 20, 21, 22, 23, 28, 29, 30, 31,
> + 32, 33, 34, 35, 40, 41, 42, 43,
> + 36, 37, 38, 39, 44, 45, 46, 47,
> + 48, 49, 50, 51, 56, 57, 58, 59,
> + 52, 53, 54, 55, 60, 61, 62, 63
> + };
> +
> + x *= pixel_size;
> + /*
> + * Where does the 4k tile start (in bytes)? This is the same for Y and
> + * F so we can use the Y-tile algorithm to get to that point.
> + */
> + tile_base =
> + y / F_TILE_HEIGHT * stride * F_TILE_HEIGHT +
> + x / F_TILE_WIDTH * 4096;
> +
> + /* Find pixel within tile */
> + tile_x = x % F_TILE_WIDTH;
> + tile_y = y % F_TILE_HEIGHT;
> +
> + /* And figure out the subtile within the 4k tile */
> + subtile = tile_y / F_SUBTILE_HEIGHT * 8 + tile_x / F_SUBTILE_WIDTH;
> +
> + /* Swizzle the subtile number according to the bspec diagram */
> + swizzle = f_subtile_map[subtile];
> +
> + /* Calculate new position */
> + pos = tile_base +
> + swizzle * F_SUBTILE_SIZE +
> + tile_y % F_SUBTILE_HEIGHT * OW_SIZE +
> + tile_x % F_SUBTILE_WIDTH;
> +
> + GEM_BUG_ON(!IS_ALIGNED(pos, pixel_size));
> +
> + return pos / pixel_size * 4;
> +}
> +
> enum client_tiling {
> CLIENT_TILING_LINEAR,
> CLIENT_TILING_X,
> CLIENT_TILING_Y,
> + CLIENT_TILING_4,
> CLIENT_NUM_TILING_TYPES
> };
>
> @@ -45,6 +107,21 @@ struct tiled_blits {
> u32 height;
> };
>
> +static bool fast_blit_ok(struct blit_buffer *buf)
> +{
> + int gen = GRAPHICS_VER(buf->vma->vm->i915);
> +
> + if (gen < 9)
> + return false;
> +
> + if (gen < 12)
> + return true;
> +
> + /* filter out platforms with unsupported X-tile support(iGPUs and DG1) in fastblit */
> + return !((IS_DG1(buf->vma->vm->i915) || (gen == 12 && !HAS_LMEM(buf->vma->vm->i915))) &&
> + buf->tiling == CLIENT_TILING_X);
> +}
> +
What would you say for this:
static bool supports_x_tiling(const struct drm_i915_private *i915)
{
int gen = GRAPHICS_VER(i915);
if (gen < 12)
return true;
if (!HAS_LMEM(i915) || IS_DG1(i915))
return false;
return true;
}
static bool fast_blit_ok(const struct blit_buffer *buf)
{
int gen = GRAPHICS_VER(buf->vma->vm->i915);
if (gen < 9)
return false;
if (gen < 12)
return true;
/* filter out platforms with unsupported X-tile support in fastblit */
if (buf->tiling == CLIENT_TILING_X && !supports_x_tiling(buf->vma->vm->i915))
return false;
return true;
}
Rest code looks good to me.
--
Zbigniew
> static int prepare_blit(const struct tiled_blits *t,
> struct blit_buffer *dst,
> struct blit_buffer *src,
> @@ -59,51 +136,103 @@ static int prepare_blit(const struct tiled_blits *t,
> if (IS_ERR(cs))
> return PTR_ERR(cs);
>
> - *cs++ = MI_LOAD_REGISTER_IMM(1);
> - *cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
> - cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
> - if (src->tiling == CLIENT_TILING_Y)
> - cmd |= BCS_SRC_Y;
> - if (dst->tiling == CLIENT_TILING_Y)
> - cmd |= BCS_DST_Y;
> - *cs++ = cmd;
> -
> - cmd = MI_FLUSH_DW;
> - if (ver >= 8)
> - cmd++;
> - *cs++ = cmd;
> - *cs++ = 0;
> - *cs++ = 0;
> - *cs++ = 0;
> -
> - cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2);
> - if (ver >= 8)
> - cmd += 2;
> -
> - src_pitch = t->width * 4;
> - if (src->tiling) {
> - cmd |= XY_SRC_COPY_BLT_SRC_TILED;
> - src_pitch /= 4;
> - }
> + if (fast_blit_ok(dst) && fast_blit_ok(src)) {
> + struct intel_gt *gt = t->ce->engine->gt;
> + u32 src_tiles = 0, dst_tiles = 0;
> + u32 src_4t = 0, dst_4t = 0;
> +
> + /* Need to program BLIT_CCTL if it is not done previously
> + * before using XY_FAST_COPY_BLT
> + */
> + *cs++ = MI_LOAD_REGISTER_IMM(1);
> + *cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base));
> + *cs++ = (BLIT_CCTL_SRC_MOCS(gt->mocs.uc_index) |
> + BLIT_CCTL_DST_MOCS(gt->mocs.uc_index));
> +
> + src_pitch = t->width; /* in dwords */
> + if (src->tiling == CLIENT_TILING_4) {
> + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
> + src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4;
> + } else if (src->tiling == CLIENT_TILING_Y) {
> + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
> + } else if (src->tiling == CLIENT_TILING_X) {
> + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X);
> + } else {
> + src_pitch *= 4; /* in bytes */
> + }
>
> - dst_pitch = t->width * 4;
> - if (dst->tiling) {
> - cmd |= XY_SRC_COPY_BLT_DST_TILED;
> - dst_pitch /= 4;
> - }
> + dst_pitch = t->width; /* in dwords */
> + if (dst->tiling == CLIENT_TILING_4) {
> + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
> + dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4;
> + } else if (dst->tiling == CLIENT_TILING_Y) {
> + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
> + } else if (dst->tiling == CLIENT_TILING_X) {
> + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X);
> + } else {
> + dst_pitch *= 4; /* in bytes */
> + }
>
> - *cs++ = cmd;
> - *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
> - *cs++ = 0;
> - *cs++ = t->height << 16 | t->width;
> - *cs++ = lower_32_bits(dst->vma->node.start);
> - if (use_64b_reloc)
> + *cs++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2) |
> + src_tiles | dst_tiles;
> + *cs++ = src_4t | dst_4t | BLT_DEPTH_32 | dst_pitch;
> + *cs++ = 0;
> + *cs++ = t->height << 16 | t->width;
> + *cs++ = lower_32_bits(dst->vma->node.start);
> *cs++ = upper_32_bits(dst->vma->node.start);
> - *cs++ = 0;
> - *cs++ = src_pitch;
> - *cs++ = lower_32_bits(src->vma->node.start);
> - if (use_64b_reloc)
> + *cs++ = 0;
> + *cs++ = src_pitch;
> + *cs++ = lower_32_bits(src->vma->node.start);
> *cs++ = upper_32_bits(src->vma->node.start);
> + } else {
> + if (ver >= 6) {
> + *cs++ = MI_LOAD_REGISTER_IMM(1);
> + *cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
> + cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
> + if (src->tiling == CLIENT_TILING_Y)
> + cmd |= BCS_SRC_Y;
> + if (dst->tiling == CLIENT_TILING_Y)
> + cmd |= BCS_DST_Y;
> + *cs++ = cmd;
> +
> + cmd = MI_FLUSH_DW;
> + if (ver >= 8)
> + cmd++;
> + *cs++ = cmd;
> + *cs++ = 0;
> + *cs++ = 0;
> + *cs++ = 0;
> + }
> +
> + cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2);
> + if (ver >= 8)
> + cmd += 2;
> +
> + src_pitch = t->width * 4;
> + if (src->tiling) {
> + cmd |= XY_SRC_COPY_BLT_SRC_TILED;
> + src_pitch /= 4;
> + }
> +
> + dst_pitch = t->width * 4;
> + if (dst->tiling) {
> + cmd |= XY_SRC_COPY_BLT_DST_TILED;
> + dst_pitch /= 4;
> + }
> +
> + *cs++ = cmd;
> + *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
> + *cs++ = 0;
> + *cs++ = t->height << 16 | t->width;
> + *cs++ = lower_32_bits(dst->vma->node.start);
> + if (use_64b_reloc)
> + *cs++ = upper_32_bits(dst->vma->node.start);
> + *cs++ = 0;
> + *cs++ = src_pitch;
> + *cs++ = lower_32_bits(src->vma->node.start);
> + if (use_64b_reloc)
> + *cs++ = upper_32_bits(src->vma->node.start);
> + }
>
> *cs++ = MI_BATCH_BUFFER_END;
>
> @@ -181,7 +310,13 @@ static int tiled_blits_create_buffers(struct tiled_blits *t,
>
> t->buffers[i].vma = vma;
> t->buffers[i].tiling =
> - i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng);
> + i915_prandom_u32_max_state(CLIENT_NUM_TILING_TYPES, prng);
> +
> + /* Platforms support either TileY or Tile4, not both */
> + if (HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_Y)
> + t->buffers[i].tiling = CLIENT_TILING_4;
> + else if (!HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_4)
> + t->buffers[i].tiling = CLIENT_TILING_Y;
> }
>
> return 0;
> @@ -206,7 +341,8 @@ static u64 swizzle_bit(unsigned int bit, u64 offset)
> static u64 tiled_offset(const struct intel_gt *gt,
> u64 v,
> unsigned int stride,
> - enum client_tiling tiling)
> + enum client_tiling tiling,
> + int x_pos, int y_pos)
> {
> unsigned int swizzle;
> u64 x, y;
> @@ -216,7 +352,12 @@ static u64 tiled_offset(const struct intel_gt *gt,
>
> y = div64_u64_rem(v, stride, &x);
>
> - if (tiling == CLIENT_TILING_X) {
> + if (tiling == CLIENT_TILING_4) {
> + v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32);
> +
> + /* no swizzling for f-tiling */
> + swizzle = I915_BIT_6_SWIZZLE_NONE;
> + } else if (tiling == CLIENT_TILING_X) {
> v = div64_u64_rem(y, 8, &y) * stride * 8;
> v += y * 512;
> v += div64_u64_rem(x, 512, &x) << 12;
> @@ -259,6 +400,7 @@ static const char *repr_tiling(enum client_tiling tiling)
> case CLIENT_TILING_LINEAR: return "linear";
> case CLIENT_TILING_X: return "X";
> case CLIENT_TILING_Y: return "Y";
> + case CLIENT_TILING_4: return "F";
> default: return "unknown";
> }
> }
> @@ -284,7 +426,7 @@ static int verify_buffer(const struct tiled_blits *t,
> } else {
> u64 v = tiled_offset(buf->vma->vm->gt,
> p * 4, t->width * 4,
> - buf->tiling);
> + buf->tiling, x, y);
>
> if (vaddr[v / sizeof(*vaddr)] != buf->start_val + p)
> ret = -EINVAL;
> @@ -504,6 +646,9 @@ static int tiled_blits_bounce(struct tiled_blits *t, struct rnd_state *prng)
> if (err)
> return err;
>
> + /* Simulating GTT eviction of the same buffer / layout */
> + t->buffers[2].tiling = t->buffers[0].tiling;
> +
> /* Reposition so that we overlap the old addresses, and slightly off */
> err = tiled_blit(t,
> &t->buffers[2], t->hole + t->align,
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index 556bca3be804..246ab8f7bf57 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -236,6 +236,28 @@
> #define XY_FAST_COLOR_BLT_DW 16
> #define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21)
> #define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31
> +
> +#define XY_FAST_COPY_BLT_D0_SRC_TILING_MASK REG_GENMASK(21, 20)
> +#define XY_FAST_COPY_BLT_D0_DST_TILING_MASK REG_GENMASK(14, 13)
> +#define XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(mode) \
> + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_SRC_TILING_MASK, mode)
> +#define XY_FAST_COPY_BLT_D0_DST_TILE_MODE(mode) \
> + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_DST_TILING_MASK, mode)
> +#define LINEAR 0
> +#define TILE_X 0x1
> +#define XMAJOR 0x1
> +#define YMAJOR 0x2
> +#define TILE_64 0x3
> +#define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31)
> +#define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30)
> +#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
> +#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
> +/* Note: MOCS value = (index << 1) */
> +#define BLIT_CCTL_SRC_MOCS(idx) \
> + REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (idx) << 1)
> +#define BLIT_CCTL_DST_MOCS(idx) \
> + REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (idx) << 1)
> +
> #define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22)
> #define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22)
> #define XY_SRC_COPY_BLT_CMD (2 << 29 | 0x53 << 22)
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Enable Tile4 tiling mode
2022-05-13 5:47 ` [Intel-gfx] [PATCH] drm/i915: Enable Tile4 tiling mode Zbigniew Kempczyński
@ 2022-05-13 7:50 ` Das, Nirmoy
0 siblings, 0 replies; 5+ messages in thread
From: Das, Nirmoy @ 2022-05-13 7:50 UTC (permalink / raw)
To: Zbigniew Kempczyński
Cc: krishnaiah.bommu, intel-gfx, matthew.auld, chris.p.wilson
On 5/13/2022 7:47 AM, Zbigniew Kempczyński wrote:
> On Thu, May 12, 2022 at 03:26:00PM +0200, Nirmoy Das wrote:
>> From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>>
>> Enable Tile4 tiling mode on platform that supports
>> Tile4 but no TileY like DG2.
>>
>> v2: disable X-tile for iGPU in fastblit
>> fix checkpath --strict warnings
>>
>> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>> Co-developed-by: Nirmoy Das <nirmoy.das@intel.com>
>> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
>> ---
>> .../i915/gem/selftests/i915_gem_client_blt.c | 235 ++++++++++++++----
>> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 22 ++
>> 2 files changed, 212 insertions(+), 45 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
>> index ddd0772fd828..e16661029c78 100644
>> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
>> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
>> @@ -6,6 +6,7 @@
>> #include "i915_selftest.h"
>>
>> #include "gt/intel_context.h"
>> +#include "gt/intel_engine_regs.h"
>> #include "gt/intel_engine_user.h"
>> #include "gt/intel_gpu_commands.h"
>> #include "gt/intel_gt.h"
>> @@ -18,10 +19,71 @@
>> #include "huge_gem_object.h"
>> #include "mock_context.h"
>>
>> +#define OW_SIZE 16 /* in bytes */
>> +#define F_SUBTILE_SIZE 64 /* in bytes */
>> +#define F_TILE_WIDTH 128 /* in bytes */
>> +#define F_TILE_HEIGHT 32 /* in pixels */
>> +#define F_SUBTILE_WIDTH OW_SIZE /* in bytes */
>> +#define F_SUBTILE_HEIGHT 4 /* in pixels */
>> +
>> +static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp)
>> +{
>> + int tile_base;
>> + int tile_x, tile_y;
>> + int swizzle, subtile;
>> + int pixel_size = bpp / 8;
>> + int pos;
>> +
>> + /*
>> + * Subtile remapping for F tile. Note that map[a]==b implies map[b]==a
>> + * so we can use the same table to tile and until.
>> + */
>> + static const u8 f_subtile_map[] = {
>> + 0, 1, 2, 3, 8, 9, 10, 11,
>> + 4, 5, 6, 7, 12, 13, 14, 15,
>> + 16, 17, 18, 19, 24, 25, 26, 27,
>> + 20, 21, 22, 23, 28, 29, 30, 31,
>> + 32, 33, 34, 35, 40, 41, 42, 43,
>> + 36, 37, 38, 39, 44, 45, 46, 47,
>> + 48, 49, 50, 51, 56, 57, 58, 59,
>> + 52, 53, 54, 55, 60, 61, 62, 63
>> + };
>> +
>> + x *= pixel_size;
>> + /*
>> + * Where does the 4k tile start (in bytes)? This is the same for Y and
>> + * F so we can use the Y-tile algorithm to get to that point.
>> + */
>> + tile_base =
>> + y / F_TILE_HEIGHT * stride * F_TILE_HEIGHT +
>> + x / F_TILE_WIDTH * 4096;
>> +
>> + /* Find pixel within tile */
>> + tile_x = x % F_TILE_WIDTH;
>> + tile_y = y % F_TILE_HEIGHT;
>> +
>> + /* And figure out the subtile within the 4k tile */
>> + subtile = tile_y / F_SUBTILE_HEIGHT * 8 + tile_x / F_SUBTILE_WIDTH;
>> +
>> + /* Swizzle the subtile number according to the bspec diagram */
>> + swizzle = f_subtile_map[subtile];
>> +
>> + /* Calculate new position */
>> + pos = tile_base +
>> + swizzle * F_SUBTILE_SIZE +
>> + tile_y % F_SUBTILE_HEIGHT * OW_SIZE +
>> + tile_x % F_SUBTILE_WIDTH;
>> +
>> + GEM_BUG_ON(!IS_ALIGNED(pos, pixel_size));
>> +
>> + return pos / pixel_size * 4;
>> +}
>> +
>> enum client_tiling {
>> CLIENT_TILING_LINEAR,
>> CLIENT_TILING_X,
>> CLIENT_TILING_Y,
>> + CLIENT_TILING_4,
>> CLIENT_NUM_TILING_TYPES
>> };
>>
>> @@ -45,6 +107,21 @@ struct tiled_blits {
>> u32 height;
>> };
>>
>> +static bool fast_blit_ok(struct blit_buffer *buf)
>> +{
>> + int gen = GRAPHICS_VER(buf->vma->vm->i915);
>> +
>> + if (gen < 9)
>> + return false;
>> +
>> + if (gen < 12)
>> + return true;
>> +
>> + /* filter out platforms with unsupported X-tile support(iGPUs and DG1) in fastblit */
>> + return !((IS_DG1(buf->vma->vm->i915) || (gen == 12 && !HAS_LMEM(buf->vma->vm->i915))) &&
>> + buf->tiling == CLIENT_TILING_X);
>> +}
>> +
> What would you say for this:
>
> static bool supports_x_tiling(const struct drm_i915_private *i915)
> {
> int gen = GRAPHICS_VER(i915);
>
> if (gen < 12)
> return true;
>
> if (!HAS_LMEM(i915) || IS_DG1(i915))
> return false;
>
> return true;
> }
>
> static bool fast_blit_ok(const struct blit_buffer *buf)
> {
> int gen = GRAPHICS_VER(buf->vma->vm->i915);
>
> if (gen < 9)
> return false;
>
> if (gen < 12)
> return true;
>
> /* filter out platforms with unsupported X-tile support in fastblit */
> if (buf->tiling == CLIENT_TILING_X && !supports_x_tiling(buf->vma->vm->i915))
> return false;
>
> return true;
> }
Looks better, I resend with that.
Thanks,
Nirmoy
>
> Rest code looks good to me.
>
> --
> Zbigniew
>
>> static int prepare_blit(const struct tiled_blits *t,
>> struct blit_buffer *dst,
>> struct blit_buffer *src,
>> @@ -59,51 +136,103 @@ static int prepare_blit(const struct tiled_blits *t,
>> if (IS_ERR(cs))
>> return PTR_ERR(cs);
>>
>> - *cs++ = MI_LOAD_REGISTER_IMM(1);
>> - *cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
>> - cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
>> - if (src->tiling == CLIENT_TILING_Y)
>> - cmd |= BCS_SRC_Y;
>> - if (dst->tiling == CLIENT_TILING_Y)
>> - cmd |= BCS_DST_Y;
>> - *cs++ = cmd;
>> -
>> - cmd = MI_FLUSH_DW;
>> - if (ver >= 8)
>> - cmd++;
>> - *cs++ = cmd;
>> - *cs++ = 0;
>> - *cs++ = 0;
>> - *cs++ = 0;
>> -
>> - cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2);
>> - if (ver >= 8)
>> - cmd += 2;
>> -
>> - src_pitch = t->width * 4;
>> - if (src->tiling) {
>> - cmd |= XY_SRC_COPY_BLT_SRC_TILED;
>> - src_pitch /= 4;
>> - }
>> + if (fast_blit_ok(dst) && fast_blit_ok(src)) {
>> + struct intel_gt *gt = t->ce->engine->gt;
>> + u32 src_tiles = 0, dst_tiles = 0;
>> + u32 src_4t = 0, dst_4t = 0;
>> +
>> + /* Need to program BLIT_CCTL if it is not done previously
>> + * before using XY_FAST_COPY_BLT
>> + */
>> + *cs++ = MI_LOAD_REGISTER_IMM(1);
>> + *cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base));
>> + *cs++ = (BLIT_CCTL_SRC_MOCS(gt->mocs.uc_index) |
>> + BLIT_CCTL_DST_MOCS(gt->mocs.uc_index));
>> +
>> + src_pitch = t->width; /* in dwords */
>> + if (src->tiling == CLIENT_TILING_4) {
>> + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
>> + src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4;
>> + } else if (src->tiling == CLIENT_TILING_Y) {
>> + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
>> + } else if (src->tiling == CLIENT_TILING_X) {
>> + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X);
>> + } else {
>> + src_pitch *= 4; /* in bytes */
>> + }
>>
>> - dst_pitch = t->width * 4;
>> - if (dst->tiling) {
>> - cmd |= XY_SRC_COPY_BLT_DST_TILED;
>> - dst_pitch /= 4;
>> - }
>> + dst_pitch = t->width; /* in dwords */
>> + if (dst->tiling == CLIENT_TILING_4) {
>> + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
>> + dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4;
>> + } else if (dst->tiling == CLIENT_TILING_Y) {
>> + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
>> + } else if (dst->tiling == CLIENT_TILING_X) {
>> + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X);
>> + } else {
>> + dst_pitch *= 4; /* in bytes */
>> + }
>>
>> - *cs++ = cmd;
>> - *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
>> - *cs++ = 0;
>> - *cs++ = t->height << 16 | t->width;
>> - *cs++ = lower_32_bits(dst->vma->node.start);
>> - if (use_64b_reloc)
>> + *cs++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2) |
>> + src_tiles | dst_tiles;
>> + *cs++ = src_4t | dst_4t | BLT_DEPTH_32 | dst_pitch;
>> + *cs++ = 0;
>> + *cs++ = t->height << 16 | t->width;
>> + *cs++ = lower_32_bits(dst->vma->node.start);
>> *cs++ = upper_32_bits(dst->vma->node.start);
>> - *cs++ = 0;
>> - *cs++ = src_pitch;
>> - *cs++ = lower_32_bits(src->vma->node.start);
>> - if (use_64b_reloc)
>> + *cs++ = 0;
>> + *cs++ = src_pitch;
>> + *cs++ = lower_32_bits(src->vma->node.start);
>> *cs++ = upper_32_bits(src->vma->node.start);
>> + } else {
>> + if (ver >= 6) {
>> + *cs++ = MI_LOAD_REGISTER_IMM(1);
>> + *cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
>> + cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
>> + if (src->tiling == CLIENT_TILING_Y)
>> + cmd |= BCS_SRC_Y;
>> + if (dst->tiling == CLIENT_TILING_Y)
>> + cmd |= BCS_DST_Y;
>> + *cs++ = cmd;
>> +
>> + cmd = MI_FLUSH_DW;
>> + if (ver >= 8)
>> + cmd++;
>> + *cs++ = cmd;
>> + *cs++ = 0;
>> + *cs++ = 0;
>> + *cs++ = 0;
>> + }
>> +
>> + cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2);
>> + if (ver >= 8)
>> + cmd += 2;
>> +
>> + src_pitch = t->width * 4;
>> + if (src->tiling) {
>> + cmd |= XY_SRC_COPY_BLT_SRC_TILED;
>> + src_pitch /= 4;
>> + }
>> +
>> + dst_pitch = t->width * 4;
>> + if (dst->tiling) {
>> + cmd |= XY_SRC_COPY_BLT_DST_TILED;
>> + dst_pitch /= 4;
>> + }
>> +
>> + *cs++ = cmd;
>> + *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
>> + *cs++ = 0;
>> + *cs++ = t->height << 16 | t->width;
>> + *cs++ = lower_32_bits(dst->vma->node.start);
>> + if (use_64b_reloc)
>> + *cs++ = upper_32_bits(dst->vma->node.start);
>> + *cs++ = 0;
>> + *cs++ = src_pitch;
>> + *cs++ = lower_32_bits(src->vma->node.start);
>> + if (use_64b_reloc)
>> + *cs++ = upper_32_bits(src->vma->node.start);
>> + }
>>
>> *cs++ = MI_BATCH_BUFFER_END;
>>
>> @@ -181,7 +310,13 @@ static int tiled_blits_create_buffers(struct tiled_blits *t,
>>
>> t->buffers[i].vma = vma;
>> t->buffers[i].tiling =
>> - i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng);
>> + i915_prandom_u32_max_state(CLIENT_NUM_TILING_TYPES, prng);
>> +
>> + /* Platforms support either TileY or Tile4, not both */
>> + if (HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_Y)
>> + t->buffers[i].tiling = CLIENT_TILING_4;
>> + else if (!HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_4)
>> + t->buffers[i].tiling = CLIENT_TILING_Y;
>> }
>>
>> return 0;
>> @@ -206,7 +341,8 @@ static u64 swizzle_bit(unsigned int bit, u64 offset)
>> static u64 tiled_offset(const struct intel_gt *gt,
>> u64 v,
>> unsigned int stride,
>> - enum client_tiling tiling)
>> + enum client_tiling tiling,
>> + int x_pos, int y_pos)
>> {
>> unsigned int swizzle;
>> u64 x, y;
>> @@ -216,7 +352,12 @@ static u64 tiled_offset(const struct intel_gt *gt,
>>
>> y = div64_u64_rem(v, stride, &x);
>>
>> - if (tiling == CLIENT_TILING_X) {
>> + if (tiling == CLIENT_TILING_4) {
>> + v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32);
>> +
>> + /* no swizzling for f-tiling */
>> + swizzle = I915_BIT_6_SWIZZLE_NONE;
>> + } else if (tiling == CLIENT_TILING_X) {
>> v = div64_u64_rem(y, 8, &y) * stride * 8;
>> v += y * 512;
>> v += div64_u64_rem(x, 512, &x) << 12;
>> @@ -259,6 +400,7 @@ static const char *repr_tiling(enum client_tiling tiling)
>> case CLIENT_TILING_LINEAR: return "linear";
>> case CLIENT_TILING_X: return "X";
>> case CLIENT_TILING_Y: return "Y";
>> + case CLIENT_TILING_4: return "F";
>> default: return "unknown";
>> }
>> }
>> @@ -284,7 +426,7 @@ static int verify_buffer(const struct tiled_blits *t,
>> } else {
>> u64 v = tiled_offset(buf->vma->vm->gt,
>> p * 4, t->width * 4,
>> - buf->tiling);
>> + buf->tiling, x, y);
>>
>> if (vaddr[v / sizeof(*vaddr)] != buf->start_val + p)
>> ret = -EINVAL;
>> @@ -504,6 +646,9 @@ static int tiled_blits_bounce(struct tiled_blits *t, struct rnd_state *prng)
>> if (err)
>> return err;
>>
>> + /* Simulating GTT eviction of the same buffer / layout */
>> + t->buffers[2].tiling = t->buffers[0].tiling;
>> +
>> /* Reposition so that we overlap the old addresses, and slightly off */
>> err = tiled_blit(t,
>> &t->buffers[2], t->hole + t->align,
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
>> index 556bca3be804..246ab8f7bf57 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
>> @@ -236,6 +236,28 @@
>> #define XY_FAST_COLOR_BLT_DW 16
>> #define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21)
>> #define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31
>> +
>> +#define XY_FAST_COPY_BLT_D0_SRC_TILING_MASK REG_GENMASK(21, 20)
>> +#define XY_FAST_COPY_BLT_D0_DST_TILING_MASK REG_GENMASK(14, 13)
>> +#define XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(mode) \
>> + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_SRC_TILING_MASK, mode)
>> +#define XY_FAST_COPY_BLT_D0_DST_TILE_MODE(mode) \
>> + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_DST_TILING_MASK, mode)
>> +#define LINEAR 0
>> +#define TILE_X 0x1
>> +#define XMAJOR 0x1
>> +#define YMAJOR 0x2
>> +#define TILE_64 0x3
>> +#define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31)
>> +#define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30)
>> +#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
>> +#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
>> +/* Note: MOCS value = (index << 1) */
>> +#define BLIT_CCTL_SRC_MOCS(idx) \
>> + REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (idx) << 1)
>> +#define BLIT_CCTL_DST_MOCS(idx) \
>> + REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (idx) << 1)
>> +
>> #define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22)
>> #define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22)
>> #define XY_SRC_COPY_BLT_CMD (2 << 29 | 0x53 << 22)
>> --
>> 2.35.1
>>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-05-13 7:50 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-12 13:26 [Intel-gfx] [PATCH] drm/i915: Enable Tile4 tiling mode Nirmoy Das
2022-05-12 17:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable Tile4 tiling mode (rev2) Patchwork
2022-05-12 21:03 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-05-13 5:47 ` [Intel-gfx] [PATCH] drm/i915: Enable Tile4 tiling mode Zbigniew Kempczyński
2022-05-13 7:50 ` Das, Nirmoy
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