[PATCH v1 0/6] Cleanups and enablement for Quartz64-A

[PATCH v1 0/6] Cleanups and enablement for Quartz64-A

[Peter Geis]

Good Morning,

The following patches clean up some dtbs_check warnings, fixup the
Quartz64-A dts, and enable some additional functionality on the
Quartz64-A.

With this series the only remaining dtbs_check warnings are due to
unconverted bindings.

Patch 6 is dependent on:
13e0ee34f39c arm64: dts: rockchip: add rk356x sfc support
currently in linux-next.


Patches 1 and 2 add some missing bindings to the rk3568 cru.
Patch 3 renames the bluetooth gpios on Quartz64-A.
Patch 4 adds the fan gpio pinctrl on Quartz64-A.
Patch 5 enables sdr-104 on Quartz64-A.
Patch 6 adds the disabled by default sfc controller to Quartz64-A.

Peter Geis (6):
  dt-binding: clock: Add missing rk3568 cru bindings
  arm64: dts: rockchip: add clocks to rk356x cru
  arm64: dts: rockchip: rename Quartz64-A bluetooth gpios
  arm64: dts: rockchip: add Quartz64-A fan pinctrl
  arm64: dts: rockchip: enable sdr-104 on sdmmc
  arm64: dts: rockchip: enable sfc controller on Quartz64 Model A

 .../bindings/clock/rockchip,rk3568-cru.yaml   | 13 +++++++++
 .../boot/dts/rockchip/rk3566-quartz64-a.dts   | 29 +++++++++++++++++--
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      |  2 ++
 3 files changed, 42 insertions(+), 2 deletions(-)

-- 
2.25.1

[PATCH v1 0/6] Cleanups and enablement for Quartz64-A

[Peter Geis]

Good Morning,

The following patches clean up some dtbs_check warnings, fixup the
Quartz64-A dts, and enable some additional functionality on the
Quartz64-A.

With this series the only remaining dtbs_check warnings are due to
unconverted bindings.

Patch 6 is dependent on:
13e0ee34f39c arm64: dts: rockchip: add rk356x sfc support
currently in linux-next.


Patches 1 and 2 add some missing bindings to the rk3568 cru.
Patch 3 renames the bluetooth gpios on Quartz64-A.
Patch 4 adds the fan gpio pinctrl on Quartz64-A.
Patch 5 enables sdr-104 on Quartz64-A.
Patch 6 adds the disabled by default sfc controller to Quartz64-A.

Peter Geis (6):
  dt-binding: clock: Add missing rk3568 cru bindings
  arm64: dts: rockchip: add clocks to rk356x cru
  arm64: dts: rockchip: rename Quartz64-A bluetooth gpios
  arm64: dts: rockchip: add Quartz64-A fan pinctrl
  arm64: dts: rockchip: enable sdr-104 on sdmmc
  arm64: dts: rockchip: enable sfc controller on Quartz64 Model A

 .../bindings/clock/rockchip,rk3568-cru.yaml   | 13 +++++++++
 .../boot/dts/rockchip/rk3566-quartz64-a.dts   | 29 +++++++++++++++++--
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      |  2 ++
 3 files changed, 42 insertions(+), 2 deletions(-)

-- 
2.25.1


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http://lists.infradead.org/mailman/listinfo/linux-rockchip

[PATCH v1 0/6] Cleanups and enablement for Quartz64-A

[Peter Geis]

Good Morning,

The following patches clean up some dtbs_check warnings, fixup the
Quartz64-A dts, and enable some additional functionality on the
Quartz64-A.

With this series the only remaining dtbs_check warnings are due to
unconverted bindings.

Patch 6 is dependent on:
13e0ee34f39c arm64: dts: rockchip: add rk356x sfc support
currently in linux-next.


Patches 1 and 2 add some missing bindings to the rk3568 cru.
Patch 3 renames the bluetooth gpios on Quartz64-A.
Patch 4 adds the fan gpio pinctrl on Quartz64-A.
Patch 5 enables sdr-104 on Quartz64-A.
Patch 6 adds the disabled by default sfc controller to Quartz64-A.

Peter Geis (6):
  dt-binding: clock: Add missing rk3568 cru bindings
  arm64: dts: rockchip: add clocks to rk356x cru
  arm64: dts: rockchip: rename Quartz64-A bluetooth gpios
  arm64: dts: rockchip: add Quartz64-A fan pinctrl
  arm64: dts: rockchip: enable sdr-104 on sdmmc
  arm64: dts: rockchip: enable sfc controller on Quartz64 Model A

 .../bindings/clock/rockchip,rk3568-cru.yaml   | 13 +++++++++
 .../boot/dts/rockchip/rk3566-quartz64-a.dts   | 29 +++++++++++++++++--
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      |  2 ++
 3 files changed, 42 insertions(+), 2 deletions(-)

-- 
2.25.1


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v1 1/6] dt-binding: clock: Add missing rk3568 cru bindings

[Peter Geis]

The rk3568 cru requires a clock input and a phandle to the grf node. Add
these bindings to clear some dtbs_check warnings.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 .../bindings/clock/rockchip,rk3568-cru.yaml         | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
index b2c26097827f..fc7546f521c5 100644
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
@@ -34,6 +34,19 @@ properties:
   "#reset-cells":
     const: 1
 
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: xin24m
+
+  rockchip,grf:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Phandle to the syscon managing the "general register files" (GRF),
+      if missing pll rates are not changeable, due to the missing pll
+      lock status.
+
 required:
   - compatible
   - reg
-- 
2.25.1

[PATCH v1 1/6] dt-binding: clock: Add missing rk3568 cru bindings

[Peter Geis]

The rk3568 cru requires a clock input and a phandle to the grf node. Add
these bindings to clear some dtbs_check warnings.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 .../bindings/clock/rockchip,rk3568-cru.yaml         | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
index b2c26097827f..fc7546f521c5 100644
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
@@ -34,6 +34,19 @@ properties:
   "#reset-cells":
     const: 1
 
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: xin24m
+
+  rockchip,grf:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Phandle to the syscon managing the "general register files" (GRF),
+      if missing pll rates are not changeable, due to the missing pll
+      lock status.
+
 required:
   - compatible
   - reg
-- 
2.25.1


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http://lists.infradead.org/mailman/listinfo/linux-rockchip

[PATCH v1 1/6] dt-binding: clock: Add missing rk3568 cru bindings

[Peter Geis]

The rk3568 cru requires a clock input and a phandle to the grf node. Add
these bindings to clear some dtbs_check warnings.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 .../bindings/clock/rockchip,rk3568-cru.yaml         | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
index b2c26097827f..fc7546f521c5 100644
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml
@@ -34,6 +34,19 @@ properties:
   "#reset-cells":
     const: 1
 
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: xin24m
+
+  rockchip,grf:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Phandle to the syscon managing the "general register files" (GRF),
+      if missing pll rates are not changeable, due to the missing pll
+      lock status.
+
 required:
   - compatible
   - reg
-- 
2.25.1


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v1 2/6] arm64: dts: rockchip: add clocks to rk356x cru

[Peter Geis]

The rk356x cru requires a 24m clock input to function. Add the clocks
properties to the cru to clear some dtbs_check warnings.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 7cdef800cb3c..fd9e8a854328 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -336,6 +336,8 @@ pmucru: clock-controller@fdd00000 {
 	cru: clock-controller@fdd20000 {
 		compatible = "rockchip,rk3568-cru";
 		reg = <0x0 0xfdd20000 0x0 0x1000>;
+		clocks = <&xin24m>;
+		clock-names = "xin24m";
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 		assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
-- 
2.25.1

[PATCH v1 2/6] arm64: dts: rockchip: add clocks to rk356x cru

[Peter Geis]

The rk356x cru requires a 24m clock input to function. Add the clocks
properties to the cru to clear some dtbs_check warnings.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 7cdef800cb3c..fd9e8a854328 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -336,6 +336,8 @@ pmucru: clock-controller@fdd00000 {
 	cru: clock-controller@fdd20000 {
 		compatible = "rockchip,rk3568-cru";
 		reg = <0x0 0xfdd20000 0x0 0x1000>;
+		clocks = <&xin24m>;
+		clock-names = "xin24m";
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 		assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
-- 
2.25.1


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v1 2/6] arm64: dts: rockchip: add clocks to rk356x cru

[Peter Geis]

The rk356x cru requires a 24m clock input to function. Add the clocks
properties to the cru to clear some dtbs_check warnings.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 7cdef800cb3c..fd9e8a854328 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -336,6 +336,8 @@ pmucru: clock-controller@fdd00000 {
 	cru: clock-controller@fdd20000 {
 		compatible = "rockchip,rk3568-cru";
 		reg = <0x0 0xfdd20000 0x0 0x1000>;
+		clocks = <&xin24m>;
+		clock-names = "xin24m";
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 		assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
-- 
2.25.1


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[PATCH v1 3/6] arm64: dts: rockchip: rename Quartz64-A bluetooth gpios

[Peter Geis]

The bluetooth binding for the Quartz64 Model A has incorrectly named
host-wakeup and device-wakeup gpios. Rename them to clear some dtbs_check
warnings.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index dd7f4b9b686b..ca0b92795d95 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -638,8 +638,8 @@ bluetooth {
 		compatible = "brcm,bcm43438-bt";
 		clocks = <&rk817 1>;
 		clock-names = "lpo";
-		device-wake-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
-		host-wake-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+		device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
 		shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
-- 
2.25.1

[PATCH v1 3/6] arm64: dts: rockchip: rename Quartz64-A bluetooth gpios

[Peter Geis]

The bluetooth binding for the Quartz64 Model A has incorrectly named
host-wakeup and device-wakeup gpios. Rename them to clear some dtbs_check
warnings.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index dd7f4b9b686b..ca0b92795d95 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -638,8 +638,8 @@ bluetooth {
 		compatible = "brcm,bcm43438-bt";
 		clocks = <&rk817 1>;
 		clock-names = "lpo";
-		device-wake-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
-		host-wake-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+		device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
 		shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
-- 
2.25.1


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[PATCH v1 3/6] arm64: dts: rockchip: rename Quartz64-A bluetooth gpios

[Peter Geis]

The bluetooth binding for the Quartz64 Model A has incorrectly named
host-wakeup and device-wakeup gpios. Rename them to clear some dtbs_check
warnings.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index dd7f4b9b686b..ca0b92795d95 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -638,8 +638,8 @@ bluetooth {
 		compatible = "brcm,bcm43438-bt";
 		clocks = <&rk817 1>;
 		clock-names = "lpo";
-		device-wake-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
-		host-wake-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+		device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
 		shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
-- 
2.25.1


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[PATCH v1 4/6] arm64: dts: rockchip: add Quartz64-A fan pinctrl

[Peter Geis]

The Quartz64 Model A fan is bound to a single gpio. Prevent pinctrl
issues in the future by binding the pinctrl assignment for the gpio.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index ca0b92795d95..991b7b1b8443 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -32,6 +32,8 @@ fan: gpio_fan {
 		gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
 		gpio-fan,speed-map = <0    0
 				      4500 1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&fan_en_h>;
 		#cooling-cells = <2>;
 	};
 
@@ -510,6 +512,12 @@ bt_wake_l: bt-wake-l {
 		};
 	};
 
+	fan {
+		fan_en_h: fan-en-h {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	leds {
 		work_led_enable_h: work-led-enable-h {
 			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
-- 
2.25.1

[PATCH v1 4/6] arm64: dts: rockchip: add Quartz64-A fan pinctrl

[Peter Geis]

The Quartz64 Model A fan is bound to a single gpio. Prevent pinctrl
issues in the future by binding the pinctrl assignment for the gpio.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index ca0b92795d95..991b7b1b8443 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -32,6 +32,8 @@ fan: gpio_fan {
 		gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
 		gpio-fan,speed-map = <0    0
 				      4500 1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&fan_en_h>;
 		#cooling-cells = <2>;
 	};
 
@@ -510,6 +512,12 @@ bt_wake_l: bt-wake-l {
 		};
 	};
 
+	fan {
+		fan_en_h: fan-en-h {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	leds {
 		work_led_enable_h: work-led-enable-h {
 			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
-- 
2.25.1


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[PATCH v1 4/6] arm64: dts: rockchip: add Quartz64-A fan pinctrl

[Peter Geis]

The Quartz64 Model A fan is bound to a single gpio. Prevent pinctrl
issues in the future by binding the pinctrl assignment for the gpio.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index ca0b92795d95..991b7b1b8443 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -32,6 +32,8 @@ fan: gpio_fan {
 		gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
 		gpio-fan,speed-map = <0    0
 				      4500 1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&fan_en_h>;
 		#cooling-cells = <2>;
 	};
 
@@ -510,6 +512,12 @@ bt_wake_l: bt-wake-l {
 		};
 	};
 
+	fan {
+		fan_en_h: fan-en-h {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	leds {
 		work_led_enable_h: work-led-enable-h {
 			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
-- 
2.25.1


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[PATCH v1 5/6] arm64: dts: rockchip: enable sdr-104 on sdmmc

[Peter Geis]

Now that we have working io-domain support, we can enable higher date
rates on the sdmmc card.

Before:
Timing buffered disk reads:  68 MB in  3.08 seconds =  22.07 MB/sec

After:
Timing buffered disk reads: 188 MB in  3.02 seconds =  62.29 MB/sec

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index 991b7b1b8443..71df64655de5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -582,6 +582,7 @@ &sdmmc0 {
 	disable-wp;
 	pinctrl-names = "default";
 	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	sd-uhs-sdr104;
 	vmmc-supply = <&vcc3v3_sd>;
 	vqmmc-supply = <&vccio_sd>;
 	status = "okay";
-- 
2.25.1

[PATCH v1 5/6] arm64: dts: rockchip: enable sdr-104 on sdmmc

[Peter Geis]

Now that we have working io-domain support, we can enable higher date
rates on the sdmmc card.

Before:
Timing buffered disk reads:  68 MB in  3.08 seconds =  22.07 MB/sec

After:
Timing buffered disk reads: 188 MB in  3.02 seconds =  62.29 MB/sec

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index 991b7b1b8443..71df64655de5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -582,6 +582,7 @@ &sdmmc0 {
 	disable-wp;
 	pinctrl-names = "default";
 	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	sd-uhs-sdr104;
 	vmmc-supply = <&vcc3v3_sd>;
 	vqmmc-supply = <&vccio_sd>;
 	status = "okay";
-- 
2.25.1


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[PATCH v1 5/6] arm64: dts: rockchip: enable sdr-104 on sdmmc

[Peter Geis]

Now that we have working io-domain support, we can enable higher date
rates on the sdmmc card.

Before:
Timing buffered disk reads:  68 MB in  3.08 seconds =  22.07 MB/sec

After:
Timing buffered disk reads: 188 MB in  3.02 seconds =  62.29 MB/sec

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index 991b7b1b8443..71df64655de5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -582,6 +582,7 @@ &sdmmc0 {
 	disable-wp;
 	pinctrl-names = "default";
 	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	sd-uhs-sdr104;
 	vmmc-supply = <&vcc3v3_sd>;
 	vqmmc-supply = <&vccio_sd>;
 	status = "okay";
-- 
2.25.1


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[PATCH v1 6/6] arm64: dts: rockchip: enable sfc controller on Quartz64 Model A

[Peter Geis]

Add the sfc controller binding for the Quartz64 Model A. This is not
populated by default, so leave it disabled.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 .../boot/dts/rockchip/rk3566-quartz64-a.dts      | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index 71df64655de5..6ec349e7e521 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -603,6 +603,22 @@ &sdmmc1 {
 	status = "okay";
 };
 
+&sfc {
+	pinctrl-0 = <&fspi_pins>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "disabled";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <24000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
 /* spdif is exposed on con40 pin 18 */
 &spdif {
 	status = "okay";
-- 
2.25.1

[PATCH v1 6/6] arm64: dts: rockchip: enable sfc controller on Quartz64 Model A

[Peter Geis]

Add the sfc controller binding for the Quartz64 Model A. This is not
populated by default, so leave it disabled.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 .../boot/dts/rockchip/rk3566-quartz64-a.dts      | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index 71df64655de5..6ec349e7e521 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -603,6 +603,22 @@ &sdmmc1 {
 	status = "okay";
 };
 
+&sfc {
+	pinctrl-0 = <&fspi_pins>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "disabled";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <24000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
 /* spdif is exposed on con40 pin 18 */
 &spdif {
 	status = "okay";
-- 
2.25.1


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[PATCH v1 6/6] arm64: dts: rockchip: enable sfc controller on Quartz64 Model A

[Peter Geis]

Add the sfc controller binding for the Quartz64 Model A. This is not
populated by default, so leave it disabled.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 .../boot/dts/rockchip/rk3566-quartz64-a.dts      | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index 71df64655de5..6ec349e7e521 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -603,6 +603,22 @@ &sdmmc1 {
 	status = "okay";
 };
 
+&sfc {
+	pinctrl-0 = <&fspi_pins>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "disabled";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <24000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
 /* spdif is exposed on con40 pin 18 */
 &spdif {
 	status = "okay";
-- 
2.25.1


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Re: [PATCH v1 1/6] dt-binding: clock: Add missing rk3568 cru bindings

[Krzysztof Kozlowski]

On 11/05/2022 17:01, Peter Geis wrote:
> The rk3568 cru requires a clock input and a phandle to the grf node. Add
> these bindings to clear some dtbs_check warnings.
> 
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> ---
>  .../bindings/clock/rockchip,rk3568-cru.yaml         | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

Re: [PATCH v1 1/6] dt-binding: clock: Add missing rk3568 cru bindings

[Krzysztof Kozlowski]

On 11/05/2022 17:01, Peter Geis wrote:
> The rk3568 cru requires a clock input and a phandle to the grf node. Add
> these bindings to clear some dtbs_check warnings.
> 
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> ---
>  .../bindings/clock/rockchip,rk3568-cru.yaml         | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

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Re: [PATCH v1 1/6] dt-binding: clock: Add missing rk3568 cru bindings

[Krzysztof Kozlowski]

On 11/05/2022 17:01, Peter Geis wrote:
> The rk3568 cru requires a clock input and a phandle to the grf node. Add
> these bindings to clear some dtbs_check warnings.
> 
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> ---
>  .../bindings/clock/rockchip,rk3568-cru.yaml         | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

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Re: [PATCH v1 0/6] Cleanups and enablement for Quartz64-A

[Heiko Stuebner]

On Wed, 11 May 2022 11:01:11 -0400, Peter Geis wrote:
> Good Morning,
> 
> The following patches clean up some dtbs_check warnings, fixup the
> Quartz64-A dts, and enable some additional functionality on the
> Quartz64-A.
> 
> With this series the only remaining dtbs_check warnings are due to
> unconverted bindings.
> 
> [...]

Applied, thanks!

[1/6] dt-binding: clock: Add missing rk3568 cru bindings
      commit: b21445db9818ccb9fa1c0ba81fd3705eb8d347e3
[2/6] arm64: dts: rockchip: add clocks to rk356x cru
      commit: 70f679ad25d5f8d0076e283bd6c61e047c7af226
[3/6] arm64: dts: rockchip: rename Quartz64-A bluetooth gpios
      commit: 650a1523756bb1e697f8927d2915cbbb92e83f8c
[4/6] arm64: dts: rockchip: add Quartz64-A fan pinctrl
      commit: 82f4f0183e5d3b2d0a2af6c70ba16f86b5897ef9
[5/6] arm64: dts: rockchip: enable sdr-104 on sdmmc
      commit: 6adce30701c810e11685911ca2114fbc0107120d
[6/6] arm64: dts: rockchip: enable sfc controller on Quartz64 Model A
      commit: e5008be69a1947d4236ab3f73c939f9c2a9a6f80

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

Re: [PATCH v1 0/6] Cleanups and enablement for Quartz64-A

[Heiko Stuebner]

On Wed, 11 May 2022 11:01:11 -0400, Peter Geis wrote:
> Good Morning,
> 
> The following patches clean up some dtbs_check warnings, fixup the
> Quartz64-A dts, and enable some additional functionality on the
> Quartz64-A.
> 
> With this series the only remaining dtbs_check warnings are due to
> unconverted bindings.
> 
> [...]

Applied, thanks!

[1/6] dt-binding: clock: Add missing rk3568 cru bindings
      commit: b21445db9818ccb9fa1c0ba81fd3705eb8d347e3
[2/6] arm64: dts: rockchip: add clocks to rk356x cru
      commit: 70f679ad25d5f8d0076e283bd6c61e047c7af226
[3/6] arm64: dts: rockchip: rename Quartz64-A bluetooth gpios
      commit: 650a1523756bb1e697f8927d2915cbbb92e83f8c
[4/6] arm64: dts: rockchip: add Quartz64-A fan pinctrl
      commit: 82f4f0183e5d3b2d0a2af6c70ba16f86b5897ef9
[5/6] arm64: dts: rockchip: enable sdr-104 on sdmmc
      commit: 6adce30701c810e11685911ca2114fbc0107120d
[6/6] arm64: dts: rockchip: enable sfc controller on Quartz64 Model A
      commit: e5008be69a1947d4236ab3f73c939f9c2a9a6f80

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

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Re: [PATCH v1 0/6] Cleanups and enablement for Quartz64-A

[Heiko Stuebner]

On Wed, 11 May 2022 11:01:11 -0400, Peter Geis wrote:
> Good Morning,
> 
> The following patches clean up some dtbs_check warnings, fixup the
> Quartz64-A dts, and enable some additional functionality on the
> Quartz64-A.
> 
> With this series the only remaining dtbs_check warnings are due to
> unconverted bindings.
> 
> [...]

Applied, thanks!

[1/6] dt-binding: clock: Add missing rk3568 cru bindings
      commit: b21445db9818ccb9fa1c0ba81fd3705eb8d347e3
[2/6] arm64: dts: rockchip: add clocks to rk356x cru
      commit: 70f679ad25d5f8d0076e283bd6c61e047c7af226
[3/6] arm64: dts: rockchip: rename Quartz64-A bluetooth gpios
      commit: 650a1523756bb1e697f8927d2915cbbb92e83f8c
[4/6] arm64: dts: rockchip: add Quartz64-A fan pinctrl
      commit: 82f4f0183e5d3b2d0a2af6c70ba16f86b5897ef9
[5/6] arm64: dts: rockchip: enable sdr-104 on sdmmc
      commit: 6adce30701c810e11685911ca2114fbc0107120d
[6/6] arm64: dts: rockchip: enable sfc controller on Quartz64 Model A
      commit: e5008be69a1947d4236ab3f73c939f9c2a9a6f80

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

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Re: [PATCH v1 6/6] arm64: dts: rockchip: enable sfc controller on Quartz64 Model A

[Chris Morgan]

On Wed, May 11, 2022 at 11:01:17AM -0400, Peter Geis wrote:
> Add the sfc controller binding for the Quartz64 Model A. This is not
> populated by default, so leave it disabled.
> 
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> ---
>  .../boot/dts/rockchip/rk3566-quartz64-a.dts      | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> index 71df64655de5..6ec349e7e521 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> @@ -603,6 +603,22 @@ &sdmmc1 {
>  	status = "okay";
>  };
>  
> +&sfc {
> +	pinctrl-0 = <&fspi_pins>;
> +	pinctrl-names = "default";
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	status = "disabled";
> +
> +	flash@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <24000000>;
> +		spi-rx-bus-width = <4>;
> +		spi-tx-bus-width = <1>;

This isn't really a concern, just a comment. Did you test this with the
spi-tx-bus-width of 4 by chance? While I did have to use 1 for my
implementation (the Odroid Go Advance) the Rockchip engineer I worked
with couldn't replicate the issue on his end and we ended up chalking
my issues up to an implementation specific problem. I'm only commenting
here because I don't want you to think that for this device the tx
always has to be 1, of course if your implementation does have issues
with a tx of 2 or 4 that's different...

Thank you.

> +	};
> +};
> +
>  /* spdif is exposed on con40 pin 18 */
>  &spdif {
>  	status = "okay";
> -- 
> 2.25.1
> 

Re: [PATCH v1 6/6] arm64: dts: rockchip: enable sfc controller on Quartz64 Model A

[Chris Morgan]

On Wed, May 11, 2022 at 11:01:17AM -0400, Peter Geis wrote:
> Add the sfc controller binding for the Quartz64 Model A. This is not
> populated by default, so leave it disabled.
> 
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> ---
>  .../boot/dts/rockchip/rk3566-quartz64-a.dts      | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> index 71df64655de5..6ec349e7e521 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> @@ -603,6 +603,22 @@ &sdmmc1 {
>  	status = "okay";
>  };
>  
> +&sfc {
> +	pinctrl-0 = <&fspi_pins>;
> +	pinctrl-names = "default";
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	status = "disabled";
> +
> +	flash@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <24000000>;
> +		spi-rx-bus-width = <4>;
> +		spi-tx-bus-width = <1>;

This isn't really a concern, just a comment. Did you test this with the
spi-tx-bus-width of 4 by chance? While I did have to use 1 for my
implementation (the Odroid Go Advance) the Rockchip engineer I worked
with couldn't replicate the issue on his end and we ended up chalking
my issues up to an implementation specific problem. I'm only commenting
here because I don't want you to think that for this device the tx
always has to be 1, of course if your implementation does have issues
with a tx of 2 or 4 that's different...

Thank you.

> +	};
> +};
> +
>  /* spdif is exposed on con40 pin 18 */
>  &spdif {
>  	status = "okay";
> -- 
> 2.25.1
> 

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Re: [PATCH v1 6/6] arm64: dts: rockchip: enable sfc controller on Quartz64 Model A

[Chris Morgan]

On Wed, May 11, 2022 at 11:01:17AM -0400, Peter Geis wrote:
> Add the sfc controller binding for the Quartz64 Model A. This is not
> populated by default, so leave it disabled.
> 
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> ---
>  .../boot/dts/rockchip/rk3566-quartz64-a.dts      | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> index 71df64655de5..6ec349e7e521 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> @@ -603,6 +603,22 @@ &sdmmc1 {
>  	status = "okay";
>  };
>  
> +&sfc {
> +	pinctrl-0 = <&fspi_pins>;
> +	pinctrl-names = "default";
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	status = "disabled";
> +
> +	flash@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <24000000>;
> +		spi-rx-bus-width = <4>;
> +		spi-tx-bus-width = <1>;

This isn't really a concern, just a comment. Did you test this with the
spi-tx-bus-width of 4 by chance? While I did have to use 1 for my
implementation (the Odroid Go Advance) the Rockchip engineer I worked
with couldn't replicate the issue on his end and we ended up chalking
my issues up to an implementation specific problem. I'm only commenting
here because I don't want you to think that for this device the tx
always has to be 1, of course if your implementation does have issues
with a tx of 2 or 4 that's different...

Thank you.

> +	};
> +};
> +
>  /* spdif is exposed on con40 pin 18 */
>  &spdif {
>  	status = "okay";
> -- 
> 2.25.1
> 

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Re: [PATCH v1 6/6] arm64: dts: rockchip: enable sfc controller on Quartz64 Model A

[Peter Geis]

On Mon, May 16, 2022 at 11:26 AM Chris Morgan <macroalpha82@gmail.com> wrote:
>
> On Wed, May 11, 2022 at 11:01:17AM -0400, Peter Geis wrote:
> > Add the sfc controller binding for the Quartz64 Model A. This is not
> > populated by default, so leave it disabled.
> >
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > ---
> >  .../boot/dts/rockchip/rk3566-quartz64-a.dts      | 16 ++++++++++++++++
> >  1 file changed, 16 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> > index 71df64655de5..6ec349e7e521 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> > @@ -603,6 +603,22 @@ &sdmmc1 {
> >       status = "okay";
> >  };
> >
> > +&sfc {
> > +     pinctrl-0 = <&fspi_pins>;
> > +     pinctrl-names = "default";
> > +     #address-cells = <1>;
> > +     #size-cells = <0>;
> > +     status = "disabled";
> > +
> > +     flash@0 {
> > +             compatible = "jedec,spi-nor";
> > +             reg = <0>;
> > +             spi-max-frequency = <24000000>;
> > +             spi-rx-bus-width = <4>;
> > +             spi-tx-bus-width = <1>;
>
> This isn't really a concern, just a comment. Did you test this with the
> spi-tx-bus-width of 4 by chance? While I did have to use 1 for my
> implementation (the Odroid Go Advance) the Rockchip engineer I worked
> with couldn't replicate the issue on his end and we ended up chalking
> my issues up to an implementation specific problem. I'm only commenting
> here because I don't want you to think that for this device the tx
> always has to be 1, of course if your implementation does have issues
> with a tx of 2 or 4 that's different...

Yes, and it was a data disaster. Looking into it I found all of the
flash chips that I could find only support 4x RX 1x TX. Some didn't
handle 4x RX terribly well either.

>
> Thank you.
>
> > +     };
> > +};
> > +
> >  /* spdif is exposed on con40 pin 18 */
> >  &spdif {
> >       status = "okay";
> > --
> > 2.25.1
> >

Re: [PATCH v1 6/6] arm64: dts: rockchip: enable sfc controller on Quartz64 Model A

[Peter Geis]

On Mon, May 16, 2022 at 11:26 AM Chris Morgan <macroalpha82@gmail.com> wrote:
>
> On Wed, May 11, 2022 at 11:01:17AM -0400, Peter Geis wrote:
> > Add the sfc controller binding for the Quartz64 Model A. This is not
> > populated by default, so leave it disabled.
> >
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > ---
> >  .../boot/dts/rockchip/rk3566-quartz64-a.dts      | 16 ++++++++++++++++
> >  1 file changed, 16 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> > index 71df64655de5..6ec349e7e521 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> > @@ -603,6 +603,22 @@ &sdmmc1 {
> >       status = "okay";
> >  };
> >
> > +&sfc {
> > +     pinctrl-0 = <&fspi_pins>;
> > +     pinctrl-names = "default";
> > +     #address-cells = <1>;
> > +     #size-cells = <0>;
> > +     status = "disabled";
> > +
> > +     flash@0 {
> > +             compatible = "jedec,spi-nor";
> > +             reg = <0>;
> > +             spi-max-frequency = <24000000>;
> > +             spi-rx-bus-width = <4>;
> > +             spi-tx-bus-width = <1>;
>
> This isn't really a concern, just a comment. Did you test this with the
> spi-tx-bus-width of 4 by chance? While I did have to use 1 for my
> implementation (the Odroid Go Advance) the Rockchip engineer I worked
> with couldn't replicate the issue on his end and we ended up chalking
> my issues up to an implementation specific problem. I'm only commenting
> here because I don't want you to think that for this device the tx
> always has to be 1, of course if your implementation does have issues
> with a tx of 2 or 4 that's different...

Yes, and it was a data disaster. Looking into it I found all of the
flash chips that I could find only support 4x RX 1x TX. Some didn't
handle 4x RX terribly well either.

>
> Thank you.
>
> > +     };
> > +};
> > +
> >  /* spdif is exposed on con40 pin 18 */
> >  &spdif {
> >       status = "okay";
> > --
> > 2.25.1
> >

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Re: [PATCH v1 6/6] arm64: dts: rockchip: enable sfc controller on Quartz64 Model A

[Peter Geis]

On Mon, May 16, 2022 at 11:26 AM Chris Morgan <macroalpha82@gmail.com> wrote:
>
> On Wed, May 11, 2022 at 11:01:17AM -0400, Peter Geis wrote:
> > Add the sfc controller binding for the Quartz64 Model A. This is not
> > populated by default, so leave it disabled.
> >
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > ---
> >  .../boot/dts/rockchip/rk3566-quartz64-a.dts      | 16 ++++++++++++++++
> >  1 file changed, 16 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> > index 71df64655de5..6ec349e7e521 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
> > @@ -603,6 +603,22 @@ &sdmmc1 {
> >       status = "okay";
> >  };
> >
> > +&sfc {
> > +     pinctrl-0 = <&fspi_pins>;
> > +     pinctrl-names = "default";
> > +     #address-cells = <1>;
> > +     #size-cells = <0>;
> > +     status = "disabled";
> > +
> > +     flash@0 {
> > +             compatible = "jedec,spi-nor";
> > +             reg = <0>;
> > +             spi-max-frequency = <24000000>;
> > +             spi-rx-bus-width = <4>;
> > +             spi-tx-bus-width = <1>;
>
> This isn't really a concern, just a comment. Did you test this with the
> spi-tx-bus-width of 4 by chance? While I did have to use 1 for my
> implementation (the Odroid Go Advance) the Rockchip engineer I worked
> with couldn't replicate the issue on his end and we ended up chalking
> my issues up to an implementation specific problem. I'm only commenting
> here because I don't want you to think that for this device the tx
> always has to be 1, of course if your implementation does have issues
> with a tx of 2 or 4 that's different...

Yes, and it was a data disaster. Looking into it I found all of the
flash chips that I could find only support 4x RX 1x TX. Some didn't
handle 4x RX terribly well either.

>
> Thank you.
>
> > +     };
> > +};
> > +
> >  /* spdif is exposed on con40 pin 18 */
> >  &spdif {
> >       status = "okay";
> > --
> > 2.25.1
> >

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