* [Intel-gfx] [PATCH] drm/i915: Update tiled blits selftest @ 2022-05-16 8:20 Nirmoy Das 2022-05-16 9:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork ` (3 more replies) 0 siblings, 4 replies; 6+ messages in thread From: Nirmoy Das @ 2022-05-16 8:20 UTC (permalink / raw) To: intel-gfx; +Cc: krishnaiah.bommu, matthew.auld, chris.p.wilson From: Bommu Krishnaiah <krishnaiah.bommu@intel.com> Update the selftest to include Tile 4 mode and switch to Tile 4 on platforms that supports Tile 4 but no Tile Y and vice versa. Also switch to XY_FAST_COPY_BLT on platforms that supports it. v4: update commit message to reflect the code changes properly. v3: add a function to find X-tile availability for a platform. v2: disable Tile X for iGPU in fastblit and fix checkpath --strict warnings. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5879 Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com> Co-developed-by: Nirmoy Das <nirmoy.das@intel.com> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com> --- .../i915/gem/selftests/i915_gem_client_blt.c | 250 ++++++++++++++---- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 22 ++ 2 files changed, 227 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c index ddd0772fd828..3cfc621ef363 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c @@ -6,6 +6,7 @@ #include "i915_selftest.h" #include "gt/intel_context.h" +#include "gt/intel_engine_regs.h" #include "gt/intel_engine_user.h" #include "gt/intel_gpu_commands.h" #include "gt/intel_gt.h" @@ -18,10 +19,71 @@ #include "huge_gem_object.h" #include "mock_context.h" +#define OW_SIZE 16 /* in bytes */ +#define F_SUBTILE_SIZE 64 /* in bytes */ +#define F_TILE_WIDTH 128 /* in bytes */ +#define F_TILE_HEIGHT 32 /* in pixels */ +#define F_SUBTILE_WIDTH OW_SIZE /* in bytes */ +#define F_SUBTILE_HEIGHT 4 /* in pixels */ + +static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp) +{ + int tile_base; + int tile_x, tile_y; + int swizzle, subtile; + int pixel_size = bpp / 8; + int pos; + + /* + * Subtile remapping for F tile. Note that map[a]==b implies map[b]==a + * so we can use the same table to tile and until. + */ + static const u8 f_subtile_map[] = { + 0, 1, 2, 3, 8, 9, 10, 11, + 4, 5, 6, 7, 12, 13, 14, 15, + 16, 17, 18, 19, 24, 25, 26, 27, + 20, 21, 22, 23, 28, 29, 30, 31, + 32, 33, 34, 35, 40, 41, 42, 43, + 36, 37, 38, 39, 44, 45, 46, 47, + 48, 49, 50, 51, 56, 57, 58, 59, + 52, 53, 54, 55, 60, 61, 62, 63 + }; + + x *= pixel_size; + /* + * Where does the 4k tile start (in bytes)? This is the same for Y and + * F so we can use the Y-tile algorithm to get to that point. + */ + tile_base = + y / F_TILE_HEIGHT * stride * F_TILE_HEIGHT + + x / F_TILE_WIDTH * 4096; + + /* Find pixel within tile */ + tile_x = x % F_TILE_WIDTH; + tile_y = y % F_TILE_HEIGHT; + + /* And figure out the subtile within the 4k tile */ + subtile = tile_y / F_SUBTILE_HEIGHT * 8 + tile_x / F_SUBTILE_WIDTH; + + /* Swizzle the subtile number according to the bspec diagram */ + swizzle = f_subtile_map[subtile]; + + /* Calculate new position */ + pos = tile_base + + swizzle * F_SUBTILE_SIZE + + tile_y % F_SUBTILE_HEIGHT * OW_SIZE + + tile_x % F_SUBTILE_WIDTH; + + GEM_BUG_ON(!IS_ALIGNED(pos, pixel_size)); + + return pos / pixel_size * 4; +} + enum client_tiling { CLIENT_TILING_LINEAR, CLIENT_TILING_X, CLIENT_TILING_Y, + CLIENT_TILING_4, CLIENT_NUM_TILING_TYPES }; @@ -45,6 +107,36 @@ struct tiled_blits { u32 height; }; +static bool supports_x_tiling(const struct drm_i915_private *i915) +{ + int gen = GRAPHICS_VER(i915); + + if (gen < 12) + return true; + + if (!HAS_LMEM(i915) || IS_DG1(i915)) + return false; + + return true; +} + +static bool fast_blit_ok(const struct blit_buffer *buf) +{ + int gen = GRAPHICS_VER(buf->vma->vm->i915); + + if (gen < 9) + return false; + + if (gen < 12) + return true; + + /* filter out platforms with unsupported X-tile support in fastblit */ + if (buf->tiling == CLIENT_TILING_X && !supports_x_tiling(buf->vma->vm->i915)) + return false; + + return true; +} + static int prepare_blit(const struct tiled_blits *t, struct blit_buffer *dst, struct blit_buffer *src, @@ -59,51 +151,103 @@ static int prepare_blit(const struct tiled_blits *t, if (IS_ERR(cs)) return PTR_ERR(cs); - *cs++ = MI_LOAD_REGISTER_IMM(1); - *cs++ = i915_mmio_reg_offset(BCS_SWCTRL); - cmd = (BCS_SRC_Y | BCS_DST_Y) << 16; - if (src->tiling == CLIENT_TILING_Y) - cmd |= BCS_SRC_Y; - if (dst->tiling == CLIENT_TILING_Y) - cmd |= BCS_DST_Y; - *cs++ = cmd; - - cmd = MI_FLUSH_DW; - if (ver >= 8) - cmd++; - *cs++ = cmd; - *cs++ = 0; - *cs++ = 0; - *cs++ = 0; - - cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2); - if (ver >= 8) - cmd += 2; - - src_pitch = t->width * 4; - if (src->tiling) { - cmd |= XY_SRC_COPY_BLT_SRC_TILED; - src_pitch /= 4; - } + if (fast_blit_ok(dst) && fast_blit_ok(src)) { + struct intel_gt *gt = t->ce->engine->gt; + u32 src_tiles = 0, dst_tiles = 0; + u32 src_4t = 0, dst_4t = 0; + + /* Need to program BLIT_CCTL if it is not done previously + * before using XY_FAST_COPY_BLT + */ + *cs++ = MI_LOAD_REGISTER_IMM(1); + *cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base)); + *cs++ = (BLIT_CCTL_SRC_MOCS(gt->mocs.uc_index) | + BLIT_CCTL_DST_MOCS(gt->mocs.uc_index)); + + src_pitch = t->width; /* in dwords */ + if (src->tiling == CLIENT_TILING_4) { + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR); + src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4; + } else if (src->tiling == CLIENT_TILING_Y) { + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR); + } else if (src->tiling == CLIENT_TILING_X) { + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X); + } else { + src_pitch *= 4; /* in bytes */ + } - dst_pitch = t->width * 4; - if (dst->tiling) { - cmd |= XY_SRC_COPY_BLT_DST_TILED; - dst_pitch /= 4; - } + dst_pitch = t->width; /* in dwords */ + if (dst->tiling == CLIENT_TILING_4) { + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR); + dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4; + } else if (dst->tiling == CLIENT_TILING_Y) { + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR); + } else if (dst->tiling == CLIENT_TILING_X) { + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X); + } else { + dst_pitch *= 4; /* in bytes */ + } - *cs++ = cmd; - *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch; - *cs++ = 0; - *cs++ = t->height << 16 | t->width; - *cs++ = lower_32_bits(dst->vma->node.start); - if (use_64b_reloc) + *cs++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2) | + src_tiles | dst_tiles; + *cs++ = src_4t | dst_4t | BLT_DEPTH_32 | dst_pitch; + *cs++ = 0; + *cs++ = t->height << 16 | t->width; + *cs++ = lower_32_bits(dst->vma->node.start); *cs++ = upper_32_bits(dst->vma->node.start); - *cs++ = 0; - *cs++ = src_pitch; - *cs++ = lower_32_bits(src->vma->node.start); - if (use_64b_reloc) + *cs++ = 0; + *cs++ = src_pitch; + *cs++ = lower_32_bits(src->vma->node.start); *cs++ = upper_32_bits(src->vma->node.start); + } else { + if (ver >= 6) { + *cs++ = MI_LOAD_REGISTER_IMM(1); + *cs++ = i915_mmio_reg_offset(BCS_SWCTRL); + cmd = (BCS_SRC_Y | BCS_DST_Y) << 16; + if (src->tiling == CLIENT_TILING_Y) + cmd |= BCS_SRC_Y; + if (dst->tiling == CLIENT_TILING_Y) + cmd |= BCS_DST_Y; + *cs++ = cmd; + + cmd = MI_FLUSH_DW; + if (ver >= 8) + cmd++; + *cs++ = cmd; + *cs++ = 0; + *cs++ = 0; + *cs++ = 0; + } + + cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2); + if (ver >= 8) + cmd += 2; + + src_pitch = t->width * 4; + if (src->tiling) { + cmd |= XY_SRC_COPY_BLT_SRC_TILED; + src_pitch /= 4; + } + + dst_pitch = t->width * 4; + if (dst->tiling) { + cmd |= XY_SRC_COPY_BLT_DST_TILED; + dst_pitch /= 4; + } + + *cs++ = cmd; + *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch; + *cs++ = 0; + *cs++ = t->height << 16 | t->width; + *cs++ = lower_32_bits(dst->vma->node.start); + if (use_64b_reloc) + *cs++ = upper_32_bits(dst->vma->node.start); + *cs++ = 0; + *cs++ = src_pitch; + *cs++ = lower_32_bits(src->vma->node.start); + if (use_64b_reloc) + *cs++ = upper_32_bits(src->vma->node.start); + } *cs++ = MI_BATCH_BUFFER_END; @@ -181,7 +325,13 @@ static int tiled_blits_create_buffers(struct tiled_blits *t, t->buffers[i].vma = vma; t->buffers[i].tiling = - i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng); + i915_prandom_u32_max_state(CLIENT_NUM_TILING_TYPES, prng); + + /* Platforms support either TileY or Tile4, not both */ + if (HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_Y) + t->buffers[i].tiling = CLIENT_TILING_4; + else if (!HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_4) + t->buffers[i].tiling = CLIENT_TILING_Y; } return 0; @@ -206,7 +356,8 @@ static u64 swizzle_bit(unsigned int bit, u64 offset) static u64 tiled_offset(const struct intel_gt *gt, u64 v, unsigned int stride, - enum client_tiling tiling) + enum client_tiling tiling, + int x_pos, int y_pos) { unsigned int swizzle; u64 x, y; @@ -216,7 +367,12 @@ static u64 tiled_offset(const struct intel_gt *gt, y = div64_u64_rem(v, stride, &x); - if (tiling == CLIENT_TILING_X) { + if (tiling == CLIENT_TILING_4) { + v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32); + + /* no swizzling for f-tiling */ + swizzle = I915_BIT_6_SWIZZLE_NONE; + } else if (tiling == CLIENT_TILING_X) { v = div64_u64_rem(y, 8, &y) * stride * 8; v += y * 512; v += div64_u64_rem(x, 512, &x) << 12; @@ -259,6 +415,7 @@ static const char *repr_tiling(enum client_tiling tiling) case CLIENT_TILING_LINEAR: return "linear"; case CLIENT_TILING_X: return "X"; case CLIENT_TILING_Y: return "Y"; + case CLIENT_TILING_4: return "F"; default: return "unknown"; } } @@ -284,7 +441,7 @@ static int verify_buffer(const struct tiled_blits *t, } else { u64 v = tiled_offset(buf->vma->vm->gt, p * 4, t->width * 4, - buf->tiling); + buf->tiling, x, y); if (vaddr[v / sizeof(*vaddr)] != buf->start_val + p) ret = -EINVAL; @@ -504,6 +661,9 @@ static int tiled_blits_bounce(struct tiled_blits *t, struct rnd_state *prng) if (err) return err; + /* Simulating GTT eviction of the same buffer / layout */ + t->buffers[2].tiling = t->buffers[0].tiling; + /* Reposition so that we overlap the old addresses, and slightly off */ err = tiled_blit(t, &t->buffers[2], t->hole + t->align, diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h index 556bca3be804..246ab8f7bf57 100644 --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h @@ -236,6 +236,28 @@ #define XY_FAST_COLOR_BLT_DW 16 #define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21) #define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31 + +#define XY_FAST_COPY_BLT_D0_SRC_TILING_MASK REG_GENMASK(21, 20) +#define XY_FAST_COPY_BLT_D0_DST_TILING_MASK REG_GENMASK(14, 13) +#define XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(mode) \ + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_SRC_TILING_MASK, mode) +#define XY_FAST_COPY_BLT_D0_DST_TILE_MODE(mode) \ + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_DST_TILING_MASK, mode) +#define LINEAR 0 +#define TILE_X 0x1 +#define XMAJOR 0x1 +#define YMAJOR 0x2 +#define TILE_64 0x3 +#define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31) +#define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30) +#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0) +#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8) +/* Note: MOCS value = (index << 1) */ +#define BLIT_CCTL_SRC_MOCS(idx) \ + REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (idx) << 1) +#define BLIT_CCTL_DST_MOCS(idx) \ + REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (idx) << 1) + #define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22) #define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22) #define XY_SRC_COPY_BLT_CMD (2 << 29 | 0x53 << 22) -- 2.35.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Update tiled blits selftest 2022-05-16 8:20 [Intel-gfx] [PATCH] drm/i915: Update tiled blits selftest Nirmoy Das @ 2022-05-16 9:30 ` Patchwork 2022-05-16 11:06 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork ` (2 subsequent siblings) 3 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2022-05-16 9:30 UTC (permalink / raw) To: Nirmoy Das; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 10315 bytes --] == Series Details == Series: drm/i915: Update tiled blits selftest URL : https://patchwork.freedesktop.org/series/104016/ State : success == Summary == CI Bug Log - changes from CI_DRM_11656 -> Patchwork_104016v1 ==================================================== Summary ------- **WARNING** Minor unknown changes coming with Patchwork_104016v1 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_104016v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/index.html Participating hosts (41 -> 42) ------------------------------ Additional (3): bat-adln-1 fi-rkl-11600 bat-dg2-9 Missing (2): fi-hsw-4770 bat-jsl-2 Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_104016v1: ### IGT changes ### #### Warnings #### * igt@debugfs_test@read_all_entries: - fi-apl-guc: [DMESG-WARN][1] ([i915#5595]) -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/fi-apl-guc/igt@debugfs_test@read_all_entries.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/fi-apl-guc/igt@debugfs_test@read_all_entries.html Known issues ------------ Here are the changes found in Patchwork_104016v1 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_huc_copy@huc-copy: - fi-rkl-11600: NOTRUN -> [SKIP][3] ([i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/fi-rkl-11600/igt@gem_huc_copy@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-rkl-11600: NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/fi-rkl-11600/igt@gem_lmem_swapping@basic.html * igt@gem_tiled_pread_basic: - fi-rkl-11600: NOTRUN -> [SKIP][5] ([i915#3282]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - fi-rkl-11600: NOTRUN -> [SKIP][6] ([i915#3012]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/fi-rkl-11600/igt@i915_pm_backlight@basic-brightness.html * igt@i915_selftest@live@hangcheck: - bat-dg1-5: [PASS][7] -> [DMESG-FAIL][8] ([i915#4494] / [i915#4957]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/bat-dg1-5/igt@i915_selftest@live@hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/bat-dg1-5/igt@i915_selftest@live@hangcheck.html * igt@i915_selftest@live@requests: - fi-pnv-d510: [PASS][9] -> [DMESG-FAIL][10] ([i915#4528]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/fi-pnv-d510/igt@i915_selftest@live@requests.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/fi-pnv-d510/igt@i915_selftest@live@requests.html * igt@kms_chamelium@dp-crc-fast: - fi-rkl-11600: NOTRUN -> [SKIP][11] ([fdo#111827]) +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/fi-rkl-11600/igt@kms_chamelium@dp-crc-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-rkl-11600: NOTRUN -> [SKIP][12] ([i915#4070] / [i915#4103]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/fi-rkl-11600/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt@kms_flip@basic-flip-vs-modeset@b-edp1: - bat-adlp-4: [PASS][13] -> [DMESG-WARN][14] ([i915#3576]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html * igt@kms_force_connector_basic@force-load-detect: - fi-rkl-11600: NOTRUN -> [SKIP][15] ([fdo#109285] / [i915#4098]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/fi-rkl-11600/igt@kms_force_connector_basic@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-rkl-11600: NOTRUN -> [SKIP][16] ([i915#4070] / [i915#533]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/fi-rkl-11600/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@primary_mmap_gtt: - fi-rkl-11600: NOTRUN -> [SKIP][17] ([i915#1072]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/fi-rkl-11600/igt@kms_psr@primary_mmap_gtt.html * igt@kms_setmode@basic-clone-single-crtc: - fi-rkl-11600: NOTRUN -> [SKIP][18] ([i915#3555] / [i915#4098]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/fi-rkl-11600/igt@kms_setmode@basic-clone-single-crtc.html * igt@prime_vgem@basic-userptr: - fi-rkl-11600: NOTRUN -> [SKIP][19] ([i915#3301] / [i915#3708]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/fi-rkl-11600/igt@prime_vgem@basic-userptr.html * igt@prime_vgem@basic-write: - fi-rkl-11600: NOTRUN -> [SKIP][20] ([i915#3291] / [i915#3708]) +2 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/fi-rkl-11600/igt@prime_vgem@basic-write.html #### Possible fixes #### * igt@core_hotunplug@unbind-rebind: - {bat-rpls-2}: [DMESG-WARN][21] ([i915#4391]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/bat-rpls-2/igt@core_hotunplug@unbind-rebind.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/bat-rpls-2/igt@core_hotunplug@unbind-rebind.html * igt@kms_busy@basic@modeset: - bat-adlp-4: [DMESG-WARN][23] ([i915#3576]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/bat-adlp-4/igt@kms_busy@basic@modeset.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/bat-adlp-4/igt@kms_busy@basic@modeset.html - {bat-adlp-6}: [DMESG-WARN][25] ([i915#3576]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/bat-adlp-6/igt@kms_busy@basic@modeset.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/bat-adlp-6/igt@kms_busy@basic@modeset.html * igt@kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-kbl-soraka: [INCOMPLETE][27] -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/fi-kbl-soraka/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/fi-kbl-soraka/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576 [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391 [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494 [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528 [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873 [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957 [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190 [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#5595]: https://gitlab.freedesktop.org/drm/intel/issues/5595 [i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763 [i915#5869]: https://gitlab.freedesktop.org/drm/intel/issues/5869 [i915#5874]: https://gitlab.freedesktop.org/drm/intel/issues/5874 [i915#5879]: https://gitlab.freedesktop.org/drm/intel/issues/5879 [i915#5885]: https://gitlab.freedesktop.org/drm/intel/issues/5885 [i915#5950]: https://gitlab.freedesktop.org/drm/intel/issues/5950 Build changes ------------- * Linux: CI_DRM_11656 -> Patchwork_104016v1 CI-20190529: 20190529 CI_DRM_11656: 416780e079b848ddd4da752cb90b619b97eb773e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6472: c815c94f0ceb33ae852622538f0136cf44c5725d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_104016v1: 416780e079b848ddd4da752cb90b619b97eb773e @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits be502ba519a9 drm/i915: Update tiled blits selftest == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/index.html [-- Attachment #2: Type: text/html, Size: 10474 bytes --] ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Update tiled blits selftest 2022-05-16 8:20 [Intel-gfx] [PATCH] drm/i915: Update tiled blits selftest Nirmoy Das 2022-05-16 9:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork @ 2022-05-16 11:06 ` Patchwork 2022-05-24 8:16 ` [Intel-gfx] [PATCH] " Zbigniew Kempczyński 2022-05-24 11:56 ` Andrzej Hajda 3 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2022-05-16 11:06 UTC (permalink / raw) To: Nirmoy Das; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 52857 bytes --] == Series Details == Series: drm/i915: Update tiled blits selftest URL : https://patchwork.freedesktop.org/series/104016/ State : success == Summary == CI Bug Log - changes from CI_DRM_11656_full -> Patchwork_104016v1_full ==================================================== Summary ------- **SUCCESS** No regressions found. Participating hosts (10 -> 13) ------------------------------ Additional (3): shard-rkl shard-dg1 shard-tglu Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_104016v1_full: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@gem_ctx_shared@q-smoketest-all: - {shard-tglu}: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-tglu-8/igt@gem_ctx_shared@q-smoketest-all.html * igt@gem_softpin@evict-single-offset: - {shard-rkl}: NOTRUN -> [FAIL][2] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-rkl-2/igt@gem_softpin@evict-single-offset.html * igt@kms_plane_scaling@downscale-with-modifier-factor-0-25@pipe-b-hdmi-a-1-downscale-with-modifier: - {shard-dg1}: NOTRUN -> [SKIP][3] +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-dg1-19/igt@kms_plane_scaling@downscale-with-modifier-factor-0-25@pipe-b-hdmi-a-1-downscale-with-modifier.html New tests --------- New tests have been introduced between CI_DRM_11656_full and Patchwork_104016v1_full: ### New IGT tests (2) ### * igt@kms_flip@flip-vs-dpms-off-vs-modeset@d-hdmi-a3: - Statuses : 1 pass(s) - Exec time: [0.63] s * igt@kms_hdr@static-toggle-suspend@pipe-a-edp-1: - Statuses : 1 pass(s) - Exec time: [6.31] s Known issues ------------ Here are the changes found in Patchwork_104016v1_full that come from known issues: ### CI changes ### #### Issues hit #### * boot: - shard-glk: ([PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28]) -> ([PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [FAIL][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53]) ([i915#4392]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk1/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk1/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk2/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk2/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk3/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk3/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk3/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk4/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk4/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk5/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk5/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk5/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk5/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk6/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk6/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk6/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk7/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk7/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk7/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk8/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk8/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk8/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk9/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk9/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk9/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk9/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk9/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk9/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk8/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk8/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk8/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk7/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk7/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk7/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk6/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk6/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk6/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk5/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk5/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk4/boot.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk4/boot.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk4/boot.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk3/boot.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk3/boot.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk3/boot.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk2/boot.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk2/boot.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk2/boot.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk1/boot.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk1/boot.html - shard-skl: ([PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [PASS][77]) -> ([PASS][78], [PASS][79], [PASS][80], [PASS][81], [FAIL][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99]) ([i915#5032]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl9/boot.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl9/boot.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl9/boot.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl8/boot.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl8/boot.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl7/boot.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl7/boot.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl7/boot.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl6/boot.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl6/boot.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl6/boot.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl4/boot.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl4/boot.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl4/boot.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl4/boot.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl3/boot.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl2/boot.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl2/boot.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl1/boot.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl1/boot.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl10/boot.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl10/boot.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl10/boot.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl10/boot.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl6/boot.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl6/boot.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl4/boot.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl4/boot.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl3/boot.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl2/boot.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl2/boot.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl1/boot.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl1/boot.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl1/boot.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl10/boot.html [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl10/boot.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl9/boot.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl9/boot.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl9/boot.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl8/boot.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl8/boot.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl8/boot.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl7/boot.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl7/boot.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl7/boot.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl6/boot.html ### IGT changes ### #### Issues hit #### * igt@gem_ccs@ctrl-surf-copy-new-ctx: - shard-iclb: NOTRUN -> [SKIP][100] ([i915#5327]) [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb7/igt@gem_ccs@ctrl-surf-copy-new-ctx.html * igt@gem_ctx_persistence@legacy-engines-mixed-process: - shard-snb: NOTRUN -> [SKIP][101] ([fdo#109271] / [i915#1099]) [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-snb7/igt@gem_ctx_persistence@legacy-engines-mixed-process.html * igt@gem_exec_capture@pi@vecs0: - shard-iclb: [PASS][102] -> [INCOMPLETE][103] ([i915#3371]) [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-iclb1/igt@gem_exec_capture@pi@vecs0.html [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb5/igt@gem_exec_capture@pi@vecs0.html * igt@gem_exec_fair@basic-deadline: - shard-glk: [PASS][104] -> [FAIL][105] ([i915#2846]) [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk3/igt@gem_exec_fair@basic-deadline.html [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk4/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_flush@basic-wb-set-default: - shard-snb: [PASS][106] -> [SKIP][107] ([fdo#109271]) +1 similar issue [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-snb4/igt@gem_exec_flush@basic-wb-set-default.html [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-snb6/igt@gem_exec_flush@basic-wb-set-default.html * igt@gem_exec_params@no-blt: - shard-iclb: NOTRUN -> [SKIP][108] ([fdo#109283]) [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb3/igt@gem_exec_params@no-blt.html * igt@gem_exec_params@secure-non-root: - shard-iclb: NOTRUN -> [SKIP][109] ([fdo#112283]) [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb3/igt@gem_exec_params@secure-non-root.html * igt@gem_exec_whisper@basic-contexts-forked-all: - shard-glk: [PASS][110] -> [DMESG-WARN][111] ([i915#118]) [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk8/igt@gem_exec_whisper@basic-contexts-forked-all.html [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk3/igt@gem_exec_whisper@basic-contexts-forked-all.html * igt@gem_huc_copy@huc-copy: - shard-tglb: [PASS][112] -> [SKIP][113] ([i915#2190]) [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-tglb3/igt@gem_huc_copy@huc-copy.html [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-tglb7/igt@gem_huc_copy@huc-copy.html * igt@gem_lmem_swapping@verify-ccs: - shard-iclb: NOTRUN -> [SKIP][114] ([i915#4613]) [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb7/igt@gem_lmem_swapping@verify-ccs.html * igt@gem_mmap_gtt@coherency: - shard-iclb: NOTRUN -> [SKIP][115] ([fdo#109292]) [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb7/igt@gem_mmap_gtt@coherency.html * igt@gem_pread@exhaustion: - shard-apl: NOTRUN -> [WARN][116] ([i915#2658]) [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-apl6/igt@gem_pread@exhaustion.html * igt@gem_pxp@verify-pxp-stale-ctx-execution: - shard-iclb: NOTRUN -> [SKIP][117] ([i915#4270]) [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb7/igt@gem_pxp@verify-pxp-stale-ctx-execution.html * igt@gem_userptr_blits@unsync-overlap: - shard-iclb: NOTRUN -> [SKIP][118] ([i915#3297]) [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb6/igt@gem_userptr_blits@unsync-overlap.html * igt@gem_userptr_blits@vma-merge: - shard-snb: NOTRUN -> [FAIL][119] ([i915#2724]) [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-snb7/igt@gem_userptr_blits@vma-merge.html * igt@gen7_exec_parse@basic-offset: - shard-skl: NOTRUN -> [SKIP][120] ([fdo#109271]) +17 similar issues [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl9/igt@gen7_exec_parse@basic-offset.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][121] -> [DMESG-WARN][122] ([i915#5566] / [i915#716]) [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl10/igt@gen9_exec_parse@allowed-single.html [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl9/igt@gen9_exec_parse@allowed-single.html * igt@gen9_exec_parse@batch-zero-length: - shard-iclb: NOTRUN -> [SKIP][123] ([i915#2856]) +1 similar issue [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb7/igt@gen9_exec_parse@batch-zero-length.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [PASS][124] -> [FAIL][125] ([i915#454]) [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-iclb1/igt@i915_pm_dc@dc6-psr.html [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb3/igt@i915_pm_dc@dc6-psr.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-iclb: NOTRUN -> [WARN][126] ([i915#2684]) [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb6/igt@i915_pm_rc6_residency@rc6-idle.html * igt@i915_query@query-topology-unsupported: - shard-iclb: NOTRUN -> [SKIP][127] ([fdo#109302]) [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb7/igt@i915_query@query-topology-unsupported.html * igt@i915_suspend@fence-restore-untiled: - shard-apl: NOTRUN -> [DMESG-WARN][128] ([i915#180]) [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-apl3/igt@i915_suspend@fence-restore-untiled.html * igt@kms_big_fb@4-tiled-addfb-size-offset-overflow: - shard-snb: NOTRUN -> [SKIP][129] ([fdo#109271]) +73 similar issues [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-snb7/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip: - shard-iclb: NOTRUN -> [SKIP][130] ([i915#5286]) +2 similar issues [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb7/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html * igt@kms_big_fb@x-tiled-16bpp-rotate-90: - shard-iclb: NOTRUN -> [SKIP][131] ([fdo#110725] / [fdo#111614]) [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb3/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html * igt@kms_big_fb@yf-tiled-64bpp-rotate-90: - shard-iclb: NOTRUN -> [SKIP][132] ([fdo#110723]) +1 similar issue [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb6/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip: - shard-skl: NOTRUN -> [FAIL][133] ([i915#3743]) [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs: - shard-apl: NOTRUN -> [SKIP][134] ([fdo#109271] / [i915#3886]) +1 similar issue [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-apl6/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc: - shard-iclb: NOTRUN -> [SKIP][135] ([fdo#109278] / [i915#3886]) +3 similar issues [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb3/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html * igt@kms_chamelium@dp-hpd-storm: - shard-iclb: NOTRUN -> [SKIP][136] ([fdo#109284] / [fdo#111827]) +6 similar issues [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb7/igt@kms_chamelium@dp-hpd-storm.html * igt@kms_chamelium@hdmi-frame-dump: - shard-snb: NOTRUN -> [SKIP][137] ([fdo#109271] / [fdo#111827]) +3 similar issues [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-snb7/igt@kms_chamelium@hdmi-frame-dump.html * igt@kms_color@pipe-d-ctm-negative: - shard-iclb: NOTRUN -> [SKIP][138] ([fdo#109278] / [i915#1149]) [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb3/igt@kms_color@pipe-d-ctm-negative.html * igt@kms_color_chamelium@pipe-a-ctm-0-5: - shard-skl: NOTRUN -> [SKIP][139] ([fdo#109271] / [fdo#111827]) +1 similar issue [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl9/igt@kms_color_chamelium@pipe-a-ctm-0-5.html * igt@kms_color_chamelium@pipe-b-ctm-limited-range: - shard-apl: NOTRUN -> [SKIP][140] ([fdo#109271] / [fdo#111827]) [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-apl6/igt@kms_color_chamelium@pipe-b-ctm-limited-range.html * igt@kms_color_chamelium@pipe-d-gamma: - shard-iclb: NOTRUN -> [SKIP][141] ([fdo#109278] / [fdo#109284] / [fdo#111827]) +1 similar issue [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb3/igt@kms_color_chamelium@pipe-d-gamma.html * igt@kms_content_protection@atomic: - shard-iclb: NOTRUN -> [SKIP][142] ([fdo#109300] / [fdo#111066]) [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb3/igt@kms_content_protection@atomic.html * igt@kms_cursor_crc@pipe-b-cursor-512x512-sliding: - shard-iclb: NOTRUN -> [SKIP][143] ([fdo#109278] / [fdo#109279]) +2 similar issues [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb7/igt@kms_cursor_crc@pipe-b-cursor-512x512-sliding.html * igt@kms_cursor_crc@pipe-c-cursor-512x170-sliding: - shard-apl: NOTRUN -> [SKIP][144] ([fdo#109271] / [i915#5691]) [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-512x170-sliding.html * igt@kms_cursor_crc@pipe-d-cursor-32x10-offscreen: - shard-iclb: NOTRUN -> [SKIP][145] ([fdo#109278]) +18 similar issues [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb6/igt@kms_cursor_crc@pipe-d-cursor-32x10-offscreen.html * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic: - shard-iclb: NOTRUN -> [SKIP][146] ([fdo#109274] / [fdo#109278]) +2 similar issues [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb3/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic: - shard-skl: [PASS][147] -> [FAIL][148] ([i915#2346]) [147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html * igt@kms_draw_crc@draw-method-rgb565-blt-4tiled: - shard-iclb: NOTRUN -> [SKIP][149] ([i915#5287]) [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb6/igt@kms_draw_crc@draw-method-rgb565-blt-4tiled.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-apl: [PASS][150] -> [FAIL][151] ([i915#4767]) [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible: - shard-iclb: NOTRUN -> [SKIP][152] ([fdo#109274]) +3 similar issues [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb3/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1: - shard-skl: [PASS][153] -> [FAIL][154] ([i915#79]) +1 similar issue [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html * igt@kms_flip@flip-vs-suspend@c-dp1: - shard-apl: [PASS][155] -> [DMESG-WARN][156] ([i915#180]) +1 similar issue [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-apl8/igt@kms_flip@flip-vs-suspend@c-dp1.html [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-apl2/igt@kms_flip@flip-vs-suspend@c-dp1.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling: - shard-glk: [PASS][157] -> [FAIL][158] ([i915#4911]) [157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt: - shard-iclb: NOTRUN -> [SKIP][159] ([fdo#109280]) +13 similar issues [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite: - shard-apl: NOTRUN -> [SKIP][160] ([fdo#109271]) +39 similar issues [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-apl6/igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite.html * igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence: - shard-apl: NOTRUN -> [SKIP][161] ([fdo#109271] / [i915#533]) [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-apl1/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][162] -> [FAIL][163] ([fdo#108145] / [i915#265]) +1 similar issue [162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@kms_plane_lowres@pipe-c-tiling-4: - shard-iclb: NOTRUN -> [SKIP][164] ([i915#5288]) [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb6/igt@kms_plane_lowres@pipe-c-tiling-4.html * igt@kms_psr@psr2_cursor_plane_onoff: - shard-iclb: NOTRUN -> [SKIP][165] ([fdo#109441]) [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb3/igt@kms_psr@psr2_cursor_plane_onoff.html * igt@kms_psr@psr2_sprite_render: - shard-iclb: [PASS][166] -> [SKIP][167] ([fdo#109441]) +1 similar issue [166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-iclb2/igt@kms_psr@psr2_sprite_render.html [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb6/igt@kms_psr@psr2_sprite_render.html * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0: - shard-skl: [PASS][168] -> [DMESG-WARN][169] ([i915#1982]) [168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl4/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl7/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html * igt@kms_writeback@writeback-fb-id: - shard-iclb: NOTRUN -> [SKIP][170] ([i915#2437]) [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb3/igt@kms_writeback@writeback-fb-id.html * igt@nouveau_crc@pipe-d-source-outp-complete: - shard-iclb: NOTRUN -> [SKIP][171] ([fdo#109278] / [i915#2530]) [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb3/igt@nouveau_crc@pipe-d-source-outp-complete.html * igt@perf@gen12-unprivileged-single-ctx-counters: - shard-iclb: NOTRUN -> [SKIP][172] ([fdo#109289]) +1 similar issue [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb7/igt@perf@gen12-unprivileged-single-ctx-counters.html * igt@perf@polling-parameterized: - shard-skl: [PASS][173] -> [FAIL][174] ([i915#5639]) [173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl1/igt@perf@polling-parameterized.html [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl2/igt@perf@polling-parameterized.html * igt@prime_nv_test@i915_import_pread_pwrite: - shard-iclb: NOTRUN -> [SKIP][175] ([fdo#109291]) +1 similar issue [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb7/igt@prime_nv_test@i915_import_pread_pwrite.html * igt@prime_vgem@fence-write-hang: - shard-iclb: NOTRUN -> [SKIP][176] ([fdo#109295]) [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb6/igt@prime_vgem@fence-write-hang.html * igt@sysfs_clients@recycle: - shard-apl: NOTRUN -> [SKIP][177] ([fdo#109271] / [i915#2994]) [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-apl6/igt@sysfs_clients@recycle.html * igt@sysfs_clients@sema-50: - shard-skl: NOTRUN -> [SKIP][178] ([fdo#109271] / [i915#2994]) [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl9/igt@sysfs_clients@sema-50.html * igt@sysfs_clients@split-50: - shard-iclb: NOTRUN -> [SKIP][179] ([i915#2994]) [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb3/igt@sysfs_clients@split-50.html #### Possible fixes #### * igt@gem_exec_fair@basic-none@vecs0: - shard-apl: [FAIL][180] ([i915#2842]) -> [PASS][181] +1 similar issue [180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-apl1/igt@gem_exec_fair@basic-none@vecs0.html [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-apl7/igt@gem_exec_fair@basic-none@vecs0.html * igt@gem_exec_flush@basic-wb-ro-before-default: - shard-snb: [SKIP][182] ([fdo#109271]) -> [PASS][183] +2 similar issues [182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-snb6/igt@gem_exec_flush@basic-wb-ro-before-default.html [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-snb4/igt@gem_exec_flush@basic-wb-ro-before-default.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-apl: [FAIL][184] ([i915#644]) -> [PASS][185] [184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-apl3/igt@gem_ppgtt@flink-and-close-vma-leak.html [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-apl3/igt@gem_ppgtt@flink-and-close-vma-leak.html * igt@i915_pm_dc@dc6-dpms: - shard-iclb: [FAIL][186] ([i915#454]) -> [PASS][187] [186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb8/igt@i915_pm_dc@dc6-dpms.html * igt@i915_selftest@live@hangcheck: - shard-snb: [INCOMPLETE][188] ([i915#3921]) -> [PASS][189] [188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-snb2/igt@i915_selftest@live@hangcheck.html [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-snb7/igt@i915_selftest@live@hangcheck.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-glk: [FAIL][190] ([i915#2346]) -> [PASS][191] [190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_cursor_legacy@flip-vs-cursor-toggle: - shard-iclb: [FAIL][192] ([i915#2346]) -> [PASS][193] [192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb5/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1: - shard-skl: [FAIL][194] ([i915#79]) -> [PASS][195] [194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html * igt@kms_flip@flip-vs-suspend-interruptible@a-edp1: - shard-skl: [INCOMPLETE][196] ([i915#5864]) -> [PASS][197] [196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl7/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl9/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html * igt@kms_flip@flip-vs-suspend@b-dp1: - shard-apl: [DMESG-WARN][198] ([i915#180]) -> [PASS][199] +4 similar issues [198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-apl8/igt@kms_flip@flip-vs-suspend@b-dp1.html [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-apl2/igt@kms_flip@flip-vs-suspend@b-dp1.html * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1: - shard-skl: [FAIL][200] ([i915#2122]) -> [PASS][201] +3 similar issues [200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling: - shard-iclb: [SKIP][202] ([i915#3701]) -> [PASS][203] +1 similar issue [202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html * igt@kms_frontbuffer_tracking@psr-suspend: - shard-tglb: [DMESG-WARN][204] ([i915#2411] / [i915#2867]) -> [PASS][205] [204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-tglb2/igt@kms_frontbuffer_tracking@psr-suspend.html [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-tglb8/igt@kms_frontbuffer_tracking@psr-suspend.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][206] ([fdo#108145] / [i915#265]) -> [PASS][207] +1 similar issue [206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt@kms_psr@psr2_primary_render: - shard-iclb: [SKIP][208] ([fdo#109441]) -> [PASS][209] [208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-iclb4/igt@kms_psr@psr2_primary_render.html [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb2/igt@kms_psr@psr2_primary_render.html * igt@kms_psr_stress_test@flip-primary-invalidate-overlay: - shard-iclb: [SKIP][210] ([i915#5519]) -> [PASS][211] [210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-iclb4/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html * igt@perf@polling-small-buf: - shard-skl: [FAIL][212] ([i915#1722]) -> [PASS][213] [212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-skl10/igt@perf@polling-small-buf.html [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-skl4/igt@perf@polling-small-buf.html #### Warnings #### * igt@gem_eio@unwedge-stress: - shard-tglb: [TIMEOUT][214] ([i915#3063]) -> [FAIL][215] ([i915#5784]) [214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-tglb6/igt@gem_eio@unwedge-stress.html [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-tglb1/igt@gem_eio@unwedge-stress.html * igt@gem_exec_balancer@parallel-contexts: - shard-iclb: [DMESG-WARN][216] ([i915#5614]) -> [SKIP][217] ([i915#4525]) +2 similar issues [216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-iclb1/igt@gem_exec_balancer@parallel-contexts.html [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb3/igt@gem_exec_balancer@parallel-contexts.html * igt@gem_exec_balancer@parallel-ordering: - shard-iclb: [SKIP][218] ([i915#4525]) -> [DMESG-FAIL][219] ([i915#5614]) [218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-iclb6/igt@gem_exec_balancer@parallel-ordering.html [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb4/igt@gem_exec_balancer@parallel-ordering.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-glk: [FAIL][220] ([i915#2851]) -> [FAIL][221] ([i915#2842]) [220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-glk2/igt@gem_exec_fair@basic-pace-solo@rcs0.html [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-glk3/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area: - shard-iclb: [SKIP][222] ([i915#2920]) -> [SKIP][223] ([fdo#111068] / [i915#658]) [222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11656/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/shard-iclb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279 [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283 [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291 [fdo#109292]: https://bugs.freedesktop.org/show_bug.cgi?id=109292 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300 [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302 [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303 [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307 [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308 [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309 [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312 [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313 [fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542 [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 [fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725 [fdo#111066]: https://bugs.freedesktop.org/show_bug.cgi?id=111066 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022 [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054 [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283 [i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099 [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257 [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722 [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755 [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825 [i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836 [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849 [i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850 [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902 [i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433 [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434 [i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435 [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658 [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681 [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684 [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705 [i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724 [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280 [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846 [i915#2851]: https://gitlab.freedesktop.org/drm/intel/issues/2851 [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856 [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867 [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002 [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012 [i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063 [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299 [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318 [i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319 [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323 [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 [i915#3371]: https://gitlab.freedesktop.org/drm/intel/issues/3371 [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 [i915#3464]: https://gitlab.freedesktop.org/drm/intel/issues/3464 [i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528 [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734 [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742 [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743 [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804 [i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825 [i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826 [i915#3828]: https://gitlab.freedesktop.org/drm/intel/issues/3828 [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 [i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952 [i915#4032]: https://gitlab.freedesktop.org/drm/intel/issues/4032 [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404 [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433 [i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369 [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387 [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391 [i915#4392]: https://gitlab.freedesktop.org/drm/intel/issues/4392 [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525 [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767 [i915#4807]: https://gitlab.freedesktop.org/drm/intel/issues/4807 [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812 [i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818 [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833 [i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842 [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852 [i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853 [i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855 [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859 [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860 [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880 [i915#4883]: https://gitlab.freedesktop.org/drm/intel/issues/4883 [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885 [i915#4886]: https://gitlab.freedesktop.org/drm/intel/issues/4886 [i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893 [i915#4911]: https://gitlab.freedesktop.org/drm/intel/issues/4911 [i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936 [i915#4941]: https://gitlab.freedesktop.org/drm/intel/issues/4941 [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991 [i915#5032]: https://gitlab.freedesktop.org/drm/intel/issues/5032 [i915#5076]: https://gitlab.freedesktop.org/drm/intel/issues/5076 [i915#5080]: https://gitlab.freedesktop.org/drm/intel/issues/5080 [i915#5098]: https://gitlab.freedesktop.org/drm/intel/issues/5098 [i915#5174]: https://gitlab.freedesktop.org/drm/intel/issues/5174 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257 [i915#5264]: https://gitlab.freedesktop.org/drm/intel/issues/5264 [i915#5266]: https://gitlab.freedesktop.org/drm/intel/issues/5266 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287 [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288 [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289 [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 [i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439 [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461 [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519 [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563 [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566 [i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608 [i915#5614]: https://gitlab.freedesktop.org/drm/intel/issues/5614 [i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639 [i915#5691]: https://gitlab.freedesktop.org/drm/intel/issues/5691 [i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723 [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784 [i915#5864]: https://gitlab.freedesktop.org/drm/intel/issues/5864 [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 Build changes ------------- * Linux: CI_DRM_11656 -> Patchwork_104016v1 CI-20190529: 20190529 CI_DRM_11656: 416780e079b848ddd4da752cb90b619b97eb773e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6472: c815c94f0ceb33ae852622538f0136cf44c5725d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_104016v1: 416780e079b848ddd4da752cb90b619b97eb773e @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104016v1/index.html [-- Attachment #2: Type: text/html, Size: 49989 bytes --] ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Update tiled blits selftest 2022-05-16 8:20 [Intel-gfx] [PATCH] drm/i915: Update tiled blits selftest Nirmoy Das 2022-05-16 9:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork 2022-05-16 11:06 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork @ 2022-05-24 8:16 ` Zbigniew Kempczyński 2022-05-24 11:56 ` Andrzej Hajda 3 siblings, 0 replies; 6+ messages in thread From: Zbigniew Kempczyński @ 2022-05-24 8:16 UTC (permalink / raw) To: Nirmoy Das; +Cc: krishnaiah.bommu, intel-gfx, matthew.auld, chris.p.wilson On Mon, May 16, 2022 at 10:20:15AM +0200, Nirmoy Das wrote: > From: Bommu Krishnaiah <krishnaiah.bommu@intel.com> > > Update the selftest to include Tile 4 mode and switch to Tile 4 on > platforms that supports Tile 4 but no Tile Y and vice versa. > Also switch to XY_FAST_COPY_BLT on platforms that supports it. > > v4: update commit message to reflect the code changes properly. > v3: add a function to find X-tile availability for a platform. > v2: disable Tile X for iGPU in fastblit and > fix checkpath --strict warnings. > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5879 > Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com> > Co-developed-by: Nirmoy Das <nirmoy.das@intel.com> > Signed-off-by: Nirmoy Das <nirmoy.das@intel.com> I keep my rb if there're no other commit msg objections: Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> -- Zbigniew > --- > .../i915/gem/selftests/i915_gem_client_blt.c | 250 ++++++++++++++---- > drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 22 ++ > 2 files changed, 227 insertions(+), 45 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c > index ddd0772fd828..3cfc621ef363 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c > @@ -6,6 +6,7 @@ > #include "i915_selftest.h" > > #include "gt/intel_context.h" > +#include "gt/intel_engine_regs.h" > #include "gt/intel_engine_user.h" > #include "gt/intel_gpu_commands.h" > #include "gt/intel_gt.h" > @@ -18,10 +19,71 @@ > #include "huge_gem_object.h" > #include "mock_context.h" > > +#define OW_SIZE 16 /* in bytes */ > +#define F_SUBTILE_SIZE 64 /* in bytes */ > +#define F_TILE_WIDTH 128 /* in bytes */ > +#define F_TILE_HEIGHT 32 /* in pixels */ > +#define F_SUBTILE_WIDTH OW_SIZE /* in bytes */ > +#define F_SUBTILE_HEIGHT 4 /* in pixels */ > + > +static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp) > +{ > + int tile_base; > + int tile_x, tile_y; > + int swizzle, subtile; > + int pixel_size = bpp / 8; > + int pos; > + > + /* > + * Subtile remapping for F tile. Note that map[a]==b implies map[b]==a > + * so we can use the same table to tile and until. > + */ > + static const u8 f_subtile_map[] = { > + 0, 1, 2, 3, 8, 9, 10, 11, > + 4, 5, 6, 7, 12, 13, 14, 15, > + 16, 17, 18, 19, 24, 25, 26, 27, > + 20, 21, 22, 23, 28, 29, 30, 31, > + 32, 33, 34, 35, 40, 41, 42, 43, > + 36, 37, 38, 39, 44, 45, 46, 47, > + 48, 49, 50, 51, 56, 57, 58, 59, > + 52, 53, 54, 55, 60, 61, 62, 63 > + }; > + > + x *= pixel_size; > + /* > + * Where does the 4k tile start (in bytes)? This is the same for Y and > + * F so we can use the Y-tile algorithm to get to that point. > + */ > + tile_base = > + y / F_TILE_HEIGHT * stride * F_TILE_HEIGHT + > + x / F_TILE_WIDTH * 4096; > + > + /* Find pixel within tile */ > + tile_x = x % F_TILE_WIDTH; > + tile_y = y % F_TILE_HEIGHT; > + > + /* And figure out the subtile within the 4k tile */ > + subtile = tile_y / F_SUBTILE_HEIGHT * 8 + tile_x / F_SUBTILE_WIDTH; > + > + /* Swizzle the subtile number according to the bspec diagram */ > + swizzle = f_subtile_map[subtile]; > + > + /* Calculate new position */ > + pos = tile_base + > + swizzle * F_SUBTILE_SIZE + > + tile_y % F_SUBTILE_HEIGHT * OW_SIZE + > + tile_x % F_SUBTILE_WIDTH; > + > + GEM_BUG_ON(!IS_ALIGNED(pos, pixel_size)); > + > + return pos / pixel_size * 4; > +} > + > enum client_tiling { > CLIENT_TILING_LINEAR, > CLIENT_TILING_X, > CLIENT_TILING_Y, > + CLIENT_TILING_4, > CLIENT_NUM_TILING_TYPES > }; > > @@ -45,6 +107,36 @@ struct tiled_blits { > u32 height; > }; > > +static bool supports_x_tiling(const struct drm_i915_private *i915) > +{ > + int gen = GRAPHICS_VER(i915); > + > + if (gen < 12) > + return true; > + > + if (!HAS_LMEM(i915) || IS_DG1(i915)) > + return false; > + > + return true; > +} > + > +static bool fast_blit_ok(const struct blit_buffer *buf) > +{ > + int gen = GRAPHICS_VER(buf->vma->vm->i915); > + > + if (gen < 9) > + return false; > + > + if (gen < 12) > + return true; > + > + /* filter out platforms with unsupported X-tile support in fastblit */ > + if (buf->tiling == CLIENT_TILING_X && !supports_x_tiling(buf->vma->vm->i915)) > + return false; > + > + return true; > +} > + > static int prepare_blit(const struct tiled_blits *t, > struct blit_buffer *dst, > struct blit_buffer *src, > @@ -59,51 +151,103 @@ static int prepare_blit(const struct tiled_blits *t, > if (IS_ERR(cs)) > return PTR_ERR(cs); > > - *cs++ = MI_LOAD_REGISTER_IMM(1); > - *cs++ = i915_mmio_reg_offset(BCS_SWCTRL); > - cmd = (BCS_SRC_Y | BCS_DST_Y) << 16; > - if (src->tiling == CLIENT_TILING_Y) > - cmd |= BCS_SRC_Y; > - if (dst->tiling == CLIENT_TILING_Y) > - cmd |= BCS_DST_Y; > - *cs++ = cmd; > - > - cmd = MI_FLUSH_DW; > - if (ver >= 8) > - cmd++; > - *cs++ = cmd; > - *cs++ = 0; > - *cs++ = 0; > - *cs++ = 0; > - > - cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2); > - if (ver >= 8) > - cmd += 2; > - > - src_pitch = t->width * 4; > - if (src->tiling) { > - cmd |= XY_SRC_COPY_BLT_SRC_TILED; > - src_pitch /= 4; > - } > + if (fast_blit_ok(dst) && fast_blit_ok(src)) { > + struct intel_gt *gt = t->ce->engine->gt; > + u32 src_tiles = 0, dst_tiles = 0; > + u32 src_4t = 0, dst_4t = 0; > + > + /* Need to program BLIT_CCTL if it is not done previously > + * before using XY_FAST_COPY_BLT > + */ > + *cs++ = MI_LOAD_REGISTER_IMM(1); > + *cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base)); > + *cs++ = (BLIT_CCTL_SRC_MOCS(gt->mocs.uc_index) | > + BLIT_CCTL_DST_MOCS(gt->mocs.uc_index)); > + > + src_pitch = t->width; /* in dwords */ > + if (src->tiling == CLIENT_TILING_4) { > + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR); > + src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4; > + } else if (src->tiling == CLIENT_TILING_Y) { > + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR); > + } else if (src->tiling == CLIENT_TILING_X) { > + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X); > + } else { > + src_pitch *= 4; /* in bytes */ > + } > > - dst_pitch = t->width * 4; > - if (dst->tiling) { > - cmd |= XY_SRC_COPY_BLT_DST_TILED; > - dst_pitch /= 4; > - } > + dst_pitch = t->width; /* in dwords */ > + if (dst->tiling == CLIENT_TILING_4) { > + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR); > + dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4; > + } else if (dst->tiling == CLIENT_TILING_Y) { > + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR); > + } else if (dst->tiling == CLIENT_TILING_X) { > + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X); > + } else { > + dst_pitch *= 4; /* in bytes */ > + } > > - *cs++ = cmd; > - *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch; > - *cs++ = 0; > - *cs++ = t->height << 16 | t->width; > - *cs++ = lower_32_bits(dst->vma->node.start); > - if (use_64b_reloc) > + *cs++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2) | > + src_tiles | dst_tiles; > + *cs++ = src_4t | dst_4t | BLT_DEPTH_32 | dst_pitch; > + *cs++ = 0; > + *cs++ = t->height << 16 | t->width; > + *cs++ = lower_32_bits(dst->vma->node.start); > *cs++ = upper_32_bits(dst->vma->node.start); > - *cs++ = 0; > - *cs++ = src_pitch; > - *cs++ = lower_32_bits(src->vma->node.start); > - if (use_64b_reloc) > + *cs++ = 0; > + *cs++ = src_pitch; > + *cs++ = lower_32_bits(src->vma->node.start); > *cs++ = upper_32_bits(src->vma->node.start); > + } else { > + if (ver >= 6) { > + *cs++ = MI_LOAD_REGISTER_IMM(1); > + *cs++ = i915_mmio_reg_offset(BCS_SWCTRL); > + cmd = (BCS_SRC_Y | BCS_DST_Y) << 16; > + if (src->tiling == CLIENT_TILING_Y) > + cmd |= BCS_SRC_Y; > + if (dst->tiling == CLIENT_TILING_Y) > + cmd |= BCS_DST_Y; > + *cs++ = cmd; > + > + cmd = MI_FLUSH_DW; > + if (ver >= 8) > + cmd++; > + *cs++ = cmd; > + *cs++ = 0; > + *cs++ = 0; > + *cs++ = 0; > + } > + > + cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2); > + if (ver >= 8) > + cmd += 2; > + > + src_pitch = t->width * 4; > + if (src->tiling) { > + cmd |= XY_SRC_COPY_BLT_SRC_TILED; > + src_pitch /= 4; > + } > + > + dst_pitch = t->width * 4; > + if (dst->tiling) { > + cmd |= XY_SRC_COPY_BLT_DST_TILED; > + dst_pitch /= 4; > + } > + > + *cs++ = cmd; > + *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch; > + *cs++ = 0; > + *cs++ = t->height << 16 | t->width; > + *cs++ = lower_32_bits(dst->vma->node.start); > + if (use_64b_reloc) > + *cs++ = upper_32_bits(dst->vma->node.start); > + *cs++ = 0; > + *cs++ = src_pitch; > + *cs++ = lower_32_bits(src->vma->node.start); > + if (use_64b_reloc) > + *cs++ = upper_32_bits(src->vma->node.start); > + } > > *cs++ = MI_BATCH_BUFFER_END; > > @@ -181,7 +325,13 @@ static int tiled_blits_create_buffers(struct tiled_blits *t, > > t->buffers[i].vma = vma; > t->buffers[i].tiling = > - i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng); > + i915_prandom_u32_max_state(CLIENT_NUM_TILING_TYPES, prng); > + > + /* Platforms support either TileY or Tile4, not both */ > + if (HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_Y) > + t->buffers[i].tiling = CLIENT_TILING_4; > + else if (!HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_4) > + t->buffers[i].tiling = CLIENT_TILING_Y; > } > > return 0; > @@ -206,7 +356,8 @@ static u64 swizzle_bit(unsigned int bit, u64 offset) > static u64 tiled_offset(const struct intel_gt *gt, > u64 v, > unsigned int stride, > - enum client_tiling tiling) > + enum client_tiling tiling, > + int x_pos, int y_pos) > { > unsigned int swizzle; > u64 x, y; > @@ -216,7 +367,12 @@ static u64 tiled_offset(const struct intel_gt *gt, > > y = div64_u64_rem(v, stride, &x); > > - if (tiling == CLIENT_TILING_X) { > + if (tiling == CLIENT_TILING_4) { > + v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32); > + > + /* no swizzling for f-tiling */ > + swizzle = I915_BIT_6_SWIZZLE_NONE; > + } else if (tiling == CLIENT_TILING_X) { > v = div64_u64_rem(y, 8, &y) * stride * 8; > v += y * 512; > v += div64_u64_rem(x, 512, &x) << 12; > @@ -259,6 +415,7 @@ static const char *repr_tiling(enum client_tiling tiling) > case CLIENT_TILING_LINEAR: return "linear"; > case CLIENT_TILING_X: return "X"; > case CLIENT_TILING_Y: return "Y"; > + case CLIENT_TILING_4: return "F"; > default: return "unknown"; > } > } > @@ -284,7 +441,7 @@ static int verify_buffer(const struct tiled_blits *t, > } else { > u64 v = tiled_offset(buf->vma->vm->gt, > p * 4, t->width * 4, > - buf->tiling); > + buf->tiling, x, y); > > if (vaddr[v / sizeof(*vaddr)] != buf->start_val + p) > ret = -EINVAL; > @@ -504,6 +661,9 @@ static int tiled_blits_bounce(struct tiled_blits *t, struct rnd_state *prng) > if (err) > return err; > > + /* Simulating GTT eviction of the same buffer / layout */ > + t->buffers[2].tiling = t->buffers[0].tiling; > + > /* Reposition so that we overlap the old addresses, and slightly off */ > err = tiled_blit(t, > &t->buffers[2], t->hole + t->align, > diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > index 556bca3be804..246ab8f7bf57 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > @@ -236,6 +236,28 @@ > #define XY_FAST_COLOR_BLT_DW 16 > #define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21) > #define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31 > + > +#define XY_FAST_COPY_BLT_D0_SRC_TILING_MASK REG_GENMASK(21, 20) > +#define XY_FAST_COPY_BLT_D0_DST_TILING_MASK REG_GENMASK(14, 13) > +#define XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(mode) \ > + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_SRC_TILING_MASK, mode) > +#define XY_FAST_COPY_BLT_D0_DST_TILE_MODE(mode) \ > + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_DST_TILING_MASK, mode) > +#define LINEAR 0 > +#define TILE_X 0x1 > +#define XMAJOR 0x1 > +#define YMAJOR 0x2 > +#define TILE_64 0x3 > +#define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31) > +#define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30) > +#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0) > +#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8) > +/* Note: MOCS value = (index << 1) */ > +#define BLIT_CCTL_SRC_MOCS(idx) \ > + REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (idx) << 1) > +#define BLIT_CCTL_DST_MOCS(idx) \ > + REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (idx) << 1) > + > #define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22) > #define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22) > #define XY_SRC_COPY_BLT_CMD (2 << 29 | 0x53 << 22) > -- > 2.35.1 > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Update tiled blits selftest 2022-05-16 8:20 [Intel-gfx] [PATCH] drm/i915: Update tiled blits selftest Nirmoy Das ` (2 preceding siblings ...) 2022-05-24 8:16 ` [Intel-gfx] [PATCH] " Zbigniew Kempczyński @ 2022-05-24 11:56 ` Andrzej Hajda 2022-05-24 12:09 ` Das, Nirmoy 3 siblings, 1 reply; 6+ messages in thread From: Andrzej Hajda @ 2022-05-24 11:56 UTC (permalink / raw) To: Nirmoy Das, intel-gfx; +Cc: krishnaiah.bommu, matthew.auld, chris.p.wilson On 16.05.2022 10:20, Nirmoy Das wrote: > From: Bommu Krishnaiah <krishnaiah.bommu@intel.com> > > Update the selftest to include Tile 4 mode and switch to Tile 4 on > platforms that supports Tile 4 but no Tile Y and vice versa. > Also switch to XY_FAST_COPY_BLT on platforms that supports it. > > v4: update commit message to reflect the code changes properly. > v3: add a function to find X-tile availability for a platform. > v2: disable Tile X for iGPU in fastblit and > fix checkpath --strict warnings. > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5879 > Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com> > Co-developed-by: Nirmoy Das <nirmoy.das@intel.com> > Signed-off-by: Nirmoy Das <nirmoy.das@intel.com> > --- > .../i915/gem/selftests/i915_gem_client_blt.c | 250 ++++++++++++++---- > drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 22 ++ > 2 files changed, 227 insertions(+), 45 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c > index ddd0772fd828..3cfc621ef363 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c > @@ -6,6 +6,7 @@ > #include "i915_selftest.h" > > #include "gt/intel_context.h" > +#include "gt/intel_engine_regs.h" > #include "gt/intel_engine_user.h" > #include "gt/intel_gpu_commands.h" > #include "gt/intel_gt.h" > @@ -18,10 +19,71 @@ > #include "huge_gem_object.h" > #include "mock_context.h" > > +#define OW_SIZE 16 /* in bytes */ > +#define F_SUBTILE_SIZE 64 /* in bytes */ > +#define F_TILE_WIDTH 128 /* in bytes */ > +#define F_TILE_HEIGHT 32 /* in pixels */ > +#define F_SUBTILE_WIDTH OW_SIZE /* in bytes */ > +#define F_SUBTILE_HEIGHT 4 /* in pixels */ > + > +static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp) > +{ > + int tile_base; > + int tile_x, tile_y; > + int swizzle, subtile; > + int pixel_size = bpp / 8; > + int pos; > + > + /* > + * Subtile remapping for F tile. Note that map[a]==b implies map[b]==a > + * so we can use the same table to tile and until. > + */ > + static const u8 f_subtile_map[] = { > + 0, 1, 2, 3, 8, 9, 10, 11, > + 4, 5, 6, 7, 12, 13, 14, 15, > + 16, 17, 18, 19, 24, 25, 26, 27, > + 20, 21, 22, 23, 28, 29, 30, 31, > + 32, 33, 34, 35, 40, 41, 42, 43, > + 36, 37, 38, 39, 44, 45, 46, 47, > + 48, 49, 50, 51, 56, 57, 58, 59, > + 52, 53, 54, 55, 60, 61, 62, 63 > + }; f_subtile_map[i] == (i with swapped bits 2,3) but I do not know if there is nice C expression/core function to use here, (i & ^12u) | (( i & 4) << 1) | ((i & 8) >> 1) does not looks nice. > + > + x *= pixel_size; > + /* > + * Where does the 4k tile start (in bytes)? This is the same for Y and > + * F so we can use the Y-tile algorithm to get to that point. > + */ > + tile_base = > + y / F_TILE_HEIGHT * stride * F_TILE_HEIGHT + > + x / F_TILE_WIDTH * 4096; > + > + /* Find pixel within tile */ > + tile_x = x % F_TILE_WIDTH; > + tile_y = y % F_TILE_HEIGHT; > + > + /* And figure out the subtile within the 4k tile */ > + subtile = tile_y / F_SUBTILE_HEIGHT * 8 + tile_x / F_SUBTILE_WIDTH; > + > + /* Swizzle the subtile number according to the bspec diagram */ > + swizzle = f_subtile_map[subtile]; > + > + /* Calculate new position */ > + pos = tile_base + > + swizzle * F_SUBTILE_SIZE + > + tile_y % F_SUBTILE_HEIGHT * OW_SIZE + > + tile_x % F_SUBTILE_WIDTH; > + > + GEM_BUG_ON(!IS_ALIGNED(pos, pixel_size)); > + > + return pos / pixel_size * 4; > +} > + > enum client_tiling { > CLIENT_TILING_LINEAR, > CLIENT_TILING_X, > CLIENT_TILING_Y, > + CLIENT_TILING_4, > CLIENT_NUM_TILING_TYPES > }; > > @@ -45,6 +107,36 @@ struct tiled_blits { > u32 height; > }; > > +static bool supports_x_tiling(const struct drm_i915_private *i915) > +{ > + int gen = GRAPHICS_VER(i915); > + > + if (gen < 12) > + return true; Why gen variable? you can use expression directly. Anyway: Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Regards Andrzej > + > + if (!HAS_LMEM(i915) || IS_DG1(i915)) > + return false; > + > + return true; > +} > + > +static bool fast_blit_ok(const struct blit_buffer *buf) > +{ > + int gen = GRAPHICS_VER(buf->vma->vm->i915); > + > + if (gen < 9) > + return false; > + > + if (gen < 12) > + return true; > + > + /* filter out platforms with unsupported X-tile support in fastblit */ > + if (buf->tiling == CLIENT_TILING_X && !supports_x_tiling(buf->vma->vm->i915)) > + return false; > + > + return true; > +} > + > static int prepare_blit(const struct tiled_blits *t, > struct blit_buffer *dst, > struct blit_buffer *src, > @@ -59,51 +151,103 @@ static int prepare_blit(const struct tiled_blits *t, > if (IS_ERR(cs)) > return PTR_ERR(cs); > > - *cs++ = MI_LOAD_REGISTER_IMM(1); > - *cs++ = i915_mmio_reg_offset(BCS_SWCTRL); > - cmd = (BCS_SRC_Y | BCS_DST_Y) << 16; > - if (src->tiling == CLIENT_TILING_Y) > - cmd |= BCS_SRC_Y; > - if (dst->tiling == CLIENT_TILING_Y) > - cmd |= BCS_DST_Y; > - *cs++ = cmd; > - > - cmd = MI_FLUSH_DW; > - if (ver >= 8) > - cmd++; > - *cs++ = cmd; > - *cs++ = 0; > - *cs++ = 0; > - *cs++ = 0; > - > - cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2); > - if (ver >= 8) > - cmd += 2; > - > - src_pitch = t->width * 4; > - if (src->tiling) { > - cmd |= XY_SRC_COPY_BLT_SRC_TILED; > - src_pitch /= 4; > - } > + if (fast_blit_ok(dst) && fast_blit_ok(src)) { > + struct intel_gt *gt = t->ce->engine->gt; > + u32 src_tiles = 0, dst_tiles = 0; > + u32 src_4t = 0, dst_4t = 0; > + > + /* Need to program BLIT_CCTL if it is not done previously > + * before using XY_FAST_COPY_BLT > + */ > + *cs++ = MI_LOAD_REGISTER_IMM(1); > + *cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base)); > + *cs++ = (BLIT_CCTL_SRC_MOCS(gt->mocs.uc_index) | > + BLIT_CCTL_DST_MOCS(gt->mocs.uc_index)); > + > + src_pitch = t->width; /* in dwords */ > + if (src->tiling == CLIENT_TILING_4) { > + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR); > + src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4; > + } else if (src->tiling == CLIENT_TILING_Y) { > + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR); > + } else if (src->tiling == CLIENT_TILING_X) { > + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X); > + } else { > + src_pitch *= 4; /* in bytes */ > + } > > - dst_pitch = t->width * 4; > - if (dst->tiling) { > - cmd |= XY_SRC_COPY_BLT_DST_TILED; > - dst_pitch /= 4; > - } > + dst_pitch = t->width; /* in dwords */ > + if (dst->tiling == CLIENT_TILING_4) { > + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR); > + dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4; > + } else if (dst->tiling == CLIENT_TILING_Y) { > + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR); > + } else if (dst->tiling == CLIENT_TILING_X) { > + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X); > + } else { > + dst_pitch *= 4; /* in bytes */ > + } > > - *cs++ = cmd; > - *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch; > - *cs++ = 0; > - *cs++ = t->height << 16 | t->width; > - *cs++ = lower_32_bits(dst->vma->node.start); > - if (use_64b_reloc) > + *cs++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2) | > + src_tiles | dst_tiles; > + *cs++ = src_4t | dst_4t | BLT_DEPTH_32 | dst_pitch; > + *cs++ = 0; > + *cs++ = t->height << 16 | t->width; > + *cs++ = lower_32_bits(dst->vma->node.start); > *cs++ = upper_32_bits(dst->vma->node.start); > - *cs++ = 0; > - *cs++ = src_pitch; > - *cs++ = lower_32_bits(src->vma->node.start); > - if (use_64b_reloc) > + *cs++ = 0; > + *cs++ = src_pitch; > + *cs++ = lower_32_bits(src->vma->node.start); > *cs++ = upper_32_bits(src->vma->node.start); > + } else { > + if (ver >= 6) { > + *cs++ = MI_LOAD_REGISTER_IMM(1); > + *cs++ = i915_mmio_reg_offset(BCS_SWCTRL); > + cmd = (BCS_SRC_Y | BCS_DST_Y) << 16; > + if (src->tiling == CLIENT_TILING_Y) > + cmd |= BCS_SRC_Y; > + if (dst->tiling == CLIENT_TILING_Y) > + cmd |= BCS_DST_Y; > + *cs++ = cmd; > + > + cmd = MI_FLUSH_DW; > + if (ver >= 8) > + cmd++; > + *cs++ = cmd; > + *cs++ = 0; > + *cs++ = 0; > + *cs++ = 0; > + } > + > + cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2); > + if (ver >= 8) > + cmd += 2; > + > + src_pitch = t->width * 4; > + if (src->tiling) { > + cmd |= XY_SRC_COPY_BLT_SRC_TILED; > + src_pitch /= 4; > + } > + > + dst_pitch = t->width * 4; > + if (dst->tiling) { > + cmd |= XY_SRC_COPY_BLT_DST_TILED; > + dst_pitch /= 4; > + } > + > + *cs++ = cmd; > + *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch; > + *cs++ = 0; > + *cs++ = t->height << 16 | t->width; > + *cs++ = lower_32_bits(dst->vma->node.start); > + if (use_64b_reloc) > + *cs++ = upper_32_bits(dst->vma->node.start); > + *cs++ = 0; > + *cs++ = src_pitch; > + *cs++ = lower_32_bits(src->vma->node.start); > + if (use_64b_reloc) > + *cs++ = upper_32_bits(src->vma->node.start); > + } > > *cs++ = MI_BATCH_BUFFER_END; > > @@ -181,7 +325,13 @@ static int tiled_blits_create_buffers(struct tiled_blits *t, > > t->buffers[i].vma = vma; > t->buffers[i].tiling = > - i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng); > + i915_prandom_u32_max_state(CLIENT_NUM_TILING_TYPES, prng); > + > + /* Platforms support either TileY or Tile4, not both */ > + if (HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_Y) > + t->buffers[i].tiling = CLIENT_TILING_4; > + else if (!HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_4) > + t->buffers[i].tiling = CLIENT_TILING_Y; > } > > return 0; > @@ -206,7 +356,8 @@ static u64 swizzle_bit(unsigned int bit, u64 offset) > static u64 tiled_offset(const struct intel_gt *gt, > u64 v, > unsigned int stride, > - enum client_tiling tiling) > + enum client_tiling tiling, > + int x_pos, int y_pos) > { > unsigned int swizzle; > u64 x, y; > @@ -216,7 +367,12 @@ static u64 tiled_offset(const struct intel_gt *gt, > > y = div64_u64_rem(v, stride, &x); > > - if (tiling == CLIENT_TILING_X) { > + if (tiling == CLIENT_TILING_4) { > + v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32); > + > + /* no swizzling for f-tiling */ > + swizzle = I915_BIT_6_SWIZZLE_NONE; > + } else if (tiling == CLIENT_TILING_X) { > v = div64_u64_rem(y, 8, &y) * stride * 8; > v += y * 512; > v += div64_u64_rem(x, 512, &x) << 12; > @@ -259,6 +415,7 @@ static const char *repr_tiling(enum client_tiling tiling) > case CLIENT_TILING_LINEAR: return "linear"; > case CLIENT_TILING_X: return "X"; > case CLIENT_TILING_Y: return "Y"; > + case CLIENT_TILING_4: return "F"; > default: return "unknown"; > } > } > @@ -284,7 +441,7 @@ static int verify_buffer(const struct tiled_blits *t, > } else { > u64 v = tiled_offset(buf->vma->vm->gt, > p * 4, t->width * 4, > - buf->tiling); > + buf->tiling, x, y); > > if (vaddr[v / sizeof(*vaddr)] != buf->start_val + p) > ret = -EINVAL; > @@ -504,6 +661,9 @@ static int tiled_blits_bounce(struct tiled_blits *t, struct rnd_state *prng) > if (err) > return err; > > + /* Simulating GTT eviction of the same buffer / layout */ > + t->buffers[2].tiling = t->buffers[0].tiling; > + > /* Reposition so that we overlap the old addresses, and slightly off */ > err = tiled_blit(t, > &t->buffers[2], t->hole + t->align, > diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > index 556bca3be804..246ab8f7bf57 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > @@ -236,6 +236,28 @@ > #define XY_FAST_COLOR_BLT_DW 16 > #define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21) > #define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31 > + > +#define XY_FAST_COPY_BLT_D0_SRC_TILING_MASK REG_GENMASK(21, 20) > +#define XY_FAST_COPY_BLT_D0_DST_TILING_MASK REG_GENMASK(14, 13) > +#define XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(mode) \ > + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_SRC_TILING_MASK, mode) > +#define XY_FAST_COPY_BLT_D0_DST_TILE_MODE(mode) \ > + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_DST_TILING_MASK, mode) > +#define LINEAR 0 > +#define TILE_X 0x1 > +#define XMAJOR 0x1 > +#define YMAJOR 0x2 > +#define TILE_64 0x3 > +#define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31) > +#define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30) > +#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0) > +#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8) > +/* Note: MOCS value = (index << 1) */ > +#define BLIT_CCTL_SRC_MOCS(idx) \ > + REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (idx) << 1) > +#define BLIT_CCTL_DST_MOCS(idx) \ > + REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (idx) << 1) > + > #define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22) > #define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22) > #define XY_SRC_COPY_BLT_CMD (2 << 29 | 0x53 << 22) ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Update tiled blits selftest 2022-05-24 11:56 ` Andrzej Hajda @ 2022-05-24 12:09 ` Das, Nirmoy 0 siblings, 0 replies; 6+ messages in thread From: Das, Nirmoy @ 2022-05-24 12:09 UTC (permalink / raw) To: Andrzej Hajda, intel-gfx; +Cc: krishnaiah.bommu, matthew.auld, chris.p.wilson Hi Andrzej, On 5/24/2022 1:56 PM, Andrzej Hajda wrote: > On 16.05.2022 10:20, Nirmoy Das wrote: >> From: Bommu Krishnaiah <krishnaiah.bommu@intel.com> >> >> Update the selftest to include Tile 4 mode and switch to Tile 4 on >> platforms that supports Tile 4 but no Tile Y and vice versa. >> Also switch to XY_FAST_COPY_BLT on platforms that supports it. >> >> v4: update commit message to reflect the code changes properly. >> v3: add a function to find X-tile availability for a platform. >> v2: disable Tile X for iGPU in fastblit and >> fix checkpath --strict warnings. >> >> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5879 >> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com> >> Co-developed-by: Nirmoy Das <nirmoy.das@intel.com> >> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com> >> --- >> .../i915/gem/selftests/i915_gem_client_blt.c | 250 ++++++++++++++---- >> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 22 ++ >> 2 files changed, 227 insertions(+), 45 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c >> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c >> index ddd0772fd828..3cfc621ef363 100644 >> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c >> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c >> @@ -6,6 +6,7 @@ >> #include "i915_selftest.h" >> #include "gt/intel_context.h" >> +#include "gt/intel_engine_regs.h" >> #include "gt/intel_engine_user.h" >> #include "gt/intel_gpu_commands.h" >> #include "gt/intel_gt.h" >> @@ -18,10 +19,71 @@ >> #include "huge_gem_object.h" >> #include "mock_context.h" >> +#define OW_SIZE 16 /* in bytes */ >> +#define F_SUBTILE_SIZE 64 /* in bytes */ >> +#define F_TILE_WIDTH 128 /* in bytes */ >> +#define F_TILE_HEIGHT 32 /* in pixels */ >> +#define F_SUBTILE_WIDTH OW_SIZE /* in bytes */ >> +#define F_SUBTILE_HEIGHT 4 /* in pixels */ >> + >> +static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp) >> +{ >> + int tile_base; >> + int tile_x, tile_y; >> + int swizzle, subtile; >> + int pixel_size = bpp / 8; >> + int pos; >> + >> + /* >> + * Subtile remapping for F tile. Note that map[a]==b implies >> map[b]==a >> + * so we can use the same table to tile and until. >> + */ >> + static const u8 f_subtile_map[] = { >> + 0, 1, 2, 3, 8, 9, 10, 11, >> + 4, 5, 6, 7, 12, 13, 14, 15, >> + 16, 17, 18, 19, 24, 25, 26, 27, >> + 20, 21, 22, 23, 28, 29, 30, 31, >> + 32, 33, 34, 35, 40, 41, 42, 43, >> + 36, 37, 38, 39, 44, 45, 46, 47, >> + 48, 49, 50, 51, 56, 57, 58, 59, >> + 52, 53, 54, 55, 60, 61, 62, 63 >> + }; > > f_subtile_map[i] == (i with swapped bits 2,3) This is looks neat but can't think of any nice C expression either. > > but I do not know if there is nice C expression/core function to use > here, > (i & ^12u) | (( i & 4) << 1) | ((i & 8) >> 1) > does not looks nice. > > >> + >> + x *= pixel_size; >> + /* >> + * Where does the 4k tile start (in bytes)? This is the same >> for Y and >> + * F so we can use the Y-tile algorithm to get to that point. >> + */ >> + tile_base = >> + y / F_TILE_HEIGHT * stride * F_TILE_HEIGHT + >> + x / F_TILE_WIDTH * 4096; >> + >> + /* Find pixel within tile */ >> + tile_x = x % F_TILE_WIDTH; >> + tile_y = y % F_TILE_HEIGHT; >> + >> + /* And figure out the subtile within the 4k tile */ >> + subtile = tile_y / F_SUBTILE_HEIGHT * 8 + tile_x / F_SUBTILE_WIDTH; >> + >> + /* Swizzle the subtile number according to the bspec diagram */ >> + swizzle = f_subtile_map[subtile]; >> + >> + /* Calculate new position */ >> + pos = tile_base + >> + swizzle * F_SUBTILE_SIZE + >> + tile_y % F_SUBTILE_HEIGHT * OW_SIZE + >> + tile_x % F_SUBTILE_WIDTH; >> + >> + GEM_BUG_ON(!IS_ALIGNED(pos, pixel_size)); >> + >> + return pos / pixel_size * 4; >> +} >> + >> enum client_tiling { >> CLIENT_TILING_LINEAR, >> CLIENT_TILING_X, >> CLIENT_TILING_Y, >> + CLIENT_TILING_4, >> CLIENT_NUM_TILING_TYPES >> }; >> @@ -45,6 +107,36 @@ struct tiled_blits { >> u32 height; >> }; >> +static bool supports_x_tiling(const struct drm_i915_private *i915) >> +{ >> + int gen = GRAPHICS_VER(i915); >> + >> + if (gen < 12) >> + return true; > > Why gen variable? you can use expression directly. Oversight from my side :/ Matt merged this an hour ago. I can post a small patch to fix that up. > > Anyway: > > Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Thanks, Nirmoy > > Regards > Andrzej > > > >> + >> + if (!HAS_LMEM(i915) || IS_DG1(i915)) >> + return false; >> + >> + return true; >> +} >> + >> +static bool fast_blit_ok(const struct blit_buffer *buf) >> +{ >> + int gen = GRAPHICS_VER(buf->vma->vm->i915); >> + >> + if (gen < 9) >> + return false; >> + >> + if (gen < 12) >> + return true; >> + >> + /* filter out platforms with unsupported X-tile support in >> fastblit */ >> + if (buf->tiling == CLIENT_TILING_X && >> !supports_x_tiling(buf->vma->vm->i915)) >> + return false; >> + >> + return true; >> +} >> + >> static int prepare_blit(const struct tiled_blits *t, >> struct blit_buffer *dst, >> struct blit_buffer *src, >> @@ -59,51 +151,103 @@ static int prepare_blit(const struct >> tiled_blits *t, >> if (IS_ERR(cs)) >> return PTR_ERR(cs); >> - *cs++ = MI_LOAD_REGISTER_IMM(1); >> - *cs++ = i915_mmio_reg_offset(BCS_SWCTRL); >> - cmd = (BCS_SRC_Y | BCS_DST_Y) << 16; >> - if (src->tiling == CLIENT_TILING_Y) >> - cmd |= BCS_SRC_Y; >> - if (dst->tiling == CLIENT_TILING_Y) >> - cmd |= BCS_DST_Y; >> - *cs++ = cmd; >> - >> - cmd = MI_FLUSH_DW; >> - if (ver >= 8) >> - cmd++; >> - *cs++ = cmd; >> - *cs++ = 0; >> - *cs++ = 0; >> - *cs++ = 0; >> - >> - cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2); >> - if (ver >= 8) >> - cmd += 2; >> - >> - src_pitch = t->width * 4; >> - if (src->tiling) { >> - cmd |= XY_SRC_COPY_BLT_SRC_TILED; >> - src_pitch /= 4; >> - } >> + if (fast_blit_ok(dst) && fast_blit_ok(src)) { >> + struct intel_gt *gt = t->ce->engine->gt; >> + u32 src_tiles = 0, dst_tiles = 0; >> + u32 src_4t = 0, dst_4t = 0; >> + >> + /* Need to program BLIT_CCTL if it is not done previously >> + * before using XY_FAST_COPY_BLT >> + */ >> + *cs++ = MI_LOAD_REGISTER_IMM(1); >> + *cs++ = >> i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base)); >> + *cs++ = (BLIT_CCTL_SRC_MOCS(gt->mocs.uc_index) | >> + BLIT_CCTL_DST_MOCS(gt->mocs.uc_index)); >> + >> + src_pitch = t->width; /* in dwords */ >> + if (src->tiling == CLIENT_TILING_4) { >> + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR); >> + src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4; >> + } else if (src->tiling == CLIENT_TILING_Y) { >> + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR); >> + } else if (src->tiling == CLIENT_TILING_X) { >> + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X); >> + } else { >> + src_pitch *= 4; /* in bytes */ >> + } >> - dst_pitch = t->width * 4; >> - if (dst->tiling) { >> - cmd |= XY_SRC_COPY_BLT_DST_TILED; >> - dst_pitch /= 4; >> - } >> + dst_pitch = t->width; /* in dwords */ >> + if (dst->tiling == CLIENT_TILING_4) { >> + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR); >> + dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4; >> + } else if (dst->tiling == CLIENT_TILING_Y) { >> + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR); >> + } else if (dst->tiling == CLIENT_TILING_X) { >> + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X); >> + } else { >> + dst_pitch *= 4; /* in bytes */ >> + } >> - *cs++ = cmd; >> - *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch; >> - *cs++ = 0; >> - *cs++ = t->height << 16 | t->width; >> - *cs++ = lower_32_bits(dst->vma->node.start); >> - if (use_64b_reloc) >> + *cs++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2) | >> + src_tiles | dst_tiles; >> + *cs++ = src_4t | dst_4t | BLT_DEPTH_32 | dst_pitch; >> + *cs++ = 0; >> + *cs++ = t->height << 16 | t->width; >> + *cs++ = lower_32_bits(dst->vma->node.start); >> *cs++ = upper_32_bits(dst->vma->node.start); >> - *cs++ = 0; >> - *cs++ = src_pitch; >> - *cs++ = lower_32_bits(src->vma->node.start); >> - if (use_64b_reloc) >> + *cs++ = 0; >> + *cs++ = src_pitch; >> + *cs++ = lower_32_bits(src->vma->node.start); >> *cs++ = upper_32_bits(src->vma->node.start); >> + } else { >> + if (ver >= 6) { >> + *cs++ = MI_LOAD_REGISTER_IMM(1); >> + *cs++ = i915_mmio_reg_offset(BCS_SWCTRL); >> + cmd = (BCS_SRC_Y | BCS_DST_Y) << 16; >> + if (src->tiling == CLIENT_TILING_Y) >> + cmd |= BCS_SRC_Y; >> + if (dst->tiling == CLIENT_TILING_Y) >> + cmd |= BCS_DST_Y; >> + *cs++ = cmd; >> + >> + cmd = MI_FLUSH_DW; >> + if (ver >= 8) >> + cmd++; >> + *cs++ = cmd; >> + *cs++ = 0; >> + *cs++ = 0; >> + *cs++ = 0; >> + } >> + >> + cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2); >> + if (ver >= 8) >> + cmd += 2; >> + >> + src_pitch = t->width * 4; >> + if (src->tiling) { >> + cmd |= XY_SRC_COPY_BLT_SRC_TILED; >> + src_pitch /= 4; >> + } >> + >> + dst_pitch = t->width * 4; >> + if (dst->tiling) { >> + cmd |= XY_SRC_COPY_BLT_DST_TILED; >> + dst_pitch /= 4; >> + } >> + >> + *cs++ = cmd; >> + *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch; >> + *cs++ = 0; >> + *cs++ = t->height << 16 | t->width; >> + *cs++ = lower_32_bits(dst->vma->node.start); >> + if (use_64b_reloc) >> + *cs++ = upper_32_bits(dst->vma->node.start); >> + *cs++ = 0; >> + *cs++ = src_pitch; >> + *cs++ = lower_32_bits(src->vma->node.start); >> + if (use_64b_reloc) >> + *cs++ = upper_32_bits(src->vma->node.start); >> + } >> *cs++ = MI_BATCH_BUFFER_END; >> @@ -181,7 +325,13 @@ static int tiled_blits_create_buffers(struct >> tiled_blits *t, >> t->buffers[i].vma = vma; >> t->buffers[i].tiling = >> - i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng); >> + i915_prandom_u32_max_state(CLIENT_NUM_TILING_TYPES, prng); >> + >> + /* Platforms support either TileY or Tile4, not both */ >> + if (HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_Y) >> + t->buffers[i].tiling = CLIENT_TILING_4; >> + else if (!HAS_4TILE(i915) && t->buffers[i].tiling == >> CLIENT_TILING_4) >> + t->buffers[i].tiling = CLIENT_TILING_Y; >> } >> return 0; >> @@ -206,7 +356,8 @@ static u64 swizzle_bit(unsigned int bit, u64 offset) >> static u64 tiled_offset(const struct intel_gt *gt, >> u64 v, >> unsigned int stride, >> - enum client_tiling tiling) >> + enum client_tiling tiling, >> + int x_pos, int y_pos) >> { >> unsigned int swizzle; >> u64 x, y; >> @@ -216,7 +367,12 @@ static u64 tiled_offset(const struct intel_gt *gt, >> y = div64_u64_rem(v, stride, &x); >> - if (tiling == CLIENT_TILING_X) { >> + if (tiling == CLIENT_TILING_4) { >> + v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32); >> + >> + /* no swizzling for f-tiling */ >> + swizzle = I915_BIT_6_SWIZZLE_NONE; >> + } else if (tiling == CLIENT_TILING_X) { >> v = div64_u64_rem(y, 8, &y) * stride * 8; >> v += y * 512; >> v += div64_u64_rem(x, 512, &x) << 12; >> @@ -259,6 +415,7 @@ static const char *repr_tiling(enum client_tiling >> tiling) >> case CLIENT_TILING_LINEAR: return "linear"; >> case CLIENT_TILING_X: return "X"; >> case CLIENT_TILING_Y: return "Y"; >> + case CLIENT_TILING_4: return "F"; >> default: return "unknown"; >> } >> } >> @@ -284,7 +441,7 @@ static int verify_buffer(const struct tiled_blits >> *t, >> } else { >> u64 v = tiled_offset(buf->vma->vm->gt, >> p * 4, t->width * 4, >> - buf->tiling); >> + buf->tiling, x, y); >> if (vaddr[v / sizeof(*vaddr)] != buf->start_val + p) >> ret = -EINVAL; >> @@ -504,6 +661,9 @@ static int tiled_blits_bounce(struct tiled_blits >> *t, struct rnd_state *prng) >> if (err) >> return err; >> + /* Simulating GTT eviction of the same buffer / layout */ >> + t->buffers[2].tiling = t->buffers[0].tiling; >> + >> /* Reposition so that we overlap the old addresses, and >> slightly off */ >> err = tiled_blit(t, >> &t->buffers[2], t->hole + t->align, >> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h >> b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h >> index 556bca3be804..246ab8f7bf57 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h >> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h >> @@ -236,6 +236,28 @@ >> #define XY_FAST_COLOR_BLT_DW 16 >> #define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21) >> #define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31 >> + >> +#define XY_FAST_COPY_BLT_D0_SRC_TILING_MASK REG_GENMASK(21, 20) >> +#define XY_FAST_COPY_BLT_D0_DST_TILING_MASK REG_GENMASK(14, 13) >> +#define XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(mode) \ >> + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_SRC_TILING_MASK, mode) >> +#define XY_FAST_COPY_BLT_D0_DST_TILE_MODE(mode) \ >> + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_DST_TILING_MASK, mode) >> +#define LINEAR 0 >> +#define TILE_X 0x1 >> +#define XMAJOR 0x1 >> +#define YMAJOR 0x2 >> +#define TILE_64 0x3 >> +#define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31) >> +#define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30) >> +#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0) >> +#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8) >> +/* Note: MOCS value = (index << 1) */ >> +#define BLIT_CCTL_SRC_MOCS(idx) \ >> + REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (idx) << 1) >> +#define BLIT_CCTL_DST_MOCS(idx) \ >> + REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (idx) << 1) >> + >> #define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22) >> #define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22) >> #define XY_SRC_COPY_BLT_CMD (2 << 29 | 0x53 << 22) > ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-05-24 12:10 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-05-16 8:20 [Intel-gfx] [PATCH] drm/i915: Update tiled blits selftest Nirmoy Das 2022-05-16 9:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork 2022-05-16 11:06 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2022-05-24 8:16 ` [Intel-gfx] [PATCH] " Zbigniew Kempczyński 2022-05-24 11:56 ` Andrzej Hajda 2022-05-24 12:09 ` Das, Nirmoy
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