* [PATCH v2 0/6] i915: SSEU handling updates
@ 2022-05-17 3:19 ` Matt Roper
0 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2022-05-17 3:19 UTC (permalink / raw)
To: intel-gfx; +Cc: tvrtko.ursulin, dri-devel
This series reworks i915's internal handling of slice/subslice/EU (SSEU)
data to represent platforms like Xe_HP in a more natural manner and to
prepare for future platforms where the masks will need to grow in size.
One key idea of this series is that although we have a fixed ABI to
convey SSEU data to userspace (i.e., multiple u8[] arrays with data
stored at different strides), we don't need to use this cumbersome
format for the driver's own internal storage. As long as we can convert
into the uapi form properly when responding to the I915_QUERY ioctl,
it's preferable to use an internal storage format that's easier for the
driver to work with.
Another key point here is that we're reaching the point where subslice
(DSS) masks will soon not fit within simple u32/u64 integer values.
Xe_HP SDV and DG2 platforms today have subslice (DSS) masks that are 32
bits, which maxes out the current storage of a u32. With PVC the masks
are represented by a pair of 32-bit registers, requiring a bump up to at
least 64-bits of storage internally. We could switch to u64 for that in
the short term, but since we already know that upcoming architectures
intend to provide DSS fuse bits via three or more registers it's best to
switch to a representation that's more future-proof but still easy to
work with in the driver code. To accomodate this, we start storing our
subslice mask for Xe_HP and beyond in a new typedef that can be
processed by the linux/bitmap.h operations.
Finally, since no userspace for Xe_HP or beyond is using the legacy
I915_GETPARAM ioctl lookups for I915_PARAM_SLICE_MASK and
I915_PARAM_SUBSLICE_MASK (since they've migrated to the more flexible
I915_QUERY ioctl that can return more than a simple u32 value), we take
the opportunity to officially drop support for those GETPARAM lookups on
modern platforms. Maintaining support for these GETPARAM lookups don't
make sense for a number of reasons:
* Traditional slices no longer exist, and newer ideas like gslices,
cslices, mslices, etc. aren't something userspace needs to query
since it can be inferred from other information.
* The GETPARAM ioctl doesn't have a way to distinguish between geometry
subslice masks and compute subslice masks, which are distinct on
Xe_HP and beyond.
* The I915_GETPARAM ioctl is limited to returning a 32-bit value, so
when subslice masks begin to exceed 32-bits (on PVC), it simply can't
return the entire mask.
* The GETPARAM ioctl doesn't have a way to give sensible information
for multi-tile devices.
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Matt Roper (6):
drm/i915/xehp: Use separate sseu init function
drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
drm/i915/sseu: Simplify gen11+ SSEU handling
drm/i915/sseu: Don't try to store EU mask internally in UAPI format
drm/i915/sseu: Disassociate internal subslice mask representation from
uapi
drm/i915/pvc: Add SSEU changes
drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 12 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_sseu.c | 428 ++++++++++++-------
drivers/gpu/drm/i915/gt/intel_sseu.h | 90 ++--
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_getparam.c | 11 +-
drivers/gpu/drm/i915/i915_pci.c | 3 +-
drivers/gpu/drm/i915/i915_query.c | 16 +-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
13 files changed, 376 insertions(+), 251 deletions(-)
--
2.35.3
^ permalink raw reply [flat|nested] 43+ messages in thread
* [Intel-gfx] [PATCH v2 0/6] i915: SSEU handling updates
@ 2022-05-17 3:19 ` Matt Roper
0 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2022-05-17 3:19 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
This series reworks i915's internal handling of slice/subslice/EU (SSEU)
data to represent platforms like Xe_HP in a more natural manner and to
prepare for future platforms where the masks will need to grow in size.
One key idea of this series is that although we have a fixed ABI to
convey SSEU data to userspace (i.e., multiple u8[] arrays with data
stored at different strides), we don't need to use this cumbersome
format for the driver's own internal storage. As long as we can convert
into the uapi form properly when responding to the I915_QUERY ioctl,
it's preferable to use an internal storage format that's easier for the
driver to work with.
Another key point here is that we're reaching the point where subslice
(DSS) masks will soon not fit within simple u32/u64 integer values.
Xe_HP SDV and DG2 platforms today have subslice (DSS) masks that are 32
bits, which maxes out the current storage of a u32. With PVC the masks
are represented by a pair of 32-bit registers, requiring a bump up to at
least 64-bits of storage internally. We could switch to u64 for that in
the short term, but since we already know that upcoming architectures
intend to provide DSS fuse bits via three or more registers it's best to
switch to a representation that's more future-proof but still easy to
work with in the driver code. To accomodate this, we start storing our
subslice mask for Xe_HP and beyond in a new typedef that can be
processed by the linux/bitmap.h operations.
Finally, since no userspace for Xe_HP or beyond is using the legacy
I915_GETPARAM ioctl lookups for I915_PARAM_SLICE_MASK and
I915_PARAM_SUBSLICE_MASK (since they've migrated to the more flexible
I915_QUERY ioctl that can return more than a simple u32 value), we take
the opportunity to officially drop support for those GETPARAM lookups on
modern platforms. Maintaining support for these GETPARAM lookups don't
make sense for a number of reasons:
* Traditional slices no longer exist, and newer ideas like gslices,
cslices, mslices, etc. aren't something userspace needs to query
since it can be inferred from other information.
* The GETPARAM ioctl doesn't have a way to distinguish between geometry
subslice masks and compute subslice masks, which are distinct on
Xe_HP and beyond.
* The I915_GETPARAM ioctl is limited to returning a 32-bit value, so
when subslice masks begin to exceed 32-bits (on PVC), it simply can't
return the entire mask.
* The GETPARAM ioctl doesn't have a way to give sensible information
for multi-tile devices.
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Matt Roper (6):
drm/i915/xehp: Use separate sseu init function
drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
drm/i915/sseu: Simplify gen11+ SSEU handling
drm/i915/sseu: Don't try to store EU mask internally in UAPI format
drm/i915/sseu: Disassociate internal subslice mask representation from
uapi
drm/i915/pvc: Add SSEU changes
drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 12 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_sseu.c | 428 ++++++++++++-------
drivers/gpu/drm/i915/gt/intel_sseu.h | 90 ++--
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_getparam.c | 11 +-
drivers/gpu/drm/i915/i915_pci.c | 3 +-
drivers/gpu/drm/i915/i915_query.c | 16 +-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
13 files changed, 376 insertions(+), 251 deletions(-)
--
2.35.3
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v2 1/6] drm/i915/xehp: Use separate sseu init function
2022-05-17 3:19 ` [Intel-gfx] " Matt Roper
@ 2022-05-17 3:20 ` Matt Roper
-1 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2022-05-17 3:20 UTC (permalink / raw)
To: intel-gfx; +Cc: tvrtko.ursulin, dri-devel
Xe_HP has enough fundamental differences from previous platforms that it
makes sense to use a separate SSEU init function to keep things
straightforward and easy to understand. We'll also add a has_xehp_dss
flag to the SSEU structure that will be used by other upcoming changes.
v2:
- Add has_xehp_dss flag
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 86 ++++++++++++++++------------
drivers/gpu/drm/i915/gt/intel_sseu.h | 5 ++
2 files changed, 54 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index fdd25691beda..b5fd479a7b85 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -169,13 +169,43 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, u8 s_en,
sseu->eu_total = compute_eu_total(sseu);
}
-static void gen12_sseu_info_init(struct intel_gt *gt)
+static void xehp_sseu_info_init(struct intel_gt *gt)
{
struct sseu_dev_info *sseu = >->info.sseu;
struct intel_uncore *uncore = gt->uncore;
u32 g_dss_en, c_dss_en = 0;
u16 eu_en = 0;
u8 eu_en_fuse;
+ int eu;
+
+ /*
+ * The concept of slice has been removed in Xe_HP. To be compatible
+ * with prior generations, assume a single slice across the entire
+ * device. Then calculate out the DSS for each workload type within
+ * that software slice.
+ */
+ intel_sseu_set_info(sseu, 1, 32, 16);
+ sseu->has_xehp_dss = 1;
+
+ g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
+ c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
+
+ eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
+
+ for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
+ if (eu_en_fuse & BIT(eu))
+ eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
+
+ gen11_compute_sseu_info(sseu, 0x1, g_dss_en, c_dss_en, eu_en);
+}
+
+static void gen12_sseu_info_init(struct intel_gt *gt)
+{
+ struct sseu_dev_info *sseu = >->info.sseu;
+ struct intel_uncore *uncore = gt->uncore;
+ u32 g_dss_en;
+ u16 eu_en = 0;
+ u8 eu_en_fuse;
u8 s_en;
int eu;
@@ -183,43 +213,23 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
* Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS.
* Instead of splitting these, provide userspace with an array
* of DSS to more closely represent the hardware resource.
- *
- * In addition, the concept of slice has been removed in Xe_HP.
- * To be compatible with prior generations, assume a single slice
- * across the entire device. Then calculate out the DSS for each
- * workload type within that software slice.
*/
- if (IS_DG2(gt->i915) || IS_XEHPSDV(gt->i915))
- intel_sseu_set_info(sseu, 1, 32, 16);
- else
- intel_sseu_set_info(sseu, 1, 6, 16);
+ intel_sseu_set_info(sseu, 1, 6, 16);
- /*
- * As mentioned above, Xe_HP does not have the concept of a slice.
- * Enable one for software backwards compatibility.
- */
- if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
- s_en = 0x1;
- else
- s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
- GEN11_GT_S_ENA_MASK;
+ s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
+ GEN11_GT_S_ENA_MASK;
g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
- if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
- c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
/* one bit per pair of EUs */
- if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
- eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
- else
- eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
- GEN11_EU_DIS_MASK);
+ eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
+ GEN11_EU_DIS_MASK);
for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, s_en, g_dss_en, c_dss_en, eu_en);
+ gen11_compute_sseu_info(sseu, s_en, g_dss_en, 0, eu_en);
/* TGL only supports slice-level power gating */
sseu->has_slice_pg = 1;
@@ -574,18 +584,20 @@ void intel_sseu_info_init(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
- if (IS_HASWELL(i915))
- hsw_sseu_info_init(gt);
- else if (IS_CHERRYVIEW(i915))
- cherryview_sseu_info_init(gt);
- else if (IS_BROADWELL(i915))
- bdw_sseu_info_init(gt);
- else if (GRAPHICS_VER(i915) == 9)
- gen9_sseu_info_init(gt);
- else if (GRAPHICS_VER(i915) == 11)
- gen11_sseu_info_init(gt);
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ xehp_sseu_info_init(gt);
else if (GRAPHICS_VER(i915) >= 12)
gen12_sseu_info_init(gt);
+ else if (GRAPHICS_VER(i915) >= 11)
+ gen11_sseu_info_init(gt);
+ else if (GRAPHICS_VER(i915) >= 9)
+ gen9_sseu_info_init(gt);
+ else if (IS_BROADWELL(i915))
+ bdw_sseu_info_init(gt);
+ else if (IS_CHERRYVIEW(i915))
+ cherryview_sseu_info_init(gt);
+ else if (IS_HASWELL(i915))
+ hsw_sseu_info_init(gt);
}
u32 intel_sseu_make_rpcs(struct intel_gt *gt,
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 5c078df4729c..4a041f9dc490 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -66,6 +66,11 @@ struct sseu_dev_info {
u8 has_slice_pg:1;
u8 has_subslice_pg:1;
u8 has_eu_pg:1;
+ /*
+ * For Xe_HP and beyond, the hardware no longer has traditional slices
+ * so we just report the entire DSS pool under a fake "slice 0."
+ */
+ u8 has_xehp_dss:1;
/* Topology fields */
u8 max_slices;
--
2.35.3
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [Intel-gfx] [PATCH v2 1/6] drm/i915/xehp: Use separate sseu init function
@ 2022-05-17 3:20 ` Matt Roper
0 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2022-05-17 3:20 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Xe_HP has enough fundamental differences from previous platforms that it
makes sense to use a separate SSEU init function to keep things
straightforward and easy to understand. We'll also add a has_xehp_dss
flag to the SSEU structure that will be used by other upcoming changes.
v2:
- Add has_xehp_dss flag
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 86 ++++++++++++++++------------
drivers/gpu/drm/i915/gt/intel_sseu.h | 5 ++
2 files changed, 54 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index fdd25691beda..b5fd479a7b85 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -169,13 +169,43 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, u8 s_en,
sseu->eu_total = compute_eu_total(sseu);
}
-static void gen12_sseu_info_init(struct intel_gt *gt)
+static void xehp_sseu_info_init(struct intel_gt *gt)
{
struct sseu_dev_info *sseu = >->info.sseu;
struct intel_uncore *uncore = gt->uncore;
u32 g_dss_en, c_dss_en = 0;
u16 eu_en = 0;
u8 eu_en_fuse;
+ int eu;
+
+ /*
+ * The concept of slice has been removed in Xe_HP. To be compatible
+ * with prior generations, assume a single slice across the entire
+ * device. Then calculate out the DSS for each workload type within
+ * that software slice.
+ */
+ intel_sseu_set_info(sseu, 1, 32, 16);
+ sseu->has_xehp_dss = 1;
+
+ g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
+ c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
+
+ eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
+
+ for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
+ if (eu_en_fuse & BIT(eu))
+ eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
+
+ gen11_compute_sseu_info(sseu, 0x1, g_dss_en, c_dss_en, eu_en);
+}
+
+static void gen12_sseu_info_init(struct intel_gt *gt)
+{
+ struct sseu_dev_info *sseu = >->info.sseu;
+ struct intel_uncore *uncore = gt->uncore;
+ u32 g_dss_en;
+ u16 eu_en = 0;
+ u8 eu_en_fuse;
u8 s_en;
int eu;
@@ -183,43 +213,23 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
* Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS.
* Instead of splitting these, provide userspace with an array
* of DSS to more closely represent the hardware resource.
- *
- * In addition, the concept of slice has been removed in Xe_HP.
- * To be compatible with prior generations, assume a single slice
- * across the entire device. Then calculate out the DSS for each
- * workload type within that software slice.
*/
- if (IS_DG2(gt->i915) || IS_XEHPSDV(gt->i915))
- intel_sseu_set_info(sseu, 1, 32, 16);
- else
- intel_sseu_set_info(sseu, 1, 6, 16);
+ intel_sseu_set_info(sseu, 1, 6, 16);
- /*
- * As mentioned above, Xe_HP does not have the concept of a slice.
- * Enable one for software backwards compatibility.
- */
- if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
- s_en = 0x1;
- else
- s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
- GEN11_GT_S_ENA_MASK;
+ s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
+ GEN11_GT_S_ENA_MASK;
g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
- if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
- c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
/* one bit per pair of EUs */
- if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
- eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
- else
- eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
- GEN11_EU_DIS_MASK);
+ eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
+ GEN11_EU_DIS_MASK);
for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, s_en, g_dss_en, c_dss_en, eu_en);
+ gen11_compute_sseu_info(sseu, s_en, g_dss_en, 0, eu_en);
/* TGL only supports slice-level power gating */
sseu->has_slice_pg = 1;
@@ -574,18 +584,20 @@ void intel_sseu_info_init(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
- if (IS_HASWELL(i915))
- hsw_sseu_info_init(gt);
- else if (IS_CHERRYVIEW(i915))
- cherryview_sseu_info_init(gt);
- else if (IS_BROADWELL(i915))
- bdw_sseu_info_init(gt);
- else if (GRAPHICS_VER(i915) == 9)
- gen9_sseu_info_init(gt);
- else if (GRAPHICS_VER(i915) == 11)
- gen11_sseu_info_init(gt);
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ xehp_sseu_info_init(gt);
else if (GRAPHICS_VER(i915) >= 12)
gen12_sseu_info_init(gt);
+ else if (GRAPHICS_VER(i915) >= 11)
+ gen11_sseu_info_init(gt);
+ else if (GRAPHICS_VER(i915) >= 9)
+ gen9_sseu_info_init(gt);
+ else if (IS_BROADWELL(i915))
+ bdw_sseu_info_init(gt);
+ else if (IS_CHERRYVIEW(i915))
+ cherryview_sseu_info_init(gt);
+ else if (IS_HASWELL(i915))
+ hsw_sseu_info_init(gt);
}
u32 intel_sseu_make_rpcs(struct intel_gt *gt,
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 5c078df4729c..4a041f9dc490 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -66,6 +66,11 @@ struct sseu_dev_info {
u8 has_slice_pg:1;
u8 has_subslice_pg:1;
u8 has_eu_pg:1;
+ /*
+ * For Xe_HP and beyond, the hardware no longer has traditional slices
+ * so we just report the entire DSS pool under a fake "slice 0."
+ */
+ u8 has_xehp_dss:1;
/* Topology fields */
u8 max_slices;
--
2.35.3
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 2/6] drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
2022-05-17 3:19 ` [Intel-gfx] " Matt Roper
@ 2022-05-17 3:20 ` Matt Roper
-1 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2022-05-17 3:20 UTC (permalink / raw)
To: intel-gfx; +Cc: tvrtko.ursulin, dri-devel
Slice/subslice/EU information should be obtained via the topology
queries provided by the I915_QUERY interface; let's turn off support for
the old GETPARAM lookups on Xe_HP and beyond where we can't return
meaningful values.
The slice mask lookup is meaningless since Xe_HP doesn't support
traditional slices (and we make no attempt to return the various new
units like gslices, cslices, mslices, etc.) here.
The subslice mask lookup is even more problematic; given the distinct
masks for geometry vs compute purposes, the combined mask returned here
is likely not what userspace would want to act upon anyway. The value
is also limited to 32-bits by the nature of the GETPARAM ioctl which is
sufficient for the initial Xe_HP platforms, but is unable to convey the
larger masks that will be needed on other upcoming platforms. Finally,
the value returned here becomes even less meaningful when used on
multi-tile platforms where each tile will have its own masks.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_getparam.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index c12a0adefda5..ac9767c56619 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -148,11 +148,19 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = intel_engines_has_context_isolation(i915);
break;
case I915_PARAM_SLICE_MASK:
+ /* Not supported from Xe_HP onward; use topology queries */
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ return -EINVAL;
+
value = sseu->slice_mask;
if (!value)
return -ENODEV;
break;
case I915_PARAM_SUBSLICE_MASK:
+ /* Not supported from Xe_HP onward; use topology queries */
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ return -EINVAL;
+
/* Only copy bits from the first slice */
memcpy(&value, sseu->subslice_mask,
min(sseu->ss_stride, (u8)sizeof(value)));
--
2.35.3
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [Intel-gfx] [PATCH v2 2/6] drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
@ 2022-05-17 3:20 ` Matt Roper
0 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2022-05-17 3:20 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Slice/subslice/EU information should be obtained via the topology
queries provided by the I915_QUERY interface; let's turn off support for
the old GETPARAM lookups on Xe_HP and beyond where we can't return
meaningful values.
The slice mask lookup is meaningless since Xe_HP doesn't support
traditional slices (and we make no attempt to return the various new
units like gslices, cslices, mslices, etc.) here.
The subslice mask lookup is even more problematic; given the distinct
masks for geometry vs compute purposes, the combined mask returned here
is likely not what userspace would want to act upon anyway. The value
is also limited to 32-bits by the nature of the GETPARAM ioctl which is
sufficient for the initial Xe_HP platforms, but is unable to convey the
larger masks that will be needed on other upcoming platforms. Finally,
the value returned here becomes even less meaningful when used on
multi-tile platforms where each tile will have its own masks.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_getparam.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index c12a0adefda5..ac9767c56619 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -148,11 +148,19 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = intel_engines_has_context_isolation(i915);
break;
case I915_PARAM_SLICE_MASK:
+ /* Not supported from Xe_HP onward; use topology queries */
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ return -EINVAL;
+
value = sseu->slice_mask;
if (!value)
return -ENODEV;
break;
case I915_PARAM_SUBSLICE_MASK:
+ /* Not supported from Xe_HP onward; use topology queries */
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ return -EINVAL;
+
/* Only copy bits from the first slice */
memcpy(&value, sseu->subslice_mask,
min(sseu->ss_stride, (u8)sizeof(value)));
--
2.35.3
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 3/6] drm/i915/sseu: Simplify gen11+ SSEU handling
2022-05-17 3:19 ` [Intel-gfx] " Matt Roper
@ 2022-05-17 3:20 ` Matt Roper
-1 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2022-05-17 3:20 UTC (permalink / raw)
To: intel-gfx; +Cc: tvrtko.ursulin, dri-devel
Although gen11 and gen12 architectures supported the concept of multiple
slices, in practice all the platforms that were actually designed only
had a single slice (i.e., note the parameters to 'intel_sseu_set_info'
that we pass for each platform). We can simplify the code slightly by
dropping the multi-slice logic from gen11+ platforms.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 80 ++++++++++++++--------------
1 file changed, 40 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index b5fd479a7b85..ade3e1805782 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -119,52 +119,37 @@ static u16 compute_eu_total(const struct sseu_dev_info *sseu)
return total;
}
-static u32 get_ss_stride_mask(struct sseu_dev_info *sseu, u8 s, u32 ss_en)
-{
- u32 ss_mask;
-
- ss_mask = ss_en >> (s * sseu->max_subslices);
- ss_mask &= GENMASK(sseu->max_subslices - 1, 0);
-
- return ss_mask;
-}
-
-static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, u8 s_en,
+static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
u32 g_ss_en, u32 c_ss_en, u16 eu_en)
{
- int s, ss;
+ u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
+ int ss;
/* g_ss_en/c_ss_en represent entire subslice mask across all slices */
GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
sizeof(g_ss_en) * BITS_PER_BYTE);
- for (s = 0; s < sseu->max_slices; s++) {
- if ((s_en & BIT(s)) == 0)
- continue;
+ sseu->slice_mask |= BIT(0);
- sseu->slice_mask |= BIT(s);
-
- /*
- * XeHP introduces the concept of compute vs geometry DSS. To
- * reduce variation between GENs around subslice usage, store a
- * mask for both the geometry and compute enabled masks since
- * userspace will need to be able to query these masks
- * independently. Also compute a total enabled subslice count
- * for the purposes of selecting subslices to use in a
- * particular GEM context.
- */
- intel_sseu_set_subslices(sseu, s, sseu->compute_subslice_mask,
- get_ss_stride_mask(sseu, s, c_ss_en));
- intel_sseu_set_subslices(sseu, s, sseu->geometry_subslice_mask,
- get_ss_stride_mask(sseu, s, g_ss_en));
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- get_ss_stride_mask(sseu, s,
- g_ss_en | c_ss_en));
+ /*
+ * XeHP introduces the concept of compute vs geometry DSS. To reduce
+ * variation between GENs around subslice usage, store a mask for both
+ * the geometry and compute enabled masks since userspace will need to
+ * be able to query these masks independently. Also compute a total
+ * enabled subslice count for the purposes of selecting subslices to
+ * use in a particular GEM context.
+ */
+ intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
+ c_ss_en & valid_ss_mask);
+ intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
+ g_ss_en & valid_ss_mask);
+ intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
+ (g_ss_en | c_ss_en) & valid_ss_mask);
+
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (intel_sseu_has_subslice(sseu, 0, ss))
+ sseu_set_eus(sseu, 0, ss, eu_en);
- for (ss = 0; ss < sseu->max_subslices; ss++)
- if (intel_sseu_has_subslice(sseu, s, ss))
- sseu_set_eus(sseu, s, ss, eu_en);
- }
sseu->eu_per_subslice = hweight16(eu_en);
sseu->eu_total = compute_eu_total(sseu);
}
@@ -196,7 +181,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, 0x1, g_dss_en, c_dss_en, eu_en);
+ gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
}
static void gen12_sseu_info_init(struct intel_gt *gt)
@@ -216,8 +201,15 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
*/
intel_sseu_set_info(sseu, 1, 6, 16);
+ /*
+ * Although gen12 architecture supported multiple slices, TGL, RKL,
+ * DG1, and ADL only had a single slice.
+ */
s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
GEN11_GT_S_ENA_MASK;
+ if (s_en != 0x1)
+ drm_dbg(>->i915->drm, "Slice mask %#x is not the expected 0x1!\n",
+ s_en);
g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
@@ -229,7 +221,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, s_en, g_dss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
/* TGL only supports slice-level power gating */
sseu->has_slice_pg = 1;
@@ -248,14 +240,22 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
else
intel_sseu_set_info(sseu, 1, 8, 8);
+ /*
+ * Although gen11 architecture supported multiple slices, ICL and
+ * EHL/JSL only had a single slice in practice.
+ */
s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
GEN11_GT_S_ENA_MASK;
+ if (s_en != 0x1)
+ drm_dbg(>->i915->drm, "Slice mask %#x is not the expected 0x1!\n",
+ s_en);
+
ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE);
eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
GEN11_EU_DIS_MASK);
- gen11_compute_sseu_info(sseu, s_en, ss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
/* ICL has no power gating restrictions. */
sseu->has_slice_pg = 1;
--
2.35.3
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [Intel-gfx] [PATCH v2 3/6] drm/i915/sseu: Simplify gen11+ SSEU handling
@ 2022-05-17 3:20 ` Matt Roper
0 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2022-05-17 3:20 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Although gen11 and gen12 architectures supported the concept of multiple
slices, in practice all the platforms that were actually designed only
had a single slice (i.e., note the parameters to 'intel_sseu_set_info'
that we pass for each platform). We can simplify the code slightly by
dropping the multi-slice logic from gen11+ platforms.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 80 ++++++++++++++--------------
1 file changed, 40 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index b5fd479a7b85..ade3e1805782 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -119,52 +119,37 @@ static u16 compute_eu_total(const struct sseu_dev_info *sseu)
return total;
}
-static u32 get_ss_stride_mask(struct sseu_dev_info *sseu, u8 s, u32 ss_en)
-{
- u32 ss_mask;
-
- ss_mask = ss_en >> (s * sseu->max_subslices);
- ss_mask &= GENMASK(sseu->max_subslices - 1, 0);
-
- return ss_mask;
-}
-
-static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, u8 s_en,
+static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
u32 g_ss_en, u32 c_ss_en, u16 eu_en)
{
- int s, ss;
+ u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
+ int ss;
/* g_ss_en/c_ss_en represent entire subslice mask across all slices */
GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
sizeof(g_ss_en) * BITS_PER_BYTE);
- for (s = 0; s < sseu->max_slices; s++) {
- if ((s_en & BIT(s)) == 0)
- continue;
+ sseu->slice_mask |= BIT(0);
- sseu->slice_mask |= BIT(s);
-
- /*
- * XeHP introduces the concept of compute vs geometry DSS. To
- * reduce variation between GENs around subslice usage, store a
- * mask for both the geometry and compute enabled masks since
- * userspace will need to be able to query these masks
- * independently. Also compute a total enabled subslice count
- * for the purposes of selecting subslices to use in a
- * particular GEM context.
- */
- intel_sseu_set_subslices(sseu, s, sseu->compute_subslice_mask,
- get_ss_stride_mask(sseu, s, c_ss_en));
- intel_sseu_set_subslices(sseu, s, sseu->geometry_subslice_mask,
- get_ss_stride_mask(sseu, s, g_ss_en));
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- get_ss_stride_mask(sseu, s,
- g_ss_en | c_ss_en));
+ /*
+ * XeHP introduces the concept of compute vs geometry DSS. To reduce
+ * variation between GENs around subslice usage, store a mask for both
+ * the geometry and compute enabled masks since userspace will need to
+ * be able to query these masks independently. Also compute a total
+ * enabled subslice count for the purposes of selecting subslices to
+ * use in a particular GEM context.
+ */
+ intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
+ c_ss_en & valid_ss_mask);
+ intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
+ g_ss_en & valid_ss_mask);
+ intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
+ (g_ss_en | c_ss_en) & valid_ss_mask);
+
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (intel_sseu_has_subslice(sseu, 0, ss))
+ sseu_set_eus(sseu, 0, ss, eu_en);
- for (ss = 0; ss < sseu->max_subslices; ss++)
- if (intel_sseu_has_subslice(sseu, s, ss))
- sseu_set_eus(sseu, s, ss, eu_en);
- }
sseu->eu_per_subslice = hweight16(eu_en);
sseu->eu_total = compute_eu_total(sseu);
}
@@ -196,7 +181,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, 0x1, g_dss_en, c_dss_en, eu_en);
+ gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
}
static void gen12_sseu_info_init(struct intel_gt *gt)
@@ -216,8 +201,15 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
*/
intel_sseu_set_info(sseu, 1, 6, 16);
+ /*
+ * Although gen12 architecture supported multiple slices, TGL, RKL,
+ * DG1, and ADL only had a single slice.
+ */
s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
GEN11_GT_S_ENA_MASK;
+ if (s_en != 0x1)
+ drm_dbg(>->i915->drm, "Slice mask %#x is not the expected 0x1!\n",
+ s_en);
g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
@@ -229,7 +221,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, s_en, g_dss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
/* TGL only supports slice-level power gating */
sseu->has_slice_pg = 1;
@@ -248,14 +240,22 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
else
intel_sseu_set_info(sseu, 1, 8, 8);
+ /*
+ * Although gen11 architecture supported multiple slices, ICL and
+ * EHL/JSL only had a single slice in practice.
+ */
s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
GEN11_GT_S_ENA_MASK;
+ if (s_en != 0x1)
+ drm_dbg(>->i915->drm, "Slice mask %#x is not the expected 0x1!\n",
+ s_en);
+
ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE);
eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
GEN11_EU_DIS_MASK);
- gen11_compute_sseu_info(sseu, s_en, ss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
/* ICL has no power gating restrictions. */
sseu->has_slice_pg = 1;
--
2.35.3
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 4/6] drm/i915/sseu: Don't try to store EU mask internally in UAPI format
2022-05-17 3:19 ` [Intel-gfx] " Matt Roper
@ 2022-05-17 3:20 ` Matt Roper
-1 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2022-05-17 3:20 UTC (permalink / raw)
To: intel-gfx; +Cc: tvrtko.ursulin, dri-devel
Storing the EU mask internally in the same format the I915_QUERY
topology queries use makes the final copy_to_user() a bit simpler, but
makes the rest of the driver's SSEU more complicated and harder to
follow. Let's switch to an internal representation that's more natural:
Xe_HP platforms will be a simple array of u16 masks, whereas pre-Xe_HP
platforms will be a two-dimensional array, indexed by [slice][subslice].
We'll convert to the uapi format only when the query uapi is called.
v2:
- Drop has_common_ss_eumask. We waste some space repeating identical
EU masks for every single DSS, but the code is simpler without it.
(Tvrtko)
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 77 +++++++++++++++++++---------
drivers/gpu/drm/i915/gt/intel_sseu.h | 9 +++-
drivers/gpu/drm/i915/i915_query.c | 8 +--
3 files changed, 65 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index ade3e1805782..d89e2e0f05e5 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -78,47 +78,76 @@ intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
return hweight32(intel_sseu_get_subslices(sseu, slice));
}
-static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
- int subslice)
-{
- int slice_stride = sseu->max_subslices * sseu->eu_stride;
-
- return slice * slice_stride + subslice * sseu->eu_stride;
-}
-
static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
int subslice)
{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
- u16 eu_mask = 0;
-
- for (i = 0; i < sseu->eu_stride; i++)
- eu_mask |=
- ((u16)sseu->eu_mask[offset + i]) << (i * BITS_PER_BYTE);
-
- return eu_mask;
+ if (sseu->has_xehp_dss) {
+ WARN_ON(slice > 0);
+ return sseu->eu_mask.xehp[subslice];
+ } else {
+ return sseu->eu_mask.hsw[slice][subslice];
+ }
}
static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
u16 eu_mask)
{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
-
- for (i = 0; i < sseu->eu_stride; i++)
- sseu->eu_mask[offset + i] =
- (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
+ if (sseu->has_xehp_dss) {
+ WARN_ON(slice > 0);
+ sseu->eu_mask.xehp[subslice] = eu_mask;
+ } else {
+ eu_mask &= GENMASK(sseu->max_eus_per_subslice - 1, 0);
+ sseu->eu_mask.hsw[slice][subslice] = eu_mask;
+ }
}
static u16 compute_eu_total(const struct sseu_dev_info *sseu)
{
- u16 i, total = 0;
+ int s, ss, total = 0;
- for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++)
- total += hweight8(sseu->eu_mask[i]);
+ for (s = 0; s < sseu->max_slices; s++)
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (sseu->has_xehp_dss)
+ total += hweight16(sseu->eu_mask.xehp[ss]);
+ else
+ total += hweight16(sseu->eu_mask.hsw[s][ss]);
return total;
}
+/**
+ * intel_sseu_copy_eumask_to_user - Copy EU mask into a userspace buffer
+ * @to: Pointer to userspace buffer to copy to
+ * @sseu: SSEU structure containing EU mask to copy
+ *
+ * Copies the EU mask to a userspace buffer in the format expected by
+ * the query ioctl's topology queries.
+ *
+ * Returns the result of the copy_to_user() operation.
+ */
+int intel_sseu_copy_eumask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu)
+{
+ u8 eu_mask[GEN_SS_MASK_SIZE * GEN_MAX_EU_STRIDE] = {};
+ int len = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
+ int s, ss, i;
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ for (ss = 0; ss < sseu->max_subslices; ss++) {
+ int uapi_offset =
+ s * sseu->max_subslices * sseu->eu_stride +
+ ss * sseu->eu_stride;
+ u16 mask = sseu_get_eus(sseu, s, ss);
+
+ for (i = 0; i < sseu->eu_stride; i++)
+ eu_mask[uapi_offset + i] =
+ (mask >> (BITS_PER_BYTE * i)) & 0xff;
+ }
+ }
+
+ return copy_to_user(to, eu_mask, len);
+}
+
static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
u32 g_ss_en, u32 c_ss_en, u16 eu_en)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 4a041f9dc490..43a8f8f98687 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -57,7 +57,11 @@ struct sseu_dev_info {
u8 subslice_mask[GEN_SS_MASK_SIZE];
u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
- u8 eu_mask[GEN_SS_MASK_SIZE * GEN_MAX_EU_STRIDE];
+ union {
+ u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
+ u16 xehp[GEN_MAX_DSS];
+ } eu_mask;
+
u16 eu_total;
u8 eu_per_subslice;
u8 min_eu_in_pool;
@@ -150,4 +154,7 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
+int intel_sseu_copy_eumask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu);
+
#endif /* __INTEL_SSEU_H__ */
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 7584cec53d5d..16f43bf32a05 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -76,10 +76,10 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
subslice_mask, subslice_length))
return -EFAULT;
- if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
- sizeof(topo) +
- slice_length + subslice_length),
- sseu->eu_mask, eu_length))
+ if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
+ sizeof(topo) +
+ slice_length + subslice_length),
+ sseu))
return -EFAULT;
return total_length;
--
2.35.3
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [Intel-gfx] [PATCH v2 4/6] drm/i915/sseu: Don't try to store EU mask internally in UAPI format
@ 2022-05-17 3:20 ` Matt Roper
0 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2022-05-17 3:20 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Storing the EU mask internally in the same format the I915_QUERY
topology queries use makes the final copy_to_user() a bit simpler, but
makes the rest of the driver's SSEU more complicated and harder to
follow. Let's switch to an internal representation that's more natural:
Xe_HP platforms will be a simple array of u16 masks, whereas pre-Xe_HP
platforms will be a two-dimensional array, indexed by [slice][subslice].
We'll convert to the uapi format only when the query uapi is called.
v2:
- Drop has_common_ss_eumask. We waste some space repeating identical
EU masks for every single DSS, but the code is simpler without it.
(Tvrtko)
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 77 +++++++++++++++++++---------
drivers/gpu/drm/i915/gt/intel_sseu.h | 9 +++-
drivers/gpu/drm/i915/i915_query.c | 8 +--
3 files changed, 65 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index ade3e1805782..d89e2e0f05e5 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -78,47 +78,76 @@ intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
return hweight32(intel_sseu_get_subslices(sseu, slice));
}
-static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
- int subslice)
-{
- int slice_stride = sseu->max_subslices * sseu->eu_stride;
-
- return slice * slice_stride + subslice * sseu->eu_stride;
-}
-
static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
int subslice)
{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
- u16 eu_mask = 0;
-
- for (i = 0; i < sseu->eu_stride; i++)
- eu_mask |=
- ((u16)sseu->eu_mask[offset + i]) << (i * BITS_PER_BYTE);
-
- return eu_mask;
+ if (sseu->has_xehp_dss) {
+ WARN_ON(slice > 0);
+ return sseu->eu_mask.xehp[subslice];
+ } else {
+ return sseu->eu_mask.hsw[slice][subslice];
+ }
}
static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
u16 eu_mask)
{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
-
- for (i = 0; i < sseu->eu_stride; i++)
- sseu->eu_mask[offset + i] =
- (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
+ if (sseu->has_xehp_dss) {
+ WARN_ON(slice > 0);
+ sseu->eu_mask.xehp[subslice] = eu_mask;
+ } else {
+ eu_mask &= GENMASK(sseu->max_eus_per_subslice - 1, 0);
+ sseu->eu_mask.hsw[slice][subslice] = eu_mask;
+ }
}
static u16 compute_eu_total(const struct sseu_dev_info *sseu)
{
- u16 i, total = 0;
+ int s, ss, total = 0;
- for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++)
- total += hweight8(sseu->eu_mask[i]);
+ for (s = 0; s < sseu->max_slices; s++)
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (sseu->has_xehp_dss)
+ total += hweight16(sseu->eu_mask.xehp[ss]);
+ else
+ total += hweight16(sseu->eu_mask.hsw[s][ss]);
return total;
}
+/**
+ * intel_sseu_copy_eumask_to_user - Copy EU mask into a userspace buffer
+ * @to: Pointer to userspace buffer to copy to
+ * @sseu: SSEU structure containing EU mask to copy
+ *
+ * Copies the EU mask to a userspace buffer in the format expected by
+ * the query ioctl's topology queries.
+ *
+ * Returns the result of the copy_to_user() operation.
+ */
+int intel_sseu_copy_eumask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu)
+{
+ u8 eu_mask[GEN_SS_MASK_SIZE * GEN_MAX_EU_STRIDE] = {};
+ int len = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
+ int s, ss, i;
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ for (ss = 0; ss < sseu->max_subslices; ss++) {
+ int uapi_offset =
+ s * sseu->max_subslices * sseu->eu_stride +
+ ss * sseu->eu_stride;
+ u16 mask = sseu_get_eus(sseu, s, ss);
+
+ for (i = 0; i < sseu->eu_stride; i++)
+ eu_mask[uapi_offset + i] =
+ (mask >> (BITS_PER_BYTE * i)) & 0xff;
+ }
+ }
+
+ return copy_to_user(to, eu_mask, len);
+}
+
static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
u32 g_ss_en, u32 c_ss_en, u16 eu_en)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 4a041f9dc490..43a8f8f98687 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -57,7 +57,11 @@ struct sseu_dev_info {
u8 subslice_mask[GEN_SS_MASK_SIZE];
u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
- u8 eu_mask[GEN_SS_MASK_SIZE * GEN_MAX_EU_STRIDE];
+ union {
+ u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
+ u16 xehp[GEN_MAX_DSS];
+ } eu_mask;
+
u16 eu_total;
u8 eu_per_subslice;
u8 min_eu_in_pool;
@@ -150,4 +154,7 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
+int intel_sseu_copy_eumask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu);
+
#endif /* __INTEL_SSEU_H__ */
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 7584cec53d5d..16f43bf32a05 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -76,10 +76,10 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
subslice_mask, subslice_length))
return -EFAULT;
- if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
- sizeof(topo) +
- slice_length + subslice_length),
- sseu->eu_mask, eu_length))
+ if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
+ sizeof(topo) +
+ slice_length + subslice_length),
+ sseu))
return -EFAULT;
return total_length;
--
2.35.3
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi
2022-05-17 3:19 ` [Intel-gfx] " Matt Roper
@ 2022-05-17 3:20 ` Matt Roper
-1 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2022-05-17 3:20 UTC (permalink / raw)
To: intel-gfx; +Cc: tvrtko.ursulin, dri-devel
As with EU masks, it's easier to store subslice/DSS masks internally in
a format that's more natural for the driver to work with, and then only
covert into the u8[] uapi form when the query ioctl is invoked. Since
the hardware design changed significantly with Xe_HP, we'll use a union
to choose between the old "hsw-style" subslice masks or the newer xehp
mask. HSW-style masks will be stored in an array of u8's, indexed by
slice (there's never more than 6 subslices per slice on older
platforms). For Xe_HP and beyond where slices no longer exist, we only
need a single bitmask. However we already know that this mask is
eventually going to grow too large for a simple u64 to hold, so we'll
represent it in a manner that can be operated on by the utilities in
linux/bitmap.h.
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 12 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 246 +++++++++++--------
drivers/gpu/drm/i915/gt/intel_sseu.h | 78 +++---
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +--
drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +-
drivers/gpu/drm/i915/i915_getparam.c | 3 +-
drivers/gpu/drm/i915/i915_query.c | 8 +-
9 files changed, 226 insertions(+), 184 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index ab4c5ab28e4d..a3bb73f5d53b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1875,6 +1875,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
{
const struct sseu_dev_info *device = >->info.sseu;
struct drm_i915_private *i915 = gt->i915;
+ unsigned int dev_subslice_mask = intel_sseu_get_hsw_subslices(device, 0);
/* No zeros in any field. */
if (!user->slice_mask || !user->subslice_mask ||
@@ -1901,7 +1902,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
if (user->slice_mask & ~device->slice_mask)
return -EINVAL;
- if (user->subslice_mask & ~device->subslice_mask[0])
+ if (user->subslice_mask & ~dev_subslice_mask)
return -EINVAL;
if (user->max_eus_per_subslice > device->max_eus_per_subslice)
@@ -1915,7 +1916,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
/* Part specific restrictions. */
if (GRAPHICS_VER(i915) == 11) {
unsigned int hw_s = hweight8(device->slice_mask);
- unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
+ unsigned int hw_ss_per_s = hweight8(dev_subslice_mask);
unsigned int req_s = hweight8(context->slice_mask);
unsigned int req_ss = hweight8(context->subslice_mask);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 1adbf34c3632..f0acf8518a51 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -674,8 +674,8 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
return;
- ccs_mask = intel_slicemask_from_dssmask(intel_sseu_get_compute_subslices(&info->sseu),
- ss_per_ccs);
+ ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
+ ss_per_ccs);
/*
* If all DSS in a quadrant are fused off, the corresponding CCS
* engine is not available for use.
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 034182f85501..2921f510642f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -133,13 +133,6 @@ static const struct intel_mmio_range dg2_lncf_steering_table[] = {
{},
};
-static u16 slicemask(struct intel_gt *gt, int count)
-{
- u64 dss_mask = intel_sseu_get_subslices(>->info.sseu, 0);
-
- return intel_slicemask_from_dssmask(dss_mask, count);
-}
-
int intel_gt_init_mmio(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
@@ -155,9 +148,12 @@ int intel_gt_init_mmio(struct intel_gt *gt)
*/
if (HAS_MSLICES(i915)) {
gt->info.mslice_mask =
- slicemask(gt, GEN_DSS_PER_MSLICE) |
+ intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
+ GEN_DSS_PER_MSLICE);
+ gt->info.mslice_mask |=
(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
GEN12_MEML3_EN_MASK);
+
if (!gt->info.mslice_mask) /* should be impossible! */
drm_warn(&i915->drm, "mslice mask all zero!\n");
}
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index d89e2e0f05e5..e1bce8a9044e 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -28,54 +28,23 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
{
unsigned int i, total = 0;
- for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
- total += hweight8(sseu->subslice_mask[i]);
+ if (sseu->has_xehp_dss)
+ return bitmap_weight(sseu->subslice_mask.xehp,
+ I915_MAX_SS_FUSE_BITS);
- return total;
-}
-
-static u32
-sseu_get_subslices(const struct sseu_dev_info *sseu,
- const u8 *subslice_mask, u8 slice)
-{
- int i, offset = slice * sseu->ss_stride;
- u32 mask = 0;
-
- GEM_BUG_ON(slice >= sseu->max_slices);
-
- for (i = 0; i < sseu->ss_stride; i++)
- mask |= (u32)subslice_mask[offset + i] << i * BITS_PER_BYTE;
-
- return mask;
-}
-
-u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
-{
- return sseu_get_subslices(sseu, sseu->subslice_mask, slice);
-}
+ for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++)
+ total += hweight8(sseu->subslice_mask.hsw[i]);
-static u32 sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
-{
- return sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
-}
-
-u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu)
-{
- return sseu_get_subslices(sseu, sseu->compute_subslice_mask, 0);
-}
-
-void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
- u8 *subslice_mask, u32 ss_mask)
-{
- int offset = slice * sseu->ss_stride;
-
- memcpy(&subslice_mask[offset], &ss_mask, sseu->ss_stride);
+ return total;
}
unsigned int
-intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
+intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice)
{
- return hweight32(intel_sseu_get_subslices(sseu, slice));
+ WARN_ON(sseu->has_xehp_dss);
+ WARN_ON(slice >= sseu->max_slices);
+
+ return sseu->subslice_mask.hsw[slice];
}
static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
@@ -148,32 +117,65 @@ int intel_sseu_copy_eumask_to_user(void __user *to,
return copy_to_user(to, eu_mask, len);
}
+/**
+ * intel_sseu_copy_ssmask_to_user - Copy subslice mask into a userspace buffer
+ * @to: Pointer to userspace buffer to copy to
+ * @sseu: SSEU structure containing subslice mask to copy
+ *
+ * Copies the subslice mask to a userspace buffer in the format expected by
+ * the query ioctl's topology queries.
+ *
+ * Returns the result of the copy_to_user() operation.
+ */
+int intel_sseu_copy_ssmask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu)
+{
+ u8 ss_mask[GEN_SS_MASK_SIZE] = {};
+ int len = sseu->max_slices * sseu->ss_stride;
+ int s, ss, i;
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ for (ss = 0; ss < sseu->max_subslices; ss++) {
+ i = s * sseu->ss_stride * BITS_PER_BYTE + ss;
+
+ if (!intel_sseu_has_subslice(sseu, s, ss))
+ continue;
+
+ ss_mask[i / BITS_PER_BYTE] |= BIT(i % BITS_PER_BYTE);
+ }
+ }
+
+ return copy_to_user(to, ss_mask, len);
+}
+
static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
- u32 g_ss_en, u32 c_ss_en, u16 eu_en)
+ u32 ss_en, u16 eu_en)
{
u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
int ss;
- /* g_ss_en/c_ss_en represent entire subslice mask across all slices */
- GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
- sizeof(g_ss_en) * BITS_PER_BYTE);
+ sseu->slice_mask |= BIT(0);
+ sseu->subslice_mask.hsw[0] = ss_en & valid_ss_mask;
+
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (intel_sseu_has_subslice(sseu, 0, ss))
+ sseu_set_eus(sseu, 0, ss, eu_en);
+
+ sseu->eu_per_subslice = hweight16(eu_en);
+ sseu->eu_total = compute_eu_total(sseu);
+}
+
+static void xehp_compute_sseu_info(struct sseu_dev_info *sseu,
+ u16 eu_en)
+{
+ int ss;
sseu->slice_mask |= BIT(0);
- /*
- * XeHP introduces the concept of compute vs geometry DSS. To reduce
- * variation between GENs around subslice usage, store a mask for both
- * the geometry and compute enabled masks since userspace will need to
- * be able to query these masks independently. Also compute a total
- * enabled subslice count for the purposes of selecting subslices to
- * use in a particular GEM context.
- */
- intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
- c_ss_en & valid_ss_mask);
- intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
- g_ss_en & valid_ss_mask);
- intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
- (g_ss_en | c_ss_en) & valid_ss_mask);
+ bitmap_or(sseu->subslice_mask.xehp,
+ sseu->compute_subslice_mask.xehp,
+ sseu->geometry_subslice_mask.xehp,
+ I915_MAX_SS_FUSE_BITS);
for (ss = 0; ss < sseu->max_subslices; ss++)
if (intel_sseu_has_subslice(sseu, 0, ss))
@@ -183,11 +185,31 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
sseu->eu_total = compute_eu_total(sseu);
}
+static void
+xehp_load_dss_mask(struct intel_uncore *uncore,
+ intel_sseu_ss_mask_t *ssmask,
+ int numregs,
+ ...)
+{
+ va_list argp;
+ u32 fuse_val[I915_MAX_SS_FUSE_REGS] = {};
+ int i;
+
+ if (WARN_ON(numregs > I915_MAX_SS_FUSE_REGS))
+ numregs = I915_MAX_SS_FUSE_REGS;
+
+ va_start(argp, numregs);
+ for (i = 0; i < numregs; i++)
+ fuse_val[i] = intel_uncore_read(uncore, va_arg(argp, i915_reg_t));
+ va_end(argp);
+
+ bitmap_from_arr32(ssmask->xehp, fuse_val, numregs * 32);
+}
+
static void xehp_sseu_info_init(struct intel_gt *gt)
{
struct sseu_dev_info *sseu = >->info.sseu;
struct intel_uncore *uncore = gt->uncore;
- u32 g_dss_en, c_dss_en = 0;
u16 eu_en = 0;
u8 eu_en_fuse;
int eu;
@@ -201,8 +223,10 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
intel_sseu_set_info(sseu, 1, 32, 16);
sseu->has_xehp_dss = 1;
- g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
- c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
+ xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 1,
+ GEN12_GT_GEOMETRY_DSS_ENABLE);
+ xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 1,
+ GEN12_GT_COMPUTE_DSS_ENABLE);
eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
@@ -210,7 +234,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
+ xehp_compute_sseu_info(sseu, eu_en);
}
static void gen12_sseu_info_init(struct intel_gt *gt)
@@ -250,7 +274,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, g_dss_en, eu_en);
/* TGL only supports slice-level power gating */
sseu->has_slice_pg = 1;
@@ -284,7 +308,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
GEN11_EU_DIS_MASK);
- gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, ss_en, eu_en);
/* ICL has no power gating restrictions. */
sseu->has_slice_pg = 1;
@@ -296,7 +320,6 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
{
struct sseu_dev_info *sseu = >->info.sseu;
u32 fuse;
- u8 subslice_mask = 0;
fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT);
@@ -310,7 +333,7 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
- subslice_mask |= BIT(0);
+ sseu->subslice_mask.hsw[0] |= BIT(0);
sseu_set_eus(sseu, 0, 0, ~disabled_mask);
}
@@ -321,12 +344,10 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
(((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
- subslice_mask |= BIT(1);
+ sseu->subslice_mask.hsw[0] |= BIT(1);
sseu_set_eus(sseu, 0, 1, ~disabled_mask);
}
- intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask, subslice_mask);
-
sseu->eu_total = compute_eu_total(sseu);
/*
@@ -381,8 +402,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
/* skip disabled slice */
continue;
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
for (ss = 0; ss < sseu->max_subslices; ss++) {
@@ -439,8 +459,8 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
sseu->has_eu_pg = sseu->eu_per_subslice > 2;
if (IS_GEN9_LP(i915)) {
-#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
- info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
+#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask.hsw[0] & BIT(ss)))
+ info->has_pooled_eu = hweight8(sseu->subslice_mask.hsw[0]) == 3;
sseu->min_eu_in_pool = 0;
if (info->has_pooled_eu) {
@@ -494,8 +514,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
/* skip disabled slice */
continue;
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
for (ss = 0; ss < sseu->max_subslices; ss++) {
u8 eu_disabled_mask;
@@ -592,8 +611,7 @@ static void hsw_sseu_info_init(struct intel_gt *gt)
sseu->eu_per_subslice);
for (s = 0; s < sseu->max_slices; s++) {
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
for (ss = 0; ss < sseu->max_subslices; ss++) {
sseu_set_eus(sseu, s, ss,
@@ -682,7 +700,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
*/
if (GRAPHICS_VER(i915) == 11 &&
slices == 1 &&
- subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
+ subslices > min_t(u8, 4, hweight8(sseu->subslice_mask.hsw[0]) / 2)) {
GEM_BUG_ON(subslices & 1);
subslice_pg = false;
@@ -748,14 +766,25 @@ void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
{
int s;
- drm_printf(p, "slice total: %u, mask=%04x\n",
- hweight8(sseu->slice_mask), sseu->slice_mask);
- drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
- for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
- s, intel_sseu_subslices_per_slice(sseu, s),
- intel_sseu_get_subslices(sseu, s));
+ if (sseu->has_xehp_dss) {
+ drm_printf(p, "subslice total: %u\n",
+ intel_sseu_subslice_total(sseu));
+ drm_printf(p, "subslice mask=%*pb\n", I915_MAX_SS_FUSE_BITS,
+ sseu->subslice_mask.xehp);
+ } else {
+ drm_printf(p, "slice total: %u, mask=%04x\n",
+ hweight8(sseu->slice_mask), sseu->slice_mask);
+ drm_printf(p, "subslice total: %u\n",
+ intel_sseu_subslice_total(sseu));
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ u8 ss_mask = sseu->subslice_mask.hsw[s];
+
+ drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
+ s, hweight8(ss_mask), ss_mask);
+ }
}
+
drm_printf(p, "EU total: %u\n", sseu->eu_total);
drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
drm_printf(p, "has slice power gating: %s\n",
@@ -772,9 +801,10 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
int s, ss;
for (s = 0; s < sseu->max_slices; s++) {
+ u8 ss_mask = sseu->subslice_mask.hsw[s];
+
drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
- s, intel_sseu_subslices_per_slice(sseu, s),
- intel_sseu_get_subslices(sseu, s));
+ s, hweight8(ss_mask), ss_mask);
for (ss = 0; ss < sseu->max_subslices; ss++) {
u16 enabled_eus = sseu_get_eus(sseu, s, ss);
@@ -788,16 +818,14 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
static void sseu_print_xehp_topology(const struct sseu_dev_info *sseu,
struct drm_printer *p)
{
- u32 g_dss_mask = sseu_get_geometry_subslices(sseu);
- u32 c_dss_mask = intel_sseu_get_compute_subslices(sseu);
int dss;
for (dss = 0; dss < sseu->max_subslices; dss++) {
u16 enabled_eus = sseu_get_eus(sseu, 0, dss);
drm_printf(p, "DSS_%02d: G:%3s C:%3s, %2u EUs (0x%04hx)\n", dss,
- str_yes_no(g_dss_mask & BIT(dss)),
- str_yes_no(c_dss_mask & BIT(dss)),
+ str_yes_no(test_bit(dss, sseu->geometry_subslice_mask.xehp)),
+ str_yes_no(test_bit(dss, sseu->compute_subslice_mask.xehp)),
hweight16(enabled_eus), enabled_eus);
}
}
@@ -815,20 +843,40 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
}
}
-u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice)
+void intel_sseu_print_ss_info(const char* type,
+ const struct sseu_dev_info *sseu,
+ struct seq_file *m)
+{
+ int s;
+
+ if (sseu->has_xehp_dss)
+ seq_printf(m, " %s Subslices: %u\n", type,
+ bitmap_weight(sseu->subslice_mask.xehp,
+ I915_MAX_SS_FUSE_BITS));
+ else
+ for (s = 0; s < fls(sseu->slice_mask); s++)
+ seq_printf(m, " %s Slice%i subslices: %u\n", type,
+ s, hweight8(sseu->subslice_mask.hsw[s]));
+}
+
+u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask,
+ int dss_per_slice)
{
+ intel_sseu_ss_mask_t per_slice_mask = {};
u16 slice_mask = 0;
int i;
- WARN_ON(sizeof(dss_mask) * 8 / dss_per_slice > 8 * sizeof(slice_mask));
+ WARN_ON(DIV_ROUND_UP(I915_MAX_SS_FUSE_BITS, dss_per_slice) >
+ 8 * sizeof(slice_mask));
- for (i = 0; dss_mask; i++) {
- if (dss_mask & GENMASK(dss_per_slice - 1, 0))
+ bitmap_fill(per_slice_mask.xehp, dss_per_slice);
+ for (i = 0; !bitmap_empty(dss_mask.xehp, I915_MAX_SS_FUSE_BITS); i++) {
+ if (bitmap_intersects(dss_mask.xehp, per_slice_mask.xehp, dss_per_slice))
slice_mask |= BIT(i);
- dss_mask >>= dss_per_slice;
+ bitmap_shift_right(dss_mask.xehp, dss_mask.xehp, dss_per_slice,
+ I915_MAX_SS_FUSE_BITS);
}
return slice_mask;
}
-
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 43a8f8f98687..7fbb9276a1c2 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -25,12 +25,16 @@ struct drm_printer;
/*
* Maximum number of subslices that can exist within a HSW-style slice. This
* is only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the
- * GEN_MAX_DSS value below).
+ * I915_MAX_SS_FUSE_BITS value below).
*/
#define GEN_MAX_SS_PER_HSW_SLICE 6
-/* Maximum number of DSS on newer platforms (Xe_HP and beyond). */
-#define GEN_MAX_DSS 32
+/*
+ * Maximum number of 32-bit registers used by hardware to express the
+ * enabled/disabled subslices.
+ */
+#define I915_MAX_SS_FUSE_REGS 1
+#define I915_MAX_SS_FUSE_BITS (I915_MAX_SS_FUSE_REGS * 32)
/* Maximum number of EUs that can exist within a subslice or DSS. */
#define GEN_MAX_EUS_PER_SS 16
@@ -38,7 +42,7 @@ struct drm_printer;
#define SSEU_MAX(a, b) ((a) > (b) ? (a) : (b))
/* The maximum number of bits needed to express each subslice/DSS independently */
-#define GEN_SS_MASK_SIZE SSEU_MAX(GEN_MAX_DSS, \
+#define GEN_SS_MASK_SIZE SSEU_MAX(I915_MAX_SS_FUSE_BITS, \
GEN_MAX_HSW_SLICES * GEN_MAX_SS_PER_HSW_SLICE)
#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
@@ -49,17 +53,24 @@ struct drm_printer;
#define GEN_DSS_PER_CSLICE 8
#define GEN_DSS_PER_MSLICE 8
-#define GEN_MAX_GSLICES (GEN_MAX_DSS / GEN_DSS_PER_GSLICE)
-#define GEN_MAX_CSLICES (GEN_MAX_DSS / GEN_DSS_PER_CSLICE)
+#define GEN_MAX_GSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_GSLICE)
+#define GEN_MAX_CSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_CSLICE)
+
+typedef union {
+ u8 hsw[GEN_MAX_HSW_SLICES];
+
+ /* Bitmap compatible with linux/bitmap.h; may exceed size of u64 */
+ unsigned long xehp[BITS_TO_LONGS(I915_MAX_SS_FUSE_BITS)];
+} intel_sseu_ss_mask_t;
struct sseu_dev_info {
u8 slice_mask;
- u8 subslice_mask[GEN_SS_MASK_SIZE];
- u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
- u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
+ intel_sseu_ss_mask_t subslice_mask;
+ intel_sseu_ss_mask_t geometry_subslice_mask;
+ intel_sseu_ss_mask_t compute_subslice_mask;
union {
u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
- u16 xehp[GEN_MAX_DSS];
+ u16 xehp[I915_MAX_SS_FUSE_BITS];
} eu_mask;
u16 eu_total;
@@ -100,7 +111,7 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
{
struct intel_sseu value = {
.slice_mask = sseu->slice_mask,
- .subslice_mask = sseu->subslice_mask[0],
+ .subslice_mask = sseu->subslice_mask.hsw[0],
.min_eus_per_subslice = sseu->max_eus_per_subslice,
.max_eus_per_subslice = sseu->max_eus_per_subslice,
};
@@ -112,18 +123,23 @@ static inline bool
intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
int subslice)
{
- u8 mask;
- int ss_idx = subslice / BITS_PER_BYTE;
-
- if (slice >= sseu->max_slices ||
- subslice >= sseu->max_subslices)
- return false;
-
- GEM_BUG_ON(ss_idx >= sseu->ss_stride);
-
- mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx];
+ if (sseu->has_xehp_dss)
+ return test_bit(subslice, sseu->subslice_mask.xehp);
+ else
+ return sseu->subslice_mask.hsw[slice] & BIT(subslice);
+}
- return mask & BIT(subslice % BITS_PER_BYTE);
+/*
+ * Used to obtain the index of the first DSS. Can start searching from the
+ * beginning of a specific dss group (e.g., gslice, cslice, etc.) if
+ * groupsize and groupnum are non-zero.
+ */
+static inline unsigned int
+intel_sseu_find_first_xehp_dss(const struct sseu_dev_info *sseu, int groupsize,
+ int groupnum)
+{
+ return find_next_bit(sseu->subslice_mask.xehp, I915_MAX_SS_FUSE_BITS,
+ groupnum * groupsize);
}
void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
@@ -133,14 +149,10 @@ unsigned int
intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
unsigned int
-intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
-
-u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
+intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice);
-u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
-
-void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
- u8 *subslice_mask, u32 ss_mask);
+intel_sseu_ss_mask_t
+intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
void intel_sseu_info_init(struct intel_gt *gt);
@@ -152,9 +164,15 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
const struct sseu_dev_info *sseu,
struct drm_printer *p);
-u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
+u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask, int dss_per_slice);
int intel_sseu_copy_eumask_to_user(void __user *to,
const struct sseu_dev_info *sseu);
+int intel_sseu_copy_ssmask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu);
+
+void intel_sseu_print_ss_info(const char* type,
+ const struct sseu_dev_info *sseu,
+ struct seq_file *m);
#endif /* __INTEL_SSEU_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
index 2d5d011e01db..d6b75e5127e0 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
@@ -4,6 +4,7 @@
* Copyright © 2020 Intel Corporation
*/
+#include <linux/bitmap.h>
#include <linux/string_helpers.h>
#include "i915_drv.h"
@@ -11,14 +12,6 @@
#include "intel_gt_regs.h"
#include "intel_sseu_debugfs.h"
-static void sseu_copy_subslices(const struct sseu_dev_info *sseu,
- int slice, u8 *to_mask)
-{
- int offset = slice * sseu->ss_stride;
-
- memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
-}
-
static void cherryview_sseu_device_status(struct intel_gt *gt,
struct sseu_dev_info *sseu)
{
@@ -41,7 +34,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt,
continue;
sseu->slice_mask = BIT(0);
- sseu->subslice_mask[0] |= BIT(ss);
+ sseu->subslice_mask.hsw[0] |= BIT(ss);
eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
@@ -92,7 +85,7 @@ static void gen11_sseu_device_status(struct intel_gt *gt,
continue;
sseu->slice_mask |= BIT(s);
- sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -147,21 +140,17 @@ static void gen9_sseu_device_status(struct intel_gt *gt,
sseu->slice_mask |= BIT(s);
if (IS_GEN9_BC(gt->i915))
- sseu_copy_subslices(&info->sseu, s,
- sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
- u8 ss_idx = s * info->sseu.ss_stride +
- ss / BITS_PER_BYTE;
if (IS_GEN9_LP(gt->i915)) {
if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
/* skip disabled subslice */
continue;
- sseu->subslice_mask[ss_idx] |=
- BIT(ss % BITS_PER_BYTE);
+ sseu->subslice_mask.hsw[s] |= BIT(s);
}
eu_cnt = eu_reg[2 * s + ss / 2] & eu_mask[ss % 2];
@@ -188,8 +177,7 @@ static void bdw_sseu_device_status(struct intel_gt *gt,
if (sseu->slice_mask) {
sseu->eu_per_subslice = info->sseu.eu_per_subslice;
for (s = 0; s < fls(sseu->slice_mask); s++)
- sseu_copy_subslices(&info->sseu, s,
- sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
sseu->eu_total = sseu->eu_per_subslice *
intel_sseu_subslice_total(sseu);
@@ -208,7 +196,6 @@ static void i915_print_sseu_info(struct seq_file *m,
const struct sseu_dev_info *sseu)
{
const char *type = is_available_info ? "Available" : "Enabled";
- int s;
seq_printf(m, " %s Slice Mask: %04x\n", type,
sseu->slice_mask);
@@ -216,10 +203,7 @@ static void i915_print_sseu_info(struct seq_file *m,
hweight8(sseu->slice_mask));
seq_printf(m, " %s Subslice Total: %u\n", type,
intel_sseu_subslice_total(sseu));
- for (s = 0; s < fls(sseu->slice_mask); s++) {
- seq_printf(m, " %s Slice%i subslices: %u\n", type,
- s, intel_sseu_subslices_per_slice(sseu, s));
- }
+ intel_sseu_print_ss_info(type, sseu, m);
seq_printf(m, " %s EU Total: %u\n", type,
sseu->eu_total);
seq_printf(m, " %s EU Per Subslice: %u\n", type,
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 756807c4b405..fc6274708f8e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -948,8 +948,8 @@ gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
* on s/ss combo, the read should be done with read_subslice_reg.
*/
slice = ffs(sseu->slice_mask) - 1;
- GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
- subslice = ffs(intel_sseu_get_subslices(sseu, slice));
+ GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw));
+ subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice));
GEM_BUG_ON(!subslice);
subslice--;
@@ -1087,11 +1087,10 @@ static void
icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
{
const struct sseu_dev_info *sseu = >->info.sseu;
- unsigned int slice, subslice;
+ unsigned int subslice;
GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
- slice = 0;
/*
* Although a platform may have subslices, we need to always steer
@@ -1102,7 +1101,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
* one of the higher subslices, we run the risk of reading back 0's or
* random garbage.
*/
- subslice = __ffs(intel_sseu_get_subslices(sseu, slice));
+ subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0));
/*
* If the subslice we picked above also steers us to a valid L3 bank,
@@ -1112,7 +1111,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
if (gt->info.l3bank_mask & BIT(subslice))
gt->steering_table[L3BANK] = NULL;
- __add_mcr_wa(gt, wal, slice, subslice);
+ __add_mcr_wa(gt, wal, 0, subslice);
}
static void
@@ -1120,7 +1119,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
{
const struct sseu_dev_info *sseu = >->info.sseu;
unsigned long slice, subslice = 0, slice_mask = 0;
- u64 dss_mask = 0;
u32 lncf_mask = 0;
int i;
@@ -1151,8 +1149,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
*/
/* Find the potential gslice candidates */
- dss_mask = intel_sseu_get_subslices(sseu, 0);
- slice_mask = intel_slicemask_from_dssmask(dss_mask, GEN_DSS_PER_GSLICE);
+ slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask,
+ GEN_DSS_PER_GSLICE);
/*
* Find the potential LNCF candidates. Either LNCF within a valid
@@ -1177,9 +1175,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
}
slice = __ffs(slice_mask);
- subslice = __ffs(dss_mask >> (slice * GEN_DSS_PER_GSLICE));
+ subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice);
WARN_ON(subslice > GEN_DSS_PER_GSLICE);
- WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0);
__add_mcr_wa(gt, wal, slice, subslice);
@@ -2030,9 +2027,8 @@ engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
static bool needs_wa_1308578152(struct intel_engine_cs *engine)
{
- u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0);
-
- return (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0;
+ return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >
+ GEN_DSS_PER_GSLICE;
}
static void
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index ac9767c56619..6fd15b39570c 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -162,8 +162,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
return -EINVAL;
/* Only copy bits from the first slice */
- memcpy(&value, sseu->subslice_mask,
- min(sseu->ss_stride, (u8)sizeof(value)));
+ value = intel_sseu_get_hsw_subslices(sseu, 0);
if (!value)
return -ENODEV;
break;
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 16f43bf32a05..9afa6d1eaf95 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -31,7 +31,7 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
static int fill_topology_info(const struct sseu_dev_info *sseu,
struct drm_i915_query_item *query_item,
- const u8 *subslice_mask)
+ intel_sseu_ss_mask_t subslice_mask)
{
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
@@ -71,9 +71,9 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
&sseu->slice_mask, slice_length))
return -EFAULT;
- if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
- sizeof(topo) + slice_length),
- subslice_mask, subslice_length))
+ if (intel_sseu_copy_ssmask_to_user(u64_to_user_ptr(query_item->data_ptr +
+ sizeof(topo) + slice_length),
+ sseu))
return -EFAULT;
if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
--
2.35.3
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [Intel-gfx] [PATCH v2 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi
@ 2022-05-17 3:20 ` Matt Roper
0 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2022-05-17 3:20 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
As with EU masks, it's easier to store subslice/DSS masks internally in
a format that's more natural for the driver to work with, and then only
covert into the u8[] uapi form when the query ioctl is invoked. Since
the hardware design changed significantly with Xe_HP, we'll use a union
to choose between the old "hsw-style" subslice masks or the newer xehp
mask. HSW-style masks will be stored in an array of u8's, indexed by
slice (there's never more than 6 subslices per slice on older
platforms). For Xe_HP and beyond where slices no longer exist, we only
need a single bitmask. However we already know that this mask is
eventually going to grow too large for a simple u64 to hold, so we'll
represent it in a manner that can be operated on by the utilities in
linux/bitmap.h.
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 12 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 246 +++++++++++--------
drivers/gpu/drm/i915/gt/intel_sseu.h | 78 +++---
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +--
drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +-
drivers/gpu/drm/i915/i915_getparam.c | 3 +-
drivers/gpu/drm/i915/i915_query.c | 8 +-
9 files changed, 226 insertions(+), 184 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index ab4c5ab28e4d..a3bb73f5d53b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1875,6 +1875,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
{
const struct sseu_dev_info *device = >->info.sseu;
struct drm_i915_private *i915 = gt->i915;
+ unsigned int dev_subslice_mask = intel_sseu_get_hsw_subslices(device, 0);
/* No zeros in any field. */
if (!user->slice_mask || !user->subslice_mask ||
@@ -1901,7 +1902,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
if (user->slice_mask & ~device->slice_mask)
return -EINVAL;
- if (user->subslice_mask & ~device->subslice_mask[0])
+ if (user->subslice_mask & ~dev_subslice_mask)
return -EINVAL;
if (user->max_eus_per_subslice > device->max_eus_per_subslice)
@@ -1915,7 +1916,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
/* Part specific restrictions. */
if (GRAPHICS_VER(i915) == 11) {
unsigned int hw_s = hweight8(device->slice_mask);
- unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
+ unsigned int hw_ss_per_s = hweight8(dev_subslice_mask);
unsigned int req_s = hweight8(context->slice_mask);
unsigned int req_ss = hweight8(context->subslice_mask);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 1adbf34c3632..f0acf8518a51 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -674,8 +674,8 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
return;
- ccs_mask = intel_slicemask_from_dssmask(intel_sseu_get_compute_subslices(&info->sseu),
- ss_per_ccs);
+ ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
+ ss_per_ccs);
/*
* If all DSS in a quadrant are fused off, the corresponding CCS
* engine is not available for use.
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 034182f85501..2921f510642f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -133,13 +133,6 @@ static const struct intel_mmio_range dg2_lncf_steering_table[] = {
{},
};
-static u16 slicemask(struct intel_gt *gt, int count)
-{
- u64 dss_mask = intel_sseu_get_subslices(>->info.sseu, 0);
-
- return intel_slicemask_from_dssmask(dss_mask, count);
-}
-
int intel_gt_init_mmio(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
@@ -155,9 +148,12 @@ int intel_gt_init_mmio(struct intel_gt *gt)
*/
if (HAS_MSLICES(i915)) {
gt->info.mslice_mask =
- slicemask(gt, GEN_DSS_PER_MSLICE) |
+ intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
+ GEN_DSS_PER_MSLICE);
+ gt->info.mslice_mask |=
(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
GEN12_MEML3_EN_MASK);
+
if (!gt->info.mslice_mask) /* should be impossible! */
drm_warn(&i915->drm, "mslice mask all zero!\n");
}
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index d89e2e0f05e5..e1bce8a9044e 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -28,54 +28,23 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
{
unsigned int i, total = 0;
- for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
- total += hweight8(sseu->subslice_mask[i]);
+ if (sseu->has_xehp_dss)
+ return bitmap_weight(sseu->subslice_mask.xehp,
+ I915_MAX_SS_FUSE_BITS);
- return total;
-}
-
-static u32
-sseu_get_subslices(const struct sseu_dev_info *sseu,
- const u8 *subslice_mask, u8 slice)
-{
- int i, offset = slice * sseu->ss_stride;
- u32 mask = 0;
-
- GEM_BUG_ON(slice >= sseu->max_slices);
-
- for (i = 0; i < sseu->ss_stride; i++)
- mask |= (u32)subslice_mask[offset + i] << i * BITS_PER_BYTE;
-
- return mask;
-}
-
-u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
-{
- return sseu_get_subslices(sseu, sseu->subslice_mask, slice);
-}
+ for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++)
+ total += hweight8(sseu->subslice_mask.hsw[i]);
-static u32 sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
-{
- return sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
-}
-
-u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu)
-{
- return sseu_get_subslices(sseu, sseu->compute_subslice_mask, 0);
-}
-
-void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
- u8 *subslice_mask, u32 ss_mask)
-{
- int offset = slice * sseu->ss_stride;
-
- memcpy(&subslice_mask[offset], &ss_mask, sseu->ss_stride);
+ return total;
}
unsigned int
-intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
+intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice)
{
- return hweight32(intel_sseu_get_subslices(sseu, slice));
+ WARN_ON(sseu->has_xehp_dss);
+ WARN_ON(slice >= sseu->max_slices);
+
+ return sseu->subslice_mask.hsw[slice];
}
static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
@@ -148,32 +117,65 @@ int intel_sseu_copy_eumask_to_user(void __user *to,
return copy_to_user(to, eu_mask, len);
}
+/**
+ * intel_sseu_copy_ssmask_to_user - Copy subslice mask into a userspace buffer
+ * @to: Pointer to userspace buffer to copy to
+ * @sseu: SSEU structure containing subslice mask to copy
+ *
+ * Copies the subslice mask to a userspace buffer in the format expected by
+ * the query ioctl's topology queries.
+ *
+ * Returns the result of the copy_to_user() operation.
+ */
+int intel_sseu_copy_ssmask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu)
+{
+ u8 ss_mask[GEN_SS_MASK_SIZE] = {};
+ int len = sseu->max_slices * sseu->ss_stride;
+ int s, ss, i;
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ for (ss = 0; ss < sseu->max_subslices; ss++) {
+ i = s * sseu->ss_stride * BITS_PER_BYTE + ss;
+
+ if (!intel_sseu_has_subslice(sseu, s, ss))
+ continue;
+
+ ss_mask[i / BITS_PER_BYTE] |= BIT(i % BITS_PER_BYTE);
+ }
+ }
+
+ return copy_to_user(to, ss_mask, len);
+}
+
static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
- u32 g_ss_en, u32 c_ss_en, u16 eu_en)
+ u32 ss_en, u16 eu_en)
{
u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
int ss;
- /* g_ss_en/c_ss_en represent entire subslice mask across all slices */
- GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
- sizeof(g_ss_en) * BITS_PER_BYTE);
+ sseu->slice_mask |= BIT(0);
+ sseu->subslice_mask.hsw[0] = ss_en & valid_ss_mask;
+
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (intel_sseu_has_subslice(sseu, 0, ss))
+ sseu_set_eus(sseu, 0, ss, eu_en);
+
+ sseu->eu_per_subslice = hweight16(eu_en);
+ sseu->eu_total = compute_eu_total(sseu);
+}
+
+static void xehp_compute_sseu_info(struct sseu_dev_info *sseu,
+ u16 eu_en)
+{
+ int ss;
sseu->slice_mask |= BIT(0);
- /*
- * XeHP introduces the concept of compute vs geometry DSS. To reduce
- * variation between GENs around subslice usage, store a mask for both
- * the geometry and compute enabled masks since userspace will need to
- * be able to query these masks independently. Also compute a total
- * enabled subslice count for the purposes of selecting subslices to
- * use in a particular GEM context.
- */
- intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
- c_ss_en & valid_ss_mask);
- intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
- g_ss_en & valid_ss_mask);
- intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
- (g_ss_en | c_ss_en) & valid_ss_mask);
+ bitmap_or(sseu->subslice_mask.xehp,
+ sseu->compute_subslice_mask.xehp,
+ sseu->geometry_subslice_mask.xehp,
+ I915_MAX_SS_FUSE_BITS);
for (ss = 0; ss < sseu->max_subslices; ss++)
if (intel_sseu_has_subslice(sseu, 0, ss))
@@ -183,11 +185,31 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
sseu->eu_total = compute_eu_total(sseu);
}
+static void
+xehp_load_dss_mask(struct intel_uncore *uncore,
+ intel_sseu_ss_mask_t *ssmask,
+ int numregs,
+ ...)
+{
+ va_list argp;
+ u32 fuse_val[I915_MAX_SS_FUSE_REGS] = {};
+ int i;
+
+ if (WARN_ON(numregs > I915_MAX_SS_FUSE_REGS))
+ numregs = I915_MAX_SS_FUSE_REGS;
+
+ va_start(argp, numregs);
+ for (i = 0; i < numregs; i++)
+ fuse_val[i] = intel_uncore_read(uncore, va_arg(argp, i915_reg_t));
+ va_end(argp);
+
+ bitmap_from_arr32(ssmask->xehp, fuse_val, numregs * 32);
+}
+
static void xehp_sseu_info_init(struct intel_gt *gt)
{
struct sseu_dev_info *sseu = >->info.sseu;
struct intel_uncore *uncore = gt->uncore;
- u32 g_dss_en, c_dss_en = 0;
u16 eu_en = 0;
u8 eu_en_fuse;
int eu;
@@ -201,8 +223,10 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
intel_sseu_set_info(sseu, 1, 32, 16);
sseu->has_xehp_dss = 1;
- g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
- c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
+ xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 1,
+ GEN12_GT_GEOMETRY_DSS_ENABLE);
+ xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 1,
+ GEN12_GT_COMPUTE_DSS_ENABLE);
eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
@@ -210,7 +234,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
+ xehp_compute_sseu_info(sseu, eu_en);
}
static void gen12_sseu_info_init(struct intel_gt *gt)
@@ -250,7 +274,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, g_dss_en, eu_en);
/* TGL only supports slice-level power gating */
sseu->has_slice_pg = 1;
@@ -284,7 +308,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
GEN11_EU_DIS_MASK);
- gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, ss_en, eu_en);
/* ICL has no power gating restrictions. */
sseu->has_slice_pg = 1;
@@ -296,7 +320,6 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
{
struct sseu_dev_info *sseu = >->info.sseu;
u32 fuse;
- u8 subslice_mask = 0;
fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT);
@@ -310,7 +333,7 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
- subslice_mask |= BIT(0);
+ sseu->subslice_mask.hsw[0] |= BIT(0);
sseu_set_eus(sseu, 0, 0, ~disabled_mask);
}
@@ -321,12 +344,10 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
(((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
- subslice_mask |= BIT(1);
+ sseu->subslice_mask.hsw[0] |= BIT(1);
sseu_set_eus(sseu, 0, 1, ~disabled_mask);
}
- intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask, subslice_mask);
-
sseu->eu_total = compute_eu_total(sseu);
/*
@@ -381,8 +402,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
/* skip disabled slice */
continue;
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
for (ss = 0; ss < sseu->max_subslices; ss++) {
@@ -439,8 +459,8 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
sseu->has_eu_pg = sseu->eu_per_subslice > 2;
if (IS_GEN9_LP(i915)) {
-#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
- info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
+#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask.hsw[0] & BIT(ss)))
+ info->has_pooled_eu = hweight8(sseu->subslice_mask.hsw[0]) == 3;
sseu->min_eu_in_pool = 0;
if (info->has_pooled_eu) {
@@ -494,8 +514,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
/* skip disabled slice */
continue;
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
for (ss = 0; ss < sseu->max_subslices; ss++) {
u8 eu_disabled_mask;
@@ -592,8 +611,7 @@ static void hsw_sseu_info_init(struct intel_gt *gt)
sseu->eu_per_subslice);
for (s = 0; s < sseu->max_slices; s++) {
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
for (ss = 0; ss < sseu->max_subslices; ss++) {
sseu_set_eus(sseu, s, ss,
@@ -682,7 +700,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
*/
if (GRAPHICS_VER(i915) == 11 &&
slices == 1 &&
- subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
+ subslices > min_t(u8, 4, hweight8(sseu->subslice_mask.hsw[0]) / 2)) {
GEM_BUG_ON(subslices & 1);
subslice_pg = false;
@@ -748,14 +766,25 @@ void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
{
int s;
- drm_printf(p, "slice total: %u, mask=%04x\n",
- hweight8(sseu->slice_mask), sseu->slice_mask);
- drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
- for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
- s, intel_sseu_subslices_per_slice(sseu, s),
- intel_sseu_get_subslices(sseu, s));
+ if (sseu->has_xehp_dss) {
+ drm_printf(p, "subslice total: %u\n",
+ intel_sseu_subslice_total(sseu));
+ drm_printf(p, "subslice mask=%*pb\n", I915_MAX_SS_FUSE_BITS,
+ sseu->subslice_mask.xehp);
+ } else {
+ drm_printf(p, "slice total: %u, mask=%04x\n",
+ hweight8(sseu->slice_mask), sseu->slice_mask);
+ drm_printf(p, "subslice total: %u\n",
+ intel_sseu_subslice_total(sseu));
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ u8 ss_mask = sseu->subslice_mask.hsw[s];
+
+ drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
+ s, hweight8(ss_mask), ss_mask);
+ }
}
+
drm_printf(p, "EU total: %u\n", sseu->eu_total);
drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
drm_printf(p, "has slice power gating: %s\n",
@@ -772,9 +801,10 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
int s, ss;
for (s = 0; s < sseu->max_slices; s++) {
+ u8 ss_mask = sseu->subslice_mask.hsw[s];
+
drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
- s, intel_sseu_subslices_per_slice(sseu, s),
- intel_sseu_get_subslices(sseu, s));
+ s, hweight8(ss_mask), ss_mask);
for (ss = 0; ss < sseu->max_subslices; ss++) {
u16 enabled_eus = sseu_get_eus(sseu, s, ss);
@@ -788,16 +818,14 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
static void sseu_print_xehp_topology(const struct sseu_dev_info *sseu,
struct drm_printer *p)
{
- u32 g_dss_mask = sseu_get_geometry_subslices(sseu);
- u32 c_dss_mask = intel_sseu_get_compute_subslices(sseu);
int dss;
for (dss = 0; dss < sseu->max_subslices; dss++) {
u16 enabled_eus = sseu_get_eus(sseu, 0, dss);
drm_printf(p, "DSS_%02d: G:%3s C:%3s, %2u EUs (0x%04hx)\n", dss,
- str_yes_no(g_dss_mask & BIT(dss)),
- str_yes_no(c_dss_mask & BIT(dss)),
+ str_yes_no(test_bit(dss, sseu->geometry_subslice_mask.xehp)),
+ str_yes_no(test_bit(dss, sseu->compute_subslice_mask.xehp)),
hweight16(enabled_eus), enabled_eus);
}
}
@@ -815,20 +843,40 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
}
}
-u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice)
+void intel_sseu_print_ss_info(const char* type,
+ const struct sseu_dev_info *sseu,
+ struct seq_file *m)
+{
+ int s;
+
+ if (sseu->has_xehp_dss)
+ seq_printf(m, " %s Subslices: %u\n", type,
+ bitmap_weight(sseu->subslice_mask.xehp,
+ I915_MAX_SS_FUSE_BITS));
+ else
+ for (s = 0; s < fls(sseu->slice_mask); s++)
+ seq_printf(m, " %s Slice%i subslices: %u\n", type,
+ s, hweight8(sseu->subslice_mask.hsw[s]));
+}
+
+u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask,
+ int dss_per_slice)
{
+ intel_sseu_ss_mask_t per_slice_mask = {};
u16 slice_mask = 0;
int i;
- WARN_ON(sizeof(dss_mask) * 8 / dss_per_slice > 8 * sizeof(slice_mask));
+ WARN_ON(DIV_ROUND_UP(I915_MAX_SS_FUSE_BITS, dss_per_slice) >
+ 8 * sizeof(slice_mask));
- for (i = 0; dss_mask; i++) {
- if (dss_mask & GENMASK(dss_per_slice - 1, 0))
+ bitmap_fill(per_slice_mask.xehp, dss_per_slice);
+ for (i = 0; !bitmap_empty(dss_mask.xehp, I915_MAX_SS_FUSE_BITS); i++) {
+ if (bitmap_intersects(dss_mask.xehp, per_slice_mask.xehp, dss_per_slice))
slice_mask |= BIT(i);
- dss_mask >>= dss_per_slice;
+ bitmap_shift_right(dss_mask.xehp, dss_mask.xehp, dss_per_slice,
+ I915_MAX_SS_FUSE_BITS);
}
return slice_mask;
}
-
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 43a8f8f98687..7fbb9276a1c2 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -25,12 +25,16 @@ struct drm_printer;
/*
* Maximum number of subslices that can exist within a HSW-style slice. This
* is only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the
- * GEN_MAX_DSS value below).
+ * I915_MAX_SS_FUSE_BITS value below).
*/
#define GEN_MAX_SS_PER_HSW_SLICE 6
-/* Maximum number of DSS on newer platforms (Xe_HP and beyond). */
-#define GEN_MAX_DSS 32
+/*
+ * Maximum number of 32-bit registers used by hardware to express the
+ * enabled/disabled subslices.
+ */
+#define I915_MAX_SS_FUSE_REGS 1
+#define I915_MAX_SS_FUSE_BITS (I915_MAX_SS_FUSE_REGS * 32)
/* Maximum number of EUs that can exist within a subslice or DSS. */
#define GEN_MAX_EUS_PER_SS 16
@@ -38,7 +42,7 @@ struct drm_printer;
#define SSEU_MAX(a, b) ((a) > (b) ? (a) : (b))
/* The maximum number of bits needed to express each subslice/DSS independently */
-#define GEN_SS_MASK_SIZE SSEU_MAX(GEN_MAX_DSS, \
+#define GEN_SS_MASK_SIZE SSEU_MAX(I915_MAX_SS_FUSE_BITS, \
GEN_MAX_HSW_SLICES * GEN_MAX_SS_PER_HSW_SLICE)
#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
@@ -49,17 +53,24 @@ struct drm_printer;
#define GEN_DSS_PER_CSLICE 8
#define GEN_DSS_PER_MSLICE 8
-#define GEN_MAX_GSLICES (GEN_MAX_DSS / GEN_DSS_PER_GSLICE)
-#define GEN_MAX_CSLICES (GEN_MAX_DSS / GEN_DSS_PER_CSLICE)
+#define GEN_MAX_GSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_GSLICE)
+#define GEN_MAX_CSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_CSLICE)
+
+typedef union {
+ u8 hsw[GEN_MAX_HSW_SLICES];
+
+ /* Bitmap compatible with linux/bitmap.h; may exceed size of u64 */
+ unsigned long xehp[BITS_TO_LONGS(I915_MAX_SS_FUSE_BITS)];
+} intel_sseu_ss_mask_t;
struct sseu_dev_info {
u8 slice_mask;
- u8 subslice_mask[GEN_SS_MASK_SIZE];
- u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
- u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
+ intel_sseu_ss_mask_t subslice_mask;
+ intel_sseu_ss_mask_t geometry_subslice_mask;
+ intel_sseu_ss_mask_t compute_subslice_mask;
union {
u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
- u16 xehp[GEN_MAX_DSS];
+ u16 xehp[I915_MAX_SS_FUSE_BITS];
} eu_mask;
u16 eu_total;
@@ -100,7 +111,7 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
{
struct intel_sseu value = {
.slice_mask = sseu->slice_mask,
- .subslice_mask = sseu->subslice_mask[0],
+ .subslice_mask = sseu->subslice_mask.hsw[0],
.min_eus_per_subslice = sseu->max_eus_per_subslice,
.max_eus_per_subslice = sseu->max_eus_per_subslice,
};
@@ -112,18 +123,23 @@ static inline bool
intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
int subslice)
{
- u8 mask;
- int ss_idx = subslice / BITS_PER_BYTE;
-
- if (slice >= sseu->max_slices ||
- subslice >= sseu->max_subslices)
- return false;
-
- GEM_BUG_ON(ss_idx >= sseu->ss_stride);
-
- mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx];
+ if (sseu->has_xehp_dss)
+ return test_bit(subslice, sseu->subslice_mask.xehp);
+ else
+ return sseu->subslice_mask.hsw[slice] & BIT(subslice);
+}
- return mask & BIT(subslice % BITS_PER_BYTE);
+/*
+ * Used to obtain the index of the first DSS. Can start searching from the
+ * beginning of a specific dss group (e.g., gslice, cslice, etc.) if
+ * groupsize and groupnum are non-zero.
+ */
+static inline unsigned int
+intel_sseu_find_first_xehp_dss(const struct sseu_dev_info *sseu, int groupsize,
+ int groupnum)
+{
+ return find_next_bit(sseu->subslice_mask.xehp, I915_MAX_SS_FUSE_BITS,
+ groupnum * groupsize);
}
void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
@@ -133,14 +149,10 @@ unsigned int
intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
unsigned int
-intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
-
-u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
+intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice);
-u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
-
-void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
- u8 *subslice_mask, u32 ss_mask);
+intel_sseu_ss_mask_t
+intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
void intel_sseu_info_init(struct intel_gt *gt);
@@ -152,9 +164,15 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
const struct sseu_dev_info *sseu,
struct drm_printer *p);
-u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
+u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask, int dss_per_slice);
int intel_sseu_copy_eumask_to_user(void __user *to,
const struct sseu_dev_info *sseu);
+int intel_sseu_copy_ssmask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu);
+
+void intel_sseu_print_ss_info(const char* type,
+ const struct sseu_dev_info *sseu,
+ struct seq_file *m);
#endif /* __INTEL_SSEU_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
index 2d5d011e01db..d6b75e5127e0 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
@@ -4,6 +4,7 @@
* Copyright © 2020 Intel Corporation
*/
+#include <linux/bitmap.h>
#include <linux/string_helpers.h>
#include "i915_drv.h"
@@ -11,14 +12,6 @@
#include "intel_gt_regs.h"
#include "intel_sseu_debugfs.h"
-static void sseu_copy_subslices(const struct sseu_dev_info *sseu,
- int slice, u8 *to_mask)
-{
- int offset = slice * sseu->ss_stride;
-
- memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
-}
-
static void cherryview_sseu_device_status(struct intel_gt *gt,
struct sseu_dev_info *sseu)
{
@@ -41,7 +34,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt,
continue;
sseu->slice_mask = BIT(0);
- sseu->subslice_mask[0] |= BIT(ss);
+ sseu->subslice_mask.hsw[0] |= BIT(ss);
eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
@@ -92,7 +85,7 @@ static void gen11_sseu_device_status(struct intel_gt *gt,
continue;
sseu->slice_mask |= BIT(s);
- sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -147,21 +140,17 @@ static void gen9_sseu_device_status(struct intel_gt *gt,
sseu->slice_mask |= BIT(s);
if (IS_GEN9_BC(gt->i915))
- sseu_copy_subslices(&info->sseu, s,
- sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
- u8 ss_idx = s * info->sseu.ss_stride +
- ss / BITS_PER_BYTE;
if (IS_GEN9_LP(gt->i915)) {
if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
/* skip disabled subslice */
continue;
- sseu->subslice_mask[ss_idx] |=
- BIT(ss % BITS_PER_BYTE);
+ sseu->subslice_mask.hsw[s] |= BIT(s);
}
eu_cnt = eu_reg[2 * s + ss / 2] & eu_mask[ss % 2];
@@ -188,8 +177,7 @@ static void bdw_sseu_device_status(struct intel_gt *gt,
if (sseu->slice_mask) {
sseu->eu_per_subslice = info->sseu.eu_per_subslice;
for (s = 0; s < fls(sseu->slice_mask); s++)
- sseu_copy_subslices(&info->sseu, s,
- sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
sseu->eu_total = sseu->eu_per_subslice *
intel_sseu_subslice_total(sseu);
@@ -208,7 +196,6 @@ static void i915_print_sseu_info(struct seq_file *m,
const struct sseu_dev_info *sseu)
{
const char *type = is_available_info ? "Available" : "Enabled";
- int s;
seq_printf(m, " %s Slice Mask: %04x\n", type,
sseu->slice_mask);
@@ -216,10 +203,7 @@ static void i915_print_sseu_info(struct seq_file *m,
hweight8(sseu->slice_mask));
seq_printf(m, " %s Subslice Total: %u\n", type,
intel_sseu_subslice_total(sseu));
- for (s = 0; s < fls(sseu->slice_mask); s++) {
- seq_printf(m, " %s Slice%i subslices: %u\n", type,
- s, intel_sseu_subslices_per_slice(sseu, s));
- }
+ intel_sseu_print_ss_info(type, sseu, m);
seq_printf(m, " %s EU Total: %u\n", type,
sseu->eu_total);
seq_printf(m, " %s EU Per Subslice: %u\n", type,
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 756807c4b405..fc6274708f8e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -948,8 +948,8 @@ gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
* on s/ss combo, the read should be done with read_subslice_reg.
*/
slice = ffs(sseu->slice_mask) - 1;
- GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
- subslice = ffs(intel_sseu_get_subslices(sseu, slice));
+ GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw));
+ subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice));
GEM_BUG_ON(!subslice);
subslice--;
@@ -1087,11 +1087,10 @@ static void
icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
{
const struct sseu_dev_info *sseu = >->info.sseu;
- unsigned int slice, subslice;
+ unsigned int subslice;
GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
- slice = 0;
/*
* Although a platform may have subslices, we need to always steer
@@ -1102,7 +1101,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
* one of the higher subslices, we run the risk of reading back 0's or
* random garbage.
*/
- subslice = __ffs(intel_sseu_get_subslices(sseu, slice));
+ subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0));
/*
* If the subslice we picked above also steers us to a valid L3 bank,
@@ -1112,7 +1111,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
if (gt->info.l3bank_mask & BIT(subslice))
gt->steering_table[L3BANK] = NULL;
- __add_mcr_wa(gt, wal, slice, subslice);
+ __add_mcr_wa(gt, wal, 0, subslice);
}
static void
@@ -1120,7 +1119,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
{
const struct sseu_dev_info *sseu = >->info.sseu;
unsigned long slice, subslice = 0, slice_mask = 0;
- u64 dss_mask = 0;
u32 lncf_mask = 0;
int i;
@@ -1151,8 +1149,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
*/
/* Find the potential gslice candidates */
- dss_mask = intel_sseu_get_subslices(sseu, 0);
- slice_mask = intel_slicemask_from_dssmask(dss_mask, GEN_DSS_PER_GSLICE);
+ slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask,
+ GEN_DSS_PER_GSLICE);
/*
* Find the potential LNCF candidates. Either LNCF within a valid
@@ -1177,9 +1175,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
}
slice = __ffs(slice_mask);
- subslice = __ffs(dss_mask >> (slice * GEN_DSS_PER_GSLICE));
+ subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice);
WARN_ON(subslice > GEN_DSS_PER_GSLICE);
- WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0);
__add_mcr_wa(gt, wal, slice, subslice);
@@ -2030,9 +2027,8 @@ engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
static bool needs_wa_1308578152(struct intel_engine_cs *engine)
{
- u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0);
-
- return (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0;
+ return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >
+ GEN_DSS_PER_GSLICE;
}
static void
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index ac9767c56619..6fd15b39570c 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -162,8 +162,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
return -EINVAL;
/* Only copy bits from the first slice */
- memcpy(&value, sseu->subslice_mask,
- min(sseu->ss_stride, (u8)sizeof(value)));
+ value = intel_sseu_get_hsw_subslices(sseu, 0);
if (!value)
return -ENODEV;
break;
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 16f43bf32a05..9afa6d1eaf95 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -31,7 +31,7 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
static int fill_topology_info(const struct sseu_dev_info *sseu,
struct drm_i915_query_item *query_item,
- const u8 *subslice_mask)
+ intel_sseu_ss_mask_t subslice_mask)
{
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
@@ -71,9 +71,9 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
&sseu->slice_mask, slice_length))
return -EFAULT;
- if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
- sizeof(topo) + slice_length),
- subslice_mask, subslice_length))
+ if (intel_sseu_copy_ssmask_to_user(u64_to_user_ptr(query_item->data_ptr +
+ sizeof(topo) + slice_length),
+ sseu))
return -EFAULT;
if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
--
2.35.3
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 6/6] drm/i915/pvc: Add SSEU changes
2022-05-17 3:19 ` [Intel-gfx] " Matt Roper
@ 2022-05-17 3:20 ` Matt Roper
-1 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2022-05-17 3:20 UTC (permalink / raw)
To: intel-gfx; +Cc: tvrtko.ursulin, dri-devel
PVC splits the mask of enabled DSS over two registers. It also changes
the meaning of the EU fuse register such that each bit represents a
single EU rather than a pair of EUs.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_sseu.c | 31 ++++++++++++++++++------
drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
6 files changed, 31 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 98ede9c93f00..4ba7f1ad9510 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -561,6 +561,7 @@
#define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
#define GEN12_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144)
+#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT _MMIO(0x9148)
#define GEN6_UCGCTL1 _MMIO(0x9400)
#define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index e1bce8a9044e..10e6e450019f 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -212,27 +212,44 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
struct intel_uncore *uncore = gt->uncore;
u16 eu_en = 0;
u8 eu_en_fuse;
+ int num_compute_regs, num_geometry_regs;
int eu;
+ if (IS_PONTEVECCHIO(gt->i915)) {
+ num_geometry_regs = 0;
+ num_compute_regs = 2;
+ } else {
+ num_geometry_regs = 1;
+ num_compute_regs = 1;
+ }
+
/*
* The concept of slice has been removed in Xe_HP. To be compatible
* with prior generations, assume a single slice across the entire
* device. Then calculate out the DSS for each workload type within
* that software slice.
*/
- intel_sseu_set_info(sseu, 1, 32, 16);
+ intel_sseu_set_info(sseu, 1,
+ 32 * max(num_geometry_regs, num_compute_regs),
+ 16);
sseu->has_xehp_dss = 1;
- xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 1,
+ xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask,
+ num_geometry_regs,
GEN12_GT_GEOMETRY_DSS_ENABLE);
- xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 1,
- GEN12_GT_COMPUTE_DSS_ENABLE);
+ xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask,
+ num_compute_regs,
+ GEN12_GT_COMPUTE_DSS_ENABLE,
+ XEHPC_GT_COMPUTE_DSS_ENABLE_EXT);
eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
- for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
- if (eu_en_fuse & BIT(eu))
- eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
+ if (HAS_ONE_EU_PER_FUSE_BIT(gt->i915))
+ eu_en = eu_en_fuse;
+ else
+ for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
+ if (eu_en_fuse & BIT(eu))
+ eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
xehp_compute_sseu_info(sseu, eu_en);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 7fbb9276a1c2..647301569707 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -33,7 +33,7 @@ struct drm_printer;
* Maximum number of 32-bit registers used by hardware to express the
* enabled/disabled subslices.
*/
-#define I915_MAX_SS_FUSE_REGS 1
+#define I915_MAX_SS_FUSE_REGS 2
#define I915_MAX_SS_FUSE_BITS (I915_MAX_SS_FUSE_REGS * 32)
/* Maximum number of EUs that can exist within a subslice or DSS. */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 10f273800645..afafc083c31d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1405,6 +1405,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915))
+#define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
+
/* i915_gem.c */
void i915_gem_init_early(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d8d893bafa51..2952e8e51885 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1050,7 +1050,8 @@ static const struct intel_device_info ats_m_info = {
#define XE_HPC_FEATURES \
XE_HP_FEATURES, \
.dma_mask_size = 52, \
- .has_l3_ccs_read = 1
+ .has_l3_ccs_read = 1, \
+ .has_one_eu_per_fuse_bit = 1
__maybe_unused
static const struct intel_device_info pvc_info = {
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 60fc35ae81df..b20ef217bf75 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -153,6 +153,7 @@ enum intel_ppgtt_type {
func(has_llc); \
func(has_logical_ring_contexts); \
func(has_mslices); \
+ func(has_one_eu_per_fuse_bit); \
func(has_pooled_eu); \
func(has_pxp); \
func(has_rc6p); \
--
2.35.3
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [Intel-gfx] [PATCH v2 6/6] drm/i915/pvc: Add SSEU changes
@ 2022-05-17 3:20 ` Matt Roper
0 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2022-05-17 3:20 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
PVC splits the mask of enabled DSS over two registers. It also changes
the meaning of the EU fuse register such that each bit represents a
single EU rather than a pair of EUs.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_sseu.c | 31 ++++++++++++++++++------
drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
6 files changed, 31 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 98ede9c93f00..4ba7f1ad9510 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -561,6 +561,7 @@
#define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
#define GEN12_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144)
+#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT _MMIO(0x9148)
#define GEN6_UCGCTL1 _MMIO(0x9400)
#define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index e1bce8a9044e..10e6e450019f 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -212,27 +212,44 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
struct intel_uncore *uncore = gt->uncore;
u16 eu_en = 0;
u8 eu_en_fuse;
+ int num_compute_regs, num_geometry_regs;
int eu;
+ if (IS_PONTEVECCHIO(gt->i915)) {
+ num_geometry_regs = 0;
+ num_compute_regs = 2;
+ } else {
+ num_geometry_regs = 1;
+ num_compute_regs = 1;
+ }
+
/*
* The concept of slice has been removed in Xe_HP. To be compatible
* with prior generations, assume a single slice across the entire
* device. Then calculate out the DSS for each workload type within
* that software slice.
*/
- intel_sseu_set_info(sseu, 1, 32, 16);
+ intel_sseu_set_info(sseu, 1,
+ 32 * max(num_geometry_regs, num_compute_regs),
+ 16);
sseu->has_xehp_dss = 1;
- xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 1,
+ xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask,
+ num_geometry_regs,
GEN12_GT_GEOMETRY_DSS_ENABLE);
- xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 1,
- GEN12_GT_COMPUTE_DSS_ENABLE);
+ xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask,
+ num_compute_regs,
+ GEN12_GT_COMPUTE_DSS_ENABLE,
+ XEHPC_GT_COMPUTE_DSS_ENABLE_EXT);
eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
- for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
- if (eu_en_fuse & BIT(eu))
- eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
+ if (HAS_ONE_EU_PER_FUSE_BIT(gt->i915))
+ eu_en = eu_en_fuse;
+ else
+ for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
+ if (eu_en_fuse & BIT(eu))
+ eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
xehp_compute_sseu_info(sseu, eu_en);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 7fbb9276a1c2..647301569707 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -33,7 +33,7 @@ struct drm_printer;
* Maximum number of 32-bit registers used by hardware to express the
* enabled/disabled subslices.
*/
-#define I915_MAX_SS_FUSE_REGS 1
+#define I915_MAX_SS_FUSE_REGS 2
#define I915_MAX_SS_FUSE_BITS (I915_MAX_SS_FUSE_REGS * 32)
/* Maximum number of EUs that can exist within a subslice or DSS. */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 10f273800645..afafc083c31d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1405,6 +1405,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915))
+#define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
+
/* i915_gem.c */
void i915_gem_init_early(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d8d893bafa51..2952e8e51885 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1050,7 +1050,8 @@ static const struct intel_device_info ats_m_info = {
#define XE_HPC_FEATURES \
XE_HP_FEATURES, \
.dma_mask_size = 52, \
- .has_l3_ccs_read = 1
+ .has_l3_ccs_read = 1, \
+ .has_one_eu_per_fuse_bit = 1
__maybe_unused
static const struct intel_device_info pvc_info = {
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 60fc35ae81df..b20ef217bf75 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -153,6 +153,7 @@ enum intel_ppgtt_type {
func(has_llc); \
func(has_logical_ring_contexts); \
func(has_mslices); \
+ func(has_one_eu_per_fuse_bit); \
func(has_pooled_eu); \
func(has_pxp); \
func(has_rc6p); \
--
2.35.3
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: SSEU handling updates (rev3)
2022-05-17 3:19 ` [Intel-gfx] " Matt Roper
` (6 preceding siblings ...)
(?)
@ 2022-05-17 3:40 ` Patchwork
-1 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2022-05-17 3:40 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: i915: SSEU handling updates (rev3)
URL : https://patchwork.freedesktop.org/series/103244/
State : warning
== Summary ==
Error: dim checkpatch failed
908d6ce4c18e drm/i915/xehp: Use separate sseu init function
358b3a7e510b drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
a75fd2d407d9 drm/i915/sseu: Simplify gen11+ SSEU handling
65bdff270cbf drm/i915/sseu: Don't try to store EU mask internally in UAPI format
f155547ecc37 drm/i915/sseu: Disassociate internal subslice mask representation from uapi
-:478: ERROR:POINTER_LOCATION: "foo* bar" should be "foo *bar"
#478: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:846:
+void intel_sseu_print_ss_info(const char* type,
-:562: WARNING:NEW_TYPEDEFS: do not add new typedefs
#562: FILE: drivers/gpu/drm/i915/gt/intel_sseu.h:59:
+typedef union {
-:658: ERROR:POINTER_LOCATION: "foo* bar" should be "foo *bar"
#658: FILE: drivers/gpu/drm/i915/gt/intel_sseu.h:174:
+void intel_sseu_print_ss_info(const char* type,
total: 2 errors, 1 warnings, 0 checks, 779 lines checked
05b8f2e9119f drm/i915/pvc: Add SSEU changes
^ permalink raw reply [flat|nested] 43+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: SSEU handling updates (rev3)
2022-05-17 3:19 ` [Intel-gfx] " Matt Roper
` (7 preceding siblings ...)
(?)
@ 2022-05-17 3:40 ` Patchwork
-1 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2022-05-17 3:40 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: i915: SSEU handling updates (rev3)
URL : https://patchwork.freedesktop.org/series/103244/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 43+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for i915: SSEU handling updates (rev3)
2022-05-17 3:19 ` [Intel-gfx] " Matt Roper
` (8 preceding siblings ...)
(?)
@ 2022-05-17 4:05 ` Patchwork
-1 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2022-05-17 4:05 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5375 bytes --]
== Series Details ==
Series: i915: SSEU handling updates (rev3)
URL : https://patchwork.freedesktop.org/series/103244/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11662 -> Patchwork_103244v3
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/index.html
Participating hosts (43 -> 43)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_103244v3 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [PASS][1] -> [DMESG-FAIL][2] ([i915#4494] / [i915#4957])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
* igt@kms_busy@basic@modeset:
- bat-adlp-4: [PASS][3] -> [DMESG-WARN][4] ([i915#3576])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/bat-adlp-4/igt@kms_busy@basic@modeset.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/bat-adlp-4/igt@kms_busy@basic@modeset.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-blb-e6850: NOTRUN -> [SKIP][5] ([fdo#109271])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/fi-blb-e6850/igt@kms_chamelium@common-hpd-after-suspend.html
#### Possible fixes ####
* igt@debugfs_test@read_all_entries:
- fi-kbl-soraka: [DMESG-WARN][6] ([i915#1982]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html
* igt@i915_selftest@live@active:
- {bat-dg2-9}: [DMESG-WARN][8] ([i915#5763]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/bat-dg2-9/igt@i915_selftest@live@active.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/bat-dg2-9/igt@i915_selftest@live@active.html
* igt@i915_selftest@live@gem_contexts:
- {bat-dg2-9}: [DMESG-FAIL][10] ([i915#5763] / [i915#5885]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/bat-dg2-9/igt@i915_selftest@live@gem_contexts.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/bat-dg2-9/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [DMESG-FAIL][12] ([i915#4528]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/fi-blb-e6850/igt@i915_selftest@live@requests.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/fi-blb-e6850/igt@i915_selftest@live@requests.html
* igt@kms_busy@basic@flip:
- {bat-adlp-6}: [DMESG-WARN][14] ([i915#3576]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/bat-adlp-6/igt@kms_busy@basic@flip.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/bat-adlp-6/igt@kms_busy@basic@flip.html
* igt@kms_flip@basic-flip-vs-modeset@b-edp1:
- bat-adlp-4: [DMESG-WARN][16] ([i915#3576]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
[i915#5879]: https://gitlab.freedesktop.org/drm/intel/issues/5879
[i915#5885]: https://gitlab.freedesktop.org/drm/intel/issues/5885
Build changes
-------------
* Linux: CI_DRM_11662 -> Patchwork_103244v3
CI-20190529: 20190529
CI_DRM_11662: 38bc558d7aba4f111c5cf767bfdd89c722ba0415 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6474: f4731438344390afe165ac41ee9e2a2e77e3d932 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103244v3: 38bc558d7aba4f111c5cf767bfdd89c722ba0415 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
62363383f768 drm/i915/pvc: Add SSEU changes
47e20bf519c9 drm/i915/sseu: Disassociate internal subslice mask representation from uapi
1438e526bb4c drm/i915/sseu: Don't try to store EU mask internally in UAPI format
20588fd9c3cd drm/i915/sseu: Simplify gen11+ SSEU handling
0d80405aee90 drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
c884dd83b006 drm/i915/xehp: Use separate sseu init function
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/index.html
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^ permalink raw reply [flat|nested] 43+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: SSEU handling updates (rev3)
2022-05-17 3:19 ` [Intel-gfx] " Matt Roper
` (9 preceding siblings ...)
(?)
@ 2022-05-17 6:25 ` Patchwork
-1 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2022-05-17 6:25 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 63538 bytes --]
== Series Details ==
Series: i915: SSEU handling updates (rev3)
URL : https://patchwork.freedesktop.org/series/103244/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11662_full -> Patchwork_103244v3_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_103244v3_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_103244v3_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 13)
------------------------------
Additional (3): shard-rkl shard-dg1 shard-tglu
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_103244v3_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_await@wide-all:
- shard-skl: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl6/igt@gem_exec_await@wide-all.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl7/igt@gem_exec_await@wide-all.html
* igt@i915_pm_sseu@full-enable:
- shard-apl: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-apl3/igt@i915_pm_sseu@full-enable.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-apl6/igt@i915_pm_sseu@full-enable.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-glk: [PASS][5] -> [FAIL][6] +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-glk7/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-glk3/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_whisper@basic-fds:
- {shard-rkl}: NOTRUN -> [INCOMPLETE][7]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-rkl-5/igt@gem_exec_whisper@basic-fds.html
* igt@i915_suspend@basic-s2idle-without-i915:
- {shard-dg1}: NOTRUN -> [INCOMPLETE][8]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-dg1-19/igt@i915_suspend@basic-s2idle-without-i915.html
New tests
---------
New tests have been introduced between CI_DRM_11662_full and Patchwork_103244v3_full:
### New IGT tests (4) ###
* igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-3-downscale-with-pixel-format:
- Statuses : 1 skip(s)
- Exec time: [0.03] s
* igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-25@pipe-b-hdmi-a-3-downscale-with-pixel-format:
- Statuses : 1 skip(s)
- Exec time: [0.02] s
* igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-25@pipe-c-hdmi-a-3-downscale-with-pixel-format:
- Statuses : 1 skip(s)
- Exec time: [0.02] s
* igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-25@pipe-d-hdmi-a-3-downscale-with-pixel-format:
- Statuses : 1 skip(s)
- Exec time: [0.02] s
Known issues
------------
Here are the changes found in Patchwork_103244v3_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-skl: ([PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31]) -> ([PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [FAIL][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56]) ([i915#5032])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl4/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl7/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl7/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl7/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl6/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl6/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl6/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl1/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl4/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl4/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl10/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl10/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl10/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl1/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl1/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl1/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl9/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl9/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl9/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl9/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl8/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl8/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl8/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl9/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl9/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl8/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl8/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl8/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl7/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl7/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl7/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl6/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl6/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl6/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl6/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl4/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl4/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl4/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl3/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl3/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl3/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl1/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl1/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl1/boot.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl10/boot.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl10/boot.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl10/boot.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl10/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][57] -> [FAIL][58] ([i915#2842]) +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: NOTRUN -> [FAIL][59] ([i915#2842])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb4/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][60] -> [FAIL][61] ([i915#2842])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-apl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-apl2/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_params@rsvd2-dirt:
- shard-iclb: NOTRUN -> [SKIP][62] ([fdo#109283])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb4/igt@gem_exec_params@rsvd2-dirt.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: NOTRUN -> [SKIP][63] ([i915#2190])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-multi:
- shard-apl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#4613])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-apl3/igt@gem_lmem_swapping@parallel-multi.html
* igt@gem_lmem_swapping@random-engines:
- shard-iclb: NOTRUN -> [SKIP][65] ([i915#4613])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb4/igt@gem_lmem_swapping@random-engines.html
- shard-skl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#4613]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl4/igt@gem_lmem_swapping@random-engines.html
- shard-kbl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#4613]) +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl1/igt@gem_lmem_swapping@random-engines.html
* igt@gem_pwrite@basic-exhaustion:
- shard-skl: NOTRUN -> [WARN][68] ([i915#2658])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl8/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_pxp@create-regular-context-2:
- shard-tglb: NOTRUN -> [SKIP][69] ([i915#4270])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb6/igt@gem_pxp@create-regular-context-2.html
* igt@gem_pxp@reject-modify-context-protection-off-3:
- shard-iclb: NOTRUN -> [SKIP][70] ([i915#4270])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb4/igt@gem_pxp@reject-modify-context-protection-off-3.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled:
- shard-iclb: NOTRUN -> [SKIP][71] ([i915#768])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb8/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled.html
* igt@gem_userptr_blits@access-control:
- shard-iclb: NOTRUN -> [SKIP][72] ([i915#3297]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb4/igt@gem_userptr_blits@access-control.html
* igt@gem_userptr_blits@readonly-unsync:
- shard-tglb: NOTRUN -> [SKIP][73] ([i915#3297])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb6/igt@gem_userptr_blits@readonly-unsync.html
* igt@gen9_exec_parse@bb-oversize:
- shard-tglb: NOTRUN -> [SKIP][74] ([i915#2527] / [i915#2856])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb6/igt@gen9_exec_parse@bb-oversize.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-iclb: NOTRUN -> [SKIP][75] ([i915#2856])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb4/igt@gen9_exec_parse@bb-start-cmd.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][76] -> [FAIL][77] ([i915#454])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-iclb6/igt@i915_pm_dc@dc6-dpms.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
- shard-kbl: NOTRUN -> [FAIL][78] ([i915#454])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl6/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@cursor-dpms:
- shard-tglb: [PASS][79] -> [INCOMPLETE][80] ([i915#2411])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-tglb6/igt@i915_pm_rpm@cursor-dpms.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb8/igt@i915_pm_rpm@cursor-dpms.html
* igt@i915_query@query-topology-unsupported:
- shard-tglb: NOTRUN -> [SKIP][81] ([fdo#109302])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb6/igt@i915_query@query-topology-unsupported.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-skl: [PASS][82] -> [INCOMPLETE][83] ([i915#4817] / [i915#4939])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl8/igt@i915_suspend@fence-restore-tiled2untiled.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl6/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_async_flips@crc:
- shard-skl: NOTRUN -> [FAIL][84] ([i915#4272])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl1/igt@kms_async_flips@crc.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][85] ([i915#5286]) +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb6/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-iclb: NOTRUN -> [SKIP][86] ([i915#5286]) +2 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb8/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][87] ([fdo#110725] / [fdo#111614])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb4/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][88] ([fdo#111614])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb6/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][89] ([fdo#111615])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb6/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180:
- shard-iclb: NOTRUN -> [SKIP][90] ([fdo#110723])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb4/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#3886]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl6/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][92] ([fdo#109278] / [i915#3886]) +2 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb4/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][93] ([fdo#111615] / [i915#3689])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb6/igt@kms_ccs@pipe-a-missing-ccs-buffer-yf_tiled_ccs.html
* igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs:
- shard-glk: NOTRUN -> [SKIP][94] ([fdo#109271]) +29 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-glk9/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#3886])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl8/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][96] ([i915#3689] / [i915#3886])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb6/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#3886]) +3 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-apl8/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#3886]) +1 similar issue
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-glk9/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][99] ([i915#3689])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb6/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_ccs.html
* igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][100] ([fdo#109271]) +85 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl6/igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@dp-hpd-storm-disable:
- shard-apl: NOTRUN -> [SKIP][101] ([fdo#109271] / [fdo#111827]) +3 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-apl8/igt@kms_chamelium@dp-hpd-storm-disable.html
* igt@kms_chamelium@hdmi-crc-nonplanar-formats:
- shard-kbl: NOTRUN -> [SKIP][102] ([fdo#109271] / [fdo#111827]) +5 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl7/igt@kms_chamelium@hdmi-crc-nonplanar-formats.html
* igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
- shard-glk: NOTRUN -> [SKIP][103] ([fdo#109271] / [fdo#111827]) +2 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-glk9/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
* igt@kms_color_chamelium@pipe-a-ctm-limited-range:
- shard-tglb: NOTRUN -> [SKIP][104] ([fdo#109284] / [fdo#111827]) +4 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb6/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-b-ctm-green-to-red:
- shard-skl: NOTRUN -> [SKIP][105] ([fdo#109271] / [fdo#111827]) +6 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl8/igt@kms_color_chamelium@pipe-b-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-b-gamma:
- shard-iclb: NOTRUN -> [SKIP][106] ([fdo#109284] / [fdo#111827]) +1 similar issue
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb4/igt@kms_color_chamelium@pipe-b-gamma.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-tglb: NOTRUN -> [SKIP][107] ([i915#3116] / [i915#3299])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb6/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-iclb: NOTRUN -> [SKIP][108] ([i915#3116])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb4/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_cursor_crc@pipe-a-cursor-256x256-rapid-movement:
- shard-snb: [PASS][109] -> [SKIP][110] ([fdo#109271]) +1 similar issue
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-snb2/igt@kms_cursor_crc@pipe-a-cursor-256x256-rapid-movement.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-snb2/igt@kms_cursor_crc@pipe-a-cursor-256x256-rapid-movement.html
* igt@kms_cursor_crc@pipe-a-cursor-max-size-offscreen:
- shard-iclb: NOTRUN -> [SKIP][111] ([fdo#109278]) +9 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb4/igt@kms_cursor_crc@pipe-a-cursor-max-size-offscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-max-size-onscreen:
- shard-tglb: NOTRUN -> [SKIP][112] ([i915#3359])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb6/igt@kms_cursor_crc@pipe-b-cursor-max-size-onscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: NOTRUN -> [DMESG-WARN][113] ([i915#180]) +1 similar issue
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-apl4/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-512x170-sliding:
- shard-apl: NOTRUN -> [SKIP][114] ([fdo#109271] / [i915#5691])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-apl8/igt@kms_cursor_crc@pipe-c-cursor-512x170-sliding.html
* igt@kms_cursor_crc@pipe-c-cursor-512x512-rapid-movement:
- shard-iclb: NOTRUN -> [SKIP][115] ([fdo#109278] / [fdo#109279])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb8/igt@kms_cursor_crc@pipe-c-cursor-512x512-rapid-movement.html
* igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
- shard-iclb: NOTRUN -> [SKIP][116] ([fdo#109274] / [fdo#109278])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb4/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-iclb: [PASS][117] -> [FAIL][118] ([i915#2346])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-iclb3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-4tiled:
- shard-iclb: NOTRUN -> [SKIP][119] ([i915#5287])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb4/igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-4tiled.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank:
- shard-tglb: NOTRUN -> [SKIP][120] ([fdo#109274] / [fdo#111825]) +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb6/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html
* igt@kms_flip@2x-nonexisting-fb-interruptible:
- shard-iclb: NOTRUN -> [SKIP][121] ([fdo#109274])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb4/igt@kms_flip@2x-nonexisting-fb-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [PASS][122] -> [FAIL][123] ([i915#79]) +1 similar issue
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
- shard-skl: [PASS][124] -> [FAIL][125] ([i915#2122]) +2 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl7/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl3/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt:
- shard-skl: NOTRUN -> [SKIP][126] ([fdo#109271]) +112 similar issues
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl1/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move:
- shard-iclb: NOTRUN -> [SKIP][127] ([fdo#109280]) +9 similar issues
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-tglb: NOTRUN -> [SKIP][128] ([fdo#109280] / [fdo#111825]) +6 similar issues
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-cpu.html
* igt@kms_hdmi_inject@inject-audio:
- shard-tglb: NOTRUN -> [SKIP][129] ([i915#433])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb6/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][130] ([fdo#109271] / [i915#533])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-apl8/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][131] ([fdo#109271] / [i915#533])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl6/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-skl: [PASS][132] -> [INCOMPLETE][133] ([i915#4939])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl9/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-glk: NOTRUN -> [FAIL][134] ([fdo#108145] / [i915#265])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-glk9/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [PASS][135] -> [FAIL][136] ([fdo#108145] / [i915#265]) +1 similar issue
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][137] ([i915#265])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl3/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
- shard-skl: NOTRUN -> [FAIL][138] ([i915#265])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: NOTRUN -> [SKIP][139] ([i915#3536])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_plane_lowres@pipe-a-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][140] ([fdo#111615] / [fdo#112054])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb6/igt@kms_plane_lowres@pipe-a-tiling-yf.html
* igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-25@pipe-d-hdmi-a-3-downscale-with-pixel-format (NEW):
- {shard-dg1}: NOTRUN -> [SKIP][141] ([i915#5176]) +3 similar issues
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-dg1-18/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-25@pipe-d-hdmi-a-3-downscale-with-pixel-format.html
* igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-5@pipe-c-edp-1-downscale-with-pixel-format:
- shard-iclb: [PASS][142] -> [SKIP][143] ([i915#5176]) +2 similar issues
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-iclb3/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-5@pipe-c-edp-1-downscale-with-pixel-format.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb2/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-5@pipe-c-edp-1-downscale-with-pixel-format.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale:
- shard-iclb: [PASS][144] -> [SKIP][145] ([i915#5235]) +5 similar issues
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-iclb4/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-kbl: NOTRUN -> [SKIP][146] ([fdo#109271] / [i915#658])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl6/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-skl: NOTRUN -> [SKIP][147] ([fdo#109271] / [i915#658])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-apl: NOTRUN -> [SKIP][148] ([fdo#109271] / [i915#658])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-apl3/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-p010:
- shard-iclb: NOTRUN -> [SKIP][149] ([fdo#109642] / [fdo#111068] / [i915#658])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb4/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [PASS][150] -> [SKIP][151] ([fdo#109441]) +2 similar issues
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb8/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- shard-apl: NOTRUN -> [SKIP][152] ([fdo#109271]) +54 similar issues
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-apl8/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
* igt@nouveau_crc@pipe-b-ctx-flip-detection:
- shard-tglb: NOTRUN -> [SKIP][153] ([i915#2530])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb6/igt@nouveau_crc@pipe-b-ctx-flip-detection.html
* igt@perf_pmu@rc6-suspend:
- shard-kbl: [PASS][154] -> [DMESG-WARN][155] ([i915#180]) +7 similar issues
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-kbl1/igt@perf_pmu@rc6-suspend.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl7/igt@perf_pmu@rc6-suspend.html
* igt@prime_nv_pcopy@test3_2:
- shard-tglb: NOTRUN -> [SKIP][156] ([fdo#109291])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb6/igt@prime_nv_pcopy@test3_2.html
* igt@prime_vgem@coherency-gtt:
- shard-tglb: NOTRUN -> [SKIP][157] ([fdo#111656])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb6/igt@prime_vgem@coherency-gtt.html
* igt@sysfs_clients@busy:
- shard-glk: NOTRUN -> [SKIP][158] ([fdo#109271] / [i915#2994])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-glk9/igt@sysfs_clients@busy.html
* igt@sysfs_clients@create:
- shard-skl: NOTRUN -> [SKIP][159] ([fdo#109271] / [i915#2994]) +2 similar issues
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl1/igt@sysfs_clients@create.html
* igt@sysfs_clients@pidname:
- shard-kbl: NOTRUN -> [SKIP][160] ([fdo#109271] / [i915#2994])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl6/igt@sysfs_clients@pidname.html
* igt@sysfs_clients@sema-25:
- shard-iclb: NOTRUN -> [SKIP][161] ([i915#2994])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb8/igt@sysfs_clients@sema-25.html
#### Possible fixes ####
* igt@gem_eio@kms:
- shard-tglb: [FAIL][162] ([i915#5784]) -> [PASS][163]
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-tglb5/igt@gem_eio@kms.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb7/igt@gem_eio@kms.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-kbl: [FAIL][164] ([i915#2842]) -> [PASS][165] +1 similar issue
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-kbl4/igt@gem_exec_fair@basic-none@rcs0.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl1/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][166] ([i915#2842]) -> [PASS][167]
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][168] ([i915#2842]) -> [PASS][169]
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_flush@basic-wb-ro-before-default:
- shard-snb: [SKIP][170] ([fdo#109271]) -> [PASS][171] +2 similar issues
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-snb6/igt@gem_exec_flush@basic-wb-ro-before-default.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-snb4/igt@gem_exec_flush@basic-wb-ro-before-default.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][172] ([i915#454]) -> [PASS][173]
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb2/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@fences:
- shard-iclb: [INCOMPLETE][174] ([i915#5096]) -> [PASS][175]
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-iclb7/igt@i915_pm_rpm@fences.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb4/igt@i915_pm_rpm@fences.html
* igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@1x-outputs:
- shard-skl: [DMESG-WARN][176] ([i915#1982]) -> [PASS][177]
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl10/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@1x-outputs.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl1/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@1x-outputs.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-apl: [DMESG-WARN][178] ([i915#180]) -> [PASS][179] +2 similar issues
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-apl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-apl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-iclb: [FAIL][180] ([i915#2346]) -> [PASS][181]
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2:
- shard-glk: [FAIL][182] ([i915#79]) -> [PASS][183]
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-glk7/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-glk3/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html
* igt@kms_flip@plain-flip-fb-recreate@a-edp1:
- shard-skl: [FAIL][184] ([i915#2122]) -> [PASS][185]
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl6/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl7/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
- shard-iclb: [SKIP][186] ([i915#3701]) -> [PASS][187]
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [DMESG-WARN][188] ([i915#180]) -> [PASS][189] +3 similar issues
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-skl: [INCOMPLETE][190] ([i915#4444] / [i915#4939]) -> [PASS][191]
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping:
- shard-iclb: [SKIP][192] ([i915#5176]) -> [PASS][193] +1 similar issue
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-iclb3/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping.html
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb7/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [SKIP][194] ([fdo#109441]) -> [PASS][195]
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-iclb3/igt@kms_psr@psr2_primary_mmap_gtt.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-iclb: [SKIP][196] ([i915#5519]) -> [PASS][197]
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-iclb5/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb5/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@perf@oa-exponents:
- shard-glk: [INCOMPLETE][198] ([i915#5213]) -> [PASS][199]
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-glk1/igt@perf@oa-exponents.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-glk9/igt@perf@oa-exponents.html
* igt@perf@polling:
- shard-skl: [FAIL][200] ([i915#1542]) -> [PASS][201]
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl8/igt@perf@polling.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl8/igt@perf@polling.html
#### Warnings ####
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][202] ([i915#3063]) -> [FAIL][203] ([i915#5784])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-tglb7/igt@gem_eio@unwedge-stress.html
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb5/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [DMESG-WARN][204] ([i915#5614]) -> [SKIP][205] ([i915#4525])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-iclb2/igt@gem_exec_balancer@parallel-keep-in-fence.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb8/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [SKIP][206] ([i915#4525]) -> [DMESG-WARN][207] ([i915#5614])
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-iclb3/igt@gem_exec_balancer@parallel-out-fence.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb2/igt@gem_exec_balancer@parallel-out-fence.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt:
- shard-skl: [SKIP][208] ([fdo#109271] / [i915#1888]) -> [SKIP][209] ([fdo#109271]) +1 similar issue
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-skl6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt.html
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-skl7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-iclb: [SKIP][210] ([i915#2920]) -> [SKIP][211] ([fdo#111068] / [i915#658])
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-iclb8/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
* igt@runner@aborted:
- shard-tglb: ([FAIL][212], [FAIL][213], [FAIL][214], [FAIL][215], [FAIL][216], [FAIL][217], [FAIL][218], [FAIL][219], [FAIL][220], [FAIL][221], [FAIL][222]) ([i915#3002] / [i915#3690] / [i915#4312] / [i915#5257]) -> ([FAIL][223], [FAIL][224], [FAIL][225], [FAIL][226], [FAIL][227], [FAIL][228], [FAIL][229], [FAIL][230], [FAIL][231], [FAIL][232]) ([i915#3002] / [i915#4312] / [i915#5257])
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-tglb8/igt@runner@aborted.html
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-tglb8/igt@runner@aborted.html
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-tglb8/igt@runner@aborted.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-tglb1/igt@runner@aborted.html
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-tglb2/igt@runner@aborted.html
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-tglb1/igt@runner@aborted.html
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-tglb1/igt@runner@aborted.html
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-tglb2/igt@runner@aborted.html
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-tglb3/igt@runner@aborted.html
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-tglb7/igt@runner@aborted.html
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-tglb7/igt@runner@aborted.html
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb7/igt@runner@aborted.html
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb1/igt@runner@aborted.html
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb3/igt@runner@aborted.html
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb1/igt@runner@aborted.html
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb5/igt@runner@aborted.html
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb3/igt@runner@aborted.html
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb2/igt@runner@aborted.html
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb1/igt@runner@aborted.html
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb6/igt@runner@aborted.html
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-tglb6/igt@runner@aborted.html
- shard-kbl: ([FAIL][233], [FAIL][234], [FAIL][235], [FAIL][236], [FAIL][237], [FAIL][238], [FAIL][239], [FAIL][240], [FAIL][241], [FAIL][242], [FAIL][243], [FAIL][244], [FAIL][245], [FAIL][246]) ([fdo#109271] / [i915#4312] / [i915#5257]) -> ([FAIL][247], [FAIL][248], [FAIL][249], [FAIL][250], [FAIL][251], [FAIL][252], [FAIL][253], [FAIL][254], [FAIL][255], [FAIL][256], [FAIL][257], [FAIL][258], [FAIL][259], [FAIL][260], [FAIL][261]) ([i915#180] / [i915#4312] / [i915#5257])
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-kbl4/igt@runner@aborted.html
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-kbl6/igt@runner@aborted.html
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-kbl7/igt@runner@aborted.html
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-kbl7/igt@runner@aborted.html
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-kbl6/igt@runner@aborted.html
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-kbl3/igt@runner@aborted.html
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-kbl4/igt@runner@aborted.html
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-kbl6/igt@runner@aborted.html
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-kbl4/igt@runner@aborted.html
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-kbl3/igt@runner@aborted.html
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-kbl1/igt@runner@aborted.html
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-kbl6/igt@runner@aborted.html
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-kbl4/igt@runner@aborted.html
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11662/shard-kbl4/igt@runner@aborted.html
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl3/igt@runner@aborted.html
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl6/igt@runner@aborted.html
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl4/igt@runner@aborted.html
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl4/igt@runner@aborted.html
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl7/igt@runner@aborted.html
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl4/igt@runner@aborted.html
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl7/igt@runner@aborted.html
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl7/igt@runner@aborted.html
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl4/igt@runner@aborted.html
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl7/igt@runner@aborted.html
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl4/igt@runner@aborted.html
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl4/igt@runner@aborted.html
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl7/igt@runner@aborted.html
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl7/igt@runner@aborted.html
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/shard-kbl3/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110254]: https://bugs.freedesktop.org/show_bug.cgi?id=110254
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3464]: https://gitlab.freedesktop.org/drm/intel/issues/3464
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3690]: https://gitlab.freedesktop.org/drm/intel/issues/3690
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3828]: https://gitlab.freedesktop.org/drm/intel/issues/3828
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4272]: https://gitlab.freedesktop.org/drm/intel/issues/4272
[i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4444]: https://gitlab.freedesktop.org/drm/intel/issues/4444
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4807]: https://gitlab.freedesktop.org/drm/intel/issues/4807
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
[i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
[i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#4886]: https://gitlab.freedesktop.org/drm/intel/issues/4886
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4929]: https://gitlab.freedesktop.org/drm/intel/issues/4929
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5032]: https://gitlab.freedesktop.org/drm/intel/issues/5032
[i915#5076]: https://gitlab.freedesktop.org/drm/intel/issues/5076
[i915#5080]: https://gitlab.freedesktop.org/drm/intel/issues/5080
[i915#5096]: https://gitlab.freedesktop.org/drm/intel/issues/5096
[i915#5098]: https://gitlab.freedesktop.org/drm/intel/issues/5098
[i915#5174]: https://gitlab.freedesktop.org/drm/intel/issues/5174
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5264]: https://gitlab.freedesktop.org/drm/intel/issues/5264
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
[i915#5614]: https://gitlab.freedesktop.org/drm/intel/issues/5614
[i915#5691]: https://gitlab.freedesktop.org/drm/intel/issues/5691
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_11662 -> Patchwork_103244v3
CI-20190529: 20190529
CI_DRM_11662: 38bc558d7aba4f111c5cf767bfdd89c722ba0415 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6474: f4731438344390afe165ac41ee9e2a2e77e3d932 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103244v3: 38bc558d7aba4f111c5cf767bfdd89c722ba0415 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v3/index.html
[-- Attachment #2: Type: text/html, Size: 65982 bytes --]
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi
2022-05-17 3:20 ` [Intel-gfx] " Matt Roper
@ 2022-05-17 15:15 ` Matt Roper
-1 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2022-05-17 15:15 UTC (permalink / raw)
To: intel-gfx; +Cc: tvrtko.ursulin, dri-devel
As with EU masks, it's easier to store subslice/DSS masks internally in
a format that's more natural for the driver to work with, and then only
covert into the u8[] uapi form when the query ioctl is invoked. Since
the hardware design changed significantly with Xe_HP, we'll use a union
to choose between the old "hsw-style" subslice masks or the newer xehp
mask. HSW-style masks will be stored in an array of u8's, indexed by
slice (there's never more than 6 subslices per slice on older
platforms). For Xe_HP and beyond where slices no longer exist, we only
need a single bitmask. However we already know that this mask is
eventually going to grow too large for a simple u64 to hold, so we'll
represent it in a manner that can be operated on by the utilities in
linux/bitmap.h.
v3:
- Fix typo: BIT(s) -> BIT(ss) in gen9_sseu_device_status()
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 12 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 246 +++++++++++--------
drivers/gpu/drm/i915/gt/intel_sseu.h | 78 +++---
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +--
drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +-
drivers/gpu/drm/i915/i915_getparam.c | 3 +-
drivers/gpu/drm/i915/i915_query.c | 8 +-
9 files changed, 226 insertions(+), 184 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index ab4c5ab28e4d..a3bb73f5d53b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1875,6 +1875,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
{
const struct sseu_dev_info *device = >->info.sseu;
struct drm_i915_private *i915 = gt->i915;
+ unsigned int dev_subslice_mask = intel_sseu_get_hsw_subslices(device, 0);
/* No zeros in any field. */
if (!user->slice_mask || !user->subslice_mask ||
@@ -1901,7 +1902,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
if (user->slice_mask & ~device->slice_mask)
return -EINVAL;
- if (user->subslice_mask & ~device->subslice_mask[0])
+ if (user->subslice_mask & ~dev_subslice_mask)
return -EINVAL;
if (user->max_eus_per_subslice > device->max_eus_per_subslice)
@@ -1915,7 +1916,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
/* Part specific restrictions. */
if (GRAPHICS_VER(i915) == 11) {
unsigned int hw_s = hweight8(device->slice_mask);
- unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
+ unsigned int hw_ss_per_s = hweight8(dev_subslice_mask);
unsigned int req_s = hweight8(context->slice_mask);
unsigned int req_ss = hweight8(context->subslice_mask);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 1adbf34c3632..f0acf8518a51 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -674,8 +674,8 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
return;
- ccs_mask = intel_slicemask_from_dssmask(intel_sseu_get_compute_subslices(&info->sseu),
- ss_per_ccs);
+ ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
+ ss_per_ccs);
/*
* If all DSS in a quadrant are fused off, the corresponding CCS
* engine is not available for use.
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 034182f85501..2921f510642f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -133,13 +133,6 @@ static const struct intel_mmio_range dg2_lncf_steering_table[] = {
{},
};
-static u16 slicemask(struct intel_gt *gt, int count)
-{
- u64 dss_mask = intel_sseu_get_subslices(>->info.sseu, 0);
-
- return intel_slicemask_from_dssmask(dss_mask, count);
-}
-
int intel_gt_init_mmio(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
@@ -155,9 +148,12 @@ int intel_gt_init_mmio(struct intel_gt *gt)
*/
if (HAS_MSLICES(i915)) {
gt->info.mslice_mask =
- slicemask(gt, GEN_DSS_PER_MSLICE) |
+ intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
+ GEN_DSS_PER_MSLICE);
+ gt->info.mslice_mask |=
(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
GEN12_MEML3_EN_MASK);
+
if (!gt->info.mslice_mask) /* should be impossible! */
drm_warn(&i915->drm, "mslice mask all zero!\n");
}
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index d89e2e0f05e5..e1bce8a9044e 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -28,54 +28,23 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
{
unsigned int i, total = 0;
- for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
- total += hweight8(sseu->subslice_mask[i]);
+ if (sseu->has_xehp_dss)
+ return bitmap_weight(sseu->subslice_mask.xehp,
+ I915_MAX_SS_FUSE_BITS);
- return total;
-}
-
-static u32
-sseu_get_subslices(const struct sseu_dev_info *sseu,
- const u8 *subslice_mask, u8 slice)
-{
- int i, offset = slice * sseu->ss_stride;
- u32 mask = 0;
-
- GEM_BUG_ON(slice >= sseu->max_slices);
-
- for (i = 0; i < sseu->ss_stride; i++)
- mask |= (u32)subslice_mask[offset + i] << i * BITS_PER_BYTE;
-
- return mask;
-}
-
-u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
-{
- return sseu_get_subslices(sseu, sseu->subslice_mask, slice);
-}
+ for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++)
+ total += hweight8(sseu->subslice_mask.hsw[i]);
-static u32 sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
-{
- return sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
-}
-
-u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu)
-{
- return sseu_get_subslices(sseu, sseu->compute_subslice_mask, 0);
-}
-
-void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
- u8 *subslice_mask, u32 ss_mask)
-{
- int offset = slice * sseu->ss_stride;
-
- memcpy(&subslice_mask[offset], &ss_mask, sseu->ss_stride);
+ return total;
}
unsigned int
-intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
+intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice)
{
- return hweight32(intel_sseu_get_subslices(sseu, slice));
+ WARN_ON(sseu->has_xehp_dss);
+ WARN_ON(slice >= sseu->max_slices);
+
+ return sseu->subslice_mask.hsw[slice];
}
static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
@@ -148,32 +117,65 @@ int intel_sseu_copy_eumask_to_user(void __user *to,
return copy_to_user(to, eu_mask, len);
}
+/**
+ * intel_sseu_copy_ssmask_to_user - Copy subslice mask into a userspace buffer
+ * @to: Pointer to userspace buffer to copy to
+ * @sseu: SSEU structure containing subslice mask to copy
+ *
+ * Copies the subslice mask to a userspace buffer in the format expected by
+ * the query ioctl's topology queries.
+ *
+ * Returns the result of the copy_to_user() operation.
+ */
+int intel_sseu_copy_ssmask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu)
+{
+ u8 ss_mask[GEN_SS_MASK_SIZE] = {};
+ int len = sseu->max_slices * sseu->ss_stride;
+ int s, ss, i;
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ for (ss = 0; ss < sseu->max_subslices; ss++) {
+ i = s * sseu->ss_stride * BITS_PER_BYTE + ss;
+
+ if (!intel_sseu_has_subslice(sseu, s, ss))
+ continue;
+
+ ss_mask[i / BITS_PER_BYTE] |= BIT(i % BITS_PER_BYTE);
+ }
+ }
+
+ return copy_to_user(to, ss_mask, len);
+}
+
static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
- u32 g_ss_en, u32 c_ss_en, u16 eu_en)
+ u32 ss_en, u16 eu_en)
{
u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
int ss;
- /* g_ss_en/c_ss_en represent entire subslice mask across all slices */
- GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
- sizeof(g_ss_en) * BITS_PER_BYTE);
+ sseu->slice_mask |= BIT(0);
+ sseu->subslice_mask.hsw[0] = ss_en & valid_ss_mask;
+
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (intel_sseu_has_subslice(sseu, 0, ss))
+ sseu_set_eus(sseu, 0, ss, eu_en);
+
+ sseu->eu_per_subslice = hweight16(eu_en);
+ sseu->eu_total = compute_eu_total(sseu);
+}
+
+static void xehp_compute_sseu_info(struct sseu_dev_info *sseu,
+ u16 eu_en)
+{
+ int ss;
sseu->slice_mask |= BIT(0);
- /*
- * XeHP introduces the concept of compute vs geometry DSS. To reduce
- * variation between GENs around subslice usage, store a mask for both
- * the geometry and compute enabled masks since userspace will need to
- * be able to query these masks independently. Also compute a total
- * enabled subslice count for the purposes of selecting subslices to
- * use in a particular GEM context.
- */
- intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
- c_ss_en & valid_ss_mask);
- intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
- g_ss_en & valid_ss_mask);
- intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
- (g_ss_en | c_ss_en) & valid_ss_mask);
+ bitmap_or(sseu->subslice_mask.xehp,
+ sseu->compute_subslice_mask.xehp,
+ sseu->geometry_subslice_mask.xehp,
+ I915_MAX_SS_FUSE_BITS);
for (ss = 0; ss < sseu->max_subslices; ss++)
if (intel_sseu_has_subslice(sseu, 0, ss))
@@ -183,11 +185,31 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
sseu->eu_total = compute_eu_total(sseu);
}
+static void
+xehp_load_dss_mask(struct intel_uncore *uncore,
+ intel_sseu_ss_mask_t *ssmask,
+ int numregs,
+ ...)
+{
+ va_list argp;
+ u32 fuse_val[I915_MAX_SS_FUSE_REGS] = {};
+ int i;
+
+ if (WARN_ON(numregs > I915_MAX_SS_FUSE_REGS))
+ numregs = I915_MAX_SS_FUSE_REGS;
+
+ va_start(argp, numregs);
+ for (i = 0; i < numregs; i++)
+ fuse_val[i] = intel_uncore_read(uncore, va_arg(argp, i915_reg_t));
+ va_end(argp);
+
+ bitmap_from_arr32(ssmask->xehp, fuse_val, numregs * 32);
+}
+
static void xehp_sseu_info_init(struct intel_gt *gt)
{
struct sseu_dev_info *sseu = >->info.sseu;
struct intel_uncore *uncore = gt->uncore;
- u32 g_dss_en, c_dss_en = 0;
u16 eu_en = 0;
u8 eu_en_fuse;
int eu;
@@ -201,8 +223,10 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
intel_sseu_set_info(sseu, 1, 32, 16);
sseu->has_xehp_dss = 1;
- g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
- c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
+ xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 1,
+ GEN12_GT_GEOMETRY_DSS_ENABLE);
+ xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 1,
+ GEN12_GT_COMPUTE_DSS_ENABLE);
eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
@@ -210,7 +234,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
+ xehp_compute_sseu_info(sseu, eu_en);
}
static void gen12_sseu_info_init(struct intel_gt *gt)
@@ -250,7 +274,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, g_dss_en, eu_en);
/* TGL only supports slice-level power gating */
sseu->has_slice_pg = 1;
@@ -284,7 +308,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
GEN11_EU_DIS_MASK);
- gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, ss_en, eu_en);
/* ICL has no power gating restrictions. */
sseu->has_slice_pg = 1;
@@ -296,7 +320,6 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
{
struct sseu_dev_info *sseu = >->info.sseu;
u32 fuse;
- u8 subslice_mask = 0;
fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT);
@@ -310,7 +333,7 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
- subslice_mask |= BIT(0);
+ sseu->subslice_mask.hsw[0] |= BIT(0);
sseu_set_eus(sseu, 0, 0, ~disabled_mask);
}
@@ -321,12 +344,10 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
(((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
- subslice_mask |= BIT(1);
+ sseu->subslice_mask.hsw[0] |= BIT(1);
sseu_set_eus(sseu, 0, 1, ~disabled_mask);
}
- intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask, subslice_mask);
-
sseu->eu_total = compute_eu_total(sseu);
/*
@@ -381,8 +402,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
/* skip disabled slice */
continue;
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
for (ss = 0; ss < sseu->max_subslices; ss++) {
@@ -439,8 +459,8 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
sseu->has_eu_pg = sseu->eu_per_subslice > 2;
if (IS_GEN9_LP(i915)) {
-#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
- info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
+#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask.hsw[0] & BIT(ss)))
+ info->has_pooled_eu = hweight8(sseu->subslice_mask.hsw[0]) == 3;
sseu->min_eu_in_pool = 0;
if (info->has_pooled_eu) {
@@ -494,8 +514,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
/* skip disabled slice */
continue;
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
for (ss = 0; ss < sseu->max_subslices; ss++) {
u8 eu_disabled_mask;
@@ -592,8 +611,7 @@ static void hsw_sseu_info_init(struct intel_gt *gt)
sseu->eu_per_subslice);
for (s = 0; s < sseu->max_slices; s++) {
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
for (ss = 0; ss < sseu->max_subslices; ss++) {
sseu_set_eus(sseu, s, ss,
@@ -682,7 +700,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
*/
if (GRAPHICS_VER(i915) == 11 &&
slices == 1 &&
- subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
+ subslices > min_t(u8, 4, hweight8(sseu->subslice_mask.hsw[0]) / 2)) {
GEM_BUG_ON(subslices & 1);
subslice_pg = false;
@@ -748,14 +766,25 @@ void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
{
int s;
- drm_printf(p, "slice total: %u, mask=%04x\n",
- hweight8(sseu->slice_mask), sseu->slice_mask);
- drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
- for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
- s, intel_sseu_subslices_per_slice(sseu, s),
- intel_sseu_get_subslices(sseu, s));
+ if (sseu->has_xehp_dss) {
+ drm_printf(p, "subslice total: %u\n",
+ intel_sseu_subslice_total(sseu));
+ drm_printf(p, "subslice mask=%*pb\n", I915_MAX_SS_FUSE_BITS,
+ sseu->subslice_mask.xehp);
+ } else {
+ drm_printf(p, "slice total: %u, mask=%04x\n",
+ hweight8(sseu->slice_mask), sseu->slice_mask);
+ drm_printf(p, "subslice total: %u\n",
+ intel_sseu_subslice_total(sseu));
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ u8 ss_mask = sseu->subslice_mask.hsw[s];
+
+ drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
+ s, hweight8(ss_mask), ss_mask);
+ }
}
+
drm_printf(p, "EU total: %u\n", sseu->eu_total);
drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
drm_printf(p, "has slice power gating: %s\n",
@@ -772,9 +801,10 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
int s, ss;
for (s = 0; s < sseu->max_slices; s++) {
+ u8 ss_mask = sseu->subslice_mask.hsw[s];
+
drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
- s, intel_sseu_subslices_per_slice(sseu, s),
- intel_sseu_get_subslices(sseu, s));
+ s, hweight8(ss_mask), ss_mask);
for (ss = 0; ss < sseu->max_subslices; ss++) {
u16 enabled_eus = sseu_get_eus(sseu, s, ss);
@@ -788,16 +818,14 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
static void sseu_print_xehp_topology(const struct sseu_dev_info *sseu,
struct drm_printer *p)
{
- u32 g_dss_mask = sseu_get_geometry_subslices(sseu);
- u32 c_dss_mask = intel_sseu_get_compute_subslices(sseu);
int dss;
for (dss = 0; dss < sseu->max_subslices; dss++) {
u16 enabled_eus = sseu_get_eus(sseu, 0, dss);
drm_printf(p, "DSS_%02d: G:%3s C:%3s, %2u EUs (0x%04hx)\n", dss,
- str_yes_no(g_dss_mask & BIT(dss)),
- str_yes_no(c_dss_mask & BIT(dss)),
+ str_yes_no(test_bit(dss, sseu->geometry_subslice_mask.xehp)),
+ str_yes_no(test_bit(dss, sseu->compute_subslice_mask.xehp)),
hweight16(enabled_eus), enabled_eus);
}
}
@@ -815,20 +843,40 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
}
}
-u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice)
+void intel_sseu_print_ss_info(const char* type,
+ const struct sseu_dev_info *sseu,
+ struct seq_file *m)
+{
+ int s;
+
+ if (sseu->has_xehp_dss)
+ seq_printf(m, " %s Subslices: %u\n", type,
+ bitmap_weight(sseu->subslice_mask.xehp,
+ I915_MAX_SS_FUSE_BITS));
+ else
+ for (s = 0; s < fls(sseu->slice_mask); s++)
+ seq_printf(m, " %s Slice%i subslices: %u\n", type,
+ s, hweight8(sseu->subslice_mask.hsw[s]));
+}
+
+u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask,
+ int dss_per_slice)
{
+ intel_sseu_ss_mask_t per_slice_mask = {};
u16 slice_mask = 0;
int i;
- WARN_ON(sizeof(dss_mask) * 8 / dss_per_slice > 8 * sizeof(slice_mask));
+ WARN_ON(DIV_ROUND_UP(I915_MAX_SS_FUSE_BITS, dss_per_slice) >
+ 8 * sizeof(slice_mask));
- for (i = 0; dss_mask; i++) {
- if (dss_mask & GENMASK(dss_per_slice - 1, 0))
+ bitmap_fill(per_slice_mask.xehp, dss_per_slice);
+ for (i = 0; !bitmap_empty(dss_mask.xehp, I915_MAX_SS_FUSE_BITS); i++) {
+ if (bitmap_intersects(dss_mask.xehp, per_slice_mask.xehp, dss_per_slice))
slice_mask |= BIT(i);
- dss_mask >>= dss_per_slice;
+ bitmap_shift_right(dss_mask.xehp, dss_mask.xehp, dss_per_slice,
+ I915_MAX_SS_FUSE_BITS);
}
return slice_mask;
}
-
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 43a8f8f98687..7fbb9276a1c2 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -25,12 +25,16 @@ struct drm_printer;
/*
* Maximum number of subslices that can exist within a HSW-style slice. This
* is only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the
- * GEN_MAX_DSS value below).
+ * I915_MAX_SS_FUSE_BITS value below).
*/
#define GEN_MAX_SS_PER_HSW_SLICE 6
-/* Maximum number of DSS on newer platforms (Xe_HP and beyond). */
-#define GEN_MAX_DSS 32
+/*
+ * Maximum number of 32-bit registers used by hardware to express the
+ * enabled/disabled subslices.
+ */
+#define I915_MAX_SS_FUSE_REGS 1
+#define I915_MAX_SS_FUSE_BITS (I915_MAX_SS_FUSE_REGS * 32)
/* Maximum number of EUs that can exist within a subslice or DSS. */
#define GEN_MAX_EUS_PER_SS 16
@@ -38,7 +42,7 @@ struct drm_printer;
#define SSEU_MAX(a, b) ((a) > (b) ? (a) : (b))
/* The maximum number of bits needed to express each subslice/DSS independently */
-#define GEN_SS_MASK_SIZE SSEU_MAX(GEN_MAX_DSS, \
+#define GEN_SS_MASK_SIZE SSEU_MAX(I915_MAX_SS_FUSE_BITS, \
GEN_MAX_HSW_SLICES * GEN_MAX_SS_PER_HSW_SLICE)
#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
@@ -49,17 +53,24 @@ struct drm_printer;
#define GEN_DSS_PER_CSLICE 8
#define GEN_DSS_PER_MSLICE 8
-#define GEN_MAX_GSLICES (GEN_MAX_DSS / GEN_DSS_PER_GSLICE)
-#define GEN_MAX_CSLICES (GEN_MAX_DSS / GEN_DSS_PER_CSLICE)
+#define GEN_MAX_GSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_GSLICE)
+#define GEN_MAX_CSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_CSLICE)
+
+typedef union {
+ u8 hsw[GEN_MAX_HSW_SLICES];
+
+ /* Bitmap compatible with linux/bitmap.h; may exceed size of u64 */
+ unsigned long xehp[BITS_TO_LONGS(I915_MAX_SS_FUSE_BITS)];
+} intel_sseu_ss_mask_t;
struct sseu_dev_info {
u8 slice_mask;
- u8 subslice_mask[GEN_SS_MASK_SIZE];
- u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
- u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
+ intel_sseu_ss_mask_t subslice_mask;
+ intel_sseu_ss_mask_t geometry_subslice_mask;
+ intel_sseu_ss_mask_t compute_subslice_mask;
union {
u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
- u16 xehp[GEN_MAX_DSS];
+ u16 xehp[I915_MAX_SS_FUSE_BITS];
} eu_mask;
u16 eu_total;
@@ -100,7 +111,7 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
{
struct intel_sseu value = {
.slice_mask = sseu->slice_mask,
- .subslice_mask = sseu->subslice_mask[0],
+ .subslice_mask = sseu->subslice_mask.hsw[0],
.min_eus_per_subslice = sseu->max_eus_per_subslice,
.max_eus_per_subslice = sseu->max_eus_per_subslice,
};
@@ -112,18 +123,23 @@ static inline bool
intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
int subslice)
{
- u8 mask;
- int ss_idx = subslice / BITS_PER_BYTE;
-
- if (slice >= sseu->max_slices ||
- subslice >= sseu->max_subslices)
- return false;
-
- GEM_BUG_ON(ss_idx >= sseu->ss_stride);
-
- mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx];
+ if (sseu->has_xehp_dss)
+ return test_bit(subslice, sseu->subslice_mask.xehp);
+ else
+ return sseu->subslice_mask.hsw[slice] & BIT(subslice);
+}
- return mask & BIT(subslice % BITS_PER_BYTE);
+/*
+ * Used to obtain the index of the first DSS. Can start searching from the
+ * beginning of a specific dss group (e.g., gslice, cslice, etc.) if
+ * groupsize and groupnum are non-zero.
+ */
+static inline unsigned int
+intel_sseu_find_first_xehp_dss(const struct sseu_dev_info *sseu, int groupsize,
+ int groupnum)
+{
+ return find_next_bit(sseu->subslice_mask.xehp, I915_MAX_SS_FUSE_BITS,
+ groupnum * groupsize);
}
void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
@@ -133,14 +149,10 @@ unsigned int
intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
unsigned int
-intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
-
-u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
+intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice);
-u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
-
-void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
- u8 *subslice_mask, u32 ss_mask);
+intel_sseu_ss_mask_t
+intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
void intel_sseu_info_init(struct intel_gt *gt);
@@ -152,9 +164,15 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
const struct sseu_dev_info *sseu,
struct drm_printer *p);
-u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
+u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask, int dss_per_slice);
int intel_sseu_copy_eumask_to_user(void __user *to,
const struct sseu_dev_info *sseu);
+int intel_sseu_copy_ssmask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu);
+
+void intel_sseu_print_ss_info(const char* type,
+ const struct sseu_dev_info *sseu,
+ struct seq_file *m);
#endif /* __INTEL_SSEU_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
index 2d5d011e01db..c2ee5e1826b5 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
@@ -4,6 +4,7 @@
* Copyright © 2020 Intel Corporation
*/
+#include <linux/bitmap.h>
#include <linux/string_helpers.h>
#include "i915_drv.h"
@@ -11,14 +12,6 @@
#include "intel_gt_regs.h"
#include "intel_sseu_debugfs.h"
-static void sseu_copy_subslices(const struct sseu_dev_info *sseu,
- int slice, u8 *to_mask)
-{
- int offset = slice * sseu->ss_stride;
-
- memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
-}
-
static void cherryview_sseu_device_status(struct intel_gt *gt,
struct sseu_dev_info *sseu)
{
@@ -41,7 +34,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt,
continue;
sseu->slice_mask = BIT(0);
- sseu->subslice_mask[0] |= BIT(ss);
+ sseu->subslice_mask.hsw[0] |= BIT(ss);
eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
@@ -92,7 +85,7 @@ static void gen11_sseu_device_status(struct intel_gt *gt,
continue;
sseu->slice_mask |= BIT(s);
- sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -147,21 +140,17 @@ static void gen9_sseu_device_status(struct intel_gt *gt,
sseu->slice_mask |= BIT(s);
if (IS_GEN9_BC(gt->i915))
- sseu_copy_subslices(&info->sseu, s,
- sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
- u8 ss_idx = s * info->sseu.ss_stride +
- ss / BITS_PER_BYTE;
if (IS_GEN9_LP(gt->i915)) {
if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
/* skip disabled subslice */
continue;
- sseu->subslice_mask[ss_idx] |=
- BIT(ss % BITS_PER_BYTE);
+ sseu->subslice_mask.hsw[s] |= BIT(ss);
}
eu_cnt = eu_reg[2 * s + ss / 2] & eu_mask[ss % 2];
@@ -188,8 +177,7 @@ static void bdw_sseu_device_status(struct intel_gt *gt,
if (sseu->slice_mask) {
sseu->eu_per_subslice = info->sseu.eu_per_subslice;
for (s = 0; s < fls(sseu->slice_mask); s++)
- sseu_copy_subslices(&info->sseu, s,
- sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
sseu->eu_total = sseu->eu_per_subslice *
intel_sseu_subslice_total(sseu);
@@ -208,7 +196,6 @@ static void i915_print_sseu_info(struct seq_file *m,
const struct sseu_dev_info *sseu)
{
const char *type = is_available_info ? "Available" : "Enabled";
- int s;
seq_printf(m, " %s Slice Mask: %04x\n", type,
sseu->slice_mask);
@@ -216,10 +203,7 @@ static void i915_print_sseu_info(struct seq_file *m,
hweight8(sseu->slice_mask));
seq_printf(m, " %s Subslice Total: %u\n", type,
intel_sseu_subslice_total(sseu));
- for (s = 0; s < fls(sseu->slice_mask); s++) {
- seq_printf(m, " %s Slice%i subslices: %u\n", type,
- s, intel_sseu_subslices_per_slice(sseu, s));
- }
+ intel_sseu_print_ss_info(type, sseu, m);
seq_printf(m, " %s EU Total: %u\n", type,
sseu->eu_total);
seq_printf(m, " %s EU Per Subslice: %u\n", type,
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 756807c4b405..fc6274708f8e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -948,8 +948,8 @@ gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
* on s/ss combo, the read should be done with read_subslice_reg.
*/
slice = ffs(sseu->slice_mask) - 1;
- GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
- subslice = ffs(intel_sseu_get_subslices(sseu, slice));
+ GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw));
+ subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice));
GEM_BUG_ON(!subslice);
subslice--;
@@ -1087,11 +1087,10 @@ static void
icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
{
const struct sseu_dev_info *sseu = >->info.sseu;
- unsigned int slice, subslice;
+ unsigned int subslice;
GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
- slice = 0;
/*
* Although a platform may have subslices, we need to always steer
@@ -1102,7 +1101,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
* one of the higher subslices, we run the risk of reading back 0's or
* random garbage.
*/
- subslice = __ffs(intel_sseu_get_subslices(sseu, slice));
+ subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0));
/*
* If the subslice we picked above also steers us to a valid L3 bank,
@@ -1112,7 +1111,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
if (gt->info.l3bank_mask & BIT(subslice))
gt->steering_table[L3BANK] = NULL;
- __add_mcr_wa(gt, wal, slice, subslice);
+ __add_mcr_wa(gt, wal, 0, subslice);
}
static void
@@ -1120,7 +1119,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
{
const struct sseu_dev_info *sseu = >->info.sseu;
unsigned long slice, subslice = 0, slice_mask = 0;
- u64 dss_mask = 0;
u32 lncf_mask = 0;
int i;
@@ -1151,8 +1149,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
*/
/* Find the potential gslice candidates */
- dss_mask = intel_sseu_get_subslices(sseu, 0);
- slice_mask = intel_slicemask_from_dssmask(dss_mask, GEN_DSS_PER_GSLICE);
+ slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask,
+ GEN_DSS_PER_GSLICE);
/*
* Find the potential LNCF candidates. Either LNCF within a valid
@@ -1177,9 +1175,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
}
slice = __ffs(slice_mask);
- subslice = __ffs(dss_mask >> (slice * GEN_DSS_PER_GSLICE));
+ subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice);
WARN_ON(subslice > GEN_DSS_PER_GSLICE);
- WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0);
__add_mcr_wa(gt, wal, slice, subslice);
@@ -2030,9 +2027,8 @@ engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
static bool needs_wa_1308578152(struct intel_engine_cs *engine)
{
- u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0);
-
- return (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0;
+ return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >
+ GEN_DSS_PER_GSLICE;
}
static void
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index ac9767c56619..6fd15b39570c 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -162,8 +162,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
return -EINVAL;
/* Only copy bits from the first slice */
- memcpy(&value, sseu->subslice_mask,
- min(sseu->ss_stride, (u8)sizeof(value)));
+ value = intel_sseu_get_hsw_subslices(sseu, 0);
if (!value)
return -ENODEV;
break;
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 16f43bf32a05..9afa6d1eaf95 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -31,7 +31,7 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
static int fill_topology_info(const struct sseu_dev_info *sseu,
struct drm_i915_query_item *query_item,
- const u8 *subslice_mask)
+ intel_sseu_ss_mask_t subslice_mask)
{
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
@@ -71,9 +71,9 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
&sseu->slice_mask, slice_length))
return -EFAULT;
- if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
- sizeof(topo) + slice_length),
- subslice_mask, subslice_length))
+ if (intel_sseu_copy_ssmask_to_user(u64_to_user_ptr(query_item->data_ptr +
+ sizeof(topo) + slice_length),
+ sseu))
return -EFAULT;
if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
--
2.35.3
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [Intel-gfx] [PATCH v3 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi
@ 2022-05-17 15:15 ` Matt Roper
0 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2022-05-17 15:15 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
As with EU masks, it's easier to store subslice/DSS masks internally in
a format that's more natural for the driver to work with, and then only
covert into the u8[] uapi form when the query ioctl is invoked. Since
the hardware design changed significantly with Xe_HP, we'll use a union
to choose between the old "hsw-style" subslice masks or the newer xehp
mask. HSW-style masks will be stored in an array of u8's, indexed by
slice (there's never more than 6 subslices per slice on older
platforms). For Xe_HP and beyond where slices no longer exist, we only
need a single bitmask. However we already know that this mask is
eventually going to grow too large for a simple u64 to hold, so we'll
represent it in a manner that can be operated on by the utilities in
linux/bitmap.h.
v3:
- Fix typo: BIT(s) -> BIT(ss) in gen9_sseu_device_status()
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 12 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 246 +++++++++++--------
drivers/gpu/drm/i915/gt/intel_sseu.h | 78 +++---
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +--
drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +-
drivers/gpu/drm/i915/i915_getparam.c | 3 +-
drivers/gpu/drm/i915/i915_query.c | 8 +-
9 files changed, 226 insertions(+), 184 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index ab4c5ab28e4d..a3bb73f5d53b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1875,6 +1875,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
{
const struct sseu_dev_info *device = >->info.sseu;
struct drm_i915_private *i915 = gt->i915;
+ unsigned int dev_subslice_mask = intel_sseu_get_hsw_subslices(device, 0);
/* No zeros in any field. */
if (!user->slice_mask || !user->subslice_mask ||
@@ -1901,7 +1902,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
if (user->slice_mask & ~device->slice_mask)
return -EINVAL;
- if (user->subslice_mask & ~device->subslice_mask[0])
+ if (user->subslice_mask & ~dev_subslice_mask)
return -EINVAL;
if (user->max_eus_per_subslice > device->max_eus_per_subslice)
@@ -1915,7 +1916,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
/* Part specific restrictions. */
if (GRAPHICS_VER(i915) == 11) {
unsigned int hw_s = hweight8(device->slice_mask);
- unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
+ unsigned int hw_ss_per_s = hweight8(dev_subslice_mask);
unsigned int req_s = hweight8(context->slice_mask);
unsigned int req_ss = hweight8(context->subslice_mask);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 1adbf34c3632..f0acf8518a51 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -674,8 +674,8 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
return;
- ccs_mask = intel_slicemask_from_dssmask(intel_sseu_get_compute_subslices(&info->sseu),
- ss_per_ccs);
+ ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
+ ss_per_ccs);
/*
* If all DSS in a quadrant are fused off, the corresponding CCS
* engine is not available for use.
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 034182f85501..2921f510642f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -133,13 +133,6 @@ static const struct intel_mmio_range dg2_lncf_steering_table[] = {
{},
};
-static u16 slicemask(struct intel_gt *gt, int count)
-{
- u64 dss_mask = intel_sseu_get_subslices(>->info.sseu, 0);
-
- return intel_slicemask_from_dssmask(dss_mask, count);
-}
-
int intel_gt_init_mmio(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
@@ -155,9 +148,12 @@ int intel_gt_init_mmio(struct intel_gt *gt)
*/
if (HAS_MSLICES(i915)) {
gt->info.mslice_mask =
- slicemask(gt, GEN_DSS_PER_MSLICE) |
+ intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
+ GEN_DSS_PER_MSLICE);
+ gt->info.mslice_mask |=
(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
GEN12_MEML3_EN_MASK);
+
if (!gt->info.mslice_mask) /* should be impossible! */
drm_warn(&i915->drm, "mslice mask all zero!\n");
}
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index d89e2e0f05e5..e1bce8a9044e 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -28,54 +28,23 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
{
unsigned int i, total = 0;
- for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
- total += hweight8(sseu->subslice_mask[i]);
+ if (sseu->has_xehp_dss)
+ return bitmap_weight(sseu->subslice_mask.xehp,
+ I915_MAX_SS_FUSE_BITS);
- return total;
-}
-
-static u32
-sseu_get_subslices(const struct sseu_dev_info *sseu,
- const u8 *subslice_mask, u8 slice)
-{
- int i, offset = slice * sseu->ss_stride;
- u32 mask = 0;
-
- GEM_BUG_ON(slice >= sseu->max_slices);
-
- for (i = 0; i < sseu->ss_stride; i++)
- mask |= (u32)subslice_mask[offset + i] << i * BITS_PER_BYTE;
-
- return mask;
-}
-
-u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
-{
- return sseu_get_subslices(sseu, sseu->subslice_mask, slice);
-}
+ for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++)
+ total += hweight8(sseu->subslice_mask.hsw[i]);
-static u32 sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
-{
- return sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
-}
-
-u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu)
-{
- return sseu_get_subslices(sseu, sseu->compute_subslice_mask, 0);
-}
-
-void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
- u8 *subslice_mask, u32 ss_mask)
-{
- int offset = slice * sseu->ss_stride;
-
- memcpy(&subslice_mask[offset], &ss_mask, sseu->ss_stride);
+ return total;
}
unsigned int
-intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
+intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice)
{
- return hweight32(intel_sseu_get_subslices(sseu, slice));
+ WARN_ON(sseu->has_xehp_dss);
+ WARN_ON(slice >= sseu->max_slices);
+
+ return sseu->subslice_mask.hsw[slice];
}
static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
@@ -148,32 +117,65 @@ int intel_sseu_copy_eumask_to_user(void __user *to,
return copy_to_user(to, eu_mask, len);
}
+/**
+ * intel_sseu_copy_ssmask_to_user - Copy subslice mask into a userspace buffer
+ * @to: Pointer to userspace buffer to copy to
+ * @sseu: SSEU structure containing subslice mask to copy
+ *
+ * Copies the subslice mask to a userspace buffer in the format expected by
+ * the query ioctl's topology queries.
+ *
+ * Returns the result of the copy_to_user() operation.
+ */
+int intel_sseu_copy_ssmask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu)
+{
+ u8 ss_mask[GEN_SS_MASK_SIZE] = {};
+ int len = sseu->max_slices * sseu->ss_stride;
+ int s, ss, i;
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ for (ss = 0; ss < sseu->max_subslices; ss++) {
+ i = s * sseu->ss_stride * BITS_PER_BYTE + ss;
+
+ if (!intel_sseu_has_subslice(sseu, s, ss))
+ continue;
+
+ ss_mask[i / BITS_PER_BYTE] |= BIT(i % BITS_PER_BYTE);
+ }
+ }
+
+ return copy_to_user(to, ss_mask, len);
+}
+
static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
- u32 g_ss_en, u32 c_ss_en, u16 eu_en)
+ u32 ss_en, u16 eu_en)
{
u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
int ss;
- /* g_ss_en/c_ss_en represent entire subslice mask across all slices */
- GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
- sizeof(g_ss_en) * BITS_PER_BYTE);
+ sseu->slice_mask |= BIT(0);
+ sseu->subslice_mask.hsw[0] = ss_en & valid_ss_mask;
+
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (intel_sseu_has_subslice(sseu, 0, ss))
+ sseu_set_eus(sseu, 0, ss, eu_en);
+
+ sseu->eu_per_subslice = hweight16(eu_en);
+ sseu->eu_total = compute_eu_total(sseu);
+}
+
+static void xehp_compute_sseu_info(struct sseu_dev_info *sseu,
+ u16 eu_en)
+{
+ int ss;
sseu->slice_mask |= BIT(0);
- /*
- * XeHP introduces the concept of compute vs geometry DSS. To reduce
- * variation between GENs around subslice usage, store a mask for both
- * the geometry and compute enabled masks since userspace will need to
- * be able to query these masks independently. Also compute a total
- * enabled subslice count for the purposes of selecting subslices to
- * use in a particular GEM context.
- */
- intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
- c_ss_en & valid_ss_mask);
- intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
- g_ss_en & valid_ss_mask);
- intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
- (g_ss_en | c_ss_en) & valid_ss_mask);
+ bitmap_or(sseu->subslice_mask.xehp,
+ sseu->compute_subslice_mask.xehp,
+ sseu->geometry_subslice_mask.xehp,
+ I915_MAX_SS_FUSE_BITS);
for (ss = 0; ss < sseu->max_subslices; ss++)
if (intel_sseu_has_subslice(sseu, 0, ss))
@@ -183,11 +185,31 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
sseu->eu_total = compute_eu_total(sseu);
}
+static void
+xehp_load_dss_mask(struct intel_uncore *uncore,
+ intel_sseu_ss_mask_t *ssmask,
+ int numregs,
+ ...)
+{
+ va_list argp;
+ u32 fuse_val[I915_MAX_SS_FUSE_REGS] = {};
+ int i;
+
+ if (WARN_ON(numregs > I915_MAX_SS_FUSE_REGS))
+ numregs = I915_MAX_SS_FUSE_REGS;
+
+ va_start(argp, numregs);
+ for (i = 0; i < numregs; i++)
+ fuse_val[i] = intel_uncore_read(uncore, va_arg(argp, i915_reg_t));
+ va_end(argp);
+
+ bitmap_from_arr32(ssmask->xehp, fuse_val, numregs * 32);
+}
+
static void xehp_sseu_info_init(struct intel_gt *gt)
{
struct sseu_dev_info *sseu = >->info.sseu;
struct intel_uncore *uncore = gt->uncore;
- u32 g_dss_en, c_dss_en = 0;
u16 eu_en = 0;
u8 eu_en_fuse;
int eu;
@@ -201,8 +223,10 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
intel_sseu_set_info(sseu, 1, 32, 16);
sseu->has_xehp_dss = 1;
- g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
- c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
+ xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 1,
+ GEN12_GT_GEOMETRY_DSS_ENABLE);
+ xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 1,
+ GEN12_GT_COMPUTE_DSS_ENABLE);
eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
@@ -210,7 +234,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
+ xehp_compute_sseu_info(sseu, eu_en);
}
static void gen12_sseu_info_init(struct intel_gt *gt)
@@ -250,7 +274,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, g_dss_en, eu_en);
/* TGL only supports slice-level power gating */
sseu->has_slice_pg = 1;
@@ -284,7 +308,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
GEN11_EU_DIS_MASK);
- gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, ss_en, eu_en);
/* ICL has no power gating restrictions. */
sseu->has_slice_pg = 1;
@@ -296,7 +320,6 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
{
struct sseu_dev_info *sseu = >->info.sseu;
u32 fuse;
- u8 subslice_mask = 0;
fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT);
@@ -310,7 +333,7 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
- subslice_mask |= BIT(0);
+ sseu->subslice_mask.hsw[0] |= BIT(0);
sseu_set_eus(sseu, 0, 0, ~disabled_mask);
}
@@ -321,12 +344,10 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
(((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
- subslice_mask |= BIT(1);
+ sseu->subslice_mask.hsw[0] |= BIT(1);
sseu_set_eus(sseu, 0, 1, ~disabled_mask);
}
- intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask, subslice_mask);
-
sseu->eu_total = compute_eu_total(sseu);
/*
@@ -381,8 +402,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
/* skip disabled slice */
continue;
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
for (ss = 0; ss < sseu->max_subslices; ss++) {
@@ -439,8 +459,8 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
sseu->has_eu_pg = sseu->eu_per_subslice > 2;
if (IS_GEN9_LP(i915)) {
-#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
- info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
+#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask.hsw[0] & BIT(ss)))
+ info->has_pooled_eu = hweight8(sseu->subslice_mask.hsw[0]) == 3;
sseu->min_eu_in_pool = 0;
if (info->has_pooled_eu) {
@@ -494,8 +514,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
/* skip disabled slice */
continue;
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
for (ss = 0; ss < sseu->max_subslices; ss++) {
u8 eu_disabled_mask;
@@ -592,8 +611,7 @@ static void hsw_sseu_info_init(struct intel_gt *gt)
sseu->eu_per_subslice);
for (s = 0; s < sseu->max_slices; s++) {
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
for (ss = 0; ss < sseu->max_subslices; ss++) {
sseu_set_eus(sseu, s, ss,
@@ -682,7 +700,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
*/
if (GRAPHICS_VER(i915) == 11 &&
slices == 1 &&
- subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
+ subslices > min_t(u8, 4, hweight8(sseu->subslice_mask.hsw[0]) / 2)) {
GEM_BUG_ON(subslices & 1);
subslice_pg = false;
@@ -748,14 +766,25 @@ void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
{
int s;
- drm_printf(p, "slice total: %u, mask=%04x\n",
- hweight8(sseu->slice_mask), sseu->slice_mask);
- drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
- for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
- s, intel_sseu_subslices_per_slice(sseu, s),
- intel_sseu_get_subslices(sseu, s));
+ if (sseu->has_xehp_dss) {
+ drm_printf(p, "subslice total: %u\n",
+ intel_sseu_subslice_total(sseu));
+ drm_printf(p, "subslice mask=%*pb\n", I915_MAX_SS_FUSE_BITS,
+ sseu->subslice_mask.xehp);
+ } else {
+ drm_printf(p, "slice total: %u, mask=%04x\n",
+ hweight8(sseu->slice_mask), sseu->slice_mask);
+ drm_printf(p, "subslice total: %u\n",
+ intel_sseu_subslice_total(sseu));
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ u8 ss_mask = sseu->subslice_mask.hsw[s];
+
+ drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
+ s, hweight8(ss_mask), ss_mask);
+ }
}
+
drm_printf(p, "EU total: %u\n", sseu->eu_total);
drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
drm_printf(p, "has slice power gating: %s\n",
@@ -772,9 +801,10 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
int s, ss;
for (s = 0; s < sseu->max_slices; s++) {
+ u8 ss_mask = sseu->subslice_mask.hsw[s];
+
drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
- s, intel_sseu_subslices_per_slice(sseu, s),
- intel_sseu_get_subslices(sseu, s));
+ s, hweight8(ss_mask), ss_mask);
for (ss = 0; ss < sseu->max_subslices; ss++) {
u16 enabled_eus = sseu_get_eus(sseu, s, ss);
@@ -788,16 +818,14 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
static void sseu_print_xehp_topology(const struct sseu_dev_info *sseu,
struct drm_printer *p)
{
- u32 g_dss_mask = sseu_get_geometry_subslices(sseu);
- u32 c_dss_mask = intel_sseu_get_compute_subslices(sseu);
int dss;
for (dss = 0; dss < sseu->max_subslices; dss++) {
u16 enabled_eus = sseu_get_eus(sseu, 0, dss);
drm_printf(p, "DSS_%02d: G:%3s C:%3s, %2u EUs (0x%04hx)\n", dss,
- str_yes_no(g_dss_mask & BIT(dss)),
- str_yes_no(c_dss_mask & BIT(dss)),
+ str_yes_no(test_bit(dss, sseu->geometry_subslice_mask.xehp)),
+ str_yes_no(test_bit(dss, sseu->compute_subslice_mask.xehp)),
hweight16(enabled_eus), enabled_eus);
}
}
@@ -815,20 +843,40 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
}
}
-u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice)
+void intel_sseu_print_ss_info(const char* type,
+ const struct sseu_dev_info *sseu,
+ struct seq_file *m)
+{
+ int s;
+
+ if (sseu->has_xehp_dss)
+ seq_printf(m, " %s Subslices: %u\n", type,
+ bitmap_weight(sseu->subslice_mask.xehp,
+ I915_MAX_SS_FUSE_BITS));
+ else
+ for (s = 0; s < fls(sseu->slice_mask); s++)
+ seq_printf(m, " %s Slice%i subslices: %u\n", type,
+ s, hweight8(sseu->subslice_mask.hsw[s]));
+}
+
+u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask,
+ int dss_per_slice)
{
+ intel_sseu_ss_mask_t per_slice_mask = {};
u16 slice_mask = 0;
int i;
- WARN_ON(sizeof(dss_mask) * 8 / dss_per_slice > 8 * sizeof(slice_mask));
+ WARN_ON(DIV_ROUND_UP(I915_MAX_SS_FUSE_BITS, dss_per_slice) >
+ 8 * sizeof(slice_mask));
- for (i = 0; dss_mask; i++) {
- if (dss_mask & GENMASK(dss_per_slice - 1, 0))
+ bitmap_fill(per_slice_mask.xehp, dss_per_slice);
+ for (i = 0; !bitmap_empty(dss_mask.xehp, I915_MAX_SS_FUSE_BITS); i++) {
+ if (bitmap_intersects(dss_mask.xehp, per_slice_mask.xehp, dss_per_slice))
slice_mask |= BIT(i);
- dss_mask >>= dss_per_slice;
+ bitmap_shift_right(dss_mask.xehp, dss_mask.xehp, dss_per_slice,
+ I915_MAX_SS_FUSE_BITS);
}
return slice_mask;
}
-
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 43a8f8f98687..7fbb9276a1c2 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -25,12 +25,16 @@ struct drm_printer;
/*
* Maximum number of subslices that can exist within a HSW-style slice. This
* is only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the
- * GEN_MAX_DSS value below).
+ * I915_MAX_SS_FUSE_BITS value below).
*/
#define GEN_MAX_SS_PER_HSW_SLICE 6
-/* Maximum number of DSS on newer platforms (Xe_HP and beyond). */
-#define GEN_MAX_DSS 32
+/*
+ * Maximum number of 32-bit registers used by hardware to express the
+ * enabled/disabled subslices.
+ */
+#define I915_MAX_SS_FUSE_REGS 1
+#define I915_MAX_SS_FUSE_BITS (I915_MAX_SS_FUSE_REGS * 32)
/* Maximum number of EUs that can exist within a subslice or DSS. */
#define GEN_MAX_EUS_PER_SS 16
@@ -38,7 +42,7 @@ struct drm_printer;
#define SSEU_MAX(a, b) ((a) > (b) ? (a) : (b))
/* The maximum number of bits needed to express each subslice/DSS independently */
-#define GEN_SS_MASK_SIZE SSEU_MAX(GEN_MAX_DSS, \
+#define GEN_SS_MASK_SIZE SSEU_MAX(I915_MAX_SS_FUSE_BITS, \
GEN_MAX_HSW_SLICES * GEN_MAX_SS_PER_HSW_SLICE)
#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
@@ -49,17 +53,24 @@ struct drm_printer;
#define GEN_DSS_PER_CSLICE 8
#define GEN_DSS_PER_MSLICE 8
-#define GEN_MAX_GSLICES (GEN_MAX_DSS / GEN_DSS_PER_GSLICE)
-#define GEN_MAX_CSLICES (GEN_MAX_DSS / GEN_DSS_PER_CSLICE)
+#define GEN_MAX_GSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_GSLICE)
+#define GEN_MAX_CSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_CSLICE)
+
+typedef union {
+ u8 hsw[GEN_MAX_HSW_SLICES];
+
+ /* Bitmap compatible with linux/bitmap.h; may exceed size of u64 */
+ unsigned long xehp[BITS_TO_LONGS(I915_MAX_SS_FUSE_BITS)];
+} intel_sseu_ss_mask_t;
struct sseu_dev_info {
u8 slice_mask;
- u8 subslice_mask[GEN_SS_MASK_SIZE];
- u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
- u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
+ intel_sseu_ss_mask_t subslice_mask;
+ intel_sseu_ss_mask_t geometry_subslice_mask;
+ intel_sseu_ss_mask_t compute_subslice_mask;
union {
u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
- u16 xehp[GEN_MAX_DSS];
+ u16 xehp[I915_MAX_SS_FUSE_BITS];
} eu_mask;
u16 eu_total;
@@ -100,7 +111,7 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
{
struct intel_sseu value = {
.slice_mask = sseu->slice_mask,
- .subslice_mask = sseu->subslice_mask[0],
+ .subslice_mask = sseu->subslice_mask.hsw[0],
.min_eus_per_subslice = sseu->max_eus_per_subslice,
.max_eus_per_subslice = sseu->max_eus_per_subslice,
};
@@ -112,18 +123,23 @@ static inline bool
intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
int subslice)
{
- u8 mask;
- int ss_idx = subslice / BITS_PER_BYTE;
-
- if (slice >= sseu->max_slices ||
- subslice >= sseu->max_subslices)
- return false;
-
- GEM_BUG_ON(ss_idx >= sseu->ss_stride);
-
- mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx];
+ if (sseu->has_xehp_dss)
+ return test_bit(subslice, sseu->subslice_mask.xehp);
+ else
+ return sseu->subslice_mask.hsw[slice] & BIT(subslice);
+}
- return mask & BIT(subslice % BITS_PER_BYTE);
+/*
+ * Used to obtain the index of the first DSS. Can start searching from the
+ * beginning of a specific dss group (e.g., gslice, cslice, etc.) if
+ * groupsize and groupnum are non-zero.
+ */
+static inline unsigned int
+intel_sseu_find_first_xehp_dss(const struct sseu_dev_info *sseu, int groupsize,
+ int groupnum)
+{
+ return find_next_bit(sseu->subslice_mask.xehp, I915_MAX_SS_FUSE_BITS,
+ groupnum * groupsize);
}
void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
@@ -133,14 +149,10 @@ unsigned int
intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
unsigned int
-intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
-
-u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
+intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice);
-u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
-
-void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
- u8 *subslice_mask, u32 ss_mask);
+intel_sseu_ss_mask_t
+intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
void intel_sseu_info_init(struct intel_gt *gt);
@@ -152,9 +164,15 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
const struct sseu_dev_info *sseu,
struct drm_printer *p);
-u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
+u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask, int dss_per_slice);
int intel_sseu_copy_eumask_to_user(void __user *to,
const struct sseu_dev_info *sseu);
+int intel_sseu_copy_ssmask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu);
+
+void intel_sseu_print_ss_info(const char* type,
+ const struct sseu_dev_info *sseu,
+ struct seq_file *m);
#endif /* __INTEL_SSEU_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
index 2d5d011e01db..c2ee5e1826b5 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
@@ -4,6 +4,7 @@
* Copyright © 2020 Intel Corporation
*/
+#include <linux/bitmap.h>
#include <linux/string_helpers.h>
#include "i915_drv.h"
@@ -11,14 +12,6 @@
#include "intel_gt_regs.h"
#include "intel_sseu_debugfs.h"
-static void sseu_copy_subslices(const struct sseu_dev_info *sseu,
- int slice, u8 *to_mask)
-{
- int offset = slice * sseu->ss_stride;
-
- memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
-}
-
static void cherryview_sseu_device_status(struct intel_gt *gt,
struct sseu_dev_info *sseu)
{
@@ -41,7 +34,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt,
continue;
sseu->slice_mask = BIT(0);
- sseu->subslice_mask[0] |= BIT(ss);
+ sseu->subslice_mask.hsw[0] |= BIT(ss);
eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
@@ -92,7 +85,7 @@ static void gen11_sseu_device_status(struct intel_gt *gt,
continue;
sseu->slice_mask |= BIT(s);
- sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -147,21 +140,17 @@ static void gen9_sseu_device_status(struct intel_gt *gt,
sseu->slice_mask |= BIT(s);
if (IS_GEN9_BC(gt->i915))
- sseu_copy_subslices(&info->sseu, s,
- sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
- u8 ss_idx = s * info->sseu.ss_stride +
- ss / BITS_PER_BYTE;
if (IS_GEN9_LP(gt->i915)) {
if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
/* skip disabled subslice */
continue;
- sseu->subslice_mask[ss_idx] |=
- BIT(ss % BITS_PER_BYTE);
+ sseu->subslice_mask.hsw[s] |= BIT(ss);
}
eu_cnt = eu_reg[2 * s + ss / 2] & eu_mask[ss % 2];
@@ -188,8 +177,7 @@ static void bdw_sseu_device_status(struct intel_gt *gt,
if (sseu->slice_mask) {
sseu->eu_per_subslice = info->sseu.eu_per_subslice;
for (s = 0; s < fls(sseu->slice_mask); s++)
- sseu_copy_subslices(&info->sseu, s,
- sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
sseu->eu_total = sseu->eu_per_subslice *
intel_sseu_subslice_total(sseu);
@@ -208,7 +196,6 @@ static void i915_print_sseu_info(struct seq_file *m,
const struct sseu_dev_info *sseu)
{
const char *type = is_available_info ? "Available" : "Enabled";
- int s;
seq_printf(m, " %s Slice Mask: %04x\n", type,
sseu->slice_mask);
@@ -216,10 +203,7 @@ static void i915_print_sseu_info(struct seq_file *m,
hweight8(sseu->slice_mask));
seq_printf(m, " %s Subslice Total: %u\n", type,
intel_sseu_subslice_total(sseu));
- for (s = 0; s < fls(sseu->slice_mask); s++) {
- seq_printf(m, " %s Slice%i subslices: %u\n", type,
- s, intel_sseu_subslices_per_slice(sseu, s));
- }
+ intel_sseu_print_ss_info(type, sseu, m);
seq_printf(m, " %s EU Total: %u\n", type,
sseu->eu_total);
seq_printf(m, " %s EU Per Subslice: %u\n", type,
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 756807c4b405..fc6274708f8e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -948,8 +948,8 @@ gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
* on s/ss combo, the read should be done with read_subslice_reg.
*/
slice = ffs(sseu->slice_mask) - 1;
- GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
- subslice = ffs(intel_sseu_get_subslices(sseu, slice));
+ GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw));
+ subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice));
GEM_BUG_ON(!subslice);
subslice--;
@@ -1087,11 +1087,10 @@ static void
icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
{
const struct sseu_dev_info *sseu = >->info.sseu;
- unsigned int slice, subslice;
+ unsigned int subslice;
GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
- slice = 0;
/*
* Although a platform may have subslices, we need to always steer
@@ -1102,7 +1101,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
* one of the higher subslices, we run the risk of reading back 0's or
* random garbage.
*/
- subslice = __ffs(intel_sseu_get_subslices(sseu, slice));
+ subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0));
/*
* If the subslice we picked above also steers us to a valid L3 bank,
@@ -1112,7 +1111,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
if (gt->info.l3bank_mask & BIT(subslice))
gt->steering_table[L3BANK] = NULL;
- __add_mcr_wa(gt, wal, slice, subslice);
+ __add_mcr_wa(gt, wal, 0, subslice);
}
static void
@@ -1120,7 +1119,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
{
const struct sseu_dev_info *sseu = >->info.sseu;
unsigned long slice, subslice = 0, slice_mask = 0;
- u64 dss_mask = 0;
u32 lncf_mask = 0;
int i;
@@ -1151,8 +1149,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
*/
/* Find the potential gslice candidates */
- dss_mask = intel_sseu_get_subslices(sseu, 0);
- slice_mask = intel_slicemask_from_dssmask(dss_mask, GEN_DSS_PER_GSLICE);
+ slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask,
+ GEN_DSS_PER_GSLICE);
/*
* Find the potential LNCF candidates. Either LNCF within a valid
@@ -1177,9 +1175,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
}
slice = __ffs(slice_mask);
- subslice = __ffs(dss_mask >> (slice * GEN_DSS_PER_GSLICE));
+ subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice);
WARN_ON(subslice > GEN_DSS_PER_GSLICE);
- WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0);
__add_mcr_wa(gt, wal, slice, subslice);
@@ -2030,9 +2027,8 @@ engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
static bool needs_wa_1308578152(struct intel_engine_cs *engine)
{
- u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0);
-
- return (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0;
+ return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >
+ GEN_DSS_PER_GSLICE;
}
static void
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index ac9767c56619..6fd15b39570c 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -162,8 +162,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
return -EINVAL;
/* Only copy bits from the first slice */
- memcpy(&value, sseu->subslice_mask,
- min(sseu->ss_stride, (u8)sizeof(value)));
+ value = intel_sseu_get_hsw_subslices(sseu, 0);
if (!value)
return -ENODEV;
break;
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 16f43bf32a05..9afa6d1eaf95 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -31,7 +31,7 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
static int fill_topology_info(const struct sseu_dev_info *sseu,
struct drm_i915_query_item *query_item,
- const u8 *subslice_mask)
+ intel_sseu_ss_mask_t subslice_mask)
{
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
@@ -71,9 +71,9 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
&sseu->slice_mask, slice_length))
return -EFAULT;
- if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
- sizeof(topo) + slice_length),
- subslice_mask, subslice_length))
+ if (intel_sseu_copy_ssmask_to_user(u64_to_user_ptr(query_item->data_ptr +
+ sizeof(topo) + slice_length),
+ sseu))
return -EFAULT;
if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
--
2.35.3
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: SSEU handling updates (rev4)
2022-05-17 3:19 ` [Intel-gfx] " Matt Roper
` (10 preceding siblings ...)
(?)
@ 2022-05-17 18:44 ` Patchwork
-1 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2022-05-17 18:44 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: i915: SSEU handling updates (rev4)
URL : https://patchwork.freedesktop.org/series/103244/
State : warning
== Summary ==
Error: dim checkpatch failed
887126b08a62 drm/i915/xehp: Use separate sseu init function
913cf54798d2 drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
2ee6de43eff7 drm/i915/sseu: Simplify gen11+ SSEU handling
616556780612 drm/i915/sseu: Don't try to store EU mask internally in UAPI format
982793037c15 drm/i915/sseu: Disassociate internal subslice mask representation from uapi
-:481: ERROR:POINTER_LOCATION: "foo* bar" should be "foo *bar"
#481: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:846:
+void intel_sseu_print_ss_info(const char* type,
-:565: WARNING:NEW_TYPEDEFS: do not add new typedefs
#565: FILE: drivers/gpu/drm/i915/gt/intel_sseu.h:59:
+typedef union {
-:661: ERROR:POINTER_LOCATION: "foo* bar" should be "foo *bar"
#661: FILE: drivers/gpu/drm/i915/gt/intel_sseu.h:174:
+void intel_sseu_print_ss_info(const char* type,
total: 2 errors, 1 warnings, 0 checks, 779 lines checked
a1f8cbcba917 drm/i915/pvc: Add SSEU changes
^ permalink raw reply [flat|nested] 43+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: SSEU handling updates (rev4)
2022-05-17 3:19 ` [Intel-gfx] " Matt Roper
` (11 preceding siblings ...)
(?)
@ 2022-05-17 18:44 ` Patchwork
-1 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2022-05-17 18:44 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: i915: SSEU handling updates (rev4)
URL : https://patchwork.freedesktop.org/series/103244/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 43+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: SSEU handling updates (rev4)
2022-05-17 3:19 ` [Intel-gfx] " Matt Roper
` (12 preceding siblings ...)
(?)
@ 2022-05-17 19:08 ` Patchwork
2022-05-17 19:19 ` Matt Roper
-1 siblings, 1 reply; 43+ messages in thread
From: Patchwork @ 2022-05-17 19:08 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8725 bytes --]
== Series Details ==
Series: i915: SSEU handling updates (rev4)
URL : https://patchwork.freedesktop.org/series/103244/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11666 -> Patchwork_103244v4
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_103244v4 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_103244v4, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/index.html
Participating hosts (41 -> 41)
------------------------------
Additional (1): fi-skl-guc
Missing (1): bat-rpls-2
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_103244v4:
### IGT changes ###
#### Possible regressions ####
* igt@prime_vgem@basic-fence-read:
- fi-kbl-soraka: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/fi-kbl-soraka/igt@prime_vgem@basic-fence-read.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-kbl-soraka/igt@prime_vgem@basic-fence-read.html
Known issues
------------
Here are the changes found in Patchwork_103244v4 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_lmem_swapping@basic:
- fi-skl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-skl-guc/igt@gem_lmem_swapping@basic.html
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [PASS][4] -> [INCOMPLETE][5] ([i915#2940] / [i915#5801])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gem:
- fi-pnv-d510: NOTRUN -> [DMESG-FAIL][6] ([i915#4528])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-pnv-d510/igt@i915_selftest@live@gem.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [PASS][7] -> [INCOMPLETE][8] ([i915#3921])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@dp-crc-fast:
- fi-skl-guc: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-skl-guc/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-skl-guc: NOTRUN -> [SKIP][10] ([fdo#109271]) +11 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-skl-guc/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-guc: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#533])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-skl-guc/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@runner@aborted:
- fi-bsw-kefka: NOTRUN -> [FAIL][12] ([fdo#109271] / [i915#3428] / [i915#4312])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-bsw-kefka/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@objects:
- {bat-dg2-9}: [DMESG-WARN][13] ([i915#5763]) -> [PASS][14] +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/bat-dg2-9/igt@i915_selftest@live@objects.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/bat-dg2-9/igt@i915_selftest@live@objects.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510: [DMESG-FAIL][15] ([i915#4528]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/fi-pnv-d510/igt@i915_selftest@live@requests.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-pnv-d510/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@reset:
- {fi-jsl-1}: [INCOMPLETE][17] -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/fi-jsl-1/igt@i915_selftest@live@reset.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-jsl-1/igt@i915_selftest@live@reset.html
* igt@kms_busy@basic@flip:
- {bat-adlp-6}: [DMESG-WARN][19] ([i915#3576]) -> [PASS][20] +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/bat-adlp-6/igt@kms_busy@basic@flip.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/bat-adlp-6/igt@kms_busy@basic@flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
[i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
[i915#5801]: https://gitlab.freedesktop.org/drm/intel/issues/5801
[i915#5885]: https://gitlab.freedesktop.org/drm/intel/issues/5885
[i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
Build changes
-------------
* Linux: CI_DRM_11666 -> Patchwork_103244v4
CI-20190529: 20190529
CI_DRM_11666: 73bb9fa49db3df15c6024a743a48139b1fcdcf7e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6476: 08aa9296163b94cf4c529fc890ae3e90e21c3cdb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103244v4: 73bb9fa49db3df15c6024a743a48139b1fcdcf7e @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
f79229c733a2 drm/i915/pvc: Add SSEU changes
995c1647a0d6 drm/i915/sseu: Disassociate internal subslice mask representation from uapi
6e28799e6216 drm/i915/sseu: Don't try to store EU mask internally in UAPI format
95fd2c3dc7e9 drm/i915/sseu: Simplify gen11+ SSEU handling
9db3639b067c drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
0f70c4e7a760 drm/i915/xehp: Use separate sseu init function
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/index.html
[-- Attachment #2: Type: text/html, Size: 8265 bytes --]
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: SSEU handling updates (rev4)
2022-05-17 19:08 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2022-05-17 19:19 ` Matt Roper
2022-05-17 20:44 ` Vudum, Lakshminarayana
0 siblings, 1 reply; 43+ messages in thread
From: Matt Roper @ 2022-05-17 19:19 UTC (permalink / raw)
To: intel-gfx; +Cc: Vudum, Lakshminarayana
On Tue, May 17, 2022 at 07:08:08PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: i915: SSEU handling updates (rev4)
> URL : https://patchwork.freedesktop.org/series/103244/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11666 -> Patchwork_103244v4
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_103244v4 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_103244v4, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/index.html
>
> Participating hosts (41 -> 41)
> ------------------------------
>
> Additional (1): fi-skl-guc
> Missing (1): bat-rpls-2
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_103244v4:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@prime_vgem@basic-fence-read:
> - fi-kbl-soraka: [PASS][1] -> [INCOMPLETE][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/fi-kbl-soraka/igt@prime_vgem@basic-fence-read.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-kbl-soraka/igt@prime_vgem@basic-fence-read.html
The results link shows 'SUCCESS' so I'm not sure why this was marked as
INCOMPLETE here?
Doesn't appear to be related to this series.
Matt
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_103244v4 that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_lmem_swapping@basic:
> - fi-skl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 similar issues
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-skl-guc/igt@gem_lmem_swapping@basic.html
>
> * igt@i915_selftest@live@execlists:
> - fi-bsw-kefka: [PASS][4] -> [INCOMPLETE][5] ([i915#2940] / [i915#5801])
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
>
> * igt@i915_selftest@live@gem:
> - fi-pnv-d510: NOTRUN -> [DMESG-FAIL][6] ([i915#4528])
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-pnv-d510/igt@i915_selftest@live@gem.html
>
> * igt@i915_selftest@live@hangcheck:
> - fi-snb-2600: [PASS][7] -> [INCOMPLETE][8] ([i915#3921])
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
>
> * igt@kms_chamelium@dp-crc-fast:
> - fi-skl-guc: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 similar issues
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-skl-guc/igt@kms_chamelium@dp-crc-fast.html
>
> * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
> - fi-skl-guc: NOTRUN -> [SKIP][10] ([fdo#109271]) +11 similar issues
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-skl-guc/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
>
> * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
> - fi-skl-guc: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#533])
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-skl-guc/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
>
> * igt@runner@aborted:
> - fi-bsw-kefka: NOTRUN -> [FAIL][12] ([fdo#109271] / [i915#3428] / [i915#4312])
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-bsw-kefka/igt@runner@aborted.html
>
>
> #### Possible fixes ####
>
> * igt@i915_selftest@live@objects:
> - {bat-dg2-9}: [DMESG-WARN][13] ([i915#5763]) -> [PASS][14] +1 similar issue
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/bat-dg2-9/igt@i915_selftest@live@objects.html
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/bat-dg2-9/igt@i915_selftest@live@objects.html
>
> * igt@i915_selftest@live@requests:
> - fi-pnv-d510: [DMESG-FAIL][15] ([i915#4528]) -> [PASS][16]
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/fi-pnv-d510/igt@i915_selftest@live@requests.html
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-pnv-d510/igt@i915_selftest@live@requests.html
>
> * igt@i915_selftest@live@reset:
> - {fi-jsl-1}: [INCOMPLETE][17] -> [PASS][18]
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/fi-jsl-1/igt@i915_selftest@live@reset.html
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-jsl-1/igt@i915_selftest@live@reset.html
>
> * igt@kms_busy@basic@flip:
> - {bat-adlp-6}: [DMESG-WARN][19] ([i915#3576]) -> [PASS][20] +1 similar issue
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/bat-adlp-6/igt@kms_busy@basic@flip.html
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/bat-adlp-6/igt@kms_busy@basic@flip.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
> [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
> [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
> [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
> [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
> [i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
> [i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
> [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
> [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
> [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
> [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
> [i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547
> [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
> [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
> [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
> [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
> [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
> [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
> [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
> [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
> [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
> [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
> [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
> [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
> [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
> [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
> [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
> [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
> [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
> [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
> [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
> [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
> [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
> [i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
> [i915#5801]: https://gitlab.freedesktop.org/drm/intel/issues/5801
> [i915#5885]: https://gitlab.freedesktop.org/drm/intel/issues/5885
> [i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_11666 -> Patchwork_103244v4
>
> CI-20190529: 20190529
> CI_DRM_11666: 73bb9fa49db3df15c6024a743a48139b1fcdcf7e @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6476: 08aa9296163b94cf4c529fc890ae3e90e21c3cdb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_103244v4: 73bb9fa49db3df15c6024a743a48139b1fcdcf7e @ git://anongit.freedesktop.org/gfx-ci/linux
>
>
> ### Linux commits
>
> f79229c733a2 drm/i915/pvc: Add SSEU changes
> 995c1647a0d6 drm/i915/sseu: Disassociate internal subslice mask representation from uapi
> 6e28799e6216 drm/i915/sseu: Don't try to store EU mask internally in UAPI format
> 95fd2c3dc7e9 drm/i915/sseu: Simplify gen11+ SSEU handling
> 9db3639b067c drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
> 0f70c4e7a760 drm/i915/xehp: Use separate sseu init function
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 43+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for i915: SSEU handling updates (rev4)
2022-05-17 3:19 ` [Intel-gfx] " Matt Roper
` (13 preceding siblings ...)
(?)
@ 2022-05-17 20:20 ` Patchwork
-1 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2022-05-17 20:20 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8318 bytes --]
== Series Details ==
Series: i915: SSEU handling updates (rev4)
URL : https://patchwork.freedesktop.org/series/103244/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11666 -> Patchwork_103244v4
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/index.html
Participating hosts (41 -> 41)
------------------------------
Additional (1): fi-skl-guc
Missing (1): bat-rpls-2
Known issues
------------
Here are the changes found in Patchwork_103244v4 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_lmem_swapping@basic:
- fi-skl-guc: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#4613]) +3 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-skl-guc/igt@gem_lmem_swapping@basic.html
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [PASS][2] -> [INCOMPLETE][3] ([i915#2940] / [i915#5801])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gem:
- fi-pnv-d510: NOTRUN -> [DMESG-FAIL][4] ([i915#4528])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-pnv-d510/igt@i915_selftest@live@gem.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [PASS][5] -> [INCOMPLETE][6] ([i915#3921])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@dp-crc-fast:
- fi-skl-guc: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-skl-guc/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-skl-guc: NOTRUN -> [SKIP][8] ([fdo#109271]) +11 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-skl-guc/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-guc: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#533])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-skl-guc/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@prime_vgem@basic-fence-read:
- fi-kbl-soraka: [PASS][10] -> [INCOMPLETE][11] ([i915#6025])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/fi-kbl-soraka/igt@prime_vgem@basic-fence-read.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-kbl-soraka/igt@prime_vgem@basic-fence-read.html
* igt@runner@aborted:
- fi-bsw-kefka: NOTRUN -> [FAIL][12] ([fdo#109271] / [i915#3428] / [i915#4312])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-bsw-kefka/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@objects:
- {bat-dg2-9}: [DMESG-WARN][13] ([i915#5763]) -> [PASS][14] +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/bat-dg2-9/igt@i915_selftest@live@objects.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/bat-dg2-9/igt@i915_selftest@live@objects.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510: [DMESG-FAIL][15] ([i915#4528]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/fi-pnv-d510/igt@i915_selftest@live@requests.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-pnv-d510/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@reset:
- {fi-jsl-1}: [INCOMPLETE][17] -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/fi-jsl-1/igt@i915_selftest@live@reset.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-jsl-1/igt@i915_selftest@live@reset.html
* igt@kms_busy@basic@flip:
- {bat-adlp-6}: [DMESG-WARN][19] ([i915#3576]) -> [PASS][20] +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/bat-adlp-6/igt@kms_busy@basic@flip.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/bat-adlp-6/igt@kms_busy@basic@flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
[i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
[i915#5801]: https://gitlab.freedesktop.org/drm/intel/issues/5801
[i915#5885]: https://gitlab.freedesktop.org/drm/intel/issues/5885
[i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
[i915#6025]: https://gitlab.freedesktop.org/drm/intel/issues/6025
Build changes
-------------
* Linux: CI_DRM_11666 -> Patchwork_103244v4
CI-20190529: 20190529
CI_DRM_11666: 73bb9fa49db3df15c6024a743a48139b1fcdcf7e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6476: 08aa9296163b94cf4c529fc890ae3e90e21c3cdb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103244v4: 73bb9fa49db3df15c6024a743a48139b1fcdcf7e @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
f79229c733a2 drm/i915/pvc: Add SSEU changes
995c1647a0d6 drm/i915/sseu: Disassociate internal subslice mask representation from uapi
6e28799e6216 drm/i915/sseu: Don't try to store EU mask internally in UAPI format
95fd2c3dc7e9 drm/i915/sseu: Simplify gen11+ SSEU handling
9db3639b067c drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
0f70c4e7a760 drm/i915/xehp: Use separate sseu init function
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/index.html
[-- Attachment #2: Type: text/html, Size: 7846 bytes --]
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: SSEU handling updates (rev4)
2022-05-17 19:19 ` Matt Roper
@ 2022-05-17 20:44 ` Vudum, Lakshminarayana
0 siblings, 0 replies; 43+ messages in thread
From: Vudum, Lakshminarayana @ 2022-05-17 20:44 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx
Since it's bat failure, I have filed a new issue
https://gitlab.freedesktop.org/drm/intel/-/issues/6025
igt@prime_vgem@basic-fence-read - incomplete - No warnings/errors
Thanks,
Lakshmi.
-----Original Message-----
From: Roper, Matthew D <matthew.d.roper@intel.com>
Sent: Tuesday, May 17, 2022 12:20 PM
To: intel-gfx@lists.freedesktop.org
Cc: Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>
Subject: Re: ✗ Fi.CI.BAT: failure for i915: SSEU handling updates (rev4)
On Tue, May 17, 2022 at 07:08:08PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: i915: SSEU handling updates (rev4)
> URL : https://patchwork.freedesktop.org/series/103244/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11666 -> Patchwork_103244v4
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_103244v4 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_103244v4, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/index.html
>
> Participating hosts (41 -> 41)
> ------------------------------
>
> Additional (1): fi-skl-guc
> Missing (1): bat-rpls-2
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_103244v4:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@prime_vgem@basic-fence-read:
> - fi-kbl-soraka: [PASS][1] -> [INCOMPLETE][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/fi-kbl-soraka/igt@prime_vgem@basic-fence-read.html
> [2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-kbl-sor
> aka/igt@prime_vgem@basic-fence-read.html
The results link shows 'SUCCESS' so I'm not sure why this was marked as INCOMPLETE here?
Doesn't appear to be related to this series.
Matt
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_103244v4 that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_lmem_swapping@basic:
> - fi-skl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 similar issues
> [3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-skl-guc
> /igt@gem_lmem_swapping@basic.html
>
> * igt@i915_selftest@live@execlists:
> - fi-bsw-kefka: [PASS][4] -> [INCOMPLETE][5] ([i915#2940] / [i915#5801])
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
> [5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-bsw-kef
> ka/igt@i915_selftest@live@execlists.html
>
> * igt@i915_selftest@live@gem:
> - fi-pnv-d510: NOTRUN -> [DMESG-FAIL][6] ([i915#4528])
> [6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-pnv-d51
> 0/igt@i915_selftest@live@gem.html
>
> * igt@i915_selftest@live@hangcheck:
> - fi-snb-2600: [PASS][7] -> [INCOMPLETE][8] ([i915#3921])
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
> [8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-snb-260
> 0/igt@i915_selftest@live@hangcheck.html
>
> * igt@kms_chamelium@dp-crc-fast:
> - fi-skl-guc: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 similar issues
> [9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-skl-guc
> /igt@kms_chamelium@dp-crc-fast.html
>
> * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
> - fi-skl-guc: NOTRUN -> [SKIP][10] ([fdo#109271]) +11 similar issues
> [10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-skl-guc
> /igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
>
> * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
> - fi-skl-guc: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#533])
> [11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-skl-guc
> /igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
>
> * igt@runner@aborted:
> - fi-bsw-kefka: NOTRUN -> [FAIL][12] ([fdo#109271] / [i915#3428] / [i915#4312])
> [12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-bsw-kef
> ka/igt@runner@aborted.html
>
>
> #### Possible fixes ####
>
> * igt@i915_selftest@live@objects:
> - {bat-dg2-9}: [DMESG-WARN][13] ([i915#5763]) -> [PASS][14] +1 similar issue
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/bat-dg2-9/igt@i915_selftest@live@objects.html
> [14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/bat-dg2-9/
> igt@i915_selftest@live@objects.html
>
> * igt@i915_selftest@live@requests:
> - fi-pnv-d510: [DMESG-FAIL][15] ([i915#4528]) -> [PASS][16]
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/fi-pnv-d510/igt@i915_selftest@live@requests.html
> [16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-pnv-d51
> 0/igt@i915_selftest@live@requests.html
>
> * igt@i915_selftest@live@reset:
> - {fi-jsl-1}: [INCOMPLETE][17] -> [PASS][18]
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/fi-jsl-1/igt@i915_selftest@live@reset.html
> [18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/fi-jsl-1/i
> gt@i915_selftest@live@reset.html
>
> * igt@kms_busy@basic@flip:
> - {bat-adlp-6}: [DMESG-WARN][19] ([i915#3576]) -> [PASS][20] +1 similar issue
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/bat-adlp-6/igt@kms_busy@basic@flip.html
> [20]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/bat-adlp-6
> /igt@kms_busy@basic@flip.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
> [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
> [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
> [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
> [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
> [i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
> [i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
> [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
> [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
> [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
> [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
> [i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547
> [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
> [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
> [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
> [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
> [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
> [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
> [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
> [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
> [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
> [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
> [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
> [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
> [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
> [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
> [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
> [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
> [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
> [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
> [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
> [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
> [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
> [i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
> [i915#5801]: https://gitlab.freedesktop.org/drm/intel/issues/5801
> [i915#5885]: https://gitlab.freedesktop.org/drm/intel/issues/5885
> [i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_11666 -> Patchwork_103244v4
>
> CI-20190529: 20190529
> CI_DRM_11666: 73bb9fa49db3df15c6024a743a48139b1fcdcf7e @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6476: 08aa9296163b94cf4c529fc890ae3e90e21c3cdb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_103244v4: 73bb9fa49db3df15c6024a743a48139b1fcdcf7e @
> git://anongit.freedesktop.org/gfx-ci/linux
>
>
> ### Linux commits
>
> f79229c733a2 drm/i915/pvc: Add SSEU changes
> 995c1647a0d6 drm/i915/sseu: Disassociate internal subslice mask
> representation from uapi
> 6e28799e6216 drm/i915/sseu: Don't try to store EU mask internally in
> UAPI format
> 95fd2c3dc7e9 drm/i915/sseu: Simplify gen11+ SSEU handling 9db3639b067c
> drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
> 0f70c4e7a760 drm/i915/xehp: Use separate sseu init function
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 43+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: SSEU handling updates (rev4)
2022-05-17 3:19 ` [Intel-gfx] " Matt Roper
` (14 preceding siblings ...)
(?)
@ 2022-05-18 0:34 ` Patchwork
2022-05-18 3:24 ` Matt Roper
-1 siblings, 1 reply; 43+ messages in thread
From: Patchwork @ 2022-05-18 0:34 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 48092 bytes --]
== Series Details ==
Series: i915: SSEU handling updates (rev4)
URL : https://patchwork.freedesktop.org/series/103244/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11666_full -> Patchwork_103244v4_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_103244v4_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_103244v4_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_103244v4_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_flip@flip-vs-panning-interruptible@c-edp1:
- shard-iclb: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb3/igt@kms_flip@flip-vs-panning-interruptible@c-edp1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb8/igt@kms_flip@flip-vs-panning-interruptible@c-edp1.html
Known issues
------------
Here are the changes found in Patchwork_103244v4_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-skl: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [FAIL][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26]) ([i915#5032]) -> ([PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl9/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl9/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl9/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl7/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl7/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl7/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl6/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl6/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl6/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl3/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl3/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl1/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl1/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl1/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl10/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl10/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl10/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl1/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl1/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl1/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl3/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl3/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl4/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl4/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl7/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl7/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl7/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl8/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl8/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/boot.html
### IGT changes ###
#### Issues hit ####
* igt@drm_buddy@all@buddy_alloc_smoke:
- shard-skl: [PASS][50] -> [INCOMPLETE][51] ([i915#5800])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl6/igt@drm_buddy@all@buddy_alloc_smoke.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl1/igt@drm_buddy@all@buddy_alloc_smoke.html
* igt@gem_create@create-massive:
- shard-kbl: NOTRUN -> [DMESG-WARN][52] ([i915#4991])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@gem_create@create-massive.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [PASS][53] -> [SKIP][54] ([i915#4525])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb4/igt@gem_exec_balancer@parallel-balancer.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb5/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-kbl: NOTRUN -> [DMESG-WARN][55] ([i915#5076] / [i915#5614])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][56] -> [FAIL][57] ([i915#2842])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglb3/igt@gem_exec_fair@basic-none-share@rcs0.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglb8/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][58] -> [FAIL][59] ([i915#2842]) +2 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][60] -> [FAIL][61] ([i915#2842]) +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][62] ([i915#2842]) +2 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: NOTRUN -> [FAIL][63] ([i915#2849])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_params@secure-non-root:
- shard-iclb: NOTRUN -> [SKIP][64] ([fdo#112283])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@gem_exec_params@secure-non-root.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][65] -> [SKIP][66] ([i915#2190])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglb5/igt@gem_huc_copy@huc-copy.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- shard-iclb: NOTRUN -> [SKIP][67] ([i915#4613]) +2 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@gem_lmem_swapping@basic.html
- shard-apl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#4613]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl6/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-skl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#4613]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_lmem_swapping@verify-random:
- shard-kbl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#4613])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@gem_lmem_swapping@verify-random.html
* igt@gem_render_copy@y-tiled-to-vebox-linear:
- shard-iclb: NOTRUN -> [SKIP][71] ([i915#768]) +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@gem_render_copy@y-tiled-to-vebox-linear.html
* igt@gem_softpin@evict-single-offset:
- shard-kbl: NOTRUN -> [FAIL][72] ([i915#4171])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@gem_softpin@evict-single-offset.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-apl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#3323])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@vma-merge:
- shard-skl: NOTRUN -> [FAIL][74] ([i915#3318])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@bb-chained:
- shard-iclb: NOTRUN -> [SKIP][75] ([i915#2856]) +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@gen9_exec_parse@bb-chained.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- shard-iclb: NOTRUN -> [SKIP][76] ([fdo#110892])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@i915_pm_rpm@modeset-non-lpsp.html
* igt@i915_pm_sseu@full-enable:
- shard-iclb: NOTRUN -> [SKIP][77] ([i915#4387])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@i915_pm_sseu@full-enable.html
* igt@i915_selftest@mock@requests:
- shard-skl: [PASS][78] -> [INCOMPLETE][79] ([i915#5183])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/igt@i915_selftest@mock@requests.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl8/igt@i915_selftest@mock@requests.html
* igt@i915_suspend@forcewake:
- shard-apl: [PASS][80] -> [DMESG-WARN][81] ([i915#180])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl6/igt@i915_suspend@forcewake.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl4/igt@i915_suspend@forcewake.html
* igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
- shard-iclb: NOTRUN -> [SKIP][82] ([i915#3826])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
* igt@kms_async_flips@crc:
- shard-skl: NOTRUN -> [FAIL][83] ([i915#4272])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_async_flips@crc.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-iclb: NOTRUN -> [SKIP][84] ([i915#5286]) +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][85] ([fdo#110725] / [fdo#111614]) +2 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][86] ([fdo#110723])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html
* igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#3886]) +5 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl6/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#3886]) +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#3886])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs:
- shard-iclb: NOTRUN -> [SKIP][90] ([fdo#109278]) +26 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][91] ([fdo#109278] / [i915#3886]) +2 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@dp-crc-multiple:
- shard-skl: NOTRUN -> [SKIP][92] ([fdo#109271] / [fdo#111827]) +12 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/igt@kms_chamelium@dp-crc-multiple.html
* igt@kms_chamelium@dp-hpd-for-each-pipe:
- shard-apl: NOTRUN -> [SKIP][93] ([fdo#109271] / [fdo#111827]) +4 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl3/igt@kms_chamelium@dp-hpd-for-each-pipe.html
* igt@kms_color_chamelium@pipe-a-ctm-red-to-blue:
- shard-iclb: NOTRUN -> [SKIP][94] ([fdo#109284] / [fdo#111827]) +9 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_color_chamelium@pipe-a-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-c-ctm-limited-range:
- shard-kbl: NOTRUN -> [SKIP][95] ([fdo#109271] / [fdo#111827])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@kms_color_chamelium@pipe-c-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-d-ctm-0-25:
- shard-iclb: NOTRUN -> [SKIP][96] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_color_chamelium@pipe-d-ctm-0-25.html
* igt@kms_content_protection@atomic:
- shard-apl: NOTRUN -> [TIMEOUT][97] ([i915#1319])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl3/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-iclb: NOTRUN -> [SKIP][98] ([i915#3116])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@lic:
- shard-iclb: NOTRUN -> [SKIP][99] ([fdo#109300] / [fdo#111066])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_content_protection@lic.html
* igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding:
- shard-iclb: NOTRUN -> [SKIP][100] ([fdo#109278] / [fdo#109279]) +3 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen:
- shard-skl: NOTRUN -> [SKIP][101] ([fdo#109271]) +151 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen:
- shard-kbl: NOTRUN -> [SKIP][102] ([fdo#109271]) +55 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl1/igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
- shard-iclb: NOTRUN -> [SKIP][103] ([fdo#109274] / [fdo#109278]) +2 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_dp_tiled_display@basic-test-pattern:
- shard-iclb: NOTRUN -> [SKIP][104] ([i915#426])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_dp_tiled_display@basic-test-pattern.html
* igt@kms_flip@2x-flip-vs-dpms:
- shard-iclb: NOTRUN -> [SKIP][105] ([fdo#109274]) +5 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_flip@2x-flip-vs-dpms.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [PASS][106] -> [FAIL][107] ([i915#2122]) +1 similar issue
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
- shard-glk: [PASS][108] -> [FAIL][109] ([i915#4911])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-glk5/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
- shard-iclb: [PASS][110] -> [SKIP][111] ([i915#3701])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
- shard-iclb: NOTRUN -> [SKIP][112] ([fdo#109280]) +22 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-iclb: NOTRUN -> [SKIP][113] ([i915#1839])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][114] ([i915#265])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][115] ([fdo#108145] / [i915#265])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl6/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-skl: NOTRUN -> [FAIL][116] ([fdo#108145] / [i915#265]) +1 similar issue
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][117] -> [FAIL][118] ([fdo#108145] / [i915#265]) +1 similar issue
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: NOTRUN -> [SKIP][119] ([i915#3536]) +1 similar issue
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_plane_scaling@downscale-with-modifier-factor-0-25@pipe-a-edp-1-downscale-with-modifier:
- shard-skl: NOTRUN -> [SKIP][120] ([fdo#109271] / [i915#5176]) +2 similar issues
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_plane_scaling@downscale-with-modifier-factor-0-25@pipe-a-edp-1-downscale-with-modifier.html
* igt@kms_plane_scaling@invalid-num-scalers@pipe-a-edp-1-invalid-num-scalers:
- shard-skl: NOTRUN -> [SKIP][121] ([fdo#109271] / [i915#5776]) +2 similar issues
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/igt@kms_plane_scaling@invalid-num-scalers@pipe-a-edp-1-invalid-num-scalers.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale:
- shard-iclb: [PASS][122] -> [SKIP][123] ([i915#5235]) +2 similar issues
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-apl: NOTRUN -> [SKIP][124] ([fdo#109271] / [i915#658]) +1 similar issue
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-iclb: NOTRUN -> [SKIP][125] ([fdo#111068] / [i915#658])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-iclb: NOTRUN -> [SKIP][126] ([fdo#109642] / [fdo#111068] / [i915#658])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr2_su@page_flip-p010:
- shard-kbl: NOTRUN -> [SKIP][127] ([fdo#109271] / [i915#658]) +1 similar issue
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-skl: NOTRUN -> [SKIP][128] ([fdo#109271] / [i915#658]) +1 similar issue
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: NOTRUN -> [SKIP][129] ([fdo#109441]) +2 similar issues
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [PASS][130] -> [SKIP][131] ([fdo#109441]) +1 similar issue
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb2/igt@kms_psr@psr2_suspend.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_psr@psr2_suspend.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-skl: [PASS][132] -> [DMESG-WARN][133] ([i915#1982])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
- shard-iclb: [PASS][134] -> [SKIP][135] ([i915#5519])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
- shard-apl: NOTRUN -> [SKIP][136] ([fdo#109271]) +118 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][137] ([IGT#2])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl6/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-apl: NOTRUN -> [SKIP][138] ([fdo#109271] / [i915#533]) +3 similar issues
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_vrr@flip-basic:
- shard-iclb: NOTRUN -> [SKIP][139] ([i915#3555]) +1 similar issue
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_vrr@flip-basic.html
* igt@nouveau_crc@pipe-a-source-rg:
- shard-iclb: NOTRUN -> [SKIP][140] ([i915#2530]) +1 similar issue
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@nouveau_crc@pipe-a-source-rg.html
* igt@perf@polling:
- shard-skl: [PASS][141] -> [FAIL][142] ([i915#1542])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl9/igt@perf@polling.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl3/igt@perf@polling.html
* igt@prime_nv_pcopy@test3_3:
- shard-iclb: NOTRUN -> [SKIP][143] ([fdo#109291]) +3 similar issues
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@prime_nv_pcopy@test3_3.html
* igt@sysfs_clients@fair-0:
- shard-skl: NOTRUN -> [SKIP][144] ([fdo#109271] / [i915#2994]) +3 similar issues
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/igt@sysfs_clients@fair-0.html
* igt@sysfs_clients@fair-3:
- shard-apl: NOTRUN -> [SKIP][145] ([fdo#109271] / [i915#2994])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl3/igt@sysfs_clients@fair-3.html
* igt@sysfs_clients@split-10:
- shard-iclb: NOTRUN -> [SKIP][146] ([i915#2994]) +2 similar issues
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@sysfs_clients@split-10.html
#### Possible fixes ####
* igt@gem_eio@in-flight-10ms:
- shard-tglb: [TIMEOUT][147] ([i915#3063]) -> [PASS][148]
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglb2/igt@gem_eio@in-flight-10ms.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglb1/igt@gem_eio@in-flight-10ms.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- {shard-tglu}: [FAIL][149] ([i915#2842]) -> [PASS][150]
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglu-6/igt@gem_exec_fair@basic-none-share@rcs0.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglu-2/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: [FAIL][151] ([i915#2842]) -> [PASS][152]
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl4/igt@gem_exec_fair@basic-none@vcs0.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl8/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-kbl: [FAIL][153] ([i915#2842]) -> [PASS][154]
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl3/igt@gem_exec_fair@basic-none@vecs0.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-iclb: [FAIL][155] ([i915#2842]) -> [PASS][156]
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@gem_exec_fair@basic-pace@rcs0.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: [SKIP][157] ([fdo#109271]) -> [PASS][158]
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs0.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [DMESG-WARN][159] ([i915#180]) -> [PASS][160] +2 similar issues
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl7/igt@gem_workarounds@suspend-resume-context.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_pm_dc@dc9-dpms:
- {shard-tglu}: [SKIP][161] ([i915#4281]) -> [PASS][162]
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglu-6/igt@i915_pm_dc@dc9-dpms.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglu-2/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-kbl: [DMESG-FAIL][163] ([i915#5334]) -> [PASS][164]
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl1/igt@i915_selftest@live@gt_heartbeat.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- shard-tglb: [DMESG-WARN][165] ([i915#5591]) -> [PASS][166]
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglb5/igt@i915_selftest@live@hangcheck.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglb6/igt@i915_selftest@live@hangcheck.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [FAIL][167] ([i915#2346] / [i915#533]) -> [PASS][168]
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2:
- shard-glk: [FAIL][169] ([i915#2122]) -> [PASS][170]
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-glk3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1:
- shard-apl: [FAIL][171] ([i915#79]) -> [PASS][172]
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [FAIL][173] ([i915#2122]) -> [PASS][174]
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][175] ([i915#180]) -> [PASS][176] +5 similar issues
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-skl: [INCOMPLETE][177] ([i915#4444] / [i915#4939]) -> [PASS][178]
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: [SKIP][179] ([fdo#109441]) -> [PASS][180] +1 similar issue
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@kms_psr@psr2_sprite_mmap_cpu.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@sysfs_heartbeat_interval@mixed@bcs0:
- shard-skl: [WARN][181] ([i915#4055]) -> [PASS][182]
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/igt@sysfs_heartbeat_interval@mixed@bcs0.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl8/igt@sysfs_heartbeat_interval@mixed@bcs0.html
* igt@sysfs_heartbeat_interval@mixed@vcs0:
- shard-skl: [FAIL][183] ([i915#1731]) -> [PASS][184]
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/igt@sysfs_heartbeat_interval@mixed@vcs0.html
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl8/igt@sysfs_heartbeat_interval@mixed@vcs0.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-contexts:
- shard-iclb: [DMESG-WARN][185] ([i915#5614]) -> [SKIP][186] ([i915#4525]) +1 similar issue
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb1/igt@gem_exec_balancer@parallel-contexts.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-iclb: [SKIP][187] ([i915#4525]) -> [DMESG-WARN][188] ([i915#5614])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@gem_exec_balancer@parallel-keep-submit-fence.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb4/igt@gem_exec_balancer@parallel-keep-submit-fence.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [DMESG-FAIL][189] ([i915#5614]) -> [SKIP][190] ([i915#4525])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@gem_exec_balancer@parallel-ordering.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][191] ([i915#658]) -> [SKIP][192] ([i915#588])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@i915_pm_dc@dc3co-vpb-simulation.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][193] ([i915#2920]) -> [SKIP][194] ([fdo#111068] / [i915#658]) +1 similar issue
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][195], [FAIL][196], [FAIL][197], [FAIL][198], [FAIL][199], [FAIL][200], [FAIL][201], [FAIL][202], [FAIL][203], [FAIL][204], [FAIL][205], [FAIL][206]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][207], [FAIL][208], [FAIL][209], [FAIL][210], [FAIL][211], [FAIL][212], [FAIL][213], [FAIL][214], [FAIL][215], [FAIL][216]) ([i915#3002] / [i915#4312] / [i915#5257])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl6/igt@runner@aborted.html
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl4/igt@runner@aborted.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@runner@aborted.html
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl1/igt@runner@aborted.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl4/igt@runner@aborted.html
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@runner@aborted.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@runner@aborted.html
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl1/igt@runner@aborted.html
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@runner@aborted.html
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@runner@aborted.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl1/igt@runner@aborted.html
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl3/igt@runner@aborted.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@runner@aborted.html
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@runner@aborted.html
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@runner@aborted.html
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl4/igt@runner@aborted.html
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@runner@aborted.html
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl1/igt@runner@aborted.html
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl3/igt@runner@aborted.html
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl1/igt@runner@aborted.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl1/igt@runner@aborted.html
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl3/igt@runner@aborted.html
- shard-apl: ([FAIL][217], [FAIL][218], [FAIL][219], [FAIL][220], [FAIL][221], [FAIL][222], [FAIL][223], [FAIL][224]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][225], [FAIL][226], [FAIL][227], [FAIL][228], [FAIL][229]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl4/igt@runner@aborted.html
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl8/igt@runner@aborted.html
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl4/igt@runner@aborted.html
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl7/igt@runner@aborted.html
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl2/igt@runner@aborted.html
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl6/igt@runner@aborted.html
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl6/igt@runner@aborted.html
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl3/igt@runner@aborted.html
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl2/igt@runner@aborted.html
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl4/igt@runner@aborted.html
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl8/igt@runner@aborted.html
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl4/igt@runner@aborted.html
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#110892]: https://bugs.freedesktop.org/show_bug.cgi?id=110892
[fdo#111066]: https://bugs.freedesktop.org/show_bug.cgi?id=111066
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4055]: https://gitlab.freedesktop.org/drm/intel/issues/4055
[i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4272]: https://gitlab.freedesktop.org/drm/intel/issues/4272
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4444]: https://gitlab.freedesktop.org/drm/intel/issues/4444
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4911]: https://gitlab.freedesktop.org/drm/intel/issues/4911
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5032]: https://gitlab.freedesktop.org/drm/intel/issues/5032
[i915#5076]: https://gitlab.freedesktop.org/drm/intel/issues/5076
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5183]: https://gitlab.freedesktop.org/drm/intel/issues/5183
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
[i915#5614]: https://gitlab.freedesktop.org/drm/intel/issues/5614
[i915#5776]: https://gitlab.freedesktop.org/drm/intel/issues/5776
[i915#5800]: https://gitlab.freedesktop.org/drm/intel/issues/5800
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_11666 -> Patchwork_103244v4
CI-20190529: 20190529
CI_DRM_11666: 73bb9fa49db3df15c6024a743a48139b1fcdcf7e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6476: 08aa9296163b94cf4c529fc890ae3e90e21c3cdb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103244v4: 73bb9fa49db3df15c6024a743a48139b1fcdcf7e @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/index.html
[-- Attachment #2: Type: text/html, Size: 57312 bytes --]
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: SSEU handling updates (rev4)
2022-05-18 0:34 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2022-05-18 3:24 ` Matt Roper
2022-05-18 16:51 ` Vudum, Lakshminarayana
0 siblings, 1 reply; 43+ messages in thread
From: Matt Roper @ 2022-05-18 3:24 UTC (permalink / raw)
To: intel-gfx; +Cc: Vudum, Lakshminarayana
On Wed, May 18, 2022 at 12:34:11AM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: i915: SSEU handling updates (rev4)
> URL : https://patchwork.freedesktop.org/series/103244/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11666_full -> Patchwork_103244v4_full
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_103244v4_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_103244v4_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Participating hosts (11 -> 11)
> ------------------------------
>
> No changes in participating hosts
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_103244v4_full:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@kms_flip@flip-vs-panning-interruptible@c-edp1:
> - shard-iclb: [PASS][1] -> [DMESG-WARN][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb3/igt@kms_flip@flip-vs-panning-interruptible@c-edp1.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb8/igt@kms_flip@flip-vs-panning-interruptible@c-edp1.html
<3> [607.307030] rcu: INFO: rcu_preempt detected stalls on CPUs/tasks:
<3> [607.307121] rcu: 3-...!: (159 GPs behind) idle=834/0/0x0 softirq=27765/27765 fqs=1 (false positive?)
<3> [607.307825] rcu: 7-...!: (172 GPs behind) idle=abc/0/0x0 softirq=23642/23643 fqs=1 (false positive?)
<4> [607.307934] (detected by 0, t=65002 jiffies, g=64137, q=5840)
<6> [607.307942] Sending NMI from CPU 0 to CPUs 3:
<4> [607.308032] NMI backtrace for cpu 3 skipped: idling at intel_idle+0x67/0xc0
<6> [607.308950] Sending NMI from CPU 0 to CPUs 7:
<4> [607.309045] NMI backtrace for cpu 7 skipped: idling at intel_idle+0x67/0xc0
<3> [607.309957] rcu: rcu_preempt kthread timer wakeup didn't happen for 64995 jiffies! g64137 f0x0 RCU_GP_WAIT_FQS(5) ->state=0x402
<3> [607.310053] rcu: Possible timer handling issue on cpu=3 timer-softirq=16787
<3> [607.310110] rcu: rcu_preempt kthread starved for 64998 jiffies! g64137 f0x0 RCU_GP_WAIT_FQS(5) ->state=0x402 ->cpu=3
<3> [607.310195] rcu: Unless rcu_preempt kthread gets sufficient CPU time, OOM is now expected behavior.
<3> [607.310267] rcu: RCU grace-period kthread stack dump:
<6> [607.310310] task:rcu_preempt state:I stack:14472 pid: 13 ppid: 2 flags:0x00004000
<6> [607.310326] Call Trace:
<6> [607.310330] <TASK>
<6> [607.310339] __schedule+0x483/0xb50
<6> [607.310353] ? schedule_timeout+0x1b9/0x2e0
<6> [607.310367] schedule+0x3f/0xa0
<6> [607.310376] schedule_timeout+0x1be/0x2e0
<6> [607.310386] ? del_timer_sync+0xb0/0xb0
<6> [607.310398] ? 0xffffffff81000000
<6> [607.310408] ? rcu_gp_cleanup+0x440/0x440
<6> [607.310413] rcu_gp_fqs_loop+0x273/0x3b0
<6> [607.310427] rcu_gp_kthread+0xb8/0x120
<6> [607.310436] kthread+0xed/0x120
<6> [607.310443] ? kthread_complete_and_exit+0x20/0x20
<6> [607.310452] ret_from_fork+0x1f/0x30
<6> [607.310478] </TASK>
<3> [607.310481] rcu: Stack dump where RCU GP kthread last ran:
<6> [607.310527] Sending NMI from CPU 0 to CPUs 3:
<4> [607.310602] NMI backtrace for cpu 3 skipped: idling at intel_idle+0x67/0xc0
It's not clear what this is from (no indication it's even related to the
graphics driver). Definitely not the kind of thing that the SSEU rework
in this series could cause to happen during a display test.
Matt
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_103244v4_full that come from known issues:
>
> ### CI changes ###
>
> #### Possible fixes ####
>
> * boot:
> - shard-skl: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [FAIL][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26]) ([i915#5032]) -> ([PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49])
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl9/boot.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl9/boot.html
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl9/boot.html
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/boot.html
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/boot.html
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/boot.html
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl7/boot.html
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl7/boot.html
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl7/boot.html
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl6/boot.html
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl6/boot.html
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl6/boot.html
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/boot.html
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/boot.html
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/boot.html
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/boot.html
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl3/boot.html
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl3/boot.html
> [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl1/boot.html
> [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl1/boot.html
> [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl1/boot.html
> [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl10/boot.html
> [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl10/boot.html
> [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl10/boot.html
> [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl1/boot.html
> [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl1/boot.html
> [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl1/boot.html
> [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl3/boot.html
> [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl3/boot.html
> [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl4/boot.html
> [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl4/boot.html
> [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/boot.html
> [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/boot.html
> [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/boot.html
> [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl7/boot.html
> [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl7/boot.html
> [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl7/boot.html
> [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl8/boot.html
> [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl8/boot.html
> [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/boot.html
> [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/boot.html
> [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/boot.html
> [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/boot.html
> [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/boot.html
> [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/boot.html
> [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/boot.html
> [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/boot.html
>
>
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@drm_buddy@all@buddy_alloc_smoke:
> - shard-skl: [PASS][50] -> [INCOMPLETE][51] ([i915#5800])
> [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl6/igt@drm_buddy@all@buddy_alloc_smoke.html
> [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl1/igt@drm_buddy@all@buddy_alloc_smoke.html
>
> * igt@gem_create@create-massive:
> - shard-kbl: NOTRUN -> [DMESG-WARN][52] ([i915#4991])
> [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@gem_create@create-massive.html
>
> * igt@gem_exec_balancer@parallel-balancer:
> - shard-iclb: [PASS][53] -> [SKIP][54] ([i915#4525])
> [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb4/igt@gem_exec_balancer@parallel-balancer.html
> [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb5/igt@gem_exec_balancer@parallel-balancer.html
>
> * igt@gem_exec_balancer@parallel-keep-in-fence:
> - shard-kbl: NOTRUN -> [DMESG-WARN][55] ([i915#5076] / [i915#5614])
> [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@gem_exec_balancer@parallel-keep-in-fence.html
>
> * igt@gem_exec_fair@basic-none-share@rcs0:
> - shard-tglb: [PASS][56] -> [FAIL][57] ([i915#2842])
> [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglb3/igt@gem_exec_fair@basic-none-share@rcs0.html
> [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglb8/igt@gem_exec_fair@basic-none-share@rcs0.html
>
> * igt@gem_exec_fair@basic-none@vcs0:
> - shard-kbl: [PASS][58] -> [FAIL][59] ([i915#2842]) +2 similar issues
> [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html
> [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
>
> * igt@gem_exec_fair@basic-pace-share@rcs0:
> - shard-glk: [PASS][60] -> [FAIL][61] ([i915#2842]) +1 similar issue
> [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
> [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
>
> * igt@gem_exec_fair@basic-pace@vcs1:
> - shard-iclb: NOTRUN -> [FAIL][62] ([i915#2842]) +2 similar issues
> [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html
>
> * igt@gem_exec_fair@basic-throttle@rcs0:
> - shard-iclb: NOTRUN -> [FAIL][63] ([i915#2849])
> [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
>
> * igt@gem_exec_params@secure-non-root:
> - shard-iclb: NOTRUN -> [SKIP][64] ([fdo#112283])
> [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@gem_exec_params@secure-non-root.html
>
> * igt@gem_huc_copy@huc-copy:
> - shard-tglb: [PASS][65] -> [SKIP][66] ([i915#2190])
> [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglb5/igt@gem_huc_copy@huc-copy.html
> [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglb6/igt@gem_huc_copy@huc-copy.html
>
> * igt@gem_lmem_swapping@basic:
> - shard-iclb: NOTRUN -> [SKIP][67] ([i915#4613]) +2 similar issues
> [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@gem_lmem_swapping@basic.html
> - shard-apl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#4613]) +1 similar issue
> [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl6/igt@gem_lmem_swapping@basic.html
>
> * igt@gem_lmem_swapping@parallel-random-verify-ccs:
> - shard-skl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#4613]) +1 similar issue
> [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
>
> * igt@gem_lmem_swapping@verify-random:
> - shard-kbl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#4613])
> [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@gem_lmem_swapping@verify-random.html
>
> * igt@gem_render_copy@y-tiled-to-vebox-linear:
> - shard-iclb: NOTRUN -> [SKIP][71] ([i915#768]) +1 similar issue
> [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@gem_render_copy@y-tiled-to-vebox-linear.html
>
> * igt@gem_softpin@evict-single-offset:
> - shard-kbl: NOTRUN -> [FAIL][72] ([i915#4171])
> [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@gem_softpin@evict-single-offset.html
>
> * igt@gem_userptr_blits@dmabuf-sync:
> - shard-apl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#3323])
> [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@gem_userptr_blits@dmabuf-sync.html
>
> * igt@gem_userptr_blits@vma-merge:
> - shard-skl: NOTRUN -> [FAIL][74] ([i915#3318])
> [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/igt@gem_userptr_blits@vma-merge.html
>
> * igt@gen9_exec_parse@bb-chained:
> - shard-iclb: NOTRUN -> [SKIP][75] ([i915#2856]) +1 similar issue
> [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@gen9_exec_parse@bb-chained.html
>
> * igt@i915_pm_rpm@modeset-non-lpsp:
> - shard-iclb: NOTRUN -> [SKIP][76] ([fdo#110892])
> [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@i915_pm_rpm@modeset-non-lpsp.html
>
> * igt@i915_pm_sseu@full-enable:
> - shard-iclb: NOTRUN -> [SKIP][77] ([i915#4387])
> [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@i915_pm_sseu@full-enable.html
>
> * igt@i915_selftest@mock@requests:
> - shard-skl: [PASS][78] -> [INCOMPLETE][79] ([i915#5183])
> [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/igt@i915_selftest@mock@requests.html
> [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl8/igt@i915_selftest@mock@requests.html
>
> * igt@i915_suspend@forcewake:
> - shard-apl: [PASS][80] -> [DMESG-WARN][81] ([i915#180])
> [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl6/igt@i915_suspend@forcewake.html
> [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl4/igt@i915_suspend@forcewake.html
>
> * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
> - shard-iclb: NOTRUN -> [SKIP][82] ([i915#3826])
> [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
>
> * igt@kms_async_flips@crc:
> - shard-skl: NOTRUN -> [FAIL][83] ([i915#4272])
> [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_async_flips@crc.html
>
> * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
> - shard-iclb: NOTRUN -> [SKIP][84] ([i915#5286]) +1 similar issue
> [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
>
> * igt@kms_big_fb@x-tiled-16bpp-rotate-270:
> - shard-iclb: NOTRUN -> [SKIP][85] ([fdo#110725] / [fdo#111614]) +2 similar issues
> [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
>
> * igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
> - shard-iclb: NOTRUN -> [SKIP][86] ([fdo#110723])
> [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html
>
> * igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs:
> - shard-apl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#3886]) +5 similar issues
> [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl6/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs.html
>
> * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs:
> - shard-skl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#3886]) +1 similar issue
> [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs.html
>
> * igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
> - shard-kbl: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#3886])
> [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
>
> * igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs:
> - shard-iclb: NOTRUN -> [SKIP][90] ([fdo#109278]) +26 similar issues
> [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs.html
>
> * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
> - shard-iclb: NOTRUN -> [SKIP][91] ([fdo#109278] / [i915#3886]) +2 similar issues
> [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
>
> * igt@kms_chamelium@dp-crc-multiple:
> - shard-skl: NOTRUN -> [SKIP][92] ([fdo#109271] / [fdo#111827]) +12 similar issues
> [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/igt@kms_chamelium@dp-crc-multiple.html
>
> * igt@kms_chamelium@dp-hpd-for-each-pipe:
> - shard-apl: NOTRUN -> [SKIP][93] ([fdo#109271] / [fdo#111827]) +4 similar issues
> [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl3/igt@kms_chamelium@dp-hpd-for-each-pipe.html
>
> * igt@kms_color_chamelium@pipe-a-ctm-red-to-blue:
> - shard-iclb: NOTRUN -> [SKIP][94] ([fdo#109284] / [fdo#111827]) +9 similar issues
> [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_color_chamelium@pipe-a-ctm-red-to-blue.html
>
> * igt@kms_color_chamelium@pipe-c-ctm-limited-range:
> - shard-kbl: NOTRUN -> [SKIP][95] ([fdo#109271] / [fdo#111827])
> [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@kms_color_chamelium@pipe-c-ctm-limited-range.html
>
> * igt@kms_color_chamelium@pipe-d-ctm-0-25:
> - shard-iclb: NOTRUN -> [SKIP][96] ([fdo#109278] / [fdo#109284] / [fdo#111827])
> [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_color_chamelium@pipe-d-ctm-0-25.html
>
> * igt@kms_content_protection@atomic:
> - shard-apl: NOTRUN -> [TIMEOUT][97] ([i915#1319])
> [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl3/igt@kms_content_protection@atomic.html
>
> * igt@kms_content_protection@dp-mst-type-0:
> - shard-iclb: NOTRUN -> [SKIP][98] ([i915#3116])
> [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_content_protection@dp-mst-type-0.html
>
> * igt@kms_content_protection@lic:
> - shard-iclb: NOTRUN -> [SKIP][99] ([fdo#109300] / [fdo#111066])
> [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_content_protection@lic.html
>
> * igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding:
> - shard-iclb: NOTRUN -> [SKIP][100] ([fdo#109278] / [fdo#109279]) +3 similar issues
> [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding.html
>
> * igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen:
> - shard-skl: NOTRUN -> [SKIP][101] ([fdo#109271]) +151 similar issues
> [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen.html
>
> * igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen:
> - shard-kbl: NOTRUN -> [SKIP][102] ([fdo#109271]) +55 similar issues
> [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl1/igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen.html
>
> * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
> - shard-iclb: NOTRUN -> [SKIP][103] ([fdo#109274] / [fdo#109278]) +2 similar issues
> [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
>
> * igt@kms_dp_tiled_display@basic-test-pattern:
> - shard-iclb: NOTRUN -> [SKIP][104] ([i915#426])
> [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_dp_tiled_display@basic-test-pattern.html
>
> * igt@kms_flip@2x-flip-vs-dpms:
> - shard-iclb: NOTRUN -> [SKIP][105] ([fdo#109274]) +5 similar issues
> [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_flip@2x-flip-vs-dpms.html
>
> * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
> - shard-skl: [PASS][106] -> [FAIL][107] ([i915#2122]) +1 similar issue
> [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
> [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
>
> * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
> - shard-glk: [PASS][108] -> [FAIL][109] ([i915#4911])
> [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-glk5/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
> [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
>
> * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
> - shard-iclb: [PASS][110] -> [SKIP][111] ([i915#3701])
> [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
> [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
> - shard-iclb: NOTRUN -> [SKIP][112] ([fdo#109280]) +22 similar issues
> [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html
>
> * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
> - shard-iclb: NOTRUN -> [SKIP][113] ([i915#1839])
> [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
>
> * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
> - shard-kbl: NOTRUN -> [FAIL][114] ([i915#265])
> [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
>
> * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
> - shard-apl: NOTRUN -> [FAIL][115] ([fdo#108145] / [i915#265])
> [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl6/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
>
> * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
> - shard-skl: NOTRUN -> [FAIL][116] ([fdo#108145] / [i915#265]) +1 similar issue
> [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html
>
> * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
> - shard-skl: [PASS][117] -> [FAIL][118] ([fdo#108145] / [i915#265]) +1 similar issue
> [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
> [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>
> * igt@kms_plane_lowres@pipe-a-tiling-x:
> - shard-iclb: NOTRUN -> [SKIP][119] ([i915#3536]) +1 similar issue
> [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-x.html
>
> * igt@kms_plane_scaling@downscale-with-modifier-factor-0-25@pipe-a-edp-1-downscale-with-modifier:
> - shard-skl: NOTRUN -> [SKIP][120] ([fdo#109271] / [i915#5176]) +2 similar issues
> [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_plane_scaling@downscale-with-modifier-factor-0-25@pipe-a-edp-1-downscale-with-modifier.html
>
> * igt@kms_plane_scaling@invalid-num-scalers@pipe-a-edp-1-invalid-num-scalers:
> - shard-skl: NOTRUN -> [SKIP][121] ([fdo#109271] / [i915#5776]) +2 similar issues
> [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/igt@kms_plane_scaling@invalid-num-scalers@pipe-a-edp-1-invalid-num-scalers.html
>
> * igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale:
> - shard-iclb: [PASS][122] -> [SKIP][123] ([i915#5235]) +2 similar issues
> [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html
> [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html
>
> * igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
> - shard-apl: NOTRUN -> [SKIP][124] ([fdo#109271] / [i915#658]) +1 similar issue
> [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
>
> * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
> - shard-iclb: NOTRUN -> [SKIP][125] ([fdo#111068] / [i915#658])
> [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
>
> * igt@kms_psr2_su@page_flip-nv12:
> - shard-iclb: NOTRUN -> [SKIP][126] ([fdo#109642] / [fdo#111068] / [i915#658])
> [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_psr2_su@page_flip-nv12.html
>
> * igt@kms_psr2_su@page_flip-p010:
> - shard-kbl: NOTRUN -> [SKIP][127] ([fdo#109271] / [i915#658]) +1 similar issue
> [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@kms_psr2_su@page_flip-p010.html
>
> * igt@kms_psr2_su@page_flip-xrgb8888:
> - shard-skl: NOTRUN -> [SKIP][128] ([fdo#109271] / [i915#658]) +1 similar issue
> [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_psr2_su@page_flip-xrgb8888.html
>
> * igt@kms_psr@psr2_sprite_plane_move:
> - shard-iclb: NOTRUN -> [SKIP][129] ([fdo#109441]) +2 similar issues
> [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html
>
> * igt@kms_psr@psr2_suspend:
> - shard-iclb: [PASS][130] -> [SKIP][131] ([fdo#109441]) +1 similar issue
> [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb2/igt@kms_psr@psr2_suspend.html
> [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_psr@psr2_suspend.html
>
> * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
> - shard-skl: [PASS][132] -> [DMESG-WARN][133] ([i915#1982])
> [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
> [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
> - shard-iclb: [PASS][134] -> [SKIP][135] ([i915#5519])
> [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
> [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
>
> * igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
> - shard-apl: NOTRUN -> [SKIP][136] ([fdo#109271]) +118 similar issues
> [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
>
> * igt@kms_sysfs_edid_timing:
> - shard-apl: NOTRUN -> [FAIL][137] ([IGT#2])
> [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl6/igt@kms_sysfs_edid_timing.html
>
> * igt@kms_vblank@pipe-d-wait-idle:
> - shard-apl: NOTRUN -> [SKIP][138] ([fdo#109271] / [i915#533]) +3 similar issues
> [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@kms_vblank@pipe-d-wait-idle.html
>
> * igt@kms_vrr@flip-basic:
> - shard-iclb: NOTRUN -> [SKIP][139] ([i915#3555]) +1 similar issue
> [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_vrr@flip-basic.html
>
> * igt@nouveau_crc@pipe-a-source-rg:
> - shard-iclb: NOTRUN -> [SKIP][140] ([i915#2530]) +1 similar issue
> [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@nouveau_crc@pipe-a-source-rg.html
>
> * igt@perf@polling:
> - shard-skl: [PASS][141] -> [FAIL][142] ([i915#1542])
> [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl9/igt@perf@polling.html
> [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl3/igt@perf@polling.html
>
> * igt@prime_nv_pcopy@test3_3:
> - shard-iclb: NOTRUN -> [SKIP][143] ([fdo#109291]) +3 similar issues
> [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@prime_nv_pcopy@test3_3.html
>
> * igt@sysfs_clients@fair-0:
> - shard-skl: NOTRUN -> [SKIP][144] ([fdo#109271] / [i915#2994]) +3 similar issues
> [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/igt@sysfs_clients@fair-0.html
>
> * igt@sysfs_clients@fair-3:
> - shard-apl: NOTRUN -> [SKIP][145] ([fdo#109271] / [i915#2994])
> [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl3/igt@sysfs_clients@fair-3.html
>
> * igt@sysfs_clients@split-10:
> - shard-iclb: NOTRUN -> [SKIP][146] ([i915#2994]) +2 similar issues
> [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@sysfs_clients@split-10.html
>
>
> #### Possible fixes ####
>
> * igt@gem_eio@in-flight-10ms:
> - shard-tglb: [TIMEOUT][147] ([i915#3063]) -> [PASS][148]
> [147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglb2/igt@gem_eio@in-flight-10ms.html
> [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglb1/igt@gem_eio@in-flight-10ms.html
>
> * igt@gem_exec_fair@basic-none-share@rcs0:
> - {shard-tglu}: [FAIL][149] ([i915#2842]) -> [PASS][150]
> [149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglu-6/igt@gem_exec_fair@basic-none-share@rcs0.html
> [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglu-2/igt@gem_exec_fair@basic-none-share@rcs0.html
>
> * igt@gem_exec_fair@basic-none@vcs0:
> - shard-apl: [FAIL][151] ([i915#2842]) -> [PASS][152]
> [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl4/igt@gem_exec_fair@basic-none@vcs0.html
> [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl8/igt@gem_exec_fair@basic-none@vcs0.html
>
> * igt@gem_exec_fair@basic-none@vecs0:
> - shard-kbl: [FAIL][153] ([i915#2842]) -> [PASS][154]
> [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl3/igt@gem_exec_fair@basic-none@vecs0.html
> [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@gem_exec_fair@basic-none@vecs0.html
>
> * igt@gem_exec_fair@basic-pace@rcs0:
> - shard-iclb: [FAIL][155] ([i915#2842]) -> [PASS][156]
> [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@gem_exec_fair@basic-pace@rcs0.html
> [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@gem_exec_fair@basic-pace@rcs0.html
>
> * igt@gem_exec_fair@basic-pace@vcs0:
> - shard-kbl: [SKIP][157] ([fdo#109271]) -> [PASS][158]
> [157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs0.html
> [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs0.html
>
> * igt@gem_workarounds@suspend-resume-context:
> - shard-apl: [DMESG-WARN][159] ([i915#180]) -> [PASS][160] +2 similar issues
> [159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl7/igt@gem_workarounds@suspend-resume-context.html
> [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@gem_workarounds@suspend-resume-context.html
>
> * igt@i915_pm_dc@dc9-dpms:
> - {shard-tglu}: [SKIP][161] ([i915#4281]) -> [PASS][162]
> [161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglu-6/igt@i915_pm_dc@dc9-dpms.html
> [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglu-2/igt@i915_pm_dc@dc9-dpms.html
>
> * igt@i915_selftest@live@gt_heartbeat:
> - shard-kbl: [DMESG-FAIL][163] ([i915#5334]) -> [PASS][164]
> [163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl1/igt@i915_selftest@live@gt_heartbeat.html
> [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@i915_selftest@live@gt_heartbeat.html
>
> * igt@i915_selftest@live@hangcheck:
> - shard-tglb: [DMESG-WARN][165] ([i915#5591]) -> [PASS][166]
> [165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglb5/igt@i915_selftest@live@hangcheck.html
> [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglb6/igt@i915_selftest@live@hangcheck.html
>
> * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
> - shard-glk: [FAIL][167] ([i915#2346] / [i915#533]) -> [PASS][168]
> [167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
> [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
>
> * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2:
> - shard-glk: [FAIL][169] ([i915#2122]) -> [PASS][170]
> [169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html
> [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-glk3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html
>
> * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1:
> - shard-apl: [FAIL][171] ([i915#79]) -> [PASS][172]
> [171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
> [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
>
> * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
> - shard-skl: [FAIL][173] ([i915#2122]) -> [PASS][174]
> [173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
> [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
>
> * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
> - shard-kbl: [DMESG-WARN][175] ([i915#180]) -> [PASS][176] +5 similar issues
> [175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
> [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
>
> * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
> - shard-skl: [INCOMPLETE][177] ([i915#4444] / [i915#4939]) -> [PASS][178]
> [177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
> [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
>
> * igt@kms_psr@psr2_sprite_mmap_cpu:
> - shard-iclb: [SKIP][179] ([fdo#109441]) -> [PASS][180] +1 similar issue
> [179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@kms_psr@psr2_sprite_mmap_cpu.html
> [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html
>
> * igt@sysfs_heartbeat_interval@mixed@bcs0:
> - shard-skl: [WARN][181] ([i915#4055]) -> [PASS][182]
> [181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/igt@sysfs_heartbeat_interval@mixed@bcs0.html
> [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl8/igt@sysfs_heartbeat_interval@mixed@bcs0.html
>
> * igt@sysfs_heartbeat_interval@mixed@vcs0:
> - shard-skl: [FAIL][183] ([i915#1731]) -> [PASS][184]
> [183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/igt@sysfs_heartbeat_interval@mixed@vcs0.html
> [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl8/igt@sysfs_heartbeat_interval@mixed@vcs0.html
>
>
> #### Warnings ####
>
> * igt@gem_exec_balancer@parallel-contexts:
> - shard-iclb: [DMESG-WARN][185] ([i915#5614]) -> [SKIP][186] ([i915#4525]) +1 similar issue
> [185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb1/igt@gem_exec_balancer@parallel-contexts.html
> [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@gem_exec_balancer@parallel-contexts.html
>
> * igt@gem_exec_balancer@parallel-keep-submit-fence:
> - shard-iclb: [SKIP][187] ([i915#4525]) -> [DMESG-WARN][188] ([i915#5614])
> [187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@gem_exec_balancer@parallel-keep-submit-fence.html
> [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb4/igt@gem_exec_balancer@parallel-keep-submit-fence.html
>
> * igt@gem_exec_balancer@parallel-ordering:
> - shard-iclb: [DMESG-FAIL][189] ([i915#5614]) -> [SKIP][190] ([i915#4525])
> [189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html
> [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@gem_exec_balancer@parallel-ordering.html
>
> * igt@i915_pm_dc@dc3co-vpb-simulation:
> - shard-iclb: [SKIP][191] ([i915#658]) -> [SKIP][192] ([i915#588])
> [191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@i915_pm_dc@dc3co-vpb-simulation.html
> [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
>
> * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
> - shard-iclb: [SKIP][193] ([i915#2920]) -> [SKIP][194] ([fdo#111068] / [i915#658]) +1 similar issue
> [193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
> [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
>
> * igt@runner@aborted:
> - shard-kbl: ([FAIL][195], [FAIL][196], [FAIL][197], [FAIL][198], [FAIL][199], [FAIL][200], [FAIL][201], [FAIL][202], [FAIL][203], [FAIL][204], [FAIL][205], [FAIL][206]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][207], [FAIL][208], [FAIL][209], [FAIL][210], [FAIL][211], [FAIL][212], [FAIL][213], [FAIL][214], [FAIL][215], [FAIL][216]) ([i915#3002] / [i915#4312] / [i915#5257])
> [195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl6/igt@runner@aborted.html
> [196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl4/igt@runner@aborted.html
> [197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@runner@aborted.html
> [198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl1/igt@runner@aborted.html
> [199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl4/igt@runner@aborted.html
> [200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@runner@aborted.html
> [201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@runner@aborted.html
> [202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl1/igt@runner@aborted.html
> [203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@runner@aborted.html
> [204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@runner@aborted.html
> [205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl1/igt@runner@aborted.html
> [206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl3/igt@runner@aborted.html
> [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@runner@aborted.html
> [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@runner@aborted.html
> [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@runner@aborted.html
> [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl4/igt@runner@aborted.html
> [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@runner@aborted.html
> [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl1/igt@runner@aborted.html
> [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl3/igt@runner@aborted.html
> [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl1/igt@runner@aborted.html
> [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl1/igt@runner@aborted.html
> [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl3/igt@runner@aborted.html
> - shard-apl: ([FAIL][217], [FAIL][218], [FAIL][219], [FAIL][220], [FAIL][221], [FAIL][222], [FAIL][223], [FAIL][224]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][225], [FAIL][226], [FAIL][227], [FAIL][228], [FAIL][229]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
> [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl4/igt@runner@aborted.html
> [218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl8/igt@runner@aborted.html
> [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl4/igt@runner@aborted.html
> [220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl7/igt@runner@aborted.html
> [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl2/igt@runner@aborted.html
> [222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl6/igt@runner@aborted.html
> [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl6/igt@runner@aborted.html
> [224]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl3/igt@runner@aborted.html
> [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl2/igt@runner@aborted.html
> [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl4/igt@runner@aborted.html
> [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl8/igt@runner@aborted.html
> [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl4/igt@runner@aborted.html
> [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@runner@aborted.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
> [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
> [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
> [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
> [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
> [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
> [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
> [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
> [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
> [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
> [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
> [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
> [fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
> [fdo#110892]: https://bugs.freedesktop.org/show_bug.cgi?id=110892
> [fdo#111066]: https://bugs.freedesktop.org/show_bug.cgi?id=111066
> [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
> [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
> [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
> [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
> [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
> [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
> [i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
> [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
> [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
> [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
> [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
> [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
> [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
> [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
> [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
> [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
> [i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
> [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
> [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
> [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
> [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
> [i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
> [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
> [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
> [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
> [i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
> [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
> [i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
> [i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778
> [i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
> [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
> [i915#4055]: https://gitlab.freedesktop.org/drm/intel/issues/4055
> [i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
> [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
> [i915#4272]: https://gitlab.freedesktop.org/drm/intel/issues/4272
> [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
> [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
> [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
> [i915#4444]: https://gitlab.freedesktop.org/drm/intel/issues/4444
> [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
> [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
> [i915#4911]: https://gitlab.freedesktop.org/drm/intel/issues/4911
> [i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
> [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
> [i915#5032]: https://gitlab.freedesktop.org/drm/intel/issues/5032
> [i915#5076]: https://gitlab.freedesktop.org/drm/intel/issues/5076
> [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
> [i915#5183]: https://gitlab.freedesktop.org/drm/intel/issues/5183
> [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
> [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
> [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
> [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
> [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
> [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
> [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
> [i915#5614]: https://gitlab.freedesktop.org/drm/intel/issues/5614
> [i915#5776]: https://gitlab.freedesktop.org/drm/intel/issues/5776
> [i915#5800]: https://gitlab.freedesktop.org/drm/intel/issues/5800
> [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
> [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
> [i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
> [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_11666 -> Patchwork_103244v4
>
> CI-20190529: 20190529
> CI_DRM_11666: 73bb9fa49db3df15c6024a743a48139b1fcdcf7e @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6476: 08aa9296163b94cf4c529fc890ae3e90e21c3cdb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_103244v4: 73bb9fa49db3df15c6024a743a48139b1fcdcf7e @ git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 43+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for i915: SSEU handling updates (rev4)
2022-05-17 3:19 ` [Intel-gfx] " Matt Roper
` (15 preceding siblings ...)
(?)
@ 2022-05-18 15:55 ` Patchwork
-1 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2022-05-18 15:55 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 58289 bytes --]
== Series Details ==
Series: i915: SSEU handling updates (rev4)
URL : https://patchwork.freedesktop.org/series/103244/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11666_full -> Patchwork_103244v4_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (11 -> 13)
------------------------------
Additional (2): shard-rkl shard-dg1
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_103244v4_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_schedule@wide@vcs1:
- {shard-dg1}: NOTRUN -> [DMESG-WARN][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-dg1-13/igt@gem_exec_schedule@wide@vcs1.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25:
- {shard-rkl}: NOTRUN -> [INCOMPLETE][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-rkl-5/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25.html
* igt@kms_vblank@pipe-b-wait-idle-hang:
- {shard-dg1}: NOTRUN -> [SKIP][3] +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-dg1-15/igt@kms_vblank@pipe-b-wait-idle-hang.html
New tests
---------
New tests have been introduced between CI_DRM_11666_full and Patchwork_103244v4_full:
### New IGT tests (4) ###
* igt@kms_plane_scaling@downscale-with-modifier-factor-0-75@pipe-a-hdmi-a-3-downscale-with-modifier:
- Statuses : 1 pass(s)
- Exec time: [0.64] s
* igt@kms_plane_scaling@downscale-with-modifier-factor-0-75@pipe-b-hdmi-a-3-downscale-with-modifier:
- Statuses : 1 pass(s)
- Exec time: [0.64] s
* igt@kms_plane_scaling@downscale-with-modifier-factor-0-75@pipe-c-hdmi-a-3-downscale-with-modifier:
- Statuses : 1 pass(s)
- Exec time: [0.59] s
* igt@kms_plane_scaling@downscale-with-modifier-factor-0-75@pipe-d-hdmi-a-3-downscale-with-modifier:
- Statuses : 1 pass(s)
- Exec time: [0.60] s
Known issues
------------
Here are the changes found in Patchwork_103244v4_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-skl: ([PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [FAIL][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27]) ([i915#5032]) -> ([PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl9/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl6/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl6/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl3/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl3/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl1/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl1/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl1/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl10/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl10/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl10/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl9/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl9/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl7/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl7/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl7/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl6/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl8/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl8/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl7/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl7/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl7/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl4/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl4/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl3/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl3/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl1/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl1/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl1/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/boot.html
### IGT changes ###
#### Issues hit ####
* igt@drm_buddy@all@buddy_alloc_smoke:
- shard-skl: [PASS][51] -> [INCOMPLETE][52] ([i915#5800])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl6/igt@drm_buddy@all@buddy_alloc_smoke.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl1/igt@drm_buddy@all@buddy_alloc_smoke.html
* igt@gem_create@create-massive:
- shard-kbl: NOTRUN -> [DMESG-WARN][53] ([i915#4991])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@gem_create@create-massive.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [PASS][54] -> [SKIP][55] ([i915#4525])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb4/igt@gem_exec_balancer@parallel-balancer.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb5/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-kbl: NOTRUN -> [DMESG-WARN][56] ([i915#5076] / [i915#5614])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][57] -> [FAIL][58] ([i915#2842])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglb3/igt@gem_exec_fair@basic-none-share@rcs0.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglb8/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][59] -> [FAIL][60] ([i915#2842]) +2 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][61] -> [FAIL][62] ([i915#2842]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][63] ([i915#2842]) +2 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: NOTRUN -> [FAIL][64] ([i915#2849])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_params@secure-non-root:
- shard-iclb: NOTRUN -> [SKIP][65] ([fdo#112283])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@gem_exec_params@secure-non-root.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][66] -> [SKIP][67] ([i915#2190])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglb5/igt@gem_huc_copy@huc-copy.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- shard-iclb: NOTRUN -> [SKIP][68] ([i915#4613]) +2 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@gem_lmem_swapping@basic.html
- shard-apl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#4613]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl6/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-skl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#4613]) +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_lmem_swapping@verify-random:
- shard-kbl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#4613])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@gem_lmem_swapping@verify-random.html
* igt@gem_render_copy@y-tiled-to-vebox-linear:
- shard-iclb: NOTRUN -> [SKIP][72] ([i915#768]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@gem_render_copy@y-tiled-to-vebox-linear.html
* igt@gem_softpin@evict-single-offset:
- shard-kbl: NOTRUN -> [FAIL][73] ([i915#4171])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@gem_softpin@evict-single-offset.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-apl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#3323])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@vma-merge:
- shard-skl: NOTRUN -> [FAIL][75] ([i915#3318])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@bb-chained:
- shard-iclb: NOTRUN -> [SKIP][76] ([i915#2856]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@gen9_exec_parse@bb-chained.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- shard-iclb: NOTRUN -> [SKIP][77] ([fdo#110892])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@i915_pm_rpm@modeset-non-lpsp.html
* igt@i915_pm_sseu@full-enable:
- shard-iclb: NOTRUN -> [SKIP][78] ([i915#4387])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@i915_pm_sseu@full-enable.html
* igt@i915_selftest@mock@requests:
- shard-skl: [PASS][79] -> [INCOMPLETE][80] ([i915#5183])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/igt@i915_selftest@mock@requests.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl8/igt@i915_selftest@mock@requests.html
* igt@i915_suspend@forcewake:
- shard-apl: [PASS][81] -> [DMESG-WARN][82] ([i915#180])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl6/igt@i915_suspend@forcewake.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl4/igt@i915_suspend@forcewake.html
* igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
- shard-iclb: NOTRUN -> [SKIP][83] ([i915#3826])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
* igt@kms_async_flips@crc:
- shard-skl: NOTRUN -> [FAIL][84] ([i915#4272])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_async_flips@crc.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-iclb: NOTRUN -> [SKIP][85] ([i915#5286]) +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][86] ([fdo#110725] / [fdo#111614]) +2 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][87] ([fdo#110723])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html
* igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#3886]) +5 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl6/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#3886]) +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#3886])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs:
- shard-iclb: NOTRUN -> [SKIP][91] ([fdo#109278]) +26 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][92] ([fdo#109278] / [i915#3886]) +2 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@dp-crc-multiple:
- shard-skl: NOTRUN -> [SKIP][93] ([fdo#109271] / [fdo#111827]) +12 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/igt@kms_chamelium@dp-crc-multiple.html
* igt@kms_chamelium@dp-hpd-for-each-pipe:
- shard-apl: NOTRUN -> [SKIP][94] ([fdo#109271] / [fdo#111827]) +4 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl3/igt@kms_chamelium@dp-hpd-for-each-pipe.html
* igt@kms_color_chamelium@pipe-a-ctm-red-to-blue:
- shard-iclb: NOTRUN -> [SKIP][95] ([fdo#109284] / [fdo#111827]) +9 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_color_chamelium@pipe-a-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-c-ctm-limited-range:
- shard-kbl: NOTRUN -> [SKIP][96] ([fdo#109271] / [fdo#111827])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@kms_color_chamelium@pipe-c-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-d-ctm-0-25:
- shard-iclb: NOTRUN -> [SKIP][97] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_color_chamelium@pipe-d-ctm-0-25.html
* igt@kms_content_protection@atomic:
- shard-apl: NOTRUN -> [TIMEOUT][98] ([i915#1319])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl3/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-iclb: NOTRUN -> [SKIP][99] ([i915#3116])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@lic:
- shard-iclb: NOTRUN -> [SKIP][100] ([fdo#109300] / [fdo#111066])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_content_protection@lic.html
* igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding:
- shard-iclb: NOTRUN -> [SKIP][101] ([fdo#109278] / [fdo#109279]) +3 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen:
- shard-skl: NOTRUN -> [SKIP][102] ([fdo#109271]) +151 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen:
- shard-kbl: NOTRUN -> [SKIP][103] ([fdo#109271]) +55 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl1/igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
- shard-iclb: NOTRUN -> [SKIP][104] ([fdo#109274] / [fdo#109278]) +2 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_dp_tiled_display@basic-test-pattern:
- shard-iclb: NOTRUN -> [SKIP][105] ([i915#426])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_dp_tiled_display@basic-test-pattern.html
* igt@kms_flip@2x-flip-vs-dpms:
- shard-iclb: NOTRUN -> [SKIP][106] ([fdo#109274]) +5 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_flip@2x-flip-vs-dpms.html
* igt@kms_flip@flip-vs-panning-interruptible@c-edp1:
- shard-iclb: [PASS][107] -> [DMESG-WARN][108] ([i915#6038])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb3/igt@kms_flip@flip-vs-panning-interruptible@c-edp1.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb8/igt@kms_flip@flip-vs-panning-interruptible@c-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [PASS][109] -> [FAIL][110] ([i915#2122]) +1 similar issue
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
- shard-glk: [PASS][111] -> [FAIL][112] ([i915#4911])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-glk5/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
- shard-iclb: [PASS][113] -> [SKIP][114] ([i915#3701])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
- shard-iclb: NOTRUN -> [SKIP][115] ([fdo#109280]) +22 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-iclb: NOTRUN -> [SKIP][116] ([i915#1839])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][117] ([i915#265])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][118] ([fdo#108145] / [i915#265])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl6/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-skl: NOTRUN -> [FAIL][119] ([fdo#108145] / [i915#265]) +1 similar issue
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][120] -> [FAIL][121] ([fdo#108145] / [i915#265]) +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: NOTRUN -> [SKIP][122] ([i915#3536]) +1 similar issue
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_plane_scaling@downscale-with-modifier-factor-0-25@pipe-a-edp-1-downscale-with-modifier:
- shard-skl: NOTRUN -> [SKIP][123] ([fdo#109271] / [i915#5176]) +2 similar issues
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_plane_scaling@downscale-with-modifier-factor-0-25@pipe-a-edp-1-downscale-with-modifier.html
* igt@kms_plane_scaling@invalid-num-scalers@pipe-a-edp-1-invalid-num-scalers:
- shard-skl: NOTRUN -> [SKIP][124] ([fdo#109271] / [i915#5776]) +2 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/igt@kms_plane_scaling@invalid-num-scalers@pipe-a-edp-1-invalid-num-scalers.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale:
- shard-iclb: [PASS][125] -> [SKIP][126] ([i915#5235]) +2 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-apl: NOTRUN -> [SKIP][127] ([fdo#109271] / [i915#658]) +1 similar issue
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-iclb: NOTRUN -> [SKIP][128] ([fdo#111068] / [i915#658])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-iclb: NOTRUN -> [SKIP][129] ([fdo#109642] / [fdo#111068] / [i915#658])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr2_su@page_flip-p010:
- shard-kbl: NOTRUN -> [SKIP][130] ([fdo#109271] / [i915#658]) +1 similar issue
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-skl: NOTRUN -> [SKIP][131] ([fdo#109271] / [i915#658]) +1 similar issue
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: NOTRUN -> [SKIP][132] ([fdo#109441]) +2 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [PASS][133] -> [SKIP][134] ([fdo#109441]) +1 similar issue
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb2/igt@kms_psr@psr2_suspend.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_psr@psr2_suspend.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-skl: [PASS][135] -> [DMESG-WARN][136] ([i915#1982])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
- shard-iclb: [PASS][137] -> [SKIP][138] ([i915#5519])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
- shard-apl: NOTRUN -> [SKIP][139] ([fdo#109271]) +118 similar issues
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][140] ([IGT#2])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl6/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-apl: NOTRUN -> [SKIP][141] ([fdo#109271] / [i915#533]) +3 similar issues
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_vrr@flip-basic:
- shard-iclb: NOTRUN -> [SKIP][142] ([i915#3555]) +1 similar issue
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_vrr@flip-basic.html
* igt@nouveau_crc@pipe-a-source-rg:
- shard-iclb: NOTRUN -> [SKIP][143] ([i915#2530]) +1 similar issue
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@nouveau_crc@pipe-a-source-rg.html
* igt@perf@polling:
- shard-skl: [PASS][144] -> [FAIL][145] ([i915#1542])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl9/igt@perf@polling.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl3/igt@perf@polling.html
* igt@prime_nv_pcopy@test3_3:
- shard-iclb: NOTRUN -> [SKIP][146] ([fdo#109291]) +3 similar issues
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@prime_nv_pcopy@test3_3.html
* igt@sysfs_clients@fair-0:
- shard-skl: NOTRUN -> [SKIP][147] ([fdo#109271] / [i915#2994]) +3 similar issues
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/igt@sysfs_clients@fair-0.html
* igt@sysfs_clients@fair-3:
- shard-apl: NOTRUN -> [SKIP][148] ([fdo#109271] / [i915#2994])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl3/igt@sysfs_clients@fair-3.html
* igt@sysfs_clients@split-10:
- shard-iclb: NOTRUN -> [SKIP][149] ([i915#2994]) +2 similar issues
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@sysfs_clients@split-10.html
#### Possible fixes ####
* igt@gem_eio@in-flight-10ms:
- shard-tglb: [TIMEOUT][150] ([i915#3063]) -> [PASS][151]
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglb2/igt@gem_eio@in-flight-10ms.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglb1/igt@gem_eio@in-flight-10ms.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- {shard-tglu}: [FAIL][152] ([i915#2842]) -> [PASS][153]
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglu-6/igt@gem_exec_fair@basic-none-share@rcs0.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglu-2/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: [FAIL][154] ([i915#2842]) -> [PASS][155]
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl4/igt@gem_exec_fair@basic-none@vcs0.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl8/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-kbl: [FAIL][156] ([i915#2842]) -> [PASS][157]
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl3/igt@gem_exec_fair@basic-none@vecs0.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-iclb: [FAIL][158] ([i915#2842]) -> [PASS][159]
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@gem_exec_fair@basic-pace@rcs0.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: [SKIP][160] ([fdo#109271]) -> [PASS][161]
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs0.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [DMESG-WARN][162] ([i915#180]) -> [PASS][163] +2 similar issues
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl7/igt@gem_workarounds@suspend-resume-context.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_pm_dc@dc9-dpms:
- {shard-tglu}: [SKIP][164] ([i915#4281]) -> [PASS][165]
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglu-6/igt@i915_pm_dc@dc9-dpms.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglu-2/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-kbl: [DMESG-FAIL][166] ([i915#5334]) -> [PASS][167]
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl1/igt@i915_selftest@live@gt_heartbeat.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- shard-tglb: [DMESG-WARN][168] ([i915#5591]) -> [PASS][169]
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglb5/igt@i915_selftest@live@hangcheck.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglb6/igt@i915_selftest@live@hangcheck.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [FAIL][170] ([i915#2346] / [i915#533]) -> [PASS][171]
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2:
- shard-glk: [FAIL][172] ([i915#2122]) -> [PASS][173]
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-glk3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1:
- shard-apl: [FAIL][174] ([i915#79]) -> [PASS][175]
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [FAIL][176] ([i915#2122]) -> [PASS][177]
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][178] ([i915#180]) -> [PASS][179] +5 similar issues
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-skl: [INCOMPLETE][180] ([i915#4444] / [i915#4939]) -> [PASS][181]
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: [SKIP][182] ([fdo#109441]) -> [PASS][183] +1 similar issue
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@kms_psr@psr2_sprite_mmap_cpu.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@sysfs_heartbeat_interval@mixed@bcs0:
- shard-skl: [WARN][184] ([i915#4055]) -> [PASS][185]
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/igt@sysfs_heartbeat_interval@mixed@bcs0.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl8/igt@sysfs_heartbeat_interval@mixed@bcs0.html
* igt@sysfs_heartbeat_interval@mixed@vcs0:
- shard-skl: [FAIL][186] ([i915#1731]) -> [PASS][187]
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/igt@sysfs_heartbeat_interval@mixed@vcs0.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl8/igt@sysfs_heartbeat_interval@mixed@vcs0.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-contexts:
- shard-iclb: [DMESG-WARN][188] ([i915#5614]) -> [SKIP][189] ([i915#4525]) +1 similar issue
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb1/igt@gem_exec_balancer@parallel-contexts.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-iclb: [SKIP][190] ([i915#4525]) -> [DMESG-WARN][191] ([i915#5614])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@gem_exec_balancer@parallel-keep-submit-fence.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb4/igt@gem_exec_balancer@parallel-keep-submit-fence.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [DMESG-FAIL][192] ([i915#5614]) -> [SKIP][193] ([i915#4525])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@gem_exec_balancer@parallel-ordering.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][194] ([i915#658]) -> [SKIP][195] ([i915#588])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@i915_pm_dc@dc3co-vpb-simulation.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][196] ([i915#2920]) -> [SKIP][197] ([fdo#111068] / [i915#658]) +1 similar issue
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][198], [FAIL][199], [FAIL][200], [FAIL][201], [FAIL][202], [FAIL][203], [FAIL][204], [FAIL][205], [FAIL][206], [FAIL][207], [FAIL][208], [FAIL][209]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][210], [FAIL][211], [FAIL][212], [FAIL][213], [FAIL][214], [FAIL][215], [FAIL][216], [FAIL][217], [FAIL][218], [FAIL][219]) ([i915#3002] / [i915#4312] / [i915#5257])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl6/igt@runner@aborted.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl4/igt@runner@aborted.html
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@runner@aborted.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl1/igt@runner@aborted.html
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl4/igt@runner@aborted.html
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@runner@aborted.html
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@runner@aborted.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl1/igt@runner@aborted.html
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@runner@aborted.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@runner@aborted.html
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl1/igt@runner@aborted.html
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl3/igt@runner@aborted.html
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@runner@aborted.html
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@runner@aborted.html
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@runner@aborted.html
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl4/igt@runner@aborted.html
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@runner@aborted.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl1/igt@runner@aborted.html
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl3/igt@runner@aborted.html
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl1/igt@runner@aborted.html
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl1/igt@runner@aborted.html
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl3/igt@runner@aborted.html
- shard-apl: ([FAIL][220], [FAIL][221], [FAIL][222], [FAIL][223], [FAIL][224], [FAIL][225], [FAIL][226], [FAIL][227]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][228], [FAIL][229], [FAIL][230], [FAIL][231], [FAIL][232]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl3/igt@runner@aborted.html
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl6/igt@runner@aborted.html
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl7/igt@runner@aborted.html
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl8/igt@runner@aborted.html
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl4/igt@runner@aborted.html
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl4/igt@runner@aborted.html
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl2/igt@runner@aborted.html
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl6/igt@runner@aborted.html
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl2/igt@runner@aborted.html
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl4/igt@runner@aborted.html
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl8/igt@runner@aborted.html
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl4/igt@runner@aborted.html
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110254]: https://bugs.freedesktop.org/show_bug.cgi?id=110254
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#110892]: https://bugs.freedesktop.org/show_bug.cgi?id=110892
[fdo#111066]: https://bugs.freedesktop.org/show_bug.cgi?id=111066
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3376]: https://gitlab.freedesktop.org/drm/intel/issues/3376
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3464]: https://gitlab.freedesktop.org/drm/intel/issues/3464
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3736]: https://gitlab.freedesktop.org/drm/intel/issues/3736
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3828]: https://gitlab.freedesktop.org/drm/intel/issues/3828
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4032]: https://gitlab.freedesktop.org/drm/intel/issues/4032
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4055]: https://gitlab.freedesktop.org/drm/intel/issues/4055
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4272]: https://gitlab.freedesktop.org/drm/intel/issues/4272
[i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4444]: https://gitlab.freedesktop.org/drm/intel/issues/4444
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4807]: https://gitlab.freedesktop.org/drm/intel/issues/4807
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
[i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
[i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874
[i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4883]: https://gitlab.freedesktop.org/drm/intel/issues/4883
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4904]: https://gitlab.freedesktop.org/drm/intel/issues/4904
[i915#4911]: https://gitlab.freedesktop.org/drm/intel/issues/4911
[i915#4929]: https://gitlab.freedesktop.org/drm/intel/issues/4929
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5032]: https://gitlab.freedesktop.org/drm/intel/issues/5032
[i915#5076]: https://gitlab.freedesktop.org/drm/intel/issues/5076
[i915#5080]: https://gitlab.freedesktop.org/drm/intel/issues/5080
[i915#5098]: https://gitlab.freedesktop.org/drm/intel/issues/5098
[i915#5115]: https://gitlab.freedesktop.org/drm/intel/issues/5115
[i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5183]: https://gitlab.freedesktop.org/drm/intel/issues/5183
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
[i915#5614]: https://gitlab.freedesktop.org/drm/intel/issues/5614
[i915#5691]: https://gitlab.freedesktop.org/drm/intel/issues/5691
[i915#5776]: https://gitlab.freedesktop.org/drm/intel/issues/5776
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5800]: https://gitlab.freedesktop.org/drm/intel/issues/5800
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
[i915#6011]: https://gitlab.freedesktop.org/drm/intel/issues/6011
[i915#6029]: https://gitlab.freedesktop.org/drm/intel/issues/6029
[i915#6038]: https://gitlab.freedesktop.org/drm/intel/issues/6038
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_11666 -> Patchwork_103244v4
CI-20190529: 20190529
CI_DRM_11666: 73bb9fa49db3df15c6024a743a48139b1fcdcf7e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6476: 08aa9296163b94cf4c529fc890ae3e90e21c3cdb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103244v4: 73bb9fa49db3df15c6024a743a48139b1fcdcf7e @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/index.html
[-- Attachment #2: Type: text/html, Size: 58934 bytes --]
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: SSEU handling updates (rev4)
2022-05-18 3:24 ` Matt Roper
@ 2022-05-18 16:51 ` Vudum, Lakshminarayana
0 siblings, 0 replies; 43+ messages in thread
From: Vudum, Lakshminarayana @ 2022-05-18 16:51 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx
Filed a new issue https://gitlab.freedesktop.org/drm/intel/-/issues/6038
igt@kms_flip@flip-vs-panning-interruptible@c-edp1 - dmesg-warn - rcu: INFO: rcu_preempt detected stalls on CPUs/tasks
Thanks,
Lakshmi.
-----Original Message-----
From: Roper, Matthew D <matthew.d.roper@intel.com>
Sent: Tuesday, May 17, 2022 8:24 PM
To: intel-gfx@lists.freedesktop.org
Cc: Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>
Subject: Re: ✗ Fi.CI.IGT: failure for i915: SSEU handling updates (rev4)
On Wed, May 18, 2022 at 12:34:11AM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: i915: SSEU handling updates (rev4)
> URL : https://patchwork.freedesktop.org/series/103244/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11666_full -> Patchwork_103244v4_full
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_103244v4_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_103244v4_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Participating hosts (11 -> 11)
> ------------------------------
>
> No changes in participating hosts
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_103244v4_full:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@kms_flip@flip-vs-panning-interruptible@c-edp1:
> - shard-iclb: [PASS][1] -> [DMESG-WARN][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb3/igt@kms_flip@flip-vs-panning-interruptible@c-edp1.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb8/igt@kms_flip@flip-vs-panning-interruptible@c-edp1.html
<3> [607.307030] rcu: INFO: rcu_preempt detected stalls on CPUs/tasks:
<3> [607.307121] rcu: 3-...!: (159 GPs behind) idle=834/0/0x0 softirq=27765/27765 fqs=1 (false positive?)
<3> [607.307825] rcu: 7-...!: (172 GPs behind) idle=abc/0/0x0 softirq=23642/23643 fqs=1 (false positive?)
<4> [607.307934] (detected by 0, t=65002 jiffies, g=64137, q=5840)
<6> [607.307942] Sending NMI from CPU 0 to CPUs 3:
<4> [607.308032] NMI backtrace for cpu 3 skipped: idling at intel_idle+0x67/0xc0
<6> [607.308950] Sending NMI from CPU 0 to CPUs 7:
<4> [607.309045] NMI backtrace for cpu 7 skipped: idling at intel_idle+0x67/0xc0
<3> [607.309957] rcu: rcu_preempt kthread timer wakeup didn't happen for 64995 jiffies! g64137 f0x0 RCU_GP_WAIT_FQS(5) ->state=0x402
<3> [607.310053] rcu: Possible timer handling issue on cpu=3 timer-softirq=16787
<3> [607.310110] rcu: rcu_preempt kthread starved for 64998 jiffies! g64137 f0x0 RCU_GP_WAIT_FQS(5) ->state=0x402 ->cpu=3
<3> [607.310195] rcu: Unless rcu_preempt kthread gets sufficient CPU time, OOM is now expected behavior.
<3> [607.310267] rcu: RCU grace-period kthread stack dump:
<6> [607.310310] task:rcu_preempt state:I stack:14472 pid: 13 ppid: 2 flags:0x00004000
<6> [607.310326] Call Trace:
<6> [607.310330] <TASK>
<6> [607.310339] __schedule+0x483/0xb50
<6> [607.310353] ? schedule_timeout+0x1b9/0x2e0
<6> [607.310367] schedule+0x3f/0xa0
<6> [607.310376] schedule_timeout+0x1be/0x2e0
<6> [607.310386] ? del_timer_sync+0xb0/0xb0
<6> [607.310398] ? 0xffffffff81000000
<6> [607.310408] ? rcu_gp_cleanup+0x440/0x440
<6> [607.310413] rcu_gp_fqs_loop+0x273/0x3b0
<6> [607.310427] rcu_gp_kthread+0xb8/0x120
<6> [607.310436] kthread+0xed/0x120
<6> [607.310443] ? kthread_complete_and_exit+0x20/0x20
<6> [607.310452] ret_from_fork+0x1f/0x30
<6> [607.310478] </TASK>
<3> [607.310481] rcu: Stack dump where RCU GP kthread last ran:
<6> [607.310527] Sending NMI from CPU 0 to CPUs 3:
<4> [607.310602] NMI backtrace for cpu 3 skipped: idling at intel_idle+0x67/0xc0
It's not clear what this is from (no indication it's even related to the
graphics driver). Definitely not the kind of thing that the SSEU rework
in this series could cause to happen during a display test.
Matt
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_103244v4_full that come from known issues:
>
> ### CI changes ###
>
> #### Possible fixes ####
>
> * boot:
> - shard-skl: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [FAIL][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26]) ([i915#5032]) -> ([PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49])
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl9/boot.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl9/boot.html
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl9/boot.html
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/boot.html
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/boot.html
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/boot.html
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl7/boot.html
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl7/boot.html
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl7/boot.html
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl6/boot.html
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl6/boot.html
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl6/boot.html
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/boot.html
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/boot.html
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/boot.html
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/boot.html
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl3/boot.html
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl3/boot.html
> [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl1/boot.html
> [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl1/boot.html
> [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl1/boot.html
> [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl10/boot.html
> [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl10/boot.html
> [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl10/boot.html
> [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl1/boot.html
> [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl1/boot.html
> [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl1/boot.html
> [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl3/boot.html
> [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl3/boot.html
> [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl4/boot.html
> [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl4/boot.html
> [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/boot.html
> [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/boot.html
> [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/boot.html
> [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl7/boot.html
> [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl7/boot.html
> [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl7/boot.html
> [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl8/boot.html
> [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl8/boot.html
> [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/boot.html
> [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/boot.html
> [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/boot.html
> [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/boot.html
> [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/boot.html
> [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/boot.html
> [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/boot.html
> [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/boot.html
>
>
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@drm_buddy@all@buddy_alloc_smoke:
> - shard-skl: [PASS][50] -> [INCOMPLETE][51] ([i915#5800])
> [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl6/igt@drm_buddy@all@buddy_alloc_smoke.html
> [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl1/igt@drm_buddy@all@buddy_alloc_smoke.html
>
> * igt@gem_create@create-massive:
> - shard-kbl: NOTRUN -> [DMESG-WARN][52] ([i915#4991])
> [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@gem_create@create-massive.html
>
> * igt@gem_exec_balancer@parallel-balancer:
> - shard-iclb: [PASS][53] -> [SKIP][54] ([i915#4525])
> [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb4/igt@gem_exec_balancer@parallel-balancer.html
> [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb5/igt@gem_exec_balancer@parallel-balancer.html
>
> * igt@gem_exec_balancer@parallel-keep-in-fence:
> - shard-kbl: NOTRUN -> [DMESG-WARN][55] ([i915#5076] / [i915#5614])
> [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@gem_exec_balancer@parallel-keep-in-fence.html
>
> * igt@gem_exec_fair@basic-none-share@rcs0:
> - shard-tglb: [PASS][56] -> [FAIL][57] ([i915#2842])
> [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglb3/igt@gem_exec_fair@basic-none-share@rcs0.html
> [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglb8/igt@gem_exec_fair@basic-none-share@rcs0.html
>
> * igt@gem_exec_fair@basic-none@vcs0:
> - shard-kbl: [PASS][58] -> [FAIL][59] ([i915#2842]) +2 similar issues
> [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html
> [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
>
> * igt@gem_exec_fair@basic-pace-share@rcs0:
> - shard-glk: [PASS][60] -> [FAIL][61] ([i915#2842]) +1 similar issue
> [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
> [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
>
> * igt@gem_exec_fair@basic-pace@vcs1:
> - shard-iclb: NOTRUN -> [FAIL][62] ([i915#2842]) +2 similar issues
> [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html
>
> * igt@gem_exec_fair@basic-throttle@rcs0:
> - shard-iclb: NOTRUN -> [FAIL][63] ([i915#2849])
> [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
>
> * igt@gem_exec_params@secure-non-root:
> - shard-iclb: NOTRUN -> [SKIP][64] ([fdo#112283])
> [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@gem_exec_params@secure-non-root.html
>
> * igt@gem_huc_copy@huc-copy:
> - shard-tglb: [PASS][65] -> [SKIP][66] ([i915#2190])
> [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglb5/igt@gem_huc_copy@huc-copy.html
> [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglb6/igt@gem_huc_copy@huc-copy.html
>
> * igt@gem_lmem_swapping@basic:
> - shard-iclb: NOTRUN -> [SKIP][67] ([i915#4613]) +2 similar issues
> [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@gem_lmem_swapping@basic.html
> - shard-apl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#4613]) +1 similar issue
> [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl6/igt@gem_lmem_swapping@basic.html
>
> * igt@gem_lmem_swapping@parallel-random-verify-ccs:
> - shard-skl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#4613]) +1 similar issue
> [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
>
> * igt@gem_lmem_swapping@verify-random:
> - shard-kbl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#4613])
> [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@gem_lmem_swapping@verify-random.html
>
> * igt@gem_render_copy@y-tiled-to-vebox-linear:
> - shard-iclb: NOTRUN -> [SKIP][71] ([i915#768]) +1 similar issue
> [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@gem_render_copy@y-tiled-to-vebox-linear.html
>
> * igt@gem_softpin@evict-single-offset:
> - shard-kbl: NOTRUN -> [FAIL][72] ([i915#4171])
> [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@gem_softpin@evict-single-offset.html
>
> * igt@gem_userptr_blits@dmabuf-sync:
> - shard-apl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#3323])
> [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@gem_userptr_blits@dmabuf-sync.html
>
> * igt@gem_userptr_blits@vma-merge:
> - shard-skl: NOTRUN -> [FAIL][74] ([i915#3318])
> [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/igt@gem_userptr_blits@vma-merge.html
>
> * igt@gen9_exec_parse@bb-chained:
> - shard-iclb: NOTRUN -> [SKIP][75] ([i915#2856]) +1 similar issue
> [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@gen9_exec_parse@bb-chained.html
>
> * igt@i915_pm_rpm@modeset-non-lpsp:
> - shard-iclb: NOTRUN -> [SKIP][76] ([fdo#110892])
> [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@i915_pm_rpm@modeset-non-lpsp.html
>
> * igt@i915_pm_sseu@full-enable:
> - shard-iclb: NOTRUN -> [SKIP][77] ([i915#4387])
> [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@i915_pm_sseu@full-enable.html
>
> * igt@i915_selftest@mock@requests:
> - shard-skl: [PASS][78] -> [INCOMPLETE][79] ([i915#5183])
> [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/igt@i915_selftest@mock@requests.html
> [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl8/igt@i915_selftest@mock@requests.html
>
> * igt@i915_suspend@forcewake:
> - shard-apl: [PASS][80] -> [DMESG-WARN][81] ([i915#180])
> [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl6/igt@i915_suspend@forcewake.html
> [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl4/igt@i915_suspend@forcewake.html
>
> * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
> - shard-iclb: NOTRUN -> [SKIP][82] ([i915#3826])
> [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
>
> * igt@kms_async_flips@crc:
> - shard-skl: NOTRUN -> [FAIL][83] ([i915#4272])
> [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_async_flips@crc.html
>
> * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
> - shard-iclb: NOTRUN -> [SKIP][84] ([i915#5286]) +1 similar issue
> [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
>
> * igt@kms_big_fb@x-tiled-16bpp-rotate-270:
> - shard-iclb: NOTRUN -> [SKIP][85] ([fdo#110725] / [fdo#111614]) +2 similar issues
> [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
>
> * igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
> - shard-iclb: NOTRUN -> [SKIP][86] ([fdo#110723])
> [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html
>
> * igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs:
> - shard-apl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#3886]) +5 similar issues
> [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl6/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs.html
>
> * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs:
> - shard-skl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#3886]) +1 similar issue
> [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs.html
>
> * igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
> - shard-kbl: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#3886])
> [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
>
> * igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs:
> - shard-iclb: NOTRUN -> [SKIP][90] ([fdo#109278]) +26 similar issues
> [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs.html
>
> * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
> - shard-iclb: NOTRUN -> [SKIP][91] ([fdo#109278] / [i915#3886]) +2 similar issues
> [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb7/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
>
> * igt@kms_chamelium@dp-crc-multiple:
> - shard-skl: NOTRUN -> [SKIP][92] ([fdo#109271] / [fdo#111827]) +12 similar issues
> [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/igt@kms_chamelium@dp-crc-multiple.html
>
> * igt@kms_chamelium@dp-hpd-for-each-pipe:
> - shard-apl: NOTRUN -> [SKIP][93] ([fdo#109271] / [fdo#111827]) +4 similar issues
> [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl3/igt@kms_chamelium@dp-hpd-for-each-pipe.html
>
> * igt@kms_color_chamelium@pipe-a-ctm-red-to-blue:
> - shard-iclb: NOTRUN -> [SKIP][94] ([fdo#109284] / [fdo#111827]) +9 similar issues
> [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_color_chamelium@pipe-a-ctm-red-to-blue.html
>
> * igt@kms_color_chamelium@pipe-c-ctm-limited-range:
> - shard-kbl: NOTRUN -> [SKIP][95] ([fdo#109271] / [fdo#111827])
> [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@kms_color_chamelium@pipe-c-ctm-limited-range.html
>
> * igt@kms_color_chamelium@pipe-d-ctm-0-25:
> - shard-iclb: NOTRUN -> [SKIP][96] ([fdo#109278] / [fdo#109284] / [fdo#111827])
> [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_color_chamelium@pipe-d-ctm-0-25.html
>
> * igt@kms_content_protection@atomic:
> - shard-apl: NOTRUN -> [TIMEOUT][97] ([i915#1319])
> [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl3/igt@kms_content_protection@atomic.html
>
> * igt@kms_content_protection@dp-mst-type-0:
> - shard-iclb: NOTRUN -> [SKIP][98] ([i915#3116])
> [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_content_protection@dp-mst-type-0.html
>
> * igt@kms_content_protection@lic:
> - shard-iclb: NOTRUN -> [SKIP][99] ([fdo#109300] / [fdo#111066])
> [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_content_protection@lic.html
>
> * igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding:
> - shard-iclb: NOTRUN -> [SKIP][100] ([fdo#109278] / [fdo#109279]) +3 similar issues
> [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding.html
>
> * igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen:
> - shard-skl: NOTRUN -> [SKIP][101] ([fdo#109271]) +151 similar issues
> [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen.html
>
> * igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen:
> - shard-kbl: NOTRUN -> [SKIP][102] ([fdo#109271]) +55 similar issues
> [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl1/igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen.html
>
> * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
> - shard-iclb: NOTRUN -> [SKIP][103] ([fdo#109274] / [fdo#109278]) +2 similar issues
> [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
>
> * igt@kms_dp_tiled_display@basic-test-pattern:
> - shard-iclb: NOTRUN -> [SKIP][104] ([i915#426])
> [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_dp_tiled_display@basic-test-pattern.html
>
> * igt@kms_flip@2x-flip-vs-dpms:
> - shard-iclb: NOTRUN -> [SKIP][105] ([fdo#109274]) +5 similar issues
> [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_flip@2x-flip-vs-dpms.html
>
> * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
> - shard-skl: [PASS][106] -> [FAIL][107] ([i915#2122]) +1 similar issue
> [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
> [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
>
> * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
> - shard-glk: [PASS][108] -> [FAIL][109] ([i915#4911])
> [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-glk5/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
> [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
>
> * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
> - shard-iclb: [PASS][110] -> [SKIP][111] ([i915#3701])
> [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
> [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
> - shard-iclb: NOTRUN -> [SKIP][112] ([fdo#109280]) +22 similar issues
> [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html
>
> * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
> - shard-iclb: NOTRUN -> [SKIP][113] ([i915#1839])
> [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
>
> * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
> - shard-kbl: NOTRUN -> [FAIL][114] ([i915#265])
> [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
>
> * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
> - shard-apl: NOTRUN -> [FAIL][115] ([fdo#108145] / [i915#265])
> [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl6/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
>
> * igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
> - shard-skl: NOTRUN -> [FAIL][116] ([fdo#108145] / [i915#265]) +1 similar issue
> [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html
>
> * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
> - shard-skl: [PASS][117] -> [FAIL][118] ([fdo#108145] / [i915#265]) +1 similar issue
> [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
> [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>
> * igt@kms_plane_lowres@pipe-a-tiling-x:
> - shard-iclb: NOTRUN -> [SKIP][119] ([i915#3536]) +1 similar issue
> [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-x.html
>
> * igt@kms_plane_scaling@downscale-with-modifier-factor-0-25@pipe-a-edp-1-downscale-with-modifier:
> - shard-skl: NOTRUN -> [SKIP][120] ([fdo#109271] / [i915#5176]) +2 similar issues
> [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_plane_scaling@downscale-with-modifier-factor-0-25@pipe-a-edp-1-downscale-with-modifier.html
>
> * igt@kms_plane_scaling@invalid-num-scalers@pipe-a-edp-1-invalid-num-scalers:
> - shard-skl: NOTRUN -> [SKIP][121] ([fdo#109271] / [i915#5776]) +2 similar issues
> [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl6/igt@kms_plane_scaling@invalid-num-scalers@pipe-a-edp-1-invalid-num-scalers.html
>
> * igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale:
> - shard-iclb: [PASS][122] -> [SKIP][123] ([i915#5235]) +2 similar issues
> [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html
> [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html
>
> * igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
> - shard-apl: NOTRUN -> [SKIP][124] ([fdo#109271] / [i915#658]) +1 similar issue
> [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
>
> * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
> - shard-iclb: NOTRUN -> [SKIP][125] ([fdo#111068] / [i915#658])
> [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
>
> * igt@kms_psr2_su@page_flip-nv12:
> - shard-iclb: NOTRUN -> [SKIP][126] ([fdo#109642] / [fdo#111068] / [i915#658])
> [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_psr2_su@page_flip-nv12.html
>
> * igt@kms_psr2_su@page_flip-p010:
> - shard-kbl: NOTRUN -> [SKIP][127] ([fdo#109271] / [i915#658]) +1 similar issue
> [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@kms_psr2_su@page_flip-p010.html
>
> * igt@kms_psr2_su@page_flip-xrgb8888:
> - shard-skl: NOTRUN -> [SKIP][128] ([fdo#109271] / [i915#658]) +1 similar issue
> [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_psr2_su@page_flip-xrgb8888.html
>
> * igt@kms_psr@psr2_sprite_plane_move:
> - shard-iclb: NOTRUN -> [SKIP][129] ([fdo#109441]) +2 similar issues
> [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html
>
> * igt@kms_psr@psr2_suspend:
> - shard-iclb: [PASS][130] -> [SKIP][131] ([fdo#109441]) +1 similar issue
> [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb2/igt@kms_psr@psr2_suspend.html
> [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_psr@psr2_suspend.html
>
> * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
> - shard-skl: [PASS][132] -> [DMESG-WARN][133] ([i915#1982])
> [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
> [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl10/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
> - shard-iclb: [PASS][134] -> [SKIP][135] ([i915#5519])
> [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
> [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
>
> * igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
> - shard-apl: NOTRUN -> [SKIP][136] ([fdo#109271]) +118 similar issues
> [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
>
> * igt@kms_sysfs_edid_timing:
> - shard-apl: NOTRUN -> [FAIL][137] ([IGT#2])
> [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl6/igt@kms_sysfs_edid_timing.html
>
> * igt@kms_vblank@pipe-d-wait-idle:
> - shard-apl: NOTRUN -> [SKIP][138] ([fdo#109271] / [i915#533]) +3 similar issues
> [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@kms_vblank@pipe-d-wait-idle.html
>
> * igt@kms_vrr@flip-basic:
> - shard-iclb: NOTRUN -> [SKIP][139] ([i915#3555]) +1 similar issue
> [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@kms_vrr@flip-basic.html
>
> * igt@nouveau_crc@pipe-a-source-rg:
> - shard-iclb: NOTRUN -> [SKIP][140] ([i915#2530]) +1 similar issue
> [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@nouveau_crc@pipe-a-source-rg.html
>
> * igt@perf@polling:
> - shard-skl: [PASS][141] -> [FAIL][142] ([i915#1542])
> [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl9/igt@perf@polling.html
> [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl3/igt@perf@polling.html
>
> * igt@prime_nv_pcopy@test3_3:
> - shard-iclb: NOTRUN -> [SKIP][143] ([fdo#109291]) +3 similar issues
> [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@prime_nv_pcopy@test3_3.html
>
> * igt@sysfs_clients@fair-0:
> - shard-skl: NOTRUN -> [SKIP][144] ([fdo#109271] / [i915#2994]) +3 similar issues
> [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/igt@sysfs_clients@fair-0.html
>
> * igt@sysfs_clients@fair-3:
> - shard-apl: NOTRUN -> [SKIP][145] ([fdo#109271] / [i915#2994])
> [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl3/igt@sysfs_clients@fair-3.html
>
> * igt@sysfs_clients@split-10:
> - shard-iclb: NOTRUN -> [SKIP][146] ([i915#2994]) +2 similar issues
> [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@sysfs_clients@split-10.html
>
>
> #### Possible fixes ####
>
> * igt@gem_eio@in-flight-10ms:
> - shard-tglb: [TIMEOUT][147] ([i915#3063]) -> [PASS][148]
> [147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglb2/igt@gem_eio@in-flight-10ms.html
> [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglb1/igt@gem_eio@in-flight-10ms.html
>
> * igt@gem_exec_fair@basic-none-share@rcs0:
> - {shard-tglu}: [FAIL][149] ([i915#2842]) -> [PASS][150]
> [149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglu-6/igt@gem_exec_fair@basic-none-share@rcs0.html
> [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglu-2/igt@gem_exec_fair@basic-none-share@rcs0.html
>
> * igt@gem_exec_fair@basic-none@vcs0:
> - shard-apl: [FAIL][151] ([i915#2842]) -> [PASS][152]
> [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl4/igt@gem_exec_fair@basic-none@vcs0.html
> [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl8/igt@gem_exec_fair@basic-none@vcs0.html
>
> * igt@gem_exec_fair@basic-none@vecs0:
> - shard-kbl: [FAIL][153] ([i915#2842]) -> [PASS][154]
> [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl3/igt@gem_exec_fair@basic-none@vecs0.html
> [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@gem_exec_fair@basic-none@vecs0.html
>
> * igt@gem_exec_fair@basic-pace@rcs0:
> - shard-iclb: [FAIL][155] ([i915#2842]) -> [PASS][156]
> [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@gem_exec_fair@basic-pace@rcs0.html
> [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@gem_exec_fair@basic-pace@rcs0.html
>
> * igt@gem_exec_fair@basic-pace@vcs0:
> - shard-kbl: [SKIP][157] ([fdo#109271]) -> [PASS][158]
> [157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs0.html
> [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs0.html
>
> * igt@gem_workarounds@suspend-resume-context:
> - shard-apl: [DMESG-WARN][159] ([i915#180]) -> [PASS][160] +2 similar issues
> [159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl7/igt@gem_workarounds@suspend-resume-context.html
> [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@gem_workarounds@suspend-resume-context.html
>
> * igt@i915_pm_dc@dc9-dpms:
> - {shard-tglu}: [SKIP][161] ([i915#4281]) -> [PASS][162]
> [161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglu-6/igt@i915_pm_dc@dc9-dpms.html
> [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglu-2/igt@i915_pm_dc@dc9-dpms.html
>
> * igt@i915_selftest@live@gt_heartbeat:
> - shard-kbl: [DMESG-FAIL][163] ([i915#5334]) -> [PASS][164]
> [163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl1/igt@i915_selftest@live@gt_heartbeat.html
> [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@i915_selftest@live@gt_heartbeat.html
>
> * igt@i915_selftest@live@hangcheck:
> - shard-tglb: [DMESG-WARN][165] ([i915#5591]) -> [PASS][166]
> [165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-tglb5/igt@i915_selftest@live@hangcheck.html
> [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-tglb6/igt@i915_selftest@live@hangcheck.html
>
> * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
> - shard-glk: [FAIL][167] ([i915#2346] / [i915#533]) -> [PASS][168]
> [167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
> [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
>
> * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2:
> - shard-glk: [FAIL][169] ([i915#2122]) -> [PASS][170]
> [169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html
> [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-glk3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html
>
> * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1:
> - shard-apl: [FAIL][171] ([i915#79]) -> [PASS][172]
> [171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
> [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
>
> * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
> - shard-skl: [FAIL][173] ([i915#2122]) -> [PASS][174]
> [173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
> [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
>
> * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
> - shard-kbl: [DMESG-WARN][175] ([i915#180]) -> [PASS][176] +5 similar issues
> [175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
> [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
>
> * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
> - shard-skl: [INCOMPLETE][177] ([i915#4444] / [i915#4939]) -> [PASS][178]
> [177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
> [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
>
> * igt@kms_psr@psr2_sprite_mmap_cpu:
> - shard-iclb: [SKIP][179] ([fdo#109441]) -> [PASS][180] +1 similar issue
> [179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@kms_psr@psr2_sprite_mmap_cpu.html
> [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html
>
> * igt@sysfs_heartbeat_interval@mixed@bcs0:
> - shard-skl: [WARN][181] ([i915#4055]) -> [PASS][182]
> [181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/igt@sysfs_heartbeat_interval@mixed@bcs0.html
> [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl8/igt@sysfs_heartbeat_interval@mixed@bcs0.html
>
> * igt@sysfs_heartbeat_interval@mixed@vcs0:
> - shard-skl: [FAIL][183] ([i915#1731]) -> [PASS][184]
> [183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-skl8/igt@sysfs_heartbeat_interval@mixed@vcs0.html
> [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-skl8/igt@sysfs_heartbeat_interval@mixed@vcs0.html
>
>
> #### Warnings ####
>
> * igt@gem_exec_balancer@parallel-contexts:
> - shard-iclb: [DMESG-WARN][185] ([i915#5614]) -> [SKIP][186] ([i915#4525]) +1 similar issue
> [185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb1/igt@gem_exec_balancer@parallel-contexts.html
> [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb6/igt@gem_exec_balancer@parallel-contexts.html
>
> * igt@gem_exec_balancer@parallel-keep-submit-fence:
> - shard-iclb: [SKIP][187] ([i915#4525]) -> [DMESG-WARN][188] ([i915#5614])
> [187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@gem_exec_balancer@parallel-keep-submit-fence.html
> [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb4/igt@gem_exec_balancer@parallel-keep-submit-fence.html
>
> * igt@gem_exec_balancer@parallel-ordering:
> - shard-iclb: [DMESG-FAIL][189] ([i915#5614]) -> [SKIP][190] ([i915#4525])
> [189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html
> [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@gem_exec_balancer@parallel-ordering.html
>
> * igt@i915_pm_dc@dc3co-vpb-simulation:
> - shard-iclb: [SKIP][191] ([i915#658]) -> [SKIP][192] ([i915#588])
> [191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb8/igt@i915_pm_dc@dc3co-vpb-simulation.html
> [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
>
> * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
> - shard-iclb: [SKIP][193] ([i915#2920]) -> [SKIP][194] ([fdo#111068] / [i915#658]) +1 similar issue
> [193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
> [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-iclb3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
>
> * igt@runner@aborted:
> - shard-kbl: ([FAIL][195], [FAIL][196], [FAIL][197], [FAIL][198], [FAIL][199], [FAIL][200], [FAIL][201], [FAIL][202], [FAIL][203], [FAIL][204], [FAIL][205], [FAIL][206]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][207], [FAIL][208], [FAIL][209], [FAIL][210], [FAIL][211], [FAIL][212], [FAIL][213], [FAIL][214], [FAIL][215], [FAIL][216]) ([i915#3002] / [i915#4312] / [i915#5257])
> [195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl6/igt@runner@aborted.html
> [196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl4/igt@runner@aborted.html
> [197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@runner@aborted.html
> [198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl1/igt@runner@aborted.html
> [199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl4/igt@runner@aborted.html
> [200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@runner@aborted.html
> [201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@runner@aborted.html
> [202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl1/igt@runner@aborted.html
> [203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@runner@aborted.html
> [204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl7/igt@runner@aborted.html
> [205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl1/igt@runner@aborted.html
> [206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-kbl3/igt@runner@aborted.html
> [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@runner@aborted.html
> [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl6/igt@runner@aborted.html
> [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@runner@aborted.html
> [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl4/igt@runner@aborted.html
> [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl7/igt@runner@aborted.html
> [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl1/igt@runner@aborted.html
> [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl3/igt@runner@aborted.html
> [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl1/igt@runner@aborted.html
> [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl1/igt@runner@aborted.html
> [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-kbl3/igt@runner@aborted.html
> - shard-apl: ([FAIL][217], [FAIL][218], [FAIL][219], [FAIL][220], [FAIL][221], [FAIL][222], [FAIL][223], [FAIL][224]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][225], [FAIL][226], [FAIL][227], [FAIL][228], [FAIL][229]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
> [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl4/igt@runner@aborted.html
> [218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl8/igt@runner@aborted.html
> [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl4/igt@runner@aborted.html
> [220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl7/igt@runner@aborted.html
> [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl2/igt@runner@aborted.html
> [222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl6/igt@runner@aborted.html
> [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl6/igt@runner@aborted.html
> [224]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11666/shard-apl3/igt@runner@aborted.html
> [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl2/igt@runner@aborted.html
> [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl4/igt@runner@aborted.html
> [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl8/igt@runner@aborted.html
> [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl4/igt@runner@aborted.html
> [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/shard-apl7/igt@runner@aborted.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
> [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
> [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
> [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
> [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
> [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
> [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
> [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
> [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
> [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
> [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
> [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
> [fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
> [fdo#110892]: https://bugs.freedesktop.org/show_bug.cgi?id=110892
> [fdo#111066]: https://bugs.freedesktop.org/show_bug.cgi?id=111066
> [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
> [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
> [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
> [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
> [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
> [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
> [i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
> [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
> [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
> [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
> [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
> [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
> [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
> [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
> [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
> [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
> [i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
> [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
> [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
> [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
> [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
> [i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
> [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
> [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
> [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
> [i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
> [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
> [i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
> [i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778
> [i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
> [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
> [i915#4055]: https://gitlab.freedesktop.org/drm/intel/issues/4055
> [i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
> [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
> [i915#4272]: https://gitlab.freedesktop.org/drm/intel/issues/4272
> [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
> [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
> [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
> [i915#4444]: https://gitlab.freedesktop.org/drm/intel/issues/4444
> [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
> [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
> [i915#4911]: https://gitlab.freedesktop.org/drm/intel/issues/4911
> [i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
> [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
> [i915#5032]: https://gitlab.freedesktop.org/drm/intel/issues/5032
> [i915#5076]: https://gitlab.freedesktop.org/drm/intel/issues/5076
> [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
> [i915#5183]: https://gitlab.freedesktop.org/drm/intel/issues/5183
> [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
> [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
> [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
> [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
> [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
> [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
> [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
> [i915#5614]: https://gitlab.freedesktop.org/drm/intel/issues/5614
> [i915#5776]: https://gitlab.freedesktop.org/drm/intel/issues/5776
> [i915#5800]: https://gitlab.freedesktop.org/drm/intel/issues/5800
> [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
> [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
> [i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
> [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_11666 -> Patchwork_103244v4
>
> CI-20190529: 20190529
> CI_DRM_11666: 73bb9fa49db3df15c6024a743a48139b1fcdcf7e @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6476: 08aa9296163b94cf4c529fc890ae3e90e21c3cdb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_103244v4: 73bb9fa49db3df15c6024a743a48139b1fcdcf7e @ git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103244v4/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 2/6] drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
2022-05-17 3:20 ` [Intel-gfx] " Matt Roper
@ 2022-05-20 9:15 ` Tvrtko Ursulin
-1 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2022-05-20 9:15 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: Jordan Justen, Lionel Landwerlin, dri-devel
On 17/05/2022 04:20, Matt Roper wrote:
> Slice/subslice/EU information should be obtained via the topology
> queries provided by the I915_QUERY interface; let's turn off support for
> the old GETPARAM lookups on Xe_HP and beyond where we can't return
> meaningful values.
>
> The slice mask lookup is meaningless since Xe_HP doesn't support
> traditional slices (and we make no attempt to return the various new
> units like gslices, cslices, mslices, etc.) here.
>
> The subslice mask lookup is even more problematic; given the distinct
> masks for geometry vs compute purposes, the combined mask returned here
> is likely not what userspace would want to act upon anyway. The value
> is also limited to 32-bits by the nature of the GETPARAM ioctl which is
> sufficient for the initial Xe_HP platforms, but is unable to convey the
> larger masks that will be needed on other upcoming platforms. Finally,
> the value returned here becomes even less meaningful when used on
> multi-tile platforms where each tile will have its own masks.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/i915_getparam.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
> index c12a0adefda5..ac9767c56619 100644
> --- a/drivers/gpu/drm/i915/i915_getparam.c
> +++ b/drivers/gpu/drm/i915/i915_getparam.c
> @@ -148,11 +148,19 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
> value = intel_engines_has_context_isolation(i915);
> break;
> case I915_PARAM_SLICE_MASK:
> + /* Not supported from Xe_HP onward; use topology queries */
> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> + return -EINVAL;
> +
> value = sseu->slice_mask;
> if (!value)
> return -ENODEV;
> break;
> case I915_PARAM_SUBSLICE_MASK:
> + /* Not supported from Xe_HP onward; use topology queries */
> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> + return -EINVAL;
> +
> /* Only copy bits from the first slice */
> memcpy(&value, sseu->subslice_mask,
> min(sseu->ss_stride, (u8)sizeof(value)));
Just in case lets run this by Jordan and Lionel since it affects DG2.
Anyone else on the userspace side who might be affected?
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/6] drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
@ 2022-05-20 9:15 ` Tvrtko Ursulin
0 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2022-05-20 9:15 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel
On 17/05/2022 04:20, Matt Roper wrote:
> Slice/subslice/EU information should be obtained via the topology
> queries provided by the I915_QUERY interface; let's turn off support for
> the old GETPARAM lookups on Xe_HP and beyond where we can't return
> meaningful values.
>
> The slice mask lookup is meaningless since Xe_HP doesn't support
> traditional slices (and we make no attempt to return the various new
> units like gslices, cslices, mslices, etc.) here.
>
> The subslice mask lookup is even more problematic; given the distinct
> masks for geometry vs compute purposes, the combined mask returned here
> is likely not what userspace would want to act upon anyway. The value
> is also limited to 32-bits by the nature of the GETPARAM ioctl which is
> sufficient for the initial Xe_HP platforms, but is unable to convey the
> larger masks that will be needed on other upcoming platforms. Finally,
> the value returned here becomes even less meaningful when used on
> multi-tile platforms where each tile will have its own masks.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/i915_getparam.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
> index c12a0adefda5..ac9767c56619 100644
> --- a/drivers/gpu/drm/i915/i915_getparam.c
> +++ b/drivers/gpu/drm/i915/i915_getparam.c
> @@ -148,11 +148,19 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
> value = intel_engines_has_context_isolation(i915);
> break;
> case I915_PARAM_SLICE_MASK:
> + /* Not supported from Xe_HP onward; use topology queries */
> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> + return -EINVAL;
> +
> value = sseu->slice_mask;
> if (!value)
> return -ENODEV;
> break;
> case I915_PARAM_SUBSLICE_MASK:
> + /* Not supported from Xe_HP onward; use topology queries */
> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> + return -EINVAL;
> +
> /* Only copy bits from the first slice */
> memcpy(&value, sseu->subslice_mask,
> min(sseu->ss_stride, (u8)sizeof(value)));
Just in case lets run this by Jordan and Lionel since it affects DG2.
Anyone else on the userspace side who might be affected?
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 3/6] drm/i915/sseu: Simplify gen11+ SSEU handling
2022-05-17 3:20 ` [Intel-gfx] " Matt Roper
@ 2022-05-20 9:21 ` Tvrtko Ursulin
-1 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2022-05-20 9:21 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel
On 17/05/2022 04:20, Matt Roper wrote:
> Although gen11 and gen12 architectures supported the concept of multiple
> slices, in practice all the platforms that were actually designed only
> had a single slice (i.e., note the parameters to 'intel_sseu_set_info'
> that we pass for each platform). We can simplify the code slightly by
> dropping the multi-slice logic from gen11+ platforms.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_sseu.c | 80 ++++++++++++++--------------
> 1 file changed, 40 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index b5fd479a7b85..ade3e1805782 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -119,52 +119,37 @@ static u16 compute_eu_total(const struct sseu_dev_info *sseu)
> return total;
> }
>
> -static u32 get_ss_stride_mask(struct sseu_dev_info *sseu, u8 s, u32 ss_en)
> -{
> - u32 ss_mask;
> -
> - ss_mask = ss_en >> (s * sseu->max_subslices);
> - ss_mask &= GENMASK(sseu->max_subslices - 1, 0);
> -
> - return ss_mask;
> -}
> -
> -static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, u8 s_en,
> +static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> u32 g_ss_en, u32 c_ss_en, u16 eu_en)
> {
> - int s, ss;
> + u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
> + int ss;
>
> /* g_ss_en/c_ss_en represent entire subslice mask across all slices */
> GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
> sizeof(g_ss_en) * BITS_PER_BYTE);
>
> - for (s = 0; s < sseu->max_slices; s++) {
> - if ((s_en & BIT(s)) == 0)
> - continue;
> + sseu->slice_mask |= BIT(0);
>
> - sseu->slice_mask |= BIT(s);
> -
> - /*
> - * XeHP introduces the concept of compute vs geometry DSS. To
> - * reduce variation between GENs around subslice usage, store a
> - * mask for both the geometry and compute enabled masks since
> - * userspace will need to be able to query these masks
> - * independently. Also compute a total enabled subslice count
> - * for the purposes of selecting subslices to use in a
> - * particular GEM context.
> - */
> - intel_sseu_set_subslices(sseu, s, sseu->compute_subslice_mask,
> - get_ss_stride_mask(sseu, s, c_ss_en));
> - intel_sseu_set_subslices(sseu, s, sseu->geometry_subslice_mask,
> - get_ss_stride_mask(sseu, s, g_ss_en));
> - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> - get_ss_stride_mask(sseu, s,
> - g_ss_en | c_ss_en));
> + /*
> + * XeHP introduces the concept of compute vs geometry DSS. To reduce
> + * variation between GENs around subslice usage, store a mask for both
> + * the geometry and compute enabled masks since userspace will need to
> + * be able to query these masks independently. Also compute a total
> + * enabled subslice count for the purposes of selecting subslices to
> + * use in a particular GEM context.
> + */
> + intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
> + c_ss_en & valid_ss_mask);
> + intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
> + g_ss_en & valid_ss_mask);
> + intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
> + (g_ss_en | c_ss_en) & valid_ss_mask);
> +
> + for (ss = 0; ss < sseu->max_subslices; ss++)
> + if (intel_sseu_has_subslice(sseu, 0, ss))
> + sseu_set_eus(sseu, 0, ss, eu_en);
>
> - for (ss = 0; ss < sseu->max_subslices; ss++)
> - if (intel_sseu_has_subslice(sseu, s, ss))
> - sseu_set_eus(sseu, s, ss, eu_en);
> - }
> sseu->eu_per_subslice = hweight16(eu_en);
> sseu->eu_total = compute_eu_total(sseu);
> }
> @@ -196,7 +181,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
> if (eu_en_fuse & BIT(eu))
> eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
>
> - gen11_compute_sseu_info(sseu, 0x1, g_dss_en, c_dss_en, eu_en);
> + gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
> }
>
> static void gen12_sseu_info_init(struct intel_gt *gt)
> @@ -216,8 +201,15 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
> */
> intel_sseu_set_info(sseu, 1, 6, 16);
>
> + /*
> + * Although gen12 architecture supported multiple slices, TGL, RKL,
> + * DG1, and ADL only had a single slice.
> + */
> s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
> GEN11_GT_S_ENA_MASK;
> + if (s_en != 0x1)
> + drm_dbg(>->i915->drm, "Slice mask %#x is not the expected 0x1!\n",
I'd make these drm_warn - drm_dbg feels pointless. Possibly even
drm_WARN_ON since it is supposed to be an impossible condition which
needs to be super loud if it happens.
Regards,
Tvrtko
> + s_en);
>
> g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
>
> @@ -229,7 +221,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
> if (eu_en_fuse & BIT(eu))
> eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
>
> - gen11_compute_sseu_info(sseu, s_en, g_dss_en, 0, eu_en);
> + gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
>
> /* TGL only supports slice-level power gating */
> sseu->has_slice_pg = 1;
> @@ -248,14 +240,22 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
> else
> intel_sseu_set_info(sseu, 1, 8, 8);
>
> + /*
> + * Although gen11 architecture supported multiple slices, ICL and
> + * EHL/JSL only had a single slice in practice.
> + */
> s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
> GEN11_GT_S_ENA_MASK;
> + if (s_en != 0x1)
> + drm_dbg(>->i915->drm, "Slice mask %#x is not the expected 0x1!\n",
> + s_en);
> +
> ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE);
>
> eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
> GEN11_EU_DIS_MASK);
>
> - gen11_compute_sseu_info(sseu, s_en, ss_en, 0, eu_en);
> + gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
>
> /* ICL has no power gating restrictions. */
> sseu->has_slice_pg = 1;
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] [PATCH v2 3/6] drm/i915/sseu: Simplify gen11+ SSEU handling
@ 2022-05-20 9:21 ` Tvrtko Ursulin
0 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2022-05-20 9:21 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel
On 17/05/2022 04:20, Matt Roper wrote:
> Although gen11 and gen12 architectures supported the concept of multiple
> slices, in practice all the platforms that were actually designed only
> had a single slice (i.e., note the parameters to 'intel_sseu_set_info'
> that we pass for each platform). We can simplify the code slightly by
> dropping the multi-slice logic from gen11+ platforms.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_sseu.c | 80 ++++++++++++++--------------
> 1 file changed, 40 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index b5fd479a7b85..ade3e1805782 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -119,52 +119,37 @@ static u16 compute_eu_total(const struct sseu_dev_info *sseu)
> return total;
> }
>
> -static u32 get_ss_stride_mask(struct sseu_dev_info *sseu, u8 s, u32 ss_en)
> -{
> - u32 ss_mask;
> -
> - ss_mask = ss_en >> (s * sseu->max_subslices);
> - ss_mask &= GENMASK(sseu->max_subslices - 1, 0);
> -
> - return ss_mask;
> -}
> -
> -static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, u8 s_en,
> +static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> u32 g_ss_en, u32 c_ss_en, u16 eu_en)
> {
> - int s, ss;
> + u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
> + int ss;
>
> /* g_ss_en/c_ss_en represent entire subslice mask across all slices */
> GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
> sizeof(g_ss_en) * BITS_PER_BYTE);
>
> - for (s = 0; s < sseu->max_slices; s++) {
> - if ((s_en & BIT(s)) == 0)
> - continue;
> + sseu->slice_mask |= BIT(0);
>
> - sseu->slice_mask |= BIT(s);
> -
> - /*
> - * XeHP introduces the concept of compute vs geometry DSS. To
> - * reduce variation between GENs around subslice usage, store a
> - * mask for both the geometry and compute enabled masks since
> - * userspace will need to be able to query these masks
> - * independently. Also compute a total enabled subslice count
> - * for the purposes of selecting subslices to use in a
> - * particular GEM context.
> - */
> - intel_sseu_set_subslices(sseu, s, sseu->compute_subslice_mask,
> - get_ss_stride_mask(sseu, s, c_ss_en));
> - intel_sseu_set_subslices(sseu, s, sseu->geometry_subslice_mask,
> - get_ss_stride_mask(sseu, s, g_ss_en));
> - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> - get_ss_stride_mask(sseu, s,
> - g_ss_en | c_ss_en));
> + /*
> + * XeHP introduces the concept of compute vs geometry DSS. To reduce
> + * variation between GENs around subslice usage, store a mask for both
> + * the geometry and compute enabled masks since userspace will need to
> + * be able to query these masks independently. Also compute a total
> + * enabled subslice count for the purposes of selecting subslices to
> + * use in a particular GEM context.
> + */
> + intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
> + c_ss_en & valid_ss_mask);
> + intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
> + g_ss_en & valid_ss_mask);
> + intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
> + (g_ss_en | c_ss_en) & valid_ss_mask);
> +
> + for (ss = 0; ss < sseu->max_subslices; ss++)
> + if (intel_sseu_has_subslice(sseu, 0, ss))
> + sseu_set_eus(sseu, 0, ss, eu_en);
>
> - for (ss = 0; ss < sseu->max_subslices; ss++)
> - if (intel_sseu_has_subslice(sseu, s, ss))
> - sseu_set_eus(sseu, s, ss, eu_en);
> - }
> sseu->eu_per_subslice = hweight16(eu_en);
> sseu->eu_total = compute_eu_total(sseu);
> }
> @@ -196,7 +181,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
> if (eu_en_fuse & BIT(eu))
> eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
>
> - gen11_compute_sseu_info(sseu, 0x1, g_dss_en, c_dss_en, eu_en);
> + gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
> }
>
> static void gen12_sseu_info_init(struct intel_gt *gt)
> @@ -216,8 +201,15 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
> */
> intel_sseu_set_info(sseu, 1, 6, 16);
>
> + /*
> + * Although gen12 architecture supported multiple slices, TGL, RKL,
> + * DG1, and ADL only had a single slice.
> + */
> s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
> GEN11_GT_S_ENA_MASK;
> + if (s_en != 0x1)
> + drm_dbg(>->i915->drm, "Slice mask %#x is not the expected 0x1!\n",
I'd make these drm_warn - drm_dbg feels pointless. Possibly even
drm_WARN_ON since it is supposed to be an impossible condition which
needs to be super loud if it happens.
Regards,
Tvrtko
> + s_en);
>
> g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
>
> @@ -229,7 +221,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
> if (eu_en_fuse & BIT(eu))
> eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
>
> - gen11_compute_sseu_info(sseu, s_en, g_dss_en, 0, eu_en);
> + gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
>
> /* TGL only supports slice-level power gating */
> sseu->has_slice_pg = 1;
> @@ -248,14 +240,22 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
> else
> intel_sseu_set_info(sseu, 1, 8, 8);
>
> + /*
> + * Although gen11 architecture supported multiple slices, ICL and
> + * EHL/JSL only had a single slice in practice.
> + */
> s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
> GEN11_GT_S_ENA_MASK;
> + if (s_en != 0x1)
> + drm_dbg(>->i915->drm, "Slice mask %#x is not the expected 0x1!\n",
> + s_en);
> +
> ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE);
>
> eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
> GEN11_EU_DIS_MASK);
>
> - gen11_compute_sseu_info(sseu, s_en, ss_en, 0, eu_en);
> + gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
>
> /* ICL has no power gating restrictions. */
> sseu->has_slice_pg = 1;
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 4/6] drm/i915/sseu: Don't try to store EU mask internally in UAPI format
2022-05-17 3:20 ` [Intel-gfx] " Matt Roper
@ 2022-05-20 9:32 ` Tvrtko Ursulin
-1 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2022-05-20 9:32 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel
On 17/05/2022 04:20, Matt Roper wrote:
> Storing the EU mask internally in the same format the I915_QUERY
> topology queries use makes the final copy_to_user() a bit simpler, but
> makes the rest of the driver's SSEU more complicated and harder to
> follow. Let's switch to an internal representation that's more natural:
> Xe_HP platforms will be a simple array of u16 masks, whereas pre-Xe_HP
> platforms will be a two-dimensional array, indexed by [slice][subslice].
> We'll convert to the uapi format only when the query uapi is called.
>
> v2:
> - Drop has_common_ss_eumask. We waste some space repeating identical
> EU masks for every single DSS, but the code is simpler without it.
> (Tvrtko)
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_sseu.c | 77 +++++++++++++++++++---------
> drivers/gpu/drm/i915/gt/intel_sseu.h | 9 +++-
> drivers/gpu/drm/i915/i915_query.c | 8 +--
> 3 files changed, 65 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index ade3e1805782..d89e2e0f05e5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -78,47 +78,76 @@ intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
> return hweight32(intel_sseu_get_subslices(sseu, slice));
> }
>
> -static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
> - int subslice)
> -{
> - int slice_stride = sseu->max_subslices * sseu->eu_stride;
> -
> - return slice * slice_stride + subslice * sseu->eu_stride;
> -}
> -
> static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
> int subslice)
> {
> - int i, offset = sseu_eu_idx(sseu, slice, subslice);
> - u16 eu_mask = 0;
> -
> - for (i = 0; i < sseu->eu_stride; i++)
> - eu_mask |=
> - ((u16)sseu->eu_mask[offset + i]) << (i * BITS_PER_BYTE);
> -
> - return eu_mask;
> + if (sseu->has_xehp_dss) {
> + WARN_ON(slice > 0);
> + return sseu->eu_mask.xehp[subslice];
> + } else {
> + return sseu->eu_mask.hsw[slice][subslice];
> + }
> }
>
> static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
> u16 eu_mask)
> {
> - int i, offset = sseu_eu_idx(sseu, slice, subslice);
> -
> - for (i = 0; i < sseu->eu_stride; i++)
> - sseu->eu_mask[offset + i] =
> - (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
> + if (sseu->has_xehp_dss) {
> + WARN_ON(slice > 0);
> + sseu->eu_mask.xehp[subslice] = eu_mask;
> + } else {
> + eu_mask &= GENMASK(sseu->max_eus_per_subslice - 1, 0);
Is this masking required? Oh I remember.. it's the type expansion! I thought that was wrong. I mean the callers are wrong. Some use u8 for the mask and then do ~mask passing it into u16 here. I don't think this function should account for that but callers should stop passing in garbage.
I had this in my patch:
GEM_WARN_ON(mask && (__fls(mask) >= sseu->max_eus_per_subslice));
And in the callers like:
- sseu_set_eus(sseu, 0, 0, ~disabled_mask);
+ sseu_set_eus(sseu, 0, 0, ~disabled_mask & 0xff);
- sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
+ sseu_set_eus(sseu, s, ss, ~eu_disabled_mask & eu_mask);
> + sseu->eu_mask.hsw[slice][subslice] = eu_mask;
> + }
> }
>
> static u16 compute_eu_total(const struct sseu_dev_info *sseu)
> {
> - u16 i, total = 0;
> + int s, ss, total = 0;
>
> - for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++)
> - total += hweight8(sseu->eu_mask[i]);
> + for (s = 0; s < sseu->max_slices; s++)
> + for (ss = 0; ss < sseu->max_subslices; ss++)
> + if (sseu->has_xehp_dss)
> + total += hweight16(sseu->eu_mask.xehp[ss]);
> + else
> + total += hweight16(sseu->eu_mask.hsw[s][ss]);
>
> return total;
> }
>
> +/**
> + * intel_sseu_copy_eumask_to_user - Copy EU mask into a userspace buffer
> + * @to: Pointer to userspace buffer to copy to
> + * @sseu: SSEU structure containing EU mask to copy
> + *
> + * Copies the EU mask to a userspace buffer in the format expected by
> + * the query ioctl's topology queries.
> + *
> + * Returns the result of the copy_to_user() operation.
> + */
> +int intel_sseu_copy_eumask_to_user(void __user *to,
> + const struct sseu_dev_info *sseu)
> +{
> + u8 eu_mask[GEN_SS_MASK_SIZE * GEN_MAX_EU_STRIDE] = {};
> + int len = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
How compilcated to kick eu_stride out of kernel struct sseu_dev_info and just calculate it here? Since I don't think it belongs in the kernel struct.
What about ss_stride - is that still in use at this point, or by the end of the series, and could it be dropped?
Regards,
Tvrtko
> + int s, ss, i;
> +
> + for (s = 0; s < sseu->max_slices; s++) {
> + for (ss = 0; ss < sseu->max_subslices; ss++) {
> + int uapi_offset =
> + s * sseu->max_subslices * sseu->eu_stride +
> + ss * sseu->eu_stride;
> + u16 mask = sseu_get_eus(sseu, s, ss);
> +
> + for (i = 0; i < sseu->eu_stride; i++)
> + eu_mask[uapi_offset + i] =
> + (mask >> (BITS_PER_BYTE * i)) & 0xff;
> + }
> + }
> +
> + return copy_to_user(to, eu_mask, len);
> +}
> +
> static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> u32 g_ss_en, u32 c_ss_en, u16 eu_en)
> {
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
> index 4a041f9dc490..43a8f8f98687 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> @@ -57,7 +57,11 @@ struct sseu_dev_info {
> u8 subslice_mask[GEN_SS_MASK_SIZE];
> u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
> u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
> - u8 eu_mask[GEN_SS_MASK_SIZE * GEN_MAX_EU_STRIDE];
> + union {
> + u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
> + u16 xehp[GEN_MAX_DSS];
> + } eu_mask;
> +
> u16 eu_total;
> u8 eu_per_subslice;
> u8 min_eu_in_pool;
> @@ -150,4 +154,7 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
>
> u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
>
> +int intel_sseu_copy_eumask_to_user(void __user *to,
> + const struct sseu_dev_info *sseu);
> +
> #endif /* __INTEL_SSEU_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 7584cec53d5d..16f43bf32a05 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -76,10 +76,10 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
> subslice_mask, subslice_length))
> return -EFAULT;
>
> - if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
> - sizeof(topo) +
> - slice_length + subslice_length),
> - sseu->eu_mask, eu_length))
> + if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
> + sizeof(topo) +
> + slice_length + subslice_length),
> + sseu))
> return -EFAULT;
>
> return total_length;
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/6] drm/i915/sseu: Don't try to store EU mask internally in UAPI format
@ 2022-05-20 9:32 ` Tvrtko Ursulin
0 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2022-05-20 9:32 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel
On 17/05/2022 04:20, Matt Roper wrote:
> Storing the EU mask internally in the same format the I915_QUERY
> topology queries use makes the final copy_to_user() a bit simpler, but
> makes the rest of the driver's SSEU more complicated and harder to
> follow. Let's switch to an internal representation that's more natural:
> Xe_HP platforms will be a simple array of u16 masks, whereas pre-Xe_HP
> platforms will be a two-dimensional array, indexed by [slice][subslice].
> We'll convert to the uapi format only when the query uapi is called.
>
> v2:
> - Drop has_common_ss_eumask. We waste some space repeating identical
> EU masks for every single DSS, but the code is simpler without it.
> (Tvrtko)
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_sseu.c | 77 +++++++++++++++++++---------
> drivers/gpu/drm/i915/gt/intel_sseu.h | 9 +++-
> drivers/gpu/drm/i915/i915_query.c | 8 +--
> 3 files changed, 65 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index ade3e1805782..d89e2e0f05e5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -78,47 +78,76 @@ intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
> return hweight32(intel_sseu_get_subslices(sseu, slice));
> }
>
> -static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
> - int subslice)
> -{
> - int slice_stride = sseu->max_subslices * sseu->eu_stride;
> -
> - return slice * slice_stride + subslice * sseu->eu_stride;
> -}
> -
> static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
> int subslice)
> {
> - int i, offset = sseu_eu_idx(sseu, slice, subslice);
> - u16 eu_mask = 0;
> -
> - for (i = 0; i < sseu->eu_stride; i++)
> - eu_mask |=
> - ((u16)sseu->eu_mask[offset + i]) << (i * BITS_PER_BYTE);
> -
> - return eu_mask;
> + if (sseu->has_xehp_dss) {
> + WARN_ON(slice > 0);
> + return sseu->eu_mask.xehp[subslice];
> + } else {
> + return sseu->eu_mask.hsw[slice][subslice];
> + }
> }
>
> static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
> u16 eu_mask)
> {
> - int i, offset = sseu_eu_idx(sseu, slice, subslice);
> -
> - for (i = 0; i < sseu->eu_stride; i++)
> - sseu->eu_mask[offset + i] =
> - (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
> + if (sseu->has_xehp_dss) {
> + WARN_ON(slice > 0);
> + sseu->eu_mask.xehp[subslice] = eu_mask;
> + } else {
> + eu_mask &= GENMASK(sseu->max_eus_per_subslice - 1, 0);
Is this masking required? Oh I remember.. it's the type expansion! I thought that was wrong. I mean the callers are wrong. Some use u8 for the mask and then do ~mask passing it into u16 here. I don't think this function should account for that but callers should stop passing in garbage.
I had this in my patch:
GEM_WARN_ON(mask && (__fls(mask) >= sseu->max_eus_per_subslice));
And in the callers like:
- sseu_set_eus(sseu, 0, 0, ~disabled_mask);
+ sseu_set_eus(sseu, 0, 0, ~disabled_mask & 0xff);
- sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
+ sseu_set_eus(sseu, s, ss, ~eu_disabled_mask & eu_mask);
> + sseu->eu_mask.hsw[slice][subslice] = eu_mask;
> + }
> }
>
> static u16 compute_eu_total(const struct sseu_dev_info *sseu)
> {
> - u16 i, total = 0;
> + int s, ss, total = 0;
>
> - for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++)
> - total += hweight8(sseu->eu_mask[i]);
> + for (s = 0; s < sseu->max_slices; s++)
> + for (ss = 0; ss < sseu->max_subslices; ss++)
> + if (sseu->has_xehp_dss)
> + total += hweight16(sseu->eu_mask.xehp[ss]);
> + else
> + total += hweight16(sseu->eu_mask.hsw[s][ss]);
>
> return total;
> }
>
> +/**
> + * intel_sseu_copy_eumask_to_user - Copy EU mask into a userspace buffer
> + * @to: Pointer to userspace buffer to copy to
> + * @sseu: SSEU structure containing EU mask to copy
> + *
> + * Copies the EU mask to a userspace buffer in the format expected by
> + * the query ioctl's topology queries.
> + *
> + * Returns the result of the copy_to_user() operation.
> + */
> +int intel_sseu_copy_eumask_to_user(void __user *to,
> + const struct sseu_dev_info *sseu)
> +{
> + u8 eu_mask[GEN_SS_MASK_SIZE * GEN_MAX_EU_STRIDE] = {};
> + int len = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
How compilcated to kick eu_stride out of kernel struct sseu_dev_info and just calculate it here? Since I don't think it belongs in the kernel struct.
What about ss_stride - is that still in use at this point, or by the end of the series, and could it be dropped?
Regards,
Tvrtko
> + int s, ss, i;
> +
> + for (s = 0; s < sseu->max_slices; s++) {
> + for (ss = 0; ss < sseu->max_subslices; ss++) {
> + int uapi_offset =
> + s * sseu->max_subslices * sseu->eu_stride +
> + ss * sseu->eu_stride;
> + u16 mask = sseu_get_eus(sseu, s, ss);
> +
> + for (i = 0; i < sseu->eu_stride; i++)
> + eu_mask[uapi_offset + i] =
> + (mask >> (BITS_PER_BYTE * i)) & 0xff;
> + }
> + }
> +
> + return copy_to_user(to, eu_mask, len);
> +}
> +
> static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> u32 g_ss_en, u32 c_ss_en, u16 eu_en)
> {
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
> index 4a041f9dc490..43a8f8f98687 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> @@ -57,7 +57,11 @@ struct sseu_dev_info {
> u8 subslice_mask[GEN_SS_MASK_SIZE];
> u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
> u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
> - u8 eu_mask[GEN_SS_MASK_SIZE * GEN_MAX_EU_STRIDE];
> + union {
> + u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
> + u16 xehp[GEN_MAX_DSS];
> + } eu_mask;
> +
> u16 eu_total;
> u8 eu_per_subslice;
> u8 min_eu_in_pool;
> @@ -150,4 +154,7 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
>
> u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
>
> +int intel_sseu_copy_eumask_to_user(void __user *to,
> + const struct sseu_dev_info *sseu);
> +
> #endif /* __INTEL_SSEU_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 7584cec53d5d..16f43bf32a05 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -76,10 +76,10 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
> subslice_mask, subslice_length))
> return -EFAULT;
>
> - if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
> - sizeof(topo) +
> - slice_length + subslice_length),
> - sseu->eu_mask, eu_length))
> + if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
> + sizeof(topo) +
> + slice_length + subslice_length),
> + sseu))
> return -EFAULT;
>
> return total_length;
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v3 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi
2022-05-17 15:15 ` [Intel-gfx] " Matt Roper
@ 2022-05-20 10:07 ` Tvrtko Ursulin
-1 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2022-05-20 10:07 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel
On 17/05/2022 16:15, Matt Roper wrote:
> As with EU masks, it's easier to store subslice/DSS masks internally in
> a format that's more natural for the driver to work with, and then only
> covert into the u8[] uapi form when the query ioctl is invoked. Since
> the hardware design changed significantly with Xe_HP, we'll use a union
> to choose between the old "hsw-style" subslice masks or the newer xehp
> mask. HSW-style masks will be stored in an array of u8's, indexed by
> slice (there's never more than 6 subslices per slice on older
> platforms). For Xe_HP and beyond where slices no longer exist, we only
> need a single bitmask. However we already know that this mask is
> eventually going to grow too large for a simple u64 to hold, so we'll
> represent it in a manner that can be operated on by the utilities in
> linux/bitmap.h.
>
> v3:
> - Fix typo: BIT(s) -> BIT(ss) in gen9_sseu_device_status()
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 12 +-
> drivers/gpu/drm/i915/gt/intel_sseu.c | 246 +++++++++++--------
> drivers/gpu/drm/i915/gt/intel_sseu.h | 78 +++---
> drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +--
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +-
> drivers/gpu/drm/i915/i915_getparam.c | 3 +-
> drivers/gpu/drm/i915/i915_query.c | 8 +-
> 9 files changed, 226 insertions(+), 184 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index ab4c5ab28e4d..a3bb73f5d53b 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -1875,6 +1875,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> {
> const struct sseu_dev_info *device = >->info.sseu;
> struct drm_i915_private *i915 = gt->i915;
> + unsigned int dev_subslice_mask = intel_sseu_get_hsw_subslices(device, 0);
>
> /* No zeros in any field. */
> if (!user->slice_mask || !user->subslice_mask ||
> @@ -1901,7 +1902,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> if (user->slice_mask & ~device->slice_mask)
> return -EINVAL;
>
> - if (user->subslice_mask & ~device->subslice_mask[0])
> + if (user->subslice_mask & ~dev_subslice_mask)
> return -EINVAL;
>
> if (user->max_eus_per_subslice > device->max_eus_per_subslice)
> @@ -1915,7 +1916,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> /* Part specific restrictions. */
> if (GRAPHICS_VER(i915) == 11) {
> unsigned int hw_s = hweight8(device->slice_mask);
> - unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
> + unsigned int hw_ss_per_s = hweight8(dev_subslice_mask);
> unsigned int req_s = hweight8(context->slice_mask);
> unsigned int req_ss = hweight8(context->subslice_mask);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 1adbf34c3632..f0acf8518a51 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -674,8 +674,8 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
> if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> return;
>
> - ccs_mask = intel_slicemask_from_dssmask(intel_sseu_get_compute_subslices(&info->sseu),
> - ss_per_ccs);
> + ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
> + ss_per_ccs);
> /*
> * If all DSS in a quadrant are fused off, the corresponding CCS
> * engine is not available for use.
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 034182f85501..2921f510642f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -133,13 +133,6 @@ static const struct intel_mmio_range dg2_lncf_steering_table[] = {
> {},
> };
>
> -static u16 slicemask(struct intel_gt *gt, int count)
> -{
> - u64 dss_mask = intel_sseu_get_subslices(>->info.sseu, 0);
> -
> - return intel_slicemask_from_dssmask(dss_mask, count);
> -}
> -
> int intel_gt_init_mmio(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> @@ -155,9 +148,12 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> */
> if (HAS_MSLICES(i915)) {
> gt->info.mslice_mask =
> - slicemask(gt, GEN_DSS_PER_MSLICE) |
> + intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
> + GEN_DSS_PER_MSLICE);
> + gt->info.mslice_mask |=
> (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> GEN12_MEML3_EN_MASK);
> +
> if (!gt->info.mslice_mask) /* should be impossible! */
> drm_warn(&i915->drm, "mslice mask all zero!\n");
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index d89e2e0f05e5..e1bce8a9044e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -28,54 +28,23 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
> {
> unsigned int i, total = 0;
>
> - for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
> - total += hweight8(sseu->subslice_mask[i]);
> + if (sseu->has_xehp_dss)
> + return bitmap_weight(sseu->subslice_mask.xehp,
> + I915_MAX_SS_FUSE_BITS);
>
> - return total;
> -}
> -
> -static u32
> -sseu_get_subslices(const struct sseu_dev_info *sseu,
> - const u8 *subslice_mask, u8 slice)
> -{
> - int i, offset = slice * sseu->ss_stride;
> - u32 mask = 0;
> -
> - GEM_BUG_ON(slice >= sseu->max_slices);
> -
> - for (i = 0; i < sseu->ss_stride; i++)
> - mask |= (u32)subslice_mask[offset + i] << i * BITS_PER_BYTE;
> -
> - return mask;
> -}
> -
> -u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
> -{
> - return sseu_get_subslices(sseu, sseu->subslice_mask, slice);
> -}
> + for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++)
> + total += hweight8(sseu->subslice_mask.hsw[i]);
>
> -static u32 sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
> -{
> - return sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
> -}
> -
> -u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu)
> -{
> - return sseu_get_subslices(sseu, sseu->compute_subslice_mask, 0);
> -}
> -
> -void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
> - u8 *subslice_mask, u32 ss_mask)
> -{
> - int offset = slice * sseu->ss_stride;
> -
> - memcpy(&subslice_mask[offset], &ss_mask, sseu->ss_stride);
> + return total;
> }
>
> unsigned int
> -intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
> +intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice)
> {
> - return hweight32(intel_sseu_get_subslices(sseu, slice));
> + WARN_ON(sseu->has_xehp_dss);
> + WARN_ON(slice >= sseu->max_slices);
Might as well "if (WARN_ON) return 0" since it's there, to avoid reading
random memmory.
> +
> + return sseu->subslice_mask.hsw[slice];
> }
>
> static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
> @@ -148,32 +117,65 @@ int intel_sseu_copy_eumask_to_user(void __user *to,
> return copy_to_user(to, eu_mask, len);
> }
>
> +/**
> + * intel_sseu_copy_ssmask_to_user - Copy subslice mask into a userspace buffer
> + * @to: Pointer to userspace buffer to copy to
> + * @sseu: SSEU structure containing subslice mask to copy
> + *
> + * Copies the subslice mask to a userspace buffer in the format expected by
> + * the query ioctl's topology queries.
> + *
> + * Returns the result of the copy_to_user() operation.
> + */
> +int intel_sseu_copy_ssmask_to_user(void __user *to,
> + const struct sseu_dev_info *sseu)
> +{
> + u8 ss_mask[GEN_SS_MASK_SIZE] = {};
> + int len = sseu->max_slices * sseu->ss_stride;
Ah yes.. ss_stride. I definitely suggest to eliminate it from the kernel
struct.
> + int s, ss, i;
> +
> + for (s = 0; s < sseu->max_slices; s++) {
> + for (ss = 0; ss < sseu->max_subslices; ss++) {
> + i = s * sseu->ss_stride * BITS_PER_BYTE + ss;
> +
> + if (!intel_sseu_has_subslice(sseu, s, ss))
> + continue;
> +
> + ss_mask[i / BITS_PER_BYTE] |= BIT(i % BITS_PER_BYTE);
> + }
> + }
> +
> + return copy_to_user(to, ss_mask, len);
> +}
> +
> static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> - u32 g_ss_en, u32 c_ss_en, u16 eu_en)
> + u32 ss_en, u16 eu_en)
> {
> u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
> int ss;
>
> - /* g_ss_en/c_ss_en represent entire subslice mask across all slices */
> - GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
> - sizeof(g_ss_en) * BITS_PER_BYTE);
> + sseu->slice_mask |= BIT(0);
> + sseu->subslice_mask.hsw[0] = ss_en & valid_ss_mask;
> +
> + for (ss = 0; ss < sseu->max_subslices; ss++)
> + if (intel_sseu_has_subslice(sseu, 0, ss))
> + sseu_set_eus(sseu, 0, ss, eu_en);
> +
> + sseu->eu_per_subslice = hweight16(eu_en);
> + sseu->eu_total = compute_eu_total(sseu);
> +}
> +
> +static void xehp_compute_sseu_info(struct sseu_dev_info *sseu,
> + u16 eu_en)
> +{
> + int ss;
>
> sseu->slice_mask |= BIT(0);
>
> - /*
> - * XeHP introduces the concept of compute vs geometry DSS. To reduce
> - * variation between GENs around subslice usage, store a mask for both
> - * the geometry and compute enabled masks since userspace will need to
> - * be able to query these masks independently. Also compute a total
> - * enabled subslice count for the purposes of selecting subslices to
> - * use in a particular GEM context.
> - */
> - intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
> - c_ss_en & valid_ss_mask);
> - intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
> - g_ss_en & valid_ss_mask);
> - intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
> - (g_ss_en | c_ss_en) & valid_ss_mask);
> + bitmap_or(sseu->subslice_mask.xehp,
> + sseu->compute_subslice_mask.xehp,
> + sseu->geometry_subslice_mask.xehp,
> + I915_MAX_SS_FUSE_BITS);
I still think it would have been better to have less coupling between
the datatype and I915_MAX_SS_FUSE_BITS define throughout (less chance of
things going out of sync), which can be achieved by adding a BITMAP_BITS
macro as mentioned before, but up to you at this point.
>
> for (ss = 0; ss < sseu->max_subslices; ss++)
> if (intel_sseu_has_subslice(sseu, 0, ss))
> @@ -183,11 +185,31 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> sseu->eu_total = compute_eu_total(sseu);
> }
>
> +static void
> +xehp_load_dss_mask(struct intel_uncore *uncore,
> + intel_sseu_ss_mask_t *ssmask,
> + int numregs,
> + ...)
> +{
> + va_list argp;
> + u32 fuse_val[I915_MAX_SS_FUSE_REGS] = {};
> + int i;
> +
> + if (WARN_ON(numregs > I915_MAX_SS_FUSE_REGS))
> + numregs = I915_MAX_SS_FUSE_REGS;
> +
> + va_start(argp, numregs);
> + for (i = 0; i < numregs; i++)
> + fuse_val[i] = intel_uncore_read(uncore, va_arg(argp, i915_reg_t));
> + va_end(argp);
> +
> + bitmap_from_arr32(ssmask->xehp, fuse_val, numregs * 32);
> +}
> +
> static void xehp_sseu_info_init(struct intel_gt *gt)
> {
> struct sseu_dev_info *sseu = >->info.sseu;
> struct intel_uncore *uncore = gt->uncore;
> - u32 g_dss_en, c_dss_en = 0;
> u16 eu_en = 0;
> u8 eu_en_fuse;
> int eu;
> @@ -201,8 +223,10 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
> intel_sseu_set_info(sseu, 1, 32, 16);
> sseu->has_xehp_dss = 1;
>
> - g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
> - c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
> + xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 1,
> + GEN12_GT_GEOMETRY_DSS_ENABLE);
> + xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 1,
> + GEN12_GT_COMPUTE_DSS_ENABLE);
>
> eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
>
> @@ -210,7 +234,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
> if (eu_en_fuse & BIT(eu))
> eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
>
> - gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
> + xehp_compute_sseu_info(sseu, eu_en);
> }
>
> static void gen12_sseu_info_init(struct intel_gt *gt)
> @@ -250,7 +274,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
> if (eu_en_fuse & BIT(eu))
> eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
>
> - gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
> + gen11_compute_sseu_info(sseu, g_dss_en, eu_en);
>
> /* TGL only supports slice-level power gating */
> sseu->has_slice_pg = 1;
> @@ -284,7 +308,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
> eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
> GEN11_EU_DIS_MASK);
>
> - gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
> + gen11_compute_sseu_info(sseu, ss_en, eu_en);
>
> /* ICL has no power gating restrictions. */
> sseu->has_slice_pg = 1;
> @@ -296,7 +320,6 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> {
> struct sseu_dev_info *sseu = >->info.sseu;
> u32 fuse;
> - u8 subslice_mask = 0;
>
> fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT);
>
> @@ -310,7 +333,7 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
> CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
>
> - subslice_mask |= BIT(0);
> + sseu->subslice_mask.hsw[0] |= BIT(0);
> sseu_set_eus(sseu, 0, 0, ~disabled_mask);
> }
>
> @@ -321,12 +344,10 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
> CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
>
> - subslice_mask |= BIT(1);
> + sseu->subslice_mask.hsw[0] |= BIT(1);
> sseu_set_eus(sseu, 0, 1, ~disabled_mask);
> }
>
> - intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask, subslice_mask);
> -
> sseu->eu_total = compute_eu_total(sseu);
>
> /*
> @@ -381,8 +402,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
> /* skip disabled slice */
> continue;
>
> - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> - subslice_mask);
> + sseu->subslice_mask.hsw[s] = subslice_mask;
>
> eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> @@ -439,8 +459,8 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
> sseu->has_eu_pg = sseu->eu_per_subslice > 2;
>
> if (IS_GEN9_LP(i915)) {
> -#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
> - info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
> +#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask.hsw[0] & BIT(ss)))
> + info->has_pooled_eu = hweight8(sseu->subslice_mask.hsw[0]) == 3;
>
> sseu->min_eu_in_pool = 0;
> if (info->has_pooled_eu) {
> @@ -494,8 +514,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
> /* skip disabled slice */
> continue;
>
> - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> - subslice_mask);
> + sseu->subslice_mask.hsw[s] = subslice_mask;
>
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> u8 eu_disabled_mask;
> @@ -592,8 +611,7 @@ static void hsw_sseu_info_init(struct intel_gt *gt)
> sseu->eu_per_subslice);
>
> for (s = 0; s < sseu->max_slices; s++) {
> - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> - subslice_mask);
> + sseu->subslice_mask.hsw[s] = subslice_mask;
>
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> sseu_set_eus(sseu, s, ss,
> @@ -682,7 +700,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
> */
> if (GRAPHICS_VER(i915) == 11 &&
> slices == 1 &&
> - subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
> + subslices > min_t(u8, 4, hweight8(sseu->subslice_mask.hsw[0]) / 2)) {
> GEM_BUG_ON(subslices & 1);
>
> subslice_pg = false;
> @@ -748,14 +766,25 @@ void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
> {
> int s;
>
> - drm_printf(p, "slice total: %u, mask=%04x\n",
> - hweight8(sseu->slice_mask), sseu->slice_mask);
> - drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
> - for (s = 0; s < sseu->max_slices; s++) {
> - drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
> - s, intel_sseu_subslices_per_slice(sseu, s),
> - intel_sseu_get_subslices(sseu, s));
> + if (sseu->has_xehp_dss) {
> + drm_printf(p, "subslice total: %u\n",
> + intel_sseu_subslice_total(sseu));
> + drm_printf(p, "subslice mask=%*pb\n", I915_MAX_SS_FUSE_BITS,
> + sseu->subslice_mask.xehp);
Do you perhaps want to use the DSS terminology here? Any point to dump
compute and geometry separately?
> + } else {
> + drm_printf(p, "slice total: %u, mask=%04x\n",
> + hweight8(sseu->slice_mask), sseu->slice_mask);
> + drm_printf(p, "subslice total: %u\n",
> + intel_sseu_subslice_total(sseu));
> +
> + for (s = 0; s < sseu->max_slices; s++) {
> + u8 ss_mask = sseu->subslice_mask.hsw[s];
> +
> + drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
> + s, hweight8(ss_mask), ss_mask);
> + }
> }
> +
> drm_printf(p, "EU total: %u\n", sseu->eu_total);
> drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
> drm_printf(p, "has slice power gating: %s\n",
> @@ -772,9 +801,10 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
> int s, ss;
>
> for (s = 0; s < sseu->max_slices; s++) {
> + u8 ss_mask = sseu->subslice_mask.hsw[s];
> +
> drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
> - s, intel_sseu_subslices_per_slice(sseu, s),
> - intel_sseu_get_subslices(sseu, s));
> + s, hweight8(ss_mask), ss_mask);
>
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> u16 enabled_eus = sseu_get_eus(sseu, s, ss);
> @@ -788,16 +818,14 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
> static void sseu_print_xehp_topology(const struct sseu_dev_info *sseu,
> struct drm_printer *p)
> {
> - u32 g_dss_mask = sseu_get_geometry_subslices(sseu);
> - u32 c_dss_mask = intel_sseu_get_compute_subslices(sseu);
> int dss;
>
> for (dss = 0; dss < sseu->max_subslices; dss++) {
> u16 enabled_eus = sseu_get_eus(sseu, 0, dss);
>
> drm_printf(p, "DSS_%02d: G:%3s C:%3s, %2u EUs (0x%04hx)\n", dss,
> - str_yes_no(g_dss_mask & BIT(dss)),
> - str_yes_no(c_dss_mask & BIT(dss)),
> + str_yes_no(test_bit(dss, sseu->geometry_subslice_mask.xehp)),
> + str_yes_no(test_bit(dss, sseu->compute_subslice_mask.xehp)),
> hweight16(enabled_eus), enabled_eus);
> }
> }
> @@ -815,20 +843,40 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
> }
> }
>
> -u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice)
> +void intel_sseu_print_ss_info(const char* type,
> + const struct sseu_dev_info *sseu,
> + struct seq_file *m)
> +{
> + int s;
> +
> + if (sseu->has_xehp_dss)
> + seq_printf(m, " %s Subslices: %u\n", type,
> + bitmap_weight(sseu->subslice_mask.xehp,
> + I915_MAX_SS_FUSE_BITS));
Same question on whether to use DSS and log them separately.
> + else
> + for (s = 0; s < fls(sseu->slice_mask); s++)
> + seq_printf(m, " %s Slice%i subslices: %u\n", type,
> + s, hweight8(sseu->subslice_mask.hsw[s]));
> +}
> +
> +u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask,
> + int dss_per_slice)
> {
> + intel_sseu_ss_mask_t per_slice_mask = {};
> u16 slice_mask = 0;
> int i;
>
> - WARN_ON(sizeof(dss_mask) * 8 / dss_per_slice > 8 * sizeof(slice_mask));
> + WARN_ON(DIV_ROUND_UP(I915_MAX_SS_FUSE_BITS, dss_per_slice) >
> + 8 * sizeof(slice_mask));
>
> - for (i = 0; dss_mask; i++) {
> - if (dss_mask & GENMASK(dss_per_slice - 1, 0))
> + bitmap_fill(per_slice_mask.xehp, dss_per_slice);
> + for (i = 0; !bitmap_empty(dss_mask.xehp, I915_MAX_SS_FUSE_BITS); i++) {
> + if (bitmap_intersects(dss_mask.xehp, per_slice_mask.xehp, dss_per_slice))
> slice_mask |= BIT(i);
>
> - dss_mask >>= dss_per_slice;
> + bitmap_shift_right(dss_mask.xehp, dss_mask.xehp, dss_per_slice,
> + I915_MAX_SS_FUSE_BITS);
> }
>
> return slice_mask;
> }
> -
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
> index 43a8f8f98687..7fbb9276a1c2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> @@ -25,12 +25,16 @@ struct drm_printer;
> /*
> * Maximum number of subslices that can exist within a HSW-style slice. This
> * is only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the
> - * GEN_MAX_DSS value below).
> + * I915_MAX_SS_FUSE_BITS value below).
> */
> #define GEN_MAX_SS_PER_HSW_SLICE 6
>
> -/* Maximum number of DSS on newer platforms (Xe_HP and beyond). */
> -#define GEN_MAX_DSS 32
> +/*
> + * Maximum number of 32-bit registers used by hardware to express the
> + * enabled/disabled subslices.
> + */
> +#define I915_MAX_SS_FUSE_REGS 1
> +#define I915_MAX_SS_FUSE_BITS (I915_MAX_SS_FUSE_REGS * 32)
>
> /* Maximum number of EUs that can exist within a subslice or DSS. */
> #define GEN_MAX_EUS_PER_SS 16
> @@ -38,7 +42,7 @@ struct drm_printer;
> #define SSEU_MAX(a, b) ((a) > (b) ? (a) : (b))
>
> /* The maximum number of bits needed to express each subslice/DSS independently */
> -#define GEN_SS_MASK_SIZE SSEU_MAX(GEN_MAX_DSS, \
> +#define GEN_SS_MASK_SIZE SSEU_MAX(I915_MAX_SS_FUSE_BITS, \
> GEN_MAX_HSW_SLICES * GEN_MAX_SS_PER_HSW_SLICE)
>
> #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
> @@ -49,17 +53,24 @@ struct drm_printer;
> #define GEN_DSS_PER_CSLICE 8
> #define GEN_DSS_PER_MSLICE 8
>
> -#define GEN_MAX_GSLICES (GEN_MAX_DSS / GEN_DSS_PER_GSLICE)
> -#define GEN_MAX_CSLICES (GEN_MAX_DSS / GEN_DSS_PER_CSLICE)
> +#define GEN_MAX_GSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_GSLICE)
> +#define GEN_MAX_CSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_CSLICE)
> +
> +typedef union {
> + u8 hsw[GEN_MAX_HSW_SLICES];
> +
> + /* Bitmap compatible with linux/bitmap.h; may exceed size of u64 */
> + unsigned long xehp[BITS_TO_LONGS(I915_MAX_SS_FUSE_BITS)];
> +} intel_sseu_ss_mask_t;
>
> struct sseu_dev_info {
> u8 slice_mask;
> - u8 subslice_mask[GEN_SS_MASK_SIZE];
> - u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
> - u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
> + intel_sseu_ss_mask_t subslice_mask;
> + intel_sseu_ss_mask_t geometry_subslice_mask;
> + intel_sseu_ss_mask_t compute_subslice_mask;
> union {
> u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
> - u16 xehp[GEN_MAX_DSS];
> + u16 xehp[I915_MAX_SS_FUSE_BITS];
> } eu_mask;
>
> u16 eu_total;
> @@ -100,7 +111,7 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
> {
> struct intel_sseu value = {
> .slice_mask = sseu->slice_mask,
> - .subslice_mask = sseu->subslice_mask[0],
> + .subslice_mask = sseu->subslice_mask.hsw[0],
> .min_eus_per_subslice = sseu->max_eus_per_subslice,
> .max_eus_per_subslice = sseu->max_eus_per_subslice,
> };
> @@ -112,18 +123,23 @@ static inline bool
> intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
> int subslice)
> {
> - u8 mask;
> - int ss_idx = subslice / BITS_PER_BYTE;
> -
> - if (slice >= sseu->max_slices ||
> - subslice >= sseu->max_subslices)
> - return false;
> -
> - GEM_BUG_ON(ss_idx >= sseu->ss_stride);
Range checks are not interesting any more?
> -
> - mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx];
> + if (sseu->has_xehp_dss)
> + return test_bit(subslice, sseu->subslice_mask.xehp);
> + else
> + return sseu->subslice_mask.hsw[slice] & BIT(subslice);
> +}
>
> - return mask & BIT(subslice % BITS_PER_BYTE);
> +/*
> + * Used to obtain the index of the first DSS. Can start searching from the
> + * beginning of a specific dss group (e.g., gslice, cslice, etc.) if
> + * groupsize and groupnum are non-zero.
> + */
> +static inline unsigned int
> +intel_sseu_find_first_xehp_dss(const struct sseu_dev_info *sseu, int groupsize,
> + int groupnum)
> +{
> + return find_next_bit(sseu->subslice_mask.xehp, I915_MAX_SS_FUSE_BITS,
> + groupnum * groupsize);
> }
>
> void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
> @@ -133,14 +149,10 @@ unsigned int
> intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
>
> unsigned int
> -intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
> -
> -u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
> +intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice);
>
> -u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
> -
> -void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
> - u8 *subslice_mask, u32 ss_mask);
> +intel_sseu_ss_mask_t
> +intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
>
> void intel_sseu_info_init(struct intel_gt *gt);
>
> @@ -152,9 +164,15 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
> const struct sseu_dev_info *sseu,
> struct drm_printer *p);
>
> -u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
> +u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask, int dss_per_slice);
>
> int intel_sseu_copy_eumask_to_user(void __user *to,
> const struct sseu_dev_info *sseu);
> +int intel_sseu_copy_ssmask_to_user(void __user *to,
> + const struct sseu_dev_info *sseu);
> +
> +void intel_sseu_print_ss_info(const char* type,
> + const struct sseu_dev_info *sseu,
> + struct seq_file *m);
>
> #endif /* __INTEL_SSEU_H__ */
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> index 2d5d011e01db..c2ee5e1826b5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> @@ -4,6 +4,7 @@
> * Copyright © 2020 Intel Corporation
> */
>
> +#include <linux/bitmap.h>
> #include <linux/string_helpers.h>
>
> #include "i915_drv.h"
> @@ -11,14 +12,6 @@
> #include "intel_gt_regs.h"
> #include "intel_sseu_debugfs.h"
>
> -static void sseu_copy_subslices(const struct sseu_dev_info *sseu,
> - int slice, u8 *to_mask)
> -{
> - int offset = slice * sseu->ss_stride;
> -
> - memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
> -}
> -
> static void cherryview_sseu_device_status(struct intel_gt *gt,
> struct sseu_dev_info *sseu)
> {
> @@ -41,7 +34,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt,
> continue;
>
> sseu->slice_mask = BIT(0);
> - sseu->subslice_mask[0] |= BIT(ss);
> + sseu->subslice_mask.hsw[0] |= BIT(ss);
> eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
> ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
> ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
> @@ -92,7 +85,7 @@ static void gen11_sseu_device_status(struct intel_gt *gt,
> continue;
>
> sseu->slice_mask |= BIT(s);
> - sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
> + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
>
> for (ss = 0; ss < info->sseu.max_subslices; ss++) {
> unsigned int eu_cnt;
> @@ -147,21 +140,17 @@ static void gen9_sseu_device_status(struct intel_gt *gt,
> sseu->slice_mask |= BIT(s);
>
> if (IS_GEN9_BC(gt->i915))
> - sseu_copy_subslices(&info->sseu, s,
> - sseu->subslice_mask);
> + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
>
> for (ss = 0; ss < info->sseu.max_subslices; ss++) {
> unsigned int eu_cnt;
> - u8 ss_idx = s * info->sseu.ss_stride +
> - ss / BITS_PER_BYTE;
>
> if (IS_GEN9_LP(gt->i915)) {
> if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> /* skip disabled subslice */
> continue;
>
> - sseu->subslice_mask[ss_idx] |=
> - BIT(ss % BITS_PER_BYTE);
> + sseu->subslice_mask.hsw[s] |= BIT(ss);
> }
>
> eu_cnt = eu_reg[2 * s + ss / 2] & eu_mask[ss % 2];
> @@ -188,8 +177,7 @@ static void bdw_sseu_device_status(struct intel_gt *gt,
> if (sseu->slice_mask) {
> sseu->eu_per_subslice = info->sseu.eu_per_subslice;
> for (s = 0; s < fls(sseu->slice_mask); s++)
> - sseu_copy_subslices(&info->sseu, s,
> - sseu->subslice_mask);
> + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
> sseu->eu_total = sseu->eu_per_subslice *
> intel_sseu_subslice_total(sseu);
>
> @@ -208,7 +196,6 @@ static void i915_print_sseu_info(struct seq_file *m,
> const struct sseu_dev_info *sseu)
> {
> const char *type = is_available_info ? "Available" : "Enabled";
> - int s;
>
> seq_printf(m, " %s Slice Mask: %04x\n", type,
> sseu->slice_mask);
> @@ -216,10 +203,7 @@ static void i915_print_sseu_info(struct seq_file *m,
> hweight8(sseu->slice_mask));
> seq_printf(m, " %s Subslice Total: %u\n", type,
> intel_sseu_subslice_total(sseu));
> - for (s = 0; s < fls(sseu->slice_mask); s++) {
> - seq_printf(m, " %s Slice%i subslices: %u\n", type,
> - s, intel_sseu_subslices_per_slice(sseu, s));
> - }
> + intel_sseu_print_ss_info(type, sseu, m);
> seq_printf(m, " %s EU Total: %u\n", type,
> sseu->eu_total);
> seq_printf(m, " %s EU Per Subslice: %u\n", type,
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 756807c4b405..fc6274708f8e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -948,8 +948,8 @@ gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> * on s/ss combo, the read should be done with read_subslice_reg.
> */
> slice = ffs(sseu->slice_mask) - 1;
> - GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
> - subslice = ffs(intel_sseu_get_subslices(sseu, slice));
> + GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw));
> + subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice));
> GEM_BUG_ON(!subslice);
> subslice--;
>
> @@ -1087,11 +1087,10 @@ static void
> icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> const struct sseu_dev_info *sseu = >->info.sseu;
> - unsigned int slice, subslice;
> + unsigned int subslice;
>
> GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
> GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
> - slice = 0;
>
> /*
> * Although a platform may have subslices, we need to always steer
> @@ -1102,7 +1101,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> * one of the higher subslices, we run the risk of reading back 0's or
> * random garbage.
> */
> - subslice = __ffs(intel_sseu_get_subslices(sseu, slice));
> + subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0));
>
> /*
> * If the subslice we picked above also steers us to a valid L3 bank,
> @@ -1112,7 +1111,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> if (gt->info.l3bank_mask & BIT(subslice))
> gt->steering_table[L3BANK] = NULL;
>
> - __add_mcr_wa(gt, wal, slice, subslice);
> + __add_mcr_wa(gt, wal, 0, subslice);
> }
>
> static void
> @@ -1120,7 +1119,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> const struct sseu_dev_info *sseu = >->info.sseu;
> unsigned long slice, subslice = 0, slice_mask = 0;
> - u64 dss_mask = 0;
> u32 lncf_mask = 0;
> int i;
>
> @@ -1151,8 +1149,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> */
>
> /* Find the potential gslice candidates */
> - dss_mask = intel_sseu_get_subslices(sseu, 0);
> - slice_mask = intel_slicemask_from_dssmask(dss_mask, GEN_DSS_PER_GSLICE);
> + slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask,
> + GEN_DSS_PER_GSLICE);
>
> /*
> * Find the potential LNCF candidates. Either LNCF within a valid
> @@ -1177,9 +1175,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> }
>
> slice = __ffs(slice_mask);
> - subslice = __ffs(dss_mask >> (slice * GEN_DSS_PER_GSLICE));
> + subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice);
> WARN_ON(subslice > GEN_DSS_PER_GSLICE);
> - WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0);
>
> __add_mcr_wa(gt, wal, slice, subslice);
>
> @@ -2030,9 +2027,8 @@ engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>
> static bool needs_wa_1308578152(struct intel_engine_cs *engine)
> {
> - u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0);
> -
> - return (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0;
> + return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >
> + GEN_DSS_PER_GSLICE;
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
> index ac9767c56619..6fd15b39570c 100644
> --- a/drivers/gpu/drm/i915/i915_getparam.c
> +++ b/drivers/gpu/drm/i915/i915_getparam.c
> @@ -162,8 +162,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
> return -EINVAL;
>
> /* Only copy bits from the first slice */
> - memcpy(&value, sseu->subslice_mask,
> - min(sseu->ss_stride, (u8)sizeof(value)));
> + value = intel_sseu_get_hsw_subslices(sseu, 0);
> if (!value)
> return -ENODEV;
> break;
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 16f43bf32a05..9afa6d1eaf95 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -31,7 +31,7 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
>
> static int fill_topology_info(const struct sseu_dev_info *sseu,
> struct drm_i915_query_item *query_item,
> - const u8 *subslice_mask)
> + intel_sseu_ss_mask_t subslice_mask)
> {
> struct drm_i915_query_topology_info topo;
> u32 slice_length, subslice_length, eu_length, total_length;
> @@ -71,9 +71,9 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
> &sseu->slice_mask, slice_length))
> return -EFAULT;
>
> - if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
> - sizeof(topo) + slice_length),
> - subslice_mask, subslice_length))
> + if (intel_sseu_copy_ssmask_to_user(u64_to_user_ptr(query_item->data_ptr +
> + sizeof(topo) + slice_length),
> + sseu))
> return -EFAULT;
>
> if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
Apart from the comments in this round I think I am happy with how it all
looks. I am happy to provide acks once the main changes I suggested are
implemented and couple questions answered. But I would prefer if you
would be able to find someone else for a more detailed review.
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] [PATCH v3 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi
@ 2022-05-20 10:07 ` Tvrtko Ursulin
0 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2022-05-20 10:07 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel
On 17/05/2022 16:15, Matt Roper wrote:
> As with EU masks, it's easier to store subslice/DSS masks internally in
> a format that's more natural for the driver to work with, and then only
> covert into the u8[] uapi form when the query ioctl is invoked. Since
> the hardware design changed significantly with Xe_HP, we'll use a union
> to choose between the old "hsw-style" subslice masks or the newer xehp
> mask. HSW-style masks will be stored in an array of u8's, indexed by
> slice (there's never more than 6 subslices per slice on older
> platforms). For Xe_HP and beyond where slices no longer exist, we only
> need a single bitmask. However we already know that this mask is
> eventually going to grow too large for a simple u64 to hold, so we'll
> represent it in a manner that can be operated on by the utilities in
> linux/bitmap.h.
>
> v3:
> - Fix typo: BIT(s) -> BIT(ss) in gen9_sseu_device_status()
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 12 +-
> drivers/gpu/drm/i915/gt/intel_sseu.c | 246 +++++++++++--------
> drivers/gpu/drm/i915/gt/intel_sseu.h | 78 +++---
> drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +--
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +-
> drivers/gpu/drm/i915/i915_getparam.c | 3 +-
> drivers/gpu/drm/i915/i915_query.c | 8 +-
> 9 files changed, 226 insertions(+), 184 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index ab4c5ab28e4d..a3bb73f5d53b 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -1875,6 +1875,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> {
> const struct sseu_dev_info *device = >->info.sseu;
> struct drm_i915_private *i915 = gt->i915;
> + unsigned int dev_subslice_mask = intel_sseu_get_hsw_subslices(device, 0);
>
> /* No zeros in any field. */
> if (!user->slice_mask || !user->subslice_mask ||
> @@ -1901,7 +1902,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> if (user->slice_mask & ~device->slice_mask)
> return -EINVAL;
>
> - if (user->subslice_mask & ~device->subslice_mask[0])
> + if (user->subslice_mask & ~dev_subslice_mask)
> return -EINVAL;
>
> if (user->max_eus_per_subslice > device->max_eus_per_subslice)
> @@ -1915,7 +1916,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> /* Part specific restrictions. */
> if (GRAPHICS_VER(i915) == 11) {
> unsigned int hw_s = hweight8(device->slice_mask);
> - unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
> + unsigned int hw_ss_per_s = hweight8(dev_subslice_mask);
> unsigned int req_s = hweight8(context->slice_mask);
> unsigned int req_ss = hweight8(context->subslice_mask);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 1adbf34c3632..f0acf8518a51 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -674,8 +674,8 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
> if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> return;
>
> - ccs_mask = intel_slicemask_from_dssmask(intel_sseu_get_compute_subslices(&info->sseu),
> - ss_per_ccs);
> + ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
> + ss_per_ccs);
> /*
> * If all DSS in a quadrant are fused off, the corresponding CCS
> * engine is not available for use.
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 034182f85501..2921f510642f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -133,13 +133,6 @@ static const struct intel_mmio_range dg2_lncf_steering_table[] = {
> {},
> };
>
> -static u16 slicemask(struct intel_gt *gt, int count)
> -{
> - u64 dss_mask = intel_sseu_get_subslices(>->info.sseu, 0);
> -
> - return intel_slicemask_from_dssmask(dss_mask, count);
> -}
> -
> int intel_gt_init_mmio(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> @@ -155,9 +148,12 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> */
> if (HAS_MSLICES(i915)) {
> gt->info.mslice_mask =
> - slicemask(gt, GEN_DSS_PER_MSLICE) |
> + intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
> + GEN_DSS_PER_MSLICE);
> + gt->info.mslice_mask |=
> (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> GEN12_MEML3_EN_MASK);
> +
> if (!gt->info.mslice_mask) /* should be impossible! */
> drm_warn(&i915->drm, "mslice mask all zero!\n");
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index d89e2e0f05e5..e1bce8a9044e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -28,54 +28,23 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
> {
> unsigned int i, total = 0;
>
> - for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
> - total += hweight8(sseu->subslice_mask[i]);
> + if (sseu->has_xehp_dss)
> + return bitmap_weight(sseu->subslice_mask.xehp,
> + I915_MAX_SS_FUSE_BITS);
>
> - return total;
> -}
> -
> -static u32
> -sseu_get_subslices(const struct sseu_dev_info *sseu,
> - const u8 *subslice_mask, u8 slice)
> -{
> - int i, offset = slice * sseu->ss_stride;
> - u32 mask = 0;
> -
> - GEM_BUG_ON(slice >= sseu->max_slices);
> -
> - for (i = 0; i < sseu->ss_stride; i++)
> - mask |= (u32)subslice_mask[offset + i] << i * BITS_PER_BYTE;
> -
> - return mask;
> -}
> -
> -u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
> -{
> - return sseu_get_subslices(sseu, sseu->subslice_mask, slice);
> -}
> + for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++)
> + total += hweight8(sseu->subslice_mask.hsw[i]);
>
> -static u32 sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
> -{
> - return sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
> -}
> -
> -u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu)
> -{
> - return sseu_get_subslices(sseu, sseu->compute_subslice_mask, 0);
> -}
> -
> -void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
> - u8 *subslice_mask, u32 ss_mask)
> -{
> - int offset = slice * sseu->ss_stride;
> -
> - memcpy(&subslice_mask[offset], &ss_mask, sseu->ss_stride);
> + return total;
> }
>
> unsigned int
> -intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
> +intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice)
> {
> - return hweight32(intel_sseu_get_subslices(sseu, slice));
> + WARN_ON(sseu->has_xehp_dss);
> + WARN_ON(slice >= sseu->max_slices);
Might as well "if (WARN_ON) return 0" since it's there, to avoid reading
random memmory.
> +
> + return sseu->subslice_mask.hsw[slice];
> }
>
> static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
> @@ -148,32 +117,65 @@ int intel_sseu_copy_eumask_to_user(void __user *to,
> return copy_to_user(to, eu_mask, len);
> }
>
> +/**
> + * intel_sseu_copy_ssmask_to_user - Copy subslice mask into a userspace buffer
> + * @to: Pointer to userspace buffer to copy to
> + * @sseu: SSEU structure containing subslice mask to copy
> + *
> + * Copies the subslice mask to a userspace buffer in the format expected by
> + * the query ioctl's topology queries.
> + *
> + * Returns the result of the copy_to_user() operation.
> + */
> +int intel_sseu_copy_ssmask_to_user(void __user *to,
> + const struct sseu_dev_info *sseu)
> +{
> + u8 ss_mask[GEN_SS_MASK_SIZE] = {};
> + int len = sseu->max_slices * sseu->ss_stride;
Ah yes.. ss_stride. I definitely suggest to eliminate it from the kernel
struct.
> + int s, ss, i;
> +
> + for (s = 0; s < sseu->max_slices; s++) {
> + for (ss = 0; ss < sseu->max_subslices; ss++) {
> + i = s * sseu->ss_stride * BITS_PER_BYTE + ss;
> +
> + if (!intel_sseu_has_subslice(sseu, s, ss))
> + continue;
> +
> + ss_mask[i / BITS_PER_BYTE] |= BIT(i % BITS_PER_BYTE);
> + }
> + }
> +
> + return copy_to_user(to, ss_mask, len);
> +}
> +
> static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> - u32 g_ss_en, u32 c_ss_en, u16 eu_en)
> + u32 ss_en, u16 eu_en)
> {
> u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
> int ss;
>
> - /* g_ss_en/c_ss_en represent entire subslice mask across all slices */
> - GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
> - sizeof(g_ss_en) * BITS_PER_BYTE);
> + sseu->slice_mask |= BIT(0);
> + sseu->subslice_mask.hsw[0] = ss_en & valid_ss_mask;
> +
> + for (ss = 0; ss < sseu->max_subslices; ss++)
> + if (intel_sseu_has_subslice(sseu, 0, ss))
> + sseu_set_eus(sseu, 0, ss, eu_en);
> +
> + sseu->eu_per_subslice = hweight16(eu_en);
> + sseu->eu_total = compute_eu_total(sseu);
> +}
> +
> +static void xehp_compute_sseu_info(struct sseu_dev_info *sseu,
> + u16 eu_en)
> +{
> + int ss;
>
> sseu->slice_mask |= BIT(0);
>
> - /*
> - * XeHP introduces the concept of compute vs geometry DSS. To reduce
> - * variation between GENs around subslice usage, store a mask for both
> - * the geometry and compute enabled masks since userspace will need to
> - * be able to query these masks independently. Also compute a total
> - * enabled subslice count for the purposes of selecting subslices to
> - * use in a particular GEM context.
> - */
> - intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
> - c_ss_en & valid_ss_mask);
> - intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
> - g_ss_en & valid_ss_mask);
> - intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
> - (g_ss_en | c_ss_en) & valid_ss_mask);
> + bitmap_or(sseu->subslice_mask.xehp,
> + sseu->compute_subslice_mask.xehp,
> + sseu->geometry_subslice_mask.xehp,
> + I915_MAX_SS_FUSE_BITS);
I still think it would have been better to have less coupling between
the datatype and I915_MAX_SS_FUSE_BITS define throughout (less chance of
things going out of sync), which can be achieved by adding a BITMAP_BITS
macro as mentioned before, but up to you at this point.
>
> for (ss = 0; ss < sseu->max_subslices; ss++)
> if (intel_sseu_has_subslice(sseu, 0, ss))
> @@ -183,11 +185,31 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> sseu->eu_total = compute_eu_total(sseu);
> }
>
> +static void
> +xehp_load_dss_mask(struct intel_uncore *uncore,
> + intel_sseu_ss_mask_t *ssmask,
> + int numregs,
> + ...)
> +{
> + va_list argp;
> + u32 fuse_val[I915_MAX_SS_FUSE_REGS] = {};
> + int i;
> +
> + if (WARN_ON(numregs > I915_MAX_SS_FUSE_REGS))
> + numregs = I915_MAX_SS_FUSE_REGS;
> +
> + va_start(argp, numregs);
> + for (i = 0; i < numregs; i++)
> + fuse_val[i] = intel_uncore_read(uncore, va_arg(argp, i915_reg_t));
> + va_end(argp);
> +
> + bitmap_from_arr32(ssmask->xehp, fuse_val, numregs * 32);
> +}
> +
> static void xehp_sseu_info_init(struct intel_gt *gt)
> {
> struct sseu_dev_info *sseu = >->info.sseu;
> struct intel_uncore *uncore = gt->uncore;
> - u32 g_dss_en, c_dss_en = 0;
> u16 eu_en = 0;
> u8 eu_en_fuse;
> int eu;
> @@ -201,8 +223,10 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
> intel_sseu_set_info(sseu, 1, 32, 16);
> sseu->has_xehp_dss = 1;
>
> - g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
> - c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
> + xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 1,
> + GEN12_GT_GEOMETRY_DSS_ENABLE);
> + xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 1,
> + GEN12_GT_COMPUTE_DSS_ENABLE);
>
> eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
>
> @@ -210,7 +234,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
> if (eu_en_fuse & BIT(eu))
> eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
>
> - gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
> + xehp_compute_sseu_info(sseu, eu_en);
> }
>
> static void gen12_sseu_info_init(struct intel_gt *gt)
> @@ -250,7 +274,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
> if (eu_en_fuse & BIT(eu))
> eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
>
> - gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
> + gen11_compute_sseu_info(sseu, g_dss_en, eu_en);
>
> /* TGL only supports slice-level power gating */
> sseu->has_slice_pg = 1;
> @@ -284,7 +308,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
> eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
> GEN11_EU_DIS_MASK);
>
> - gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
> + gen11_compute_sseu_info(sseu, ss_en, eu_en);
>
> /* ICL has no power gating restrictions. */
> sseu->has_slice_pg = 1;
> @@ -296,7 +320,6 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> {
> struct sseu_dev_info *sseu = >->info.sseu;
> u32 fuse;
> - u8 subslice_mask = 0;
>
> fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT);
>
> @@ -310,7 +333,7 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
> CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
>
> - subslice_mask |= BIT(0);
> + sseu->subslice_mask.hsw[0] |= BIT(0);
> sseu_set_eus(sseu, 0, 0, ~disabled_mask);
> }
>
> @@ -321,12 +344,10 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
> CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
>
> - subslice_mask |= BIT(1);
> + sseu->subslice_mask.hsw[0] |= BIT(1);
> sseu_set_eus(sseu, 0, 1, ~disabled_mask);
> }
>
> - intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask, subslice_mask);
> -
> sseu->eu_total = compute_eu_total(sseu);
>
> /*
> @@ -381,8 +402,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
> /* skip disabled slice */
> continue;
>
> - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> - subslice_mask);
> + sseu->subslice_mask.hsw[s] = subslice_mask;
>
> eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> @@ -439,8 +459,8 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
> sseu->has_eu_pg = sseu->eu_per_subslice > 2;
>
> if (IS_GEN9_LP(i915)) {
> -#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
> - info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
> +#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask.hsw[0] & BIT(ss)))
> + info->has_pooled_eu = hweight8(sseu->subslice_mask.hsw[0]) == 3;
>
> sseu->min_eu_in_pool = 0;
> if (info->has_pooled_eu) {
> @@ -494,8 +514,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
> /* skip disabled slice */
> continue;
>
> - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> - subslice_mask);
> + sseu->subslice_mask.hsw[s] = subslice_mask;
>
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> u8 eu_disabled_mask;
> @@ -592,8 +611,7 @@ static void hsw_sseu_info_init(struct intel_gt *gt)
> sseu->eu_per_subslice);
>
> for (s = 0; s < sseu->max_slices; s++) {
> - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> - subslice_mask);
> + sseu->subslice_mask.hsw[s] = subslice_mask;
>
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> sseu_set_eus(sseu, s, ss,
> @@ -682,7 +700,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
> */
> if (GRAPHICS_VER(i915) == 11 &&
> slices == 1 &&
> - subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
> + subslices > min_t(u8, 4, hweight8(sseu->subslice_mask.hsw[0]) / 2)) {
> GEM_BUG_ON(subslices & 1);
>
> subslice_pg = false;
> @@ -748,14 +766,25 @@ void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
> {
> int s;
>
> - drm_printf(p, "slice total: %u, mask=%04x\n",
> - hweight8(sseu->slice_mask), sseu->slice_mask);
> - drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
> - for (s = 0; s < sseu->max_slices; s++) {
> - drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
> - s, intel_sseu_subslices_per_slice(sseu, s),
> - intel_sseu_get_subslices(sseu, s));
> + if (sseu->has_xehp_dss) {
> + drm_printf(p, "subslice total: %u\n",
> + intel_sseu_subslice_total(sseu));
> + drm_printf(p, "subslice mask=%*pb\n", I915_MAX_SS_FUSE_BITS,
> + sseu->subslice_mask.xehp);
Do you perhaps want to use the DSS terminology here? Any point to dump
compute and geometry separately?
> + } else {
> + drm_printf(p, "slice total: %u, mask=%04x\n",
> + hweight8(sseu->slice_mask), sseu->slice_mask);
> + drm_printf(p, "subslice total: %u\n",
> + intel_sseu_subslice_total(sseu));
> +
> + for (s = 0; s < sseu->max_slices; s++) {
> + u8 ss_mask = sseu->subslice_mask.hsw[s];
> +
> + drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
> + s, hweight8(ss_mask), ss_mask);
> + }
> }
> +
> drm_printf(p, "EU total: %u\n", sseu->eu_total);
> drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
> drm_printf(p, "has slice power gating: %s\n",
> @@ -772,9 +801,10 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
> int s, ss;
>
> for (s = 0; s < sseu->max_slices; s++) {
> + u8 ss_mask = sseu->subslice_mask.hsw[s];
> +
> drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
> - s, intel_sseu_subslices_per_slice(sseu, s),
> - intel_sseu_get_subslices(sseu, s));
> + s, hweight8(ss_mask), ss_mask);
>
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> u16 enabled_eus = sseu_get_eus(sseu, s, ss);
> @@ -788,16 +818,14 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
> static void sseu_print_xehp_topology(const struct sseu_dev_info *sseu,
> struct drm_printer *p)
> {
> - u32 g_dss_mask = sseu_get_geometry_subslices(sseu);
> - u32 c_dss_mask = intel_sseu_get_compute_subslices(sseu);
> int dss;
>
> for (dss = 0; dss < sseu->max_subslices; dss++) {
> u16 enabled_eus = sseu_get_eus(sseu, 0, dss);
>
> drm_printf(p, "DSS_%02d: G:%3s C:%3s, %2u EUs (0x%04hx)\n", dss,
> - str_yes_no(g_dss_mask & BIT(dss)),
> - str_yes_no(c_dss_mask & BIT(dss)),
> + str_yes_no(test_bit(dss, sseu->geometry_subslice_mask.xehp)),
> + str_yes_no(test_bit(dss, sseu->compute_subslice_mask.xehp)),
> hweight16(enabled_eus), enabled_eus);
> }
> }
> @@ -815,20 +843,40 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
> }
> }
>
> -u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice)
> +void intel_sseu_print_ss_info(const char* type,
> + const struct sseu_dev_info *sseu,
> + struct seq_file *m)
> +{
> + int s;
> +
> + if (sseu->has_xehp_dss)
> + seq_printf(m, " %s Subslices: %u\n", type,
> + bitmap_weight(sseu->subslice_mask.xehp,
> + I915_MAX_SS_FUSE_BITS));
Same question on whether to use DSS and log them separately.
> + else
> + for (s = 0; s < fls(sseu->slice_mask); s++)
> + seq_printf(m, " %s Slice%i subslices: %u\n", type,
> + s, hweight8(sseu->subslice_mask.hsw[s]));
> +}
> +
> +u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask,
> + int dss_per_slice)
> {
> + intel_sseu_ss_mask_t per_slice_mask = {};
> u16 slice_mask = 0;
> int i;
>
> - WARN_ON(sizeof(dss_mask) * 8 / dss_per_slice > 8 * sizeof(slice_mask));
> + WARN_ON(DIV_ROUND_UP(I915_MAX_SS_FUSE_BITS, dss_per_slice) >
> + 8 * sizeof(slice_mask));
>
> - for (i = 0; dss_mask; i++) {
> - if (dss_mask & GENMASK(dss_per_slice - 1, 0))
> + bitmap_fill(per_slice_mask.xehp, dss_per_slice);
> + for (i = 0; !bitmap_empty(dss_mask.xehp, I915_MAX_SS_FUSE_BITS); i++) {
> + if (bitmap_intersects(dss_mask.xehp, per_slice_mask.xehp, dss_per_slice))
> slice_mask |= BIT(i);
>
> - dss_mask >>= dss_per_slice;
> + bitmap_shift_right(dss_mask.xehp, dss_mask.xehp, dss_per_slice,
> + I915_MAX_SS_FUSE_BITS);
> }
>
> return slice_mask;
> }
> -
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
> index 43a8f8f98687..7fbb9276a1c2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> @@ -25,12 +25,16 @@ struct drm_printer;
> /*
> * Maximum number of subslices that can exist within a HSW-style slice. This
> * is only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the
> - * GEN_MAX_DSS value below).
> + * I915_MAX_SS_FUSE_BITS value below).
> */
> #define GEN_MAX_SS_PER_HSW_SLICE 6
>
> -/* Maximum number of DSS on newer platforms (Xe_HP and beyond). */
> -#define GEN_MAX_DSS 32
> +/*
> + * Maximum number of 32-bit registers used by hardware to express the
> + * enabled/disabled subslices.
> + */
> +#define I915_MAX_SS_FUSE_REGS 1
> +#define I915_MAX_SS_FUSE_BITS (I915_MAX_SS_FUSE_REGS * 32)
>
> /* Maximum number of EUs that can exist within a subslice or DSS. */
> #define GEN_MAX_EUS_PER_SS 16
> @@ -38,7 +42,7 @@ struct drm_printer;
> #define SSEU_MAX(a, b) ((a) > (b) ? (a) : (b))
>
> /* The maximum number of bits needed to express each subslice/DSS independently */
> -#define GEN_SS_MASK_SIZE SSEU_MAX(GEN_MAX_DSS, \
> +#define GEN_SS_MASK_SIZE SSEU_MAX(I915_MAX_SS_FUSE_BITS, \
> GEN_MAX_HSW_SLICES * GEN_MAX_SS_PER_HSW_SLICE)
>
> #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
> @@ -49,17 +53,24 @@ struct drm_printer;
> #define GEN_DSS_PER_CSLICE 8
> #define GEN_DSS_PER_MSLICE 8
>
> -#define GEN_MAX_GSLICES (GEN_MAX_DSS / GEN_DSS_PER_GSLICE)
> -#define GEN_MAX_CSLICES (GEN_MAX_DSS / GEN_DSS_PER_CSLICE)
> +#define GEN_MAX_GSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_GSLICE)
> +#define GEN_MAX_CSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_CSLICE)
> +
> +typedef union {
> + u8 hsw[GEN_MAX_HSW_SLICES];
> +
> + /* Bitmap compatible with linux/bitmap.h; may exceed size of u64 */
> + unsigned long xehp[BITS_TO_LONGS(I915_MAX_SS_FUSE_BITS)];
> +} intel_sseu_ss_mask_t;
>
> struct sseu_dev_info {
> u8 slice_mask;
> - u8 subslice_mask[GEN_SS_MASK_SIZE];
> - u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
> - u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
> + intel_sseu_ss_mask_t subslice_mask;
> + intel_sseu_ss_mask_t geometry_subslice_mask;
> + intel_sseu_ss_mask_t compute_subslice_mask;
> union {
> u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
> - u16 xehp[GEN_MAX_DSS];
> + u16 xehp[I915_MAX_SS_FUSE_BITS];
> } eu_mask;
>
> u16 eu_total;
> @@ -100,7 +111,7 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
> {
> struct intel_sseu value = {
> .slice_mask = sseu->slice_mask,
> - .subslice_mask = sseu->subslice_mask[0],
> + .subslice_mask = sseu->subslice_mask.hsw[0],
> .min_eus_per_subslice = sseu->max_eus_per_subslice,
> .max_eus_per_subslice = sseu->max_eus_per_subslice,
> };
> @@ -112,18 +123,23 @@ static inline bool
> intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
> int subslice)
> {
> - u8 mask;
> - int ss_idx = subslice / BITS_PER_BYTE;
> -
> - if (slice >= sseu->max_slices ||
> - subslice >= sseu->max_subslices)
> - return false;
> -
> - GEM_BUG_ON(ss_idx >= sseu->ss_stride);
Range checks are not interesting any more?
> -
> - mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx];
> + if (sseu->has_xehp_dss)
> + return test_bit(subslice, sseu->subslice_mask.xehp);
> + else
> + return sseu->subslice_mask.hsw[slice] & BIT(subslice);
> +}
>
> - return mask & BIT(subslice % BITS_PER_BYTE);
> +/*
> + * Used to obtain the index of the first DSS. Can start searching from the
> + * beginning of a specific dss group (e.g., gslice, cslice, etc.) if
> + * groupsize and groupnum are non-zero.
> + */
> +static inline unsigned int
> +intel_sseu_find_first_xehp_dss(const struct sseu_dev_info *sseu, int groupsize,
> + int groupnum)
> +{
> + return find_next_bit(sseu->subslice_mask.xehp, I915_MAX_SS_FUSE_BITS,
> + groupnum * groupsize);
> }
>
> void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
> @@ -133,14 +149,10 @@ unsigned int
> intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
>
> unsigned int
> -intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
> -
> -u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
> +intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice);
>
> -u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
> -
> -void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
> - u8 *subslice_mask, u32 ss_mask);
> +intel_sseu_ss_mask_t
> +intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
>
> void intel_sseu_info_init(struct intel_gt *gt);
>
> @@ -152,9 +164,15 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
> const struct sseu_dev_info *sseu,
> struct drm_printer *p);
>
> -u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
> +u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask, int dss_per_slice);
>
> int intel_sseu_copy_eumask_to_user(void __user *to,
> const struct sseu_dev_info *sseu);
> +int intel_sseu_copy_ssmask_to_user(void __user *to,
> + const struct sseu_dev_info *sseu);
> +
> +void intel_sseu_print_ss_info(const char* type,
> + const struct sseu_dev_info *sseu,
> + struct seq_file *m);
>
> #endif /* __INTEL_SSEU_H__ */
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> index 2d5d011e01db..c2ee5e1826b5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> @@ -4,6 +4,7 @@
> * Copyright © 2020 Intel Corporation
> */
>
> +#include <linux/bitmap.h>
> #include <linux/string_helpers.h>
>
> #include "i915_drv.h"
> @@ -11,14 +12,6 @@
> #include "intel_gt_regs.h"
> #include "intel_sseu_debugfs.h"
>
> -static void sseu_copy_subslices(const struct sseu_dev_info *sseu,
> - int slice, u8 *to_mask)
> -{
> - int offset = slice * sseu->ss_stride;
> -
> - memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
> -}
> -
> static void cherryview_sseu_device_status(struct intel_gt *gt,
> struct sseu_dev_info *sseu)
> {
> @@ -41,7 +34,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt,
> continue;
>
> sseu->slice_mask = BIT(0);
> - sseu->subslice_mask[0] |= BIT(ss);
> + sseu->subslice_mask.hsw[0] |= BIT(ss);
> eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
> ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
> ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
> @@ -92,7 +85,7 @@ static void gen11_sseu_device_status(struct intel_gt *gt,
> continue;
>
> sseu->slice_mask |= BIT(s);
> - sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
> + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
>
> for (ss = 0; ss < info->sseu.max_subslices; ss++) {
> unsigned int eu_cnt;
> @@ -147,21 +140,17 @@ static void gen9_sseu_device_status(struct intel_gt *gt,
> sseu->slice_mask |= BIT(s);
>
> if (IS_GEN9_BC(gt->i915))
> - sseu_copy_subslices(&info->sseu, s,
> - sseu->subslice_mask);
> + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
>
> for (ss = 0; ss < info->sseu.max_subslices; ss++) {
> unsigned int eu_cnt;
> - u8 ss_idx = s * info->sseu.ss_stride +
> - ss / BITS_PER_BYTE;
>
> if (IS_GEN9_LP(gt->i915)) {
> if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> /* skip disabled subslice */
> continue;
>
> - sseu->subslice_mask[ss_idx] |=
> - BIT(ss % BITS_PER_BYTE);
> + sseu->subslice_mask.hsw[s] |= BIT(ss);
> }
>
> eu_cnt = eu_reg[2 * s + ss / 2] & eu_mask[ss % 2];
> @@ -188,8 +177,7 @@ static void bdw_sseu_device_status(struct intel_gt *gt,
> if (sseu->slice_mask) {
> sseu->eu_per_subslice = info->sseu.eu_per_subslice;
> for (s = 0; s < fls(sseu->slice_mask); s++)
> - sseu_copy_subslices(&info->sseu, s,
> - sseu->subslice_mask);
> + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
> sseu->eu_total = sseu->eu_per_subslice *
> intel_sseu_subslice_total(sseu);
>
> @@ -208,7 +196,6 @@ static void i915_print_sseu_info(struct seq_file *m,
> const struct sseu_dev_info *sseu)
> {
> const char *type = is_available_info ? "Available" : "Enabled";
> - int s;
>
> seq_printf(m, " %s Slice Mask: %04x\n", type,
> sseu->slice_mask);
> @@ -216,10 +203,7 @@ static void i915_print_sseu_info(struct seq_file *m,
> hweight8(sseu->slice_mask));
> seq_printf(m, " %s Subslice Total: %u\n", type,
> intel_sseu_subslice_total(sseu));
> - for (s = 0; s < fls(sseu->slice_mask); s++) {
> - seq_printf(m, " %s Slice%i subslices: %u\n", type,
> - s, intel_sseu_subslices_per_slice(sseu, s));
> - }
> + intel_sseu_print_ss_info(type, sseu, m);
> seq_printf(m, " %s EU Total: %u\n", type,
> sseu->eu_total);
> seq_printf(m, " %s EU Per Subslice: %u\n", type,
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 756807c4b405..fc6274708f8e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -948,8 +948,8 @@ gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> * on s/ss combo, the read should be done with read_subslice_reg.
> */
> slice = ffs(sseu->slice_mask) - 1;
> - GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
> - subslice = ffs(intel_sseu_get_subslices(sseu, slice));
> + GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw));
> + subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice));
> GEM_BUG_ON(!subslice);
> subslice--;
>
> @@ -1087,11 +1087,10 @@ static void
> icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> const struct sseu_dev_info *sseu = >->info.sseu;
> - unsigned int slice, subslice;
> + unsigned int subslice;
>
> GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
> GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
> - slice = 0;
>
> /*
> * Although a platform may have subslices, we need to always steer
> @@ -1102,7 +1101,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> * one of the higher subslices, we run the risk of reading back 0's or
> * random garbage.
> */
> - subslice = __ffs(intel_sseu_get_subslices(sseu, slice));
> + subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0));
>
> /*
> * If the subslice we picked above also steers us to a valid L3 bank,
> @@ -1112,7 +1111,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> if (gt->info.l3bank_mask & BIT(subslice))
> gt->steering_table[L3BANK] = NULL;
>
> - __add_mcr_wa(gt, wal, slice, subslice);
> + __add_mcr_wa(gt, wal, 0, subslice);
> }
>
> static void
> @@ -1120,7 +1119,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> const struct sseu_dev_info *sseu = >->info.sseu;
> unsigned long slice, subslice = 0, slice_mask = 0;
> - u64 dss_mask = 0;
> u32 lncf_mask = 0;
> int i;
>
> @@ -1151,8 +1149,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> */
>
> /* Find the potential gslice candidates */
> - dss_mask = intel_sseu_get_subslices(sseu, 0);
> - slice_mask = intel_slicemask_from_dssmask(dss_mask, GEN_DSS_PER_GSLICE);
> + slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask,
> + GEN_DSS_PER_GSLICE);
>
> /*
> * Find the potential LNCF candidates. Either LNCF within a valid
> @@ -1177,9 +1175,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> }
>
> slice = __ffs(slice_mask);
> - subslice = __ffs(dss_mask >> (slice * GEN_DSS_PER_GSLICE));
> + subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice);
> WARN_ON(subslice > GEN_DSS_PER_GSLICE);
> - WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0);
>
> __add_mcr_wa(gt, wal, slice, subslice);
>
> @@ -2030,9 +2027,8 @@ engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>
> static bool needs_wa_1308578152(struct intel_engine_cs *engine)
> {
> - u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0);
> -
> - return (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0;
> + return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >
> + GEN_DSS_PER_GSLICE;
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
> index ac9767c56619..6fd15b39570c 100644
> --- a/drivers/gpu/drm/i915/i915_getparam.c
> +++ b/drivers/gpu/drm/i915/i915_getparam.c
> @@ -162,8 +162,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
> return -EINVAL;
>
> /* Only copy bits from the first slice */
> - memcpy(&value, sseu->subslice_mask,
> - min(sseu->ss_stride, (u8)sizeof(value)));
> + value = intel_sseu_get_hsw_subslices(sseu, 0);
> if (!value)
> return -ENODEV;
> break;
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 16f43bf32a05..9afa6d1eaf95 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -31,7 +31,7 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
>
> static int fill_topology_info(const struct sseu_dev_info *sseu,
> struct drm_i915_query_item *query_item,
> - const u8 *subslice_mask)
> + intel_sseu_ss_mask_t subslice_mask)
> {
> struct drm_i915_query_topology_info topo;
> u32 slice_length, subslice_length, eu_length, total_length;
> @@ -71,9 +71,9 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
> &sseu->slice_mask, slice_length))
> return -EFAULT;
>
> - if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
> - sizeof(topo) + slice_length),
> - subslice_mask, subslice_length))
> + if (intel_sseu_copy_ssmask_to_user(u64_to_user_ptr(query_item->data_ptr +
> + sizeof(topo) + slice_length),
> + sseu))
> return -EFAULT;
>
> if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
Apart from the comments in this round I think I am happy with how it all
looks. I am happy to provide acks once the main changes I suggested are
implemented and couple questions answered. But I would prefer if you
would be able to find someone else for a more detailed review.
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 2/6] drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
2022-05-20 9:15 ` [Intel-gfx] " Tvrtko Ursulin
@ 2022-05-20 20:42 ` Matt Roper
-1 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2022-05-20 20:42 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Jordan Justen, intel-gfx, Lionel Landwerlin, dri-devel
On Fri, May 20, 2022 at 10:15:32AM +0100, Tvrtko Ursulin wrote:
>
> On 17/05/2022 04:20, Matt Roper wrote:
> > Slice/subslice/EU information should be obtained via the topology
> > queries provided by the I915_QUERY interface; let's turn off support for
> > the old GETPARAM lookups on Xe_HP and beyond where we can't return
> > meaningful values.
> >
> > The slice mask lookup is meaningless since Xe_HP doesn't support
> > traditional slices (and we make no attempt to return the various new
> > units like gslices, cslices, mslices, etc.) here.
> >
> > The subslice mask lookup is even more problematic; given the distinct
> > masks for geometry vs compute purposes, the combined mask returned here
> > is likely not what userspace would want to act upon anyway. The value
> > is also limited to 32-bits by the nature of the GETPARAM ioctl which is
> > sufficient for the initial Xe_HP platforms, but is unable to convey the
> > larger masks that will be needed on other upcoming platforms. Finally,
> > the value returned here becomes even less meaningful when used on
> > multi-tile platforms where each tile will have its own masks.
> >
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_getparam.c | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
> > index c12a0adefda5..ac9767c56619 100644
> > --- a/drivers/gpu/drm/i915/i915_getparam.c
> > +++ b/drivers/gpu/drm/i915/i915_getparam.c
> > @@ -148,11 +148,19 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
> > value = intel_engines_has_context_isolation(i915);
> > break;
> > case I915_PARAM_SLICE_MASK:
> > + /* Not supported from Xe_HP onward; use topology queries */
> > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> > + return -EINVAL;
> > +
> > value = sseu->slice_mask;
> > if (!value)
> > return -ENODEV;
> > break;
> > case I915_PARAM_SUBSLICE_MASK:
> > + /* Not supported from Xe_HP onward; use topology queries */
> > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> > + return -EINVAL;
> > +
> > /* Only copy bits from the first slice */
> > memcpy(&value, sseu->subslice_mask,
> > min(sseu->ss_stride, (u8)sizeof(value)));
>
> Just in case lets run this by Jordan and Lionel since it affects DG2. Anyone
> else on the userspace side who might be affected?
When I grep'd Mesa, I found two uses of I915_PARAM_SLICE_MASK and
I915_PARAM_SUBSLICE_MASK:
* oa_metrics_kernel_support: The topology query is used on gen10+ so
the getparam code is only called on gen9 and below
* getparam_topology: Invoked via intel_get_device_info_from_fd(). The
topology query is attempted first. Only if that fails _and_ we're on
a pre-gen10 platform does it fall back to GETPARAM.
I also checked https://github.com/intel/compute-runtime and only see
these being issued in one place:
* HwInfoConfig::configureHwInfoDrm: Only used if drm->queryTopology()
returns a failure first.
I think those are the only relevant userspace for SSEU topology, so as
far as I can tell nobody is still relying on the legacy getparams by the
time we get to Xe_HP hardware.
Matt
>
> Regards,
>
> Tvrtko
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/6] drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
@ 2022-05-20 20:42 ` Matt Roper
0 siblings, 0 replies; 43+ messages in thread
From: Matt Roper @ 2022-05-20 20:42 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx, dri-devel
On Fri, May 20, 2022 at 10:15:32AM +0100, Tvrtko Ursulin wrote:
>
> On 17/05/2022 04:20, Matt Roper wrote:
> > Slice/subslice/EU information should be obtained via the topology
> > queries provided by the I915_QUERY interface; let's turn off support for
> > the old GETPARAM lookups on Xe_HP and beyond where we can't return
> > meaningful values.
> >
> > The slice mask lookup is meaningless since Xe_HP doesn't support
> > traditional slices (and we make no attempt to return the various new
> > units like gslices, cslices, mslices, etc.) here.
> >
> > The subslice mask lookup is even more problematic; given the distinct
> > masks for geometry vs compute purposes, the combined mask returned here
> > is likely not what userspace would want to act upon anyway. The value
> > is also limited to 32-bits by the nature of the GETPARAM ioctl which is
> > sufficient for the initial Xe_HP platforms, but is unable to convey the
> > larger masks that will be needed on other upcoming platforms. Finally,
> > the value returned here becomes even less meaningful when used on
> > multi-tile platforms where each tile will have its own masks.
> >
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_getparam.c | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
> > index c12a0adefda5..ac9767c56619 100644
> > --- a/drivers/gpu/drm/i915/i915_getparam.c
> > +++ b/drivers/gpu/drm/i915/i915_getparam.c
> > @@ -148,11 +148,19 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
> > value = intel_engines_has_context_isolation(i915);
> > break;
> > case I915_PARAM_SLICE_MASK:
> > + /* Not supported from Xe_HP onward; use topology queries */
> > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> > + return -EINVAL;
> > +
> > value = sseu->slice_mask;
> > if (!value)
> > return -ENODEV;
> > break;
> > case I915_PARAM_SUBSLICE_MASK:
> > + /* Not supported from Xe_HP onward; use topology queries */
> > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> > + return -EINVAL;
> > +
> > /* Only copy bits from the first slice */
> > memcpy(&value, sseu->subslice_mask,
> > min(sseu->ss_stride, (u8)sizeof(value)));
>
> Just in case lets run this by Jordan and Lionel since it affects DG2. Anyone
> else on the userspace side who might be affected?
When I grep'd Mesa, I found two uses of I915_PARAM_SLICE_MASK and
I915_PARAM_SUBSLICE_MASK:
* oa_metrics_kernel_support: The topology query is used on gen10+ so
the getparam code is only called on gen9 and below
* getparam_topology: Invoked via intel_get_device_info_from_fd(). The
topology query is attempted first. Only if that fails _and_ we're on
a pre-gen10 platform does it fall back to GETPARAM.
I also checked https://github.com/intel/compute-runtime and only see
these being issued in one place:
* HwInfoConfig::configureHwInfoDrm: Only used if drm->queryTopology()
returns a failure first.
I think those are the only relevant userspace for SSEU topology, so as
far as I can tell nobody is still relying on the legacy getparams by the
time we get to Xe_HP hardware.
Matt
>
> Regards,
>
> Tvrtko
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 2/6] drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
2022-05-20 20:42 ` [Intel-gfx] " Matt Roper
@ 2022-05-24 8:51 ` Tvrtko Ursulin
-1 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2022-05-24 8:51 UTC (permalink / raw)
To: Matt Roper; +Cc: Jordan Justen, intel-gfx, Lionel Landwerlin, dri-devel
On 20/05/2022 21:42, Matt Roper wrote:
> On Fri, May 20, 2022 at 10:15:32AM +0100, Tvrtko Ursulin wrote:
>>
>> On 17/05/2022 04:20, Matt Roper wrote:
>>> Slice/subslice/EU information should be obtained via the topology
>>> queries provided by the I915_QUERY interface; let's turn off support for
>>> the old GETPARAM lookups on Xe_HP and beyond where we can't return
>>> meaningful values.
>>>
>>> The slice mask lookup is meaningless since Xe_HP doesn't support
>>> traditional slices (and we make no attempt to return the various new
>>> units like gslices, cslices, mslices, etc.) here.
>>>
>>> The subslice mask lookup is even more problematic; given the distinct
>>> masks for geometry vs compute purposes, the combined mask returned here
>>> is likely not what userspace would want to act upon anyway. The value
>>> is also limited to 32-bits by the nature of the GETPARAM ioctl which is
>>> sufficient for the initial Xe_HP platforms, but is unable to convey the
>>> larger masks that will be needed on other upcoming platforms. Finally,
>>> the value returned here becomes even less meaningful when used on
>>> multi-tile platforms where each tile will have its own masks.
>>>
>>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/i915_getparam.c | 8 ++++++++
>>> 1 file changed, 8 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
>>> index c12a0adefda5..ac9767c56619 100644
>>> --- a/drivers/gpu/drm/i915/i915_getparam.c
>>> +++ b/drivers/gpu/drm/i915/i915_getparam.c
>>> @@ -148,11 +148,19 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
>>> value = intel_engines_has_context_isolation(i915);
>>> break;
>>> case I915_PARAM_SLICE_MASK:
>>> + /* Not supported from Xe_HP onward; use topology queries */
>>> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
>>> + return -EINVAL;
>>> +
>>> value = sseu->slice_mask;
>>> if (!value)
>>> return -ENODEV;
>>> break;
>>> case I915_PARAM_SUBSLICE_MASK:
>>> + /* Not supported from Xe_HP onward; use topology queries */
>>> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
>>> + return -EINVAL;
>>> +
>>> /* Only copy bits from the first slice */
>>> memcpy(&value, sseu->subslice_mask,
>>> min(sseu->ss_stride, (u8)sizeof(value)));
>>
>> Just in case lets run this by Jordan and Lionel since it affects DG2. Anyone
>> else on the userspace side who might be affected?
>
> When I grep'd Mesa, I found two uses of I915_PARAM_SLICE_MASK and
> I915_PARAM_SUBSLICE_MASK:
>
> * oa_metrics_kernel_support: The topology query is used on gen10+ so
> the getparam code is only called on gen9 and below
>
> * getparam_topology: Invoked via intel_get_device_info_from_fd(). The
> topology query is attempted first. Only if that fails _and_ we're on
> a pre-gen10 platform does it fall back to GETPARAM.
>
> I also checked https://github.com/intel/compute-runtime and only see
> these being issued in one place:
>
> * HwInfoConfig::configureHwInfoDrm: Only used if drm->queryTopology()
> returns a failure first.
>
>
> I think those are the only relevant userspace for SSEU topology, so as
> far as I can tell nobody is still relying on the legacy getparams by the
> time we get to Xe_HP hardware.
Sounds good to me - I also had a look at the media and compute drivers
and couldn't find any use. However I still think it is best if UMD teams
would ack this patch.
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/6] drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
@ 2022-05-24 8:51 ` Tvrtko Ursulin
0 siblings, 0 replies; 43+ messages in thread
From: Tvrtko Ursulin @ 2022-05-24 8:51 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, dri-devel
On 20/05/2022 21:42, Matt Roper wrote:
> On Fri, May 20, 2022 at 10:15:32AM +0100, Tvrtko Ursulin wrote:
>>
>> On 17/05/2022 04:20, Matt Roper wrote:
>>> Slice/subslice/EU information should be obtained via the topology
>>> queries provided by the I915_QUERY interface; let's turn off support for
>>> the old GETPARAM lookups on Xe_HP and beyond where we can't return
>>> meaningful values.
>>>
>>> The slice mask lookup is meaningless since Xe_HP doesn't support
>>> traditional slices (and we make no attempt to return the various new
>>> units like gslices, cslices, mslices, etc.) here.
>>>
>>> The subslice mask lookup is even more problematic; given the distinct
>>> masks for geometry vs compute purposes, the combined mask returned here
>>> is likely not what userspace would want to act upon anyway. The value
>>> is also limited to 32-bits by the nature of the GETPARAM ioctl which is
>>> sufficient for the initial Xe_HP platforms, but is unable to convey the
>>> larger masks that will be needed on other upcoming platforms. Finally,
>>> the value returned here becomes even less meaningful when used on
>>> multi-tile platforms where each tile will have its own masks.
>>>
>>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/i915_getparam.c | 8 ++++++++
>>> 1 file changed, 8 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
>>> index c12a0adefda5..ac9767c56619 100644
>>> --- a/drivers/gpu/drm/i915/i915_getparam.c
>>> +++ b/drivers/gpu/drm/i915/i915_getparam.c
>>> @@ -148,11 +148,19 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
>>> value = intel_engines_has_context_isolation(i915);
>>> break;
>>> case I915_PARAM_SLICE_MASK:
>>> + /* Not supported from Xe_HP onward; use topology queries */
>>> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
>>> + return -EINVAL;
>>> +
>>> value = sseu->slice_mask;
>>> if (!value)
>>> return -ENODEV;
>>> break;
>>> case I915_PARAM_SUBSLICE_MASK:
>>> + /* Not supported from Xe_HP onward; use topology queries */
>>> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
>>> + return -EINVAL;
>>> +
>>> /* Only copy bits from the first slice */
>>> memcpy(&value, sseu->subslice_mask,
>>> min(sseu->ss_stride, (u8)sizeof(value)));
>>
>> Just in case lets run this by Jordan and Lionel since it affects DG2. Anyone
>> else on the userspace side who might be affected?
>
> When I grep'd Mesa, I found two uses of I915_PARAM_SLICE_MASK and
> I915_PARAM_SUBSLICE_MASK:
>
> * oa_metrics_kernel_support: The topology query is used on gen10+ so
> the getparam code is only called on gen9 and below
>
> * getparam_topology: Invoked via intel_get_device_info_from_fd(). The
> topology query is attempted first. Only if that fails _and_ we're on
> a pre-gen10 platform does it fall back to GETPARAM.
>
> I also checked https://github.com/intel/compute-runtime and only see
> these being issued in one place:
>
> * HwInfoConfig::configureHwInfoDrm: Only used if drm->queryTopology()
> returns a failure first.
>
>
> I think those are the only relevant userspace for SSEU topology, so as
> far as I can tell nobody is still relying on the legacy getparams by the
> time we get to Xe_HP hardware.
Sounds good to me - I also had a look at the media and compute drivers
and couldn't find any use. However I still think it is best if UMD teams
would ack this patch.
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/6] drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
2022-05-17 3:20 ` [Intel-gfx] " Matt Roper
(?)
(?)
@ 2022-06-01 5:59 ` Lionel Landwerlin
-1 siblings, 0 replies; 43+ messages in thread
From: Lionel Landwerlin @ 2022-06-01 5:59 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel
On 17/05/2022 06:20, Matt Roper wrote:
> Slice/subslice/EU information should be obtained via the topology
> queries provided by the I915_QUERY interface; let's turn off support for
> the old GETPARAM lookups on Xe_HP and beyond where we can't return
> meaningful values.
>
> The slice mask lookup is meaningless since Xe_HP doesn't support
> traditional slices (and we make no attempt to return the various new
> units like gslices, cslices, mslices, etc.) here.
>
> The subslice mask lookup is even more problematic; given the distinct
> masks for geometry vs compute purposes, the combined mask returned here
> is likely not what userspace would want to act upon anyway. The value
> is also limited to 32-bits by the nature of the GETPARAM ioctl which is
> sufficient for the initial Xe_HP platforms, but is unable to convey the
> larger masks that will be needed on other upcoming platforms. Finally,
> the value returned here becomes even less meaningful when used on
> multi-tile platforms where each tile will have its own masks.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Sounds fair. We've been relying on the topology query in Mesa since it's
available and it's a requirement for Gfx10+.
FYI, we're also not using I915_PARAM_EU_TOTAL on Gfx10+ for the same reason.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
> drivers/gpu/drm/i915/i915_getparam.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
> index c12a0adefda5..ac9767c56619 100644
> --- a/drivers/gpu/drm/i915/i915_getparam.c
> +++ b/drivers/gpu/drm/i915/i915_getparam.c
> @@ -148,11 +148,19 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
> value = intel_engines_has_context_isolation(i915);
> break;
> case I915_PARAM_SLICE_MASK:
> + /* Not supported from Xe_HP onward; use topology queries */
> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> + return -EINVAL;
> +
> value = sseu->slice_mask;
> if (!value)
> return -ENODEV;
> break;
> case I915_PARAM_SUBSLICE_MASK:
> + /* Not supported from Xe_HP onward; use topology queries */
> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> + return -EINVAL;
> +
> /* Only copy bits from the first slice */
> memcpy(&value, sseu->subslice_mask,
> min(sseu->ss_stride, (u8)sizeof(value)));
^ permalink raw reply [flat|nested] 43+ messages in thread
end of thread, other threads:[~2022-06-01 6:00 UTC | newest]
Thread overview: 43+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-17 3:19 [PATCH v2 0/6] i915: SSEU handling updates Matt Roper
2022-05-17 3:19 ` [Intel-gfx] " Matt Roper
2022-05-17 3:20 ` [PATCH v2 1/6] drm/i915/xehp: Use separate sseu init function Matt Roper
2022-05-17 3:20 ` [Intel-gfx] " Matt Roper
2022-05-17 3:20 ` [PATCH v2 2/6] drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK Matt Roper
2022-05-17 3:20 ` [Intel-gfx] " Matt Roper
2022-05-20 9:15 ` Tvrtko Ursulin
2022-05-20 9:15 ` [Intel-gfx] " Tvrtko Ursulin
2022-05-20 20:42 ` Matt Roper
2022-05-20 20:42 ` [Intel-gfx] " Matt Roper
2022-05-24 8:51 ` Tvrtko Ursulin
2022-05-24 8:51 ` [Intel-gfx] " Tvrtko Ursulin
2022-06-01 5:59 ` Lionel Landwerlin
2022-05-17 3:20 ` [PATCH v2 3/6] drm/i915/sseu: Simplify gen11+ SSEU handling Matt Roper
2022-05-17 3:20 ` [Intel-gfx] " Matt Roper
2022-05-20 9:21 ` Tvrtko Ursulin
2022-05-20 9:21 ` [Intel-gfx] " Tvrtko Ursulin
2022-05-17 3:20 ` [PATCH v2 4/6] drm/i915/sseu: Don't try to store EU mask internally in UAPI format Matt Roper
2022-05-17 3:20 ` [Intel-gfx] " Matt Roper
2022-05-20 9:32 ` Tvrtko Ursulin
2022-05-20 9:32 ` [Intel-gfx] " Tvrtko Ursulin
2022-05-17 3:20 ` [PATCH v2 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi Matt Roper
2022-05-17 3:20 ` [Intel-gfx] " Matt Roper
2022-05-17 15:15 ` [PATCH v3 " Matt Roper
2022-05-17 15:15 ` [Intel-gfx] " Matt Roper
2022-05-20 10:07 ` Tvrtko Ursulin
2022-05-20 10:07 ` [Intel-gfx] " Tvrtko Ursulin
2022-05-17 3:20 ` [PATCH v2 6/6] drm/i915/pvc: Add SSEU changes Matt Roper
2022-05-17 3:20 ` [Intel-gfx] " Matt Roper
2022-05-17 3:40 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: SSEU handling updates (rev3) Patchwork
2022-05-17 3:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-17 4:05 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-05-17 6:25 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-05-17 18:44 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: SSEU handling updates (rev4) Patchwork
2022-05-17 18:44 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-17 19:08 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-05-17 19:19 ` Matt Roper
2022-05-17 20:44 ` Vudum, Lakshminarayana
2022-05-17 20:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-05-18 0:34 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-05-18 3:24 ` Matt Roper
2022-05-18 16:51 ` Vudum, Lakshminarayana
2022-05-18 15:55 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
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