* [PATCH v4 0/6] i915: SSEU handling updates
@ 2022-05-20 23:04 ` Matt Roper
0 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-05-20 23:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Tvrtko Ursulin, dri-devel
This series reworks i915's internal handling of slice/subslice/EU (SSEU)
data to represent platforms like Xe_HP in a more natural manner and to
prepare for future platforms where the masks will need to grow in size.
One key idea of this series is that although we have a fixed ABI to
convey SSEU data to userspace (i.e., multiple u8[] arrays with data
stored at different strides), we don't need to use this cumbersome
format for the driver's own internal storage. As long as we can convert
into the uapi form properly when responding to the I915_QUERY ioctl,
it's preferable to use an internal storage format that's easier for the
driver to work with.
Another key point here is that we're reaching the point where subslice
(DSS) masks will soon not fit within simple u32/u64 integer values.
Xe_HP SDV and DG2 platforms today have subslice (DSS) masks that are 32
bits, which maxes out the current storage of a u32. With PVC the masks
are represented by a pair of 32-bit registers, requiring a bump up to at
least 64-bits of storage internally. We could switch to u64 for that in
the short term, but since we already know that upcoming architectures
intend to provide DSS fuse bits via three or more registers it's best to
switch to a representation that's more future-proof but still easy to
work with in the driver code. To accomodate this, we start storing our
subslice mask for Xe_HP and beyond in a new typedef that can be
processed by the linux/bitmap.h operations.
Finally, since no userspace for Xe_HP or beyond is using the legacy
I915_GETPARAM ioctl lookups for I915_PARAM_SLICE_MASK and
I915_PARAM_SUBSLICE_MASK (since they've migrated to the more flexible
I915_QUERY ioctl that can return more than a simple u32 value), we take
the opportunity to officially drop support for those GETPARAM lookups on
modern platforms. Maintaining support for these GETPARAM lookups don't
make sense for a number of reasons:
* Traditional slices no longer exist, and newer ideas like gslices,
cslices, mslices, etc. aren't something userspace needs to query
since it can be inferred from other information.
* The GETPARAM ioctl doesn't have a way to distinguish between geometry
subslice masks and compute subslice masks, which are distinct on
Xe_HP and beyond.
* The I915_GETPARAM ioctl is limited to returning a 32-bit value, so
when subslice masks begin to exceed 32-bits (on PVC), it simply can't
return the entire mask.
* The GETPARAM ioctl doesn't have a way to give sensible information
for multi-tile devices.
v2:
- Switch to union of hsw/xehp formats to keep the representation in a
natural format for different types of hardware.
- Avoid accessing internals of intel_sseu_ss_mask_t directly outside of
intel_sseu.[ch].
- Include PVC SSEU which needs the larger SS mask storage enabled by
this series.
v3:
- Correct a BIT(s) typo that should have been BIT(ss), causing
incorrect handling on gen9 platforms.
v4:
- Eliminate sseu->{ss,eu}_stride fields and just calculate the proper
value in the UAPI code that needs them.
- Handle unwanted ~u8 sign extension at the callsite instead of inside
sseu_set_eus.
- Use BITMAP_BITS() macro rather than passing I915_MAX_SS_FUSE_BITS
around directly to bitmap operations.
- Improved debugfs / dmesg reporting for Xe_HP dumps
- Various assertion check improvements.
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Matt Roper (6):
drm/i915/xehp: Use separate sseu init function
drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
drm/i915/sseu: Simplify gen11+ SSEU handling
drm/i915/sseu: Don't try to store EU mask internally in UAPI format
drm/i915/sseu: Disassociate internal subslice mask representation from
uapi
drm/i915/pvc: Add SSEU changes
drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 12 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_sseu.c | 450 ++++++++++++-------
drivers/gpu/drm/i915/gt/intel_sseu.h | 94 ++--
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_getparam.c | 11 +-
drivers/gpu/drm/i915/i915_pci.c | 3 +-
drivers/gpu/drm/i915/i915_query.c | 26 +-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
13 files changed, 398 insertions(+), 265 deletions(-)
--
2.35.3
^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH v4 0/6] i915: SSEU handling updates
@ 2022-05-20 23:04 ` Matt Roper
0 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-05-20 23:04 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
This series reworks i915's internal handling of slice/subslice/EU (SSEU)
data to represent platforms like Xe_HP in a more natural manner and to
prepare for future platforms where the masks will need to grow in size.
One key idea of this series is that although we have a fixed ABI to
convey SSEU data to userspace (i.e., multiple u8[] arrays with data
stored at different strides), we don't need to use this cumbersome
format for the driver's own internal storage. As long as we can convert
into the uapi form properly when responding to the I915_QUERY ioctl,
it's preferable to use an internal storage format that's easier for the
driver to work with.
Another key point here is that we're reaching the point where subslice
(DSS) masks will soon not fit within simple u32/u64 integer values.
Xe_HP SDV and DG2 platforms today have subslice (DSS) masks that are 32
bits, which maxes out the current storage of a u32. With PVC the masks
are represented by a pair of 32-bit registers, requiring a bump up to at
least 64-bits of storage internally. We could switch to u64 for that in
the short term, but since we already know that upcoming architectures
intend to provide DSS fuse bits via three or more registers it's best to
switch to a representation that's more future-proof but still easy to
work with in the driver code. To accomodate this, we start storing our
subslice mask for Xe_HP and beyond in a new typedef that can be
processed by the linux/bitmap.h operations.
Finally, since no userspace for Xe_HP or beyond is using the legacy
I915_GETPARAM ioctl lookups for I915_PARAM_SLICE_MASK and
I915_PARAM_SUBSLICE_MASK (since they've migrated to the more flexible
I915_QUERY ioctl that can return more than a simple u32 value), we take
the opportunity to officially drop support for those GETPARAM lookups on
modern platforms. Maintaining support for these GETPARAM lookups don't
make sense for a number of reasons:
* Traditional slices no longer exist, and newer ideas like gslices,
cslices, mslices, etc. aren't something userspace needs to query
since it can be inferred from other information.
* The GETPARAM ioctl doesn't have a way to distinguish between geometry
subslice masks and compute subslice masks, which are distinct on
Xe_HP and beyond.
* The I915_GETPARAM ioctl is limited to returning a 32-bit value, so
when subslice masks begin to exceed 32-bits (on PVC), it simply can't
return the entire mask.
* The GETPARAM ioctl doesn't have a way to give sensible information
for multi-tile devices.
v2:
- Switch to union of hsw/xehp formats to keep the representation in a
natural format for different types of hardware.
- Avoid accessing internals of intel_sseu_ss_mask_t directly outside of
intel_sseu.[ch].
- Include PVC SSEU which needs the larger SS mask storage enabled by
this series.
v3:
- Correct a BIT(s) typo that should have been BIT(ss), causing
incorrect handling on gen9 platforms.
v4:
- Eliminate sseu->{ss,eu}_stride fields and just calculate the proper
value in the UAPI code that needs them.
- Handle unwanted ~u8 sign extension at the callsite instead of inside
sseu_set_eus.
- Use BITMAP_BITS() macro rather than passing I915_MAX_SS_FUSE_BITS
around directly to bitmap operations.
- Improved debugfs / dmesg reporting for Xe_HP dumps
- Various assertion check improvements.
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Matt Roper (6):
drm/i915/xehp: Use separate sseu init function
drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
drm/i915/sseu: Simplify gen11+ SSEU handling
drm/i915/sseu: Don't try to store EU mask internally in UAPI format
drm/i915/sseu: Disassociate internal subslice mask representation from
uapi
drm/i915/pvc: Add SSEU changes
drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 12 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_sseu.c | 450 ++++++++++++-------
drivers/gpu/drm/i915/gt/intel_sseu.h | 94 ++--
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_getparam.c | 11 +-
drivers/gpu/drm/i915/i915_pci.c | 3 +-
drivers/gpu/drm/i915/i915_query.c | 26 +-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
13 files changed, 398 insertions(+), 265 deletions(-)
--
2.35.3
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v4 1/6] drm/i915/xehp: Use separate sseu init function
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
@ 2022-05-20 23:04 ` Matt Roper
-1 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-05-20 23:04 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Xe_HP has enough fundamental differences from previous platforms that it
makes sense to use a separate SSEU init function to keep things
straightforward and easy to understand. We'll also add a has_xehp_dss
flag to the SSEU structure that will be used by other upcoming changes.
v2:
- Add has_xehp_dss flag
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 86 ++++++++++++++++------------
drivers/gpu/drm/i915/gt/intel_sseu.h | 5 ++
2 files changed, 54 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index fdd25691beda..b5fd479a7b85 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -169,13 +169,43 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, u8 s_en,
sseu->eu_total = compute_eu_total(sseu);
}
-static void gen12_sseu_info_init(struct intel_gt *gt)
+static void xehp_sseu_info_init(struct intel_gt *gt)
{
struct sseu_dev_info *sseu = >->info.sseu;
struct intel_uncore *uncore = gt->uncore;
u32 g_dss_en, c_dss_en = 0;
u16 eu_en = 0;
u8 eu_en_fuse;
+ int eu;
+
+ /*
+ * The concept of slice has been removed in Xe_HP. To be compatible
+ * with prior generations, assume a single slice across the entire
+ * device. Then calculate out the DSS for each workload type within
+ * that software slice.
+ */
+ intel_sseu_set_info(sseu, 1, 32, 16);
+ sseu->has_xehp_dss = 1;
+
+ g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
+ c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
+
+ eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
+
+ for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
+ if (eu_en_fuse & BIT(eu))
+ eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
+
+ gen11_compute_sseu_info(sseu, 0x1, g_dss_en, c_dss_en, eu_en);
+}
+
+static void gen12_sseu_info_init(struct intel_gt *gt)
+{
+ struct sseu_dev_info *sseu = >->info.sseu;
+ struct intel_uncore *uncore = gt->uncore;
+ u32 g_dss_en;
+ u16 eu_en = 0;
+ u8 eu_en_fuse;
u8 s_en;
int eu;
@@ -183,43 +213,23 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
* Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS.
* Instead of splitting these, provide userspace with an array
* of DSS to more closely represent the hardware resource.
- *
- * In addition, the concept of slice has been removed in Xe_HP.
- * To be compatible with prior generations, assume a single slice
- * across the entire device. Then calculate out the DSS for each
- * workload type within that software slice.
*/
- if (IS_DG2(gt->i915) || IS_XEHPSDV(gt->i915))
- intel_sseu_set_info(sseu, 1, 32, 16);
- else
- intel_sseu_set_info(sseu, 1, 6, 16);
+ intel_sseu_set_info(sseu, 1, 6, 16);
- /*
- * As mentioned above, Xe_HP does not have the concept of a slice.
- * Enable one for software backwards compatibility.
- */
- if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
- s_en = 0x1;
- else
- s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
- GEN11_GT_S_ENA_MASK;
+ s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
+ GEN11_GT_S_ENA_MASK;
g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
- if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
- c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
/* one bit per pair of EUs */
- if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
- eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
- else
- eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
- GEN11_EU_DIS_MASK);
+ eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
+ GEN11_EU_DIS_MASK);
for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, s_en, g_dss_en, c_dss_en, eu_en);
+ gen11_compute_sseu_info(sseu, s_en, g_dss_en, 0, eu_en);
/* TGL only supports slice-level power gating */
sseu->has_slice_pg = 1;
@@ -574,18 +584,20 @@ void intel_sseu_info_init(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
- if (IS_HASWELL(i915))
- hsw_sseu_info_init(gt);
- else if (IS_CHERRYVIEW(i915))
- cherryview_sseu_info_init(gt);
- else if (IS_BROADWELL(i915))
- bdw_sseu_info_init(gt);
- else if (GRAPHICS_VER(i915) == 9)
- gen9_sseu_info_init(gt);
- else if (GRAPHICS_VER(i915) == 11)
- gen11_sseu_info_init(gt);
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ xehp_sseu_info_init(gt);
else if (GRAPHICS_VER(i915) >= 12)
gen12_sseu_info_init(gt);
+ else if (GRAPHICS_VER(i915) >= 11)
+ gen11_sseu_info_init(gt);
+ else if (GRAPHICS_VER(i915) >= 9)
+ gen9_sseu_info_init(gt);
+ else if (IS_BROADWELL(i915))
+ bdw_sseu_info_init(gt);
+ else if (IS_CHERRYVIEW(i915))
+ cherryview_sseu_info_init(gt);
+ else if (IS_HASWELL(i915))
+ hsw_sseu_info_init(gt);
}
u32 intel_sseu_make_rpcs(struct intel_gt *gt,
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 5c078df4729c..4a041f9dc490 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -66,6 +66,11 @@ struct sseu_dev_info {
u8 has_slice_pg:1;
u8 has_subslice_pg:1;
u8 has_eu_pg:1;
+ /*
+ * For Xe_HP and beyond, the hardware no longer has traditional slices
+ * so we just report the entire DSS pool under a fake "slice 0."
+ */
+ u8 has_xehp_dss:1;
/* Topology fields */
u8 max_slices;
--
2.35.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH v4 1/6] drm/i915/xehp: Use separate sseu init function
@ 2022-05-20 23:04 ` Matt Roper
0 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-05-20 23:04 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Xe_HP has enough fundamental differences from previous platforms that it
makes sense to use a separate SSEU init function to keep things
straightforward and easy to understand. We'll also add a has_xehp_dss
flag to the SSEU structure that will be used by other upcoming changes.
v2:
- Add has_xehp_dss flag
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 86 ++++++++++++++++------------
drivers/gpu/drm/i915/gt/intel_sseu.h | 5 ++
2 files changed, 54 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index fdd25691beda..b5fd479a7b85 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -169,13 +169,43 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, u8 s_en,
sseu->eu_total = compute_eu_total(sseu);
}
-static void gen12_sseu_info_init(struct intel_gt *gt)
+static void xehp_sseu_info_init(struct intel_gt *gt)
{
struct sseu_dev_info *sseu = >->info.sseu;
struct intel_uncore *uncore = gt->uncore;
u32 g_dss_en, c_dss_en = 0;
u16 eu_en = 0;
u8 eu_en_fuse;
+ int eu;
+
+ /*
+ * The concept of slice has been removed in Xe_HP. To be compatible
+ * with prior generations, assume a single slice across the entire
+ * device. Then calculate out the DSS for each workload type within
+ * that software slice.
+ */
+ intel_sseu_set_info(sseu, 1, 32, 16);
+ sseu->has_xehp_dss = 1;
+
+ g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
+ c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
+
+ eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
+
+ for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
+ if (eu_en_fuse & BIT(eu))
+ eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
+
+ gen11_compute_sseu_info(sseu, 0x1, g_dss_en, c_dss_en, eu_en);
+}
+
+static void gen12_sseu_info_init(struct intel_gt *gt)
+{
+ struct sseu_dev_info *sseu = >->info.sseu;
+ struct intel_uncore *uncore = gt->uncore;
+ u32 g_dss_en;
+ u16 eu_en = 0;
+ u8 eu_en_fuse;
u8 s_en;
int eu;
@@ -183,43 +213,23 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
* Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS.
* Instead of splitting these, provide userspace with an array
* of DSS to more closely represent the hardware resource.
- *
- * In addition, the concept of slice has been removed in Xe_HP.
- * To be compatible with prior generations, assume a single slice
- * across the entire device. Then calculate out the DSS for each
- * workload type within that software slice.
*/
- if (IS_DG2(gt->i915) || IS_XEHPSDV(gt->i915))
- intel_sseu_set_info(sseu, 1, 32, 16);
- else
- intel_sseu_set_info(sseu, 1, 6, 16);
+ intel_sseu_set_info(sseu, 1, 6, 16);
- /*
- * As mentioned above, Xe_HP does not have the concept of a slice.
- * Enable one for software backwards compatibility.
- */
- if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
- s_en = 0x1;
- else
- s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
- GEN11_GT_S_ENA_MASK;
+ s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
+ GEN11_GT_S_ENA_MASK;
g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
- if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
- c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
/* one bit per pair of EUs */
- if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
- eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
- else
- eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
- GEN11_EU_DIS_MASK);
+ eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
+ GEN11_EU_DIS_MASK);
for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, s_en, g_dss_en, c_dss_en, eu_en);
+ gen11_compute_sseu_info(sseu, s_en, g_dss_en, 0, eu_en);
/* TGL only supports slice-level power gating */
sseu->has_slice_pg = 1;
@@ -574,18 +584,20 @@ void intel_sseu_info_init(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
- if (IS_HASWELL(i915))
- hsw_sseu_info_init(gt);
- else if (IS_CHERRYVIEW(i915))
- cherryview_sseu_info_init(gt);
- else if (IS_BROADWELL(i915))
- bdw_sseu_info_init(gt);
- else if (GRAPHICS_VER(i915) == 9)
- gen9_sseu_info_init(gt);
- else if (GRAPHICS_VER(i915) == 11)
- gen11_sseu_info_init(gt);
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ xehp_sseu_info_init(gt);
else if (GRAPHICS_VER(i915) >= 12)
gen12_sseu_info_init(gt);
+ else if (GRAPHICS_VER(i915) >= 11)
+ gen11_sseu_info_init(gt);
+ else if (GRAPHICS_VER(i915) >= 9)
+ gen9_sseu_info_init(gt);
+ else if (IS_BROADWELL(i915))
+ bdw_sseu_info_init(gt);
+ else if (IS_CHERRYVIEW(i915))
+ cherryview_sseu_info_init(gt);
+ else if (IS_HASWELL(i915))
+ hsw_sseu_info_init(gt);
}
u32 intel_sseu_make_rpcs(struct intel_gt *gt,
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 5c078df4729c..4a041f9dc490 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -66,6 +66,11 @@ struct sseu_dev_info {
u8 has_slice_pg:1;
u8 has_subslice_pg:1;
u8 has_eu_pg:1;
+ /*
+ * For Xe_HP and beyond, the hardware no longer has traditional slices
+ * so we just report the entire DSS pool under a fake "slice 0."
+ */
+ u8 has_xehp_dss:1;
/* Topology fields */
u8 max_slices;
--
2.35.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 2/6] drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
@ 2022-05-20 23:04 ` Matt Roper
-1 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-05-20 23:04 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Slice/subslice/EU information should be obtained via the topology
queries provided by the I915_QUERY interface; let's turn off support for
the old GETPARAM lookups on Xe_HP and beyond where we can't return
meaningful values.
The slice mask lookup is meaningless since Xe_HP doesn't support
traditional slices (and we make no attempt to return the various new
units like gslices, cslices, mslices, etc.) here.
The subslice mask lookup is even more problematic; given the distinct
masks for geometry vs compute purposes, the combined mask returned here
is likely not what userspace would want to act upon anyway. The value
is also limited to 32-bits by the nature of the GETPARAM ioctl which is
sufficient for the initial Xe_HP platforms, but is unable to convey the
larger masks that will be needed on other upcoming platforms. Finally,
the value returned here becomes even less meaningful when used on
multi-tile platforms where each tile will have its own masks.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_getparam.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index c12a0adefda5..ac9767c56619 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -148,11 +148,19 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = intel_engines_has_context_isolation(i915);
break;
case I915_PARAM_SLICE_MASK:
+ /* Not supported from Xe_HP onward; use topology queries */
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ return -EINVAL;
+
value = sseu->slice_mask;
if (!value)
return -ENODEV;
break;
case I915_PARAM_SUBSLICE_MASK:
+ /* Not supported from Xe_HP onward; use topology queries */
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ return -EINVAL;
+
/* Only copy bits from the first slice */
memcpy(&value, sseu->subslice_mask,
min(sseu->ss_stride, (u8)sizeof(value)));
--
2.35.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH v4 2/6] drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
@ 2022-05-20 23:04 ` Matt Roper
0 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-05-20 23:04 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Slice/subslice/EU information should be obtained via the topology
queries provided by the I915_QUERY interface; let's turn off support for
the old GETPARAM lookups on Xe_HP and beyond where we can't return
meaningful values.
The slice mask lookup is meaningless since Xe_HP doesn't support
traditional slices (and we make no attempt to return the various new
units like gslices, cslices, mslices, etc.) here.
The subslice mask lookup is even more problematic; given the distinct
masks for geometry vs compute purposes, the combined mask returned here
is likely not what userspace would want to act upon anyway. The value
is also limited to 32-bits by the nature of the GETPARAM ioctl which is
sufficient for the initial Xe_HP platforms, but is unable to convey the
larger masks that will be needed on other upcoming platforms. Finally,
the value returned here becomes even less meaningful when used on
multi-tile platforms where each tile will have its own masks.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_getparam.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index c12a0adefda5..ac9767c56619 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -148,11 +148,19 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = intel_engines_has_context_isolation(i915);
break;
case I915_PARAM_SLICE_MASK:
+ /* Not supported from Xe_HP onward; use topology queries */
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ return -EINVAL;
+
value = sseu->slice_mask;
if (!value)
return -ENODEV;
break;
case I915_PARAM_SUBSLICE_MASK:
+ /* Not supported from Xe_HP onward; use topology queries */
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ return -EINVAL;
+
/* Only copy bits from the first slice */
memcpy(&value, sseu->subslice_mask,
min(sseu->ss_stride, (u8)sizeof(value)));
--
2.35.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 3/6] drm/i915/sseu: Simplify gen11+ SSEU handling
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
@ 2022-05-20 23:04 ` Matt Roper
-1 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-05-20 23:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Tvrtko Ursulin, dri-devel
Although gen11 and gen12 architectures supported the concept of multiple
slices, in practice all the platforms that were actually designed only
had a single slice (i.e., note the parameters to 'intel_sseu_set_info'
that we pass for each platform). We can simplify the code slightly by
dropping the multi-slice logic from gen11+ platforms.
v2:
- Promote drm_dbg to drm_WARN_ON if the slice fuse register reports
unexpected fusing. (Tvrtko)
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 76 +++++++++++++---------------
1 file changed, 36 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index b5fd479a7b85..7e5222ad2f98 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -119,52 +119,37 @@ static u16 compute_eu_total(const struct sseu_dev_info *sseu)
return total;
}
-static u32 get_ss_stride_mask(struct sseu_dev_info *sseu, u8 s, u32 ss_en)
-{
- u32 ss_mask;
-
- ss_mask = ss_en >> (s * sseu->max_subslices);
- ss_mask &= GENMASK(sseu->max_subslices - 1, 0);
-
- return ss_mask;
-}
-
-static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, u8 s_en,
+static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
u32 g_ss_en, u32 c_ss_en, u16 eu_en)
{
- int s, ss;
+ u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
+ int ss;
/* g_ss_en/c_ss_en represent entire subslice mask across all slices */
GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
sizeof(g_ss_en) * BITS_PER_BYTE);
- for (s = 0; s < sseu->max_slices; s++) {
- if ((s_en & BIT(s)) == 0)
- continue;
+ sseu->slice_mask |= BIT(0);
- sseu->slice_mask |= BIT(s);
-
- /*
- * XeHP introduces the concept of compute vs geometry DSS. To
- * reduce variation between GENs around subslice usage, store a
- * mask for both the geometry and compute enabled masks since
- * userspace will need to be able to query these masks
- * independently. Also compute a total enabled subslice count
- * for the purposes of selecting subslices to use in a
- * particular GEM context.
- */
- intel_sseu_set_subslices(sseu, s, sseu->compute_subslice_mask,
- get_ss_stride_mask(sseu, s, c_ss_en));
- intel_sseu_set_subslices(sseu, s, sseu->geometry_subslice_mask,
- get_ss_stride_mask(sseu, s, g_ss_en));
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- get_ss_stride_mask(sseu, s,
- g_ss_en | c_ss_en));
+ /*
+ * XeHP introduces the concept of compute vs geometry DSS. To reduce
+ * variation between GENs around subslice usage, store a mask for both
+ * the geometry and compute enabled masks since userspace will need to
+ * be able to query these masks independently. Also compute a total
+ * enabled subslice count for the purposes of selecting subslices to
+ * use in a particular GEM context.
+ */
+ intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
+ c_ss_en & valid_ss_mask);
+ intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
+ g_ss_en & valid_ss_mask);
+ intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
+ (g_ss_en | c_ss_en) & valid_ss_mask);
+
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (intel_sseu_has_subslice(sseu, 0, ss))
+ sseu_set_eus(sseu, 0, ss, eu_en);
- for (ss = 0; ss < sseu->max_subslices; ss++)
- if (intel_sseu_has_subslice(sseu, s, ss))
- sseu_set_eus(sseu, s, ss, eu_en);
- }
sseu->eu_per_subslice = hweight16(eu_en);
sseu->eu_total = compute_eu_total(sseu);
}
@@ -196,7 +181,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, 0x1, g_dss_en, c_dss_en, eu_en);
+ gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
}
static void gen12_sseu_info_init(struct intel_gt *gt)
@@ -216,8 +201,13 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
*/
intel_sseu_set_info(sseu, 1, 6, 16);
+ /*
+ * Although gen12 architecture supported multiple slices, TGL, RKL,
+ * DG1, and ADL only had a single slice.
+ */
s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
GEN11_GT_S_ENA_MASK;
+ drm_WARN_ON(>->i915->drm, s_en != 0x1);
g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
@@ -229,7 +219,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, s_en, g_dss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
/* TGL only supports slice-level power gating */
sseu->has_slice_pg = 1;
@@ -248,14 +238,20 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
else
intel_sseu_set_info(sseu, 1, 8, 8);
+ /*
+ * Although gen11 architecture supported multiple slices, ICL and
+ * EHL/JSL only had a single slice in practice.
+ */
s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
GEN11_GT_S_ENA_MASK;
+ drm_WARN_ON(>->i915->drm, s_en != 0x1);
+
ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE);
eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
GEN11_EU_DIS_MASK);
- gen11_compute_sseu_info(sseu, s_en, ss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
/* ICL has no power gating restrictions. */
sseu->has_slice_pg = 1;
--
2.35.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH v4 3/6] drm/i915/sseu: Simplify gen11+ SSEU handling
@ 2022-05-20 23:04 ` Matt Roper
0 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-05-20 23:04 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Although gen11 and gen12 architectures supported the concept of multiple
slices, in practice all the platforms that were actually designed only
had a single slice (i.e., note the parameters to 'intel_sseu_set_info'
that we pass for each platform). We can simplify the code slightly by
dropping the multi-slice logic from gen11+ platforms.
v2:
- Promote drm_dbg to drm_WARN_ON if the slice fuse register reports
unexpected fusing. (Tvrtko)
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 76 +++++++++++++---------------
1 file changed, 36 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index b5fd479a7b85..7e5222ad2f98 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -119,52 +119,37 @@ static u16 compute_eu_total(const struct sseu_dev_info *sseu)
return total;
}
-static u32 get_ss_stride_mask(struct sseu_dev_info *sseu, u8 s, u32 ss_en)
-{
- u32 ss_mask;
-
- ss_mask = ss_en >> (s * sseu->max_subslices);
- ss_mask &= GENMASK(sseu->max_subslices - 1, 0);
-
- return ss_mask;
-}
-
-static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, u8 s_en,
+static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
u32 g_ss_en, u32 c_ss_en, u16 eu_en)
{
- int s, ss;
+ u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
+ int ss;
/* g_ss_en/c_ss_en represent entire subslice mask across all slices */
GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
sizeof(g_ss_en) * BITS_PER_BYTE);
- for (s = 0; s < sseu->max_slices; s++) {
- if ((s_en & BIT(s)) == 0)
- continue;
+ sseu->slice_mask |= BIT(0);
- sseu->slice_mask |= BIT(s);
-
- /*
- * XeHP introduces the concept of compute vs geometry DSS. To
- * reduce variation between GENs around subslice usage, store a
- * mask for both the geometry and compute enabled masks since
- * userspace will need to be able to query these masks
- * independently. Also compute a total enabled subslice count
- * for the purposes of selecting subslices to use in a
- * particular GEM context.
- */
- intel_sseu_set_subslices(sseu, s, sseu->compute_subslice_mask,
- get_ss_stride_mask(sseu, s, c_ss_en));
- intel_sseu_set_subslices(sseu, s, sseu->geometry_subslice_mask,
- get_ss_stride_mask(sseu, s, g_ss_en));
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- get_ss_stride_mask(sseu, s,
- g_ss_en | c_ss_en));
+ /*
+ * XeHP introduces the concept of compute vs geometry DSS. To reduce
+ * variation between GENs around subslice usage, store a mask for both
+ * the geometry and compute enabled masks since userspace will need to
+ * be able to query these masks independently. Also compute a total
+ * enabled subslice count for the purposes of selecting subslices to
+ * use in a particular GEM context.
+ */
+ intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
+ c_ss_en & valid_ss_mask);
+ intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
+ g_ss_en & valid_ss_mask);
+ intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
+ (g_ss_en | c_ss_en) & valid_ss_mask);
+
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (intel_sseu_has_subslice(sseu, 0, ss))
+ sseu_set_eus(sseu, 0, ss, eu_en);
- for (ss = 0; ss < sseu->max_subslices; ss++)
- if (intel_sseu_has_subslice(sseu, s, ss))
- sseu_set_eus(sseu, s, ss, eu_en);
- }
sseu->eu_per_subslice = hweight16(eu_en);
sseu->eu_total = compute_eu_total(sseu);
}
@@ -196,7 +181,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, 0x1, g_dss_en, c_dss_en, eu_en);
+ gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
}
static void gen12_sseu_info_init(struct intel_gt *gt)
@@ -216,8 +201,13 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
*/
intel_sseu_set_info(sseu, 1, 6, 16);
+ /*
+ * Although gen12 architecture supported multiple slices, TGL, RKL,
+ * DG1, and ADL only had a single slice.
+ */
s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
GEN11_GT_S_ENA_MASK;
+ drm_WARN_ON(>->i915->drm, s_en != 0x1);
g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
@@ -229,7 +219,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, s_en, g_dss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
/* TGL only supports slice-level power gating */
sseu->has_slice_pg = 1;
@@ -248,14 +238,20 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
else
intel_sseu_set_info(sseu, 1, 8, 8);
+ /*
+ * Although gen11 architecture supported multiple slices, ICL and
+ * EHL/JSL only had a single slice in practice.
+ */
s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) &
GEN11_GT_S_ENA_MASK;
+ drm_WARN_ON(>->i915->drm, s_en != 0x1);
+
ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE);
eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
GEN11_EU_DIS_MASK);
- gen11_compute_sseu_info(sseu, s_en, ss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
/* ICL has no power gating restrictions. */
sseu->has_slice_pg = 1;
--
2.35.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 4/6] drm/i915/sseu: Don't try to store EU mask internally in UAPI format
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
@ 2022-05-20 23:04 ` Matt Roper
-1 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-05-20 23:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Tvrtko Ursulin, dri-devel
Storing the EU mask internally in the same format the I915_QUERY
topology queries use makes the final copy_to_user() a bit simpler, but
makes the rest of the driver's SSEU more complicated and harder to
follow. Let's switch to an internal representation that's more natural:
Xe_HP platforms will be a simple array of u16 masks, whereas pre-Xe_HP
platforms will be a two-dimensional array, indexed by [slice][subslice].
We'll convert to the uapi format only when the query uapi is called.
v2:
- Drop has_common_ss_eumask. We waste some space repeating identical
EU masks for every single DSS, but the code is simpler without it.
(Tvrtko)
v3:
- Mask down EUs passed to sseu_set_eus at the callsite rather than
inside the function. (Tvrtko)
- Eliminate sseu->eu_stride and calculate it when needed. (Tvrtko)
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 88 ++++++++++++++++++----------
drivers/gpu/drm/i915/gt/intel_sseu.h | 10 +++-
drivers/gpu/drm/i915/i915_query.c | 13 ++--
3 files changed, 73 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 7e5222ad2f98..285cfd758bdc 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -19,8 +19,6 @@ void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
GEM_BUG_ON(sseu->ss_stride > GEN_MAX_SUBSLICE_STRIDE);
- sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
- GEM_BUG_ON(sseu->eu_stride > GEN_MAX_EU_STRIDE);
}
unsigned int
@@ -78,47 +76,77 @@ intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
return hweight32(intel_sseu_get_subslices(sseu, slice));
}
-static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
- int subslice)
-{
- int slice_stride = sseu->max_subslices * sseu->eu_stride;
-
- return slice * slice_stride + subslice * sseu->eu_stride;
-}
-
static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
int subslice)
{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
- u16 eu_mask = 0;
-
- for (i = 0; i < sseu->eu_stride; i++)
- eu_mask |=
- ((u16)sseu->eu_mask[offset + i]) << (i * BITS_PER_BYTE);
-
- return eu_mask;
+ if (sseu->has_xehp_dss) {
+ WARN_ON(slice > 0);
+ return sseu->eu_mask.xehp[subslice];
+ } else {
+ return sseu->eu_mask.hsw[slice][subslice];
+ }
}
static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
u16 eu_mask)
{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
-
- for (i = 0; i < sseu->eu_stride; i++)
- sseu->eu_mask[offset + i] =
- (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
+ GEM_WARN_ON(eu_mask && __fls(eu_mask) >= sseu->max_eus_per_subslice);
+ if (sseu->has_xehp_dss) {
+ GEM_WARN_ON(slice > 0);
+ sseu->eu_mask.xehp[subslice] = eu_mask;
+ } else {
+ sseu->eu_mask.hsw[slice][subslice] = eu_mask;
+ }
}
static u16 compute_eu_total(const struct sseu_dev_info *sseu)
{
- u16 i, total = 0;
+ int s, ss, total = 0;
- for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++)
- total += hweight8(sseu->eu_mask[i]);
+ for (s = 0; s < sseu->max_slices; s++)
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (sseu->has_xehp_dss)
+ total += hweight16(sseu->eu_mask.xehp[ss]);
+ else
+ total += hweight16(sseu->eu_mask.hsw[s][ss]);
return total;
}
+/**
+ * intel_sseu_copy_eumask_to_user - Copy EU mask into a userspace buffer
+ * @to: Pointer to userspace buffer to copy to
+ * @sseu: SSEU structure containing EU mask to copy
+ *
+ * Copies the EU mask to a userspace buffer in the format expected by
+ * the query ioctl's topology queries.
+ *
+ * Returns the result of the copy_to_user() operation.
+ */
+int intel_sseu_copy_eumask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu)
+{
+ u8 eu_mask[GEN_SS_MASK_SIZE * GEN_MAX_EU_STRIDE] = {};
+ int eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
+ int len = sseu->max_slices * sseu->max_subslices * eu_stride;
+ int s, ss, i;
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ for (ss = 0; ss < sseu->max_subslices; ss++) {
+ int uapi_offset =
+ s * sseu->max_subslices * eu_stride +
+ ss * eu_stride;
+ u16 mask = sseu_get_eus(sseu, s, ss);
+
+ for (i = 0; i < eu_stride; i++)
+ eu_mask[uapi_offset + i] =
+ (mask >> (BITS_PER_BYTE * i)) & 0xff;
+ }
+ }
+
+ return copy_to_user(to, eu_mask, len);
+}
+
static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
u32 g_ss_en, u32 c_ss_en, u16 eu_en)
{
@@ -278,7 +306,7 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
subslice_mask |= BIT(0);
- sseu_set_eus(sseu, 0, 0, ~disabled_mask);
+ sseu_set_eus(sseu, 0, 0, ~disabled_mask & 0xFF);
}
if (!(fuse & CHV_FGT_DISABLE_SS1)) {
@@ -289,7 +317,7 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
subslice_mask |= BIT(1);
- sseu_set_eus(sseu, 0, 1, ~disabled_mask);
+ sseu_set_eus(sseu, 0, 1, ~disabled_mask & 0xFF);
}
intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask, subslice_mask);
@@ -362,7 +390,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask;
- sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
+ sseu_set_eus(sseu, s, ss, ~eu_disabled_mask & eu_mask);
eu_per_ss = sseu->max_eus_per_subslice -
hweight8(eu_disabled_mask);
@@ -475,7 +503,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
eu_disabled_mask =
eu_disable[s] >> (ss * sseu->max_eus_per_subslice);
- sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
+ sseu_set_eus(sseu, s, ss, ~eu_disabled_mask & 0xFF);
n_disabled = hweight8(eu_disabled_mask);
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 4a041f9dc490..ffa375e68959 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -57,7 +57,11 @@ struct sseu_dev_info {
u8 subslice_mask[GEN_SS_MASK_SIZE];
u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
- u8 eu_mask[GEN_SS_MASK_SIZE * GEN_MAX_EU_STRIDE];
+ union {
+ u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
+ u16 xehp[GEN_MAX_DSS];
+ } eu_mask;
+
u16 eu_total;
u8 eu_per_subslice;
u8 min_eu_in_pool;
@@ -78,7 +82,6 @@ struct sseu_dev_info {
u8 max_eus_per_subslice;
u8 ss_stride;
- u8 eu_stride;
};
/*
@@ -150,4 +153,7 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
+int intel_sseu_copy_eumask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu);
+
#endif /* __INTEL_SSEU_H__ */
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 7584cec53d5d..89c475d525b8 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -35,6 +35,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
{
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
+ int eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
@@ -44,7 +45,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
slice_length = sizeof(sseu->slice_mask);
subslice_length = sseu->max_slices * sseu->ss_stride;
- eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
+ eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
total_length = sizeof(topo) + slice_length + subslice_length +
eu_length;
@@ -61,7 +62,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
topo.subslice_offset = slice_length;
topo.subslice_stride = sseu->ss_stride;
topo.eu_offset = slice_length + subslice_length;
- topo.eu_stride = sseu->eu_stride;
+ topo.eu_stride = eu_stride;
if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
&topo, sizeof(topo)))
@@ -76,10 +77,10 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
subslice_mask, subslice_length))
return -EFAULT;
- if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
- sizeof(topo) +
- slice_length + subslice_length),
- sseu->eu_mask, eu_length))
+ if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
+ sizeof(topo) +
+ slice_length + subslice_length),
+ sseu))
return -EFAULT;
return total_length;
--
2.35.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH v4 4/6] drm/i915/sseu: Don't try to store EU mask internally in UAPI format
@ 2022-05-20 23:04 ` Matt Roper
0 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-05-20 23:04 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Storing the EU mask internally in the same format the I915_QUERY
topology queries use makes the final copy_to_user() a bit simpler, but
makes the rest of the driver's SSEU more complicated and harder to
follow. Let's switch to an internal representation that's more natural:
Xe_HP platforms will be a simple array of u16 masks, whereas pre-Xe_HP
platforms will be a two-dimensional array, indexed by [slice][subslice].
We'll convert to the uapi format only when the query uapi is called.
v2:
- Drop has_common_ss_eumask. We waste some space repeating identical
EU masks for every single DSS, but the code is simpler without it.
(Tvrtko)
v3:
- Mask down EUs passed to sseu_set_eus at the callsite rather than
inside the function. (Tvrtko)
- Eliminate sseu->eu_stride and calculate it when needed. (Tvrtko)
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 88 ++++++++++++++++++----------
drivers/gpu/drm/i915/gt/intel_sseu.h | 10 +++-
drivers/gpu/drm/i915/i915_query.c | 13 ++--
3 files changed, 73 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 7e5222ad2f98..285cfd758bdc 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -19,8 +19,6 @@ void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
GEM_BUG_ON(sseu->ss_stride > GEN_MAX_SUBSLICE_STRIDE);
- sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
- GEM_BUG_ON(sseu->eu_stride > GEN_MAX_EU_STRIDE);
}
unsigned int
@@ -78,47 +76,77 @@ intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
return hweight32(intel_sseu_get_subslices(sseu, slice));
}
-static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
- int subslice)
-{
- int slice_stride = sseu->max_subslices * sseu->eu_stride;
-
- return slice * slice_stride + subslice * sseu->eu_stride;
-}
-
static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
int subslice)
{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
- u16 eu_mask = 0;
-
- for (i = 0; i < sseu->eu_stride; i++)
- eu_mask |=
- ((u16)sseu->eu_mask[offset + i]) << (i * BITS_PER_BYTE);
-
- return eu_mask;
+ if (sseu->has_xehp_dss) {
+ WARN_ON(slice > 0);
+ return sseu->eu_mask.xehp[subslice];
+ } else {
+ return sseu->eu_mask.hsw[slice][subslice];
+ }
}
static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
u16 eu_mask)
{
- int i, offset = sseu_eu_idx(sseu, slice, subslice);
-
- for (i = 0; i < sseu->eu_stride; i++)
- sseu->eu_mask[offset + i] =
- (eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
+ GEM_WARN_ON(eu_mask && __fls(eu_mask) >= sseu->max_eus_per_subslice);
+ if (sseu->has_xehp_dss) {
+ GEM_WARN_ON(slice > 0);
+ sseu->eu_mask.xehp[subslice] = eu_mask;
+ } else {
+ sseu->eu_mask.hsw[slice][subslice] = eu_mask;
+ }
}
static u16 compute_eu_total(const struct sseu_dev_info *sseu)
{
- u16 i, total = 0;
+ int s, ss, total = 0;
- for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++)
- total += hweight8(sseu->eu_mask[i]);
+ for (s = 0; s < sseu->max_slices; s++)
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (sseu->has_xehp_dss)
+ total += hweight16(sseu->eu_mask.xehp[ss]);
+ else
+ total += hweight16(sseu->eu_mask.hsw[s][ss]);
return total;
}
+/**
+ * intel_sseu_copy_eumask_to_user - Copy EU mask into a userspace buffer
+ * @to: Pointer to userspace buffer to copy to
+ * @sseu: SSEU structure containing EU mask to copy
+ *
+ * Copies the EU mask to a userspace buffer in the format expected by
+ * the query ioctl's topology queries.
+ *
+ * Returns the result of the copy_to_user() operation.
+ */
+int intel_sseu_copy_eumask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu)
+{
+ u8 eu_mask[GEN_SS_MASK_SIZE * GEN_MAX_EU_STRIDE] = {};
+ int eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
+ int len = sseu->max_slices * sseu->max_subslices * eu_stride;
+ int s, ss, i;
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ for (ss = 0; ss < sseu->max_subslices; ss++) {
+ int uapi_offset =
+ s * sseu->max_subslices * eu_stride +
+ ss * eu_stride;
+ u16 mask = sseu_get_eus(sseu, s, ss);
+
+ for (i = 0; i < eu_stride; i++)
+ eu_mask[uapi_offset + i] =
+ (mask >> (BITS_PER_BYTE * i)) & 0xff;
+ }
+ }
+
+ return copy_to_user(to, eu_mask, len);
+}
+
static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
u32 g_ss_en, u32 c_ss_en, u16 eu_en)
{
@@ -278,7 +306,7 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
subslice_mask |= BIT(0);
- sseu_set_eus(sseu, 0, 0, ~disabled_mask);
+ sseu_set_eus(sseu, 0, 0, ~disabled_mask & 0xFF);
}
if (!(fuse & CHV_FGT_DISABLE_SS1)) {
@@ -289,7 +317,7 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
subslice_mask |= BIT(1);
- sseu_set_eus(sseu, 0, 1, ~disabled_mask);
+ sseu_set_eus(sseu, 0, 1, ~disabled_mask & 0xFF);
}
intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask, subslice_mask);
@@ -362,7 +390,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask;
- sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
+ sseu_set_eus(sseu, s, ss, ~eu_disabled_mask & eu_mask);
eu_per_ss = sseu->max_eus_per_subslice -
hweight8(eu_disabled_mask);
@@ -475,7 +503,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
eu_disabled_mask =
eu_disable[s] >> (ss * sseu->max_eus_per_subslice);
- sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
+ sseu_set_eus(sseu, s, ss, ~eu_disabled_mask & 0xFF);
n_disabled = hweight8(eu_disabled_mask);
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 4a041f9dc490..ffa375e68959 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -57,7 +57,11 @@ struct sseu_dev_info {
u8 subslice_mask[GEN_SS_MASK_SIZE];
u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
- u8 eu_mask[GEN_SS_MASK_SIZE * GEN_MAX_EU_STRIDE];
+ union {
+ u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
+ u16 xehp[GEN_MAX_DSS];
+ } eu_mask;
+
u16 eu_total;
u8 eu_per_subslice;
u8 min_eu_in_pool;
@@ -78,7 +82,6 @@ struct sseu_dev_info {
u8 max_eus_per_subslice;
u8 ss_stride;
- u8 eu_stride;
};
/*
@@ -150,4 +153,7 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
+int intel_sseu_copy_eumask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu);
+
#endif /* __INTEL_SSEU_H__ */
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 7584cec53d5d..89c475d525b8 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -35,6 +35,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
{
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
+ int eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
@@ -44,7 +45,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
slice_length = sizeof(sseu->slice_mask);
subslice_length = sseu->max_slices * sseu->ss_stride;
- eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
+ eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
total_length = sizeof(topo) + slice_length + subslice_length +
eu_length;
@@ -61,7 +62,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
topo.subslice_offset = slice_length;
topo.subslice_stride = sseu->ss_stride;
topo.eu_offset = slice_length + subslice_length;
- topo.eu_stride = sseu->eu_stride;
+ topo.eu_stride = eu_stride;
if (copy_to_user(u64_to_user_ptr(query_item->data_ptr),
&topo, sizeof(topo)))
@@ -76,10 +77,10 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
subslice_mask, subslice_length))
return -EFAULT;
- if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
- sizeof(topo) +
- slice_length + subslice_length),
- sseu->eu_mask, eu_length))
+ if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
+ sizeof(topo) +
+ slice_length + subslice_length),
+ sseu))
return -EFAULT;
return total_length;
--
2.35.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
@ 2022-05-20 23:04 ` Matt Roper
-1 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-05-20 23:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Tvrtko Ursulin, dri-devel
As with EU masks, it's easier to store subslice/DSS masks internally in
a format that's more natural for the driver to work with, and then only
covert into the u8[] uapi form when the query ioctl is invoked. Since
the hardware design changed significantly with Xe_HP, we'll use a union
to choose between the old "hsw-style" subslice masks or the newer xehp
mask. HSW-style masks will be stored in an array of u8's, indexed by
slice (there's never more than 6 subslices per slice on older
platforms). For Xe_HP and beyond where slices no longer exist, we only
need a single bitmask. However we already know that this mask is
eventually going to grow too large for a simple u64 to hold, so we'll
represent it in a manner that can be operated on by the utilities in
linux/bitmap.h.
v2:
- Fix typo: BIT(s) -> BIT(ss) in gen9_sseu_device_status()
v3:
- Eliminate sseu->ss_stride and just calculate the stride while
specifically handling uapi. (Tvrtko)
- Use BITMAP_BITS() macro to refer to size of masks rather than
passing I915_MAX_SS_FUSE_BITS directly. (Tvrtko)
- Report compute/geometry DSS masks separately when dumping Xe_HP SSEU
info. (Tvrtko)
- Restore dropped range checks to intel_sseu_has_subslice(). (Tvrtko)
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 12 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 261 +++++++++++--------
drivers/gpu/drm/i915/gt/intel_sseu.h | 81 +++---
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +--
drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +-
drivers/gpu/drm/i915/i915_getparam.c | 3 +-
drivers/gpu/drm/i915/i915_query.c | 13 +-
9 files changed, 244 insertions(+), 189 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index ab4c5ab28e4d..a3bb73f5d53b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1875,6 +1875,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
{
const struct sseu_dev_info *device = >->info.sseu;
struct drm_i915_private *i915 = gt->i915;
+ unsigned int dev_subslice_mask = intel_sseu_get_hsw_subslices(device, 0);
/* No zeros in any field. */
if (!user->slice_mask || !user->subslice_mask ||
@@ -1901,7 +1902,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
if (user->slice_mask & ~device->slice_mask)
return -EINVAL;
- if (user->subslice_mask & ~device->subslice_mask[0])
+ if (user->subslice_mask & ~dev_subslice_mask)
return -EINVAL;
if (user->max_eus_per_subslice > device->max_eus_per_subslice)
@@ -1915,7 +1916,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
/* Part specific restrictions. */
if (GRAPHICS_VER(i915) == 11) {
unsigned int hw_s = hweight8(device->slice_mask);
- unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
+ unsigned int hw_ss_per_s = hweight8(dev_subslice_mask);
unsigned int req_s = hweight8(context->slice_mask);
unsigned int req_ss = hweight8(context->subslice_mask);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 1adbf34c3632..f0acf8518a51 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -674,8 +674,8 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
return;
- ccs_mask = intel_slicemask_from_dssmask(intel_sseu_get_compute_subslices(&info->sseu),
- ss_per_ccs);
+ ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
+ ss_per_ccs);
/*
* If all DSS in a quadrant are fused off, the corresponding CCS
* engine is not available for use.
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 034182f85501..2921f510642f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -133,13 +133,6 @@ static const struct intel_mmio_range dg2_lncf_steering_table[] = {
{},
};
-static u16 slicemask(struct intel_gt *gt, int count)
-{
- u64 dss_mask = intel_sseu_get_subslices(>->info.sseu, 0);
-
- return intel_slicemask_from_dssmask(dss_mask, count);
-}
-
int intel_gt_init_mmio(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
@@ -155,9 +148,12 @@ int intel_gt_init_mmio(struct intel_gt *gt)
*/
if (HAS_MSLICES(i915)) {
gt->info.mslice_mask =
- slicemask(gt, GEN_DSS_PER_MSLICE) |
+ intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
+ GEN_DSS_PER_MSLICE);
+ gt->info.mslice_mask |=
(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
GEN12_MEML3_EN_MASK);
+
if (!gt->info.mslice_mask) /* should be impossible! */
drm_warn(&i915->drm, "mslice mask all zero!\n");
}
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 285cfd758bdc..6fbc2ac507b7 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -10,15 +10,14 @@
#include "intel_gt_regs.h"
#include "intel_sseu.h"
+#define BITMAP_BITS(mask) ((int)BITS_PER_TYPE(typeof(mask)))
+
void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
u8 max_subslices, u8 max_eus_per_subslice)
{
sseu->max_slices = max_slices;
sseu->max_subslices = max_subslices;
sseu->max_eus_per_subslice = max_eus_per_subslice;
-
- sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
- GEM_BUG_ON(sseu->ss_stride > GEN_MAX_SUBSLICE_STRIDE);
}
unsigned int
@@ -26,54 +25,24 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
{
unsigned int i, total = 0;
- for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
- total += hweight8(sseu->subslice_mask[i]);
-
- return total;
-}
-
-static u32
-sseu_get_subslices(const struct sseu_dev_info *sseu,
- const u8 *subslice_mask, u8 slice)
-{
- int i, offset = slice * sseu->ss_stride;
- u32 mask = 0;
-
- GEM_BUG_ON(slice >= sseu->max_slices);
-
- for (i = 0; i < sseu->ss_stride; i++)
- mask |= (u32)subslice_mask[offset + i] << i * BITS_PER_BYTE;
-
- return mask;
-}
-
-u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
-{
- return sseu_get_subslices(sseu, sseu->subslice_mask, slice);
-}
+ if (sseu->has_xehp_dss)
+ return bitmap_weight(sseu->subslice_mask.xehp,
+ BITMAP_BITS(sseu->subslice_mask));
-static u32 sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
-{
- return sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
-}
+ for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++)
+ total += hweight8(sseu->subslice_mask.hsw[i]);
-u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu)
-{
- return sseu_get_subslices(sseu, sseu->compute_subslice_mask, 0);
-}
-
-void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
- u8 *subslice_mask, u32 ss_mask)
-{
- int offset = slice * sseu->ss_stride;
-
- memcpy(&subslice_mask[offset], &ss_mask, sseu->ss_stride);
+ return total;
}
unsigned int
-intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
+intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice)
{
- return hweight32(intel_sseu_get_subslices(sseu, slice));
+ WARN_ON(sseu->has_xehp_dss);
+ if (WARN_ON(slice >= sseu->max_slices))
+ return 0;
+
+ return sseu->subslice_mask.hsw[slice];
}
static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
@@ -147,32 +116,66 @@ int intel_sseu_copy_eumask_to_user(void __user *to,
return copy_to_user(to, eu_mask, len);
}
+/**
+ * intel_sseu_copy_ssmask_to_user - Copy subslice mask into a userspace buffer
+ * @to: Pointer to userspace buffer to copy to
+ * @sseu: SSEU structure containing subslice mask to copy
+ *
+ * Copies the subslice mask to a userspace buffer in the format expected by
+ * the query ioctl's topology queries.
+ *
+ * Returns the result of the copy_to_user() operation.
+ */
+int intel_sseu_copy_ssmask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu)
+{
+ u8 ss_mask[GEN_SS_MASK_SIZE] = {};
+ int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
+ int len = sseu->max_slices * ss_stride;
+ int s, ss, i;
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ for (ss = 0; ss < sseu->max_subslices; ss++) {
+ i = s * ss_stride * BITS_PER_BYTE + ss;
+
+ if (!intel_sseu_has_subslice(sseu, s, ss))
+ continue;
+
+ ss_mask[i / BITS_PER_BYTE] |= BIT(i % BITS_PER_BYTE);
+ }
+ }
+
+ return copy_to_user(to, ss_mask, len);
+}
+
static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
- u32 g_ss_en, u32 c_ss_en, u16 eu_en)
+ u32 ss_en, u16 eu_en)
{
u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
int ss;
- /* g_ss_en/c_ss_en represent entire subslice mask across all slices */
- GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
- sizeof(g_ss_en) * BITS_PER_BYTE);
+ sseu->slice_mask |= BIT(0);
+ sseu->subslice_mask.hsw[0] = ss_en & valid_ss_mask;
+
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (intel_sseu_has_subslice(sseu, 0, ss))
+ sseu_set_eus(sseu, 0, ss, eu_en);
+
+ sseu->eu_per_subslice = hweight16(eu_en);
+ sseu->eu_total = compute_eu_total(sseu);
+}
+
+static void xehp_compute_sseu_info(struct sseu_dev_info *sseu,
+ u16 eu_en)
+{
+ int ss;
sseu->slice_mask |= BIT(0);
- /*
- * XeHP introduces the concept of compute vs geometry DSS. To reduce
- * variation between GENs around subslice usage, store a mask for both
- * the geometry and compute enabled masks since userspace will need to
- * be able to query these masks independently. Also compute a total
- * enabled subslice count for the purposes of selecting subslices to
- * use in a particular GEM context.
- */
- intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
- c_ss_en & valid_ss_mask);
- intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
- g_ss_en & valid_ss_mask);
- intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
- (g_ss_en | c_ss_en) & valid_ss_mask);
+ bitmap_or(sseu->subslice_mask.xehp,
+ sseu->compute_subslice_mask.xehp,
+ sseu->geometry_subslice_mask.xehp,
+ BITMAP_BITS(sseu->subslice_mask));
for (ss = 0; ss < sseu->max_subslices; ss++)
if (intel_sseu_has_subslice(sseu, 0, ss))
@@ -182,11 +185,31 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
sseu->eu_total = compute_eu_total(sseu);
}
+static void
+xehp_load_dss_mask(struct intel_uncore *uncore,
+ intel_sseu_ss_mask_t *ssmask,
+ int numregs,
+ ...)
+{
+ va_list argp;
+ u32 fuse_val[I915_MAX_SS_FUSE_REGS] = {};
+ int i;
+
+ if (WARN_ON(numregs > I915_MAX_SS_FUSE_REGS))
+ numregs = I915_MAX_SS_FUSE_REGS;
+
+ va_start(argp, numregs);
+ for (i = 0; i < numregs; i++)
+ fuse_val[i] = intel_uncore_read(uncore, va_arg(argp, i915_reg_t));
+ va_end(argp);
+
+ bitmap_from_arr32(ssmask->xehp, fuse_val, numregs * 32);
+}
+
static void xehp_sseu_info_init(struct intel_gt *gt)
{
struct sseu_dev_info *sseu = >->info.sseu;
struct intel_uncore *uncore = gt->uncore;
- u32 g_dss_en, c_dss_en = 0;
u16 eu_en = 0;
u8 eu_en_fuse;
int eu;
@@ -200,8 +223,10 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
intel_sseu_set_info(sseu, 1, 32, 16);
sseu->has_xehp_dss = 1;
- g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
- c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
+ xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 1,
+ GEN12_GT_GEOMETRY_DSS_ENABLE);
+ xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 1,
+ GEN12_GT_COMPUTE_DSS_ENABLE);
eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
@@ -209,7 +234,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
+ xehp_compute_sseu_info(sseu, eu_en);
}
static void gen12_sseu_info_init(struct intel_gt *gt)
@@ -247,7 +272,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, g_dss_en, eu_en);
/* TGL only supports slice-level power gating */
sseu->has_slice_pg = 1;
@@ -279,7 +304,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
GEN11_EU_DIS_MASK);
- gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, ss_en, eu_en);
/* ICL has no power gating restrictions. */
sseu->has_slice_pg = 1;
@@ -291,7 +316,6 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
{
struct sseu_dev_info *sseu = >->info.sseu;
u32 fuse;
- u8 subslice_mask = 0;
fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT);
@@ -305,7 +329,7 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
- subslice_mask |= BIT(0);
+ sseu->subslice_mask.hsw[0] |= BIT(0);
sseu_set_eus(sseu, 0, 0, ~disabled_mask & 0xFF);
}
@@ -316,12 +340,10 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
(((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
- subslice_mask |= BIT(1);
+ sseu->subslice_mask.hsw[0] |= BIT(1);
sseu_set_eus(sseu, 0, 1, ~disabled_mask & 0xFF);
}
- intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask, subslice_mask);
-
sseu->eu_total = compute_eu_total(sseu);
/*
@@ -376,8 +398,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
/* skip disabled slice */
continue;
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
for (ss = 0; ss < sseu->max_subslices; ss++) {
@@ -434,8 +455,8 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
sseu->has_eu_pg = sseu->eu_per_subslice > 2;
if (IS_GEN9_LP(i915)) {
-#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
- info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
+#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask.hsw[0] & BIT(ss)))
+ info->has_pooled_eu = hweight8(sseu->subslice_mask.hsw[0]) == 3;
sseu->min_eu_in_pool = 0;
if (info->has_pooled_eu) {
@@ -489,8 +510,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
/* skip disabled slice */
continue;
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
for (ss = 0; ss < sseu->max_subslices; ss++) {
u8 eu_disabled_mask;
@@ -587,8 +607,7 @@ static void hsw_sseu_info_init(struct intel_gt *gt)
sseu->eu_per_subslice);
for (s = 0; s < sseu->max_slices; s++) {
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
for (ss = 0; ss < sseu->max_subslices; ss++) {
sseu_set_eus(sseu, s, ss,
@@ -677,7 +696,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
*/
if (GRAPHICS_VER(i915) == 11 &&
slices == 1 &&
- subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
+ subslices > min_t(u8, 4, hweight8(sseu->subslice_mask.hsw[0]) / 2)) {
GEM_BUG_ON(subslices & 1);
subslice_pg = false;
@@ -743,14 +762,29 @@ void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
{
int s;
- drm_printf(p, "slice total: %u, mask=%04x\n",
- hweight8(sseu->slice_mask), sseu->slice_mask);
- drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
- for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
- s, intel_sseu_subslices_per_slice(sseu, s),
- intel_sseu_get_subslices(sseu, s));
+ if (sseu->has_xehp_dss) {
+ drm_printf(p, "subslice total: %u\n",
+ intel_sseu_subslice_total(sseu));
+ drm_printf(p, "geometry dss mask=%*pb\n",
+ BITMAP_BITS(sseu->geometry_subslice_mask),
+ sseu->geometry_subslice_mask.xehp);
+ drm_printf(p, "compute dss mask=%*pb\n",
+ BITMAP_BITS(sseu->compute_subslice_mask),
+ sseu->compute_subslice_mask.xehp);
+ } else {
+ drm_printf(p, "slice total: %u, mask=%04x\n",
+ hweight8(sseu->slice_mask), sseu->slice_mask);
+ drm_printf(p, "subslice total: %u\n",
+ intel_sseu_subslice_total(sseu));
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ u8 ss_mask = sseu->subslice_mask.hsw[s];
+
+ drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
+ s, hweight8(ss_mask), ss_mask);
+ }
}
+
drm_printf(p, "EU total: %u\n", sseu->eu_total);
drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
drm_printf(p, "has slice power gating: %s\n",
@@ -767,9 +801,10 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
int s, ss;
for (s = 0; s < sseu->max_slices; s++) {
+ u8 ss_mask = sseu->subslice_mask.hsw[s];
+
drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
- s, intel_sseu_subslices_per_slice(sseu, s),
- intel_sseu_get_subslices(sseu, s));
+ s, hweight8(ss_mask), ss_mask);
for (ss = 0; ss < sseu->max_subslices; ss++) {
u16 enabled_eus = sseu_get_eus(sseu, s, ss);
@@ -783,16 +818,14 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
static void sseu_print_xehp_topology(const struct sseu_dev_info *sseu,
struct drm_printer *p)
{
- u32 g_dss_mask = sseu_get_geometry_subslices(sseu);
- u32 c_dss_mask = intel_sseu_get_compute_subslices(sseu);
int dss;
for (dss = 0; dss < sseu->max_subslices; dss++) {
u16 enabled_eus = sseu_get_eus(sseu, 0, dss);
drm_printf(p, "DSS_%02d: G:%3s C:%3s, %2u EUs (0x%04hx)\n", dss,
- str_yes_no(g_dss_mask & BIT(dss)),
- str_yes_no(c_dss_mask & BIT(dss)),
+ str_yes_no(test_bit(dss, sseu->geometry_subslice_mask.xehp)),
+ str_yes_no(test_bit(dss, sseu->compute_subslice_mask.xehp)),
hweight16(enabled_eus), enabled_eus);
}
}
@@ -810,20 +843,44 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
}
}
-u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice)
+void intel_sseu_print_ss_info(const char* type,
+ const struct sseu_dev_info *sseu,
+ struct seq_file *m)
+{
+ int s;
+
+ if (sseu->has_xehp_dss) {
+ seq_printf(m, " %s Geometry DSS: %u\n", type,
+ bitmap_weight(sseu->geometry_subslice_mask.xehp,
+ BITMAP_BITS(sseu->geometry_subslice_mask)));
+ seq_printf(m, " %s Compute DSS: %u\n", type,
+ bitmap_weight(sseu->compute_subslice_mask.xehp,
+ BITMAP_BITS(sseu->compute_subslice_mask)));
+ } else {
+ for (s = 0; s < fls(sseu->slice_mask); s++)
+ seq_printf(m, " %s Slice%i subslices: %u\n", type,
+ s, hweight8(sseu->subslice_mask.hsw[s]));
+ }
+}
+
+u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask,
+ int dss_per_slice)
{
+ intel_sseu_ss_mask_t per_slice_mask = {};
u16 slice_mask = 0;
int i;
- WARN_ON(sizeof(dss_mask) * 8 / dss_per_slice > 8 * sizeof(slice_mask));
+ WARN_ON(DIV_ROUND_UP(BITMAP_BITS(dss_mask), dss_per_slice) >
+ 8 * sizeof(slice_mask));
- for (i = 0; dss_mask; i++) {
- if (dss_mask & GENMASK(dss_per_slice - 1, 0))
+ bitmap_fill(per_slice_mask.xehp, dss_per_slice);
+ for (i = 0; !bitmap_empty(dss_mask.xehp, BITMAP_BITS(dss_mask)); i++) {
+ if (bitmap_intersects(dss_mask.xehp, per_slice_mask.xehp, dss_per_slice))
slice_mask |= BIT(i);
- dss_mask >>= dss_per_slice;
+ bitmap_shift_right(dss_mask.xehp, dss_mask.xehp, dss_per_slice,
+ BITMAP_BITS(dss_mask));
}
return slice_mask;
}
-
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index ffa375e68959..0d3def55e770 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -25,12 +25,16 @@ struct drm_printer;
/*
* Maximum number of subslices that can exist within a HSW-style slice. This
* is only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the
- * GEN_MAX_DSS value below).
+ * I915_MAX_SS_FUSE_BITS value below).
*/
#define GEN_MAX_SS_PER_HSW_SLICE 6
-/* Maximum number of DSS on newer platforms (Xe_HP and beyond). */
-#define GEN_MAX_DSS 32
+/*
+ * Maximum number of 32-bit registers used by hardware to express the
+ * enabled/disabled subslices.
+ */
+#define I915_MAX_SS_FUSE_REGS 1
+#define I915_MAX_SS_FUSE_BITS (I915_MAX_SS_FUSE_REGS * 32)
/* Maximum number of EUs that can exist within a subslice or DSS. */
#define GEN_MAX_EUS_PER_SS 16
@@ -38,7 +42,7 @@ struct drm_printer;
#define SSEU_MAX(a, b) ((a) > (b) ? (a) : (b))
/* The maximum number of bits needed to express each subslice/DSS independently */
-#define GEN_SS_MASK_SIZE SSEU_MAX(GEN_MAX_DSS, \
+#define GEN_SS_MASK_SIZE SSEU_MAX(I915_MAX_SS_FUSE_BITS, \
GEN_MAX_HSW_SLICES * GEN_MAX_SS_PER_HSW_SLICE)
#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
@@ -49,17 +53,24 @@ struct drm_printer;
#define GEN_DSS_PER_CSLICE 8
#define GEN_DSS_PER_MSLICE 8
-#define GEN_MAX_GSLICES (GEN_MAX_DSS / GEN_DSS_PER_GSLICE)
-#define GEN_MAX_CSLICES (GEN_MAX_DSS / GEN_DSS_PER_CSLICE)
+#define GEN_MAX_GSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_GSLICE)
+#define GEN_MAX_CSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_CSLICE)
+
+typedef union {
+ u8 hsw[GEN_MAX_HSW_SLICES];
+
+ /* Bitmap compatible with linux/bitmap.h; may exceed size of u64 */
+ unsigned long xehp[BITS_TO_LONGS(I915_MAX_SS_FUSE_BITS)];
+} intel_sseu_ss_mask_t;
struct sseu_dev_info {
u8 slice_mask;
- u8 subslice_mask[GEN_SS_MASK_SIZE];
- u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
- u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
+ intel_sseu_ss_mask_t subslice_mask;
+ intel_sseu_ss_mask_t geometry_subslice_mask;
+ intel_sseu_ss_mask_t compute_subslice_mask;
union {
u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
- u16 xehp[GEN_MAX_DSS];
+ u16 xehp[I915_MAX_SS_FUSE_BITS];
} eu_mask;
u16 eu_total;
@@ -80,8 +91,6 @@ struct sseu_dev_info {
u8 max_slices;
u8 max_subslices;
u8 max_eus_per_subslice;
-
- u8 ss_stride;
};
/*
@@ -99,7 +108,7 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
{
struct intel_sseu value = {
.slice_mask = sseu->slice_mask,
- .subslice_mask = sseu->subslice_mask[0],
+ .subslice_mask = sseu->subslice_mask.hsw[0],
.min_eus_per_subslice = sseu->max_eus_per_subslice,
.max_eus_per_subslice = sseu->max_eus_per_subslice,
};
@@ -111,18 +120,28 @@ static inline bool
intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
int subslice)
{
- u8 mask;
- int ss_idx = subslice / BITS_PER_BYTE;
-
- if (slice >= sseu->max_slices ||
- subslice >= sseu->max_subslices)
+ if (GEM_WARN_ON(slice >= sseu->max_slices))
+ return false;
+ if (GEM_WARN_ON(subslice >= sseu->max_subslices))
return false;
- GEM_BUG_ON(ss_idx >= sseu->ss_stride);
-
- mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx];
+ if (sseu->has_xehp_dss)
+ return test_bit(subslice, sseu->subslice_mask.xehp);
+ else
+ return sseu->subslice_mask.hsw[slice] & BIT(subslice);
+}
- return mask & BIT(subslice % BITS_PER_BYTE);
+/*
+ * Used to obtain the index of the first DSS. Can start searching from the
+ * beginning of a specific dss group (e.g., gslice, cslice, etc.) if
+ * groupsize and groupnum are non-zero.
+ */
+static inline unsigned int
+intel_sseu_find_first_xehp_dss(const struct sseu_dev_info *sseu, int groupsize,
+ int groupnum)
+{
+ return find_next_bit(sseu->subslice_mask.xehp, I915_MAX_SS_FUSE_BITS,
+ groupnum * groupsize);
}
void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
@@ -132,14 +151,10 @@ unsigned int
intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
unsigned int
-intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
+intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice);
-u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
-
-u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
-
-void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
- u8 *subslice_mask, u32 ss_mask);
+intel_sseu_ss_mask_t
+intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
void intel_sseu_info_init(struct intel_gt *gt);
@@ -151,9 +166,15 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
const struct sseu_dev_info *sseu,
struct drm_printer *p);
-u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
+u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask, int dss_per_slice);
int intel_sseu_copy_eumask_to_user(void __user *to,
const struct sseu_dev_info *sseu);
+int intel_sseu_copy_ssmask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu);
+
+void intel_sseu_print_ss_info(const char* type,
+ const struct sseu_dev_info *sseu,
+ struct seq_file *m);
#endif /* __INTEL_SSEU_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
index 2d5d011e01db..c2ee5e1826b5 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
@@ -4,6 +4,7 @@
* Copyright © 2020 Intel Corporation
*/
+#include <linux/bitmap.h>
#include <linux/string_helpers.h>
#include "i915_drv.h"
@@ -11,14 +12,6 @@
#include "intel_gt_regs.h"
#include "intel_sseu_debugfs.h"
-static void sseu_copy_subslices(const struct sseu_dev_info *sseu,
- int slice, u8 *to_mask)
-{
- int offset = slice * sseu->ss_stride;
-
- memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
-}
-
static void cherryview_sseu_device_status(struct intel_gt *gt,
struct sseu_dev_info *sseu)
{
@@ -41,7 +34,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt,
continue;
sseu->slice_mask = BIT(0);
- sseu->subslice_mask[0] |= BIT(ss);
+ sseu->subslice_mask.hsw[0] |= BIT(ss);
eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
@@ -92,7 +85,7 @@ static void gen11_sseu_device_status(struct intel_gt *gt,
continue;
sseu->slice_mask |= BIT(s);
- sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -147,21 +140,17 @@ static void gen9_sseu_device_status(struct intel_gt *gt,
sseu->slice_mask |= BIT(s);
if (IS_GEN9_BC(gt->i915))
- sseu_copy_subslices(&info->sseu, s,
- sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
- u8 ss_idx = s * info->sseu.ss_stride +
- ss / BITS_PER_BYTE;
if (IS_GEN9_LP(gt->i915)) {
if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
/* skip disabled subslice */
continue;
- sseu->subslice_mask[ss_idx] |=
- BIT(ss % BITS_PER_BYTE);
+ sseu->subslice_mask.hsw[s] |= BIT(ss);
}
eu_cnt = eu_reg[2 * s + ss / 2] & eu_mask[ss % 2];
@@ -188,8 +177,7 @@ static void bdw_sseu_device_status(struct intel_gt *gt,
if (sseu->slice_mask) {
sseu->eu_per_subslice = info->sseu.eu_per_subslice;
for (s = 0; s < fls(sseu->slice_mask); s++)
- sseu_copy_subslices(&info->sseu, s,
- sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
sseu->eu_total = sseu->eu_per_subslice *
intel_sseu_subslice_total(sseu);
@@ -208,7 +196,6 @@ static void i915_print_sseu_info(struct seq_file *m,
const struct sseu_dev_info *sseu)
{
const char *type = is_available_info ? "Available" : "Enabled";
- int s;
seq_printf(m, " %s Slice Mask: %04x\n", type,
sseu->slice_mask);
@@ -216,10 +203,7 @@ static void i915_print_sseu_info(struct seq_file *m,
hweight8(sseu->slice_mask));
seq_printf(m, " %s Subslice Total: %u\n", type,
intel_sseu_subslice_total(sseu));
- for (s = 0; s < fls(sseu->slice_mask); s++) {
- seq_printf(m, " %s Slice%i subslices: %u\n", type,
- s, intel_sseu_subslices_per_slice(sseu, s));
- }
+ intel_sseu_print_ss_info(type, sseu, m);
seq_printf(m, " %s EU Total: %u\n", type,
sseu->eu_total);
seq_printf(m, " %s EU Per Subslice: %u\n", type,
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 73b59ea6fd3b..1bf62273e02d 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -948,8 +948,8 @@ gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
* on s/ss combo, the read should be done with read_subslice_reg.
*/
slice = ffs(sseu->slice_mask) - 1;
- GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
- subslice = ffs(intel_sseu_get_subslices(sseu, slice));
+ GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw));
+ subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice));
GEM_BUG_ON(!subslice);
subslice--;
@@ -1087,11 +1087,10 @@ static void
icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
{
const struct sseu_dev_info *sseu = >->info.sseu;
- unsigned int slice, subslice;
+ unsigned int subslice;
GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
- slice = 0;
/*
* Although a platform may have subslices, we need to always steer
@@ -1102,7 +1101,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
* one of the higher subslices, we run the risk of reading back 0's or
* random garbage.
*/
- subslice = __ffs(intel_sseu_get_subslices(sseu, slice));
+ subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0));
/*
* If the subslice we picked above also steers us to a valid L3 bank,
@@ -1112,7 +1111,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
if (gt->info.l3bank_mask & BIT(subslice))
gt->steering_table[L3BANK] = NULL;
- __add_mcr_wa(gt, wal, slice, subslice);
+ __add_mcr_wa(gt, wal, 0, subslice);
}
static void
@@ -1120,7 +1119,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
{
const struct sseu_dev_info *sseu = >->info.sseu;
unsigned long slice, subslice = 0, slice_mask = 0;
- u64 dss_mask = 0;
u32 lncf_mask = 0;
int i;
@@ -1151,8 +1149,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
*/
/* Find the potential gslice candidates */
- dss_mask = intel_sseu_get_subslices(sseu, 0);
- slice_mask = intel_slicemask_from_dssmask(dss_mask, GEN_DSS_PER_GSLICE);
+ slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask,
+ GEN_DSS_PER_GSLICE);
/*
* Find the potential LNCF candidates. Either LNCF within a valid
@@ -1177,9 +1175,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
}
slice = __ffs(slice_mask);
- subslice = __ffs(dss_mask >> (slice * GEN_DSS_PER_GSLICE));
+ subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice);
WARN_ON(subslice > GEN_DSS_PER_GSLICE);
- WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0);
__add_mcr_wa(gt, wal, slice, subslice);
@@ -2030,9 +2027,8 @@ engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
static bool needs_wa_1308578152(struct intel_engine_cs *engine)
{
- u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0);
-
- return (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0;
+ return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >
+ GEN_DSS_PER_GSLICE;
}
static void
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index ac9767c56619..6fd15b39570c 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -162,8 +162,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
return -EINVAL;
/* Only copy bits from the first slice */
- memcpy(&value, sseu->subslice_mask,
- min(sseu->ss_stride, (u8)sizeof(value)));
+ value = intel_sseu_get_hsw_subslices(sseu, 0);
if (!value)
return -ENODEV;
break;
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 89c475d525b8..0094f67c63f2 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -31,10 +31,11 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
static int fill_topology_info(const struct sseu_dev_info *sseu,
struct drm_i915_query_item *query_item,
- const u8 *subslice_mask)
+ intel_sseu_ss_mask_t subslice_mask)
{
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
+ int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
int eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
@@ -44,7 +45,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
return -ENODEV;
slice_length = sizeof(sseu->slice_mask);
- subslice_length = sseu->max_slices * sseu->ss_stride;
+ subslice_length = sseu->max_slices * ss_stride;
eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
total_length = sizeof(topo) + slice_length + subslice_length +
eu_length;
@@ -60,7 +61,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
topo.subslice_offset = slice_length;
- topo.subslice_stride = sseu->ss_stride;
+ topo.subslice_stride = ss_stride;
topo.eu_offset = slice_length + subslice_length;
topo.eu_stride = eu_stride;
@@ -72,9 +73,9 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
&sseu->slice_mask, slice_length))
return -EFAULT;
- if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
- sizeof(topo) + slice_length),
- subslice_mask, subslice_length))
+ if (intel_sseu_copy_ssmask_to_user(u64_to_user_ptr(query_item->data_ptr +
+ sizeof(topo) + slice_length),
+ sseu))
return -EFAULT;
if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
--
2.35.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH v4 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi
@ 2022-05-20 23:04 ` Matt Roper
0 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-05-20 23:04 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
As with EU masks, it's easier to store subslice/DSS masks internally in
a format that's more natural for the driver to work with, and then only
covert into the u8[] uapi form when the query ioctl is invoked. Since
the hardware design changed significantly with Xe_HP, we'll use a union
to choose between the old "hsw-style" subslice masks or the newer xehp
mask. HSW-style masks will be stored in an array of u8's, indexed by
slice (there's never more than 6 subslices per slice on older
platforms). For Xe_HP and beyond where slices no longer exist, we only
need a single bitmask. However we already know that this mask is
eventually going to grow too large for a simple u64 to hold, so we'll
represent it in a manner that can be operated on by the utilities in
linux/bitmap.h.
v2:
- Fix typo: BIT(s) -> BIT(ss) in gen9_sseu_device_status()
v3:
- Eliminate sseu->ss_stride and just calculate the stride while
specifically handling uapi. (Tvrtko)
- Use BITMAP_BITS() macro to refer to size of masks rather than
passing I915_MAX_SS_FUSE_BITS directly. (Tvrtko)
- Report compute/geometry DSS masks separately when dumping Xe_HP SSEU
info. (Tvrtko)
- Restore dropped range checks to intel_sseu_has_subslice(). (Tvrtko)
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 12 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 261 +++++++++++--------
drivers/gpu/drm/i915/gt/intel_sseu.h | 81 +++---
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +--
drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +-
drivers/gpu/drm/i915/i915_getparam.c | 3 +-
drivers/gpu/drm/i915/i915_query.c | 13 +-
9 files changed, 244 insertions(+), 189 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index ab4c5ab28e4d..a3bb73f5d53b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1875,6 +1875,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
{
const struct sseu_dev_info *device = >->info.sseu;
struct drm_i915_private *i915 = gt->i915;
+ unsigned int dev_subslice_mask = intel_sseu_get_hsw_subslices(device, 0);
/* No zeros in any field. */
if (!user->slice_mask || !user->subslice_mask ||
@@ -1901,7 +1902,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
if (user->slice_mask & ~device->slice_mask)
return -EINVAL;
- if (user->subslice_mask & ~device->subslice_mask[0])
+ if (user->subslice_mask & ~dev_subslice_mask)
return -EINVAL;
if (user->max_eus_per_subslice > device->max_eus_per_subslice)
@@ -1915,7 +1916,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
/* Part specific restrictions. */
if (GRAPHICS_VER(i915) == 11) {
unsigned int hw_s = hweight8(device->slice_mask);
- unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
+ unsigned int hw_ss_per_s = hweight8(dev_subslice_mask);
unsigned int req_s = hweight8(context->slice_mask);
unsigned int req_ss = hweight8(context->subslice_mask);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 1adbf34c3632..f0acf8518a51 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -674,8 +674,8 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
return;
- ccs_mask = intel_slicemask_from_dssmask(intel_sseu_get_compute_subslices(&info->sseu),
- ss_per_ccs);
+ ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
+ ss_per_ccs);
/*
* If all DSS in a quadrant are fused off, the corresponding CCS
* engine is not available for use.
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 034182f85501..2921f510642f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -133,13 +133,6 @@ static const struct intel_mmio_range dg2_lncf_steering_table[] = {
{},
};
-static u16 slicemask(struct intel_gt *gt, int count)
-{
- u64 dss_mask = intel_sseu_get_subslices(>->info.sseu, 0);
-
- return intel_slicemask_from_dssmask(dss_mask, count);
-}
-
int intel_gt_init_mmio(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
@@ -155,9 +148,12 @@ int intel_gt_init_mmio(struct intel_gt *gt)
*/
if (HAS_MSLICES(i915)) {
gt->info.mslice_mask =
- slicemask(gt, GEN_DSS_PER_MSLICE) |
+ intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
+ GEN_DSS_PER_MSLICE);
+ gt->info.mslice_mask |=
(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
GEN12_MEML3_EN_MASK);
+
if (!gt->info.mslice_mask) /* should be impossible! */
drm_warn(&i915->drm, "mslice mask all zero!\n");
}
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 285cfd758bdc..6fbc2ac507b7 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -10,15 +10,14 @@
#include "intel_gt_regs.h"
#include "intel_sseu.h"
+#define BITMAP_BITS(mask) ((int)BITS_PER_TYPE(typeof(mask)))
+
void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
u8 max_subslices, u8 max_eus_per_subslice)
{
sseu->max_slices = max_slices;
sseu->max_subslices = max_subslices;
sseu->max_eus_per_subslice = max_eus_per_subslice;
-
- sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
- GEM_BUG_ON(sseu->ss_stride > GEN_MAX_SUBSLICE_STRIDE);
}
unsigned int
@@ -26,54 +25,24 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
{
unsigned int i, total = 0;
- for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
- total += hweight8(sseu->subslice_mask[i]);
-
- return total;
-}
-
-static u32
-sseu_get_subslices(const struct sseu_dev_info *sseu,
- const u8 *subslice_mask, u8 slice)
-{
- int i, offset = slice * sseu->ss_stride;
- u32 mask = 0;
-
- GEM_BUG_ON(slice >= sseu->max_slices);
-
- for (i = 0; i < sseu->ss_stride; i++)
- mask |= (u32)subslice_mask[offset + i] << i * BITS_PER_BYTE;
-
- return mask;
-}
-
-u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
-{
- return sseu_get_subslices(sseu, sseu->subslice_mask, slice);
-}
+ if (sseu->has_xehp_dss)
+ return bitmap_weight(sseu->subslice_mask.xehp,
+ BITMAP_BITS(sseu->subslice_mask));
-static u32 sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
-{
- return sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
-}
+ for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++)
+ total += hweight8(sseu->subslice_mask.hsw[i]);
-u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu)
-{
- return sseu_get_subslices(sseu, sseu->compute_subslice_mask, 0);
-}
-
-void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
- u8 *subslice_mask, u32 ss_mask)
-{
- int offset = slice * sseu->ss_stride;
-
- memcpy(&subslice_mask[offset], &ss_mask, sseu->ss_stride);
+ return total;
}
unsigned int
-intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
+intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice)
{
- return hweight32(intel_sseu_get_subslices(sseu, slice));
+ WARN_ON(sseu->has_xehp_dss);
+ if (WARN_ON(slice >= sseu->max_slices))
+ return 0;
+
+ return sseu->subslice_mask.hsw[slice];
}
static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
@@ -147,32 +116,66 @@ int intel_sseu_copy_eumask_to_user(void __user *to,
return copy_to_user(to, eu_mask, len);
}
+/**
+ * intel_sseu_copy_ssmask_to_user - Copy subslice mask into a userspace buffer
+ * @to: Pointer to userspace buffer to copy to
+ * @sseu: SSEU structure containing subslice mask to copy
+ *
+ * Copies the subslice mask to a userspace buffer in the format expected by
+ * the query ioctl's topology queries.
+ *
+ * Returns the result of the copy_to_user() operation.
+ */
+int intel_sseu_copy_ssmask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu)
+{
+ u8 ss_mask[GEN_SS_MASK_SIZE] = {};
+ int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
+ int len = sseu->max_slices * ss_stride;
+ int s, ss, i;
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ for (ss = 0; ss < sseu->max_subslices; ss++) {
+ i = s * ss_stride * BITS_PER_BYTE + ss;
+
+ if (!intel_sseu_has_subslice(sseu, s, ss))
+ continue;
+
+ ss_mask[i / BITS_PER_BYTE] |= BIT(i % BITS_PER_BYTE);
+ }
+ }
+
+ return copy_to_user(to, ss_mask, len);
+}
+
static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
- u32 g_ss_en, u32 c_ss_en, u16 eu_en)
+ u32 ss_en, u16 eu_en)
{
u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
int ss;
- /* g_ss_en/c_ss_en represent entire subslice mask across all slices */
- GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
- sizeof(g_ss_en) * BITS_PER_BYTE);
+ sseu->slice_mask |= BIT(0);
+ sseu->subslice_mask.hsw[0] = ss_en & valid_ss_mask;
+
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (intel_sseu_has_subslice(sseu, 0, ss))
+ sseu_set_eus(sseu, 0, ss, eu_en);
+
+ sseu->eu_per_subslice = hweight16(eu_en);
+ sseu->eu_total = compute_eu_total(sseu);
+}
+
+static void xehp_compute_sseu_info(struct sseu_dev_info *sseu,
+ u16 eu_en)
+{
+ int ss;
sseu->slice_mask |= BIT(0);
- /*
- * XeHP introduces the concept of compute vs geometry DSS. To reduce
- * variation between GENs around subslice usage, store a mask for both
- * the geometry and compute enabled masks since userspace will need to
- * be able to query these masks independently. Also compute a total
- * enabled subslice count for the purposes of selecting subslices to
- * use in a particular GEM context.
- */
- intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
- c_ss_en & valid_ss_mask);
- intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
- g_ss_en & valid_ss_mask);
- intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
- (g_ss_en | c_ss_en) & valid_ss_mask);
+ bitmap_or(sseu->subslice_mask.xehp,
+ sseu->compute_subslice_mask.xehp,
+ sseu->geometry_subslice_mask.xehp,
+ BITMAP_BITS(sseu->subslice_mask));
for (ss = 0; ss < sseu->max_subslices; ss++)
if (intel_sseu_has_subslice(sseu, 0, ss))
@@ -182,11 +185,31 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
sseu->eu_total = compute_eu_total(sseu);
}
+static void
+xehp_load_dss_mask(struct intel_uncore *uncore,
+ intel_sseu_ss_mask_t *ssmask,
+ int numregs,
+ ...)
+{
+ va_list argp;
+ u32 fuse_val[I915_MAX_SS_FUSE_REGS] = {};
+ int i;
+
+ if (WARN_ON(numregs > I915_MAX_SS_FUSE_REGS))
+ numregs = I915_MAX_SS_FUSE_REGS;
+
+ va_start(argp, numregs);
+ for (i = 0; i < numregs; i++)
+ fuse_val[i] = intel_uncore_read(uncore, va_arg(argp, i915_reg_t));
+ va_end(argp);
+
+ bitmap_from_arr32(ssmask->xehp, fuse_val, numregs * 32);
+}
+
static void xehp_sseu_info_init(struct intel_gt *gt)
{
struct sseu_dev_info *sseu = >->info.sseu;
struct intel_uncore *uncore = gt->uncore;
- u32 g_dss_en, c_dss_en = 0;
u16 eu_en = 0;
u8 eu_en_fuse;
int eu;
@@ -200,8 +223,10 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
intel_sseu_set_info(sseu, 1, 32, 16);
sseu->has_xehp_dss = 1;
- g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
- c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
+ xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 1,
+ GEN12_GT_GEOMETRY_DSS_ENABLE);
+ xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 1,
+ GEN12_GT_COMPUTE_DSS_ENABLE);
eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
@@ -209,7 +234,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
+ xehp_compute_sseu_info(sseu, eu_en);
}
static void gen12_sseu_info_init(struct intel_gt *gt)
@@ -247,7 +272,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, g_dss_en, eu_en);
/* TGL only supports slice-level power gating */
sseu->has_slice_pg = 1;
@@ -279,7 +304,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
GEN11_EU_DIS_MASK);
- gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, ss_en, eu_en);
/* ICL has no power gating restrictions. */
sseu->has_slice_pg = 1;
@@ -291,7 +316,6 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
{
struct sseu_dev_info *sseu = >->info.sseu;
u32 fuse;
- u8 subslice_mask = 0;
fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT);
@@ -305,7 +329,7 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
- subslice_mask |= BIT(0);
+ sseu->subslice_mask.hsw[0] |= BIT(0);
sseu_set_eus(sseu, 0, 0, ~disabled_mask & 0xFF);
}
@@ -316,12 +340,10 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
(((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
- subslice_mask |= BIT(1);
+ sseu->subslice_mask.hsw[0] |= BIT(1);
sseu_set_eus(sseu, 0, 1, ~disabled_mask & 0xFF);
}
- intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask, subslice_mask);
-
sseu->eu_total = compute_eu_total(sseu);
/*
@@ -376,8 +398,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
/* skip disabled slice */
continue;
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
for (ss = 0; ss < sseu->max_subslices; ss++) {
@@ -434,8 +455,8 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
sseu->has_eu_pg = sseu->eu_per_subslice > 2;
if (IS_GEN9_LP(i915)) {
-#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
- info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
+#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask.hsw[0] & BIT(ss)))
+ info->has_pooled_eu = hweight8(sseu->subslice_mask.hsw[0]) == 3;
sseu->min_eu_in_pool = 0;
if (info->has_pooled_eu) {
@@ -489,8 +510,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
/* skip disabled slice */
continue;
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
for (ss = 0; ss < sseu->max_subslices; ss++) {
u8 eu_disabled_mask;
@@ -587,8 +607,7 @@ static void hsw_sseu_info_init(struct intel_gt *gt)
sseu->eu_per_subslice);
for (s = 0; s < sseu->max_slices; s++) {
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
for (ss = 0; ss < sseu->max_subslices; ss++) {
sseu_set_eus(sseu, s, ss,
@@ -677,7 +696,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
*/
if (GRAPHICS_VER(i915) == 11 &&
slices == 1 &&
- subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
+ subslices > min_t(u8, 4, hweight8(sseu->subslice_mask.hsw[0]) / 2)) {
GEM_BUG_ON(subslices & 1);
subslice_pg = false;
@@ -743,14 +762,29 @@ void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
{
int s;
- drm_printf(p, "slice total: %u, mask=%04x\n",
- hweight8(sseu->slice_mask), sseu->slice_mask);
- drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
- for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
- s, intel_sseu_subslices_per_slice(sseu, s),
- intel_sseu_get_subslices(sseu, s));
+ if (sseu->has_xehp_dss) {
+ drm_printf(p, "subslice total: %u\n",
+ intel_sseu_subslice_total(sseu));
+ drm_printf(p, "geometry dss mask=%*pb\n",
+ BITMAP_BITS(sseu->geometry_subslice_mask),
+ sseu->geometry_subslice_mask.xehp);
+ drm_printf(p, "compute dss mask=%*pb\n",
+ BITMAP_BITS(sseu->compute_subslice_mask),
+ sseu->compute_subslice_mask.xehp);
+ } else {
+ drm_printf(p, "slice total: %u, mask=%04x\n",
+ hweight8(sseu->slice_mask), sseu->slice_mask);
+ drm_printf(p, "subslice total: %u\n",
+ intel_sseu_subslice_total(sseu));
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ u8 ss_mask = sseu->subslice_mask.hsw[s];
+
+ drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
+ s, hweight8(ss_mask), ss_mask);
+ }
}
+
drm_printf(p, "EU total: %u\n", sseu->eu_total);
drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
drm_printf(p, "has slice power gating: %s\n",
@@ -767,9 +801,10 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
int s, ss;
for (s = 0; s < sseu->max_slices; s++) {
+ u8 ss_mask = sseu->subslice_mask.hsw[s];
+
drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
- s, intel_sseu_subslices_per_slice(sseu, s),
- intel_sseu_get_subslices(sseu, s));
+ s, hweight8(ss_mask), ss_mask);
for (ss = 0; ss < sseu->max_subslices; ss++) {
u16 enabled_eus = sseu_get_eus(sseu, s, ss);
@@ -783,16 +818,14 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
static void sseu_print_xehp_topology(const struct sseu_dev_info *sseu,
struct drm_printer *p)
{
- u32 g_dss_mask = sseu_get_geometry_subslices(sseu);
- u32 c_dss_mask = intel_sseu_get_compute_subslices(sseu);
int dss;
for (dss = 0; dss < sseu->max_subslices; dss++) {
u16 enabled_eus = sseu_get_eus(sseu, 0, dss);
drm_printf(p, "DSS_%02d: G:%3s C:%3s, %2u EUs (0x%04hx)\n", dss,
- str_yes_no(g_dss_mask & BIT(dss)),
- str_yes_no(c_dss_mask & BIT(dss)),
+ str_yes_no(test_bit(dss, sseu->geometry_subslice_mask.xehp)),
+ str_yes_no(test_bit(dss, sseu->compute_subslice_mask.xehp)),
hweight16(enabled_eus), enabled_eus);
}
}
@@ -810,20 +843,44 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
}
}
-u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice)
+void intel_sseu_print_ss_info(const char* type,
+ const struct sseu_dev_info *sseu,
+ struct seq_file *m)
+{
+ int s;
+
+ if (sseu->has_xehp_dss) {
+ seq_printf(m, " %s Geometry DSS: %u\n", type,
+ bitmap_weight(sseu->geometry_subslice_mask.xehp,
+ BITMAP_BITS(sseu->geometry_subslice_mask)));
+ seq_printf(m, " %s Compute DSS: %u\n", type,
+ bitmap_weight(sseu->compute_subslice_mask.xehp,
+ BITMAP_BITS(sseu->compute_subslice_mask)));
+ } else {
+ for (s = 0; s < fls(sseu->slice_mask); s++)
+ seq_printf(m, " %s Slice%i subslices: %u\n", type,
+ s, hweight8(sseu->subslice_mask.hsw[s]));
+ }
+}
+
+u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask,
+ int dss_per_slice)
{
+ intel_sseu_ss_mask_t per_slice_mask = {};
u16 slice_mask = 0;
int i;
- WARN_ON(sizeof(dss_mask) * 8 / dss_per_slice > 8 * sizeof(slice_mask));
+ WARN_ON(DIV_ROUND_UP(BITMAP_BITS(dss_mask), dss_per_slice) >
+ 8 * sizeof(slice_mask));
- for (i = 0; dss_mask; i++) {
- if (dss_mask & GENMASK(dss_per_slice - 1, 0))
+ bitmap_fill(per_slice_mask.xehp, dss_per_slice);
+ for (i = 0; !bitmap_empty(dss_mask.xehp, BITMAP_BITS(dss_mask)); i++) {
+ if (bitmap_intersects(dss_mask.xehp, per_slice_mask.xehp, dss_per_slice))
slice_mask |= BIT(i);
- dss_mask >>= dss_per_slice;
+ bitmap_shift_right(dss_mask.xehp, dss_mask.xehp, dss_per_slice,
+ BITMAP_BITS(dss_mask));
}
return slice_mask;
}
-
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index ffa375e68959..0d3def55e770 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -25,12 +25,16 @@ struct drm_printer;
/*
* Maximum number of subslices that can exist within a HSW-style slice. This
* is only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the
- * GEN_MAX_DSS value below).
+ * I915_MAX_SS_FUSE_BITS value below).
*/
#define GEN_MAX_SS_PER_HSW_SLICE 6
-/* Maximum number of DSS on newer platforms (Xe_HP and beyond). */
-#define GEN_MAX_DSS 32
+/*
+ * Maximum number of 32-bit registers used by hardware to express the
+ * enabled/disabled subslices.
+ */
+#define I915_MAX_SS_FUSE_REGS 1
+#define I915_MAX_SS_FUSE_BITS (I915_MAX_SS_FUSE_REGS * 32)
/* Maximum number of EUs that can exist within a subslice or DSS. */
#define GEN_MAX_EUS_PER_SS 16
@@ -38,7 +42,7 @@ struct drm_printer;
#define SSEU_MAX(a, b) ((a) > (b) ? (a) : (b))
/* The maximum number of bits needed to express each subslice/DSS independently */
-#define GEN_SS_MASK_SIZE SSEU_MAX(GEN_MAX_DSS, \
+#define GEN_SS_MASK_SIZE SSEU_MAX(I915_MAX_SS_FUSE_BITS, \
GEN_MAX_HSW_SLICES * GEN_MAX_SS_PER_HSW_SLICE)
#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
@@ -49,17 +53,24 @@ struct drm_printer;
#define GEN_DSS_PER_CSLICE 8
#define GEN_DSS_PER_MSLICE 8
-#define GEN_MAX_GSLICES (GEN_MAX_DSS / GEN_DSS_PER_GSLICE)
-#define GEN_MAX_CSLICES (GEN_MAX_DSS / GEN_DSS_PER_CSLICE)
+#define GEN_MAX_GSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_GSLICE)
+#define GEN_MAX_CSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_CSLICE)
+
+typedef union {
+ u8 hsw[GEN_MAX_HSW_SLICES];
+
+ /* Bitmap compatible with linux/bitmap.h; may exceed size of u64 */
+ unsigned long xehp[BITS_TO_LONGS(I915_MAX_SS_FUSE_BITS)];
+} intel_sseu_ss_mask_t;
struct sseu_dev_info {
u8 slice_mask;
- u8 subslice_mask[GEN_SS_MASK_SIZE];
- u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
- u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
+ intel_sseu_ss_mask_t subslice_mask;
+ intel_sseu_ss_mask_t geometry_subslice_mask;
+ intel_sseu_ss_mask_t compute_subslice_mask;
union {
u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
- u16 xehp[GEN_MAX_DSS];
+ u16 xehp[I915_MAX_SS_FUSE_BITS];
} eu_mask;
u16 eu_total;
@@ -80,8 +91,6 @@ struct sseu_dev_info {
u8 max_slices;
u8 max_subslices;
u8 max_eus_per_subslice;
-
- u8 ss_stride;
};
/*
@@ -99,7 +108,7 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
{
struct intel_sseu value = {
.slice_mask = sseu->slice_mask,
- .subslice_mask = sseu->subslice_mask[0],
+ .subslice_mask = sseu->subslice_mask.hsw[0],
.min_eus_per_subslice = sseu->max_eus_per_subslice,
.max_eus_per_subslice = sseu->max_eus_per_subslice,
};
@@ -111,18 +120,28 @@ static inline bool
intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
int subslice)
{
- u8 mask;
- int ss_idx = subslice / BITS_PER_BYTE;
-
- if (slice >= sseu->max_slices ||
- subslice >= sseu->max_subslices)
+ if (GEM_WARN_ON(slice >= sseu->max_slices))
+ return false;
+ if (GEM_WARN_ON(subslice >= sseu->max_subslices))
return false;
- GEM_BUG_ON(ss_idx >= sseu->ss_stride);
-
- mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx];
+ if (sseu->has_xehp_dss)
+ return test_bit(subslice, sseu->subslice_mask.xehp);
+ else
+ return sseu->subslice_mask.hsw[slice] & BIT(subslice);
+}
- return mask & BIT(subslice % BITS_PER_BYTE);
+/*
+ * Used to obtain the index of the first DSS. Can start searching from the
+ * beginning of a specific dss group (e.g., gslice, cslice, etc.) if
+ * groupsize and groupnum are non-zero.
+ */
+static inline unsigned int
+intel_sseu_find_first_xehp_dss(const struct sseu_dev_info *sseu, int groupsize,
+ int groupnum)
+{
+ return find_next_bit(sseu->subslice_mask.xehp, I915_MAX_SS_FUSE_BITS,
+ groupnum * groupsize);
}
void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
@@ -132,14 +151,10 @@ unsigned int
intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
unsigned int
-intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
+intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice);
-u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
-
-u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
-
-void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
- u8 *subslice_mask, u32 ss_mask);
+intel_sseu_ss_mask_t
+intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
void intel_sseu_info_init(struct intel_gt *gt);
@@ -151,9 +166,15 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
const struct sseu_dev_info *sseu,
struct drm_printer *p);
-u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
+u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask, int dss_per_slice);
int intel_sseu_copy_eumask_to_user(void __user *to,
const struct sseu_dev_info *sseu);
+int intel_sseu_copy_ssmask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu);
+
+void intel_sseu_print_ss_info(const char* type,
+ const struct sseu_dev_info *sseu,
+ struct seq_file *m);
#endif /* __INTEL_SSEU_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
index 2d5d011e01db..c2ee5e1826b5 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
@@ -4,6 +4,7 @@
* Copyright © 2020 Intel Corporation
*/
+#include <linux/bitmap.h>
#include <linux/string_helpers.h>
#include "i915_drv.h"
@@ -11,14 +12,6 @@
#include "intel_gt_regs.h"
#include "intel_sseu_debugfs.h"
-static void sseu_copy_subslices(const struct sseu_dev_info *sseu,
- int slice, u8 *to_mask)
-{
- int offset = slice * sseu->ss_stride;
-
- memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
-}
-
static void cherryview_sseu_device_status(struct intel_gt *gt,
struct sseu_dev_info *sseu)
{
@@ -41,7 +34,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt,
continue;
sseu->slice_mask = BIT(0);
- sseu->subslice_mask[0] |= BIT(ss);
+ sseu->subslice_mask.hsw[0] |= BIT(ss);
eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
@@ -92,7 +85,7 @@ static void gen11_sseu_device_status(struct intel_gt *gt,
continue;
sseu->slice_mask |= BIT(s);
- sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -147,21 +140,17 @@ static void gen9_sseu_device_status(struct intel_gt *gt,
sseu->slice_mask |= BIT(s);
if (IS_GEN9_BC(gt->i915))
- sseu_copy_subslices(&info->sseu, s,
- sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
- u8 ss_idx = s * info->sseu.ss_stride +
- ss / BITS_PER_BYTE;
if (IS_GEN9_LP(gt->i915)) {
if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
/* skip disabled subslice */
continue;
- sseu->subslice_mask[ss_idx] |=
- BIT(ss % BITS_PER_BYTE);
+ sseu->subslice_mask.hsw[s] |= BIT(ss);
}
eu_cnt = eu_reg[2 * s + ss / 2] & eu_mask[ss % 2];
@@ -188,8 +177,7 @@ static void bdw_sseu_device_status(struct intel_gt *gt,
if (sseu->slice_mask) {
sseu->eu_per_subslice = info->sseu.eu_per_subslice;
for (s = 0; s < fls(sseu->slice_mask); s++)
- sseu_copy_subslices(&info->sseu, s,
- sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
sseu->eu_total = sseu->eu_per_subslice *
intel_sseu_subslice_total(sseu);
@@ -208,7 +196,6 @@ static void i915_print_sseu_info(struct seq_file *m,
const struct sseu_dev_info *sseu)
{
const char *type = is_available_info ? "Available" : "Enabled";
- int s;
seq_printf(m, " %s Slice Mask: %04x\n", type,
sseu->slice_mask);
@@ -216,10 +203,7 @@ static void i915_print_sseu_info(struct seq_file *m,
hweight8(sseu->slice_mask));
seq_printf(m, " %s Subslice Total: %u\n", type,
intel_sseu_subslice_total(sseu));
- for (s = 0; s < fls(sseu->slice_mask); s++) {
- seq_printf(m, " %s Slice%i subslices: %u\n", type,
- s, intel_sseu_subslices_per_slice(sseu, s));
- }
+ intel_sseu_print_ss_info(type, sseu, m);
seq_printf(m, " %s EU Total: %u\n", type,
sseu->eu_total);
seq_printf(m, " %s EU Per Subslice: %u\n", type,
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 73b59ea6fd3b..1bf62273e02d 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -948,8 +948,8 @@ gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
* on s/ss combo, the read should be done with read_subslice_reg.
*/
slice = ffs(sseu->slice_mask) - 1;
- GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
- subslice = ffs(intel_sseu_get_subslices(sseu, slice));
+ GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw));
+ subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice));
GEM_BUG_ON(!subslice);
subslice--;
@@ -1087,11 +1087,10 @@ static void
icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
{
const struct sseu_dev_info *sseu = >->info.sseu;
- unsigned int slice, subslice;
+ unsigned int subslice;
GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
- slice = 0;
/*
* Although a platform may have subslices, we need to always steer
@@ -1102,7 +1101,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
* one of the higher subslices, we run the risk of reading back 0's or
* random garbage.
*/
- subslice = __ffs(intel_sseu_get_subslices(sseu, slice));
+ subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0));
/*
* If the subslice we picked above also steers us to a valid L3 bank,
@@ -1112,7 +1111,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
if (gt->info.l3bank_mask & BIT(subslice))
gt->steering_table[L3BANK] = NULL;
- __add_mcr_wa(gt, wal, slice, subslice);
+ __add_mcr_wa(gt, wal, 0, subslice);
}
static void
@@ -1120,7 +1119,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
{
const struct sseu_dev_info *sseu = >->info.sseu;
unsigned long slice, subslice = 0, slice_mask = 0;
- u64 dss_mask = 0;
u32 lncf_mask = 0;
int i;
@@ -1151,8 +1149,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
*/
/* Find the potential gslice candidates */
- dss_mask = intel_sseu_get_subslices(sseu, 0);
- slice_mask = intel_slicemask_from_dssmask(dss_mask, GEN_DSS_PER_GSLICE);
+ slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask,
+ GEN_DSS_PER_GSLICE);
/*
* Find the potential LNCF candidates. Either LNCF within a valid
@@ -1177,9 +1175,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
}
slice = __ffs(slice_mask);
- subslice = __ffs(dss_mask >> (slice * GEN_DSS_PER_GSLICE));
+ subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice);
WARN_ON(subslice > GEN_DSS_PER_GSLICE);
- WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0);
__add_mcr_wa(gt, wal, slice, subslice);
@@ -2030,9 +2027,8 @@ engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
static bool needs_wa_1308578152(struct intel_engine_cs *engine)
{
- u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0);
-
- return (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0;
+ return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >
+ GEN_DSS_PER_GSLICE;
}
static void
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index ac9767c56619..6fd15b39570c 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -162,8 +162,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
return -EINVAL;
/* Only copy bits from the first slice */
- memcpy(&value, sseu->subslice_mask,
- min(sseu->ss_stride, (u8)sizeof(value)));
+ value = intel_sseu_get_hsw_subslices(sseu, 0);
if (!value)
return -ENODEV;
break;
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 89c475d525b8..0094f67c63f2 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -31,10 +31,11 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
static int fill_topology_info(const struct sseu_dev_info *sseu,
struct drm_i915_query_item *query_item,
- const u8 *subslice_mask)
+ intel_sseu_ss_mask_t subslice_mask)
{
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
+ int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
int eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
@@ -44,7 +45,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
return -ENODEV;
slice_length = sizeof(sseu->slice_mask);
- subslice_length = sseu->max_slices * sseu->ss_stride;
+ subslice_length = sseu->max_slices * ss_stride;
eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
total_length = sizeof(topo) + slice_length + subslice_length +
eu_length;
@@ -60,7 +61,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
topo.subslice_offset = slice_length;
- topo.subslice_stride = sseu->ss_stride;
+ topo.subslice_stride = ss_stride;
topo.eu_offset = slice_length + subslice_length;
topo.eu_stride = eu_stride;
@@ -72,9 +73,9 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
&sseu->slice_mask, slice_length))
return -EFAULT;
- if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
- sizeof(topo) + slice_length),
- subslice_mask, subslice_length))
+ if (intel_sseu_copy_ssmask_to_user(u64_to_user_ptr(query_item->data_ptr +
+ sizeof(topo) + slice_length),
+ sseu))
return -EFAULT;
if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
--
2.35.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v4 6/6] drm/i915/pvc: Add SSEU changes
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
@ 2022-05-20 23:04 ` Matt Roper
-1 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-05-20 23:04 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
PVC splits the mask of enabled DSS over two registers. It also changes
the meaning of the EU fuse register such that each bit represents a
single EU rather than a pair of EUs.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_sseu.c | 31 ++++++++++++++++++------
drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
6 files changed, 31 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 7246eb870c7e..3f2b46c884f9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -561,6 +561,7 @@
#define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
#define GEN12_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144)
+#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT _MMIO(0x9148)
#define GEN6_UCGCTL1 _MMIO(0x9400)
#define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 6fbc2ac507b7..82e6f324b2ef 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -212,27 +212,44 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
struct intel_uncore *uncore = gt->uncore;
u16 eu_en = 0;
u8 eu_en_fuse;
+ int num_compute_regs, num_geometry_regs;
int eu;
+ if (IS_PONTEVECCHIO(gt->i915)) {
+ num_geometry_regs = 0;
+ num_compute_regs = 2;
+ } else {
+ num_geometry_regs = 1;
+ num_compute_regs = 1;
+ }
+
/*
* The concept of slice has been removed in Xe_HP. To be compatible
* with prior generations, assume a single slice across the entire
* device. Then calculate out the DSS for each workload type within
* that software slice.
*/
- intel_sseu_set_info(sseu, 1, 32, 16);
+ intel_sseu_set_info(sseu, 1,
+ 32 * max(num_geometry_regs, num_compute_regs),
+ 16);
sseu->has_xehp_dss = 1;
- xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 1,
+ xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask,
+ num_geometry_regs,
GEN12_GT_GEOMETRY_DSS_ENABLE);
- xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 1,
- GEN12_GT_COMPUTE_DSS_ENABLE);
+ xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask,
+ num_compute_regs,
+ GEN12_GT_COMPUTE_DSS_ENABLE,
+ XEHPC_GT_COMPUTE_DSS_ENABLE_EXT);
eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
- for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
- if (eu_en_fuse & BIT(eu))
- eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
+ if (HAS_ONE_EU_PER_FUSE_BIT(gt->i915))
+ eu_en = eu_en_fuse;
+ else
+ for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
+ if (eu_en_fuse & BIT(eu))
+ eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
xehp_compute_sseu_info(sseu, eu_en);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 0d3def55e770..79732c1af6c4 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -33,7 +33,7 @@ struct drm_printer;
* Maximum number of 32-bit registers used by hardware to express the
* enabled/disabled subslices.
*/
-#define I915_MAX_SS_FUSE_REGS 1
+#define I915_MAX_SS_FUSE_REGS 2
#define I915_MAX_SS_FUSE_BITS (I915_MAX_SS_FUSE_REGS * 32)
/* Maximum number of EUs that can exist within a subslice or DSS. */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c5fc402d9c50..1f8422e9511b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1405,6 +1405,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915))
+#define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
+
/* i915_gem.c */
void i915_gem_init_early(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 5ad9884874c2..9cee3c69edde 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1079,7 +1079,8 @@ static const struct intel_device_info ats_m_info = {
#define XE_HPC_FEATURES \
XE_HP_FEATURES, \
.dma_mask_size = 52, \
- .has_l3_ccs_read = 1
+ .has_l3_ccs_read = 1, \
+ .has_one_eu_per_fuse_bit = 1
__maybe_unused
static const struct intel_device_info pvc_info = {
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index a134914237dd..d4ae3a7861cd 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -157,6 +157,7 @@ enum intel_ppgtt_type {
func(has_logical_ring_elsq); \
func(has_media_ratio_mode); \
func(has_mslices); \
+ func(has_one_eu_per_fuse_bit); \
func(has_pooled_eu); \
func(has_pxp); \
func(has_rc6); \
--
2.35.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH v4 6/6] drm/i915/pvc: Add SSEU changes
@ 2022-05-20 23:04 ` Matt Roper
0 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-05-20 23:04 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
PVC splits the mask of enabled DSS over two registers. It also changes
the meaning of the EU fuse register such that each bit represents a
single EU rather than a pair of EUs.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_sseu.c | 31 ++++++++++++++++++------
drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
6 files changed, 31 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 7246eb870c7e..3f2b46c884f9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -561,6 +561,7 @@
#define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
#define GEN12_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144)
+#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT _MMIO(0x9148)
#define GEN6_UCGCTL1 _MMIO(0x9400)
#define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 6fbc2ac507b7..82e6f324b2ef 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -212,27 +212,44 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
struct intel_uncore *uncore = gt->uncore;
u16 eu_en = 0;
u8 eu_en_fuse;
+ int num_compute_regs, num_geometry_regs;
int eu;
+ if (IS_PONTEVECCHIO(gt->i915)) {
+ num_geometry_regs = 0;
+ num_compute_regs = 2;
+ } else {
+ num_geometry_regs = 1;
+ num_compute_regs = 1;
+ }
+
/*
* The concept of slice has been removed in Xe_HP. To be compatible
* with prior generations, assume a single slice across the entire
* device. Then calculate out the DSS for each workload type within
* that software slice.
*/
- intel_sseu_set_info(sseu, 1, 32, 16);
+ intel_sseu_set_info(sseu, 1,
+ 32 * max(num_geometry_regs, num_compute_regs),
+ 16);
sseu->has_xehp_dss = 1;
- xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 1,
+ xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask,
+ num_geometry_regs,
GEN12_GT_GEOMETRY_DSS_ENABLE);
- xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 1,
- GEN12_GT_COMPUTE_DSS_ENABLE);
+ xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask,
+ num_compute_regs,
+ GEN12_GT_COMPUTE_DSS_ENABLE,
+ XEHPC_GT_COMPUTE_DSS_ENABLE_EXT);
eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
- for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
- if (eu_en_fuse & BIT(eu))
- eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
+ if (HAS_ONE_EU_PER_FUSE_BIT(gt->i915))
+ eu_en = eu_en_fuse;
+ else
+ for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++)
+ if (eu_en_fuse & BIT(eu))
+ eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
xehp_compute_sseu_info(sseu, eu_en);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 0d3def55e770..79732c1af6c4 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -33,7 +33,7 @@ struct drm_printer;
* Maximum number of 32-bit registers used by hardware to express the
* enabled/disabled subslices.
*/
-#define I915_MAX_SS_FUSE_REGS 1
+#define I915_MAX_SS_FUSE_REGS 2
#define I915_MAX_SS_FUSE_BITS (I915_MAX_SS_FUSE_REGS * 32)
/* Maximum number of EUs that can exist within a subslice or DSS. */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c5fc402d9c50..1f8422e9511b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1405,6 +1405,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915))
+#define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
+
/* i915_gem.c */
void i915_gem_init_early(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 5ad9884874c2..9cee3c69edde 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1079,7 +1079,8 @@ static const struct intel_device_info ats_m_info = {
#define XE_HPC_FEATURES \
XE_HP_FEATURES, \
.dma_mask_size = 52, \
- .has_l3_ccs_read = 1
+ .has_l3_ccs_read = 1, \
+ .has_one_eu_per_fuse_bit = 1
__maybe_unused
static const struct intel_device_info pvc_info = {
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index a134914237dd..d4ae3a7861cd 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -157,6 +157,7 @@ enum intel_ppgtt_type {
func(has_logical_ring_elsq); \
func(has_media_ratio_mode); \
func(has_mslices); \
+ func(has_one_eu_per_fuse_bit); \
func(has_pooled_eu); \
func(has_pxp); \
func(has_rc6); \
--
2.35.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: SSEU handling updates
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
` (6 preceding siblings ...)
(?)
@ 2022-05-20 23:46 ` Patchwork
-1 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2022-05-20 23:46 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: i915: SSEU handling updates
URL : https://patchwork.freedesktop.org/series/104244/
State : warning
== Summary ==
Error: dim checkpatch failed
715c882f826e drm/i915/xehp: Use separate sseu init function
194ba3678abd drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
c1bbe76c5724 drm/i915/sseu: Simplify gen11+ SSEU handling
cb927114d301 drm/i915/sseu: Don't try to store EU mask internally in UAPI format
a0263df1c5fd drm/i915/sseu: Disassociate internal subslice mask representation from uapi
-:514: ERROR:POINTER_LOCATION: "foo* bar" should be "foo *bar"
#514: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:846:
+void intel_sseu_print_ss_info(const char* type,
-:602: WARNING:NEW_TYPEDEFS: do not add new typedefs
#602: FILE: drivers/gpu/drm/i915/gt/intel_sseu.h:59:
+typedef union {
-:710: ERROR:POINTER_LOCATION: "foo* bar" should be "foo *bar"
#710: FILE: drivers/gpu/drm/i915/gt/intel_sseu.h:176:
+void intel_sseu_print_ss_info(const char* type,
total: 2 errors, 1 warnings, 0 checks, 837 lines checked
2e230636389f drm/i915/pvc: Add SSEU changes
^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: SSEU handling updates
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
` (7 preceding siblings ...)
(?)
@ 2022-05-20 23:46 ` Patchwork
-1 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2022-05-20 23:46 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: i915: SSEU handling updates
URL : https://patchwork.freedesktop.org/series/104244/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: SSEU handling updates
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
` (8 preceding siblings ...)
(?)
@ 2022-05-20 23:55 ` Patchwork
-1 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2022-05-20 23:55 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 16616 bytes --]
== Series Details ==
Series: i915: SSEU handling updates
URL : https://patchwork.freedesktop.org/series/104244/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11682 -> Patchwork_104244v1
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_104244v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_104244v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/index.html
Participating hosts (44 -> 46)
------------------------------
Additional (2): bat-dg2-9 fi-tgl-u2
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_104244v1:
### IGT changes ###
#### Possible regressions ####
* igt@debugfs_test@read_all_entries:
- fi-glk-dsi: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-glk-dsi/igt@debugfs_test@read_all_entries.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-glk-dsi/igt@debugfs_test@read_all_entries.html
- fi-kbl-guc: [PASS][3] -> [DMESG-WARN][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-kbl-guc/igt@debugfs_test@read_all_entries.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-kbl-guc/igt@debugfs_test@read_all_entries.html
- fi-bdw-gvtdvm: [PASS][5] -> [DMESG-WARN][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-bdw-gvtdvm/igt@debugfs_test@read_all_entries.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-bdw-gvtdvm/igt@debugfs_test@read_all_entries.html
- fi-bsw-kefka: [PASS][7] -> [DMESG-WARN][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-bsw-kefka/igt@debugfs_test@read_all_entries.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-bsw-kefka/igt@debugfs_test@read_all_entries.html
- fi-bdw-5557u: [PASS][9] -> [DMESG-WARN][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-bdw-5557u/igt@debugfs_test@read_all_entries.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-bdw-5557u/igt@debugfs_test@read_all_entries.html
- fi-rkl-11600: [PASS][11] -> [DMESG-WARN][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-rkl-11600/igt@debugfs_test@read_all_entries.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-rkl-11600/igt@debugfs_test@read_all_entries.html
- fi-skl-guc: [PASS][13] -> [DMESG-WARN][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-skl-guc/igt@debugfs_test@read_all_entries.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-skl-guc/igt@debugfs_test@read_all_entries.html
- fi-kbl-7567u: [PASS][15] -> [DMESG-WARN][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-kbl-7567u/igt@debugfs_test@read_all_entries.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-kbl-7567u/igt@debugfs_test@read_all_entries.html
- fi-glk-j4005: [PASS][17] -> [DMESG-WARN][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-glk-j4005/igt@debugfs_test@read_all_entries.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-glk-j4005/igt@debugfs_test@read_all_entries.html
- fi-kbl-8809g: [PASS][19] -> [DMESG-WARN][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-kbl-8809g/igt@debugfs_test@read_all_entries.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-kbl-8809g/igt@debugfs_test@read_all_entries.html
- fi-bsw-nick: [PASS][21] -> [DMESG-WARN][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-bsw-nick/igt@debugfs_test@read_all_entries.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-bsw-nick/igt@debugfs_test@read_all_entries.html
- fi-tgl-1115g4: [PASS][23] -> [DMESG-WARN][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-tgl-1115g4/igt@debugfs_test@read_all_entries.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-tgl-1115g4/igt@debugfs_test@read_all_entries.html
- fi-cfl-8109u: [PASS][25] -> [DMESG-WARN][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-cfl-8109u/igt@debugfs_test@read_all_entries.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-cfl-8109u/igt@debugfs_test@read_all_entries.html
- fi-skl-6600u: [PASS][27] -> [DMESG-WARN][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-skl-6600u/igt@debugfs_test@read_all_entries.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-skl-6600u/igt@debugfs_test@read_all_entries.html
- fi-bxt-dsi: [PASS][29] -> [DMESG-WARN][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-bxt-dsi/igt@debugfs_test@read_all_entries.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-bxt-dsi/igt@debugfs_test@read_all_entries.html
- fi-cfl-8700k: [PASS][31] -> [DMESG-WARN][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-cfl-8700k/igt@debugfs_test@read_all_entries.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-cfl-8700k/igt@debugfs_test@read_all_entries.html
- fi-tgl-u2: NOTRUN -> [DMESG-WARN][33]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-tgl-u2/igt@debugfs_test@read_all_entries.html
- fi-bsw-n3050: [PASS][34] -> [DMESG-WARN][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-bsw-n3050/igt@debugfs_test@read_all_entries.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-bsw-n3050/igt@debugfs_test@read_all_entries.html
- fi-skl-6700k2: [PASS][36] -> [DMESG-WARN][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-skl-6700k2/igt@debugfs_test@read_all_entries.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-skl-6700k2/igt@debugfs_test@read_all_entries.html
- fi-cfl-guc: [PASS][38] -> [DMESG-WARN][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-cfl-guc/igt@debugfs_test@read_all_entries.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-cfl-guc/igt@debugfs_test@read_all_entries.html
* igt@runner@aborted:
- fi-rkl-guc: NOTRUN -> [FAIL][40]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-rkl-guc/igt@runner@aborted.html
- fi-adl-ddr5: NOTRUN -> [FAIL][41]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-adl-ddr5/igt@runner@aborted.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@debugfs_test@read_all_entries:
- {bat-jsl-1}: [PASS][42] -> [DMESG-WARN][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/bat-jsl-1/igt@debugfs_test@read_all_entries.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/bat-jsl-1/igt@debugfs_test@read_all_entries.html
- {bat-jsl-2}: [PASS][44] -> [DMESG-WARN][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/bat-jsl-2/igt@debugfs_test@read_all_entries.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/bat-jsl-2/igt@debugfs_test@read_all_entries.html
- {fi-ehl-2}: [PASS][46] -> [DMESG-WARN][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-ehl-2/igt@debugfs_test@read_all_entries.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-ehl-2/igt@debugfs_test@read_all_entries.html
- {fi-jsl-1}: [PASS][48] -> [DMESG-WARN][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-jsl-1/igt@debugfs_test@read_all_entries.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-jsl-1/igt@debugfs_test@read_all_entries.html
* igt@runner@aborted:
- {bat-adln-1}: NOTRUN -> [FAIL][50]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/bat-adln-1/igt@runner@aborted.html
- {bat-adlm-1}: NOTRUN -> [FAIL][51]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/bat-adlm-1/igt@runner@aborted.html
- {bat-adlp-6}: NOTRUN -> [FAIL][52]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/bat-adlp-6/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_104244v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@read_all_entries:
- fi-kbl-soraka: [PASS][53] -> [DMESG-WARN][54] ([i915#1982])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html
* igt@i915_selftest@live@gem:
- fi-blb-e6850: NOTRUN -> [DMESG-FAIL][55] ([i915#4528])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-blb-e6850/igt@i915_selftest@live@gem.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [PASS][56] -> [INCOMPLETE][57] ([i915#3921])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@runner@aborted:
- fi-rkl-11600: NOTRUN -> [FAIL][58] ([i915#4312])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-rkl-11600/igt@runner@aborted.html
- fi-bsw-kefka: NOTRUN -> [FAIL][59] ([i915#4312])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-bsw-kefka/igt@runner@aborted.html
- fi-bdw-gvtdvm: NOTRUN -> [FAIL][60] ([i915#4312])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-bdw-gvtdvm/igt@runner@aborted.html
- fi-cfl-8700k: NOTRUN -> [FAIL][61] ([i915#4312] / [i915#5257])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-cfl-8700k/igt@runner@aborted.html
- fi-skl-6600u: NOTRUN -> [FAIL][62] ([i915#4312] / [i915#5257])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-skl-6600u/igt@runner@aborted.html
- fi-cfl-8109u: NOTRUN -> [FAIL][63] ([i915#4312] / [i915#5257])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-cfl-8109u/igt@runner@aborted.html
- fi-glk-dsi: NOTRUN -> [FAIL][64] ([i915#4312] / [i915#5257])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-glk-dsi/igt@runner@aborted.html
- fi-bsw-nick: NOTRUN -> [FAIL][65] ([i915#4312])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-bsw-nick/igt@runner@aborted.html
- fi-kbl-8809g: NOTRUN -> [FAIL][66] ([i915#4312] / [i915#5257])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-kbl-8809g/igt@runner@aborted.html
- fi-bdw-5557u: NOTRUN -> [FAIL][67] ([i915#4312])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-bdw-5557u/igt@runner@aborted.html
- fi-kbl-soraka: NOTRUN -> [FAIL][68] ([i915#4312] / [i915#5257])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-kbl-soraka/igt@runner@aborted.html
- fi-kbl-guc: NOTRUN -> [FAIL][69] ([i915#4312] / [i915#5257])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-kbl-guc/igt@runner@aborted.html
- fi-bxt-dsi: NOTRUN -> [FAIL][70] ([i915#4312] / [i915#5257])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-bxt-dsi/igt@runner@aborted.html
- fi-cfl-guc: NOTRUN -> [FAIL][71] ([i915#4312] / [i915#5257])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-cfl-guc/igt@runner@aborted.html
- fi-glk-j4005: NOTRUN -> [FAIL][72] ([i915#4312] / [i915#5257])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-glk-j4005/igt@runner@aborted.html
- fi-kbl-7567u: NOTRUN -> [FAIL][73] ([i915#4312] / [i915#5257])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-kbl-7567u/igt@runner@aborted.html
- fi-skl-guc: NOTRUN -> [FAIL][74] ([i915#4312] / [i915#5257])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-skl-guc/igt@runner@aborted.html
- fi-skl-6700k2: NOTRUN -> [FAIL][75] ([i915#4312] / [i915#5257])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-skl-6700k2/igt@runner@aborted.html
- fi-bsw-n3050: NOTRUN -> [FAIL][76] ([i915#4312])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-bsw-n3050/igt@runner@aborted.html
- fi-tgl-u2: NOTRUN -> [FAIL][77] ([i915#4312] / [i915#5257])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-tgl-u2/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [DMESG-FAIL][78] ([i915#4528]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/fi-blb-e6850/igt@i915_selftest@live@requests.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/fi-blb-e6850/igt@i915_selftest@live@requests.html
#### Warnings ####
* igt@runner@aborted:
- bat-dg1-5: [FAIL][80] ([i915#4312] / [i915#5257]) -> [FAIL][81] ([i915#5257])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/bat-dg1-5/igt@runner@aborted.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/bat-dg1-5/igt@runner@aborted.html
- bat-dg1-6: [FAIL][82] ([i915#4312] / [i915#5257]) -> [FAIL][83] ([i915#5257])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11682/bat-dg1-6/igt@runner@aborted.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/bat-dg1-6/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#5171]: https://gitlab.freedesktop.org/drm/intel/issues/5171
[i915#5174]: https://gitlab.freedesktop.org/drm/intel/issues/5174
[i915#5181]: https://gitlab.freedesktop.org/drm/intel/issues/5181
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5606]: https://gitlab.freedesktop.org/drm/intel/issues/5606
[i915#5703]: https://gitlab.freedesktop.org/drm/intel/issues/5703
[i915#5775]: https://gitlab.freedesktop.org/drm/intel/issues/5775
[i915#6030]: https://gitlab.freedesktop.org/drm/intel/issues/6030
Build changes
-------------
* Linux: CI_DRM_11682 -> Patchwork_104244v1
CI-20190529: 20190529
CI_DRM_11682: 8a34ee3d1f9619f8c235c485235a1a5d20f61585 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6484: 14ad49f5b6ed861eda93e9d6b6ed0f3c77d228d1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_104244v1: 8a34ee3d1f9619f8c235c485235a1a5d20f61585 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
1c2d30fa0a47 drm/i915/pvc: Add SSEU changes
c3e603a983a8 drm/i915/sseu: Disassociate internal subslice mask representation from uapi
2ea0bf0eb68f drm/i915/sseu: Don't try to store EU mask internally in UAPI format
546c939bab69 drm/i915/sseu: Simplify gen11+ SSEU handling
d88979ad64a7 drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
3a8e16bde463 drm/i915/xehp: Use separate sseu init function
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v1/index.html
[-- Attachment #2: Type: text/html, Size: 20072 bytes --]
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
@ 2022-05-23 7:59 ` Tvrtko Ursulin
-1 siblings, 0 replies; 36+ messages in thread
From: Tvrtko Ursulin @ 2022-05-23 7:59 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel
On 21/05/2022 00:04, Matt Roper wrote:
> As with EU masks, it's easier to store subslice/DSS masks internally in
> a format that's more natural for the driver to work with, and then only
> covert into the u8[] uapi form when the query ioctl is invoked. Since
> the hardware design changed significantly with Xe_HP, we'll use a union
> to choose between the old "hsw-style" subslice masks or the newer xehp
> mask. HSW-style masks will be stored in an array of u8's, indexed by
> slice (there's never more than 6 subslices per slice on older
> platforms). For Xe_HP and beyond where slices no longer exist, we only
> need a single bitmask. However we already know that this mask is
> eventually going to grow too large for a simple u64 to hold, so we'll
> represent it in a manner that can be operated on by the utilities in
> linux/bitmap.h.
>
> v2:
> - Fix typo: BIT(s) -> BIT(ss) in gen9_sseu_device_status()
>
> v3:
> - Eliminate sseu->ss_stride and just calculate the stride while
> specifically handling uapi. (Tvrtko)
> - Use BITMAP_BITS() macro to refer to size of masks rather than
> passing I915_MAX_SS_FUSE_BITS directly. (Tvrtko)
> - Report compute/geometry DSS masks separately when dumping Xe_HP SSEU
> info. (Tvrtko)
> - Restore dropped range checks to intel_sseu_has_subslice(). (Tvrtko)
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 12 +-
> drivers/gpu/drm/i915/gt/intel_sseu.c | 261 +++++++++++--------
> drivers/gpu/drm/i915/gt/intel_sseu.h | 81 +++---
> drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +--
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +-
> drivers/gpu/drm/i915/i915_getparam.c | 3 +-
> drivers/gpu/drm/i915/i915_query.c | 13 +-
> 9 files changed, 244 insertions(+), 189 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index ab4c5ab28e4d..a3bb73f5d53b 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -1875,6 +1875,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> {
> const struct sseu_dev_info *device = >->info.sseu;
> struct drm_i915_private *i915 = gt->i915;
> + unsigned int dev_subslice_mask = intel_sseu_get_hsw_subslices(device, 0);
>
> /* No zeros in any field. */
> if (!user->slice_mask || !user->subslice_mask ||
> @@ -1901,7 +1902,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> if (user->slice_mask & ~device->slice_mask)
> return -EINVAL;
>
> - if (user->subslice_mask & ~device->subslice_mask[0])
> + if (user->subslice_mask & ~dev_subslice_mask)
> return -EINVAL;
>
> if (user->max_eus_per_subslice > device->max_eus_per_subslice)
> @@ -1915,7 +1916,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> /* Part specific restrictions. */
> if (GRAPHICS_VER(i915) == 11) {
> unsigned int hw_s = hweight8(device->slice_mask);
> - unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
> + unsigned int hw_ss_per_s = hweight8(dev_subslice_mask);
> unsigned int req_s = hweight8(context->slice_mask);
> unsigned int req_ss = hweight8(context->subslice_mask);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 1adbf34c3632..f0acf8518a51 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -674,8 +674,8 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
> if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> return;
>
> - ccs_mask = intel_slicemask_from_dssmask(intel_sseu_get_compute_subslices(&info->sseu),
> - ss_per_ccs);
> + ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
> + ss_per_ccs);
> /*
> * If all DSS in a quadrant are fused off, the corresponding CCS
> * engine is not available for use.
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 034182f85501..2921f510642f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -133,13 +133,6 @@ static const struct intel_mmio_range dg2_lncf_steering_table[] = {
> {},
> };
>
> -static u16 slicemask(struct intel_gt *gt, int count)
> -{
> - u64 dss_mask = intel_sseu_get_subslices(>->info.sseu, 0);
> -
> - return intel_slicemask_from_dssmask(dss_mask, count);
> -}
> -
> int intel_gt_init_mmio(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> @@ -155,9 +148,12 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> */
> if (HAS_MSLICES(i915)) {
> gt->info.mslice_mask =
> - slicemask(gt, GEN_DSS_PER_MSLICE) |
> + intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
> + GEN_DSS_PER_MSLICE);
> + gt->info.mslice_mask |=
> (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> GEN12_MEML3_EN_MASK);
> +
> if (!gt->info.mslice_mask) /* should be impossible! */
> drm_warn(&i915->drm, "mslice mask all zero!\n");
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index 285cfd758bdc..6fbc2ac507b7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -10,15 +10,14 @@
> #include "intel_gt_regs.h"
> #include "intel_sseu.h"
>
> +#define BITMAP_BITS(mask) ((int)BITS_PER_TYPE(typeof(mask)))
> +
> void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
> u8 max_subslices, u8 max_eus_per_subslice)
> {
> sseu->max_slices = max_slices;
> sseu->max_subslices = max_subslices;
> sseu->max_eus_per_subslice = max_eus_per_subslice;
> -
> - sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
> - GEM_BUG_ON(sseu->ss_stride > GEN_MAX_SUBSLICE_STRIDE);
> }
>
> unsigned int
> @@ -26,54 +25,24 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
> {
> unsigned int i, total = 0;
>
> - for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
> - total += hweight8(sseu->subslice_mask[i]);
> -
> - return total;
> -}
> -
> -static u32
> -sseu_get_subslices(const struct sseu_dev_info *sseu,
> - const u8 *subslice_mask, u8 slice)
> -{
> - int i, offset = slice * sseu->ss_stride;
> - u32 mask = 0;
> -
> - GEM_BUG_ON(slice >= sseu->max_slices);
> -
> - for (i = 0; i < sseu->ss_stride; i++)
> - mask |= (u32)subslice_mask[offset + i] << i * BITS_PER_BYTE;
> -
> - return mask;
> -}
> -
> -u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
> -{
> - return sseu_get_subslices(sseu, sseu->subslice_mask, slice);
> -}
> + if (sseu->has_xehp_dss)
> + return bitmap_weight(sseu->subslice_mask.xehp,
> + BITMAP_BITS(sseu->subslice_mask));
Shouldn't argument to BITMAP_BITS strictly be ***.xehp? It works without
it because union will be larger, same size as bitmap. (Or hm will it on
32-bit builds?) If so this tweak applies throughout the patch. Or append
the .xehp union member name in the macro itself? If renamed to i915
specific name that would work I think.
Regards,
Tvrtko
>
> -static u32 sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
> -{
> - return sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
> -}
> + for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++)
> + total += hweight8(sseu->subslice_mask.hsw[i]);
>
> -u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu)
> -{
> - return sseu_get_subslices(sseu, sseu->compute_subslice_mask, 0);
> -}
> -
> -void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
> - u8 *subslice_mask, u32 ss_mask)
> -{
> - int offset = slice * sseu->ss_stride;
> -
> - memcpy(&subslice_mask[offset], &ss_mask, sseu->ss_stride);
> + return total;
> }
>
> unsigned int
> -intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
> +intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice)
> {
> - return hweight32(intel_sseu_get_subslices(sseu, slice));
> + WARN_ON(sseu->has_xehp_dss);
> + if (WARN_ON(slice >= sseu->max_slices))
> + return 0;
> +
> + return sseu->subslice_mask.hsw[slice];
> }
>
> static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
> @@ -147,32 +116,66 @@ int intel_sseu_copy_eumask_to_user(void __user *to,
> return copy_to_user(to, eu_mask, len);
> }
>
> +/**
> + * intel_sseu_copy_ssmask_to_user - Copy subslice mask into a userspace buffer
> + * @to: Pointer to userspace buffer to copy to
> + * @sseu: SSEU structure containing subslice mask to copy
> + *
> + * Copies the subslice mask to a userspace buffer in the format expected by
> + * the query ioctl's topology queries.
> + *
> + * Returns the result of the copy_to_user() operation.
> + */
> +int intel_sseu_copy_ssmask_to_user(void __user *to,
> + const struct sseu_dev_info *sseu)
> +{
> + u8 ss_mask[GEN_SS_MASK_SIZE] = {};
> + int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
> + int len = sseu->max_slices * ss_stride;
> + int s, ss, i;
> +
> + for (s = 0; s < sseu->max_slices; s++) {
> + for (ss = 0; ss < sseu->max_subslices; ss++) {
> + i = s * ss_stride * BITS_PER_BYTE + ss;
> +
> + if (!intel_sseu_has_subslice(sseu, s, ss))
> + continue;
> +
> + ss_mask[i / BITS_PER_BYTE] |= BIT(i % BITS_PER_BYTE);
> + }
> + }
> +
> + return copy_to_user(to, ss_mask, len);
> +}
> +
> static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> - u32 g_ss_en, u32 c_ss_en, u16 eu_en)
> + u32 ss_en, u16 eu_en)
> {
> u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
> int ss;
>
> - /* g_ss_en/c_ss_en represent entire subslice mask across all slices */
> - GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
> - sizeof(g_ss_en) * BITS_PER_BYTE);
> + sseu->slice_mask |= BIT(0);
> + sseu->subslice_mask.hsw[0] = ss_en & valid_ss_mask;
> +
> + for (ss = 0; ss < sseu->max_subslices; ss++)
> + if (intel_sseu_has_subslice(sseu, 0, ss))
> + sseu_set_eus(sseu, 0, ss, eu_en);
> +
> + sseu->eu_per_subslice = hweight16(eu_en);
> + sseu->eu_total = compute_eu_total(sseu);
> +}
> +
> +static void xehp_compute_sseu_info(struct sseu_dev_info *sseu,
> + u16 eu_en)
> +{
> + int ss;
>
> sseu->slice_mask |= BIT(0);
>
> - /*
> - * XeHP introduces the concept of compute vs geometry DSS. To reduce
> - * variation between GENs around subslice usage, store a mask for both
> - * the geometry and compute enabled masks since userspace will need to
> - * be able to query these masks independently. Also compute a total
> - * enabled subslice count for the purposes of selecting subslices to
> - * use in a particular GEM context.
> - */
> - intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
> - c_ss_en & valid_ss_mask);
> - intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
> - g_ss_en & valid_ss_mask);
> - intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
> - (g_ss_en | c_ss_en) & valid_ss_mask);
> + bitmap_or(sseu->subslice_mask.xehp,
> + sseu->compute_subslice_mask.xehp,
> + sseu->geometry_subslice_mask.xehp,
> + BITMAP_BITS(sseu->subslice_mask));
>
> for (ss = 0; ss < sseu->max_subslices; ss++)
> if (intel_sseu_has_subslice(sseu, 0, ss))
> @@ -182,11 +185,31 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> sseu->eu_total = compute_eu_total(sseu);
> }
>
> +static void
> +xehp_load_dss_mask(struct intel_uncore *uncore,
> + intel_sseu_ss_mask_t *ssmask,
> + int numregs,
> + ...)
> +{
> + va_list argp;
> + u32 fuse_val[I915_MAX_SS_FUSE_REGS] = {};
> + int i;
> +
> + if (WARN_ON(numregs > I915_MAX_SS_FUSE_REGS))
> + numregs = I915_MAX_SS_FUSE_REGS;
> +
> + va_start(argp, numregs);
> + for (i = 0; i < numregs; i++)
> + fuse_val[i] = intel_uncore_read(uncore, va_arg(argp, i915_reg_t));
> + va_end(argp);
> +
> + bitmap_from_arr32(ssmask->xehp, fuse_val, numregs * 32);
> +}
> +
> static void xehp_sseu_info_init(struct intel_gt *gt)
> {
> struct sseu_dev_info *sseu = >->info.sseu;
> struct intel_uncore *uncore = gt->uncore;
> - u32 g_dss_en, c_dss_en = 0;
> u16 eu_en = 0;
> u8 eu_en_fuse;
> int eu;
> @@ -200,8 +223,10 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
> intel_sseu_set_info(sseu, 1, 32, 16);
> sseu->has_xehp_dss = 1;
>
> - g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
> - c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
> + xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 1,
> + GEN12_GT_GEOMETRY_DSS_ENABLE);
> + xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 1,
> + GEN12_GT_COMPUTE_DSS_ENABLE);
>
> eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
>
> @@ -209,7 +234,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
> if (eu_en_fuse & BIT(eu))
> eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
>
> - gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
> + xehp_compute_sseu_info(sseu, eu_en);
> }
>
> static void gen12_sseu_info_init(struct intel_gt *gt)
> @@ -247,7 +272,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
> if (eu_en_fuse & BIT(eu))
> eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
>
> - gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
> + gen11_compute_sseu_info(sseu, g_dss_en, eu_en);
>
> /* TGL only supports slice-level power gating */
> sseu->has_slice_pg = 1;
> @@ -279,7 +304,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
> eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
> GEN11_EU_DIS_MASK);
>
> - gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
> + gen11_compute_sseu_info(sseu, ss_en, eu_en);
>
> /* ICL has no power gating restrictions. */
> sseu->has_slice_pg = 1;
> @@ -291,7 +316,6 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> {
> struct sseu_dev_info *sseu = >->info.sseu;
> u32 fuse;
> - u8 subslice_mask = 0;
>
> fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT);
>
> @@ -305,7 +329,7 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
> CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
>
> - subslice_mask |= BIT(0);
> + sseu->subslice_mask.hsw[0] |= BIT(0);
> sseu_set_eus(sseu, 0, 0, ~disabled_mask & 0xFF);
> }
>
> @@ -316,12 +340,10 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
> CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
>
> - subslice_mask |= BIT(1);
> + sseu->subslice_mask.hsw[0] |= BIT(1);
> sseu_set_eus(sseu, 0, 1, ~disabled_mask & 0xFF);
> }
>
> - intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask, subslice_mask);
> -
> sseu->eu_total = compute_eu_total(sseu);
>
> /*
> @@ -376,8 +398,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
> /* skip disabled slice */
> continue;
>
> - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> - subslice_mask);
> + sseu->subslice_mask.hsw[s] = subslice_mask;
>
> eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> @@ -434,8 +455,8 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
> sseu->has_eu_pg = sseu->eu_per_subslice > 2;
>
> if (IS_GEN9_LP(i915)) {
> -#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
> - info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
> +#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask.hsw[0] & BIT(ss)))
> + info->has_pooled_eu = hweight8(sseu->subslice_mask.hsw[0]) == 3;
>
> sseu->min_eu_in_pool = 0;
> if (info->has_pooled_eu) {
> @@ -489,8 +510,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
> /* skip disabled slice */
> continue;
>
> - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> - subslice_mask);
> + sseu->subslice_mask.hsw[s] = subslice_mask;
>
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> u8 eu_disabled_mask;
> @@ -587,8 +607,7 @@ static void hsw_sseu_info_init(struct intel_gt *gt)
> sseu->eu_per_subslice);
>
> for (s = 0; s < sseu->max_slices; s++) {
> - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> - subslice_mask);
> + sseu->subslice_mask.hsw[s] = subslice_mask;
>
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> sseu_set_eus(sseu, s, ss,
> @@ -677,7 +696,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
> */
> if (GRAPHICS_VER(i915) == 11 &&
> slices == 1 &&
> - subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
> + subslices > min_t(u8, 4, hweight8(sseu->subslice_mask.hsw[0]) / 2)) {
> GEM_BUG_ON(subslices & 1);
>
> subslice_pg = false;
> @@ -743,14 +762,29 @@ void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
> {
> int s;
>
> - drm_printf(p, "slice total: %u, mask=%04x\n",
> - hweight8(sseu->slice_mask), sseu->slice_mask);
> - drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
> - for (s = 0; s < sseu->max_slices; s++) {
> - drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
> - s, intel_sseu_subslices_per_slice(sseu, s),
> - intel_sseu_get_subslices(sseu, s));
> + if (sseu->has_xehp_dss) {
> + drm_printf(p, "subslice total: %u\n",
> + intel_sseu_subslice_total(sseu));
> + drm_printf(p, "geometry dss mask=%*pb\n",
> + BITMAP_BITS(sseu->geometry_subslice_mask),
> + sseu->geometry_subslice_mask.xehp);
> + drm_printf(p, "compute dss mask=%*pb\n",
> + BITMAP_BITS(sseu->compute_subslice_mask),
> + sseu->compute_subslice_mask.xehp);
> + } else {
> + drm_printf(p, "slice total: %u, mask=%04x\n",
> + hweight8(sseu->slice_mask), sseu->slice_mask);
> + drm_printf(p, "subslice total: %u\n",
> + intel_sseu_subslice_total(sseu));
> +
> + for (s = 0; s < sseu->max_slices; s++) {
> + u8 ss_mask = sseu->subslice_mask.hsw[s];
> +
> + drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
> + s, hweight8(ss_mask), ss_mask);
> + }
> }
> +
> drm_printf(p, "EU total: %u\n", sseu->eu_total);
> drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
> drm_printf(p, "has slice power gating: %s\n",
> @@ -767,9 +801,10 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
> int s, ss;
>
> for (s = 0; s < sseu->max_slices; s++) {
> + u8 ss_mask = sseu->subslice_mask.hsw[s];
> +
> drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
> - s, intel_sseu_subslices_per_slice(sseu, s),
> - intel_sseu_get_subslices(sseu, s));
> + s, hweight8(ss_mask), ss_mask);
>
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> u16 enabled_eus = sseu_get_eus(sseu, s, ss);
> @@ -783,16 +818,14 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
> static void sseu_print_xehp_topology(const struct sseu_dev_info *sseu,
> struct drm_printer *p)
> {
> - u32 g_dss_mask = sseu_get_geometry_subslices(sseu);
> - u32 c_dss_mask = intel_sseu_get_compute_subslices(sseu);
> int dss;
>
> for (dss = 0; dss < sseu->max_subslices; dss++) {
> u16 enabled_eus = sseu_get_eus(sseu, 0, dss);
>
> drm_printf(p, "DSS_%02d: G:%3s C:%3s, %2u EUs (0x%04hx)\n", dss,
> - str_yes_no(g_dss_mask & BIT(dss)),
> - str_yes_no(c_dss_mask & BIT(dss)),
> + str_yes_no(test_bit(dss, sseu->geometry_subslice_mask.xehp)),
> + str_yes_no(test_bit(dss, sseu->compute_subslice_mask.xehp)),
> hweight16(enabled_eus), enabled_eus);
> }
> }
> @@ -810,20 +843,44 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
> }
> }
>
> -u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice)
> +void intel_sseu_print_ss_info(const char* type,
> + const struct sseu_dev_info *sseu,
> + struct seq_file *m)
> +{
> + int s;
> +
> + if (sseu->has_xehp_dss) {
> + seq_printf(m, " %s Geometry DSS: %u\n", type,
> + bitmap_weight(sseu->geometry_subslice_mask.xehp,
> + BITMAP_BITS(sseu->geometry_subslice_mask)));
> + seq_printf(m, " %s Compute DSS: %u\n", type,
> + bitmap_weight(sseu->compute_subslice_mask.xehp,
> + BITMAP_BITS(sseu->compute_subslice_mask)));
> + } else {
> + for (s = 0; s < fls(sseu->slice_mask); s++)
> + seq_printf(m, " %s Slice%i subslices: %u\n", type,
> + s, hweight8(sseu->subslice_mask.hsw[s]));
> + }
> +}
> +
> +u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask,
> + int dss_per_slice)
> {
> + intel_sseu_ss_mask_t per_slice_mask = {};
> u16 slice_mask = 0;
> int i;
>
> - WARN_ON(sizeof(dss_mask) * 8 / dss_per_slice > 8 * sizeof(slice_mask));
> + WARN_ON(DIV_ROUND_UP(BITMAP_BITS(dss_mask), dss_per_slice) >
> + 8 * sizeof(slice_mask));
>
> - for (i = 0; dss_mask; i++) {
> - if (dss_mask & GENMASK(dss_per_slice - 1, 0))
> + bitmap_fill(per_slice_mask.xehp, dss_per_slice);
> + for (i = 0; !bitmap_empty(dss_mask.xehp, BITMAP_BITS(dss_mask)); i++) {
> + if (bitmap_intersects(dss_mask.xehp, per_slice_mask.xehp, dss_per_slice))
> slice_mask |= BIT(i);
>
> - dss_mask >>= dss_per_slice;
> + bitmap_shift_right(dss_mask.xehp, dss_mask.xehp, dss_per_slice,
> + BITMAP_BITS(dss_mask));
> }
>
> return slice_mask;
> }
> -
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
> index ffa375e68959..0d3def55e770 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> @@ -25,12 +25,16 @@ struct drm_printer;
> /*
> * Maximum number of subslices that can exist within a HSW-style slice. This
> * is only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the
> - * GEN_MAX_DSS value below).
> + * I915_MAX_SS_FUSE_BITS value below).
> */
> #define GEN_MAX_SS_PER_HSW_SLICE 6
>
> -/* Maximum number of DSS on newer platforms (Xe_HP and beyond). */
> -#define GEN_MAX_DSS 32
> +/*
> + * Maximum number of 32-bit registers used by hardware to express the
> + * enabled/disabled subslices.
> + */
> +#define I915_MAX_SS_FUSE_REGS 1
> +#define I915_MAX_SS_FUSE_BITS (I915_MAX_SS_FUSE_REGS * 32)
>
> /* Maximum number of EUs that can exist within a subslice or DSS. */
> #define GEN_MAX_EUS_PER_SS 16
> @@ -38,7 +42,7 @@ struct drm_printer;
> #define SSEU_MAX(a, b) ((a) > (b) ? (a) : (b))
>
> /* The maximum number of bits needed to express each subslice/DSS independently */
> -#define GEN_SS_MASK_SIZE SSEU_MAX(GEN_MAX_DSS, \
> +#define GEN_SS_MASK_SIZE SSEU_MAX(I915_MAX_SS_FUSE_BITS, \
> GEN_MAX_HSW_SLICES * GEN_MAX_SS_PER_HSW_SLICE)
>
> #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
> @@ -49,17 +53,24 @@ struct drm_printer;
> #define GEN_DSS_PER_CSLICE 8
> #define GEN_DSS_PER_MSLICE 8
>
> -#define GEN_MAX_GSLICES (GEN_MAX_DSS / GEN_DSS_PER_GSLICE)
> -#define GEN_MAX_CSLICES (GEN_MAX_DSS / GEN_DSS_PER_CSLICE)
> +#define GEN_MAX_GSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_GSLICE)
> +#define GEN_MAX_CSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_CSLICE)
> +
> +typedef union {
> + u8 hsw[GEN_MAX_HSW_SLICES];
> +
> + /* Bitmap compatible with linux/bitmap.h; may exceed size of u64 */
> + unsigned long xehp[BITS_TO_LONGS(I915_MAX_SS_FUSE_BITS)];
> +} intel_sseu_ss_mask_t;
>
> struct sseu_dev_info {
> u8 slice_mask;
> - u8 subslice_mask[GEN_SS_MASK_SIZE];
> - u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
> - u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
> + intel_sseu_ss_mask_t subslice_mask;
> + intel_sseu_ss_mask_t geometry_subslice_mask;
> + intel_sseu_ss_mask_t compute_subslice_mask;
> union {
> u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
> - u16 xehp[GEN_MAX_DSS];
> + u16 xehp[I915_MAX_SS_FUSE_BITS];
> } eu_mask;
>
> u16 eu_total;
> @@ -80,8 +91,6 @@ struct sseu_dev_info {
> u8 max_slices;
> u8 max_subslices;
> u8 max_eus_per_subslice;
> -
> - u8 ss_stride;
> };
>
> /*
> @@ -99,7 +108,7 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
> {
> struct intel_sseu value = {
> .slice_mask = sseu->slice_mask,
> - .subslice_mask = sseu->subslice_mask[0],
> + .subslice_mask = sseu->subslice_mask.hsw[0],
> .min_eus_per_subslice = sseu->max_eus_per_subslice,
> .max_eus_per_subslice = sseu->max_eus_per_subslice,
> };
> @@ -111,18 +120,28 @@ static inline bool
> intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
> int subslice)
> {
> - u8 mask;
> - int ss_idx = subslice / BITS_PER_BYTE;
> -
> - if (slice >= sseu->max_slices ||
> - subslice >= sseu->max_subslices)
> + if (GEM_WARN_ON(slice >= sseu->max_slices))
> + return false;
> + if (GEM_WARN_ON(subslice >= sseu->max_subslices))
> return false;
>
> - GEM_BUG_ON(ss_idx >= sseu->ss_stride);
> -
> - mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx];
> + if (sseu->has_xehp_dss)
> + return test_bit(subslice, sseu->subslice_mask.xehp);
> + else
> + return sseu->subslice_mask.hsw[slice] & BIT(subslice);
> +}
>
> - return mask & BIT(subslice % BITS_PER_BYTE);
> +/*
> + * Used to obtain the index of the first DSS. Can start searching from the
> + * beginning of a specific dss group (e.g., gslice, cslice, etc.) if
> + * groupsize and groupnum are non-zero.
> + */
> +static inline unsigned int
> +intel_sseu_find_first_xehp_dss(const struct sseu_dev_info *sseu, int groupsize,
> + int groupnum)
> +{
> + return find_next_bit(sseu->subslice_mask.xehp, I915_MAX_SS_FUSE_BITS,
> + groupnum * groupsize);
> }
>
> void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
> @@ -132,14 +151,10 @@ unsigned int
> intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
>
> unsigned int
> -intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
> +intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice);
>
> -u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
> -
> -u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
> -
> -void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
> - u8 *subslice_mask, u32 ss_mask);
> +intel_sseu_ss_mask_t
> +intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
>
> void intel_sseu_info_init(struct intel_gt *gt);
>
> @@ -151,9 +166,15 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
> const struct sseu_dev_info *sseu,
> struct drm_printer *p);
>
> -u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
> +u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask, int dss_per_slice);
>
> int intel_sseu_copy_eumask_to_user(void __user *to,
> const struct sseu_dev_info *sseu);
> +int intel_sseu_copy_ssmask_to_user(void __user *to,
> + const struct sseu_dev_info *sseu);
> +
> +void intel_sseu_print_ss_info(const char* type,
> + const struct sseu_dev_info *sseu,
> + struct seq_file *m);
>
> #endif /* __INTEL_SSEU_H__ */
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> index 2d5d011e01db..c2ee5e1826b5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> @@ -4,6 +4,7 @@
> * Copyright © 2020 Intel Corporation
> */
>
> +#include <linux/bitmap.h>
> #include <linux/string_helpers.h>
>
> #include "i915_drv.h"
> @@ -11,14 +12,6 @@
> #include "intel_gt_regs.h"
> #include "intel_sseu_debugfs.h"
>
> -static void sseu_copy_subslices(const struct sseu_dev_info *sseu,
> - int slice, u8 *to_mask)
> -{
> - int offset = slice * sseu->ss_stride;
> -
> - memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
> -}
> -
> static void cherryview_sseu_device_status(struct intel_gt *gt,
> struct sseu_dev_info *sseu)
> {
> @@ -41,7 +34,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt,
> continue;
>
> sseu->slice_mask = BIT(0);
> - sseu->subslice_mask[0] |= BIT(ss);
> + sseu->subslice_mask.hsw[0] |= BIT(ss);
> eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
> ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
> ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
> @@ -92,7 +85,7 @@ static void gen11_sseu_device_status(struct intel_gt *gt,
> continue;
>
> sseu->slice_mask |= BIT(s);
> - sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
> + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
>
> for (ss = 0; ss < info->sseu.max_subslices; ss++) {
> unsigned int eu_cnt;
> @@ -147,21 +140,17 @@ static void gen9_sseu_device_status(struct intel_gt *gt,
> sseu->slice_mask |= BIT(s);
>
> if (IS_GEN9_BC(gt->i915))
> - sseu_copy_subslices(&info->sseu, s,
> - sseu->subslice_mask);
> + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
>
> for (ss = 0; ss < info->sseu.max_subslices; ss++) {
> unsigned int eu_cnt;
> - u8 ss_idx = s * info->sseu.ss_stride +
> - ss / BITS_PER_BYTE;
>
> if (IS_GEN9_LP(gt->i915)) {
> if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> /* skip disabled subslice */
> continue;
>
> - sseu->subslice_mask[ss_idx] |=
> - BIT(ss % BITS_PER_BYTE);
> + sseu->subslice_mask.hsw[s] |= BIT(ss);
> }
>
> eu_cnt = eu_reg[2 * s + ss / 2] & eu_mask[ss % 2];
> @@ -188,8 +177,7 @@ static void bdw_sseu_device_status(struct intel_gt *gt,
> if (sseu->slice_mask) {
> sseu->eu_per_subslice = info->sseu.eu_per_subslice;
> for (s = 0; s < fls(sseu->slice_mask); s++)
> - sseu_copy_subslices(&info->sseu, s,
> - sseu->subslice_mask);
> + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
> sseu->eu_total = sseu->eu_per_subslice *
> intel_sseu_subslice_total(sseu);
>
> @@ -208,7 +196,6 @@ static void i915_print_sseu_info(struct seq_file *m,
> const struct sseu_dev_info *sseu)
> {
> const char *type = is_available_info ? "Available" : "Enabled";
> - int s;
>
> seq_printf(m, " %s Slice Mask: %04x\n", type,
> sseu->slice_mask);
> @@ -216,10 +203,7 @@ static void i915_print_sseu_info(struct seq_file *m,
> hweight8(sseu->slice_mask));
> seq_printf(m, " %s Subslice Total: %u\n", type,
> intel_sseu_subslice_total(sseu));
> - for (s = 0; s < fls(sseu->slice_mask); s++) {
> - seq_printf(m, " %s Slice%i subslices: %u\n", type,
> - s, intel_sseu_subslices_per_slice(sseu, s));
> - }
> + intel_sseu_print_ss_info(type, sseu, m);
> seq_printf(m, " %s EU Total: %u\n", type,
> sseu->eu_total);
> seq_printf(m, " %s EU Per Subslice: %u\n", type,
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 73b59ea6fd3b..1bf62273e02d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -948,8 +948,8 @@ gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> * on s/ss combo, the read should be done with read_subslice_reg.
> */
> slice = ffs(sseu->slice_mask) - 1;
> - GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
> - subslice = ffs(intel_sseu_get_subslices(sseu, slice));
> + GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw));
> + subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice));
> GEM_BUG_ON(!subslice);
> subslice--;
>
> @@ -1087,11 +1087,10 @@ static void
> icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> const struct sseu_dev_info *sseu = >->info.sseu;
> - unsigned int slice, subslice;
> + unsigned int subslice;
>
> GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
> GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
> - slice = 0;
>
> /*
> * Although a platform may have subslices, we need to always steer
> @@ -1102,7 +1101,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> * one of the higher subslices, we run the risk of reading back 0's or
> * random garbage.
> */
> - subslice = __ffs(intel_sseu_get_subslices(sseu, slice));
> + subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0));
>
> /*
> * If the subslice we picked above also steers us to a valid L3 bank,
> @@ -1112,7 +1111,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> if (gt->info.l3bank_mask & BIT(subslice))
> gt->steering_table[L3BANK] = NULL;
>
> - __add_mcr_wa(gt, wal, slice, subslice);
> + __add_mcr_wa(gt, wal, 0, subslice);
> }
>
> static void
> @@ -1120,7 +1119,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> const struct sseu_dev_info *sseu = >->info.sseu;
> unsigned long slice, subslice = 0, slice_mask = 0;
> - u64 dss_mask = 0;
> u32 lncf_mask = 0;
> int i;
>
> @@ -1151,8 +1149,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> */
>
> /* Find the potential gslice candidates */
> - dss_mask = intel_sseu_get_subslices(sseu, 0);
> - slice_mask = intel_slicemask_from_dssmask(dss_mask, GEN_DSS_PER_GSLICE);
> + slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask,
> + GEN_DSS_PER_GSLICE);
>
> /*
> * Find the potential LNCF candidates. Either LNCF within a valid
> @@ -1177,9 +1175,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> }
>
> slice = __ffs(slice_mask);
> - subslice = __ffs(dss_mask >> (slice * GEN_DSS_PER_GSLICE));
> + subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice);
> WARN_ON(subslice > GEN_DSS_PER_GSLICE);
> - WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0);
>
> __add_mcr_wa(gt, wal, slice, subslice);
>
> @@ -2030,9 +2027,8 @@ engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>
> static bool needs_wa_1308578152(struct intel_engine_cs *engine)
> {
> - u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0);
> -
> - return (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0;
> + return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >
> + GEN_DSS_PER_GSLICE;
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
> index ac9767c56619..6fd15b39570c 100644
> --- a/drivers/gpu/drm/i915/i915_getparam.c
> +++ b/drivers/gpu/drm/i915/i915_getparam.c
> @@ -162,8 +162,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
> return -EINVAL;
>
> /* Only copy bits from the first slice */
> - memcpy(&value, sseu->subslice_mask,
> - min(sseu->ss_stride, (u8)sizeof(value)));
> + value = intel_sseu_get_hsw_subslices(sseu, 0);
> if (!value)
> return -ENODEV;
> break;
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 89c475d525b8..0094f67c63f2 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -31,10 +31,11 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
>
> static int fill_topology_info(const struct sseu_dev_info *sseu,
> struct drm_i915_query_item *query_item,
> - const u8 *subslice_mask)
> + intel_sseu_ss_mask_t subslice_mask)
> {
> struct drm_i915_query_topology_info topo;
> u32 slice_length, subslice_length, eu_length, total_length;
> + int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
> int eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
> int ret;
>
> @@ -44,7 +45,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
> return -ENODEV;
>
> slice_length = sizeof(sseu->slice_mask);
> - subslice_length = sseu->max_slices * sseu->ss_stride;
> + subslice_length = sseu->max_slices * ss_stride;
> eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
> total_length = sizeof(topo) + slice_length + subslice_length +
> eu_length;
> @@ -60,7 +61,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
> topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
>
> topo.subslice_offset = slice_length;
> - topo.subslice_stride = sseu->ss_stride;
> + topo.subslice_stride = ss_stride;
> topo.eu_offset = slice_length + subslice_length;
> topo.eu_stride = eu_stride;
>
> @@ -72,9 +73,9 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
> &sseu->slice_mask, slice_length))
> return -EFAULT;
>
> - if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
> - sizeof(topo) + slice_length),
> - subslice_mask, subslice_length))
> + if (intel_sseu_copy_ssmask_to_user(u64_to_user_ptr(query_item->data_ptr +
> + sizeof(topo) + slice_length),
> + sseu))
> return -EFAULT;
>
> if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v4 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi
@ 2022-05-23 7:59 ` Tvrtko Ursulin
0 siblings, 0 replies; 36+ messages in thread
From: Tvrtko Ursulin @ 2022-05-23 7:59 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel
On 21/05/2022 00:04, Matt Roper wrote:
> As with EU masks, it's easier to store subslice/DSS masks internally in
> a format that's more natural for the driver to work with, and then only
> covert into the u8[] uapi form when the query ioctl is invoked. Since
> the hardware design changed significantly with Xe_HP, we'll use a union
> to choose between the old "hsw-style" subslice masks or the newer xehp
> mask. HSW-style masks will be stored in an array of u8's, indexed by
> slice (there's never more than 6 subslices per slice on older
> platforms). For Xe_HP and beyond where slices no longer exist, we only
> need a single bitmask. However we already know that this mask is
> eventually going to grow too large for a simple u64 to hold, so we'll
> represent it in a manner that can be operated on by the utilities in
> linux/bitmap.h.
>
> v2:
> - Fix typo: BIT(s) -> BIT(ss) in gen9_sseu_device_status()
>
> v3:
> - Eliminate sseu->ss_stride and just calculate the stride while
> specifically handling uapi. (Tvrtko)
> - Use BITMAP_BITS() macro to refer to size of masks rather than
> passing I915_MAX_SS_FUSE_BITS directly. (Tvrtko)
> - Report compute/geometry DSS masks separately when dumping Xe_HP SSEU
> info. (Tvrtko)
> - Restore dropped range checks to intel_sseu_has_subslice(). (Tvrtko)
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 12 +-
> drivers/gpu/drm/i915/gt/intel_sseu.c | 261 +++++++++++--------
> drivers/gpu/drm/i915/gt/intel_sseu.h | 81 +++---
> drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +--
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +-
> drivers/gpu/drm/i915/i915_getparam.c | 3 +-
> drivers/gpu/drm/i915/i915_query.c | 13 +-
> 9 files changed, 244 insertions(+), 189 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index ab4c5ab28e4d..a3bb73f5d53b 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -1875,6 +1875,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> {
> const struct sseu_dev_info *device = >->info.sseu;
> struct drm_i915_private *i915 = gt->i915;
> + unsigned int dev_subslice_mask = intel_sseu_get_hsw_subslices(device, 0);
>
> /* No zeros in any field. */
> if (!user->slice_mask || !user->subslice_mask ||
> @@ -1901,7 +1902,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> if (user->slice_mask & ~device->slice_mask)
> return -EINVAL;
>
> - if (user->subslice_mask & ~device->subslice_mask[0])
> + if (user->subslice_mask & ~dev_subslice_mask)
> return -EINVAL;
>
> if (user->max_eus_per_subslice > device->max_eus_per_subslice)
> @@ -1915,7 +1916,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> /* Part specific restrictions. */
> if (GRAPHICS_VER(i915) == 11) {
> unsigned int hw_s = hweight8(device->slice_mask);
> - unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
> + unsigned int hw_ss_per_s = hweight8(dev_subslice_mask);
> unsigned int req_s = hweight8(context->slice_mask);
> unsigned int req_ss = hweight8(context->subslice_mask);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 1adbf34c3632..f0acf8518a51 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -674,8 +674,8 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
> if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> return;
>
> - ccs_mask = intel_slicemask_from_dssmask(intel_sseu_get_compute_subslices(&info->sseu),
> - ss_per_ccs);
> + ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
> + ss_per_ccs);
> /*
> * If all DSS in a quadrant are fused off, the corresponding CCS
> * engine is not available for use.
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 034182f85501..2921f510642f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -133,13 +133,6 @@ static const struct intel_mmio_range dg2_lncf_steering_table[] = {
> {},
> };
>
> -static u16 slicemask(struct intel_gt *gt, int count)
> -{
> - u64 dss_mask = intel_sseu_get_subslices(>->info.sseu, 0);
> -
> - return intel_slicemask_from_dssmask(dss_mask, count);
> -}
> -
> int intel_gt_init_mmio(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> @@ -155,9 +148,12 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> */
> if (HAS_MSLICES(i915)) {
> gt->info.mslice_mask =
> - slicemask(gt, GEN_DSS_PER_MSLICE) |
> + intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
> + GEN_DSS_PER_MSLICE);
> + gt->info.mslice_mask |=
> (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> GEN12_MEML3_EN_MASK);
> +
> if (!gt->info.mslice_mask) /* should be impossible! */
> drm_warn(&i915->drm, "mslice mask all zero!\n");
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index 285cfd758bdc..6fbc2ac507b7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -10,15 +10,14 @@
> #include "intel_gt_regs.h"
> #include "intel_sseu.h"
>
> +#define BITMAP_BITS(mask) ((int)BITS_PER_TYPE(typeof(mask)))
> +
> void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
> u8 max_subslices, u8 max_eus_per_subslice)
> {
> sseu->max_slices = max_slices;
> sseu->max_subslices = max_subslices;
> sseu->max_eus_per_subslice = max_eus_per_subslice;
> -
> - sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
> - GEM_BUG_ON(sseu->ss_stride > GEN_MAX_SUBSLICE_STRIDE);
> }
>
> unsigned int
> @@ -26,54 +25,24 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
> {
> unsigned int i, total = 0;
>
> - for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
> - total += hweight8(sseu->subslice_mask[i]);
> -
> - return total;
> -}
> -
> -static u32
> -sseu_get_subslices(const struct sseu_dev_info *sseu,
> - const u8 *subslice_mask, u8 slice)
> -{
> - int i, offset = slice * sseu->ss_stride;
> - u32 mask = 0;
> -
> - GEM_BUG_ON(slice >= sseu->max_slices);
> -
> - for (i = 0; i < sseu->ss_stride; i++)
> - mask |= (u32)subslice_mask[offset + i] << i * BITS_PER_BYTE;
> -
> - return mask;
> -}
> -
> -u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
> -{
> - return sseu_get_subslices(sseu, sseu->subslice_mask, slice);
> -}
> + if (sseu->has_xehp_dss)
> + return bitmap_weight(sseu->subslice_mask.xehp,
> + BITMAP_BITS(sseu->subslice_mask));
Shouldn't argument to BITMAP_BITS strictly be ***.xehp? It works without
it because union will be larger, same size as bitmap. (Or hm will it on
32-bit builds?) If so this tweak applies throughout the patch. Or append
the .xehp union member name in the macro itself? If renamed to i915
specific name that would work I think.
Regards,
Tvrtko
>
> -static u32 sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
> -{
> - return sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
> -}
> + for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++)
> + total += hweight8(sseu->subslice_mask.hsw[i]);
>
> -u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu)
> -{
> - return sseu_get_subslices(sseu, sseu->compute_subslice_mask, 0);
> -}
> -
> -void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
> - u8 *subslice_mask, u32 ss_mask)
> -{
> - int offset = slice * sseu->ss_stride;
> -
> - memcpy(&subslice_mask[offset], &ss_mask, sseu->ss_stride);
> + return total;
> }
>
> unsigned int
> -intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
> +intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice)
> {
> - return hweight32(intel_sseu_get_subslices(sseu, slice));
> + WARN_ON(sseu->has_xehp_dss);
> + if (WARN_ON(slice >= sseu->max_slices))
> + return 0;
> +
> + return sseu->subslice_mask.hsw[slice];
> }
>
> static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
> @@ -147,32 +116,66 @@ int intel_sseu_copy_eumask_to_user(void __user *to,
> return copy_to_user(to, eu_mask, len);
> }
>
> +/**
> + * intel_sseu_copy_ssmask_to_user - Copy subslice mask into a userspace buffer
> + * @to: Pointer to userspace buffer to copy to
> + * @sseu: SSEU structure containing subslice mask to copy
> + *
> + * Copies the subslice mask to a userspace buffer in the format expected by
> + * the query ioctl's topology queries.
> + *
> + * Returns the result of the copy_to_user() operation.
> + */
> +int intel_sseu_copy_ssmask_to_user(void __user *to,
> + const struct sseu_dev_info *sseu)
> +{
> + u8 ss_mask[GEN_SS_MASK_SIZE] = {};
> + int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
> + int len = sseu->max_slices * ss_stride;
> + int s, ss, i;
> +
> + for (s = 0; s < sseu->max_slices; s++) {
> + for (ss = 0; ss < sseu->max_subslices; ss++) {
> + i = s * ss_stride * BITS_PER_BYTE + ss;
> +
> + if (!intel_sseu_has_subslice(sseu, s, ss))
> + continue;
> +
> + ss_mask[i / BITS_PER_BYTE] |= BIT(i % BITS_PER_BYTE);
> + }
> + }
> +
> + return copy_to_user(to, ss_mask, len);
> +}
> +
> static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> - u32 g_ss_en, u32 c_ss_en, u16 eu_en)
> + u32 ss_en, u16 eu_en)
> {
> u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
> int ss;
>
> - /* g_ss_en/c_ss_en represent entire subslice mask across all slices */
> - GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
> - sizeof(g_ss_en) * BITS_PER_BYTE);
> + sseu->slice_mask |= BIT(0);
> + sseu->subslice_mask.hsw[0] = ss_en & valid_ss_mask;
> +
> + for (ss = 0; ss < sseu->max_subslices; ss++)
> + if (intel_sseu_has_subslice(sseu, 0, ss))
> + sseu_set_eus(sseu, 0, ss, eu_en);
> +
> + sseu->eu_per_subslice = hweight16(eu_en);
> + sseu->eu_total = compute_eu_total(sseu);
> +}
> +
> +static void xehp_compute_sseu_info(struct sseu_dev_info *sseu,
> + u16 eu_en)
> +{
> + int ss;
>
> sseu->slice_mask |= BIT(0);
>
> - /*
> - * XeHP introduces the concept of compute vs geometry DSS. To reduce
> - * variation between GENs around subslice usage, store a mask for both
> - * the geometry and compute enabled masks since userspace will need to
> - * be able to query these masks independently. Also compute a total
> - * enabled subslice count for the purposes of selecting subslices to
> - * use in a particular GEM context.
> - */
> - intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
> - c_ss_en & valid_ss_mask);
> - intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
> - g_ss_en & valid_ss_mask);
> - intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
> - (g_ss_en | c_ss_en) & valid_ss_mask);
> + bitmap_or(sseu->subslice_mask.xehp,
> + sseu->compute_subslice_mask.xehp,
> + sseu->geometry_subslice_mask.xehp,
> + BITMAP_BITS(sseu->subslice_mask));
>
> for (ss = 0; ss < sseu->max_subslices; ss++)
> if (intel_sseu_has_subslice(sseu, 0, ss))
> @@ -182,11 +185,31 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> sseu->eu_total = compute_eu_total(sseu);
> }
>
> +static void
> +xehp_load_dss_mask(struct intel_uncore *uncore,
> + intel_sseu_ss_mask_t *ssmask,
> + int numregs,
> + ...)
> +{
> + va_list argp;
> + u32 fuse_val[I915_MAX_SS_FUSE_REGS] = {};
> + int i;
> +
> + if (WARN_ON(numregs > I915_MAX_SS_FUSE_REGS))
> + numregs = I915_MAX_SS_FUSE_REGS;
> +
> + va_start(argp, numregs);
> + for (i = 0; i < numregs; i++)
> + fuse_val[i] = intel_uncore_read(uncore, va_arg(argp, i915_reg_t));
> + va_end(argp);
> +
> + bitmap_from_arr32(ssmask->xehp, fuse_val, numregs * 32);
> +}
> +
> static void xehp_sseu_info_init(struct intel_gt *gt)
> {
> struct sseu_dev_info *sseu = >->info.sseu;
> struct intel_uncore *uncore = gt->uncore;
> - u32 g_dss_en, c_dss_en = 0;
> u16 eu_en = 0;
> u8 eu_en_fuse;
> int eu;
> @@ -200,8 +223,10 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
> intel_sseu_set_info(sseu, 1, 32, 16);
> sseu->has_xehp_dss = 1;
>
> - g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
> - c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
> + xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 1,
> + GEN12_GT_GEOMETRY_DSS_ENABLE);
> + xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 1,
> + GEN12_GT_COMPUTE_DSS_ENABLE);
>
> eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
>
> @@ -209,7 +234,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
> if (eu_en_fuse & BIT(eu))
> eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
>
> - gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
> + xehp_compute_sseu_info(sseu, eu_en);
> }
>
> static void gen12_sseu_info_init(struct intel_gt *gt)
> @@ -247,7 +272,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
> if (eu_en_fuse & BIT(eu))
> eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
>
> - gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
> + gen11_compute_sseu_info(sseu, g_dss_en, eu_en);
>
> /* TGL only supports slice-level power gating */
> sseu->has_slice_pg = 1;
> @@ -279,7 +304,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
> eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
> GEN11_EU_DIS_MASK);
>
> - gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
> + gen11_compute_sseu_info(sseu, ss_en, eu_en);
>
> /* ICL has no power gating restrictions. */
> sseu->has_slice_pg = 1;
> @@ -291,7 +316,6 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> {
> struct sseu_dev_info *sseu = >->info.sseu;
> u32 fuse;
> - u8 subslice_mask = 0;
>
> fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT);
>
> @@ -305,7 +329,7 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
> CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
>
> - subslice_mask |= BIT(0);
> + sseu->subslice_mask.hsw[0] |= BIT(0);
> sseu_set_eus(sseu, 0, 0, ~disabled_mask & 0xFF);
> }
>
> @@ -316,12 +340,10 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
> CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
>
> - subslice_mask |= BIT(1);
> + sseu->subslice_mask.hsw[0] |= BIT(1);
> sseu_set_eus(sseu, 0, 1, ~disabled_mask & 0xFF);
> }
>
> - intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask, subslice_mask);
> -
> sseu->eu_total = compute_eu_total(sseu);
>
> /*
> @@ -376,8 +398,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
> /* skip disabled slice */
> continue;
>
> - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> - subslice_mask);
> + sseu->subslice_mask.hsw[s] = subslice_mask;
>
> eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> @@ -434,8 +455,8 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
> sseu->has_eu_pg = sseu->eu_per_subslice > 2;
>
> if (IS_GEN9_LP(i915)) {
> -#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
> - info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
> +#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask.hsw[0] & BIT(ss)))
> + info->has_pooled_eu = hweight8(sseu->subslice_mask.hsw[0]) == 3;
>
> sseu->min_eu_in_pool = 0;
> if (info->has_pooled_eu) {
> @@ -489,8 +510,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
> /* skip disabled slice */
> continue;
>
> - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> - subslice_mask);
> + sseu->subslice_mask.hsw[s] = subslice_mask;
>
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> u8 eu_disabled_mask;
> @@ -587,8 +607,7 @@ static void hsw_sseu_info_init(struct intel_gt *gt)
> sseu->eu_per_subslice);
>
> for (s = 0; s < sseu->max_slices; s++) {
> - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> - subslice_mask);
> + sseu->subslice_mask.hsw[s] = subslice_mask;
>
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> sseu_set_eus(sseu, s, ss,
> @@ -677,7 +696,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
> */
> if (GRAPHICS_VER(i915) == 11 &&
> slices == 1 &&
> - subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
> + subslices > min_t(u8, 4, hweight8(sseu->subslice_mask.hsw[0]) / 2)) {
> GEM_BUG_ON(subslices & 1);
>
> subslice_pg = false;
> @@ -743,14 +762,29 @@ void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
> {
> int s;
>
> - drm_printf(p, "slice total: %u, mask=%04x\n",
> - hweight8(sseu->slice_mask), sseu->slice_mask);
> - drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
> - for (s = 0; s < sseu->max_slices; s++) {
> - drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
> - s, intel_sseu_subslices_per_slice(sseu, s),
> - intel_sseu_get_subslices(sseu, s));
> + if (sseu->has_xehp_dss) {
> + drm_printf(p, "subslice total: %u\n",
> + intel_sseu_subslice_total(sseu));
> + drm_printf(p, "geometry dss mask=%*pb\n",
> + BITMAP_BITS(sseu->geometry_subslice_mask),
> + sseu->geometry_subslice_mask.xehp);
> + drm_printf(p, "compute dss mask=%*pb\n",
> + BITMAP_BITS(sseu->compute_subslice_mask),
> + sseu->compute_subslice_mask.xehp);
> + } else {
> + drm_printf(p, "slice total: %u, mask=%04x\n",
> + hweight8(sseu->slice_mask), sseu->slice_mask);
> + drm_printf(p, "subslice total: %u\n",
> + intel_sseu_subslice_total(sseu));
> +
> + for (s = 0; s < sseu->max_slices; s++) {
> + u8 ss_mask = sseu->subslice_mask.hsw[s];
> +
> + drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
> + s, hweight8(ss_mask), ss_mask);
> + }
> }
> +
> drm_printf(p, "EU total: %u\n", sseu->eu_total);
> drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
> drm_printf(p, "has slice power gating: %s\n",
> @@ -767,9 +801,10 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
> int s, ss;
>
> for (s = 0; s < sseu->max_slices; s++) {
> + u8 ss_mask = sseu->subslice_mask.hsw[s];
> +
> drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
> - s, intel_sseu_subslices_per_slice(sseu, s),
> - intel_sseu_get_subslices(sseu, s));
> + s, hweight8(ss_mask), ss_mask);
>
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> u16 enabled_eus = sseu_get_eus(sseu, s, ss);
> @@ -783,16 +818,14 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
> static void sseu_print_xehp_topology(const struct sseu_dev_info *sseu,
> struct drm_printer *p)
> {
> - u32 g_dss_mask = sseu_get_geometry_subslices(sseu);
> - u32 c_dss_mask = intel_sseu_get_compute_subslices(sseu);
> int dss;
>
> for (dss = 0; dss < sseu->max_subslices; dss++) {
> u16 enabled_eus = sseu_get_eus(sseu, 0, dss);
>
> drm_printf(p, "DSS_%02d: G:%3s C:%3s, %2u EUs (0x%04hx)\n", dss,
> - str_yes_no(g_dss_mask & BIT(dss)),
> - str_yes_no(c_dss_mask & BIT(dss)),
> + str_yes_no(test_bit(dss, sseu->geometry_subslice_mask.xehp)),
> + str_yes_no(test_bit(dss, sseu->compute_subslice_mask.xehp)),
> hweight16(enabled_eus), enabled_eus);
> }
> }
> @@ -810,20 +843,44 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
> }
> }
>
> -u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice)
> +void intel_sseu_print_ss_info(const char* type,
> + const struct sseu_dev_info *sseu,
> + struct seq_file *m)
> +{
> + int s;
> +
> + if (sseu->has_xehp_dss) {
> + seq_printf(m, " %s Geometry DSS: %u\n", type,
> + bitmap_weight(sseu->geometry_subslice_mask.xehp,
> + BITMAP_BITS(sseu->geometry_subslice_mask)));
> + seq_printf(m, " %s Compute DSS: %u\n", type,
> + bitmap_weight(sseu->compute_subslice_mask.xehp,
> + BITMAP_BITS(sseu->compute_subslice_mask)));
> + } else {
> + for (s = 0; s < fls(sseu->slice_mask); s++)
> + seq_printf(m, " %s Slice%i subslices: %u\n", type,
> + s, hweight8(sseu->subslice_mask.hsw[s]));
> + }
> +}
> +
> +u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask,
> + int dss_per_slice)
> {
> + intel_sseu_ss_mask_t per_slice_mask = {};
> u16 slice_mask = 0;
> int i;
>
> - WARN_ON(sizeof(dss_mask) * 8 / dss_per_slice > 8 * sizeof(slice_mask));
> + WARN_ON(DIV_ROUND_UP(BITMAP_BITS(dss_mask), dss_per_slice) >
> + 8 * sizeof(slice_mask));
>
> - for (i = 0; dss_mask; i++) {
> - if (dss_mask & GENMASK(dss_per_slice - 1, 0))
> + bitmap_fill(per_slice_mask.xehp, dss_per_slice);
> + for (i = 0; !bitmap_empty(dss_mask.xehp, BITMAP_BITS(dss_mask)); i++) {
> + if (bitmap_intersects(dss_mask.xehp, per_slice_mask.xehp, dss_per_slice))
> slice_mask |= BIT(i);
>
> - dss_mask >>= dss_per_slice;
> + bitmap_shift_right(dss_mask.xehp, dss_mask.xehp, dss_per_slice,
> + BITMAP_BITS(dss_mask));
> }
>
> return slice_mask;
> }
> -
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
> index ffa375e68959..0d3def55e770 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> @@ -25,12 +25,16 @@ struct drm_printer;
> /*
> * Maximum number of subslices that can exist within a HSW-style slice. This
> * is only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the
> - * GEN_MAX_DSS value below).
> + * I915_MAX_SS_FUSE_BITS value below).
> */
> #define GEN_MAX_SS_PER_HSW_SLICE 6
>
> -/* Maximum number of DSS on newer platforms (Xe_HP and beyond). */
> -#define GEN_MAX_DSS 32
> +/*
> + * Maximum number of 32-bit registers used by hardware to express the
> + * enabled/disabled subslices.
> + */
> +#define I915_MAX_SS_FUSE_REGS 1
> +#define I915_MAX_SS_FUSE_BITS (I915_MAX_SS_FUSE_REGS * 32)
>
> /* Maximum number of EUs that can exist within a subslice or DSS. */
> #define GEN_MAX_EUS_PER_SS 16
> @@ -38,7 +42,7 @@ struct drm_printer;
> #define SSEU_MAX(a, b) ((a) > (b) ? (a) : (b))
>
> /* The maximum number of bits needed to express each subslice/DSS independently */
> -#define GEN_SS_MASK_SIZE SSEU_MAX(GEN_MAX_DSS, \
> +#define GEN_SS_MASK_SIZE SSEU_MAX(I915_MAX_SS_FUSE_BITS, \
> GEN_MAX_HSW_SLICES * GEN_MAX_SS_PER_HSW_SLICE)
>
> #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
> @@ -49,17 +53,24 @@ struct drm_printer;
> #define GEN_DSS_PER_CSLICE 8
> #define GEN_DSS_PER_MSLICE 8
>
> -#define GEN_MAX_GSLICES (GEN_MAX_DSS / GEN_DSS_PER_GSLICE)
> -#define GEN_MAX_CSLICES (GEN_MAX_DSS / GEN_DSS_PER_CSLICE)
> +#define GEN_MAX_GSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_GSLICE)
> +#define GEN_MAX_CSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_CSLICE)
> +
> +typedef union {
> + u8 hsw[GEN_MAX_HSW_SLICES];
> +
> + /* Bitmap compatible with linux/bitmap.h; may exceed size of u64 */
> + unsigned long xehp[BITS_TO_LONGS(I915_MAX_SS_FUSE_BITS)];
> +} intel_sseu_ss_mask_t;
>
> struct sseu_dev_info {
> u8 slice_mask;
> - u8 subslice_mask[GEN_SS_MASK_SIZE];
> - u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
> - u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
> + intel_sseu_ss_mask_t subslice_mask;
> + intel_sseu_ss_mask_t geometry_subslice_mask;
> + intel_sseu_ss_mask_t compute_subslice_mask;
> union {
> u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
> - u16 xehp[GEN_MAX_DSS];
> + u16 xehp[I915_MAX_SS_FUSE_BITS];
> } eu_mask;
>
> u16 eu_total;
> @@ -80,8 +91,6 @@ struct sseu_dev_info {
> u8 max_slices;
> u8 max_subslices;
> u8 max_eus_per_subslice;
> -
> - u8 ss_stride;
> };
>
> /*
> @@ -99,7 +108,7 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
> {
> struct intel_sseu value = {
> .slice_mask = sseu->slice_mask,
> - .subslice_mask = sseu->subslice_mask[0],
> + .subslice_mask = sseu->subslice_mask.hsw[0],
> .min_eus_per_subslice = sseu->max_eus_per_subslice,
> .max_eus_per_subslice = sseu->max_eus_per_subslice,
> };
> @@ -111,18 +120,28 @@ static inline bool
> intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
> int subslice)
> {
> - u8 mask;
> - int ss_idx = subslice / BITS_PER_BYTE;
> -
> - if (slice >= sseu->max_slices ||
> - subslice >= sseu->max_subslices)
> + if (GEM_WARN_ON(slice >= sseu->max_slices))
> + return false;
> + if (GEM_WARN_ON(subslice >= sseu->max_subslices))
> return false;
>
> - GEM_BUG_ON(ss_idx >= sseu->ss_stride);
> -
> - mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx];
> + if (sseu->has_xehp_dss)
> + return test_bit(subslice, sseu->subslice_mask.xehp);
> + else
> + return sseu->subslice_mask.hsw[slice] & BIT(subslice);
> +}
>
> - return mask & BIT(subslice % BITS_PER_BYTE);
> +/*
> + * Used to obtain the index of the first DSS. Can start searching from the
> + * beginning of a specific dss group (e.g., gslice, cslice, etc.) if
> + * groupsize and groupnum are non-zero.
> + */
> +static inline unsigned int
> +intel_sseu_find_first_xehp_dss(const struct sseu_dev_info *sseu, int groupsize,
> + int groupnum)
> +{
> + return find_next_bit(sseu->subslice_mask.xehp, I915_MAX_SS_FUSE_BITS,
> + groupnum * groupsize);
> }
>
> void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
> @@ -132,14 +151,10 @@ unsigned int
> intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
>
> unsigned int
> -intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
> +intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice);
>
> -u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
> -
> -u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
> -
> -void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
> - u8 *subslice_mask, u32 ss_mask);
> +intel_sseu_ss_mask_t
> +intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
>
> void intel_sseu_info_init(struct intel_gt *gt);
>
> @@ -151,9 +166,15 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
> const struct sseu_dev_info *sseu,
> struct drm_printer *p);
>
> -u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
> +u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask, int dss_per_slice);
>
> int intel_sseu_copy_eumask_to_user(void __user *to,
> const struct sseu_dev_info *sseu);
> +int intel_sseu_copy_ssmask_to_user(void __user *to,
> + const struct sseu_dev_info *sseu);
> +
> +void intel_sseu_print_ss_info(const char* type,
> + const struct sseu_dev_info *sseu,
> + struct seq_file *m);
>
> #endif /* __INTEL_SSEU_H__ */
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> index 2d5d011e01db..c2ee5e1826b5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> @@ -4,6 +4,7 @@
> * Copyright © 2020 Intel Corporation
> */
>
> +#include <linux/bitmap.h>
> #include <linux/string_helpers.h>
>
> #include "i915_drv.h"
> @@ -11,14 +12,6 @@
> #include "intel_gt_regs.h"
> #include "intel_sseu_debugfs.h"
>
> -static void sseu_copy_subslices(const struct sseu_dev_info *sseu,
> - int slice, u8 *to_mask)
> -{
> - int offset = slice * sseu->ss_stride;
> -
> - memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
> -}
> -
> static void cherryview_sseu_device_status(struct intel_gt *gt,
> struct sseu_dev_info *sseu)
> {
> @@ -41,7 +34,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt,
> continue;
>
> sseu->slice_mask = BIT(0);
> - sseu->subslice_mask[0] |= BIT(ss);
> + sseu->subslice_mask.hsw[0] |= BIT(ss);
> eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
> ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
> ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
> @@ -92,7 +85,7 @@ static void gen11_sseu_device_status(struct intel_gt *gt,
> continue;
>
> sseu->slice_mask |= BIT(s);
> - sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
> + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
>
> for (ss = 0; ss < info->sseu.max_subslices; ss++) {
> unsigned int eu_cnt;
> @@ -147,21 +140,17 @@ static void gen9_sseu_device_status(struct intel_gt *gt,
> sseu->slice_mask |= BIT(s);
>
> if (IS_GEN9_BC(gt->i915))
> - sseu_copy_subslices(&info->sseu, s,
> - sseu->subslice_mask);
> + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
>
> for (ss = 0; ss < info->sseu.max_subslices; ss++) {
> unsigned int eu_cnt;
> - u8 ss_idx = s * info->sseu.ss_stride +
> - ss / BITS_PER_BYTE;
>
> if (IS_GEN9_LP(gt->i915)) {
> if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> /* skip disabled subslice */
> continue;
>
> - sseu->subslice_mask[ss_idx] |=
> - BIT(ss % BITS_PER_BYTE);
> + sseu->subslice_mask.hsw[s] |= BIT(ss);
> }
>
> eu_cnt = eu_reg[2 * s + ss / 2] & eu_mask[ss % 2];
> @@ -188,8 +177,7 @@ static void bdw_sseu_device_status(struct intel_gt *gt,
> if (sseu->slice_mask) {
> sseu->eu_per_subslice = info->sseu.eu_per_subslice;
> for (s = 0; s < fls(sseu->slice_mask); s++)
> - sseu_copy_subslices(&info->sseu, s,
> - sseu->subslice_mask);
> + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
> sseu->eu_total = sseu->eu_per_subslice *
> intel_sseu_subslice_total(sseu);
>
> @@ -208,7 +196,6 @@ static void i915_print_sseu_info(struct seq_file *m,
> const struct sseu_dev_info *sseu)
> {
> const char *type = is_available_info ? "Available" : "Enabled";
> - int s;
>
> seq_printf(m, " %s Slice Mask: %04x\n", type,
> sseu->slice_mask);
> @@ -216,10 +203,7 @@ static void i915_print_sseu_info(struct seq_file *m,
> hweight8(sseu->slice_mask));
> seq_printf(m, " %s Subslice Total: %u\n", type,
> intel_sseu_subslice_total(sseu));
> - for (s = 0; s < fls(sseu->slice_mask); s++) {
> - seq_printf(m, " %s Slice%i subslices: %u\n", type,
> - s, intel_sseu_subslices_per_slice(sseu, s));
> - }
> + intel_sseu_print_ss_info(type, sseu, m);
> seq_printf(m, " %s EU Total: %u\n", type,
> sseu->eu_total);
> seq_printf(m, " %s EU Per Subslice: %u\n", type,
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 73b59ea6fd3b..1bf62273e02d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -948,8 +948,8 @@ gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> * on s/ss combo, the read should be done with read_subslice_reg.
> */
> slice = ffs(sseu->slice_mask) - 1;
> - GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
> - subslice = ffs(intel_sseu_get_subslices(sseu, slice));
> + GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw));
> + subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice));
> GEM_BUG_ON(!subslice);
> subslice--;
>
> @@ -1087,11 +1087,10 @@ static void
> icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> const struct sseu_dev_info *sseu = >->info.sseu;
> - unsigned int slice, subslice;
> + unsigned int subslice;
>
> GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
> GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
> - slice = 0;
>
> /*
> * Although a platform may have subslices, we need to always steer
> @@ -1102,7 +1101,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> * one of the higher subslices, we run the risk of reading back 0's or
> * random garbage.
> */
> - subslice = __ffs(intel_sseu_get_subslices(sseu, slice));
> + subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0));
>
> /*
> * If the subslice we picked above also steers us to a valid L3 bank,
> @@ -1112,7 +1111,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> if (gt->info.l3bank_mask & BIT(subslice))
> gt->steering_table[L3BANK] = NULL;
>
> - __add_mcr_wa(gt, wal, slice, subslice);
> + __add_mcr_wa(gt, wal, 0, subslice);
> }
>
> static void
> @@ -1120,7 +1119,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> const struct sseu_dev_info *sseu = >->info.sseu;
> unsigned long slice, subslice = 0, slice_mask = 0;
> - u64 dss_mask = 0;
> u32 lncf_mask = 0;
> int i;
>
> @@ -1151,8 +1149,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> */
>
> /* Find the potential gslice candidates */
> - dss_mask = intel_sseu_get_subslices(sseu, 0);
> - slice_mask = intel_slicemask_from_dssmask(dss_mask, GEN_DSS_PER_GSLICE);
> + slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask,
> + GEN_DSS_PER_GSLICE);
>
> /*
> * Find the potential LNCF candidates. Either LNCF within a valid
> @@ -1177,9 +1175,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> }
>
> slice = __ffs(slice_mask);
> - subslice = __ffs(dss_mask >> (slice * GEN_DSS_PER_GSLICE));
> + subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice);
> WARN_ON(subslice > GEN_DSS_PER_GSLICE);
> - WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0);
>
> __add_mcr_wa(gt, wal, slice, subslice);
>
> @@ -2030,9 +2027,8 @@ engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>
> static bool needs_wa_1308578152(struct intel_engine_cs *engine)
> {
> - u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0);
> -
> - return (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0;
> + return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >
> + GEN_DSS_PER_GSLICE;
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
> index ac9767c56619..6fd15b39570c 100644
> --- a/drivers/gpu/drm/i915/i915_getparam.c
> +++ b/drivers/gpu/drm/i915/i915_getparam.c
> @@ -162,8 +162,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
> return -EINVAL;
>
> /* Only copy bits from the first slice */
> - memcpy(&value, sseu->subslice_mask,
> - min(sseu->ss_stride, (u8)sizeof(value)));
> + value = intel_sseu_get_hsw_subslices(sseu, 0);
> if (!value)
> return -ENODEV;
> break;
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 89c475d525b8..0094f67c63f2 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -31,10 +31,11 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
>
> static int fill_topology_info(const struct sseu_dev_info *sseu,
> struct drm_i915_query_item *query_item,
> - const u8 *subslice_mask)
> + intel_sseu_ss_mask_t subslice_mask)
> {
> struct drm_i915_query_topology_info topo;
> u32 slice_length, subslice_length, eu_length, total_length;
> + int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
> int eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
> int ret;
>
> @@ -44,7 +45,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
> return -ENODEV;
>
> slice_length = sizeof(sseu->slice_mask);
> - subslice_length = sseu->max_slices * sseu->ss_stride;
> + subslice_length = sseu->max_slices * ss_stride;
> eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
> total_length = sizeof(topo) + slice_length + subslice_length +
> eu_length;
> @@ -60,7 +61,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
> topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
>
> topo.subslice_offset = slice_length;
> - topo.subslice_stride = sseu->ss_stride;
> + topo.subslice_stride = ss_stride;
> topo.eu_offset = slice_length + subslice_length;
> topo.eu_stride = eu_stride;
>
> @@ -72,9 +73,9 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
> &sseu->slice_mask, slice_length))
> return -EFAULT;
>
> - if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
> - sizeof(topo) + slice_length),
> - subslice_mask, subslice_length))
> + if (intel_sseu_copy_ssmask_to_user(u64_to_user_ptr(query_item->data_ptr +
> + sizeof(topo) + slice_length),
> + sseu))
> return -EFAULT;
>
> if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v5 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
@ 2022-05-23 20:45 ` Matt Roper
-1 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-05-23 20:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Tvrtko Ursulin, dri-devel
As with EU masks, it's easier to store subslice/DSS masks internally in
a format that's more natural for the driver to work with, and then only
covert into the u8[] uapi form when the query ioctl is invoked. Since
the hardware design changed significantly with Xe_HP, we'll use a union
to choose between the old "hsw-style" subslice masks or the newer xehp
mask. HSW-style masks will be stored in an array of u8's, indexed by
slice (there's never more than 6 subslices per slice on older
platforms). For Xe_HP and beyond where slices no longer exist, we only
need a single bitmask. However we already know that this mask is
eventually going to grow too large for a simple u64 to hold, so we'll
represent it in a manner that can be operated on by the utilities in
linux/bitmap.h.
v2:
- Fix typo: BIT(s) -> BIT(ss) in gen9_sseu_device_status()
v3:
- Eliminate sseu->ss_stride and just calculate the stride while
specifically handling uapi. (Tvrtko)
- Use BITMAP_BITS() macro to refer to size of masks rather than
passing I915_MAX_SS_FUSE_BITS directly. (Tvrtko)
- Report compute/geometry DSS masks separately when dumping Xe_HP SSEU
info. (Tvrtko)
- Restore dropped range checks to intel_sseu_has_subslice(). (Tvrtko)
v4:
- Make the bitmap size macro check the size of the .xehp field rather
than the containing union. (Tvrtko)
- Don't add GEM_BUG_ON() intel_sseu_has_subslice()'s check for whether
slice or subslice ID exceed sseu->max_[sub]slices; various loops
in the driver are expected to exceed these, so we should just
silently return 'false.'
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 12 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 261 +++++++++++--------
drivers/gpu/drm/i915/gt/intel_sseu.h | 76 ++++--
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +--
drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +-
drivers/gpu/drm/i915/i915_getparam.c | 3 +-
drivers/gpu/drm/i915/i915_query.c | 13 +-
9 files changed, 241 insertions(+), 187 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index ab4c5ab28e4d..a3bb73f5d53b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1875,6 +1875,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
{
const struct sseu_dev_info *device = >->info.sseu;
struct drm_i915_private *i915 = gt->i915;
+ unsigned int dev_subslice_mask = intel_sseu_get_hsw_subslices(device, 0);
/* No zeros in any field. */
if (!user->slice_mask || !user->subslice_mask ||
@@ -1901,7 +1902,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
if (user->slice_mask & ~device->slice_mask)
return -EINVAL;
- if (user->subslice_mask & ~device->subslice_mask[0])
+ if (user->subslice_mask & ~dev_subslice_mask)
return -EINVAL;
if (user->max_eus_per_subslice > device->max_eus_per_subslice)
@@ -1915,7 +1916,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
/* Part specific restrictions. */
if (GRAPHICS_VER(i915) == 11) {
unsigned int hw_s = hweight8(device->slice_mask);
- unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
+ unsigned int hw_ss_per_s = hweight8(dev_subslice_mask);
unsigned int req_s = hweight8(context->slice_mask);
unsigned int req_ss = hweight8(context->subslice_mask);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 1adbf34c3632..f0acf8518a51 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -674,8 +674,8 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
return;
- ccs_mask = intel_slicemask_from_dssmask(intel_sseu_get_compute_subslices(&info->sseu),
- ss_per_ccs);
+ ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
+ ss_per_ccs);
/*
* If all DSS in a quadrant are fused off, the corresponding CCS
* engine is not available for use.
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 034182f85501..2921f510642f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -133,13 +133,6 @@ static const struct intel_mmio_range dg2_lncf_steering_table[] = {
{},
};
-static u16 slicemask(struct intel_gt *gt, int count)
-{
- u64 dss_mask = intel_sseu_get_subslices(>->info.sseu, 0);
-
- return intel_slicemask_from_dssmask(dss_mask, count);
-}
-
int intel_gt_init_mmio(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
@@ -155,9 +148,12 @@ int intel_gt_init_mmio(struct intel_gt *gt)
*/
if (HAS_MSLICES(i915)) {
gt->info.mslice_mask =
- slicemask(gt, GEN_DSS_PER_MSLICE) |
+ intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
+ GEN_DSS_PER_MSLICE);
+ gt->info.mslice_mask |=
(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
GEN12_MEML3_EN_MASK);
+
if (!gt->info.mslice_mask) /* should be impossible! */
drm_warn(&i915->drm, "mslice mask all zero!\n");
}
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 285cfd758bdc..3a721db20290 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -10,15 +10,14 @@
#include "intel_gt_regs.h"
#include "intel_sseu.h"
+#define XEHP_BITMAP_BITS(mask) ((int)BITS_PER_TYPE(typeof(mask.xehp)))
+
void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
u8 max_subslices, u8 max_eus_per_subslice)
{
sseu->max_slices = max_slices;
sseu->max_subslices = max_subslices;
sseu->max_eus_per_subslice = max_eus_per_subslice;
-
- sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
- GEM_BUG_ON(sseu->ss_stride > GEN_MAX_SUBSLICE_STRIDE);
}
unsigned int
@@ -26,54 +25,24 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
{
unsigned int i, total = 0;
- for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
- total += hweight8(sseu->subslice_mask[i]);
-
- return total;
-}
-
-static u32
-sseu_get_subslices(const struct sseu_dev_info *sseu,
- const u8 *subslice_mask, u8 slice)
-{
- int i, offset = slice * sseu->ss_stride;
- u32 mask = 0;
-
- GEM_BUG_ON(slice >= sseu->max_slices);
-
- for (i = 0; i < sseu->ss_stride; i++)
- mask |= (u32)subslice_mask[offset + i] << i * BITS_PER_BYTE;
-
- return mask;
-}
-
-u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
-{
- return sseu_get_subslices(sseu, sseu->subslice_mask, slice);
-}
+ if (sseu->has_xehp_dss)
+ return bitmap_weight(sseu->subslice_mask.xehp,
+ XEHP_BITMAP_BITS(sseu->subslice_mask));
-static u32 sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
-{
- return sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
-}
+ for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++)
+ total += hweight8(sseu->subslice_mask.hsw[i]);
-u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu)
-{
- return sseu_get_subslices(sseu, sseu->compute_subslice_mask, 0);
-}
-
-void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
- u8 *subslice_mask, u32 ss_mask)
-{
- int offset = slice * sseu->ss_stride;
-
- memcpy(&subslice_mask[offset], &ss_mask, sseu->ss_stride);
+ return total;
}
unsigned int
-intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
+intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice)
{
- return hweight32(intel_sseu_get_subslices(sseu, slice));
+ WARN_ON(sseu->has_xehp_dss);
+ if (WARN_ON(slice >= sseu->max_slices))
+ return 0;
+
+ return sseu->subslice_mask.hsw[slice];
}
static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
@@ -147,32 +116,66 @@ int intel_sseu_copy_eumask_to_user(void __user *to,
return copy_to_user(to, eu_mask, len);
}
+/**
+ * intel_sseu_copy_ssmask_to_user - Copy subslice mask into a userspace buffer
+ * @to: Pointer to userspace buffer to copy to
+ * @sseu: SSEU structure containing subslice mask to copy
+ *
+ * Copies the subslice mask to a userspace buffer in the format expected by
+ * the query ioctl's topology queries.
+ *
+ * Returns the result of the copy_to_user() operation.
+ */
+int intel_sseu_copy_ssmask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu)
+{
+ u8 ss_mask[GEN_SS_MASK_SIZE] = {};
+ int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
+ int len = sseu->max_slices * ss_stride;
+ int s, ss, i;
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ for (ss = 0; ss < sseu->max_subslices; ss++) {
+ i = s * ss_stride * BITS_PER_BYTE + ss;
+
+ if (!intel_sseu_has_subslice(sseu, s, ss))
+ continue;
+
+ ss_mask[i / BITS_PER_BYTE] |= BIT(i % BITS_PER_BYTE);
+ }
+ }
+
+ return copy_to_user(to, ss_mask, len);
+}
+
static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
- u32 g_ss_en, u32 c_ss_en, u16 eu_en)
+ u32 ss_en, u16 eu_en)
{
u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
int ss;
- /* g_ss_en/c_ss_en represent entire subslice mask across all slices */
- GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
- sizeof(g_ss_en) * BITS_PER_BYTE);
+ sseu->slice_mask |= BIT(0);
+ sseu->subslice_mask.hsw[0] = ss_en & valid_ss_mask;
+
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (intel_sseu_has_subslice(sseu, 0, ss))
+ sseu_set_eus(sseu, 0, ss, eu_en);
+
+ sseu->eu_per_subslice = hweight16(eu_en);
+ sseu->eu_total = compute_eu_total(sseu);
+}
+
+static void xehp_compute_sseu_info(struct sseu_dev_info *sseu,
+ u16 eu_en)
+{
+ int ss;
sseu->slice_mask |= BIT(0);
- /*
- * XeHP introduces the concept of compute vs geometry DSS. To reduce
- * variation between GENs around subslice usage, store a mask for both
- * the geometry and compute enabled masks since userspace will need to
- * be able to query these masks independently. Also compute a total
- * enabled subslice count for the purposes of selecting subslices to
- * use in a particular GEM context.
- */
- intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
- c_ss_en & valid_ss_mask);
- intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
- g_ss_en & valid_ss_mask);
- intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
- (g_ss_en | c_ss_en) & valid_ss_mask);
+ bitmap_or(sseu->subslice_mask.xehp,
+ sseu->compute_subslice_mask.xehp,
+ sseu->geometry_subslice_mask.xehp,
+ XEHP_BITMAP_BITS(sseu->subslice_mask));
for (ss = 0; ss < sseu->max_subslices; ss++)
if (intel_sseu_has_subslice(sseu, 0, ss))
@@ -182,11 +185,31 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
sseu->eu_total = compute_eu_total(sseu);
}
+static void
+xehp_load_dss_mask(struct intel_uncore *uncore,
+ intel_sseu_ss_mask_t *ssmask,
+ int numregs,
+ ...)
+{
+ va_list argp;
+ u32 fuse_val[I915_MAX_SS_FUSE_REGS] = {};
+ int i;
+
+ if (WARN_ON(numregs > I915_MAX_SS_FUSE_REGS))
+ numregs = I915_MAX_SS_FUSE_REGS;
+
+ va_start(argp, numregs);
+ for (i = 0; i < numregs; i++)
+ fuse_val[i] = intel_uncore_read(uncore, va_arg(argp, i915_reg_t));
+ va_end(argp);
+
+ bitmap_from_arr32(ssmask->xehp, fuse_val, numregs * 32);
+}
+
static void xehp_sseu_info_init(struct intel_gt *gt)
{
struct sseu_dev_info *sseu = >->info.sseu;
struct intel_uncore *uncore = gt->uncore;
- u32 g_dss_en, c_dss_en = 0;
u16 eu_en = 0;
u8 eu_en_fuse;
int eu;
@@ -200,8 +223,10 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
intel_sseu_set_info(sseu, 1, 32, 16);
sseu->has_xehp_dss = 1;
- g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
- c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
+ xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 1,
+ GEN12_GT_GEOMETRY_DSS_ENABLE);
+ xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 1,
+ GEN12_GT_COMPUTE_DSS_ENABLE);
eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
@@ -209,7 +234,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
+ xehp_compute_sseu_info(sseu, eu_en);
}
static void gen12_sseu_info_init(struct intel_gt *gt)
@@ -247,7 +272,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, g_dss_en, eu_en);
/* TGL only supports slice-level power gating */
sseu->has_slice_pg = 1;
@@ -279,7 +304,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
GEN11_EU_DIS_MASK);
- gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, ss_en, eu_en);
/* ICL has no power gating restrictions. */
sseu->has_slice_pg = 1;
@@ -291,7 +316,6 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
{
struct sseu_dev_info *sseu = >->info.sseu;
u32 fuse;
- u8 subslice_mask = 0;
fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT);
@@ -305,7 +329,7 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
- subslice_mask |= BIT(0);
+ sseu->subslice_mask.hsw[0] |= BIT(0);
sseu_set_eus(sseu, 0, 0, ~disabled_mask & 0xFF);
}
@@ -316,12 +340,10 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
(((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
- subslice_mask |= BIT(1);
+ sseu->subslice_mask.hsw[0] |= BIT(1);
sseu_set_eus(sseu, 0, 1, ~disabled_mask & 0xFF);
}
- intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask, subslice_mask);
-
sseu->eu_total = compute_eu_total(sseu);
/*
@@ -376,8 +398,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
/* skip disabled slice */
continue;
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
for (ss = 0; ss < sseu->max_subslices; ss++) {
@@ -434,8 +455,8 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
sseu->has_eu_pg = sseu->eu_per_subslice > 2;
if (IS_GEN9_LP(i915)) {
-#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
- info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
+#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask.hsw[0] & BIT(ss)))
+ info->has_pooled_eu = hweight8(sseu->subslice_mask.hsw[0]) == 3;
sseu->min_eu_in_pool = 0;
if (info->has_pooled_eu) {
@@ -489,8 +510,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
/* skip disabled slice */
continue;
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
for (ss = 0; ss < sseu->max_subslices; ss++) {
u8 eu_disabled_mask;
@@ -587,8 +607,7 @@ static void hsw_sseu_info_init(struct intel_gt *gt)
sseu->eu_per_subslice);
for (s = 0; s < sseu->max_slices; s++) {
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
for (ss = 0; ss < sseu->max_subslices; ss++) {
sseu_set_eus(sseu, s, ss,
@@ -677,7 +696,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
*/
if (GRAPHICS_VER(i915) == 11 &&
slices == 1 &&
- subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
+ subslices > min_t(u8, 4, hweight8(sseu->subslice_mask.hsw[0]) / 2)) {
GEM_BUG_ON(subslices & 1);
subslice_pg = false;
@@ -743,14 +762,29 @@ void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
{
int s;
- drm_printf(p, "slice total: %u, mask=%04x\n",
- hweight8(sseu->slice_mask), sseu->slice_mask);
- drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
- for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
- s, intel_sseu_subslices_per_slice(sseu, s),
- intel_sseu_get_subslices(sseu, s));
+ if (sseu->has_xehp_dss) {
+ drm_printf(p, "subslice total: %u\n",
+ intel_sseu_subslice_total(sseu));
+ drm_printf(p, "geometry dss mask=%*pb\n",
+ XEHP_BITMAP_BITS(sseu->geometry_subslice_mask),
+ sseu->geometry_subslice_mask.xehp);
+ drm_printf(p, "compute dss mask=%*pb\n",
+ XEHP_BITMAP_BITS(sseu->compute_subslice_mask),
+ sseu->compute_subslice_mask.xehp);
+ } else {
+ drm_printf(p, "slice total: %u, mask=%04x\n",
+ hweight8(sseu->slice_mask), sseu->slice_mask);
+ drm_printf(p, "subslice total: %u\n",
+ intel_sseu_subslice_total(sseu));
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ u8 ss_mask = sseu->subslice_mask.hsw[s];
+
+ drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
+ s, hweight8(ss_mask), ss_mask);
+ }
}
+
drm_printf(p, "EU total: %u\n", sseu->eu_total);
drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
drm_printf(p, "has slice power gating: %s\n",
@@ -767,9 +801,10 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
int s, ss;
for (s = 0; s < sseu->max_slices; s++) {
+ u8 ss_mask = sseu->subslice_mask.hsw[s];
+
drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
- s, intel_sseu_subslices_per_slice(sseu, s),
- intel_sseu_get_subslices(sseu, s));
+ s, hweight8(ss_mask), ss_mask);
for (ss = 0; ss < sseu->max_subslices; ss++) {
u16 enabled_eus = sseu_get_eus(sseu, s, ss);
@@ -783,16 +818,14 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
static void sseu_print_xehp_topology(const struct sseu_dev_info *sseu,
struct drm_printer *p)
{
- u32 g_dss_mask = sseu_get_geometry_subslices(sseu);
- u32 c_dss_mask = intel_sseu_get_compute_subslices(sseu);
int dss;
for (dss = 0; dss < sseu->max_subslices; dss++) {
u16 enabled_eus = sseu_get_eus(sseu, 0, dss);
drm_printf(p, "DSS_%02d: G:%3s C:%3s, %2u EUs (0x%04hx)\n", dss,
- str_yes_no(g_dss_mask & BIT(dss)),
- str_yes_no(c_dss_mask & BIT(dss)),
+ str_yes_no(test_bit(dss, sseu->geometry_subslice_mask.xehp)),
+ str_yes_no(test_bit(dss, sseu->compute_subslice_mask.xehp)),
hweight16(enabled_eus), enabled_eus);
}
}
@@ -810,20 +843,44 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
}
}
-u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice)
+void intel_sseu_print_ss_info(const char* type,
+ const struct sseu_dev_info *sseu,
+ struct seq_file *m)
+{
+ int s;
+
+ if (sseu->has_xehp_dss) {
+ seq_printf(m, " %s Geometry DSS: %u\n", type,
+ bitmap_weight(sseu->geometry_subslice_mask.xehp,
+ XEHP_BITMAP_BITS(sseu->geometry_subslice_mask)));
+ seq_printf(m, " %s Compute DSS: %u\n", type,
+ bitmap_weight(sseu->compute_subslice_mask.xehp,
+ XEHP_BITMAP_BITS(sseu->compute_subslice_mask)));
+ } else {
+ for (s = 0; s < fls(sseu->slice_mask); s++)
+ seq_printf(m, " %s Slice%i subslices: %u\n", type,
+ s, hweight8(sseu->subslice_mask.hsw[s]));
+ }
+}
+
+u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask,
+ int dss_per_slice)
{
+ intel_sseu_ss_mask_t per_slice_mask = {};
u16 slice_mask = 0;
int i;
- WARN_ON(sizeof(dss_mask) * 8 / dss_per_slice > 8 * sizeof(slice_mask));
+ WARN_ON(DIV_ROUND_UP(XEHP_BITMAP_BITS(dss_mask), dss_per_slice) >
+ 8 * sizeof(slice_mask));
- for (i = 0; dss_mask; i++) {
- if (dss_mask & GENMASK(dss_per_slice - 1, 0))
+ bitmap_fill(per_slice_mask.xehp, dss_per_slice);
+ for (i = 0; !bitmap_empty(dss_mask.xehp, XEHP_BITMAP_BITS(dss_mask)); i++) {
+ if (bitmap_intersects(dss_mask.xehp, per_slice_mask.xehp, dss_per_slice))
slice_mask |= BIT(i);
- dss_mask >>= dss_per_slice;
+ bitmap_shift_right(dss_mask.xehp, dss_mask.xehp, dss_per_slice,
+ XEHP_BITMAP_BITS(dss_mask));
}
return slice_mask;
}
-
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index ffa375e68959..e7f336a7ffbb 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -25,12 +25,16 @@ struct drm_printer;
/*
* Maximum number of subslices that can exist within a HSW-style slice. This
* is only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the
- * GEN_MAX_DSS value below).
+ * I915_MAX_SS_FUSE_BITS value below).
*/
#define GEN_MAX_SS_PER_HSW_SLICE 6
-/* Maximum number of DSS on newer platforms (Xe_HP and beyond). */
-#define GEN_MAX_DSS 32
+/*
+ * Maximum number of 32-bit registers used by hardware to express the
+ * enabled/disabled subslices.
+ */
+#define I915_MAX_SS_FUSE_REGS 1
+#define I915_MAX_SS_FUSE_BITS (I915_MAX_SS_FUSE_REGS * 32)
/* Maximum number of EUs that can exist within a subslice or DSS. */
#define GEN_MAX_EUS_PER_SS 16
@@ -38,7 +42,7 @@ struct drm_printer;
#define SSEU_MAX(a, b) ((a) > (b) ? (a) : (b))
/* The maximum number of bits needed to express each subslice/DSS independently */
-#define GEN_SS_MASK_SIZE SSEU_MAX(GEN_MAX_DSS, \
+#define GEN_SS_MASK_SIZE SSEU_MAX(I915_MAX_SS_FUSE_BITS, \
GEN_MAX_HSW_SLICES * GEN_MAX_SS_PER_HSW_SLICE)
#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
@@ -49,17 +53,24 @@ struct drm_printer;
#define GEN_DSS_PER_CSLICE 8
#define GEN_DSS_PER_MSLICE 8
-#define GEN_MAX_GSLICES (GEN_MAX_DSS / GEN_DSS_PER_GSLICE)
-#define GEN_MAX_CSLICES (GEN_MAX_DSS / GEN_DSS_PER_CSLICE)
+#define GEN_MAX_GSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_GSLICE)
+#define GEN_MAX_CSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_CSLICE)
+
+typedef union {
+ u8 hsw[GEN_MAX_HSW_SLICES];
+
+ /* Bitmap compatible with linux/bitmap.h; may exceed size of u64 */
+ unsigned long xehp[BITS_TO_LONGS(I915_MAX_SS_FUSE_BITS)];
+} intel_sseu_ss_mask_t;
struct sseu_dev_info {
u8 slice_mask;
- u8 subslice_mask[GEN_SS_MASK_SIZE];
- u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
- u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
+ intel_sseu_ss_mask_t subslice_mask;
+ intel_sseu_ss_mask_t geometry_subslice_mask;
+ intel_sseu_ss_mask_t compute_subslice_mask;
union {
u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
- u16 xehp[GEN_MAX_DSS];
+ u16 xehp[I915_MAX_SS_FUSE_BITS];
} eu_mask;
u16 eu_total;
@@ -80,8 +91,6 @@ struct sseu_dev_info {
u8 max_slices;
u8 max_subslices;
u8 max_eus_per_subslice;
-
- u8 ss_stride;
};
/*
@@ -99,7 +108,7 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
{
struct intel_sseu value = {
.slice_mask = sseu->slice_mask,
- .subslice_mask = sseu->subslice_mask[0],
+ .subslice_mask = sseu->subslice_mask.hsw[0],
.min_eus_per_subslice = sseu->max_eus_per_subslice,
.max_eus_per_subslice = sseu->max_eus_per_subslice,
};
@@ -111,18 +120,27 @@ static inline bool
intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
int subslice)
{
- u8 mask;
- int ss_idx = subslice / BITS_PER_BYTE;
-
if (slice >= sseu->max_slices ||
subslice >= sseu->max_subslices)
return false;
- GEM_BUG_ON(ss_idx >= sseu->ss_stride);
-
- mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx];
+ if (sseu->has_xehp_dss)
+ return test_bit(subslice, sseu->subslice_mask.xehp);
+ else
+ return sseu->subslice_mask.hsw[slice] & BIT(subslice);
+}
- return mask & BIT(subslice % BITS_PER_BYTE);
+/*
+ * Used to obtain the index of the first DSS. Can start searching from the
+ * beginning of a specific dss group (e.g., gslice, cslice, etc.) if
+ * groupsize and groupnum are non-zero.
+ */
+static inline unsigned int
+intel_sseu_find_first_xehp_dss(const struct sseu_dev_info *sseu, int groupsize,
+ int groupnum)
+{
+ return find_next_bit(sseu->subslice_mask.xehp, I915_MAX_SS_FUSE_BITS,
+ groupnum * groupsize);
}
void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
@@ -132,14 +150,10 @@ unsigned int
intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
unsigned int
-intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
-
-u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
+intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice);
-u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
-
-void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
- u8 *subslice_mask, u32 ss_mask);
+intel_sseu_ss_mask_t
+intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
void intel_sseu_info_init(struct intel_gt *gt);
@@ -151,9 +165,15 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
const struct sseu_dev_info *sseu,
struct drm_printer *p);
-u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
+u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask, int dss_per_slice);
int intel_sseu_copy_eumask_to_user(void __user *to,
const struct sseu_dev_info *sseu);
+int intel_sseu_copy_ssmask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu);
+
+void intel_sseu_print_ss_info(const char* type,
+ const struct sseu_dev_info *sseu,
+ struct seq_file *m);
#endif /* __INTEL_SSEU_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
index 2d5d011e01db..c2ee5e1826b5 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
@@ -4,6 +4,7 @@
* Copyright © 2020 Intel Corporation
*/
+#include <linux/bitmap.h>
#include <linux/string_helpers.h>
#include "i915_drv.h"
@@ -11,14 +12,6 @@
#include "intel_gt_regs.h"
#include "intel_sseu_debugfs.h"
-static void sseu_copy_subslices(const struct sseu_dev_info *sseu,
- int slice, u8 *to_mask)
-{
- int offset = slice * sseu->ss_stride;
-
- memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
-}
-
static void cherryview_sseu_device_status(struct intel_gt *gt,
struct sseu_dev_info *sseu)
{
@@ -41,7 +34,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt,
continue;
sseu->slice_mask = BIT(0);
- sseu->subslice_mask[0] |= BIT(ss);
+ sseu->subslice_mask.hsw[0] |= BIT(ss);
eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
@@ -92,7 +85,7 @@ static void gen11_sseu_device_status(struct intel_gt *gt,
continue;
sseu->slice_mask |= BIT(s);
- sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -147,21 +140,17 @@ static void gen9_sseu_device_status(struct intel_gt *gt,
sseu->slice_mask |= BIT(s);
if (IS_GEN9_BC(gt->i915))
- sseu_copy_subslices(&info->sseu, s,
- sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
- u8 ss_idx = s * info->sseu.ss_stride +
- ss / BITS_PER_BYTE;
if (IS_GEN9_LP(gt->i915)) {
if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
/* skip disabled subslice */
continue;
- sseu->subslice_mask[ss_idx] |=
- BIT(ss % BITS_PER_BYTE);
+ sseu->subslice_mask.hsw[s] |= BIT(ss);
}
eu_cnt = eu_reg[2 * s + ss / 2] & eu_mask[ss % 2];
@@ -188,8 +177,7 @@ static void bdw_sseu_device_status(struct intel_gt *gt,
if (sseu->slice_mask) {
sseu->eu_per_subslice = info->sseu.eu_per_subslice;
for (s = 0; s < fls(sseu->slice_mask); s++)
- sseu_copy_subslices(&info->sseu, s,
- sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
sseu->eu_total = sseu->eu_per_subslice *
intel_sseu_subslice_total(sseu);
@@ -208,7 +196,6 @@ static void i915_print_sseu_info(struct seq_file *m,
const struct sseu_dev_info *sseu)
{
const char *type = is_available_info ? "Available" : "Enabled";
- int s;
seq_printf(m, " %s Slice Mask: %04x\n", type,
sseu->slice_mask);
@@ -216,10 +203,7 @@ static void i915_print_sseu_info(struct seq_file *m,
hweight8(sseu->slice_mask));
seq_printf(m, " %s Subslice Total: %u\n", type,
intel_sseu_subslice_total(sseu));
- for (s = 0; s < fls(sseu->slice_mask); s++) {
- seq_printf(m, " %s Slice%i subslices: %u\n", type,
- s, intel_sseu_subslices_per_slice(sseu, s));
- }
+ intel_sseu_print_ss_info(type, sseu, m);
seq_printf(m, " %s EU Total: %u\n", type,
sseu->eu_total);
seq_printf(m, " %s EU Per Subslice: %u\n", type,
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 73b59ea6fd3b..1bf62273e02d 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -948,8 +948,8 @@ gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
* on s/ss combo, the read should be done with read_subslice_reg.
*/
slice = ffs(sseu->slice_mask) - 1;
- GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
- subslice = ffs(intel_sseu_get_subslices(sseu, slice));
+ GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw));
+ subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice));
GEM_BUG_ON(!subslice);
subslice--;
@@ -1087,11 +1087,10 @@ static void
icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
{
const struct sseu_dev_info *sseu = >->info.sseu;
- unsigned int slice, subslice;
+ unsigned int subslice;
GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
- slice = 0;
/*
* Although a platform may have subslices, we need to always steer
@@ -1102,7 +1101,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
* one of the higher subslices, we run the risk of reading back 0's or
* random garbage.
*/
- subslice = __ffs(intel_sseu_get_subslices(sseu, slice));
+ subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0));
/*
* If the subslice we picked above also steers us to a valid L3 bank,
@@ -1112,7 +1111,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
if (gt->info.l3bank_mask & BIT(subslice))
gt->steering_table[L3BANK] = NULL;
- __add_mcr_wa(gt, wal, slice, subslice);
+ __add_mcr_wa(gt, wal, 0, subslice);
}
static void
@@ -1120,7 +1119,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
{
const struct sseu_dev_info *sseu = >->info.sseu;
unsigned long slice, subslice = 0, slice_mask = 0;
- u64 dss_mask = 0;
u32 lncf_mask = 0;
int i;
@@ -1151,8 +1149,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
*/
/* Find the potential gslice candidates */
- dss_mask = intel_sseu_get_subslices(sseu, 0);
- slice_mask = intel_slicemask_from_dssmask(dss_mask, GEN_DSS_PER_GSLICE);
+ slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask,
+ GEN_DSS_PER_GSLICE);
/*
* Find the potential LNCF candidates. Either LNCF within a valid
@@ -1177,9 +1175,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
}
slice = __ffs(slice_mask);
- subslice = __ffs(dss_mask >> (slice * GEN_DSS_PER_GSLICE));
+ subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice);
WARN_ON(subslice > GEN_DSS_PER_GSLICE);
- WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0);
__add_mcr_wa(gt, wal, slice, subslice);
@@ -2030,9 +2027,8 @@ engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
static bool needs_wa_1308578152(struct intel_engine_cs *engine)
{
- u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0);
-
- return (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0;
+ return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >
+ GEN_DSS_PER_GSLICE;
}
static void
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index ac9767c56619..6fd15b39570c 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -162,8 +162,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
return -EINVAL;
/* Only copy bits from the first slice */
- memcpy(&value, sseu->subslice_mask,
- min(sseu->ss_stride, (u8)sizeof(value)));
+ value = intel_sseu_get_hsw_subslices(sseu, 0);
if (!value)
return -ENODEV;
break;
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 89c475d525b8..0094f67c63f2 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -31,10 +31,11 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
static int fill_topology_info(const struct sseu_dev_info *sseu,
struct drm_i915_query_item *query_item,
- const u8 *subslice_mask)
+ intel_sseu_ss_mask_t subslice_mask)
{
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
+ int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
int eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
@@ -44,7 +45,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
return -ENODEV;
slice_length = sizeof(sseu->slice_mask);
- subslice_length = sseu->max_slices * sseu->ss_stride;
+ subslice_length = sseu->max_slices * ss_stride;
eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
total_length = sizeof(topo) + slice_length + subslice_length +
eu_length;
@@ -60,7 +61,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
topo.subslice_offset = slice_length;
- topo.subslice_stride = sseu->ss_stride;
+ topo.subslice_stride = ss_stride;
topo.eu_offset = slice_length + subslice_length;
topo.eu_stride = eu_stride;
@@ -72,9 +73,9 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
&sseu->slice_mask, slice_length))
return -EFAULT;
- if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
- sizeof(topo) + slice_length),
- subslice_mask, subslice_length))
+ if (intel_sseu_copy_ssmask_to_user(u64_to_user_ptr(query_item->data_ptr +
+ sizeof(topo) + slice_length),
+ sseu))
return -EFAULT;
if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
--
2.35.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH v5 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi
@ 2022-05-23 20:45 ` Matt Roper
0 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-05-23 20:45 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
As with EU masks, it's easier to store subslice/DSS masks internally in
a format that's more natural for the driver to work with, and then only
covert into the u8[] uapi form when the query ioctl is invoked. Since
the hardware design changed significantly with Xe_HP, we'll use a union
to choose between the old "hsw-style" subslice masks or the newer xehp
mask. HSW-style masks will be stored in an array of u8's, indexed by
slice (there's never more than 6 subslices per slice on older
platforms). For Xe_HP and beyond where slices no longer exist, we only
need a single bitmask. However we already know that this mask is
eventually going to grow too large for a simple u64 to hold, so we'll
represent it in a manner that can be operated on by the utilities in
linux/bitmap.h.
v2:
- Fix typo: BIT(s) -> BIT(ss) in gen9_sseu_device_status()
v3:
- Eliminate sseu->ss_stride and just calculate the stride while
specifically handling uapi. (Tvrtko)
- Use BITMAP_BITS() macro to refer to size of masks rather than
passing I915_MAX_SS_FUSE_BITS directly. (Tvrtko)
- Report compute/geometry DSS masks separately when dumping Xe_HP SSEU
info. (Tvrtko)
- Restore dropped range checks to intel_sseu_has_subslice(). (Tvrtko)
v4:
- Make the bitmap size macro check the size of the .xehp field rather
than the containing union. (Tvrtko)
- Don't add GEM_BUG_ON() intel_sseu_has_subslice()'s check for whether
slice or subslice ID exceed sseu->max_[sub]slices; various loops
in the driver are expected to exceed these, so we should just
silently return 'false.'
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 12 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 261 +++++++++++--------
drivers/gpu/drm/i915/gt/intel_sseu.h | 76 ++++--
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +--
drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +-
drivers/gpu/drm/i915/i915_getparam.c | 3 +-
drivers/gpu/drm/i915/i915_query.c | 13 +-
9 files changed, 241 insertions(+), 187 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index ab4c5ab28e4d..a3bb73f5d53b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1875,6 +1875,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
{
const struct sseu_dev_info *device = >->info.sseu;
struct drm_i915_private *i915 = gt->i915;
+ unsigned int dev_subslice_mask = intel_sseu_get_hsw_subslices(device, 0);
/* No zeros in any field. */
if (!user->slice_mask || !user->subslice_mask ||
@@ -1901,7 +1902,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
if (user->slice_mask & ~device->slice_mask)
return -EINVAL;
- if (user->subslice_mask & ~device->subslice_mask[0])
+ if (user->subslice_mask & ~dev_subslice_mask)
return -EINVAL;
if (user->max_eus_per_subslice > device->max_eus_per_subslice)
@@ -1915,7 +1916,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
/* Part specific restrictions. */
if (GRAPHICS_VER(i915) == 11) {
unsigned int hw_s = hweight8(device->slice_mask);
- unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
+ unsigned int hw_ss_per_s = hweight8(dev_subslice_mask);
unsigned int req_s = hweight8(context->slice_mask);
unsigned int req_ss = hweight8(context->subslice_mask);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 1adbf34c3632..f0acf8518a51 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -674,8 +674,8 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
return;
- ccs_mask = intel_slicemask_from_dssmask(intel_sseu_get_compute_subslices(&info->sseu),
- ss_per_ccs);
+ ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
+ ss_per_ccs);
/*
* If all DSS in a quadrant are fused off, the corresponding CCS
* engine is not available for use.
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 034182f85501..2921f510642f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -133,13 +133,6 @@ static const struct intel_mmio_range dg2_lncf_steering_table[] = {
{},
};
-static u16 slicemask(struct intel_gt *gt, int count)
-{
- u64 dss_mask = intel_sseu_get_subslices(>->info.sseu, 0);
-
- return intel_slicemask_from_dssmask(dss_mask, count);
-}
-
int intel_gt_init_mmio(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
@@ -155,9 +148,12 @@ int intel_gt_init_mmio(struct intel_gt *gt)
*/
if (HAS_MSLICES(i915)) {
gt->info.mslice_mask =
- slicemask(gt, GEN_DSS_PER_MSLICE) |
+ intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
+ GEN_DSS_PER_MSLICE);
+ gt->info.mslice_mask |=
(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
GEN12_MEML3_EN_MASK);
+
if (!gt->info.mslice_mask) /* should be impossible! */
drm_warn(&i915->drm, "mslice mask all zero!\n");
}
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 285cfd758bdc..3a721db20290 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -10,15 +10,14 @@
#include "intel_gt_regs.h"
#include "intel_sseu.h"
+#define XEHP_BITMAP_BITS(mask) ((int)BITS_PER_TYPE(typeof(mask.xehp)))
+
void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
u8 max_subslices, u8 max_eus_per_subslice)
{
sseu->max_slices = max_slices;
sseu->max_subslices = max_subslices;
sseu->max_eus_per_subslice = max_eus_per_subslice;
-
- sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
- GEM_BUG_ON(sseu->ss_stride > GEN_MAX_SUBSLICE_STRIDE);
}
unsigned int
@@ -26,54 +25,24 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
{
unsigned int i, total = 0;
- for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
- total += hweight8(sseu->subslice_mask[i]);
-
- return total;
-}
-
-static u32
-sseu_get_subslices(const struct sseu_dev_info *sseu,
- const u8 *subslice_mask, u8 slice)
-{
- int i, offset = slice * sseu->ss_stride;
- u32 mask = 0;
-
- GEM_BUG_ON(slice >= sseu->max_slices);
-
- for (i = 0; i < sseu->ss_stride; i++)
- mask |= (u32)subslice_mask[offset + i] << i * BITS_PER_BYTE;
-
- return mask;
-}
-
-u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
-{
- return sseu_get_subslices(sseu, sseu->subslice_mask, slice);
-}
+ if (sseu->has_xehp_dss)
+ return bitmap_weight(sseu->subslice_mask.xehp,
+ XEHP_BITMAP_BITS(sseu->subslice_mask));
-static u32 sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
-{
- return sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
-}
+ for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++)
+ total += hweight8(sseu->subslice_mask.hsw[i]);
-u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu)
-{
- return sseu_get_subslices(sseu, sseu->compute_subslice_mask, 0);
-}
-
-void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
- u8 *subslice_mask, u32 ss_mask)
-{
- int offset = slice * sseu->ss_stride;
-
- memcpy(&subslice_mask[offset], &ss_mask, sseu->ss_stride);
+ return total;
}
unsigned int
-intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
+intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice)
{
- return hweight32(intel_sseu_get_subslices(sseu, slice));
+ WARN_ON(sseu->has_xehp_dss);
+ if (WARN_ON(slice >= sseu->max_slices))
+ return 0;
+
+ return sseu->subslice_mask.hsw[slice];
}
static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
@@ -147,32 +116,66 @@ int intel_sseu_copy_eumask_to_user(void __user *to,
return copy_to_user(to, eu_mask, len);
}
+/**
+ * intel_sseu_copy_ssmask_to_user - Copy subslice mask into a userspace buffer
+ * @to: Pointer to userspace buffer to copy to
+ * @sseu: SSEU structure containing subslice mask to copy
+ *
+ * Copies the subslice mask to a userspace buffer in the format expected by
+ * the query ioctl's topology queries.
+ *
+ * Returns the result of the copy_to_user() operation.
+ */
+int intel_sseu_copy_ssmask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu)
+{
+ u8 ss_mask[GEN_SS_MASK_SIZE] = {};
+ int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
+ int len = sseu->max_slices * ss_stride;
+ int s, ss, i;
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ for (ss = 0; ss < sseu->max_subslices; ss++) {
+ i = s * ss_stride * BITS_PER_BYTE + ss;
+
+ if (!intel_sseu_has_subslice(sseu, s, ss))
+ continue;
+
+ ss_mask[i / BITS_PER_BYTE] |= BIT(i % BITS_PER_BYTE);
+ }
+ }
+
+ return copy_to_user(to, ss_mask, len);
+}
+
static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
- u32 g_ss_en, u32 c_ss_en, u16 eu_en)
+ u32 ss_en, u16 eu_en)
{
u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
int ss;
- /* g_ss_en/c_ss_en represent entire subslice mask across all slices */
- GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
- sizeof(g_ss_en) * BITS_PER_BYTE);
+ sseu->slice_mask |= BIT(0);
+ sseu->subslice_mask.hsw[0] = ss_en & valid_ss_mask;
+
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (intel_sseu_has_subslice(sseu, 0, ss))
+ sseu_set_eus(sseu, 0, ss, eu_en);
+
+ sseu->eu_per_subslice = hweight16(eu_en);
+ sseu->eu_total = compute_eu_total(sseu);
+}
+
+static void xehp_compute_sseu_info(struct sseu_dev_info *sseu,
+ u16 eu_en)
+{
+ int ss;
sseu->slice_mask |= BIT(0);
- /*
- * XeHP introduces the concept of compute vs geometry DSS. To reduce
- * variation between GENs around subslice usage, store a mask for both
- * the geometry and compute enabled masks since userspace will need to
- * be able to query these masks independently. Also compute a total
- * enabled subslice count for the purposes of selecting subslices to
- * use in a particular GEM context.
- */
- intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
- c_ss_en & valid_ss_mask);
- intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
- g_ss_en & valid_ss_mask);
- intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
- (g_ss_en | c_ss_en) & valid_ss_mask);
+ bitmap_or(sseu->subslice_mask.xehp,
+ sseu->compute_subslice_mask.xehp,
+ sseu->geometry_subslice_mask.xehp,
+ XEHP_BITMAP_BITS(sseu->subslice_mask));
for (ss = 0; ss < sseu->max_subslices; ss++)
if (intel_sseu_has_subslice(sseu, 0, ss))
@@ -182,11 +185,31 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
sseu->eu_total = compute_eu_total(sseu);
}
+static void
+xehp_load_dss_mask(struct intel_uncore *uncore,
+ intel_sseu_ss_mask_t *ssmask,
+ int numregs,
+ ...)
+{
+ va_list argp;
+ u32 fuse_val[I915_MAX_SS_FUSE_REGS] = {};
+ int i;
+
+ if (WARN_ON(numregs > I915_MAX_SS_FUSE_REGS))
+ numregs = I915_MAX_SS_FUSE_REGS;
+
+ va_start(argp, numregs);
+ for (i = 0; i < numregs; i++)
+ fuse_val[i] = intel_uncore_read(uncore, va_arg(argp, i915_reg_t));
+ va_end(argp);
+
+ bitmap_from_arr32(ssmask->xehp, fuse_val, numregs * 32);
+}
+
static void xehp_sseu_info_init(struct intel_gt *gt)
{
struct sseu_dev_info *sseu = >->info.sseu;
struct intel_uncore *uncore = gt->uncore;
- u32 g_dss_en, c_dss_en = 0;
u16 eu_en = 0;
u8 eu_en_fuse;
int eu;
@@ -200,8 +223,10 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
intel_sseu_set_info(sseu, 1, 32, 16);
sseu->has_xehp_dss = 1;
- g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
- c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
+ xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 1,
+ GEN12_GT_GEOMETRY_DSS_ENABLE);
+ xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 1,
+ GEN12_GT_COMPUTE_DSS_ENABLE);
eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
@@ -209,7 +234,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
+ xehp_compute_sseu_info(sseu, eu_en);
}
static void gen12_sseu_info_init(struct intel_gt *gt)
@@ -247,7 +272,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
if (eu_en_fuse & BIT(eu))
eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
- gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, g_dss_en, eu_en);
/* TGL only supports slice-level power gating */
sseu->has_slice_pg = 1;
@@ -279,7 +304,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
GEN11_EU_DIS_MASK);
- gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
+ gen11_compute_sseu_info(sseu, ss_en, eu_en);
/* ICL has no power gating restrictions. */
sseu->has_slice_pg = 1;
@@ -291,7 +316,6 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
{
struct sseu_dev_info *sseu = >->info.sseu;
u32 fuse;
- u8 subslice_mask = 0;
fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT);
@@ -305,7 +329,7 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
- subslice_mask |= BIT(0);
+ sseu->subslice_mask.hsw[0] |= BIT(0);
sseu_set_eus(sseu, 0, 0, ~disabled_mask & 0xFF);
}
@@ -316,12 +340,10 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
(((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
- subslice_mask |= BIT(1);
+ sseu->subslice_mask.hsw[0] |= BIT(1);
sseu_set_eus(sseu, 0, 1, ~disabled_mask & 0xFF);
}
- intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask, subslice_mask);
-
sseu->eu_total = compute_eu_total(sseu);
/*
@@ -376,8 +398,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
/* skip disabled slice */
continue;
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
for (ss = 0; ss < sseu->max_subslices; ss++) {
@@ -434,8 +455,8 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
sseu->has_eu_pg = sseu->eu_per_subslice > 2;
if (IS_GEN9_LP(i915)) {
-#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
- info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
+#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask.hsw[0] & BIT(ss)))
+ info->has_pooled_eu = hweight8(sseu->subslice_mask.hsw[0]) == 3;
sseu->min_eu_in_pool = 0;
if (info->has_pooled_eu) {
@@ -489,8 +510,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
/* skip disabled slice */
continue;
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
for (ss = 0; ss < sseu->max_subslices; ss++) {
u8 eu_disabled_mask;
@@ -587,8 +607,7 @@ static void hsw_sseu_info_init(struct intel_gt *gt)
sseu->eu_per_subslice);
for (s = 0; s < sseu->max_slices; s++) {
- intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
- subslice_mask);
+ sseu->subslice_mask.hsw[s] = subslice_mask;
for (ss = 0; ss < sseu->max_subslices; ss++) {
sseu_set_eus(sseu, s, ss,
@@ -677,7 +696,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
*/
if (GRAPHICS_VER(i915) == 11 &&
slices == 1 &&
- subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
+ subslices > min_t(u8, 4, hweight8(sseu->subslice_mask.hsw[0]) / 2)) {
GEM_BUG_ON(subslices & 1);
subslice_pg = false;
@@ -743,14 +762,29 @@ void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
{
int s;
- drm_printf(p, "slice total: %u, mask=%04x\n",
- hweight8(sseu->slice_mask), sseu->slice_mask);
- drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
- for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
- s, intel_sseu_subslices_per_slice(sseu, s),
- intel_sseu_get_subslices(sseu, s));
+ if (sseu->has_xehp_dss) {
+ drm_printf(p, "subslice total: %u\n",
+ intel_sseu_subslice_total(sseu));
+ drm_printf(p, "geometry dss mask=%*pb\n",
+ XEHP_BITMAP_BITS(sseu->geometry_subslice_mask),
+ sseu->geometry_subslice_mask.xehp);
+ drm_printf(p, "compute dss mask=%*pb\n",
+ XEHP_BITMAP_BITS(sseu->compute_subslice_mask),
+ sseu->compute_subslice_mask.xehp);
+ } else {
+ drm_printf(p, "slice total: %u, mask=%04x\n",
+ hweight8(sseu->slice_mask), sseu->slice_mask);
+ drm_printf(p, "subslice total: %u\n",
+ intel_sseu_subslice_total(sseu));
+
+ for (s = 0; s < sseu->max_slices; s++) {
+ u8 ss_mask = sseu->subslice_mask.hsw[s];
+
+ drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
+ s, hweight8(ss_mask), ss_mask);
+ }
}
+
drm_printf(p, "EU total: %u\n", sseu->eu_total);
drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
drm_printf(p, "has slice power gating: %s\n",
@@ -767,9 +801,10 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
int s, ss;
for (s = 0; s < sseu->max_slices; s++) {
+ u8 ss_mask = sseu->subslice_mask.hsw[s];
+
drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
- s, intel_sseu_subslices_per_slice(sseu, s),
- intel_sseu_get_subslices(sseu, s));
+ s, hweight8(ss_mask), ss_mask);
for (ss = 0; ss < sseu->max_subslices; ss++) {
u16 enabled_eus = sseu_get_eus(sseu, s, ss);
@@ -783,16 +818,14 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
static void sseu_print_xehp_topology(const struct sseu_dev_info *sseu,
struct drm_printer *p)
{
- u32 g_dss_mask = sseu_get_geometry_subslices(sseu);
- u32 c_dss_mask = intel_sseu_get_compute_subslices(sseu);
int dss;
for (dss = 0; dss < sseu->max_subslices; dss++) {
u16 enabled_eus = sseu_get_eus(sseu, 0, dss);
drm_printf(p, "DSS_%02d: G:%3s C:%3s, %2u EUs (0x%04hx)\n", dss,
- str_yes_no(g_dss_mask & BIT(dss)),
- str_yes_no(c_dss_mask & BIT(dss)),
+ str_yes_no(test_bit(dss, sseu->geometry_subslice_mask.xehp)),
+ str_yes_no(test_bit(dss, sseu->compute_subslice_mask.xehp)),
hweight16(enabled_eus), enabled_eus);
}
}
@@ -810,20 +843,44 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
}
}
-u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice)
+void intel_sseu_print_ss_info(const char* type,
+ const struct sseu_dev_info *sseu,
+ struct seq_file *m)
+{
+ int s;
+
+ if (sseu->has_xehp_dss) {
+ seq_printf(m, " %s Geometry DSS: %u\n", type,
+ bitmap_weight(sseu->geometry_subslice_mask.xehp,
+ XEHP_BITMAP_BITS(sseu->geometry_subslice_mask)));
+ seq_printf(m, " %s Compute DSS: %u\n", type,
+ bitmap_weight(sseu->compute_subslice_mask.xehp,
+ XEHP_BITMAP_BITS(sseu->compute_subslice_mask)));
+ } else {
+ for (s = 0; s < fls(sseu->slice_mask); s++)
+ seq_printf(m, " %s Slice%i subslices: %u\n", type,
+ s, hweight8(sseu->subslice_mask.hsw[s]));
+ }
+}
+
+u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask,
+ int dss_per_slice)
{
+ intel_sseu_ss_mask_t per_slice_mask = {};
u16 slice_mask = 0;
int i;
- WARN_ON(sizeof(dss_mask) * 8 / dss_per_slice > 8 * sizeof(slice_mask));
+ WARN_ON(DIV_ROUND_UP(XEHP_BITMAP_BITS(dss_mask), dss_per_slice) >
+ 8 * sizeof(slice_mask));
- for (i = 0; dss_mask; i++) {
- if (dss_mask & GENMASK(dss_per_slice - 1, 0))
+ bitmap_fill(per_slice_mask.xehp, dss_per_slice);
+ for (i = 0; !bitmap_empty(dss_mask.xehp, XEHP_BITMAP_BITS(dss_mask)); i++) {
+ if (bitmap_intersects(dss_mask.xehp, per_slice_mask.xehp, dss_per_slice))
slice_mask |= BIT(i);
- dss_mask >>= dss_per_slice;
+ bitmap_shift_right(dss_mask.xehp, dss_mask.xehp, dss_per_slice,
+ XEHP_BITMAP_BITS(dss_mask));
}
return slice_mask;
}
-
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index ffa375e68959..e7f336a7ffbb 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -25,12 +25,16 @@ struct drm_printer;
/*
* Maximum number of subslices that can exist within a HSW-style slice. This
* is only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the
- * GEN_MAX_DSS value below).
+ * I915_MAX_SS_FUSE_BITS value below).
*/
#define GEN_MAX_SS_PER_HSW_SLICE 6
-/* Maximum number of DSS on newer platforms (Xe_HP and beyond). */
-#define GEN_MAX_DSS 32
+/*
+ * Maximum number of 32-bit registers used by hardware to express the
+ * enabled/disabled subslices.
+ */
+#define I915_MAX_SS_FUSE_REGS 1
+#define I915_MAX_SS_FUSE_BITS (I915_MAX_SS_FUSE_REGS * 32)
/* Maximum number of EUs that can exist within a subslice or DSS. */
#define GEN_MAX_EUS_PER_SS 16
@@ -38,7 +42,7 @@ struct drm_printer;
#define SSEU_MAX(a, b) ((a) > (b) ? (a) : (b))
/* The maximum number of bits needed to express each subslice/DSS independently */
-#define GEN_SS_MASK_SIZE SSEU_MAX(GEN_MAX_DSS, \
+#define GEN_SS_MASK_SIZE SSEU_MAX(I915_MAX_SS_FUSE_BITS, \
GEN_MAX_HSW_SLICES * GEN_MAX_SS_PER_HSW_SLICE)
#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
@@ -49,17 +53,24 @@ struct drm_printer;
#define GEN_DSS_PER_CSLICE 8
#define GEN_DSS_PER_MSLICE 8
-#define GEN_MAX_GSLICES (GEN_MAX_DSS / GEN_DSS_PER_GSLICE)
-#define GEN_MAX_CSLICES (GEN_MAX_DSS / GEN_DSS_PER_CSLICE)
+#define GEN_MAX_GSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_GSLICE)
+#define GEN_MAX_CSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_CSLICE)
+
+typedef union {
+ u8 hsw[GEN_MAX_HSW_SLICES];
+
+ /* Bitmap compatible with linux/bitmap.h; may exceed size of u64 */
+ unsigned long xehp[BITS_TO_LONGS(I915_MAX_SS_FUSE_BITS)];
+} intel_sseu_ss_mask_t;
struct sseu_dev_info {
u8 slice_mask;
- u8 subslice_mask[GEN_SS_MASK_SIZE];
- u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
- u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
+ intel_sseu_ss_mask_t subslice_mask;
+ intel_sseu_ss_mask_t geometry_subslice_mask;
+ intel_sseu_ss_mask_t compute_subslice_mask;
union {
u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
- u16 xehp[GEN_MAX_DSS];
+ u16 xehp[I915_MAX_SS_FUSE_BITS];
} eu_mask;
u16 eu_total;
@@ -80,8 +91,6 @@ struct sseu_dev_info {
u8 max_slices;
u8 max_subslices;
u8 max_eus_per_subslice;
-
- u8 ss_stride;
};
/*
@@ -99,7 +108,7 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
{
struct intel_sseu value = {
.slice_mask = sseu->slice_mask,
- .subslice_mask = sseu->subslice_mask[0],
+ .subslice_mask = sseu->subslice_mask.hsw[0],
.min_eus_per_subslice = sseu->max_eus_per_subslice,
.max_eus_per_subslice = sseu->max_eus_per_subslice,
};
@@ -111,18 +120,27 @@ static inline bool
intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
int subslice)
{
- u8 mask;
- int ss_idx = subslice / BITS_PER_BYTE;
-
if (slice >= sseu->max_slices ||
subslice >= sseu->max_subslices)
return false;
- GEM_BUG_ON(ss_idx >= sseu->ss_stride);
-
- mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx];
+ if (sseu->has_xehp_dss)
+ return test_bit(subslice, sseu->subslice_mask.xehp);
+ else
+ return sseu->subslice_mask.hsw[slice] & BIT(subslice);
+}
- return mask & BIT(subslice % BITS_PER_BYTE);
+/*
+ * Used to obtain the index of the first DSS. Can start searching from the
+ * beginning of a specific dss group (e.g., gslice, cslice, etc.) if
+ * groupsize and groupnum are non-zero.
+ */
+static inline unsigned int
+intel_sseu_find_first_xehp_dss(const struct sseu_dev_info *sseu, int groupsize,
+ int groupnum)
+{
+ return find_next_bit(sseu->subslice_mask.xehp, I915_MAX_SS_FUSE_BITS,
+ groupnum * groupsize);
}
void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
@@ -132,14 +150,10 @@ unsigned int
intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
unsigned int
-intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
-
-u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
+intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice);
-u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
-
-void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
- u8 *subslice_mask, u32 ss_mask);
+intel_sseu_ss_mask_t
+intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
void intel_sseu_info_init(struct intel_gt *gt);
@@ -151,9 +165,15 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
const struct sseu_dev_info *sseu,
struct drm_printer *p);
-u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
+u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask, int dss_per_slice);
int intel_sseu_copy_eumask_to_user(void __user *to,
const struct sseu_dev_info *sseu);
+int intel_sseu_copy_ssmask_to_user(void __user *to,
+ const struct sseu_dev_info *sseu);
+
+void intel_sseu_print_ss_info(const char* type,
+ const struct sseu_dev_info *sseu,
+ struct seq_file *m);
#endif /* __INTEL_SSEU_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
index 2d5d011e01db..c2ee5e1826b5 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
@@ -4,6 +4,7 @@
* Copyright © 2020 Intel Corporation
*/
+#include <linux/bitmap.h>
#include <linux/string_helpers.h>
#include "i915_drv.h"
@@ -11,14 +12,6 @@
#include "intel_gt_regs.h"
#include "intel_sseu_debugfs.h"
-static void sseu_copy_subslices(const struct sseu_dev_info *sseu,
- int slice, u8 *to_mask)
-{
- int offset = slice * sseu->ss_stride;
-
- memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
-}
-
static void cherryview_sseu_device_status(struct intel_gt *gt,
struct sseu_dev_info *sseu)
{
@@ -41,7 +34,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt,
continue;
sseu->slice_mask = BIT(0);
- sseu->subslice_mask[0] |= BIT(ss);
+ sseu->subslice_mask.hsw[0] |= BIT(ss);
eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
@@ -92,7 +85,7 @@ static void gen11_sseu_device_status(struct intel_gt *gt,
continue;
sseu->slice_mask |= BIT(s);
- sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -147,21 +140,17 @@ static void gen9_sseu_device_status(struct intel_gt *gt,
sseu->slice_mask |= BIT(s);
if (IS_GEN9_BC(gt->i915))
- sseu_copy_subslices(&info->sseu, s,
- sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
- u8 ss_idx = s * info->sseu.ss_stride +
- ss / BITS_PER_BYTE;
if (IS_GEN9_LP(gt->i915)) {
if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
/* skip disabled subslice */
continue;
- sseu->subslice_mask[ss_idx] |=
- BIT(ss % BITS_PER_BYTE);
+ sseu->subslice_mask.hsw[s] |= BIT(ss);
}
eu_cnt = eu_reg[2 * s + ss / 2] & eu_mask[ss % 2];
@@ -188,8 +177,7 @@ static void bdw_sseu_device_status(struct intel_gt *gt,
if (sseu->slice_mask) {
sseu->eu_per_subslice = info->sseu.eu_per_subslice;
for (s = 0; s < fls(sseu->slice_mask); s++)
- sseu_copy_subslices(&info->sseu, s,
- sseu->subslice_mask);
+ sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
sseu->eu_total = sseu->eu_per_subslice *
intel_sseu_subslice_total(sseu);
@@ -208,7 +196,6 @@ static void i915_print_sseu_info(struct seq_file *m,
const struct sseu_dev_info *sseu)
{
const char *type = is_available_info ? "Available" : "Enabled";
- int s;
seq_printf(m, " %s Slice Mask: %04x\n", type,
sseu->slice_mask);
@@ -216,10 +203,7 @@ static void i915_print_sseu_info(struct seq_file *m,
hweight8(sseu->slice_mask));
seq_printf(m, " %s Subslice Total: %u\n", type,
intel_sseu_subslice_total(sseu));
- for (s = 0; s < fls(sseu->slice_mask); s++) {
- seq_printf(m, " %s Slice%i subslices: %u\n", type,
- s, intel_sseu_subslices_per_slice(sseu, s));
- }
+ intel_sseu_print_ss_info(type, sseu, m);
seq_printf(m, " %s EU Total: %u\n", type,
sseu->eu_total);
seq_printf(m, " %s EU Per Subslice: %u\n", type,
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 73b59ea6fd3b..1bf62273e02d 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -948,8 +948,8 @@ gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
* on s/ss combo, the read should be done with read_subslice_reg.
*/
slice = ffs(sseu->slice_mask) - 1;
- GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
- subslice = ffs(intel_sseu_get_subslices(sseu, slice));
+ GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw));
+ subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice));
GEM_BUG_ON(!subslice);
subslice--;
@@ -1087,11 +1087,10 @@ static void
icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
{
const struct sseu_dev_info *sseu = >->info.sseu;
- unsigned int slice, subslice;
+ unsigned int subslice;
GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
- slice = 0;
/*
* Although a platform may have subslices, we need to always steer
@@ -1102,7 +1101,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
* one of the higher subslices, we run the risk of reading back 0's or
* random garbage.
*/
- subslice = __ffs(intel_sseu_get_subslices(sseu, slice));
+ subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0));
/*
* If the subslice we picked above also steers us to a valid L3 bank,
@@ -1112,7 +1111,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
if (gt->info.l3bank_mask & BIT(subslice))
gt->steering_table[L3BANK] = NULL;
- __add_mcr_wa(gt, wal, slice, subslice);
+ __add_mcr_wa(gt, wal, 0, subslice);
}
static void
@@ -1120,7 +1119,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
{
const struct sseu_dev_info *sseu = >->info.sseu;
unsigned long slice, subslice = 0, slice_mask = 0;
- u64 dss_mask = 0;
u32 lncf_mask = 0;
int i;
@@ -1151,8 +1149,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
*/
/* Find the potential gslice candidates */
- dss_mask = intel_sseu_get_subslices(sseu, 0);
- slice_mask = intel_slicemask_from_dssmask(dss_mask, GEN_DSS_PER_GSLICE);
+ slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask,
+ GEN_DSS_PER_GSLICE);
/*
* Find the potential LNCF candidates. Either LNCF within a valid
@@ -1177,9 +1175,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
}
slice = __ffs(slice_mask);
- subslice = __ffs(dss_mask >> (slice * GEN_DSS_PER_GSLICE));
+ subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice);
WARN_ON(subslice > GEN_DSS_PER_GSLICE);
- WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0);
__add_mcr_wa(gt, wal, slice, subslice);
@@ -2030,9 +2027,8 @@ engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
static bool needs_wa_1308578152(struct intel_engine_cs *engine)
{
- u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0);
-
- return (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0;
+ return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >
+ GEN_DSS_PER_GSLICE;
}
static void
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index ac9767c56619..6fd15b39570c 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -162,8 +162,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
return -EINVAL;
/* Only copy bits from the first slice */
- memcpy(&value, sseu->subslice_mask,
- min(sseu->ss_stride, (u8)sizeof(value)));
+ value = intel_sseu_get_hsw_subslices(sseu, 0);
if (!value)
return -ENODEV;
break;
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 89c475d525b8..0094f67c63f2 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -31,10 +31,11 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
static int fill_topology_info(const struct sseu_dev_info *sseu,
struct drm_i915_query_item *query_item,
- const u8 *subslice_mask)
+ intel_sseu_ss_mask_t subslice_mask)
{
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
+ int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
int eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
@@ -44,7 +45,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
return -ENODEV;
slice_length = sizeof(sseu->slice_mask);
- subslice_length = sseu->max_slices * sseu->ss_stride;
+ subslice_length = sseu->max_slices * ss_stride;
eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
total_length = sizeof(topo) + slice_length + subslice_length +
eu_length;
@@ -60,7 +61,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
topo.subslice_offset = slice_length;
- topo.subslice_stride = sseu->ss_stride;
+ topo.subslice_stride = ss_stride;
topo.eu_offset = slice_length + subslice_length;
topo.eu_stride = eu_stride;
@@ -72,9 +73,9 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
&sseu->slice_mask, slice_length))
return -EFAULT;
- if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
- sizeof(topo) + slice_length),
- subslice_mask, subslice_length))
+ if (intel_sseu_copy_ssmask_to_user(u64_to_user_ptr(query_item->data_ptr +
+ sizeof(topo) + slice_length),
+ sseu))
return -EFAULT;
if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
--
2.35.3
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: SSEU handling updates (rev2)
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
` (9 preceding siblings ...)
(?)
@ 2022-05-23 21:00 ` Patchwork
-1 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2022-05-23 21:00 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: i915: SSEU handling updates (rev2)
URL : https://patchwork.freedesktop.org/series/104244/
State : warning
== Summary ==
Error: dim checkpatch failed
65fb3ea005ad drm/i915/xehp: Use separate sseu init function
0299a3bc6a24 drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
07be465e9bf5 drm/i915/sseu: Simplify gen11+ SSEU handling
a779fdef7481 drm/i915/sseu: Don't try to store EU mask internally in UAPI format
6fc4ea291341 drm/i915/sseu: Disassociate internal subslice mask representation from uapi
-:522: ERROR:POINTER_LOCATION: "foo* bar" should be "foo *bar"
#522: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:846:
+void intel_sseu_print_ss_info(const char* type,
-:610: WARNING:NEW_TYPEDEFS: do not add new typedefs
#610: FILE: drivers/gpu/drm/i915/gt/intel_sseu.h:59:
+typedef union {
-:715: ERROR:POINTER_LOCATION: "foo* bar" should be "foo *bar"
#715: FILE: drivers/gpu/drm/i915/gt/intel_sseu.h:175:
+void intel_sseu_print_ss_info(const char* type,
total: 2 errors, 1 warnings, 0 checks, 834 lines checked
fcd7226e193b drm/i915/pvc: Add SSEU changes
^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: SSEU handling updates (rev2)
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
` (10 preceding siblings ...)
(?)
@ 2022-05-23 21:00 ` Patchwork
-1 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2022-05-23 21:00 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: i915: SSEU handling updates (rev2)
URL : https://patchwork.freedesktop.org/series/104244/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: SSEU handling updates (rev2)
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
` (11 preceding siblings ...)
(?)
@ 2022-05-23 21:23 ` Patchwork
2022-05-23 23:31 ` Matt Roper
-1 siblings, 1 reply; 36+ messages in thread
From: Patchwork @ 2022-05-23 21:23 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 7346 bytes --]
== Series Details ==
Series: i915: SSEU handling updates (rev2)
URL : https://patchwork.freedesktop.org/series/104244/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11693 -> Patchwork_104244v2
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_104244v2 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_104244v2, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/index.html
Participating hosts (44 -> 45)
------------------------------
Additional (2): fi-icl-u2 fi-tgl-u2
Missing (1): fi-hsw-4770
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_104244v2:
### CI changes ###
#### Possible regressions ####
* boot:
- fi-bdw-5557u: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/fi-bdw-5557u/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-bdw-5557u/boot.html
Known issues
------------
Here are the changes found in Patchwork_104244v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_gttfill@basic:
- fi-icl-u2: NOTRUN -> [INCOMPLETE][3] ([i915#4890])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-icl-u2/igt@gem_exec_gttfill@basic.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-u2: NOTRUN -> [SKIP][4] ([i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@gem_huc_copy@huc-copy.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [PASS][5] -> [DMESG-FAIL][6] ([i915#4494] / [i915#4957])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
- fi-snb-2600: [PASS][7] -> [INCOMPLETE][8] ([i915#3921])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_busy@basic@flip:
- fi-tgl-u2: NOTRUN -> [DMESG-WARN][9] ([i915#402]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_busy@basic@flip.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-tgl-u2: NOTRUN -> [SKIP][10] ([fdo#109284] / [fdo#111827]) +7 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-u2: NOTRUN -> [SKIP][11] ([i915#4103]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-modeset@b-edp1:
- bat-adlp-4: [PASS][12] -> [DMESG-WARN][13] ([i915#3576])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-u2: NOTRUN -> [SKIP][14] ([fdo#109285])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-tgl-u2: NOTRUN -> [SKIP][15] ([i915#3555])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-u2: NOTRUN -> [SKIP][16] ([i915#3301])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-icl-u2: NOTRUN -> [FAIL][17] ([i915#4312])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-icl-u2/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@smem:
- {fi-ehl-2}: [DMESG-WARN][18] ([i915#5122]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html
* igt@kms_flip@basic-plain-flip@a-edp1:
- bat-adlp-4: [DMESG-WARN][20] ([i915#3576]) -> [PASS][21] +2 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/bat-adlp-4/igt@kms_flip@basic-plain-flip@a-edp1.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/bat-adlp-4/igt@kms_flip@basic-plain-flip@a-edp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4890]: https://gitlab.freedesktop.org/drm/intel/issues/4890
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
Build changes
-------------
* Linux: CI_DRM_11693 -> Patchwork_104244v2
CI-20190529: 20190529
CI_DRM_11693: 14289bc81309b2126f4ba9f339837dacf34ddf9c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6485: 51663917b40d36086cc1c555ce4f67b22937694d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_104244v2: 14289bc81309b2126f4ba9f339837dacf34ddf9c @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
e3100146e9db drm/i915/pvc: Add SSEU changes
920dde2397e4 drm/i915/sseu: Disassociate internal subslice mask representation from uapi
67224fa58023 drm/i915/sseu: Don't try to store EU mask internally in UAPI format
ec3d320f5b49 drm/i915/sseu: Simplify gen11+ SSEU handling
f00314dcab14 drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
5edcd0a4da5f drm/i915/xehp: Use separate sseu init function
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/index.html
[-- Attachment #2: Type: text/html, Size: 8441 bytes --]
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: SSEU handling updates (rev2)
2022-05-23 21:23 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2022-05-23 23:31 ` Matt Roper
2022-05-24 16:20 ` Vudum, Lakshminarayana
0 siblings, 1 reply; 36+ messages in thread
From: Matt Roper @ 2022-05-23 23:31 UTC (permalink / raw)
To: intel-gfx; +Cc: Vudum, Lakshminarayana
On Mon, May 23, 2022 at 09:23:33PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: i915: SSEU handling updates (rev2)
> URL : https://patchwork.freedesktop.org/series/104244/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11693 -> Patchwork_104244v2
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_104244v2 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_104244v2, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/index.html
>
> Participating hosts (44 -> 45)
> ------------------------------
>
> Additional (2): fi-icl-u2 fi-tgl-u2
> Missing (1): fi-hsw-4770
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_104244v2:
>
> ### CI changes ###
>
> #### Possible regressions ####
>
> * boot:
> - fi-bdw-5557u: [PASS][1] -> [FAIL][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/fi-bdw-5557u/boot.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-bdw-5557u/boot.html
I don't see a boot failure here? It looks like i915 loaded
successfully, without errors. It also looks like more tests ran
successfully on the machine after that as well.
Matt
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_104244v2 that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_exec_gttfill@basic:
> - fi-icl-u2: NOTRUN -> [INCOMPLETE][3] ([i915#4890])
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-icl-u2/igt@gem_exec_gttfill@basic.html
>
> * igt@gem_huc_copy@huc-copy:
> - fi-tgl-u2: NOTRUN -> [SKIP][4] ([i915#2190])
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@gem_huc_copy@huc-copy.html
>
> * igt@i915_selftest@live@hangcheck:
> - bat-dg1-6: [PASS][5] -> [DMESG-FAIL][6] ([i915#4494] / [i915#4957])
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
> - fi-snb-2600: [PASS][7] -> [INCOMPLETE][8] ([i915#3921])
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
>
> * igt@kms_busy@basic@flip:
> - fi-tgl-u2: NOTRUN -> [DMESG-WARN][9] ([i915#402]) +3 similar issues
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_busy@basic@flip.html
>
> * igt@kms_chamelium@dp-hpd-fast:
> - fi-tgl-u2: NOTRUN -> [SKIP][10] ([fdo#109284] / [fdo#111827]) +7 similar issues
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_chamelium@dp-hpd-fast.html
>
> * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
> - fi-tgl-u2: NOTRUN -> [SKIP][11] ([i915#4103]) +1 similar issue
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
>
> * igt@kms_flip@basic-flip-vs-modeset@b-edp1:
> - bat-adlp-4: [PASS][12] -> [DMESG-WARN][13] ([i915#3576])
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html
>
> * igt@kms_force_connector_basic@force-load-detect:
> - fi-tgl-u2: NOTRUN -> [SKIP][14] ([fdo#109285])
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_force_connector_basic@force-load-detect.html
>
> * igt@kms_setmode@basic-clone-single-crtc:
> - fi-tgl-u2: NOTRUN -> [SKIP][15] ([i915#3555])
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_setmode@basic-clone-single-crtc.html
>
> * igt@prime_vgem@basic-userptr:
> - fi-tgl-u2: NOTRUN -> [SKIP][16] ([i915#3301])
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@prime_vgem@basic-userptr.html
>
> * igt@runner@aborted:
> - fi-icl-u2: NOTRUN -> [FAIL][17] ([i915#4312])
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-icl-u2/igt@runner@aborted.html
>
>
> #### Possible fixes ####
>
> * igt@gem_exec_suspend@basic-s0@smem:
> - {fi-ehl-2}: [DMESG-WARN][18] ([i915#5122]) -> [PASS][19]
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html
>
> * igt@kms_flip@basic-plain-flip@a-edp1:
> - bat-adlp-4: [DMESG-WARN][20] ([i915#3576]) -> [PASS][21] +2 similar issues
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/bat-adlp-4/igt@kms_flip@basic-plain-flip@a-edp1.html
> [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/bat-adlp-4/igt@kms_flip@basic-plain-flip@a-edp1.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
> [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
> [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
> [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
> [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
> [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
> [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
> [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
> [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
> [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
> [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
> [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
> [i915#4890]: https://gitlab.freedesktop.org/drm/intel/issues/4890
> [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
> [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_11693 -> Patchwork_104244v2
>
> CI-20190529: 20190529
> CI_DRM_11693: 14289bc81309b2126f4ba9f339837dacf34ddf9c @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6485: 51663917b40d36086cc1c555ce4f67b22937694d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_104244v2: 14289bc81309b2126f4ba9f339837dacf34ddf9c @ git://anongit.freedesktop.org/gfx-ci/linux
>
>
> ### Linux commits
>
> e3100146e9db drm/i915/pvc: Add SSEU changes
> 920dde2397e4 drm/i915/sseu: Disassociate internal subslice mask representation from uapi
> 67224fa58023 drm/i915/sseu: Don't try to store EU mask internally in UAPI format
> ec3d320f5b49 drm/i915/sseu: Simplify gen11+ SSEU handling
> f00314dcab14 drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
> 5edcd0a4da5f drm/i915/xehp: Use separate sseu init function
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: SSEU handling updates (rev2)
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
` (12 preceding siblings ...)
(?)
@ 2022-05-24 2:51 ` Patchwork
-1 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2022-05-24 2:51 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 7346 bytes --]
== Series Details ==
Series: i915: SSEU handling updates (rev2)
URL : https://patchwork.freedesktop.org/series/104244/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11693 -> Patchwork_104244v2
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_104244v2 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_104244v2, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/index.html
Participating hosts (44 -> 45)
------------------------------
Additional (2): fi-icl-u2 fi-tgl-u2
Missing (1): fi-hsw-4770
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_104244v2:
### CI changes ###
#### Possible regressions ####
* boot:
- fi-bdw-5557u: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/fi-bdw-5557u/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-bdw-5557u/boot.html
Known issues
------------
Here are the changes found in Patchwork_104244v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_gttfill@basic:
- fi-icl-u2: NOTRUN -> [INCOMPLETE][3] ([i915#4890])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-icl-u2/igt@gem_exec_gttfill@basic.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-u2: NOTRUN -> [SKIP][4] ([i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@gem_huc_copy@huc-copy.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [PASS][5] -> [DMESG-FAIL][6] ([i915#4494] / [i915#4957])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
- fi-snb-2600: [PASS][7] -> [INCOMPLETE][8] ([i915#3921])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_busy@basic@flip:
- fi-tgl-u2: NOTRUN -> [DMESG-WARN][9] ([i915#402]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_busy@basic@flip.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-tgl-u2: NOTRUN -> [SKIP][10] ([fdo#109284] / [fdo#111827]) +7 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-u2: NOTRUN -> [SKIP][11] ([i915#4103]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-modeset@b-edp1:
- bat-adlp-4: [PASS][12] -> [DMESG-WARN][13] ([i915#3576])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-u2: NOTRUN -> [SKIP][14] ([fdo#109285])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-tgl-u2: NOTRUN -> [SKIP][15] ([i915#3555])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-u2: NOTRUN -> [SKIP][16] ([i915#3301])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-icl-u2: NOTRUN -> [FAIL][17] ([i915#4312])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-icl-u2/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@smem:
- {fi-ehl-2}: [DMESG-WARN][18] ([i915#5122]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html
* igt@kms_flip@basic-plain-flip@a-edp1:
- bat-adlp-4: [DMESG-WARN][20] ([i915#3576]) -> [PASS][21] +2 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/bat-adlp-4/igt@kms_flip@basic-plain-flip@a-edp1.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/bat-adlp-4/igt@kms_flip@basic-plain-flip@a-edp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4890]: https://gitlab.freedesktop.org/drm/intel/issues/4890
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
Build changes
-------------
* Linux: CI_DRM_11693 -> Patchwork_104244v2
CI-20190529: 20190529
CI_DRM_11693: 14289bc81309b2126f4ba9f339837dacf34ddf9c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6485: 51663917b40d36086cc1c555ce4f67b22937694d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_104244v2: 14289bc81309b2126f4ba9f339837dacf34ddf9c @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
e3100146e9db drm/i915/pvc: Add SSEU changes
920dde2397e4 drm/i915/sseu: Disassociate internal subslice mask representation from uapi
67224fa58023 drm/i915/sseu: Don't try to store EU mask internally in UAPI format
ec3d320f5b49 drm/i915/sseu: Simplify gen11+ SSEU handling
f00314dcab14 drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
5edcd0a4da5f drm/i915/xehp: Use separate sseu init function
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/index.html
[-- Attachment #2: Type: text/html, Size: 8441 bytes --]
^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for i915: SSEU handling updates (rev2)
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
` (13 preceding siblings ...)
(?)
@ 2022-05-24 5:52 ` Patchwork
-1 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2022-05-24 5:52 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6986 bytes --]
== Series Details ==
Series: i915: SSEU handling updates (rev2)
URL : https://patchwork.freedesktop.org/series/104244/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11693 -> Patchwork_104244v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/index.html
Participating hosts (44 -> 45)
------------------------------
Additional (2): fi-icl-u2 fi-tgl-u2
Missing (1): fi-hsw-4770
Known issues
------------
Here are the changes found in Patchwork_104244v2 that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- fi-bdw-5557u: [PASS][1] -> [FAIL][2] ([i915#6074])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/fi-bdw-5557u/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-bdw-5557u/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_gttfill@basic:
- fi-icl-u2: NOTRUN -> [INCOMPLETE][3] ([i915#4890])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-icl-u2/igt@gem_exec_gttfill@basic.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-u2: NOTRUN -> [SKIP][4] ([i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@gem_huc_copy@huc-copy.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [PASS][5] -> [DMESG-FAIL][6] ([i915#4494] / [i915#4957])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
- fi-snb-2600: [PASS][7] -> [INCOMPLETE][8] ([i915#3921])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_busy@basic@flip:
- fi-tgl-u2: NOTRUN -> [DMESG-WARN][9] ([i915#402]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_busy@basic@flip.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-tgl-u2: NOTRUN -> [SKIP][10] ([fdo#109284] / [fdo#111827]) +7 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-u2: NOTRUN -> [SKIP][11] ([i915#4103]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-modeset@b-edp1:
- bat-adlp-4: [PASS][12] -> [DMESG-WARN][13] ([i915#3576])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-u2: NOTRUN -> [SKIP][14] ([fdo#109285])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-tgl-u2: NOTRUN -> [SKIP][15] ([i915#3555])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-u2: NOTRUN -> [SKIP][16] ([i915#3301])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-icl-u2: NOTRUN -> [FAIL][17] ([i915#4312])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-icl-u2/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@smem:
- {fi-ehl-2}: [DMESG-WARN][18] ([i915#5122]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html
* igt@kms_flip@basic-plain-flip@a-edp1:
- bat-adlp-4: [DMESG-WARN][20] ([i915#3576]) -> [PASS][21] +2 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/bat-adlp-4/igt@kms_flip@basic-plain-flip@a-edp1.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/bat-adlp-4/igt@kms_flip@basic-plain-flip@a-edp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4890]: https://gitlab.freedesktop.org/drm/intel/issues/4890
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
[i915#6074]: https://gitlab.freedesktop.org/drm/intel/issues/6074
Build changes
-------------
* Linux: CI_DRM_11693 -> Patchwork_104244v2
CI-20190529: 20190529
CI_DRM_11693: 14289bc81309b2126f4ba9f339837dacf34ddf9c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6485: 51663917b40d36086cc1c555ce4f67b22937694d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_104244v2: 14289bc81309b2126f4ba9f339837dacf34ddf9c @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
e3100146e9db drm/i915/pvc: Add SSEU changes
920dde2397e4 drm/i915/sseu: Disassociate internal subslice mask representation from uapi
67224fa58023 drm/i915/sseu: Don't try to store EU mask internally in UAPI format
ec3d320f5b49 drm/i915/sseu: Simplify gen11+ SSEU handling
f00314dcab14 drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
5edcd0a4da5f drm/i915/xehp: Use separate sseu init function
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/index.html
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^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: SSEU handling updates (rev2)
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
` (14 preceding siblings ...)
(?)
@ 2022-05-24 7:07 ` Patchwork
-1 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2022-05-24 7:07 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 40553 bytes --]
== Series Details ==
Series: i915: SSEU handling updates (rev2)
URL : https://patchwork.freedesktop.org/series/104244/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11693_full -> Patchwork_104244v2_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_104244v2_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_104244v2_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (12 -> 12)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_104244v2_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@dmabuf:
- shard-skl: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl4/igt@i915_selftest@live@dmabuf.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl3/igt@i915_selftest@live@dmabuf.html
Known issues
------------
Here are the changes found in Patchwork_104244v2_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-skl: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22]) -> ([PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [FAIL][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44]) ([i915#5032])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl6/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl5/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl5/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl4/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl4/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl2/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl2/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl1/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl1/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl10/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl10/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl10/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl9/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl9/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl8/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl8/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl8/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl7/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl7/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl6/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl6/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl4/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl4/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl3/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl3/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl3/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl2/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl2/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl1/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl1/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl10/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl10/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl9/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl9/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl9/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl9/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl8/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl8/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl8/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl7/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl7/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl6/boot.html
### IGT changes ###
#### Issues hit ####
* igt@api_intel_allocator@fork-simple-stress-signal:
- shard-iclb: [PASS][45] -> [DMESG-WARN][46] ([i915#4391])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb1/igt@api_intel_allocator@fork-simple-stress-signal.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb7/igt@api_intel_allocator@fork-simple-stress-signal.html
* igt@gem_create@create-massive:
- shard-skl: NOTRUN -> [DMESG-WARN][47] ([i915#4991])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl1/igt@gem_create@create-massive.html
* igt@gem_eio@in-flight-contexts-1us:
- shard-apl: NOTRUN -> [TIMEOUT][48] ([i915#3063])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl6/igt@gem_eio@in-flight-contexts-1us.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: NOTRUN -> [FAIL][49] ([i915#2846])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][50] -> [FAIL][51] ([i915#2842])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-tglb: NOTRUN -> [FAIL][52] ([i915#2842])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [PASS][53] -> [FAIL][54] ([i915#2842]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl6/igt@gem_exec_fair@basic-pace@rcs0.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl4/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_flush@basic-wb-rw-default:
- shard-snb: [PASS][55] -> [SKIP][56] ([fdo#109271]) +2 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-snb2/igt@gem_exec_flush@basic-wb-rw-default.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-snb6/igt@gem_exec_flush@basic-wb-rw-default.html
* igt@gem_lmem_swapping@basic:
- shard-tglb: NOTRUN -> [SKIP][57] ([i915#4613])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@random:
- shard-apl: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#4613]) +2 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl3/igt@gem_lmem_swapping@random.html
* igt@gem_lmem_swapping@verify-random-ccs:
- shard-skl: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#4613]) +2 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl2/igt@gem_lmem_swapping@verify-random-ccs.html
* igt@gem_pxp@verify-pxp-stale-buf-optout-execution:
- shard-tglb: NOTRUN -> [SKIP][60] ([i915#4270])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][61] -> [DMESG-WARN][62] ([i915#5566] / [i915#716])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-apl1/igt@gen9_exec_parse@allowed-single.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl1/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc6-dpms:
- shard-skl: NOTRUN -> [FAIL][63] ([i915#454])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl8/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][64] -> [FAIL][65] ([i915#454])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-apl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#1937])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl6/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][67] ([i915#5286])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][68] ([fdo#111614])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][69] ([i915#3743]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][70] ([i915#3763])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#3886]) +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl6/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#3886]) +5 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl8/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#3886])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk2/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][74] ([i915#3689] / [i915#3886])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][75] ([i915#3689])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_ccs.html
* igt@kms_ccs@pipe-d-random-ccs-data-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][76] ([fdo#111615] / [i915#3689])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_ccs@pipe-d-random-ccs-data-yf_tiled_ccs.html
* igt@kms_chamelium@hdmi-audio:
- shard-apl: NOTRUN -> [SKIP][77] ([fdo#109271] / [fdo#111827]) +8 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl6/igt@kms_chamelium@hdmi-audio.html
* igt@kms_color@pipe-c-deep-color:
- shard-tglb: NOTRUN -> [SKIP][78] ([i915#3555])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_color@pipe-c-deep-color.html
* igt@kms_color_chamelium@pipe-a-ctm-negative:
- shard-tglb: NOTRUN -> [SKIP][79] ([fdo#109284] / [fdo#111827])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_color_chamelium@pipe-a-ctm-negative.html
* igt@kms_color_chamelium@pipe-d-ctm-red-to-blue:
- shard-skl: NOTRUN -> [SKIP][80] ([fdo#109271] / [fdo#111827]) +9 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl8/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-d-degamma:
- shard-glk: NOTRUN -> [SKIP][81] ([fdo#109271] / [fdo#111827]) +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk2/igt@kms_color_chamelium@pipe-d-degamma.html
* igt@kms_cursor_crc@pipe-a-cursor-32x10-sliding:
- shard-tglb: NOTRUN -> [SKIP][82] ([i915#3359])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_cursor_crc@pipe-a-cursor-32x10-sliding.html
* igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding:
- shard-tglb: NOTRUN -> [SKIP][83] ([fdo#109279] / [i915#3359]) +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
- shard-tglb: NOTRUN -> [SKIP][84] ([fdo#109274] / [fdo#111825])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-4tiled:
- shard-tglb: NOTRUN -> [SKIP][85] ([i915#5287])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-4tiled.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-tglb: NOTRUN -> [SKIP][86] ([fdo#109274] / [fdo#111825] / [i915#3966])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][87] -> [FAIL][88] ([i915#79])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [PASS][89] -> [FAIL][90] ([i915#2122])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-skl: [PASS][91] -> [FAIL][92] ([i915#79])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-edp1:
- shard-iclb: [PASS][93] -> [DMESG-WARN][94] ([i915#2867])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb1/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb7/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
- shard-iclb: [PASS][95] -> [SKIP][96] ([i915#3701])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
- shard-glk: [PASS][97] -> [FAIL][98] ([i915#4911])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-glk9/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
- shard-skl: NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#3701])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl4/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-tglb: NOTRUN -> [SKIP][100] ([fdo#109280] / [fdo#111825]) +3 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-apl: NOTRUN -> [SKIP][101] ([fdo#109271]) +91 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
- shard-glk: NOTRUN -> [SKIP][102] ([fdo#109271]) +24 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk2/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][103] ([fdo#109271] / [i915#533])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl6/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-apl: [PASS][104] -> [DMESG-WARN][105] ([i915#180]) +3 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-glk: NOTRUN -> [FAIL][106] ([fdo#108145] / [i915#265])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk2/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-skl: NOTRUN -> [FAIL][107] ([fdo#108145] / [i915#265]) +1 similar issue
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
* igt@kms_plane_lowres@pipe-a-tiling-none:
- shard-tglb: NOTRUN -> [SKIP][108] ([i915#3536])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_plane_lowres@pipe-a-tiling-none.html
* igt@kms_plane_lowres@pipe-c-tiling-4:
- shard-tglb: NOTRUN -> [SKIP][109] ([i915#5288])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_plane_lowres@pipe-c-tiling-4.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-edp-1-planes-upscale-downscale:
- shard-skl: NOTRUN -> [SKIP][110] ([fdo#109271]) +168 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl4/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-edp-1-planes-upscale-downscale.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-edp-1-planes-upscale-downscale:
- shard-iclb: [PASS][111] -> [SKIP][112] ([i915#5235]) +2 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb3/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-edp-1-planes-upscale-downscale.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-edp-1-planes-upscale-downscale.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-skl: NOTRUN -> [SKIP][113] ([fdo#109271] / [i915#658])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl2/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-glk: NOTRUN -> [SKIP][114] ([fdo#109271] / [i915#658]) +1 similar issue
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk2/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][115] -> [SKIP][116] ([fdo#109441]) +1 similar issue
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb4/igt@kms_psr@psr2_sprite_plane_move.html
* igt@nouveau_crc@ctx-flip-threshold-reset-after-capture:
- shard-tglb: NOTRUN -> [SKIP][117] ([i915#2530])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@nouveau_crc@ctx-flip-threshold-reset-after-capture.html
* igt@perf@stress-open-close:
- shard-glk: [PASS][118] -> [INCOMPLETE][119] ([i915#5213])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-glk2/igt@perf@stress-open-close.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk5/igt@perf@stress-open-close.html
* igt@prime_nv_api@i915_self_import_to_different_fd:
- shard-tglb: NOTRUN -> [SKIP][120] ([fdo#109291])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@prime_nv_api@i915_self_import_to_different_fd.html
* igt@sysfs_clients@fair-3:
- shard-glk: NOTRUN -> [SKIP][121] ([fdo#109271] / [i915#2994])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk2/igt@sysfs_clients@fair-3.html
* igt@sysfs_clients@fair-7:
- shard-apl: NOTRUN -> [SKIP][122] ([fdo#109271] / [i915#2994]) +1 similar issue
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl6/igt@sysfs_clients@fair-7.html
* igt@sysfs_clients@pidname:
- shard-tglb: NOTRUN -> [SKIP][123] ([i915#2994])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@sysfs_clients@pidname.html
#### Possible fixes ####
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][124] ([i915#658]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb3/igt@feature_discovery@psr2.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-iclb: [TIMEOUT][126] ([i915#3070]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb3/igt@gem_eio@in-flight-contexts-10ms.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb2/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_eio@in-flight-immediate:
- shard-tglb: [TIMEOUT][128] ([i915#3063]) -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-tglb1/igt@gem_eio@in-flight-immediate.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb6/igt@gem_eio@in-flight-immediate.html
* igt@gem_eio@reset-stress:
- shard-apl: [FAIL][130] -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-apl2/igt@gem_eio@reset-stress.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl1/igt@gem_eio@reset-stress.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [FAIL][132] ([i915#2842]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-apl4/igt@gem_exec_fair@basic-none@vecs0.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl3/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [FAIL][134] ([i915#2842]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-glk3/igt@gem_exec_fair@basic-throttle@rcs0.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [DMESG-WARN][136] ([i915#5566] / [i915#716]) -> [PASS][137]
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-glk3/igt@gen9_exec_parse@allowed-single.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk2/igt@gen9_exec_parse@allowed-single.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [INCOMPLETE][138] ([i915#3921]) -> [PASS][139]
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-snb5/igt@i915_selftest@live@hangcheck.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-snb7/igt@i915_selftest@live@hangcheck.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@b-edp1:
- shard-skl: [FAIL][140] ([i915#2122]) -> [PASS][141]
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl2/igt@kms_flip@flip-vs-blocking-wf-vblank@b-edp1.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl9/igt@kms_flip@flip-vs-blocking-wf-vblank@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [FAIL][142] ([i915#79]) -> [PASS][143]
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1:
- shard-glk: [FAIL][144] ([i915#79]) -> [PASS][145]
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1:
- shard-kbl: [FAIL][146] ([i915#79]) -> [PASS][147]
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [DMESG-WARN][148] ([i915#180]) -> [PASS][149] +2 similar issues
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-kbl: [DMESG-WARN][150] ([i915#180]) -> [PASS][151]
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl7/igt@kms_flip@flip-vs-suspend@a-dp1.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl3/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale:
- shard-iclb: [SKIP][152] ([i915#5235]) -> [PASS][153] +2 similar issues
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb4/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][154] ([fdo#109441]) -> [PASS][155] +2 similar issues
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb3/igt@kms_psr@psr2_primary_mmap_cpu.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-iclb: [SKIP][156] ([i915#5519]) -> [PASS][157]
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb8/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb5/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
#### Warnings ####
* igt@kms_flip@flip-vs-suspend@b-dp1:
- shard-kbl: [DMESG-WARN][158] ([i915#180]) -> [INCOMPLETE][159] ([i915#3614])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl7/igt@kms_flip@flip-vs-suspend@b-dp1.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl3/igt@kms_flip@flip-vs-suspend@b-dp1.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-iclb: [SKIP][160] ([i915#658]) -> [SKIP][161] ([i915#2920])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb3/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-iclb: [SKIP][162] ([i915#2920]) -> [SKIP][163] ([i915#658])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb4/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][164], [FAIL][165], [FAIL][166], [FAIL][167], [FAIL][168], [FAIL][169], [FAIL][170], [FAIL][171], [FAIL][172]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][173], [FAIL][174], [FAIL][175], [FAIL][176], [FAIL][177], [FAIL][178], [FAIL][179], [FAIL][180]) ([i915#3002] / [i915#4312] / [i915#5257])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl4/igt@runner@aborted.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl1/igt@runner@aborted.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl7/igt@runner@aborted.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl7/igt@runner@aborted.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl1/igt@runner@aborted.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl4/igt@runner@aborted.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl7/igt@runner@aborted.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl1/igt@runner@aborted.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl6/igt@runner@aborted.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl1/igt@runner@aborted.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl6/igt@runner@aborted.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl7/igt@runner@aborted.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl6/igt@runner@aborted.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl7/igt@runner@aborted.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl4/igt@runner@aborted.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl1/igt@runner@aborted.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl7/igt@runner@aborted.html
- shard-skl: ([FAIL][181], [FAIL][182], [FAIL][183], [FAIL][184]) ([i915#2029] / [i915#4312] / [i915#5257]) -> ([FAIL][185], [FAIL][186], [FAIL][187]) ([i915#3002] / [i915#4312] / [i915#5257])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl6/igt@runner@aborted.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl2/igt@runner@aborted.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl8/igt@runner@aborted.html
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl5/igt@runner@aborted.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl9/igt@runner@aborted.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl9/igt@runner@aborted.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl1/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3614]: https://gitlab.freedesktop.org/drm/intel/issues/3614
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3763]: https://gitlab.freedesktop.org/drm/intel/issues/3763
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4241]: https://gitlab.freedesktop.org/drm/intel/issues/4241
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4883]: https://gitlab.freedesktop.org/drm/intel/issues/4883
[i915#4911]: https://gitlab.freedesktop.org/drm/intel/issues/4911
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5032]: https://gitlab.freedesktop.org/drm/intel/issues/5032
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5182]: https://gitlab.freedesktop.org/drm/intel/issues/5182
[i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
[i915#5721]: https://gitlab.freedesktop.org/drm/intel/issues/5721
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_11693 -> Patchwork_104244v2
CI-20190529: 20190529
CI_DRM_11693: 14289bc81309b2126f4ba9f339837dacf34ddf9c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6485: 51663917b40d36086cc1c555ce4f67b22937694d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_104244v2: 14289bc81309b2126f4ba9f339837dacf34ddf9c @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/index.html
[-- Attachment #2: Type: text/html, Size: 47371 bytes --]
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 0/6] i915: SSEU handling updates
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
@ 2022-05-24 7:32 ` Tvrtko Ursulin
-1 siblings, 0 replies; 36+ messages in thread
From: Tvrtko Ursulin @ 2022-05-24 7:32 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel
On 21/05/2022 00:04, Matt Roper wrote:
> This series reworks i915's internal handling of slice/subslice/EU (SSEU)
> data to represent platforms like Xe_HP in a more natural manner and to
> prepare for future platforms where the masks will need to grow in size.
> One key idea of this series is that although we have a fixed ABI to
> convey SSEU data to userspace (i.e., multiple u8[] arrays with data
> stored at different strides), we don't need to use this cumbersome
> format for the driver's own internal storage. As long as we can convert
> into the uapi form properly when responding to the I915_QUERY ioctl,
> it's preferable to use an internal storage format that's easier for the
> driver to work with.
>
> Another key point here is that we're reaching the point where subslice
> (DSS) masks will soon not fit within simple u32/u64 integer values.
> Xe_HP SDV and DG2 platforms today have subslice (DSS) masks that are 32
> bits, which maxes out the current storage of a u32. With PVC the masks
> are represented by a pair of 32-bit registers, requiring a bump up to at
> least 64-bits of storage internally. We could switch to u64 for that in
> the short term, but since we already know that upcoming architectures
> intend to provide DSS fuse bits via three or more registers it's best to
> switch to a representation that's more future-proof but still easy to
> work with in the driver code. To accomodate this, we start storing our
> subslice mask for Xe_HP and beyond in a new typedef that can be
> processed by the linux/bitmap.h operations.
>
> Finally, since no userspace for Xe_HP or beyond is using the legacy
> I915_GETPARAM ioctl lookups for I915_PARAM_SLICE_MASK and
> I915_PARAM_SUBSLICE_MASK (since they've migrated to the more flexible
> I915_QUERY ioctl that can return more than a simple u32 value), we take
> the opportunity to officially drop support for those GETPARAM lookups on
> modern platforms. Maintaining support for these GETPARAM lookups don't
> make sense for a number of reasons:
>
> * Traditional slices no longer exist, and newer ideas like gslices,
> cslices, mslices, etc. aren't something userspace needs to query
> since it can be inferred from other information.
> * The GETPARAM ioctl doesn't have a way to distinguish between geometry
> subslice masks and compute subslice masks, which are distinct on
> Xe_HP and beyond.
> * The I915_GETPARAM ioctl is limited to returning a 32-bit value, so
> when subslice masks begin to exceed 32-bits (on PVC), it simply can't
> return the entire mask.
> * The GETPARAM ioctl doesn't have a way to give sensible information
> for multi-tile devices.
>
> v2:
> - Switch to union of hsw/xehp formats to keep the representation in a
> natural format for different types of hardware.
> - Avoid accessing internals of intel_sseu_ss_mask_t directly outside of
> intel_sseu.[ch].
> - Include PVC SSEU which needs the larger SS mask storage enabled by
> this series.
>
> v3:
> - Correct a BIT(s) typo that should have been BIT(ss), causing
> incorrect handling on gen9 platforms.
>
> v4:
> - Eliminate sseu->{ss,eu}_stride fields and just calculate the proper
> value in the UAPI code that needs them.
> - Handle unwanted ~u8 sign extension at the callsite instead of inside
> sseu_set_eus.
> - Use BITMAP_BITS() macro rather than passing I915_MAX_SS_FUSE_BITS
> around directly to bitmap operations.
> - Improved debugfs / dmesg reporting for Xe_HP dumps
> - Various assertion check improvements.
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>
>
> Matt Roper (6):
> drm/i915/xehp: Use separate sseu init function
> drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
> drm/i915/sseu: Simplify gen11+ SSEU handling
> drm/i915/sseu: Don't try to store EU mask internally in UAPI format
> drm/i915/sseu: Disassociate internal subslice mask representation from
> uapi
> drm/i915/pvc: Add SSEU changes
For the series:
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Almost r-b actually, but I do not feel completely comfortable that I
read everything closely enough to not have missed something. So I prefer
someone else does a really detailed pass to be sure.
Regards,
Tvrtko
>
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 12 +-
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_sseu.c | 450 ++++++++++++-------
> drivers/gpu/drm/i915/gt/intel_sseu.h | 94 ++--
> drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +-
> drivers/gpu/drm/i915/i915_drv.h | 2 +
> drivers/gpu/drm/i915/i915_getparam.c | 11 +-
> drivers/gpu/drm/i915/i915_pci.c | 3 +-
> drivers/gpu/drm/i915/i915_query.c | 26 +-
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> 13 files changed, 398 insertions(+), 265 deletions(-)
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v4 0/6] i915: SSEU handling updates
@ 2022-05-24 7:32 ` Tvrtko Ursulin
0 siblings, 0 replies; 36+ messages in thread
From: Tvrtko Ursulin @ 2022-05-24 7:32 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel
On 21/05/2022 00:04, Matt Roper wrote:
> This series reworks i915's internal handling of slice/subslice/EU (SSEU)
> data to represent platforms like Xe_HP in a more natural manner and to
> prepare for future platforms where the masks will need to grow in size.
> One key idea of this series is that although we have a fixed ABI to
> convey SSEU data to userspace (i.e., multiple u8[] arrays with data
> stored at different strides), we don't need to use this cumbersome
> format for the driver's own internal storage. As long as we can convert
> into the uapi form properly when responding to the I915_QUERY ioctl,
> it's preferable to use an internal storage format that's easier for the
> driver to work with.
>
> Another key point here is that we're reaching the point where subslice
> (DSS) masks will soon not fit within simple u32/u64 integer values.
> Xe_HP SDV and DG2 platforms today have subslice (DSS) masks that are 32
> bits, which maxes out the current storage of a u32. With PVC the masks
> are represented by a pair of 32-bit registers, requiring a bump up to at
> least 64-bits of storage internally. We could switch to u64 for that in
> the short term, but since we already know that upcoming architectures
> intend to provide DSS fuse bits via three or more registers it's best to
> switch to a representation that's more future-proof but still easy to
> work with in the driver code. To accomodate this, we start storing our
> subslice mask for Xe_HP and beyond in a new typedef that can be
> processed by the linux/bitmap.h operations.
>
> Finally, since no userspace for Xe_HP or beyond is using the legacy
> I915_GETPARAM ioctl lookups for I915_PARAM_SLICE_MASK and
> I915_PARAM_SUBSLICE_MASK (since they've migrated to the more flexible
> I915_QUERY ioctl that can return more than a simple u32 value), we take
> the opportunity to officially drop support for those GETPARAM lookups on
> modern platforms. Maintaining support for these GETPARAM lookups don't
> make sense for a number of reasons:
>
> * Traditional slices no longer exist, and newer ideas like gslices,
> cslices, mslices, etc. aren't something userspace needs to query
> since it can be inferred from other information.
> * The GETPARAM ioctl doesn't have a way to distinguish between geometry
> subslice masks and compute subslice masks, which are distinct on
> Xe_HP and beyond.
> * The I915_GETPARAM ioctl is limited to returning a 32-bit value, so
> when subslice masks begin to exceed 32-bits (on PVC), it simply can't
> return the entire mask.
> * The GETPARAM ioctl doesn't have a way to give sensible information
> for multi-tile devices.
>
> v2:
> - Switch to union of hsw/xehp formats to keep the representation in a
> natural format for different types of hardware.
> - Avoid accessing internals of intel_sseu_ss_mask_t directly outside of
> intel_sseu.[ch].
> - Include PVC SSEU which needs the larger SS mask storage enabled by
> this series.
>
> v3:
> - Correct a BIT(s) typo that should have been BIT(ss), causing
> incorrect handling on gen9 platforms.
>
> v4:
> - Eliminate sseu->{ss,eu}_stride fields and just calculate the proper
> value in the UAPI code that needs them.
> - Handle unwanted ~u8 sign extension at the callsite instead of inside
> sseu_set_eus.
> - Use BITMAP_BITS() macro rather than passing I915_MAX_SS_FUSE_BITS
> around directly to bitmap operations.
> - Improved debugfs / dmesg reporting for Xe_HP dumps
> - Various assertion check improvements.
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>
>
> Matt Roper (6):
> drm/i915/xehp: Use separate sseu init function
> drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK
> drm/i915/sseu: Simplify gen11+ SSEU handling
> drm/i915/sseu: Don't try to store EU mask internally in UAPI format
> drm/i915/sseu: Disassociate internal subslice mask representation from
> uapi
> drm/i915/pvc: Add SSEU changes
For the series:
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Almost r-b actually, but I do not feel completely comfortable that I
read everything closely enough to not have missed something. So I prefer
someone else does a really detailed pass to be sure.
Regards,
Tvrtko
>
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 12 +-
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_sseu.c | 450 ++++++++++++-------
> drivers/gpu/drm/i915/gt/intel_sseu.h | 94 ++--
> drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +-
> drivers/gpu/drm/i915/i915_drv.h | 2 +
> drivers/gpu/drm/i915/i915_getparam.c | 11 +-
> drivers/gpu/drm/i915/i915_pci.c | 3 +-
> drivers/gpu/drm/i915/i915_query.c | 26 +-
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> 13 files changed, 398 insertions(+), 265 deletions(-)
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for i915: SSEU handling updates (rev2)
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
` (16 preceding siblings ...)
(?)
@ 2022-05-24 16:12 ` Patchwork
-1 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2022-05-24 16:12 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
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== Series Details ==
Series: i915: SSEU handling updates (rev2)
URL : https://patchwork.freedesktop.org/series/104244/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11693_full -> Patchwork_104244v2_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (12 -> 13)
------------------------------
Additional (1): shard-rkl
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_104244v2_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_color@pipe-b-deep-color:
- {shard-rkl}: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-rkl-6/igt@kms_color@pipe-b-deep-color.html
Known issues
------------
Here are the changes found in Patchwork_104244v2_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-skl: ([PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21]) -> ([PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [FAIL][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43]) ([i915#5032])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl7/boot.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl6/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl6/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl5/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl5/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl4/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl4/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl2/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl2/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl1/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl1/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl10/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl10/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl10/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl9/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl9/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl8/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl8/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl8/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl7/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl9/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl9/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl9/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl9/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl8/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl8/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl8/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl7/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl7/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl6/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl6/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl4/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl4/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl3/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl3/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl3/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl2/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl2/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl1/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl1/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl10/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl10/boot.html
### IGT changes ###
#### Issues hit ####
* igt@api_intel_allocator@fork-simple-stress-signal:
- shard-iclb: [PASS][44] -> [DMESG-WARN][45] ([i915#4391])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb1/igt@api_intel_allocator@fork-simple-stress-signal.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb7/igt@api_intel_allocator@fork-simple-stress-signal.html
* igt@gem_create@create-massive:
- shard-skl: NOTRUN -> [DMESG-WARN][46] ([i915#4991])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl1/igt@gem_create@create-massive.html
* igt@gem_eio@in-flight-contexts-1us:
- shard-apl: NOTRUN -> [TIMEOUT][47] ([i915#3063])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl6/igt@gem_eio@in-flight-contexts-1us.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: NOTRUN -> [FAIL][48] ([i915#2846])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][49] -> [FAIL][50] ([i915#2842])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-tglb: NOTRUN -> [FAIL][51] ([i915#2842])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [PASS][52] -> [FAIL][53] ([i915#2842]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl6/igt@gem_exec_fair@basic-pace@rcs0.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl4/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_flush@basic-wb-rw-default:
- shard-snb: [PASS][54] -> [SKIP][55] ([fdo#109271]) +2 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-snb2/igt@gem_exec_flush@basic-wb-rw-default.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-snb6/igt@gem_exec_flush@basic-wb-rw-default.html
* igt@gem_lmem_swapping@basic:
- shard-tglb: NOTRUN -> [SKIP][56] ([i915#4613])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@random:
- shard-apl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#4613]) +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl3/igt@gem_lmem_swapping@random.html
* igt@gem_lmem_swapping@verify-random-ccs:
- shard-skl: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#4613]) +2 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl2/igt@gem_lmem_swapping@verify-random-ccs.html
* igt@gem_pxp@verify-pxp-stale-buf-optout-execution:
- shard-tglb: NOTRUN -> [SKIP][59] ([i915#4270])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][60] -> [DMESG-WARN][61] ([i915#5566] / [i915#716])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-apl1/igt@gen9_exec_parse@allowed-single.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl1/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc6-dpms:
- shard-skl: NOTRUN -> [FAIL][62] ([i915#454])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl8/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][63] -> [FAIL][64] ([i915#454])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-apl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#1937])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl6/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_selftest@live@dmabuf:
- shard-skl: [PASS][66] -> [INCOMPLETE][67] ([i915#6075])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl4/igt@i915_selftest@live@dmabuf.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl3/igt@i915_selftest@live@dmabuf.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][68] ([i915#5286])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][69] ([fdo#111614])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][70] ([i915#3743]) +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][71] ([i915#3763])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#3886]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl6/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#3886]) +5 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl8/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#3886])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk2/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][75] ([i915#3689] / [i915#3886])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][76] ([i915#3689])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_ccs.html
* igt@kms_ccs@pipe-d-random-ccs-data-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][77] ([fdo#111615] / [i915#3689])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_ccs@pipe-d-random-ccs-data-yf_tiled_ccs.html
* igt@kms_chamelium@hdmi-audio:
- shard-apl: NOTRUN -> [SKIP][78] ([fdo#109271] / [fdo#111827]) +8 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl6/igt@kms_chamelium@hdmi-audio.html
* igt@kms_color@pipe-c-deep-color:
- shard-tglb: NOTRUN -> [SKIP][79] ([i915#3555])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_color@pipe-c-deep-color.html
* igt@kms_color_chamelium@pipe-a-ctm-negative:
- shard-tglb: NOTRUN -> [SKIP][80] ([fdo#109284] / [fdo#111827])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_color_chamelium@pipe-a-ctm-negative.html
* igt@kms_color_chamelium@pipe-d-ctm-red-to-blue:
- shard-skl: NOTRUN -> [SKIP][81] ([fdo#109271] / [fdo#111827]) +9 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl8/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-d-degamma:
- shard-glk: NOTRUN -> [SKIP][82] ([fdo#109271] / [fdo#111827]) +1 similar issue
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk2/igt@kms_color_chamelium@pipe-d-degamma.html
* igt@kms_cursor_crc@pipe-a-cursor-32x10-sliding:
- shard-tglb: NOTRUN -> [SKIP][83] ([i915#3359])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_cursor_crc@pipe-a-cursor-32x10-sliding.html
* igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding:
- shard-tglb: NOTRUN -> [SKIP][84] ([fdo#109279] / [i915#3359]) +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
- shard-tglb: NOTRUN -> [SKIP][85] ([fdo#109274] / [fdo#111825])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-4tiled:
- shard-tglb: NOTRUN -> [SKIP][86] ([i915#5287])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-4tiled.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-tglb: NOTRUN -> [SKIP][87] ([fdo#109274] / [fdo#111825] / [i915#3966])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][88] -> [FAIL][89] ([i915#79])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [PASS][90] -> [FAIL][91] ([i915#2122])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-skl: [PASS][92] -> [FAIL][93] ([i915#79])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-edp1:
- shard-iclb: [PASS][94] -> [DMESG-WARN][95] ([i915#2867])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb1/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb7/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
- shard-iclb: [PASS][96] -> [SKIP][97] ([i915#3701])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
- shard-glk: [PASS][98] -> [FAIL][99] ([i915#4911])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-glk9/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
- shard-skl: NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#3701])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl4/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-tglb: NOTRUN -> [SKIP][101] ([fdo#109280] / [fdo#111825]) +3 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-apl: NOTRUN -> [SKIP][102] ([fdo#109271]) +91 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
- shard-glk: NOTRUN -> [SKIP][103] ([fdo#109271]) +24 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk2/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][104] ([fdo#109271] / [i915#533])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl6/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-apl: [PASS][105] -> [DMESG-WARN][106] ([i915#180]) +3 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-glk: NOTRUN -> [FAIL][107] ([fdo#108145] / [i915#265])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk2/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-skl: NOTRUN -> [FAIL][108] ([fdo#108145] / [i915#265]) +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
* igt@kms_plane_lowres@pipe-a-tiling-none:
- shard-tglb: NOTRUN -> [SKIP][109] ([i915#3536])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_plane_lowres@pipe-a-tiling-none.html
* igt@kms_plane_lowres@pipe-c-tiling-4:
- shard-tglb: NOTRUN -> [SKIP][110] ([i915#5288])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@kms_plane_lowres@pipe-c-tiling-4.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-edp-1-planes-upscale-downscale:
- shard-skl: NOTRUN -> [SKIP][111] ([fdo#109271]) +168 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl4/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-edp-1-planes-upscale-downscale.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-edp-1-planes-upscale-downscale:
- shard-iclb: [PASS][112] -> [SKIP][113] ([i915#5235]) +2 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb3/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-edp-1-planes-upscale-downscale.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-edp-1-planes-upscale-downscale.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-skl: NOTRUN -> [SKIP][114] ([fdo#109271] / [i915#658])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl2/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-glk: NOTRUN -> [SKIP][115] ([fdo#109271] / [i915#658]) +1 similar issue
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk2/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][116] -> [SKIP][117] ([fdo#109441]) +1 similar issue
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb4/igt@kms_psr@psr2_sprite_plane_move.html
* igt@nouveau_crc@ctx-flip-threshold-reset-after-capture:
- shard-tglb: NOTRUN -> [SKIP][118] ([i915#2530])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@nouveau_crc@ctx-flip-threshold-reset-after-capture.html
* igt@perf@stress-open-close:
- shard-glk: [PASS][119] -> [INCOMPLETE][120] ([i915#5213])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-glk2/igt@perf@stress-open-close.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk5/igt@perf@stress-open-close.html
* igt@prime_nv_api@i915_self_import_to_different_fd:
- shard-tglb: NOTRUN -> [SKIP][121] ([fdo#109291])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@prime_nv_api@i915_self_import_to_different_fd.html
* igt@sysfs_clients@fair-3:
- shard-glk: NOTRUN -> [SKIP][122] ([fdo#109271] / [i915#2994])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk2/igt@sysfs_clients@fair-3.html
* igt@sysfs_clients@fair-7:
- shard-apl: NOTRUN -> [SKIP][123] ([fdo#109271] / [i915#2994]) +1 similar issue
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl6/igt@sysfs_clients@fair-7.html
* igt@sysfs_clients@pidname:
- shard-tglb: NOTRUN -> [SKIP][124] ([i915#2994])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb7/igt@sysfs_clients@pidname.html
#### Possible fixes ####
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][125] ([i915#658]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb3/igt@feature_discovery@psr2.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-iclb: [TIMEOUT][127] ([i915#3070]) -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb3/igt@gem_eio@in-flight-contexts-10ms.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb2/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_eio@in-flight-immediate:
- shard-tglb: [TIMEOUT][129] ([i915#3063]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-tglb1/igt@gem_eio@in-flight-immediate.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-tglb6/igt@gem_eio@in-flight-immediate.html
* igt@gem_eio@reset-stress:
- shard-apl: [FAIL][131] -> [PASS][132]
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-apl2/igt@gem_eio@reset-stress.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl1/igt@gem_eio@reset-stress.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [FAIL][133] ([i915#2842]) -> [PASS][134]
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-apl4/igt@gem_exec_fair@basic-none@vecs0.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl3/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [FAIL][135] ([i915#2842]) -> [PASS][136]
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-glk3/igt@gem_exec_fair@basic-throttle@rcs0.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [DMESG-WARN][137] ([i915#5566] / [i915#716]) -> [PASS][138]
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-glk3/igt@gen9_exec_parse@allowed-single.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk2/igt@gen9_exec_parse@allowed-single.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [INCOMPLETE][139] ([i915#3921]) -> [PASS][140]
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-snb5/igt@i915_selftest@live@hangcheck.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-snb7/igt@i915_selftest@live@hangcheck.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@b-edp1:
- shard-skl: [FAIL][141] ([i915#2122]) -> [PASS][142]
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl2/igt@kms_flip@flip-vs-blocking-wf-vblank@b-edp1.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl9/igt@kms_flip@flip-vs-blocking-wf-vblank@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [FAIL][143] ([i915#79]) -> [PASS][144]
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1:
- shard-glk: [FAIL][145] ([i915#79]) -> [PASS][146]
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1:
- shard-kbl: [FAIL][147] ([i915#79]) -> [PASS][148]
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [DMESG-WARN][149] ([i915#180]) -> [PASS][150] +2 similar issues
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-kbl: [DMESG-WARN][151] ([i915#180]) -> [PASS][152]
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl7/igt@kms_flip@flip-vs-suspend@a-dp1.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl3/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale:
- shard-iclb: [SKIP][153] ([i915#5235]) -> [PASS][154] +2 similar issues
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb4/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][155] ([fdo#109441]) -> [PASS][156] +2 similar issues
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb3/igt@kms_psr@psr2_primary_mmap_cpu.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-iclb: [SKIP][157] ([i915#5519]) -> [PASS][158]
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb8/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb5/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
#### Warnings ####
* igt@kms_flip@flip-vs-suspend@b-dp1:
- shard-kbl: [DMESG-WARN][159] ([i915#180]) -> [INCOMPLETE][160] ([i915#3614])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl7/igt@kms_flip@flip-vs-suspend@b-dp1.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl3/igt@kms_flip@flip-vs-suspend@b-dp1.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-iclb: [SKIP][161] ([i915#658]) -> [SKIP][162] ([i915#2920])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb3/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-iclb: [SKIP][163] ([i915#2920]) -> [SKIP][164] ([i915#658])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-iclb4/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][165], [FAIL][166], [FAIL][167], [FAIL][168], [FAIL][169], [FAIL][170], [FAIL][171], [FAIL][172], [FAIL][173]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][174], [FAIL][175], [FAIL][176], [FAIL][177], [FAIL][178], [FAIL][179], [FAIL][180], [FAIL][181]) ([i915#3002] / [i915#4312] / [i915#5257])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl1/igt@runner@aborted.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl7/igt@runner@aborted.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl7/igt@runner@aborted.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl7/igt@runner@aborted.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl6/igt@runner@aborted.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl4/igt@runner@aborted.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl4/igt@runner@aborted.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl1/igt@runner@aborted.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-kbl1/igt@runner@aborted.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl6/igt@runner@aborted.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl7/igt@runner@aborted.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl4/igt@runner@aborted.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl7/igt@runner@aborted.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl1/igt@runner@aborted.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl6/igt@runner@aborted.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl1/igt@runner@aborted.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-kbl7/igt@runner@aborted.html
- shard-skl: ([FAIL][182], [FAIL][183], [FAIL][184], [FAIL][185]) ([i915#2029] / [i915#4312] / [i915#5257]) -> ([FAIL][186], [FAIL][187], [FAIL][188]) ([i915#3002] / [i915#4312] / [i915#5257])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl2/igt@runner@aborted.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl5/igt@runner@aborted.html
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl6/igt@runner@aborted.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/shard-skl8/igt@runner@aborted.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl9/igt@runner@aborted.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl1/igt@runner@aborted.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl9/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110254]: https://bugs.freedesktop.org/show_bug.cgi?id=110254
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3376]: https://gitlab.freedesktop.org/drm/intel/issues/3376
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3614]: https://gitlab.freedesktop.org/drm/intel/issues/3614
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3639]: https://gitlab.freedesktop.org/drm/intel/issues/3639
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3763]: https://gitlab.freedesktop.org/drm/intel/issues/3763
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3828]: https://gitlab.freedesktop.org/drm/intel/issues/3828
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4241]: https://gitlab.freedesktop.org/drm/intel/issues/4241
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4883]: https://gitlab.freedesktop.org/drm/intel/issues/4883
[i915#4911]: https://gitlab.freedesktop.org/drm/intel/issues/4911
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5032]: https://gitlab.freedesktop.org/drm/intel/issues/5032
[i915#5098]: https://gitlab.freedesktop.org/drm/intel/issues/5098
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5182]: https://gitlab.freedesktop.org/drm/intel/issues/5182
[i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
[i915#5721]: https://gitlab.freedesktop.org/drm/intel/issues/5721
[i915#6075]: https://gitlab.freedesktop.org/drm/intel/issues/6075
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_11693 -> Patchwork_104244v2
CI-20190529: 20190529
CI_DRM_11693: 14289bc81309b2126f4ba9f339837dacf34ddf9c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6485: 51663917b40d36086cc1c555ce4f67b22937694d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_104244v2: 14289bc81309b2126f4ba9f339837dacf34ddf9c @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/index.html
[-- Attachment #2: Type: text/html, Size: 47464 bytes --]
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: SSEU handling updates (rev2)
2022-05-23 23:31 ` Matt Roper
@ 2022-05-24 16:20 ` Vudum, Lakshminarayana
0 siblings, 0 replies; 36+ messages in thread
From: Vudum, Lakshminarayana @ 2022-05-24 16:20 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx
CI: boot test failure seems to fail always in the same manner.
https://gitlab.freedesktop.org/drm/intel/-/issues/6074
BDW: CI:Boot - fail - No warnings/errors
I believe the shards failures is unrelated (as there no logs) to this patch. So I created a generic bug for GEN9 to track of failures that doesn't have logs. This bug will be reviewed weekly by the team.
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/shard-skl3/igt@i915_selftest@live@dmabuf.html
https://gitlab.freedesktop.org/drm/intel/-/issues/6075
Thanks,
Lakshmi.
-----Original Message-----
From: Roper, Matthew D <matthew.d.roper@intel.com>
Sent: Monday, May 23, 2022 4:32 PM
To: intel-gfx@lists.freedesktop.org
Cc: Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>
Subject: Re: ✗ Fi.CI.BAT: failure for i915: SSEU handling updates (rev2)
On Mon, May 23, 2022 at 09:23:33PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: i915: SSEU handling updates (rev2)
> URL : https://patchwork.freedesktop.org/series/104244/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11693 -> Patchwork_104244v2
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_104244v2 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_104244v2, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/index.html
>
> Participating hosts (44 -> 45)
> ------------------------------
>
> Additional (2): fi-icl-u2 fi-tgl-u2
> Missing (1): fi-hsw-4770
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_104244v2:
>
> ### CI changes ###
>
> #### Possible regressions ####
>
> * boot:
> - fi-bdw-5557u: [PASS][1] -> [FAIL][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/fi-bdw-5557u/boot.html
> [2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-bdw-555
> 7u/boot.html
I don't see a boot failure here? It looks like i915 loaded successfully, without errors. It also looks like more tests ran successfully on the machine after that as well.
Matt
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_104244v2 that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_exec_gttfill@basic:
> - fi-icl-u2: NOTRUN -> [INCOMPLETE][3] ([i915#4890])
> [3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-icl-u2/
> igt@gem_exec_gttfill@basic.html
>
> * igt@gem_huc_copy@huc-copy:
> - fi-tgl-u2: NOTRUN -> [SKIP][4] ([i915#2190])
> [4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/
> igt@gem_huc_copy@huc-copy.html
>
> * igt@i915_selftest@live@hangcheck:
> - bat-dg1-6: [PASS][5] -> [DMESG-FAIL][6] ([i915#4494] / [i915#4957])
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
> - fi-snb-2600: [PASS][7] -> [INCOMPLETE][8] ([i915#3921])
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
> [8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-snb-260
> 0/igt@i915_selftest@live@hangcheck.html
>
> * igt@kms_busy@basic@flip:
> - fi-tgl-u2: NOTRUN -> [DMESG-WARN][9] ([i915#402]) +3 similar issues
> [9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/
> igt@kms_busy@basic@flip.html
>
> * igt@kms_chamelium@dp-hpd-fast:
> - fi-tgl-u2: NOTRUN -> [SKIP][10] ([fdo#109284] / [fdo#111827]) +7 similar issues
> [10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/
> igt@kms_chamelium@dp-hpd-fast.html
>
> * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
> - fi-tgl-u2: NOTRUN -> [SKIP][11] ([i915#4103]) +1 similar issue
> [11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/
> igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
>
> * igt@kms_flip@basic-flip-vs-modeset@b-edp1:
> - bat-adlp-4: [PASS][12] -> [DMESG-WARN][13] ([i915#3576])
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html
> [13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/bat-adlp-4
> /igt@kms_flip@basic-flip-vs-modeset@b-edp1.html
>
> * igt@kms_force_connector_basic@force-load-detect:
> - fi-tgl-u2: NOTRUN -> [SKIP][14] ([fdo#109285])
> [14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/
> igt@kms_force_connector_basic@force-load-detect.html
>
> * igt@kms_setmode@basic-clone-single-crtc:
> - fi-tgl-u2: NOTRUN -> [SKIP][15] ([i915#3555])
> [15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/
> igt@kms_setmode@basic-clone-single-crtc.html
>
> * igt@prime_vgem@basic-userptr:
> - fi-tgl-u2: NOTRUN -> [SKIP][16] ([i915#3301])
> [16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-tgl-u2/
> igt@prime_vgem@basic-userptr.html
>
> * igt@runner@aborted:
> - fi-icl-u2: NOTRUN -> [FAIL][17] ([i915#4312])
> [17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-icl-u2/
> igt@runner@aborted.html
>
>
> #### Possible fixes ####
>
> * igt@gem_exec_suspend@basic-s0@smem:
> - {fi-ehl-2}: [DMESG-WARN][18] ([i915#5122]) -> [PASS][19]
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html
> [19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/fi-ehl-2/i
> gt@gem_exec_suspend@basic-s0@smem.html
>
> * igt@kms_flip@basic-plain-flip@a-edp1:
> - bat-adlp-4: [DMESG-WARN][20] ([i915#3576]) -> [PASS][21] +2 similar issues
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11693/bat-adlp-4/igt@kms_flip@basic-plain-flip@a-edp1.html
> [21]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/bat-adlp-4
> /igt@kms_flip@basic-plain-flip@a-edp1.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
> [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
> [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
> [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
> [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
> [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
> [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
> [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
> [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
> [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
> [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
> [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
> [i915#4890]: https://gitlab.freedesktop.org/drm/intel/issues/4890
> [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
> [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_11693 -> Patchwork_104244v2
>
> CI-20190529: 20190529
> CI_DRM_11693: 14289bc81309b2126f4ba9f339837dacf34ddf9c @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6485: 51663917b40d36086cc1c555ce4f67b22937694d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_104244v2: 14289bc81309b2126f4ba9f339837dacf34ddf9c @
> git://anongit.freedesktop.org/gfx-ci/linux
>
>
> ### Linux commits
>
> e3100146e9db drm/i915/pvc: Add SSEU changes
> 920dde2397e4 drm/i915/sseu: Disassociate internal subslice mask
> representation from uapi
> 67224fa58023 drm/i915/sseu: Don't try to store EU mask internally in
> UAPI format
> ec3d320f5b49 drm/i915/sseu: Simplify gen11+ SSEU handling
> f00314dcab14 drm/i915/xehp: Drop GETPARAM lookups of
> I915_PARAM_[SUB]SLICE_MASK 5edcd0a4da5f drm/i915/xehp: Use separate
> sseu init function
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104244v2/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v5 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi
2022-05-23 20:45 ` [Intel-gfx] " Matt Roper
@ 2022-06-01 8:18 ` Balasubramani Vivekanandan
-1 siblings, 0 replies; 36+ messages in thread
From: Balasubramani Vivekanandan @ 2022-06-01 8:18 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: Tvrtko Ursulin, dri-devel
On 23.05.2022 13:45, Matt Roper wrote:
> As with EU masks, it's easier to store subslice/DSS masks internally in
> a format that's more natural for the driver to work with, and then only
> covert into the u8[] uapi form when the query ioctl is invoked. Since
> the hardware design changed significantly with Xe_HP, we'll use a union
> to choose between the old "hsw-style" subslice masks or the newer xehp
> mask. HSW-style masks will be stored in an array of u8's, indexed by
> slice (there's never more than 6 subslices per slice on older
> platforms). For Xe_HP and beyond where slices no longer exist, we only
> need a single bitmask. However we already know that this mask is
> eventually going to grow too large for a simple u64 to hold, so we'll
> represent it in a manner that can be operated on by the utilities in
> linux/bitmap.h.
>
> v2:
> - Fix typo: BIT(s) -> BIT(ss) in gen9_sseu_device_status()
>
> v3:
> - Eliminate sseu->ss_stride and just calculate the stride while
> specifically handling uapi. (Tvrtko)
> - Use BITMAP_BITS() macro to refer to size of masks rather than
> passing I915_MAX_SS_FUSE_BITS directly. (Tvrtko)
> - Report compute/geometry DSS masks separately when dumping Xe_HP SSEU
> info. (Tvrtko)
> - Restore dropped range checks to intel_sseu_has_subslice(). (Tvrtko)
>
> v4:
> - Make the bitmap size macro check the size of the .xehp field rather
> than the containing union. (Tvrtko)
> - Don't add GEM_BUG_ON() intel_sseu_has_subslice()'s check for whether
> slice or subslice ID exceed sseu->max_[sub]slices; various loops
> in the driver are expected to exceed these, so we should just
> silently return 'false.'
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 12 +-
> drivers/gpu/drm/i915/gt/intel_sseu.c | 261 +++++++++++--------
> drivers/gpu/drm/i915/gt/intel_sseu.h | 76 ++++--
> drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +--
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +-
> drivers/gpu/drm/i915/i915_getparam.c | 3 +-
> drivers/gpu/drm/i915/i915_query.c | 13 +-
> 9 files changed, 241 insertions(+), 187 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index ab4c5ab28e4d..a3bb73f5d53b 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -1875,6 +1875,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> {
> const struct sseu_dev_info *device = >->info.sseu;
> struct drm_i915_private *i915 = gt->i915;
> + unsigned int dev_subslice_mask = intel_sseu_get_hsw_subslices(device, 0);
>
> /* No zeros in any field. */
> if (!user->slice_mask || !user->subslice_mask ||
> @@ -1901,7 +1902,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> if (user->slice_mask & ~device->slice_mask)
> return -EINVAL;
>
> - if (user->subslice_mask & ~device->subslice_mask[0])
> + if (user->subslice_mask & ~dev_subslice_mask)
> return -EINVAL;
>
> if (user->max_eus_per_subslice > device->max_eus_per_subslice)
> @@ -1915,7 +1916,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> /* Part specific restrictions. */
> if (GRAPHICS_VER(i915) == 11) {
> unsigned int hw_s = hweight8(device->slice_mask);
> - unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
> + unsigned int hw_ss_per_s = hweight8(dev_subslice_mask);
> unsigned int req_s = hweight8(context->slice_mask);
> unsigned int req_ss = hweight8(context->subslice_mask);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 1adbf34c3632..f0acf8518a51 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -674,8 +674,8 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
> if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> return;
>
> - ccs_mask = intel_slicemask_from_dssmask(intel_sseu_get_compute_subslices(&info->sseu),
> - ss_per_ccs);
> + ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
> + ss_per_ccs);
> /*
> * If all DSS in a quadrant are fused off, the corresponding CCS
> * engine is not available for use.
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 034182f85501..2921f510642f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -133,13 +133,6 @@ static const struct intel_mmio_range dg2_lncf_steering_table[] = {
> {},
> };
>
> -static u16 slicemask(struct intel_gt *gt, int count)
> -{
> - u64 dss_mask = intel_sseu_get_subslices(>->info.sseu, 0);
> -
> - return intel_slicemask_from_dssmask(dss_mask, count);
> -}
> -
> int intel_gt_init_mmio(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> @@ -155,9 +148,12 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> */
> if (HAS_MSLICES(i915)) {
> gt->info.mslice_mask =
> - slicemask(gt, GEN_DSS_PER_MSLICE) |
> + intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
> + GEN_DSS_PER_MSLICE);
> + gt->info.mslice_mask |=
> (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> GEN12_MEML3_EN_MASK);
> +
> if (!gt->info.mslice_mask) /* should be impossible! */
> drm_warn(&i915->drm, "mslice mask all zero!\n");
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index 285cfd758bdc..3a721db20290 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -10,15 +10,14 @@
> #include "intel_gt_regs.h"
> #include "intel_sseu.h"
>
> +#define XEHP_BITMAP_BITS(mask) ((int)BITS_PER_TYPE(typeof(mask.xehp)))
> +
> void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
> u8 max_subslices, u8 max_eus_per_subslice)
> {
> sseu->max_slices = max_slices;
> sseu->max_subslices = max_subslices;
> sseu->max_eus_per_subslice = max_eus_per_subslice;
> -
> - sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
> - GEM_BUG_ON(sseu->ss_stride > GEN_MAX_SUBSLICE_STRIDE);
> }
>
> unsigned int
> @@ -26,54 +25,24 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
> {
> unsigned int i, total = 0;
>
> - for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
> - total += hweight8(sseu->subslice_mask[i]);
> -
> - return total;
> -}
> -
> -static u32
> -sseu_get_subslices(const struct sseu_dev_info *sseu,
> - const u8 *subslice_mask, u8 slice)
> -{
> - int i, offset = slice * sseu->ss_stride;
> - u32 mask = 0;
> -
> - GEM_BUG_ON(slice >= sseu->max_slices);
> -
> - for (i = 0; i < sseu->ss_stride; i++)
> - mask |= (u32)subslice_mask[offset + i] << i * BITS_PER_BYTE;
> -
> - return mask;
> -}
> -
> -u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
> -{
> - return sseu_get_subslices(sseu, sseu->subslice_mask, slice);
> -}
> + if (sseu->has_xehp_dss)
> + return bitmap_weight(sseu->subslice_mask.xehp,
> + XEHP_BITMAP_BITS(sseu->subslice_mask));
>
> -static u32 sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
> -{
> - return sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
> -}
> + for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++)
> + total += hweight8(sseu->subslice_mask.hsw[i]);
>
> -u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu)
> -{
> - return sseu_get_subslices(sseu, sseu->compute_subslice_mask, 0);
> -}
> -
> -void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
> - u8 *subslice_mask, u32 ss_mask)
> -{
> - int offset = slice * sseu->ss_stride;
> -
> - memcpy(&subslice_mask[offset], &ss_mask, sseu->ss_stride);
> + return total;
> }
>
> unsigned int
> -intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
> +intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice)
> {
> - return hweight32(intel_sseu_get_subslices(sseu, slice));
> + WARN_ON(sseu->has_xehp_dss);
> + if (WARN_ON(slice >= sseu->max_slices))
> + return 0;
> +
> + return sseu->subslice_mask.hsw[slice];
> }
>
> static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
> @@ -147,32 +116,66 @@ int intel_sseu_copy_eumask_to_user(void __user *to,
> return copy_to_user(to, eu_mask, len);
> }
>
> +/**
> + * intel_sseu_copy_ssmask_to_user - Copy subslice mask into a userspace buffer
> + * @to: Pointer to userspace buffer to copy to
> + * @sseu: SSEU structure containing subslice mask to copy
> + *
> + * Copies the subslice mask to a userspace buffer in the format expected by
> + * the query ioctl's topology queries.
> + *
> + * Returns the result of the copy_to_user() operation.
> + */
> +int intel_sseu_copy_ssmask_to_user(void __user *to,
> + const struct sseu_dev_info *sseu)
> +{
> + u8 ss_mask[GEN_SS_MASK_SIZE] = {};
> + int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
> + int len = sseu->max_slices * ss_stride;
> + int s, ss, i;
> +
> + for (s = 0; s < sseu->max_slices; s++) {
> + for (ss = 0; ss < sseu->max_subslices; ss++) {
> + i = s * ss_stride * BITS_PER_BYTE + ss;
> +
> + if (!intel_sseu_has_subslice(sseu, s, ss))
> + continue;
> +
> + ss_mask[i / BITS_PER_BYTE] |= BIT(i % BITS_PER_BYTE);
> + }
> + }
> +
> + return copy_to_user(to, ss_mask, len);
> +}
> +
> static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> - u32 g_ss_en, u32 c_ss_en, u16 eu_en)
> + u32 ss_en, u16 eu_en)
> {
> u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
> int ss;
>
> - /* g_ss_en/c_ss_en represent entire subslice mask across all slices */
> - GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
> - sizeof(g_ss_en) * BITS_PER_BYTE);
> + sseu->slice_mask |= BIT(0);
> + sseu->subslice_mask.hsw[0] = ss_en & valid_ss_mask;
> +
> + for (ss = 0; ss < sseu->max_subslices; ss++)
> + if (intel_sseu_has_subslice(sseu, 0, ss))
> + sseu_set_eus(sseu, 0, ss, eu_en);
> +
> + sseu->eu_per_subslice = hweight16(eu_en);
> + sseu->eu_total = compute_eu_total(sseu);
> +}
> +
> +static void xehp_compute_sseu_info(struct sseu_dev_info *sseu,
> + u16 eu_en)
> +{
> + int ss;
>
> sseu->slice_mask |= BIT(0);
>
> - /*
> - * XeHP introduces the concept of compute vs geometry DSS. To reduce
> - * variation between GENs around subslice usage, store a mask for both
> - * the geometry and compute enabled masks since userspace will need to
> - * be able to query these masks independently. Also compute a total
> - * enabled subslice count for the purposes of selecting subslices to
> - * use in a particular GEM context.
> - */
> - intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
> - c_ss_en & valid_ss_mask);
> - intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
> - g_ss_en & valid_ss_mask);
> - intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
> - (g_ss_en | c_ss_en) & valid_ss_mask);
> + bitmap_or(sseu->subslice_mask.xehp,
> + sseu->compute_subslice_mask.xehp,
> + sseu->geometry_subslice_mask.xehp,
> + XEHP_BITMAP_BITS(sseu->subslice_mask));
>
> for (ss = 0; ss < sseu->max_subslices; ss++)
> if (intel_sseu_has_subslice(sseu, 0, ss))
> @@ -182,11 +185,31 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> sseu->eu_total = compute_eu_total(sseu);
> }
>
> +static void
> +xehp_load_dss_mask(struct intel_uncore *uncore,
> + intel_sseu_ss_mask_t *ssmask,
> + int numregs,
> + ...)
> +{
> + va_list argp;
> + u32 fuse_val[I915_MAX_SS_FUSE_REGS] = {};
> + int i;
> +
> + if (WARN_ON(numregs > I915_MAX_SS_FUSE_REGS))
> + numregs = I915_MAX_SS_FUSE_REGS;
> +
> + va_start(argp, numregs);
> + for (i = 0; i < numregs; i++)
> + fuse_val[i] = intel_uncore_read(uncore, va_arg(argp, i915_reg_t));
> + va_end(argp);
> +
> + bitmap_from_arr32(ssmask->xehp, fuse_val, numregs * 32);
> +}
> +
> static void xehp_sseu_info_init(struct intel_gt *gt)
> {
> struct sseu_dev_info *sseu = >->info.sseu;
> struct intel_uncore *uncore = gt->uncore;
> - u32 g_dss_en, c_dss_en = 0;
> u16 eu_en = 0;
> u8 eu_en_fuse;
> int eu;
> @@ -200,8 +223,10 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
> intel_sseu_set_info(sseu, 1, 32, 16);
> sseu->has_xehp_dss = 1;
>
> - g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
> - c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
> + xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 1,
> + GEN12_GT_GEOMETRY_DSS_ENABLE);
> + xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 1,
> + GEN12_GT_COMPUTE_DSS_ENABLE);
>
> eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
>
> @@ -209,7 +234,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
> if (eu_en_fuse & BIT(eu))
> eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
>
> - gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
> + xehp_compute_sseu_info(sseu, eu_en);
> }
>
> static void gen12_sseu_info_init(struct intel_gt *gt)
> @@ -247,7 +272,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
> if (eu_en_fuse & BIT(eu))
> eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
>
> - gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
> + gen11_compute_sseu_info(sseu, g_dss_en, eu_en);
>
> /* TGL only supports slice-level power gating */
> sseu->has_slice_pg = 1;
> @@ -279,7 +304,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
> eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
> GEN11_EU_DIS_MASK);
>
> - gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
> + gen11_compute_sseu_info(sseu, ss_en, eu_en);
>
> /* ICL has no power gating restrictions. */
> sseu->has_slice_pg = 1;
> @@ -291,7 +316,6 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> {
> struct sseu_dev_info *sseu = >->info.sseu;
> u32 fuse;
> - u8 subslice_mask = 0;
>
> fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT);
>
> @@ -305,7 +329,7 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
> CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
>
> - subslice_mask |= BIT(0);
> + sseu->subslice_mask.hsw[0] |= BIT(0);
> sseu_set_eus(sseu, 0, 0, ~disabled_mask & 0xFF);
> }
>
> @@ -316,12 +340,10 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
> CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
>
> - subslice_mask |= BIT(1);
> + sseu->subslice_mask.hsw[0] |= BIT(1);
> sseu_set_eus(sseu, 0, 1, ~disabled_mask & 0xFF);
> }
>
> - intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask, subslice_mask);
> -
> sseu->eu_total = compute_eu_total(sseu);
>
> /*
> @@ -376,8 +398,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
> /* skip disabled slice */
> continue;
>
> - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> - subslice_mask);
> + sseu->subslice_mask.hsw[s] = subslice_mask;
>
> eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> @@ -434,8 +455,8 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
> sseu->has_eu_pg = sseu->eu_per_subslice > 2;
>
> if (IS_GEN9_LP(i915)) {
> -#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
> - info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
> +#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask.hsw[0] & BIT(ss)))
> + info->has_pooled_eu = hweight8(sseu->subslice_mask.hsw[0]) == 3;
>
> sseu->min_eu_in_pool = 0;
> if (info->has_pooled_eu) {
> @@ -489,8 +510,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
> /* skip disabled slice */
> continue;
>
> - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> - subslice_mask);
> + sseu->subslice_mask.hsw[s] = subslice_mask;
>
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> u8 eu_disabled_mask;
> @@ -587,8 +607,7 @@ static void hsw_sseu_info_init(struct intel_gt *gt)
> sseu->eu_per_subslice);
>
> for (s = 0; s < sseu->max_slices; s++) {
> - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> - subslice_mask);
> + sseu->subslice_mask.hsw[s] = subslice_mask;
>
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> sseu_set_eus(sseu, s, ss,
> @@ -677,7 +696,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
> */
> if (GRAPHICS_VER(i915) == 11 &&
> slices == 1 &&
> - subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
> + subslices > min_t(u8, 4, hweight8(sseu->subslice_mask.hsw[0]) / 2)) {
> GEM_BUG_ON(subslices & 1);
>
> subslice_pg = false;
> @@ -743,14 +762,29 @@ void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
> {
> int s;
>
> - drm_printf(p, "slice total: %u, mask=%04x\n",
> - hweight8(sseu->slice_mask), sseu->slice_mask);
> - drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
> - for (s = 0; s < sseu->max_slices; s++) {
> - drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
> - s, intel_sseu_subslices_per_slice(sseu, s),
> - intel_sseu_get_subslices(sseu, s));
> + if (sseu->has_xehp_dss) {
> + drm_printf(p, "subslice total: %u\n",
> + intel_sseu_subslice_total(sseu));
> + drm_printf(p, "geometry dss mask=%*pb\n",
> + XEHP_BITMAP_BITS(sseu->geometry_subslice_mask),
> + sseu->geometry_subslice_mask.xehp);
> + drm_printf(p, "compute dss mask=%*pb\n",
> + XEHP_BITMAP_BITS(sseu->compute_subslice_mask),
> + sseu->compute_subslice_mask.xehp);
> + } else {
> + drm_printf(p, "slice total: %u, mask=%04x\n",
> + hweight8(sseu->slice_mask), sseu->slice_mask);
> + drm_printf(p, "subslice total: %u\n",
> + intel_sseu_subslice_total(sseu));
> +
> + for (s = 0; s < sseu->max_slices; s++) {
> + u8 ss_mask = sseu->subslice_mask.hsw[s];
> +
> + drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
> + s, hweight8(ss_mask), ss_mask);
> + }
> }
> +
> drm_printf(p, "EU total: %u\n", sseu->eu_total);
> drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
> drm_printf(p, "has slice power gating: %s\n",
> @@ -767,9 +801,10 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
> int s, ss;
>
> for (s = 0; s < sseu->max_slices; s++) {
> + u8 ss_mask = sseu->subslice_mask.hsw[s];
> +
> drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
> - s, intel_sseu_subslices_per_slice(sseu, s),
> - intel_sseu_get_subslices(sseu, s));
> + s, hweight8(ss_mask), ss_mask);
>
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> u16 enabled_eus = sseu_get_eus(sseu, s, ss);
> @@ -783,16 +818,14 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
> static void sseu_print_xehp_topology(const struct sseu_dev_info *sseu,
> struct drm_printer *p)
> {
> - u32 g_dss_mask = sseu_get_geometry_subslices(sseu);
> - u32 c_dss_mask = intel_sseu_get_compute_subslices(sseu);
> int dss;
>
> for (dss = 0; dss < sseu->max_subslices; dss++) {
> u16 enabled_eus = sseu_get_eus(sseu, 0, dss);
>
> drm_printf(p, "DSS_%02d: G:%3s C:%3s, %2u EUs (0x%04hx)\n", dss,
> - str_yes_no(g_dss_mask & BIT(dss)),
> - str_yes_no(c_dss_mask & BIT(dss)),
> + str_yes_no(test_bit(dss, sseu->geometry_subslice_mask.xehp)),
> + str_yes_no(test_bit(dss, sseu->compute_subslice_mask.xehp)),
> hweight16(enabled_eus), enabled_eus);
> }
> }
> @@ -810,20 +843,44 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
> }
> }
>
> -u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice)
> +void intel_sseu_print_ss_info(const char* type,
> + const struct sseu_dev_info *sseu,
> + struct seq_file *m)
> +{
> + int s;
> +
> + if (sseu->has_xehp_dss) {
> + seq_printf(m, " %s Geometry DSS: %u\n", type,
> + bitmap_weight(sseu->geometry_subslice_mask.xehp,
> + XEHP_BITMAP_BITS(sseu->geometry_subslice_mask)));
> + seq_printf(m, " %s Compute DSS: %u\n", type,
> + bitmap_weight(sseu->compute_subslice_mask.xehp,
> + XEHP_BITMAP_BITS(sseu->compute_subslice_mask)));
> + } else {
> + for (s = 0; s < fls(sseu->slice_mask); s++)
> + seq_printf(m, " %s Slice%i subslices: %u\n", type,
> + s, hweight8(sseu->subslice_mask.hsw[s]));
> + }
> +}
> +
> +u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask,
> + int dss_per_slice)
> {
> + intel_sseu_ss_mask_t per_slice_mask = {};
> u16 slice_mask = 0;
> int i;
>
> - WARN_ON(sizeof(dss_mask) * 8 / dss_per_slice > 8 * sizeof(slice_mask));
> + WARN_ON(DIV_ROUND_UP(XEHP_BITMAP_BITS(dss_mask), dss_per_slice) >
> + 8 * sizeof(slice_mask));
>
> - for (i = 0; dss_mask; i++) {
> - if (dss_mask & GENMASK(dss_per_slice - 1, 0))
> + bitmap_fill(per_slice_mask.xehp, dss_per_slice);
> + for (i = 0; !bitmap_empty(dss_mask.xehp, XEHP_BITMAP_BITS(dss_mask)); i++) {
> + if (bitmap_intersects(dss_mask.xehp, per_slice_mask.xehp, dss_per_slice))
> slice_mask |= BIT(i);
>
> - dss_mask >>= dss_per_slice;
> + bitmap_shift_right(dss_mask.xehp, dss_mask.xehp, dss_per_slice,
> + XEHP_BITMAP_BITS(dss_mask));
> }
>
> return slice_mask;
> }
> -
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
> index ffa375e68959..e7f336a7ffbb 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> @@ -25,12 +25,16 @@ struct drm_printer;
> /*
> * Maximum number of subslices that can exist within a HSW-style slice. This
> * is only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the
> - * GEN_MAX_DSS value below).
> + * I915_MAX_SS_FUSE_BITS value below).
> */
> #define GEN_MAX_SS_PER_HSW_SLICE 6
>
> -/* Maximum number of DSS on newer platforms (Xe_HP and beyond). */
> -#define GEN_MAX_DSS 32
> +/*
> + * Maximum number of 32-bit registers used by hardware to express the
> + * enabled/disabled subslices.
> + */
> +#define I915_MAX_SS_FUSE_REGS 1
> +#define I915_MAX_SS_FUSE_BITS (I915_MAX_SS_FUSE_REGS * 32)
>
> /* Maximum number of EUs that can exist within a subslice or DSS. */
> #define GEN_MAX_EUS_PER_SS 16
> @@ -38,7 +42,7 @@ struct drm_printer;
> #define SSEU_MAX(a, b) ((a) > (b) ? (a) : (b))
>
> /* The maximum number of bits needed to express each subslice/DSS independently */
> -#define GEN_SS_MASK_SIZE SSEU_MAX(GEN_MAX_DSS, \
> +#define GEN_SS_MASK_SIZE SSEU_MAX(I915_MAX_SS_FUSE_BITS, \
> GEN_MAX_HSW_SLICES * GEN_MAX_SS_PER_HSW_SLICE)
>
> #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
> @@ -49,17 +53,24 @@ struct drm_printer;
> #define GEN_DSS_PER_CSLICE 8
> #define GEN_DSS_PER_MSLICE 8
>
> -#define GEN_MAX_GSLICES (GEN_MAX_DSS / GEN_DSS_PER_GSLICE)
> -#define GEN_MAX_CSLICES (GEN_MAX_DSS / GEN_DSS_PER_CSLICE)
> +#define GEN_MAX_GSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_GSLICE)
> +#define GEN_MAX_CSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_CSLICE)
> +
> +typedef union {
> + u8 hsw[GEN_MAX_HSW_SLICES];
> +
> + /* Bitmap compatible with linux/bitmap.h; may exceed size of u64 */
> + unsigned long xehp[BITS_TO_LONGS(I915_MAX_SS_FUSE_BITS)];
> +} intel_sseu_ss_mask_t;
>
> struct sseu_dev_info {
> u8 slice_mask;
> - u8 subslice_mask[GEN_SS_MASK_SIZE];
> - u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
> - u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
> + intel_sseu_ss_mask_t subslice_mask;
> + intel_sseu_ss_mask_t geometry_subslice_mask;
> + intel_sseu_ss_mask_t compute_subslice_mask;
> union {
> u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
> - u16 xehp[GEN_MAX_DSS];
> + u16 xehp[I915_MAX_SS_FUSE_BITS];
> } eu_mask;
>
> u16 eu_total;
> @@ -80,8 +91,6 @@ struct sseu_dev_info {
> u8 max_slices;
> u8 max_subslices;
> u8 max_eus_per_subslice;
> -
> - u8 ss_stride;
> };
>
> /*
> @@ -99,7 +108,7 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
> {
> struct intel_sseu value = {
> .slice_mask = sseu->slice_mask,
> - .subslice_mask = sseu->subslice_mask[0],
> + .subslice_mask = sseu->subslice_mask.hsw[0],
> .min_eus_per_subslice = sseu->max_eus_per_subslice,
> .max_eus_per_subslice = sseu->max_eus_per_subslice,
> };
> @@ -111,18 +120,27 @@ static inline bool
> intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
> int subslice)
> {
> - u8 mask;
> - int ss_idx = subslice / BITS_PER_BYTE;
> -
> if (slice >= sseu->max_slices ||
> subslice >= sseu->max_subslices)
> return false;
>
> - GEM_BUG_ON(ss_idx >= sseu->ss_stride);
> -
> - mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx];
> + if (sseu->has_xehp_dss)
> + return test_bit(subslice, sseu->subslice_mask.xehp);
> + else
> + return sseu->subslice_mask.hsw[slice] & BIT(subslice);
> +}
>
> - return mask & BIT(subslice % BITS_PER_BYTE);
> +/*
> + * Used to obtain the index of the first DSS. Can start searching from the
> + * beginning of a specific dss group (e.g., gslice, cslice, etc.) if
> + * groupsize and groupnum are non-zero.
> + */
> +static inline unsigned int
> +intel_sseu_find_first_xehp_dss(const struct sseu_dev_info *sseu, int groupsize,
> + int groupnum)
> +{
> + return find_next_bit(sseu->subslice_mask.xehp, I915_MAX_SS_FUSE_BITS,
> + groupnum * groupsize);
Any specific reason for not replacing I915_MAX_SS_FUSE_BITS with
XEHP_BITMAP_BITS here?
Regards,
Bala
> }
>
> void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
> @@ -132,14 +150,10 @@ unsigned int
> intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
>
> unsigned int
> -intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
> -
> -u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
> +intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice);
>
> -u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
> -
> -void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
> - u8 *subslice_mask, u32 ss_mask);
> +intel_sseu_ss_mask_t
> +intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
>
> void intel_sseu_info_init(struct intel_gt *gt);
>
> @@ -151,9 +165,15 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
> const struct sseu_dev_info *sseu,
> struct drm_printer *p);
>
> -u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
> +u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask, int dss_per_slice);
>
> int intel_sseu_copy_eumask_to_user(void __user *to,
> const struct sseu_dev_info *sseu);
> +int intel_sseu_copy_ssmask_to_user(void __user *to,
> + const struct sseu_dev_info *sseu);
> +
> +void intel_sseu_print_ss_info(const char* type,
> + const struct sseu_dev_info *sseu,
> + struct seq_file *m);
>
> #endif /* __INTEL_SSEU_H__ */
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> index 2d5d011e01db..c2ee5e1826b5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> @@ -4,6 +4,7 @@
> * Copyright © 2020 Intel Corporation
> */
>
> +#include <linux/bitmap.h>
> #include <linux/string_helpers.h>
>
> #include "i915_drv.h"
> @@ -11,14 +12,6 @@
> #include "intel_gt_regs.h"
> #include "intel_sseu_debugfs.h"
>
> -static void sseu_copy_subslices(const struct sseu_dev_info *sseu,
> - int slice, u8 *to_mask)
> -{
> - int offset = slice * sseu->ss_stride;
> -
> - memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
> -}
> -
> static void cherryview_sseu_device_status(struct intel_gt *gt,
> struct sseu_dev_info *sseu)
> {
> @@ -41,7 +34,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt,
> continue;
>
> sseu->slice_mask = BIT(0);
> - sseu->subslice_mask[0] |= BIT(ss);
> + sseu->subslice_mask.hsw[0] |= BIT(ss);
> eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
> ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
> ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
> @@ -92,7 +85,7 @@ static void gen11_sseu_device_status(struct intel_gt *gt,
> continue;
>
> sseu->slice_mask |= BIT(s);
> - sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
> + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
>
> for (ss = 0; ss < info->sseu.max_subslices; ss++) {
> unsigned int eu_cnt;
> @@ -147,21 +140,17 @@ static void gen9_sseu_device_status(struct intel_gt *gt,
> sseu->slice_mask |= BIT(s);
>
> if (IS_GEN9_BC(gt->i915))
> - sseu_copy_subslices(&info->sseu, s,
> - sseu->subslice_mask);
> + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
>
> for (ss = 0; ss < info->sseu.max_subslices; ss++) {
> unsigned int eu_cnt;
> - u8 ss_idx = s * info->sseu.ss_stride +
> - ss / BITS_PER_BYTE;
>
> if (IS_GEN9_LP(gt->i915)) {
> if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> /* skip disabled subslice */
> continue;
>
> - sseu->subslice_mask[ss_idx] |=
> - BIT(ss % BITS_PER_BYTE);
> + sseu->subslice_mask.hsw[s] |= BIT(ss);
> }
>
> eu_cnt = eu_reg[2 * s + ss / 2] & eu_mask[ss % 2];
> @@ -188,8 +177,7 @@ static void bdw_sseu_device_status(struct intel_gt *gt,
> if (sseu->slice_mask) {
> sseu->eu_per_subslice = info->sseu.eu_per_subslice;
> for (s = 0; s < fls(sseu->slice_mask); s++)
> - sseu_copy_subslices(&info->sseu, s,
> - sseu->subslice_mask);
> + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
> sseu->eu_total = sseu->eu_per_subslice *
> intel_sseu_subslice_total(sseu);
>
> @@ -208,7 +196,6 @@ static void i915_print_sseu_info(struct seq_file *m,
> const struct sseu_dev_info *sseu)
> {
> const char *type = is_available_info ? "Available" : "Enabled";
> - int s;
>
> seq_printf(m, " %s Slice Mask: %04x\n", type,
> sseu->slice_mask);
> @@ -216,10 +203,7 @@ static void i915_print_sseu_info(struct seq_file *m,
> hweight8(sseu->slice_mask));
> seq_printf(m, " %s Subslice Total: %u\n", type,
> intel_sseu_subslice_total(sseu));
> - for (s = 0; s < fls(sseu->slice_mask); s++) {
> - seq_printf(m, " %s Slice%i subslices: %u\n", type,
> - s, intel_sseu_subslices_per_slice(sseu, s));
> - }
> + intel_sseu_print_ss_info(type, sseu, m);
> seq_printf(m, " %s EU Total: %u\n", type,
> sseu->eu_total);
> seq_printf(m, " %s EU Per Subslice: %u\n", type,
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 73b59ea6fd3b..1bf62273e02d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -948,8 +948,8 @@ gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> * on s/ss combo, the read should be done with read_subslice_reg.
> */
> slice = ffs(sseu->slice_mask) - 1;
> - GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
> - subslice = ffs(intel_sseu_get_subslices(sseu, slice));
> + GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw));
> + subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice));
> GEM_BUG_ON(!subslice);
> subslice--;
>
> @@ -1087,11 +1087,10 @@ static void
> icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> const struct sseu_dev_info *sseu = >->info.sseu;
> - unsigned int slice, subslice;
> + unsigned int subslice;
>
> GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
> GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
> - slice = 0;
>
> /*
> * Although a platform may have subslices, we need to always steer
> @@ -1102,7 +1101,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> * one of the higher subslices, we run the risk of reading back 0's or
> * random garbage.
> */
> - subslice = __ffs(intel_sseu_get_subslices(sseu, slice));
> + subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0));
>
> /*
> * If the subslice we picked above also steers us to a valid L3 bank,
> @@ -1112,7 +1111,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> if (gt->info.l3bank_mask & BIT(subslice))
> gt->steering_table[L3BANK] = NULL;
>
> - __add_mcr_wa(gt, wal, slice, subslice);
> + __add_mcr_wa(gt, wal, 0, subslice);
> }
>
> static void
> @@ -1120,7 +1119,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> const struct sseu_dev_info *sseu = >->info.sseu;
> unsigned long slice, subslice = 0, slice_mask = 0;
> - u64 dss_mask = 0;
> u32 lncf_mask = 0;
> int i;
>
> @@ -1151,8 +1149,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> */
>
> /* Find the potential gslice candidates */
> - dss_mask = intel_sseu_get_subslices(sseu, 0);
> - slice_mask = intel_slicemask_from_dssmask(dss_mask, GEN_DSS_PER_GSLICE);
> + slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask,
> + GEN_DSS_PER_GSLICE);
>
> /*
> * Find the potential LNCF candidates. Either LNCF within a valid
> @@ -1177,9 +1175,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> }
>
> slice = __ffs(slice_mask);
> - subslice = __ffs(dss_mask >> (slice * GEN_DSS_PER_GSLICE));
> + subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice);
> WARN_ON(subslice > GEN_DSS_PER_GSLICE);
> - WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0);
>
> __add_mcr_wa(gt, wal, slice, subslice);
>
> @@ -2030,9 +2027,8 @@ engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>
> static bool needs_wa_1308578152(struct intel_engine_cs *engine)
> {
> - u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0);
> -
> - return (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0;
> + return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >
> + GEN_DSS_PER_GSLICE;
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
> index ac9767c56619..6fd15b39570c 100644
> --- a/drivers/gpu/drm/i915/i915_getparam.c
> +++ b/drivers/gpu/drm/i915/i915_getparam.c
> @@ -162,8 +162,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
> return -EINVAL;
>
> /* Only copy bits from the first slice */
> - memcpy(&value, sseu->subslice_mask,
> - min(sseu->ss_stride, (u8)sizeof(value)));
> + value = intel_sseu_get_hsw_subslices(sseu, 0);
> if (!value)
> return -ENODEV;
> break;
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 89c475d525b8..0094f67c63f2 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -31,10 +31,11 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
>
> static int fill_topology_info(const struct sseu_dev_info *sseu,
> struct drm_i915_query_item *query_item,
> - const u8 *subslice_mask)
> + intel_sseu_ss_mask_t subslice_mask)
> {
> struct drm_i915_query_topology_info topo;
> u32 slice_length, subslice_length, eu_length, total_length;
> + int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
> int eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
> int ret;
>
> @@ -44,7 +45,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
> return -ENODEV;
>
> slice_length = sizeof(sseu->slice_mask);
> - subslice_length = sseu->max_slices * sseu->ss_stride;
> + subslice_length = sseu->max_slices * ss_stride;
> eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
> total_length = sizeof(topo) + slice_length + subslice_length +
> eu_length;
> @@ -60,7 +61,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
> topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
>
> topo.subslice_offset = slice_length;
> - topo.subslice_stride = sseu->ss_stride;
> + topo.subslice_stride = ss_stride;
> topo.eu_offset = slice_length + subslice_length;
> topo.eu_stride = eu_stride;
>
> @@ -72,9 +73,9 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
> &sseu->slice_mask, slice_length))
> return -EFAULT;
>
> - if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
> - sizeof(topo) + slice_length),
> - subslice_mask, subslice_length))
> + if (intel_sseu_copy_ssmask_to_user(u64_to_user_ptr(query_item->data_ptr +
> + sizeof(topo) + slice_length),
> + sseu))
> return -EFAULT;
>
> if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
> --
> 2.35.3
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v5 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi
@ 2022-06-01 8:18 ` Balasubramani Vivekanandan
0 siblings, 0 replies; 36+ messages in thread
From: Balasubramani Vivekanandan @ 2022-06-01 8:18 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel
On 23.05.2022 13:45, Matt Roper wrote:
> As with EU masks, it's easier to store subslice/DSS masks internally in
> a format that's more natural for the driver to work with, and then only
> covert into the u8[] uapi form when the query ioctl is invoked. Since
> the hardware design changed significantly with Xe_HP, we'll use a union
> to choose between the old "hsw-style" subslice masks or the newer xehp
> mask. HSW-style masks will be stored in an array of u8's, indexed by
> slice (there's never more than 6 subslices per slice on older
> platforms). For Xe_HP and beyond where slices no longer exist, we only
> need a single bitmask. However we already know that this mask is
> eventually going to grow too large for a simple u64 to hold, so we'll
> represent it in a manner that can be operated on by the utilities in
> linux/bitmap.h.
>
> v2:
> - Fix typo: BIT(s) -> BIT(ss) in gen9_sseu_device_status()
>
> v3:
> - Eliminate sseu->ss_stride and just calculate the stride while
> specifically handling uapi. (Tvrtko)
> - Use BITMAP_BITS() macro to refer to size of masks rather than
> passing I915_MAX_SS_FUSE_BITS directly. (Tvrtko)
> - Report compute/geometry DSS masks separately when dumping Xe_HP SSEU
> info. (Tvrtko)
> - Restore dropped range checks to intel_sseu_has_subslice(). (Tvrtko)
>
> v4:
> - Make the bitmap size macro check the size of the .xehp field rather
> than the containing union. (Tvrtko)
> - Don't add GEM_BUG_ON() intel_sseu_has_subslice()'s check for whether
> slice or subslice ID exceed sseu->max_[sub]slices; various loops
> in the driver are expected to exceed these, so we should just
> silently return 'false.'
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 12 +-
> drivers/gpu/drm/i915/gt/intel_sseu.c | 261 +++++++++++--------
> drivers/gpu/drm/i915/gt/intel_sseu.h | 76 ++++--
> drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +--
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +-
> drivers/gpu/drm/i915/i915_getparam.c | 3 +-
> drivers/gpu/drm/i915/i915_query.c | 13 +-
> 9 files changed, 241 insertions(+), 187 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index ab4c5ab28e4d..a3bb73f5d53b 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -1875,6 +1875,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> {
> const struct sseu_dev_info *device = >->info.sseu;
> struct drm_i915_private *i915 = gt->i915;
> + unsigned int dev_subslice_mask = intel_sseu_get_hsw_subslices(device, 0);
>
> /* No zeros in any field. */
> if (!user->slice_mask || !user->subslice_mask ||
> @@ -1901,7 +1902,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> if (user->slice_mask & ~device->slice_mask)
> return -EINVAL;
>
> - if (user->subslice_mask & ~device->subslice_mask[0])
> + if (user->subslice_mask & ~dev_subslice_mask)
> return -EINVAL;
>
> if (user->max_eus_per_subslice > device->max_eus_per_subslice)
> @@ -1915,7 +1916,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> /* Part specific restrictions. */
> if (GRAPHICS_VER(i915) == 11) {
> unsigned int hw_s = hweight8(device->slice_mask);
> - unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
> + unsigned int hw_ss_per_s = hweight8(dev_subslice_mask);
> unsigned int req_s = hweight8(context->slice_mask);
> unsigned int req_ss = hweight8(context->subslice_mask);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 1adbf34c3632..f0acf8518a51 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -674,8 +674,8 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
> if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> return;
>
> - ccs_mask = intel_slicemask_from_dssmask(intel_sseu_get_compute_subslices(&info->sseu),
> - ss_per_ccs);
> + ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
> + ss_per_ccs);
> /*
> * If all DSS in a quadrant are fused off, the corresponding CCS
> * engine is not available for use.
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 034182f85501..2921f510642f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -133,13 +133,6 @@ static const struct intel_mmio_range dg2_lncf_steering_table[] = {
> {},
> };
>
> -static u16 slicemask(struct intel_gt *gt, int count)
> -{
> - u64 dss_mask = intel_sseu_get_subslices(>->info.sseu, 0);
> -
> - return intel_slicemask_from_dssmask(dss_mask, count);
> -}
> -
> int intel_gt_init_mmio(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> @@ -155,9 +148,12 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> */
> if (HAS_MSLICES(i915)) {
> gt->info.mslice_mask =
> - slicemask(gt, GEN_DSS_PER_MSLICE) |
> + intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
> + GEN_DSS_PER_MSLICE);
> + gt->info.mslice_mask |=
> (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> GEN12_MEML3_EN_MASK);
> +
> if (!gt->info.mslice_mask) /* should be impossible! */
> drm_warn(&i915->drm, "mslice mask all zero!\n");
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index 285cfd758bdc..3a721db20290 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -10,15 +10,14 @@
> #include "intel_gt_regs.h"
> #include "intel_sseu.h"
>
> +#define XEHP_BITMAP_BITS(mask) ((int)BITS_PER_TYPE(typeof(mask.xehp)))
> +
> void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
> u8 max_subslices, u8 max_eus_per_subslice)
> {
> sseu->max_slices = max_slices;
> sseu->max_subslices = max_subslices;
> sseu->max_eus_per_subslice = max_eus_per_subslice;
> -
> - sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
> - GEM_BUG_ON(sseu->ss_stride > GEN_MAX_SUBSLICE_STRIDE);
> }
>
> unsigned int
> @@ -26,54 +25,24 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
> {
> unsigned int i, total = 0;
>
> - for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
> - total += hweight8(sseu->subslice_mask[i]);
> -
> - return total;
> -}
> -
> -static u32
> -sseu_get_subslices(const struct sseu_dev_info *sseu,
> - const u8 *subslice_mask, u8 slice)
> -{
> - int i, offset = slice * sseu->ss_stride;
> - u32 mask = 0;
> -
> - GEM_BUG_ON(slice >= sseu->max_slices);
> -
> - for (i = 0; i < sseu->ss_stride; i++)
> - mask |= (u32)subslice_mask[offset + i] << i * BITS_PER_BYTE;
> -
> - return mask;
> -}
> -
> -u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
> -{
> - return sseu_get_subslices(sseu, sseu->subslice_mask, slice);
> -}
> + if (sseu->has_xehp_dss)
> + return bitmap_weight(sseu->subslice_mask.xehp,
> + XEHP_BITMAP_BITS(sseu->subslice_mask));
>
> -static u32 sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
> -{
> - return sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
> -}
> + for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++)
> + total += hweight8(sseu->subslice_mask.hsw[i]);
>
> -u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu)
> -{
> - return sseu_get_subslices(sseu, sseu->compute_subslice_mask, 0);
> -}
> -
> -void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
> - u8 *subslice_mask, u32 ss_mask)
> -{
> - int offset = slice * sseu->ss_stride;
> -
> - memcpy(&subslice_mask[offset], &ss_mask, sseu->ss_stride);
> + return total;
> }
>
> unsigned int
> -intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
> +intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice)
> {
> - return hweight32(intel_sseu_get_subslices(sseu, slice));
> + WARN_ON(sseu->has_xehp_dss);
> + if (WARN_ON(slice >= sseu->max_slices))
> + return 0;
> +
> + return sseu->subslice_mask.hsw[slice];
> }
>
> static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
> @@ -147,32 +116,66 @@ int intel_sseu_copy_eumask_to_user(void __user *to,
> return copy_to_user(to, eu_mask, len);
> }
>
> +/**
> + * intel_sseu_copy_ssmask_to_user - Copy subslice mask into a userspace buffer
> + * @to: Pointer to userspace buffer to copy to
> + * @sseu: SSEU structure containing subslice mask to copy
> + *
> + * Copies the subslice mask to a userspace buffer in the format expected by
> + * the query ioctl's topology queries.
> + *
> + * Returns the result of the copy_to_user() operation.
> + */
> +int intel_sseu_copy_ssmask_to_user(void __user *to,
> + const struct sseu_dev_info *sseu)
> +{
> + u8 ss_mask[GEN_SS_MASK_SIZE] = {};
> + int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
> + int len = sseu->max_slices * ss_stride;
> + int s, ss, i;
> +
> + for (s = 0; s < sseu->max_slices; s++) {
> + for (ss = 0; ss < sseu->max_subslices; ss++) {
> + i = s * ss_stride * BITS_PER_BYTE + ss;
> +
> + if (!intel_sseu_has_subslice(sseu, s, ss))
> + continue;
> +
> + ss_mask[i / BITS_PER_BYTE] |= BIT(i % BITS_PER_BYTE);
> + }
> + }
> +
> + return copy_to_user(to, ss_mask, len);
> +}
> +
> static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> - u32 g_ss_en, u32 c_ss_en, u16 eu_en)
> + u32 ss_en, u16 eu_en)
> {
> u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
> int ss;
>
> - /* g_ss_en/c_ss_en represent entire subslice mask across all slices */
> - GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
> - sizeof(g_ss_en) * BITS_PER_BYTE);
> + sseu->slice_mask |= BIT(0);
> + sseu->subslice_mask.hsw[0] = ss_en & valid_ss_mask;
> +
> + for (ss = 0; ss < sseu->max_subslices; ss++)
> + if (intel_sseu_has_subslice(sseu, 0, ss))
> + sseu_set_eus(sseu, 0, ss, eu_en);
> +
> + sseu->eu_per_subslice = hweight16(eu_en);
> + sseu->eu_total = compute_eu_total(sseu);
> +}
> +
> +static void xehp_compute_sseu_info(struct sseu_dev_info *sseu,
> + u16 eu_en)
> +{
> + int ss;
>
> sseu->slice_mask |= BIT(0);
>
> - /*
> - * XeHP introduces the concept of compute vs geometry DSS. To reduce
> - * variation between GENs around subslice usage, store a mask for both
> - * the geometry and compute enabled masks since userspace will need to
> - * be able to query these masks independently. Also compute a total
> - * enabled subslice count for the purposes of selecting subslices to
> - * use in a particular GEM context.
> - */
> - intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
> - c_ss_en & valid_ss_mask);
> - intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
> - g_ss_en & valid_ss_mask);
> - intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
> - (g_ss_en | c_ss_en) & valid_ss_mask);
> + bitmap_or(sseu->subslice_mask.xehp,
> + sseu->compute_subslice_mask.xehp,
> + sseu->geometry_subslice_mask.xehp,
> + XEHP_BITMAP_BITS(sseu->subslice_mask));
>
> for (ss = 0; ss < sseu->max_subslices; ss++)
> if (intel_sseu_has_subslice(sseu, 0, ss))
> @@ -182,11 +185,31 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> sseu->eu_total = compute_eu_total(sseu);
> }
>
> +static void
> +xehp_load_dss_mask(struct intel_uncore *uncore,
> + intel_sseu_ss_mask_t *ssmask,
> + int numregs,
> + ...)
> +{
> + va_list argp;
> + u32 fuse_val[I915_MAX_SS_FUSE_REGS] = {};
> + int i;
> +
> + if (WARN_ON(numregs > I915_MAX_SS_FUSE_REGS))
> + numregs = I915_MAX_SS_FUSE_REGS;
> +
> + va_start(argp, numregs);
> + for (i = 0; i < numregs; i++)
> + fuse_val[i] = intel_uncore_read(uncore, va_arg(argp, i915_reg_t));
> + va_end(argp);
> +
> + bitmap_from_arr32(ssmask->xehp, fuse_val, numregs * 32);
> +}
> +
> static void xehp_sseu_info_init(struct intel_gt *gt)
> {
> struct sseu_dev_info *sseu = >->info.sseu;
> struct intel_uncore *uncore = gt->uncore;
> - u32 g_dss_en, c_dss_en = 0;
> u16 eu_en = 0;
> u8 eu_en_fuse;
> int eu;
> @@ -200,8 +223,10 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
> intel_sseu_set_info(sseu, 1, 32, 16);
> sseu->has_xehp_dss = 1;
>
> - g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
> - c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
> + xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 1,
> + GEN12_GT_GEOMETRY_DSS_ENABLE);
> + xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 1,
> + GEN12_GT_COMPUTE_DSS_ENABLE);
>
> eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
>
> @@ -209,7 +234,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
> if (eu_en_fuse & BIT(eu))
> eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
>
> - gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
> + xehp_compute_sseu_info(sseu, eu_en);
> }
>
> static void gen12_sseu_info_init(struct intel_gt *gt)
> @@ -247,7 +272,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
> if (eu_en_fuse & BIT(eu))
> eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
>
> - gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
> + gen11_compute_sseu_info(sseu, g_dss_en, eu_en);
>
> /* TGL only supports slice-level power gating */
> sseu->has_slice_pg = 1;
> @@ -279,7 +304,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
> eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
> GEN11_EU_DIS_MASK);
>
> - gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
> + gen11_compute_sseu_info(sseu, ss_en, eu_en);
>
> /* ICL has no power gating restrictions. */
> sseu->has_slice_pg = 1;
> @@ -291,7 +316,6 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> {
> struct sseu_dev_info *sseu = >->info.sseu;
> u32 fuse;
> - u8 subslice_mask = 0;
>
> fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT);
>
> @@ -305,7 +329,7 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
> CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
>
> - subslice_mask |= BIT(0);
> + sseu->subslice_mask.hsw[0] |= BIT(0);
> sseu_set_eus(sseu, 0, 0, ~disabled_mask & 0xFF);
> }
>
> @@ -316,12 +340,10 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
> CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
>
> - subslice_mask |= BIT(1);
> + sseu->subslice_mask.hsw[0] |= BIT(1);
> sseu_set_eus(sseu, 0, 1, ~disabled_mask & 0xFF);
> }
>
> - intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask, subslice_mask);
> -
> sseu->eu_total = compute_eu_total(sseu);
>
> /*
> @@ -376,8 +398,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
> /* skip disabled slice */
> continue;
>
> - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> - subslice_mask);
> + sseu->subslice_mask.hsw[s] = subslice_mask;
>
> eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> @@ -434,8 +455,8 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
> sseu->has_eu_pg = sseu->eu_per_subslice > 2;
>
> if (IS_GEN9_LP(i915)) {
> -#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
> - info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
> +#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask.hsw[0] & BIT(ss)))
> + info->has_pooled_eu = hweight8(sseu->subslice_mask.hsw[0]) == 3;
>
> sseu->min_eu_in_pool = 0;
> if (info->has_pooled_eu) {
> @@ -489,8 +510,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
> /* skip disabled slice */
> continue;
>
> - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> - subslice_mask);
> + sseu->subslice_mask.hsw[s] = subslice_mask;
>
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> u8 eu_disabled_mask;
> @@ -587,8 +607,7 @@ static void hsw_sseu_info_init(struct intel_gt *gt)
> sseu->eu_per_subslice);
>
> for (s = 0; s < sseu->max_slices; s++) {
> - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> - subslice_mask);
> + sseu->subslice_mask.hsw[s] = subslice_mask;
>
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> sseu_set_eus(sseu, s, ss,
> @@ -677,7 +696,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
> */
> if (GRAPHICS_VER(i915) == 11 &&
> slices == 1 &&
> - subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
> + subslices > min_t(u8, 4, hweight8(sseu->subslice_mask.hsw[0]) / 2)) {
> GEM_BUG_ON(subslices & 1);
>
> subslice_pg = false;
> @@ -743,14 +762,29 @@ void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
> {
> int s;
>
> - drm_printf(p, "slice total: %u, mask=%04x\n",
> - hweight8(sseu->slice_mask), sseu->slice_mask);
> - drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
> - for (s = 0; s < sseu->max_slices; s++) {
> - drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
> - s, intel_sseu_subslices_per_slice(sseu, s),
> - intel_sseu_get_subslices(sseu, s));
> + if (sseu->has_xehp_dss) {
> + drm_printf(p, "subslice total: %u\n",
> + intel_sseu_subslice_total(sseu));
> + drm_printf(p, "geometry dss mask=%*pb\n",
> + XEHP_BITMAP_BITS(sseu->geometry_subslice_mask),
> + sseu->geometry_subslice_mask.xehp);
> + drm_printf(p, "compute dss mask=%*pb\n",
> + XEHP_BITMAP_BITS(sseu->compute_subslice_mask),
> + sseu->compute_subslice_mask.xehp);
> + } else {
> + drm_printf(p, "slice total: %u, mask=%04x\n",
> + hweight8(sseu->slice_mask), sseu->slice_mask);
> + drm_printf(p, "subslice total: %u\n",
> + intel_sseu_subslice_total(sseu));
> +
> + for (s = 0; s < sseu->max_slices; s++) {
> + u8 ss_mask = sseu->subslice_mask.hsw[s];
> +
> + drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
> + s, hweight8(ss_mask), ss_mask);
> + }
> }
> +
> drm_printf(p, "EU total: %u\n", sseu->eu_total);
> drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
> drm_printf(p, "has slice power gating: %s\n",
> @@ -767,9 +801,10 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
> int s, ss;
>
> for (s = 0; s < sseu->max_slices; s++) {
> + u8 ss_mask = sseu->subslice_mask.hsw[s];
> +
> drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
> - s, intel_sseu_subslices_per_slice(sseu, s),
> - intel_sseu_get_subslices(sseu, s));
> + s, hweight8(ss_mask), ss_mask);
>
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> u16 enabled_eus = sseu_get_eus(sseu, s, ss);
> @@ -783,16 +818,14 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
> static void sseu_print_xehp_topology(const struct sseu_dev_info *sseu,
> struct drm_printer *p)
> {
> - u32 g_dss_mask = sseu_get_geometry_subslices(sseu);
> - u32 c_dss_mask = intel_sseu_get_compute_subslices(sseu);
> int dss;
>
> for (dss = 0; dss < sseu->max_subslices; dss++) {
> u16 enabled_eus = sseu_get_eus(sseu, 0, dss);
>
> drm_printf(p, "DSS_%02d: G:%3s C:%3s, %2u EUs (0x%04hx)\n", dss,
> - str_yes_no(g_dss_mask & BIT(dss)),
> - str_yes_no(c_dss_mask & BIT(dss)),
> + str_yes_no(test_bit(dss, sseu->geometry_subslice_mask.xehp)),
> + str_yes_no(test_bit(dss, sseu->compute_subslice_mask.xehp)),
> hweight16(enabled_eus), enabled_eus);
> }
> }
> @@ -810,20 +843,44 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
> }
> }
>
> -u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice)
> +void intel_sseu_print_ss_info(const char* type,
> + const struct sseu_dev_info *sseu,
> + struct seq_file *m)
> +{
> + int s;
> +
> + if (sseu->has_xehp_dss) {
> + seq_printf(m, " %s Geometry DSS: %u\n", type,
> + bitmap_weight(sseu->geometry_subslice_mask.xehp,
> + XEHP_BITMAP_BITS(sseu->geometry_subslice_mask)));
> + seq_printf(m, " %s Compute DSS: %u\n", type,
> + bitmap_weight(sseu->compute_subslice_mask.xehp,
> + XEHP_BITMAP_BITS(sseu->compute_subslice_mask)));
> + } else {
> + for (s = 0; s < fls(sseu->slice_mask); s++)
> + seq_printf(m, " %s Slice%i subslices: %u\n", type,
> + s, hweight8(sseu->subslice_mask.hsw[s]));
> + }
> +}
> +
> +u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask,
> + int dss_per_slice)
> {
> + intel_sseu_ss_mask_t per_slice_mask = {};
> u16 slice_mask = 0;
> int i;
>
> - WARN_ON(sizeof(dss_mask) * 8 / dss_per_slice > 8 * sizeof(slice_mask));
> + WARN_ON(DIV_ROUND_UP(XEHP_BITMAP_BITS(dss_mask), dss_per_slice) >
> + 8 * sizeof(slice_mask));
>
> - for (i = 0; dss_mask; i++) {
> - if (dss_mask & GENMASK(dss_per_slice - 1, 0))
> + bitmap_fill(per_slice_mask.xehp, dss_per_slice);
> + for (i = 0; !bitmap_empty(dss_mask.xehp, XEHP_BITMAP_BITS(dss_mask)); i++) {
> + if (bitmap_intersects(dss_mask.xehp, per_slice_mask.xehp, dss_per_slice))
> slice_mask |= BIT(i);
>
> - dss_mask >>= dss_per_slice;
> + bitmap_shift_right(dss_mask.xehp, dss_mask.xehp, dss_per_slice,
> + XEHP_BITMAP_BITS(dss_mask));
> }
>
> return slice_mask;
> }
> -
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
> index ffa375e68959..e7f336a7ffbb 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> @@ -25,12 +25,16 @@ struct drm_printer;
> /*
> * Maximum number of subslices that can exist within a HSW-style slice. This
> * is only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the
> - * GEN_MAX_DSS value below).
> + * I915_MAX_SS_FUSE_BITS value below).
> */
> #define GEN_MAX_SS_PER_HSW_SLICE 6
>
> -/* Maximum number of DSS on newer platforms (Xe_HP and beyond). */
> -#define GEN_MAX_DSS 32
> +/*
> + * Maximum number of 32-bit registers used by hardware to express the
> + * enabled/disabled subslices.
> + */
> +#define I915_MAX_SS_FUSE_REGS 1
> +#define I915_MAX_SS_FUSE_BITS (I915_MAX_SS_FUSE_REGS * 32)
>
> /* Maximum number of EUs that can exist within a subslice or DSS. */
> #define GEN_MAX_EUS_PER_SS 16
> @@ -38,7 +42,7 @@ struct drm_printer;
> #define SSEU_MAX(a, b) ((a) > (b) ? (a) : (b))
>
> /* The maximum number of bits needed to express each subslice/DSS independently */
> -#define GEN_SS_MASK_SIZE SSEU_MAX(GEN_MAX_DSS, \
> +#define GEN_SS_MASK_SIZE SSEU_MAX(I915_MAX_SS_FUSE_BITS, \
> GEN_MAX_HSW_SLICES * GEN_MAX_SS_PER_HSW_SLICE)
>
> #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
> @@ -49,17 +53,24 @@ struct drm_printer;
> #define GEN_DSS_PER_CSLICE 8
> #define GEN_DSS_PER_MSLICE 8
>
> -#define GEN_MAX_GSLICES (GEN_MAX_DSS / GEN_DSS_PER_GSLICE)
> -#define GEN_MAX_CSLICES (GEN_MAX_DSS / GEN_DSS_PER_CSLICE)
> +#define GEN_MAX_GSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_GSLICE)
> +#define GEN_MAX_CSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_CSLICE)
> +
> +typedef union {
> + u8 hsw[GEN_MAX_HSW_SLICES];
> +
> + /* Bitmap compatible with linux/bitmap.h; may exceed size of u64 */
> + unsigned long xehp[BITS_TO_LONGS(I915_MAX_SS_FUSE_BITS)];
> +} intel_sseu_ss_mask_t;
>
> struct sseu_dev_info {
> u8 slice_mask;
> - u8 subslice_mask[GEN_SS_MASK_SIZE];
> - u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
> - u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
> + intel_sseu_ss_mask_t subslice_mask;
> + intel_sseu_ss_mask_t geometry_subslice_mask;
> + intel_sseu_ss_mask_t compute_subslice_mask;
> union {
> u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
> - u16 xehp[GEN_MAX_DSS];
> + u16 xehp[I915_MAX_SS_FUSE_BITS];
> } eu_mask;
>
> u16 eu_total;
> @@ -80,8 +91,6 @@ struct sseu_dev_info {
> u8 max_slices;
> u8 max_subslices;
> u8 max_eus_per_subslice;
> -
> - u8 ss_stride;
> };
>
> /*
> @@ -99,7 +108,7 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
> {
> struct intel_sseu value = {
> .slice_mask = sseu->slice_mask,
> - .subslice_mask = sseu->subslice_mask[0],
> + .subslice_mask = sseu->subslice_mask.hsw[0],
> .min_eus_per_subslice = sseu->max_eus_per_subslice,
> .max_eus_per_subslice = sseu->max_eus_per_subslice,
> };
> @@ -111,18 +120,27 @@ static inline bool
> intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
> int subslice)
> {
> - u8 mask;
> - int ss_idx = subslice / BITS_PER_BYTE;
> -
> if (slice >= sseu->max_slices ||
> subslice >= sseu->max_subslices)
> return false;
>
> - GEM_BUG_ON(ss_idx >= sseu->ss_stride);
> -
> - mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx];
> + if (sseu->has_xehp_dss)
> + return test_bit(subslice, sseu->subslice_mask.xehp);
> + else
> + return sseu->subslice_mask.hsw[slice] & BIT(subslice);
> +}
>
> - return mask & BIT(subslice % BITS_PER_BYTE);
> +/*
> + * Used to obtain the index of the first DSS. Can start searching from the
> + * beginning of a specific dss group (e.g., gslice, cslice, etc.) if
> + * groupsize and groupnum are non-zero.
> + */
> +static inline unsigned int
> +intel_sseu_find_first_xehp_dss(const struct sseu_dev_info *sseu, int groupsize,
> + int groupnum)
> +{
> + return find_next_bit(sseu->subslice_mask.xehp, I915_MAX_SS_FUSE_BITS,
> + groupnum * groupsize);
Any specific reason for not replacing I915_MAX_SS_FUSE_BITS with
XEHP_BITMAP_BITS here?
Regards,
Bala
> }
>
> void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
> @@ -132,14 +150,10 @@ unsigned int
> intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
>
> unsigned int
> -intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
> -
> -u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
> +intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice);
>
> -u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
> -
> -void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
> - u8 *subslice_mask, u32 ss_mask);
> +intel_sseu_ss_mask_t
> +intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
>
> void intel_sseu_info_init(struct intel_gt *gt);
>
> @@ -151,9 +165,15 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
> const struct sseu_dev_info *sseu,
> struct drm_printer *p);
>
> -u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
> +u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask, int dss_per_slice);
>
> int intel_sseu_copy_eumask_to_user(void __user *to,
> const struct sseu_dev_info *sseu);
> +int intel_sseu_copy_ssmask_to_user(void __user *to,
> + const struct sseu_dev_info *sseu);
> +
> +void intel_sseu_print_ss_info(const char* type,
> + const struct sseu_dev_info *sseu,
> + struct seq_file *m);
>
> #endif /* __INTEL_SSEU_H__ */
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> index 2d5d011e01db..c2ee5e1826b5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> @@ -4,6 +4,7 @@
> * Copyright © 2020 Intel Corporation
> */
>
> +#include <linux/bitmap.h>
> #include <linux/string_helpers.h>
>
> #include "i915_drv.h"
> @@ -11,14 +12,6 @@
> #include "intel_gt_regs.h"
> #include "intel_sseu_debugfs.h"
>
> -static void sseu_copy_subslices(const struct sseu_dev_info *sseu,
> - int slice, u8 *to_mask)
> -{
> - int offset = slice * sseu->ss_stride;
> -
> - memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
> -}
> -
> static void cherryview_sseu_device_status(struct intel_gt *gt,
> struct sseu_dev_info *sseu)
> {
> @@ -41,7 +34,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt,
> continue;
>
> sseu->slice_mask = BIT(0);
> - sseu->subslice_mask[0] |= BIT(ss);
> + sseu->subslice_mask.hsw[0] |= BIT(ss);
> eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
> ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
> ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
> @@ -92,7 +85,7 @@ static void gen11_sseu_device_status(struct intel_gt *gt,
> continue;
>
> sseu->slice_mask |= BIT(s);
> - sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
> + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
>
> for (ss = 0; ss < info->sseu.max_subslices; ss++) {
> unsigned int eu_cnt;
> @@ -147,21 +140,17 @@ static void gen9_sseu_device_status(struct intel_gt *gt,
> sseu->slice_mask |= BIT(s);
>
> if (IS_GEN9_BC(gt->i915))
> - sseu_copy_subslices(&info->sseu, s,
> - sseu->subslice_mask);
> + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
>
> for (ss = 0; ss < info->sseu.max_subslices; ss++) {
> unsigned int eu_cnt;
> - u8 ss_idx = s * info->sseu.ss_stride +
> - ss / BITS_PER_BYTE;
>
> if (IS_GEN9_LP(gt->i915)) {
> if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> /* skip disabled subslice */
> continue;
>
> - sseu->subslice_mask[ss_idx] |=
> - BIT(ss % BITS_PER_BYTE);
> + sseu->subslice_mask.hsw[s] |= BIT(ss);
> }
>
> eu_cnt = eu_reg[2 * s + ss / 2] & eu_mask[ss % 2];
> @@ -188,8 +177,7 @@ static void bdw_sseu_device_status(struct intel_gt *gt,
> if (sseu->slice_mask) {
> sseu->eu_per_subslice = info->sseu.eu_per_subslice;
> for (s = 0; s < fls(sseu->slice_mask); s++)
> - sseu_copy_subslices(&info->sseu, s,
> - sseu->subslice_mask);
> + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
> sseu->eu_total = sseu->eu_per_subslice *
> intel_sseu_subslice_total(sseu);
>
> @@ -208,7 +196,6 @@ static void i915_print_sseu_info(struct seq_file *m,
> const struct sseu_dev_info *sseu)
> {
> const char *type = is_available_info ? "Available" : "Enabled";
> - int s;
>
> seq_printf(m, " %s Slice Mask: %04x\n", type,
> sseu->slice_mask);
> @@ -216,10 +203,7 @@ static void i915_print_sseu_info(struct seq_file *m,
> hweight8(sseu->slice_mask));
> seq_printf(m, " %s Subslice Total: %u\n", type,
> intel_sseu_subslice_total(sseu));
> - for (s = 0; s < fls(sseu->slice_mask); s++) {
> - seq_printf(m, " %s Slice%i subslices: %u\n", type,
> - s, intel_sseu_subslices_per_slice(sseu, s));
> - }
> + intel_sseu_print_ss_info(type, sseu, m);
> seq_printf(m, " %s EU Total: %u\n", type,
> sseu->eu_total);
> seq_printf(m, " %s EU Per Subslice: %u\n", type,
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 73b59ea6fd3b..1bf62273e02d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -948,8 +948,8 @@ gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> * on s/ss combo, the read should be done with read_subslice_reg.
> */
> slice = ffs(sseu->slice_mask) - 1;
> - GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
> - subslice = ffs(intel_sseu_get_subslices(sseu, slice));
> + GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw));
> + subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice));
> GEM_BUG_ON(!subslice);
> subslice--;
>
> @@ -1087,11 +1087,10 @@ static void
> icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> const struct sseu_dev_info *sseu = >->info.sseu;
> - unsigned int slice, subslice;
> + unsigned int subslice;
>
> GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
> GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
> - slice = 0;
>
> /*
> * Although a platform may have subslices, we need to always steer
> @@ -1102,7 +1101,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> * one of the higher subslices, we run the risk of reading back 0's or
> * random garbage.
> */
> - subslice = __ffs(intel_sseu_get_subslices(sseu, slice));
> + subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0));
>
> /*
> * If the subslice we picked above also steers us to a valid L3 bank,
> @@ -1112,7 +1111,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> if (gt->info.l3bank_mask & BIT(subslice))
> gt->steering_table[L3BANK] = NULL;
>
> - __add_mcr_wa(gt, wal, slice, subslice);
> + __add_mcr_wa(gt, wal, 0, subslice);
> }
>
> static void
> @@ -1120,7 +1119,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> const struct sseu_dev_info *sseu = >->info.sseu;
> unsigned long slice, subslice = 0, slice_mask = 0;
> - u64 dss_mask = 0;
> u32 lncf_mask = 0;
> int i;
>
> @@ -1151,8 +1149,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> */
>
> /* Find the potential gslice candidates */
> - dss_mask = intel_sseu_get_subslices(sseu, 0);
> - slice_mask = intel_slicemask_from_dssmask(dss_mask, GEN_DSS_PER_GSLICE);
> + slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask,
> + GEN_DSS_PER_GSLICE);
>
> /*
> * Find the potential LNCF candidates. Either LNCF within a valid
> @@ -1177,9 +1175,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> }
>
> slice = __ffs(slice_mask);
> - subslice = __ffs(dss_mask >> (slice * GEN_DSS_PER_GSLICE));
> + subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice);
> WARN_ON(subslice > GEN_DSS_PER_GSLICE);
> - WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0);
>
> __add_mcr_wa(gt, wal, slice, subslice);
>
> @@ -2030,9 +2027,8 @@ engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>
> static bool needs_wa_1308578152(struct intel_engine_cs *engine)
> {
> - u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0);
> -
> - return (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0;
> + return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >
> + GEN_DSS_PER_GSLICE;
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
> index ac9767c56619..6fd15b39570c 100644
> --- a/drivers/gpu/drm/i915/i915_getparam.c
> +++ b/drivers/gpu/drm/i915/i915_getparam.c
> @@ -162,8 +162,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
> return -EINVAL;
>
> /* Only copy bits from the first slice */
> - memcpy(&value, sseu->subslice_mask,
> - min(sseu->ss_stride, (u8)sizeof(value)));
> + value = intel_sseu_get_hsw_subslices(sseu, 0);
> if (!value)
> return -ENODEV;
> break;
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 89c475d525b8..0094f67c63f2 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -31,10 +31,11 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
>
> static int fill_topology_info(const struct sseu_dev_info *sseu,
> struct drm_i915_query_item *query_item,
> - const u8 *subslice_mask)
> + intel_sseu_ss_mask_t subslice_mask)
> {
> struct drm_i915_query_topology_info topo;
> u32 slice_length, subslice_length, eu_length, total_length;
> + int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
> int eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
> int ret;
>
> @@ -44,7 +45,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
> return -ENODEV;
>
> slice_length = sizeof(sseu->slice_mask);
> - subslice_length = sseu->max_slices * sseu->ss_stride;
> + subslice_length = sseu->max_slices * ss_stride;
> eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
> total_length = sizeof(topo) + slice_length + subslice_length +
> eu_length;
> @@ -60,7 +61,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
> topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
>
> topo.subslice_offset = slice_length;
> - topo.subslice_stride = sseu->ss_stride;
> + topo.subslice_stride = ss_stride;
> topo.eu_offset = slice_length + subslice_length;
> topo.eu_stride = eu_stride;
>
> @@ -72,9 +73,9 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
> &sseu->slice_mask, slice_length))
> return -EFAULT;
>
> - if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
> - sizeof(topo) + slice_length),
> - subslice_mask, subslice_length))
> + if (intel_sseu_copy_ssmask_to_user(u64_to_user_ptr(query_item->data_ptr +
> + sizeof(topo) + slice_length),
> + sseu))
> return -EFAULT;
>
> if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
> --
> 2.35.3
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v5 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi
2022-06-01 8:18 ` [Intel-gfx] " Balasubramani Vivekanandan
@ 2022-06-01 14:40 ` Matt Roper
-1 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-06-01 14:40 UTC (permalink / raw)
To: Balasubramani Vivekanandan; +Cc: Tvrtko Ursulin, intel-gfx, dri-devel
On Wed, Jun 01, 2022 at 01:48:56PM +0530, Balasubramani Vivekanandan wrote:
> On 23.05.2022 13:45, Matt Roper wrote:
> > As with EU masks, it's easier to store subslice/DSS masks internally in
> > a format that's more natural for the driver to work with, and then only
> > covert into the u8[] uapi form when the query ioctl is invoked. Since
> > the hardware design changed significantly with Xe_HP, we'll use a union
> > to choose between the old "hsw-style" subslice masks or the newer xehp
> > mask. HSW-style masks will be stored in an array of u8's, indexed by
> > slice (there's never more than 6 subslices per slice on older
> > platforms). For Xe_HP and beyond where slices no longer exist, we only
> > need a single bitmask. However we already know that this mask is
> > eventually going to grow too large for a simple u64 to hold, so we'll
> > represent it in a manner that can be operated on by the utilities in
> > linux/bitmap.h.
> >
> > v2:
> > - Fix typo: BIT(s) -> BIT(ss) in gen9_sseu_device_status()
> >
> > v3:
> > - Eliminate sseu->ss_stride and just calculate the stride while
> > specifically handling uapi. (Tvrtko)
> > - Use BITMAP_BITS() macro to refer to size of masks rather than
> > passing I915_MAX_SS_FUSE_BITS directly. (Tvrtko)
> > - Report compute/geometry DSS masks separately when dumping Xe_HP SSEU
> > info. (Tvrtko)
> > - Restore dropped range checks to intel_sseu_has_subslice(). (Tvrtko)
> >
> > v4:
> > - Make the bitmap size macro check the size of the .xehp field rather
> > than the containing union. (Tvrtko)
> > - Don't add GEM_BUG_ON() intel_sseu_has_subslice()'s check for whether
> > slice or subslice ID exceed sseu->max_[sub]slices; various loops
> > in the driver are expected to exceed these, so we should just
> > silently return 'false.'
> >
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +-
> > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
> > drivers/gpu/drm/i915/gt/intel_gt.c | 12 +-
> > drivers/gpu/drm/i915/gt/intel_sseu.c | 261 +++++++++++--------
> > drivers/gpu/drm/i915/gt/intel_sseu.h | 76 ++++--
> > drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +--
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +-
> > drivers/gpu/drm/i915/i915_getparam.c | 3 +-
> > drivers/gpu/drm/i915/i915_query.c | 13 +-
> > 9 files changed, 241 insertions(+), 187 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > index ab4c5ab28e4d..a3bb73f5d53b 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > @@ -1875,6 +1875,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> > {
> > const struct sseu_dev_info *device = >->info.sseu;
> > struct drm_i915_private *i915 = gt->i915;
> > + unsigned int dev_subslice_mask = intel_sseu_get_hsw_subslices(device, 0);
> >
> > /* No zeros in any field. */
> > if (!user->slice_mask || !user->subslice_mask ||
> > @@ -1901,7 +1902,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> > if (user->slice_mask & ~device->slice_mask)
> > return -EINVAL;
> >
> > - if (user->subslice_mask & ~device->subslice_mask[0])
> > + if (user->subslice_mask & ~dev_subslice_mask)
> > return -EINVAL;
> >
> > if (user->max_eus_per_subslice > device->max_eus_per_subslice)
> > @@ -1915,7 +1916,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> > /* Part specific restrictions. */
> > if (GRAPHICS_VER(i915) == 11) {
> > unsigned int hw_s = hweight8(device->slice_mask);
> > - unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
> > + unsigned int hw_ss_per_s = hweight8(dev_subslice_mask);
> > unsigned int req_s = hweight8(context->slice_mask);
> > unsigned int req_ss = hweight8(context->subslice_mask);
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > index 1adbf34c3632..f0acf8518a51 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > @@ -674,8 +674,8 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
> > if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> > return;
> >
> > - ccs_mask = intel_slicemask_from_dssmask(intel_sseu_get_compute_subslices(&info->sseu),
> > - ss_per_ccs);
> > + ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
> > + ss_per_ccs);
> > /*
> > * If all DSS in a quadrant are fused off, the corresponding CCS
> > * engine is not available for use.
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> > index 034182f85501..2921f510642f 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > @@ -133,13 +133,6 @@ static const struct intel_mmio_range dg2_lncf_steering_table[] = {
> > {},
> > };
> >
> > -static u16 slicemask(struct intel_gt *gt, int count)
> > -{
> > - u64 dss_mask = intel_sseu_get_subslices(>->info.sseu, 0);
> > -
> > - return intel_slicemask_from_dssmask(dss_mask, count);
> > -}
> > -
> > int intel_gt_init_mmio(struct intel_gt *gt)
> > {
> > struct drm_i915_private *i915 = gt->i915;
> > @@ -155,9 +148,12 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> > */
> > if (HAS_MSLICES(i915)) {
> > gt->info.mslice_mask =
> > - slicemask(gt, GEN_DSS_PER_MSLICE) |
> > + intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
> > + GEN_DSS_PER_MSLICE);
> > + gt->info.mslice_mask |=
> > (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> > GEN12_MEML3_EN_MASK);
> > +
> > if (!gt->info.mslice_mask) /* should be impossible! */
> > drm_warn(&i915->drm, "mslice mask all zero!\n");
> > }
> > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> > index 285cfd758bdc..3a721db20290 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> > @@ -10,15 +10,14 @@
> > #include "intel_gt_regs.h"
> > #include "intel_sseu.h"
> >
> > +#define XEHP_BITMAP_BITS(mask) ((int)BITS_PER_TYPE(typeof(mask.xehp)))
> > +
> > void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
> > u8 max_subslices, u8 max_eus_per_subslice)
> > {
> > sseu->max_slices = max_slices;
> > sseu->max_subslices = max_subslices;
> > sseu->max_eus_per_subslice = max_eus_per_subslice;
> > -
> > - sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
> > - GEM_BUG_ON(sseu->ss_stride > GEN_MAX_SUBSLICE_STRIDE);
> > }
> >
> > unsigned int
> > @@ -26,54 +25,24 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
> > {
> > unsigned int i, total = 0;
> >
> > - for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
> > - total += hweight8(sseu->subslice_mask[i]);
> > -
> > - return total;
> > -}
> > -
> > -static u32
> > -sseu_get_subslices(const struct sseu_dev_info *sseu,
> > - const u8 *subslice_mask, u8 slice)
> > -{
> > - int i, offset = slice * sseu->ss_stride;
> > - u32 mask = 0;
> > -
> > - GEM_BUG_ON(slice >= sseu->max_slices);
> > -
> > - for (i = 0; i < sseu->ss_stride; i++)
> > - mask |= (u32)subslice_mask[offset + i] << i * BITS_PER_BYTE;
> > -
> > - return mask;
> > -}
> > -
> > -u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
> > -{
> > - return sseu_get_subslices(sseu, sseu->subslice_mask, slice);
> > -}
> > + if (sseu->has_xehp_dss)
> > + return bitmap_weight(sseu->subslice_mask.xehp,
> > + XEHP_BITMAP_BITS(sseu->subslice_mask));
> >
> > -static u32 sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
> > -{
> > - return sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
> > -}
> > + for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++)
> > + total += hweight8(sseu->subslice_mask.hsw[i]);
> >
> > -u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu)
> > -{
> > - return sseu_get_subslices(sseu, sseu->compute_subslice_mask, 0);
> > -}
> > -
> > -void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
> > - u8 *subslice_mask, u32 ss_mask)
> > -{
> > - int offset = slice * sseu->ss_stride;
> > -
> > - memcpy(&subslice_mask[offset], &ss_mask, sseu->ss_stride);
> > + return total;
> > }
> >
> > unsigned int
> > -intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
> > +intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice)
> > {
> > - return hweight32(intel_sseu_get_subslices(sseu, slice));
> > + WARN_ON(sseu->has_xehp_dss);
> > + if (WARN_ON(slice >= sseu->max_slices))
> > + return 0;
> > +
> > + return sseu->subslice_mask.hsw[slice];
> > }
> >
> > static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
> > @@ -147,32 +116,66 @@ int intel_sseu_copy_eumask_to_user(void __user *to,
> > return copy_to_user(to, eu_mask, len);
> > }
> >
> > +/**
> > + * intel_sseu_copy_ssmask_to_user - Copy subslice mask into a userspace buffer
> > + * @to: Pointer to userspace buffer to copy to
> > + * @sseu: SSEU structure containing subslice mask to copy
> > + *
> > + * Copies the subslice mask to a userspace buffer in the format expected by
> > + * the query ioctl's topology queries.
> > + *
> > + * Returns the result of the copy_to_user() operation.
> > + */
> > +int intel_sseu_copy_ssmask_to_user(void __user *to,
> > + const struct sseu_dev_info *sseu)
> > +{
> > + u8 ss_mask[GEN_SS_MASK_SIZE] = {};
> > + int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
> > + int len = sseu->max_slices * ss_stride;
> > + int s, ss, i;
> > +
> > + for (s = 0; s < sseu->max_slices; s++) {
> > + for (ss = 0; ss < sseu->max_subslices; ss++) {
> > + i = s * ss_stride * BITS_PER_BYTE + ss;
> > +
> > + if (!intel_sseu_has_subslice(sseu, s, ss))
> > + continue;
> > +
> > + ss_mask[i / BITS_PER_BYTE] |= BIT(i % BITS_PER_BYTE);
> > + }
> > + }
> > +
> > + return copy_to_user(to, ss_mask, len);
> > +}
> > +
> > static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> > - u32 g_ss_en, u32 c_ss_en, u16 eu_en)
> > + u32 ss_en, u16 eu_en)
> > {
> > u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
> > int ss;
> >
> > - /* g_ss_en/c_ss_en represent entire subslice mask across all slices */
> > - GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
> > - sizeof(g_ss_en) * BITS_PER_BYTE);
> > + sseu->slice_mask |= BIT(0);
> > + sseu->subslice_mask.hsw[0] = ss_en & valid_ss_mask;
> > +
> > + for (ss = 0; ss < sseu->max_subslices; ss++)
> > + if (intel_sseu_has_subslice(sseu, 0, ss))
> > + sseu_set_eus(sseu, 0, ss, eu_en);
> > +
> > + sseu->eu_per_subslice = hweight16(eu_en);
> > + sseu->eu_total = compute_eu_total(sseu);
> > +}
> > +
> > +static void xehp_compute_sseu_info(struct sseu_dev_info *sseu,
> > + u16 eu_en)
> > +{
> > + int ss;
> >
> > sseu->slice_mask |= BIT(0);
> >
> > - /*
> > - * XeHP introduces the concept of compute vs geometry DSS. To reduce
> > - * variation between GENs around subslice usage, store a mask for both
> > - * the geometry and compute enabled masks since userspace will need to
> > - * be able to query these masks independently. Also compute a total
> > - * enabled subslice count for the purposes of selecting subslices to
> > - * use in a particular GEM context.
> > - */
> > - intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
> > - c_ss_en & valid_ss_mask);
> > - intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
> > - g_ss_en & valid_ss_mask);
> > - intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
> > - (g_ss_en | c_ss_en) & valid_ss_mask);
> > + bitmap_or(sseu->subslice_mask.xehp,
> > + sseu->compute_subslice_mask.xehp,
> > + sseu->geometry_subslice_mask.xehp,
> > + XEHP_BITMAP_BITS(sseu->subslice_mask));
> >
> > for (ss = 0; ss < sseu->max_subslices; ss++)
> > if (intel_sseu_has_subslice(sseu, 0, ss))
> > @@ -182,11 +185,31 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> > sseu->eu_total = compute_eu_total(sseu);
> > }
> >
> > +static void
> > +xehp_load_dss_mask(struct intel_uncore *uncore,
> > + intel_sseu_ss_mask_t *ssmask,
> > + int numregs,
> > + ...)
> > +{
> > + va_list argp;
> > + u32 fuse_val[I915_MAX_SS_FUSE_REGS] = {};
> > + int i;
> > +
> > + if (WARN_ON(numregs > I915_MAX_SS_FUSE_REGS))
> > + numregs = I915_MAX_SS_FUSE_REGS;
> > +
> > + va_start(argp, numregs);
> > + for (i = 0; i < numregs; i++)
> > + fuse_val[i] = intel_uncore_read(uncore, va_arg(argp, i915_reg_t));
> > + va_end(argp);
> > +
> > + bitmap_from_arr32(ssmask->xehp, fuse_val, numregs * 32);
> > +}
> > +
> > static void xehp_sseu_info_init(struct intel_gt *gt)
> > {
> > struct sseu_dev_info *sseu = >->info.sseu;
> > struct intel_uncore *uncore = gt->uncore;
> > - u32 g_dss_en, c_dss_en = 0;
> > u16 eu_en = 0;
> > u8 eu_en_fuse;
> > int eu;
> > @@ -200,8 +223,10 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
> > intel_sseu_set_info(sseu, 1, 32, 16);
> > sseu->has_xehp_dss = 1;
> >
> > - g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
> > - c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
> > + xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 1,
> > + GEN12_GT_GEOMETRY_DSS_ENABLE);
> > + xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 1,
> > + GEN12_GT_COMPUTE_DSS_ENABLE);
> >
> > eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
> >
> > @@ -209,7 +234,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
> > if (eu_en_fuse & BIT(eu))
> > eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
> >
> > - gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
> > + xehp_compute_sseu_info(sseu, eu_en);
> > }
> >
> > static void gen12_sseu_info_init(struct intel_gt *gt)
> > @@ -247,7 +272,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
> > if (eu_en_fuse & BIT(eu))
> > eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
> >
> > - gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
> > + gen11_compute_sseu_info(sseu, g_dss_en, eu_en);
> >
> > /* TGL only supports slice-level power gating */
> > sseu->has_slice_pg = 1;
> > @@ -279,7 +304,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
> > eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
> > GEN11_EU_DIS_MASK);
> >
> > - gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
> > + gen11_compute_sseu_info(sseu, ss_en, eu_en);
> >
> > /* ICL has no power gating restrictions. */
> > sseu->has_slice_pg = 1;
> > @@ -291,7 +316,6 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> > {
> > struct sseu_dev_info *sseu = >->info.sseu;
> > u32 fuse;
> > - u8 subslice_mask = 0;
> >
> > fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT);
> >
> > @@ -305,7 +329,7 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> > (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
> > CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
> >
> > - subslice_mask |= BIT(0);
> > + sseu->subslice_mask.hsw[0] |= BIT(0);
> > sseu_set_eus(sseu, 0, 0, ~disabled_mask & 0xFF);
> > }
> >
> > @@ -316,12 +340,10 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> > (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
> > CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
> >
> > - subslice_mask |= BIT(1);
> > + sseu->subslice_mask.hsw[0] |= BIT(1);
> > sseu_set_eus(sseu, 0, 1, ~disabled_mask & 0xFF);
> > }
> >
> > - intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask, subslice_mask);
> > -
> > sseu->eu_total = compute_eu_total(sseu);
> >
> > /*
> > @@ -376,8 +398,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
> > /* skip disabled slice */
> > continue;
> >
> > - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> > - subslice_mask);
> > + sseu->subslice_mask.hsw[s] = subslice_mask;
> >
> > eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
> > for (ss = 0; ss < sseu->max_subslices; ss++) {
> > @@ -434,8 +455,8 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
> > sseu->has_eu_pg = sseu->eu_per_subslice > 2;
> >
> > if (IS_GEN9_LP(i915)) {
> > -#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
> > - info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
> > +#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask.hsw[0] & BIT(ss)))
> > + info->has_pooled_eu = hweight8(sseu->subslice_mask.hsw[0]) == 3;
> >
> > sseu->min_eu_in_pool = 0;
> > if (info->has_pooled_eu) {
> > @@ -489,8 +510,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
> > /* skip disabled slice */
> > continue;
> >
> > - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> > - subslice_mask);
> > + sseu->subslice_mask.hsw[s] = subslice_mask;
> >
> > for (ss = 0; ss < sseu->max_subslices; ss++) {
> > u8 eu_disabled_mask;
> > @@ -587,8 +607,7 @@ static void hsw_sseu_info_init(struct intel_gt *gt)
> > sseu->eu_per_subslice);
> >
> > for (s = 0; s < sseu->max_slices; s++) {
> > - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> > - subslice_mask);
> > + sseu->subslice_mask.hsw[s] = subslice_mask;
> >
> > for (ss = 0; ss < sseu->max_subslices; ss++) {
> > sseu_set_eus(sseu, s, ss,
> > @@ -677,7 +696,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
> > */
> > if (GRAPHICS_VER(i915) == 11 &&
> > slices == 1 &&
> > - subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
> > + subslices > min_t(u8, 4, hweight8(sseu->subslice_mask.hsw[0]) / 2)) {
> > GEM_BUG_ON(subslices & 1);
> >
> > subslice_pg = false;
> > @@ -743,14 +762,29 @@ void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
> > {
> > int s;
> >
> > - drm_printf(p, "slice total: %u, mask=%04x\n",
> > - hweight8(sseu->slice_mask), sseu->slice_mask);
> > - drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
> > - for (s = 0; s < sseu->max_slices; s++) {
> > - drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
> > - s, intel_sseu_subslices_per_slice(sseu, s),
> > - intel_sseu_get_subslices(sseu, s));
> > + if (sseu->has_xehp_dss) {
> > + drm_printf(p, "subslice total: %u\n",
> > + intel_sseu_subslice_total(sseu));
> > + drm_printf(p, "geometry dss mask=%*pb\n",
> > + XEHP_BITMAP_BITS(sseu->geometry_subslice_mask),
> > + sseu->geometry_subslice_mask.xehp);
> > + drm_printf(p, "compute dss mask=%*pb\n",
> > + XEHP_BITMAP_BITS(sseu->compute_subslice_mask),
> > + sseu->compute_subslice_mask.xehp);
> > + } else {
> > + drm_printf(p, "slice total: %u, mask=%04x\n",
> > + hweight8(sseu->slice_mask), sseu->slice_mask);
> > + drm_printf(p, "subslice total: %u\n",
> > + intel_sseu_subslice_total(sseu));
> > +
> > + for (s = 0; s < sseu->max_slices; s++) {
> > + u8 ss_mask = sseu->subslice_mask.hsw[s];
> > +
> > + drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
> > + s, hweight8(ss_mask), ss_mask);
> > + }
> > }
> > +
> > drm_printf(p, "EU total: %u\n", sseu->eu_total);
> > drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
> > drm_printf(p, "has slice power gating: %s\n",
> > @@ -767,9 +801,10 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
> > int s, ss;
> >
> > for (s = 0; s < sseu->max_slices; s++) {
> > + u8 ss_mask = sseu->subslice_mask.hsw[s];
> > +
> > drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
> > - s, intel_sseu_subslices_per_slice(sseu, s),
> > - intel_sseu_get_subslices(sseu, s));
> > + s, hweight8(ss_mask), ss_mask);
> >
> > for (ss = 0; ss < sseu->max_subslices; ss++) {
> > u16 enabled_eus = sseu_get_eus(sseu, s, ss);
> > @@ -783,16 +818,14 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
> > static void sseu_print_xehp_topology(const struct sseu_dev_info *sseu,
> > struct drm_printer *p)
> > {
> > - u32 g_dss_mask = sseu_get_geometry_subslices(sseu);
> > - u32 c_dss_mask = intel_sseu_get_compute_subslices(sseu);
> > int dss;
> >
> > for (dss = 0; dss < sseu->max_subslices; dss++) {
> > u16 enabled_eus = sseu_get_eus(sseu, 0, dss);
> >
> > drm_printf(p, "DSS_%02d: G:%3s C:%3s, %2u EUs (0x%04hx)\n", dss,
> > - str_yes_no(g_dss_mask & BIT(dss)),
> > - str_yes_no(c_dss_mask & BIT(dss)),
> > + str_yes_no(test_bit(dss, sseu->geometry_subslice_mask.xehp)),
> > + str_yes_no(test_bit(dss, sseu->compute_subslice_mask.xehp)),
> > hweight16(enabled_eus), enabled_eus);
> > }
> > }
> > @@ -810,20 +843,44 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
> > }
> > }
> >
> > -u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice)
> > +void intel_sseu_print_ss_info(const char* type,
> > + const struct sseu_dev_info *sseu,
> > + struct seq_file *m)
> > +{
> > + int s;
> > +
> > + if (sseu->has_xehp_dss) {
> > + seq_printf(m, " %s Geometry DSS: %u\n", type,
> > + bitmap_weight(sseu->geometry_subslice_mask.xehp,
> > + XEHP_BITMAP_BITS(sseu->geometry_subslice_mask)));
> > + seq_printf(m, " %s Compute DSS: %u\n", type,
> > + bitmap_weight(sseu->compute_subslice_mask.xehp,
> > + XEHP_BITMAP_BITS(sseu->compute_subslice_mask)));
> > + } else {
> > + for (s = 0; s < fls(sseu->slice_mask); s++)
> > + seq_printf(m, " %s Slice%i subslices: %u\n", type,
> > + s, hweight8(sseu->subslice_mask.hsw[s]));
> > + }
> > +}
> > +
> > +u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask,
> > + int dss_per_slice)
> > {
> > + intel_sseu_ss_mask_t per_slice_mask = {};
> > u16 slice_mask = 0;
> > int i;
> >
> > - WARN_ON(sizeof(dss_mask) * 8 / dss_per_slice > 8 * sizeof(slice_mask));
> > + WARN_ON(DIV_ROUND_UP(XEHP_BITMAP_BITS(dss_mask), dss_per_slice) >
> > + 8 * sizeof(slice_mask));
> >
> > - for (i = 0; dss_mask; i++) {
> > - if (dss_mask & GENMASK(dss_per_slice - 1, 0))
> > + bitmap_fill(per_slice_mask.xehp, dss_per_slice);
> > + for (i = 0; !bitmap_empty(dss_mask.xehp, XEHP_BITMAP_BITS(dss_mask)); i++) {
> > + if (bitmap_intersects(dss_mask.xehp, per_slice_mask.xehp, dss_per_slice))
> > slice_mask |= BIT(i);
> >
> > - dss_mask >>= dss_per_slice;
> > + bitmap_shift_right(dss_mask.xehp, dss_mask.xehp, dss_per_slice,
> > + XEHP_BITMAP_BITS(dss_mask));
> > }
> >
> > return slice_mask;
> > }
> > -
> > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > index ffa375e68959..e7f336a7ffbb 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > @@ -25,12 +25,16 @@ struct drm_printer;
> > /*
> > * Maximum number of subslices that can exist within a HSW-style slice. This
> > * is only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the
> > - * GEN_MAX_DSS value below).
> > + * I915_MAX_SS_FUSE_BITS value below).
> > */
> > #define GEN_MAX_SS_PER_HSW_SLICE 6
> >
> > -/* Maximum number of DSS on newer platforms (Xe_HP and beyond). */
> > -#define GEN_MAX_DSS 32
> > +/*
> > + * Maximum number of 32-bit registers used by hardware to express the
> > + * enabled/disabled subslices.
> > + */
> > +#define I915_MAX_SS_FUSE_REGS 1
> > +#define I915_MAX_SS_FUSE_BITS (I915_MAX_SS_FUSE_REGS * 32)
> >
> > /* Maximum number of EUs that can exist within a subslice or DSS. */
> > #define GEN_MAX_EUS_PER_SS 16
> > @@ -38,7 +42,7 @@ struct drm_printer;
> > #define SSEU_MAX(a, b) ((a) > (b) ? (a) : (b))
> >
> > /* The maximum number of bits needed to express each subslice/DSS independently */
> > -#define GEN_SS_MASK_SIZE SSEU_MAX(GEN_MAX_DSS, \
> > +#define GEN_SS_MASK_SIZE SSEU_MAX(I915_MAX_SS_FUSE_BITS, \
> > GEN_MAX_HSW_SLICES * GEN_MAX_SS_PER_HSW_SLICE)
> >
> > #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
> > @@ -49,17 +53,24 @@ struct drm_printer;
> > #define GEN_DSS_PER_CSLICE 8
> > #define GEN_DSS_PER_MSLICE 8
> >
> > -#define GEN_MAX_GSLICES (GEN_MAX_DSS / GEN_DSS_PER_GSLICE)
> > -#define GEN_MAX_CSLICES (GEN_MAX_DSS / GEN_DSS_PER_CSLICE)
> > +#define GEN_MAX_GSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_GSLICE)
> > +#define GEN_MAX_CSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_CSLICE)
> > +
> > +typedef union {
> > + u8 hsw[GEN_MAX_HSW_SLICES];
> > +
> > + /* Bitmap compatible with linux/bitmap.h; may exceed size of u64 */
> > + unsigned long xehp[BITS_TO_LONGS(I915_MAX_SS_FUSE_BITS)];
> > +} intel_sseu_ss_mask_t;
> >
> > struct sseu_dev_info {
> > u8 slice_mask;
> > - u8 subslice_mask[GEN_SS_MASK_SIZE];
> > - u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
> > - u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
> > + intel_sseu_ss_mask_t subslice_mask;
> > + intel_sseu_ss_mask_t geometry_subslice_mask;
> > + intel_sseu_ss_mask_t compute_subslice_mask;
> > union {
> > u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
> > - u16 xehp[GEN_MAX_DSS];
> > + u16 xehp[I915_MAX_SS_FUSE_BITS];
> > } eu_mask;
> >
> > u16 eu_total;
> > @@ -80,8 +91,6 @@ struct sseu_dev_info {
> > u8 max_slices;
> > u8 max_subslices;
> > u8 max_eus_per_subslice;
> > -
> > - u8 ss_stride;
> > };
> >
> > /*
> > @@ -99,7 +108,7 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
> > {
> > struct intel_sseu value = {
> > .slice_mask = sseu->slice_mask,
> > - .subslice_mask = sseu->subslice_mask[0],
> > + .subslice_mask = sseu->subslice_mask.hsw[0],
> > .min_eus_per_subslice = sseu->max_eus_per_subslice,
> > .max_eus_per_subslice = sseu->max_eus_per_subslice,
> > };
> > @@ -111,18 +120,27 @@ static inline bool
> > intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
> > int subslice)
> > {
> > - u8 mask;
> > - int ss_idx = subslice / BITS_PER_BYTE;
> > -
> > if (slice >= sseu->max_slices ||
> > subslice >= sseu->max_subslices)
> > return false;
> >
> > - GEM_BUG_ON(ss_idx >= sseu->ss_stride);
> > -
> > - mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx];
> > + if (sseu->has_xehp_dss)
> > + return test_bit(subslice, sseu->subslice_mask.xehp);
> > + else
> > + return sseu->subslice_mask.hsw[slice] & BIT(subslice);
> > +}
> >
> > - return mask & BIT(subslice % BITS_PER_BYTE);
> > +/*
> > + * Used to obtain the index of the first DSS. Can start searching from the
> > + * beginning of a specific dss group (e.g., gslice, cslice, etc.) if
> > + * groupsize and groupnum are non-zero.
> > + */
> > +static inline unsigned int
> > +intel_sseu_find_first_xehp_dss(const struct sseu_dev_info *sseu, int groupsize,
> > + int groupnum)
> > +{
> > + return find_next_bit(sseu->subslice_mask.xehp, I915_MAX_SS_FUSE_BITS,
> > + groupnum * groupsize);
> Any specific reason for not replacing I915_MAX_SS_FUSE_BITS with
> XEHP_BITMAP_BITS here?
It looks like I just missed this one while changing the others. I'll
send an update that makes that change.
Matt
>
> Regards,
> Bala
> > }
> >
> > void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
> > @@ -132,14 +150,10 @@ unsigned int
> > intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
> >
> > unsigned int
> > -intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
> > -
> > -u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
> > +intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice);
> >
> > -u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
> > -
> > -void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
> > - u8 *subslice_mask, u32 ss_mask);
> > +intel_sseu_ss_mask_t
> > +intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
> >
> > void intel_sseu_info_init(struct intel_gt *gt);
> >
> > @@ -151,9 +165,15 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
> > const struct sseu_dev_info *sseu,
> > struct drm_printer *p);
> >
> > -u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
> > +u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask, int dss_per_slice);
> >
> > int intel_sseu_copy_eumask_to_user(void __user *to,
> > const struct sseu_dev_info *sseu);
> > +int intel_sseu_copy_ssmask_to_user(void __user *to,
> > + const struct sseu_dev_info *sseu);
> > +
> > +void intel_sseu_print_ss_info(const char* type,
> > + const struct sseu_dev_info *sseu,
> > + struct seq_file *m);
> >
> > #endif /* __INTEL_SSEU_H__ */
> > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> > index 2d5d011e01db..c2ee5e1826b5 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> > @@ -4,6 +4,7 @@
> > * Copyright © 2020 Intel Corporation
> > */
> >
> > +#include <linux/bitmap.h>
> > #include <linux/string_helpers.h>
> >
> > #include "i915_drv.h"
> > @@ -11,14 +12,6 @@
> > #include "intel_gt_regs.h"
> > #include "intel_sseu_debugfs.h"
> >
> > -static void sseu_copy_subslices(const struct sseu_dev_info *sseu,
> > - int slice, u8 *to_mask)
> > -{
> > - int offset = slice * sseu->ss_stride;
> > -
> > - memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
> > -}
> > -
> > static void cherryview_sseu_device_status(struct intel_gt *gt,
> > struct sseu_dev_info *sseu)
> > {
> > @@ -41,7 +34,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt,
> > continue;
> >
> > sseu->slice_mask = BIT(0);
> > - sseu->subslice_mask[0] |= BIT(ss);
> > + sseu->subslice_mask.hsw[0] |= BIT(ss);
> > eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
> > ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
> > ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
> > @@ -92,7 +85,7 @@ static void gen11_sseu_device_status(struct intel_gt *gt,
> > continue;
> >
> > sseu->slice_mask |= BIT(s);
> > - sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
> > + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
> >
> > for (ss = 0; ss < info->sseu.max_subslices; ss++) {
> > unsigned int eu_cnt;
> > @@ -147,21 +140,17 @@ static void gen9_sseu_device_status(struct intel_gt *gt,
> > sseu->slice_mask |= BIT(s);
> >
> > if (IS_GEN9_BC(gt->i915))
> > - sseu_copy_subslices(&info->sseu, s,
> > - sseu->subslice_mask);
> > + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
> >
> > for (ss = 0; ss < info->sseu.max_subslices; ss++) {
> > unsigned int eu_cnt;
> > - u8 ss_idx = s * info->sseu.ss_stride +
> > - ss / BITS_PER_BYTE;
> >
> > if (IS_GEN9_LP(gt->i915)) {
> > if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> > /* skip disabled subslice */
> > continue;
> >
> > - sseu->subslice_mask[ss_idx] |=
> > - BIT(ss % BITS_PER_BYTE);
> > + sseu->subslice_mask.hsw[s] |= BIT(ss);
> > }
> >
> > eu_cnt = eu_reg[2 * s + ss / 2] & eu_mask[ss % 2];
> > @@ -188,8 +177,7 @@ static void bdw_sseu_device_status(struct intel_gt *gt,
> > if (sseu->slice_mask) {
> > sseu->eu_per_subslice = info->sseu.eu_per_subslice;
> > for (s = 0; s < fls(sseu->slice_mask); s++)
> > - sseu_copy_subslices(&info->sseu, s,
> > - sseu->subslice_mask);
> > + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
> > sseu->eu_total = sseu->eu_per_subslice *
> > intel_sseu_subslice_total(sseu);
> >
> > @@ -208,7 +196,6 @@ static void i915_print_sseu_info(struct seq_file *m,
> > const struct sseu_dev_info *sseu)
> > {
> > const char *type = is_available_info ? "Available" : "Enabled";
> > - int s;
> >
> > seq_printf(m, " %s Slice Mask: %04x\n", type,
> > sseu->slice_mask);
> > @@ -216,10 +203,7 @@ static void i915_print_sseu_info(struct seq_file *m,
> > hweight8(sseu->slice_mask));
> > seq_printf(m, " %s Subslice Total: %u\n", type,
> > intel_sseu_subslice_total(sseu));
> > - for (s = 0; s < fls(sseu->slice_mask); s++) {
> > - seq_printf(m, " %s Slice%i subslices: %u\n", type,
> > - s, intel_sseu_subslices_per_slice(sseu, s));
> > - }
> > + intel_sseu_print_ss_info(type, sseu, m);
> > seq_printf(m, " %s EU Total: %u\n", type,
> > sseu->eu_total);
> > seq_printf(m, " %s EU Per Subslice: %u\n", type,
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 73b59ea6fd3b..1bf62273e02d 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -948,8 +948,8 @@ gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> > * on s/ss combo, the read should be done with read_subslice_reg.
> > */
> > slice = ffs(sseu->slice_mask) - 1;
> > - GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
> > - subslice = ffs(intel_sseu_get_subslices(sseu, slice));
> > + GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw));
> > + subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice));
> > GEM_BUG_ON(!subslice);
> > subslice--;
> >
> > @@ -1087,11 +1087,10 @@ static void
> > icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> > {
> > const struct sseu_dev_info *sseu = >->info.sseu;
> > - unsigned int slice, subslice;
> > + unsigned int subslice;
> >
> > GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
> > GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
> > - slice = 0;
> >
> > /*
> > * Although a platform may have subslices, we need to always steer
> > @@ -1102,7 +1101,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> > * one of the higher subslices, we run the risk of reading back 0's or
> > * random garbage.
> > */
> > - subslice = __ffs(intel_sseu_get_subslices(sseu, slice));
> > + subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0));
> >
> > /*
> > * If the subslice we picked above also steers us to a valid L3 bank,
> > @@ -1112,7 +1111,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> > if (gt->info.l3bank_mask & BIT(subslice))
> > gt->steering_table[L3BANK] = NULL;
> >
> > - __add_mcr_wa(gt, wal, slice, subslice);
> > + __add_mcr_wa(gt, wal, 0, subslice);
> > }
> >
> > static void
> > @@ -1120,7 +1119,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> > {
> > const struct sseu_dev_info *sseu = >->info.sseu;
> > unsigned long slice, subslice = 0, slice_mask = 0;
> > - u64 dss_mask = 0;
> > u32 lncf_mask = 0;
> > int i;
> >
> > @@ -1151,8 +1149,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> > */
> >
> > /* Find the potential gslice candidates */
> > - dss_mask = intel_sseu_get_subslices(sseu, 0);
> > - slice_mask = intel_slicemask_from_dssmask(dss_mask, GEN_DSS_PER_GSLICE);
> > + slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask,
> > + GEN_DSS_PER_GSLICE);
> >
> > /*
> > * Find the potential LNCF candidates. Either LNCF within a valid
> > @@ -1177,9 +1175,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> > }
> >
> > slice = __ffs(slice_mask);
> > - subslice = __ffs(dss_mask >> (slice * GEN_DSS_PER_GSLICE));
> > + subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice);
> > WARN_ON(subslice > GEN_DSS_PER_GSLICE);
> > - WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0);
> >
> > __add_mcr_wa(gt, wal, slice, subslice);
> >
> > @@ -2030,9 +2027,8 @@ engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> >
> > static bool needs_wa_1308578152(struct intel_engine_cs *engine)
> > {
> > - u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0);
> > -
> > - return (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0;
> > + return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >
> > + GEN_DSS_PER_GSLICE;
> > }
> >
> > static void
> > diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
> > index ac9767c56619..6fd15b39570c 100644
> > --- a/drivers/gpu/drm/i915/i915_getparam.c
> > +++ b/drivers/gpu/drm/i915/i915_getparam.c
> > @@ -162,8 +162,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
> > return -EINVAL;
> >
> > /* Only copy bits from the first slice */
> > - memcpy(&value, sseu->subslice_mask,
> > - min(sseu->ss_stride, (u8)sizeof(value)));
> > + value = intel_sseu_get_hsw_subslices(sseu, 0);
> > if (!value)
> > return -ENODEV;
> > break;
> > diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> > index 89c475d525b8..0094f67c63f2 100644
> > --- a/drivers/gpu/drm/i915/i915_query.c
> > +++ b/drivers/gpu/drm/i915/i915_query.c
> > @@ -31,10 +31,11 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
> >
> > static int fill_topology_info(const struct sseu_dev_info *sseu,
> > struct drm_i915_query_item *query_item,
> > - const u8 *subslice_mask)
> > + intel_sseu_ss_mask_t subslice_mask)
> > {
> > struct drm_i915_query_topology_info topo;
> > u32 slice_length, subslice_length, eu_length, total_length;
> > + int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
> > int eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
> > int ret;
> >
> > @@ -44,7 +45,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
> > return -ENODEV;
> >
> > slice_length = sizeof(sseu->slice_mask);
> > - subslice_length = sseu->max_slices * sseu->ss_stride;
> > + subslice_length = sseu->max_slices * ss_stride;
> > eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
> > total_length = sizeof(topo) + slice_length + subslice_length +
> > eu_length;
> > @@ -60,7 +61,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
> > topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
> >
> > topo.subslice_offset = slice_length;
> > - topo.subslice_stride = sseu->ss_stride;
> > + topo.subslice_stride = ss_stride;
> > topo.eu_offset = slice_length + subslice_length;
> > topo.eu_stride = eu_stride;
> >
> > @@ -72,9 +73,9 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
> > &sseu->slice_mask, slice_length))
> > return -EFAULT;
> >
> > - if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
> > - sizeof(topo) + slice_length),
> > - subslice_mask, subslice_length))
> > + if (intel_sseu_copy_ssmask_to_user(u64_to_user_ptr(query_item->data_ptr +
> > + sizeof(topo) + slice_length),
> > + sseu))
> > return -EFAULT;
> >
> > if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
> > --
> > 2.35.3
> >
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v5 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi
@ 2022-06-01 14:40 ` Matt Roper
0 siblings, 0 replies; 36+ messages in thread
From: Matt Roper @ 2022-06-01 14:40 UTC (permalink / raw)
To: Balasubramani Vivekanandan; +Cc: intel-gfx, dri-devel
On Wed, Jun 01, 2022 at 01:48:56PM +0530, Balasubramani Vivekanandan wrote:
> On 23.05.2022 13:45, Matt Roper wrote:
> > As with EU masks, it's easier to store subslice/DSS masks internally in
> > a format that's more natural for the driver to work with, and then only
> > covert into the u8[] uapi form when the query ioctl is invoked. Since
> > the hardware design changed significantly with Xe_HP, we'll use a union
> > to choose between the old "hsw-style" subslice masks or the newer xehp
> > mask. HSW-style masks will be stored in an array of u8's, indexed by
> > slice (there's never more than 6 subslices per slice on older
> > platforms). For Xe_HP and beyond where slices no longer exist, we only
> > need a single bitmask. However we already know that this mask is
> > eventually going to grow too large for a simple u64 to hold, so we'll
> > represent it in a manner that can be operated on by the utilities in
> > linux/bitmap.h.
> >
> > v2:
> > - Fix typo: BIT(s) -> BIT(ss) in gen9_sseu_device_status()
> >
> > v3:
> > - Eliminate sseu->ss_stride and just calculate the stride while
> > specifically handling uapi. (Tvrtko)
> > - Use BITMAP_BITS() macro to refer to size of masks rather than
> > passing I915_MAX_SS_FUSE_BITS directly. (Tvrtko)
> > - Report compute/geometry DSS masks separately when dumping Xe_HP SSEU
> > info. (Tvrtko)
> > - Restore dropped range checks to intel_sseu_has_subslice(). (Tvrtko)
> >
> > v4:
> > - Make the bitmap size macro check the size of the .xehp field rather
> > than the containing union. (Tvrtko)
> > - Don't add GEM_BUG_ON() intel_sseu_has_subslice()'s check for whether
> > slice or subslice ID exceed sseu->max_[sub]slices; various loops
> > in the driver are expected to exceed these, so we should just
> > silently return 'false.'
> >
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 +-
> > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
> > drivers/gpu/drm/i915/gt/intel_gt.c | 12 +-
> > drivers/gpu/drm/i915/gt/intel_sseu.c | 261 +++++++++++--------
> > drivers/gpu/drm/i915/gt/intel_sseu.h | 76 ++++--
> > drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 30 +--
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +-
> > drivers/gpu/drm/i915/i915_getparam.c | 3 +-
> > drivers/gpu/drm/i915/i915_query.c | 13 +-
> > 9 files changed, 241 insertions(+), 187 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > index ab4c5ab28e4d..a3bb73f5d53b 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > @@ -1875,6 +1875,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> > {
> > const struct sseu_dev_info *device = >->info.sseu;
> > struct drm_i915_private *i915 = gt->i915;
> > + unsigned int dev_subslice_mask = intel_sseu_get_hsw_subslices(device, 0);
> >
> > /* No zeros in any field. */
> > if (!user->slice_mask || !user->subslice_mask ||
> > @@ -1901,7 +1902,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> > if (user->slice_mask & ~device->slice_mask)
> > return -EINVAL;
> >
> > - if (user->subslice_mask & ~device->subslice_mask[0])
> > + if (user->subslice_mask & ~dev_subslice_mask)
> > return -EINVAL;
> >
> > if (user->max_eus_per_subslice > device->max_eus_per_subslice)
> > @@ -1915,7 +1916,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
> > /* Part specific restrictions. */
> > if (GRAPHICS_VER(i915) == 11) {
> > unsigned int hw_s = hweight8(device->slice_mask);
> > - unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
> > + unsigned int hw_ss_per_s = hweight8(dev_subslice_mask);
> > unsigned int req_s = hweight8(context->slice_mask);
> > unsigned int req_ss = hweight8(context->subslice_mask);
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > index 1adbf34c3632..f0acf8518a51 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > @@ -674,8 +674,8 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
> > if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))
> > return;
> >
> > - ccs_mask = intel_slicemask_from_dssmask(intel_sseu_get_compute_subslices(&info->sseu),
> > - ss_per_ccs);
> > + ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
> > + ss_per_ccs);
> > /*
> > * If all DSS in a quadrant are fused off, the corresponding CCS
> > * engine is not available for use.
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> > index 034182f85501..2921f510642f 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > @@ -133,13 +133,6 @@ static const struct intel_mmio_range dg2_lncf_steering_table[] = {
> > {},
> > };
> >
> > -static u16 slicemask(struct intel_gt *gt, int count)
> > -{
> > - u64 dss_mask = intel_sseu_get_subslices(>->info.sseu, 0);
> > -
> > - return intel_slicemask_from_dssmask(dss_mask, count);
> > -}
> > -
> > int intel_gt_init_mmio(struct intel_gt *gt)
> > {
> > struct drm_i915_private *i915 = gt->i915;
> > @@ -155,9 +148,12 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> > */
> > if (HAS_MSLICES(i915)) {
> > gt->info.mslice_mask =
> > - slicemask(gt, GEN_DSS_PER_MSLICE) |
> > + intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask,
> > + GEN_DSS_PER_MSLICE);
> > + gt->info.mslice_mask |=
> > (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> > GEN12_MEML3_EN_MASK);
> > +
> > if (!gt->info.mslice_mask) /* should be impossible! */
> > drm_warn(&i915->drm, "mslice mask all zero!\n");
> > }
> > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> > index 285cfd758bdc..3a721db20290 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> > @@ -10,15 +10,14 @@
> > #include "intel_gt_regs.h"
> > #include "intel_sseu.h"
> >
> > +#define XEHP_BITMAP_BITS(mask) ((int)BITS_PER_TYPE(typeof(mask.xehp)))
> > +
> > void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
> > u8 max_subslices, u8 max_eus_per_subslice)
> > {
> > sseu->max_slices = max_slices;
> > sseu->max_subslices = max_subslices;
> > sseu->max_eus_per_subslice = max_eus_per_subslice;
> > -
> > - sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
> > - GEM_BUG_ON(sseu->ss_stride > GEN_MAX_SUBSLICE_STRIDE);
> > }
> >
> > unsigned int
> > @@ -26,54 +25,24 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
> > {
> > unsigned int i, total = 0;
> >
> > - for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
> > - total += hweight8(sseu->subslice_mask[i]);
> > -
> > - return total;
> > -}
> > -
> > -static u32
> > -sseu_get_subslices(const struct sseu_dev_info *sseu,
> > - const u8 *subslice_mask, u8 slice)
> > -{
> > - int i, offset = slice * sseu->ss_stride;
> > - u32 mask = 0;
> > -
> > - GEM_BUG_ON(slice >= sseu->max_slices);
> > -
> > - for (i = 0; i < sseu->ss_stride; i++)
> > - mask |= (u32)subslice_mask[offset + i] << i * BITS_PER_BYTE;
> > -
> > - return mask;
> > -}
> > -
> > -u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
> > -{
> > - return sseu_get_subslices(sseu, sseu->subslice_mask, slice);
> > -}
> > + if (sseu->has_xehp_dss)
> > + return bitmap_weight(sseu->subslice_mask.xehp,
> > + XEHP_BITMAP_BITS(sseu->subslice_mask));
> >
> > -static u32 sseu_get_geometry_subslices(const struct sseu_dev_info *sseu)
> > -{
> > - return sseu_get_subslices(sseu, sseu->geometry_subslice_mask, 0);
> > -}
> > + for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++)
> > + total += hweight8(sseu->subslice_mask.hsw[i]);
> >
> > -u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu)
> > -{
> > - return sseu_get_subslices(sseu, sseu->compute_subslice_mask, 0);
> > -}
> > -
> > -void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
> > - u8 *subslice_mask, u32 ss_mask)
> > -{
> > - int offset = slice * sseu->ss_stride;
> > -
> > - memcpy(&subslice_mask[offset], &ss_mask, sseu->ss_stride);
> > + return total;
> > }
> >
> > unsigned int
> > -intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
> > +intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice)
> > {
> > - return hweight32(intel_sseu_get_subslices(sseu, slice));
> > + WARN_ON(sseu->has_xehp_dss);
> > + if (WARN_ON(slice >= sseu->max_slices))
> > + return 0;
> > +
> > + return sseu->subslice_mask.hsw[slice];
> > }
> >
> > static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
> > @@ -147,32 +116,66 @@ int intel_sseu_copy_eumask_to_user(void __user *to,
> > return copy_to_user(to, eu_mask, len);
> > }
> >
> > +/**
> > + * intel_sseu_copy_ssmask_to_user - Copy subslice mask into a userspace buffer
> > + * @to: Pointer to userspace buffer to copy to
> > + * @sseu: SSEU structure containing subslice mask to copy
> > + *
> > + * Copies the subslice mask to a userspace buffer in the format expected by
> > + * the query ioctl's topology queries.
> > + *
> > + * Returns the result of the copy_to_user() operation.
> > + */
> > +int intel_sseu_copy_ssmask_to_user(void __user *to,
> > + const struct sseu_dev_info *sseu)
> > +{
> > + u8 ss_mask[GEN_SS_MASK_SIZE] = {};
> > + int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
> > + int len = sseu->max_slices * ss_stride;
> > + int s, ss, i;
> > +
> > + for (s = 0; s < sseu->max_slices; s++) {
> > + for (ss = 0; ss < sseu->max_subslices; ss++) {
> > + i = s * ss_stride * BITS_PER_BYTE + ss;
> > +
> > + if (!intel_sseu_has_subslice(sseu, s, ss))
> > + continue;
> > +
> > + ss_mask[i / BITS_PER_BYTE] |= BIT(i % BITS_PER_BYTE);
> > + }
> > + }
> > +
> > + return copy_to_user(to, ss_mask, len);
> > +}
> > +
> > static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> > - u32 g_ss_en, u32 c_ss_en, u16 eu_en)
> > + u32 ss_en, u16 eu_en)
> > {
> > u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0);
> > int ss;
> >
> > - /* g_ss_en/c_ss_en represent entire subslice mask across all slices */
> > - GEM_BUG_ON(sseu->max_slices * sseu->max_subslices >
> > - sizeof(g_ss_en) * BITS_PER_BYTE);
> > + sseu->slice_mask |= BIT(0);
> > + sseu->subslice_mask.hsw[0] = ss_en & valid_ss_mask;
> > +
> > + for (ss = 0; ss < sseu->max_subslices; ss++)
> > + if (intel_sseu_has_subslice(sseu, 0, ss))
> > + sseu_set_eus(sseu, 0, ss, eu_en);
> > +
> > + sseu->eu_per_subslice = hweight16(eu_en);
> > + sseu->eu_total = compute_eu_total(sseu);
> > +}
> > +
> > +static void xehp_compute_sseu_info(struct sseu_dev_info *sseu,
> > + u16 eu_en)
> > +{
> > + int ss;
> >
> > sseu->slice_mask |= BIT(0);
> >
> > - /*
> > - * XeHP introduces the concept of compute vs geometry DSS. To reduce
> > - * variation between GENs around subslice usage, store a mask for both
> > - * the geometry and compute enabled masks since userspace will need to
> > - * be able to query these masks independently. Also compute a total
> > - * enabled subslice count for the purposes of selecting subslices to
> > - * use in a particular GEM context.
> > - */
> > - intel_sseu_set_subslices(sseu, 0, sseu->compute_subslice_mask,
> > - c_ss_en & valid_ss_mask);
> > - intel_sseu_set_subslices(sseu, 0, sseu->geometry_subslice_mask,
> > - g_ss_en & valid_ss_mask);
> > - intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask,
> > - (g_ss_en | c_ss_en) & valid_ss_mask);
> > + bitmap_or(sseu->subslice_mask.xehp,
> > + sseu->compute_subslice_mask.xehp,
> > + sseu->geometry_subslice_mask.xehp,
> > + XEHP_BITMAP_BITS(sseu->subslice_mask));
> >
> > for (ss = 0; ss < sseu->max_subslices; ss++)
> > if (intel_sseu_has_subslice(sseu, 0, ss))
> > @@ -182,11 +185,31 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu,
> > sseu->eu_total = compute_eu_total(sseu);
> > }
> >
> > +static void
> > +xehp_load_dss_mask(struct intel_uncore *uncore,
> > + intel_sseu_ss_mask_t *ssmask,
> > + int numregs,
> > + ...)
> > +{
> > + va_list argp;
> > + u32 fuse_val[I915_MAX_SS_FUSE_REGS] = {};
> > + int i;
> > +
> > + if (WARN_ON(numregs > I915_MAX_SS_FUSE_REGS))
> > + numregs = I915_MAX_SS_FUSE_REGS;
> > +
> > + va_start(argp, numregs);
> > + for (i = 0; i < numregs; i++)
> > + fuse_val[i] = intel_uncore_read(uncore, va_arg(argp, i915_reg_t));
> > + va_end(argp);
> > +
> > + bitmap_from_arr32(ssmask->xehp, fuse_val, numregs * 32);
> > +}
> > +
> > static void xehp_sseu_info_init(struct intel_gt *gt)
> > {
> > struct sseu_dev_info *sseu = >->info.sseu;
> > struct intel_uncore *uncore = gt->uncore;
> > - u32 g_dss_en, c_dss_en = 0;
> > u16 eu_en = 0;
> > u8 eu_en_fuse;
> > int eu;
> > @@ -200,8 +223,10 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
> > intel_sseu_set_info(sseu, 1, 32, 16);
> > sseu->has_xehp_dss = 1;
> >
> > - g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE);
> > - c_dss_en = intel_uncore_read(uncore, GEN12_GT_COMPUTE_DSS_ENABLE);
> > + xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 1,
> > + GEN12_GT_GEOMETRY_DSS_ENABLE);
> > + xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 1,
> > + GEN12_GT_COMPUTE_DSS_ENABLE);
> >
> > eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK;
> >
> > @@ -209,7 +234,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
> > if (eu_en_fuse & BIT(eu))
> > eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
> >
> > - gen11_compute_sseu_info(sseu, g_dss_en, c_dss_en, eu_en);
> > + xehp_compute_sseu_info(sseu, eu_en);
> > }
> >
> > static void gen12_sseu_info_init(struct intel_gt *gt)
> > @@ -247,7 +272,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt)
> > if (eu_en_fuse & BIT(eu))
> > eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1);
> >
> > - gen11_compute_sseu_info(sseu, g_dss_en, 0, eu_en);
> > + gen11_compute_sseu_info(sseu, g_dss_en, eu_en);
> >
> > /* TGL only supports slice-level power gating */
> > sseu->has_slice_pg = 1;
> > @@ -279,7 +304,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt)
> > eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) &
> > GEN11_EU_DIS_MASK);
> >
> > - gen11_compute_sseu_info(sseu, ss_en, 0, eu_en);
> > + gen11_compute_sseu_info(sseu, ss_en, eu_en);
> >
> > /* ICL has no power gating restrictions. */
> > sseu->has_slice_pg = 1;
> > @@ -291,7 +316,6 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> > {
> > struct sseu_dev_info *sseu = >->info.sseu;
> > u32 fuse;
> > - u8 subslice_mask = 0;
> >
> > fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT);
> >
> > @@ -305,7 +329,7 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> > (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
> > CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
> >
> > - subslice_mask |= BIT(0);
> > + sseu->subslice_mask.hsw[0] |= BIT(0);
> > sseu_set_eus(sseu, 0, 0, ~disabled_mask & 0xFF);
> > }
> >
> > @@ -316,12 +340,10 @@ static void cherryview_sseu_info_init(struct intel_gt *gt)
> > (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
> > CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
> >
> > - subslice_mask |= BIT(1);
> > + sseu->subslice_mask.hsw[0] |= BIT(1);
> > sseu_set_eus(sseu, 0, 1, ~disabled_mask & 0xFF);
> > }
> >
> > - intel_sseu_set_subslices(sseu, 0, sseu->subslice_mask, subslice_mask);
> > -
> > sseu->eu_total = compute_eu_total(sseu);
> >
> > /*
> > @@ -376,8 +398,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
> > /* skip disabled slice */
> > continue;
> >
> > - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> > - subslice_mask);
> > + sseu->subslice_mask.hsw[s] = subslice_mask;
> >
> > eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s));
> > for (ss = 0; ss < sseu->max_subslices; ss++) {
> > @@ -434,8 +455,8 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
> > sseu->has_eu_pg = sseu->eu_per_subslice > 2;
> >
> > if (IS_GEN9_LP(i915)) {
> > -#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss)))
> > - info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
> > +#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask.hsw[0] & BIT(ss)))
> > + info->has_pooled_eu = hweight8(sseu->subslice_mask.hsw[0]) == 3;
> >
> > sseu->min_eu_in_pool = 0;
> > if (info->has_pooled_eu) {
> > @@ -489,8 +510,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt)
> > /* skip disabled slice */
> > continue;
> >
> > - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> > - subslice_mask);
> > + sseu->subslice_mask.hsw[s] = subslice_mask;
> >
> > for (ss = 0; ss < sseu->max_subslices; ss++) {
> > u8 eu_disabled_mask;
> > @@ -587,8 +607,7 @@ static void hsw_sseu_info_init(struct intel_gt *gt)
> > sseu->eu_per_subslice);
> >
> > for (s = 0; s < sseu->max_slices; s++) {
> > - intel_sseu_set_subslices(sseu, s, sseu->subslice_mask,
> > - subslice_mask);
> > + sseu->subslice_mask.hsw[s] = subslice_mask;
> >
> > for (ss = 0; ss < sseu->max_subslices; ss++) {
> > sseu_set_eus(sseu, s, ss,
> > @@ -677,7 +696,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
> > */
> > if (GRAPHICS_VER(i915) == 11 &&
> > slices == 1 &&
> > - subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
> > + subslices > min_t(u8, 4, hweight8(sseu->subslice_mask.hsw[0]) / 2)) {
> > GEM_BUG_ON(subslices & 1);
> >
> > subslice_pg = false;
> > @@ -743,14 +762,29 @@ void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
> > {
> > int s;
> >
> > - drm_printf(p, "slice total: %u, mask=%04x\n",
> > - hweight8(sseu->slice_mask), sseu->slice_mask);
> > - drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
> > - for (s = 0; s < sseu->max_slices; s++) {
> > - drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
> > - s, intel_sseu_subslices_per_slice(sseu, s),
> > - intel_sseu_get_subslices(sseu, s));
> > + if (sseu->has_xehp_dss) {
> > + drm_printf(p, "subslice total: %u\n",
> > + intel_sseu_subslice_total(sseu));
> > + drm_printf(p, "geometry dss mask=%*pb\n",
> > + XEHP_BITMAP_BITS(sseu->geometry_subslice_mask),
> > + sseu->geometry_subslice_mask.xehp);
> > + drm_printf(p, "compute dss mask=%*pb\n",
> > + XEHP_BITMAP_BITS(sseu->compute_subslice_mask),
> > + sseu->compute_subslice_mask.xehp);
> > + } else {
> > + drm_printf(p, "slice total: %u, mask=%04x\n",
> > + hweight8(sseu->slice_mask), sseu->slice_mask);
> > + drm_printf(p, "subslice total: %u\n",
> > + intel_sseu_subslice_total(sseu));
> > +
> > + for (s = 0; s < sseu->max_slices; s++) {
> > + u8 ss_mask = sseu->subslice_mask.hsw[s];
> > +
> > + drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
> > + s, hweight8(ss_mask), ss_mask);
> > + }
> > }
> > +
> > drm_printf(p, "EU total: %u\n", sseu->eu_total);
> > drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
> > drm_printf(p, "has slice power gating: %s\n",
> > @@ -767,9 +801,10 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
> > int s, ss;
> >
> > for (s = 0; s < sseu->max_slices; s++) {
> > + u8 ss_mask = sseu->subslice_mask.hsw[s];
> > +
> > drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
> > - s, intel_sseu_subslices_per_slice(sseu, s),
> > - intel_sseu_get_subslices(sseu, s));
> > + s, hweight8(ss_mask), ss_mask);
> >
> > for (ss = 0; ss < sseu->max_subslices; ss++) {
> > u16 enabled_eus = sseu_get_eus(sseu, s, ss);
> > @@ -783,16 +818,14 @@ static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu,
> > static void sseu_print_xehp_topology(const struct sseu_dev_info *sseu,
> > struct drm_printer *p)
> > {
> > - u32 g_dss_mask = sseu_get_geometry_subslices(sseu);
> > - u32 c_dss_mask = intel_sseu_get_compute_subslices(sseu);
> > int dss;
> >
> > for (dss = 0; dss < sseu->max_subslices; dss++) {
> > u16 enabled_eus = sseu_get_eus(sseu, 0, dss);
> >
> > drm_printf(p, "DSS_%02d: G:%3s C:%3s, %2u EUs (0x%04hx)\n", dss,
> > - str_yes_no(g_dss_mask & BIT(dss)),
> > - str_yes_no(c_dss_mask & BIT(dss)),
> > + str_yes_no(test_bit(dss, sseu->geometry_subslice_mask.xehp)),
> > + str_yes_no(test_bit(dss, sseu->compute_subslice_mask.xehp)),
> > hweight16(enabled_eus), enabled_eus);
> > }
> > }
> > @@ -810,20 +843,44 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
> > }
> > }
> >
> > -u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice)
> > +void intel_sseu_print_ss_info(const char* type,
> > + const struct sseu_dev_info *sseu,
> > + struct seq_file *m)
> > +{
> > + int s;
> > +
> > + if (sseu->has_xehp_dss) {
> > + seq_printf(m, " %s Geometry DSS: %u\n", type,
> > + bitmap_weight(sseu->geometry_subslice_mask.xehp,
> > + XEHP_BITMAP_BITS(sseu->geometry_subslice_mask)));
> > + seq_printf(m, " %s Compute DSS: %u\n", type,
> > + bitmap_weight(sseu->compute_subslice_mask.xehp,
> > + XEHP_BITMAP_BITS(sseu->compute_subslice_mask)));
> > + } else {
> > + for (s = 0; s < fls(sseu->slice_mask); s++)
> > + seq_printf(m, " %s Slice%i subslices: %u\n", type,
> > + s, hweight8(sseu->subslice_mask.hsw[s]));
> > + }
> > +}
> > +
> > +u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask,
> > + int dss_per_slice)
> > {
> > + intel_sseu_ss_mask_t per_slice_mask = {};
> > u16 slice_mask = 0;
> > int i;
> >
> > - WARN_ON(sizeof(dss_mask) * 8 / dss_per_slice > 8 * sizeof(slice_mask));
> > + WARN_ON(DIV_ROUND_UP(XEHP_BITMAP_BITS(dss_mask), dss_per_slice) >
> > + 8 * sizeof(slice_mask));
> >
> > - for (i = 0; dss_mask; i++) {
> > - if (dss_mask & GENMASK(dss_per_slice - 1, 0))
> > + bitmap_fill(per_slice_mask.xehp, dss_per_slice);
> > + for (i = 0; !bitmap_empty(dss_mask.xehp, XEHP_BITMAP_BITS(dss_mask)); i++) {
> > + if (bitmap_intersects(dss_mask.xehp, per_slice_mask.xehp, dss_per_slice))
> > slice_mask |= BIT(i);
> >
> > - dss_mask >>= dss_per_slice;
> > + bitmap_shift_right(dss_mask.xehp, dss_mask.xehp, dss_per_slice,
> > + XEHP_BITMAP_BITS(dss_mask));
> > }
> >
> > return slice_mask;
> > }
> > -
> > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > index ffa375e68959..e7f336a7ffbb 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> > @@ -25,12 +25,16 @@ struct drm_printer;
> > /*
> > * Maximum number of subslices that can exist within a HSW-style slice. This
> > * is only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the
> > - * GEN_MAX_DSS value below).
> > + * I915_MAX_SS_FUSE_BITS value below).
> > */
> > #define GEN_MAX_SS_PER_HSW_SLICE 6
> >
> > -/* Maximum number of DSS on newer platforms (Xe_HP and beyond). */
> > -#define GEN_MAX_DSS 32
> > +/*
> > + * Maximum number of 32-bit registers used by hardware to express the
> > + * enabled/disabled subslices.
> > + */
> > +#define I915_MAX_SS_FUSE_REGS 1
> > +#define I915_MAX_SS_FUSE_BITS (I915_MAX_SS_FUSE_REGS * 32)
> >
> > /* Maximum number of EUs that can exist within a subslice or DSS. */
> > #define GEN_MAX_EUS_PER_SS 16
> > @@ -38,7 +42,7 @@ struct drm_printer;
> > #define SSEU_MAX(a, b) ((a) > (b) ? (a) : (b))
> >
> > /* The maximum number of bits needed to express each subslice/DSS independently */
> > -#define GEN_SS_MASK_SIZE SSEU_MAX(GEN_MAX_DSS, \
> > +#define GEN_SS_MASK_SIZE SSEU_MAX(I915_MAX_SS_FUSE_BITS, \
> > GEN_MAX_HSW_SLICES * GEN_MAX_SS_PER_HSW_SLICE)
> >
> > #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
> > @@ -49,17 +53,24 @@ struct drm_printer;
> > #define GEN_DSS_PER_CSLICE 8
> > #define GEN_DSS_PER_MSLICE 8
> >
> > -#define GEN_MAX_GSLICES (GEN_MAX_DSS / GEN_DSS_PER_GSLICE)
> > -#define GEN_MAX_CSLICES (GEN_MAX_DSS / GEN_DSS_PER_CSLICE)
> > +#define GEN_MAX_GSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_GSLICE)
> > +#define GEN_MAX_CSLICES (I915_MAX_SS_FUSE_BITS / GEN_DSS_PER_CSLICE)
> > +
> > +typedef union {
> > + u8 hsw[GEN_MAX_HSW_SLICES];
> > +
> > + /* Bitmap compatible with linux/bitmap.h; may exceed size of u64 */
> > + unsigned long xehp[BITS_TO_LONGS(I915_MAX_SS_FUSE_BITS)];
> > +} intel_sseu_ss_mask_t;
> >
> > struct sseu_dev_info {
> > u8 slice_mask;
> > - u8 subslice_mask[GEN_SS_MASK_SIZE];
> > - u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
> > - u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
> > + intel_sseu_ss_mask_t subslice_mask;
> > + intel_sseu_ss_mask_t geometry_subslice_mask;
> > + intel_sseu_ss_mask_t compute_subslice_mask;
> > union {
> > u16 hsw[GEN_MAX_HSW_SLICES][GEN_MAX_SS_PER_HSW_SLICE];
> > - u16 xehp[GEN_MAX_DSS];
> > + u16 xehp[I915_MAX_SS_FUSE_BITS];
> > } eu_mask;
> >
> > u16 eu_total;
> > @@ -80,8 +91,6 @@ struct sseu_dev_info {
> > u8 max_slices;
> > u8 max_subslices;
> > u8 max_eus_per_subslice;
> > -
> > - u8 ss_stride;
> > };
> >
> > /*
> > @@ -99,7 +108,7 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
> > {
> > struct intel_sseu value = {
> > .slice_mask = sseu->slice_mask,
> > - .subslice_mask = sseu->subslice_mask[0],
> > + .subslice_mask = sseu->subslice_mask.hsw[0],
> > .min_eus_per_subslice = sseu->max_eus_per_subslice,
> > .max_eus_per_subslice = sseu->max_eus_per_subslice,
> > };
> > @@ -111,18 +120,27 @@ static inline bool
> > intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
> > int subslice)
> > {
> > - u8 mask;
> > - int ss_idx = subslice / BITS_PER_BYTE;
> > -
> > if (slice >= sseu->max_slices ||
> > subslice >= sseu->max_subslices)
> > return false;
> >
> > - GEM_BUG_ON(ss_idx >= sseu->ss_stride);
> > -
> > - mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx];
> > + if (sseu->has_xehp_dss)
> > + return test_bit(subslice, sseu->subslice_mask.xehp);
> > + else
> > + return sseu->subslice_mask.hsw[slice] & BIT(subslice);
> > +}
> >
> > - return mask & BIT(subslice % BITS_PER_BYTE);
> > +/*
> > + * Used to obtain the index of the first DSS. Can start searching from the
> > + * beginning of a specific dss group (e.g., gslice, cslice, etc.) if
> > + * groupsize and groupnum are non-zero.
> > + */
> > +static inline unsigned int
> > +intel_sseu_find_first_xehp_dss(const struct sseu_dev_info *sseu, int groupsize,
> > + int groupnum)
> > +{
> > + return find_next_bit(sseu->subslice_mask.xehp, I915_MAX_SS_FUSE_BITS,
> > + groupnum * groupsize);
> Any specific reason for not replacing I915_MAX_SS_FUSE_BITS with
> XEHP_BITMAP_BITS here?
It looks like I just missed this one while changing the others. I'll
send an update that makes that change.
Matt
>
> Regards,
> Bala
> > }
> >
> > void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
> > @@ -132,14 +150,10 @@ unsigned int
> > intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
> >
> > unsigned int
> > -intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
> > -
> > -u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
> > +intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice);
> >
> > -u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
> > -
> > -void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
> > - u8 *subslice_mask, u32 ss_mask);
> > +intel_sseu_ss_mask_t
> > +intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
> >
> > void intel_sseu_info_init(struct intel_gt *gt);
> >
> > @@ -151,9 +165,15 @@ void intel_sseu_print_topology(struct drm_i915_private *i915,
> > const struct sseu_dev_info *sseu,
> > struct drm_printer *p);
> >
> > -u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
> > +u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask, int dss_per_slice);
> >
> > int intel_sseu_copy_eumask_to_user(void __user *to,
> > const struct sseu_dev_info *sseu);
> > +int intel_sseu_copy_ssmask_to_user(void __user *to,
> > + const struct sseu_dev_info *sseu);
> > +
> > +void intel_sseu_print_ss_info(const char* type,
> > + const struct sseu_dev_info *sseu,
> > + struct seq_file *m);
> >
> > #endif /* __INTEL_SSEU_H__ */
> > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> > index 2d5d011e01db..c2ee5e1826b5 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> > @@ -4,6 +4,7 @@
> > * Copyright © 2020 Intel Corporation
> > */
> >
> > +#include <linux/bitmap.h>
> > #include <linux/string_helpers.h>
> >
> > #include "i915_drv.h"
> > @@ -11,14 +12,6 @@
> > #include "intel_gt_regs.h"
> > #include "intel_sseu_debugfs.h"
> >
> > -static void sseu_copy_subslices(const struct sseu_dev_info *sseu,
> > - int slice, u8 *to_mask)
> > -{
> > - int offset = slice * sseu->ss_stride;
> > -
> > - memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
> > -}
> > -
> > static void cherryview_sseu_device_status(struct intel_gt *gt,
> > struct sseu_dev_info *sseu)
> > {
> > @@ -41,7 +34,7 @@ static void cherryview_sseu_device_status(struct intel_gt *gt,
> > continue;
> >
> > sseu->slice_mask = BIT(0);
> > - sseu->subslice_mask[0] |= BIT(ss);
> > + sseu->subslice_mask.hsw[0] |= BIT(ss);
> > eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
> > ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
> > ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
> > @@ -92,7 +85,7 @@ static void gen11_sseu_device_status(struct intel_gt *gt,
> > continue;
> >
> > sseu->slice_mask |= BIT(s);
> > - sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
> > + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
> >
> > for (ss = 0; ss < info->sseu.max_subslices; ss++) {
> > unsigned int eu_cnt;
> > @@ -147,21 +140,17 @@ static void gen9_sseu_device_status(struct intel_gt *gt,
> > sseu->slice_mask |= BIT(s);
> >
> > if (IS_GEN9_BC(gt->i915))
> > - sseu_copy_subslices(&info->sseu, s,
> > - sseu->subslice_mask);
> > + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
> >
> > for (ss = 0; ss < info->sseu.max_subslices; ss++) {
> > unsigned int eu_cnt;
> > - u8 ss_idx = s * info->sseu.ss_stride +
> > - ss / BITS_PER_BYTE;
> >
> > if (IS_GEN9_LP(gt->i915)) {
> > if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> > /* skip disabled subslice */
> > continue;
> >
> > - sseu->subslice_mask[ss_idx] |=
> > - BIT(ss % BITS_PER_BYTE);
> > + sseu->subslice_mask.hsw[s] |= BIT(ss);
> > }
> >
> > eu_cnt = eu_reg[2 * s + ss / 2] & eu_mask[ss % 2];
> > @@ -188,8 +177,7 @@ static void bdw_sseu_device_status(struct intel_gt *gt,
> > if (sseu->slice_mask) {
> > sseu->eu_per_subslice = info->sseu.eu_per_subslice;
> > for (s = 0; s < fls(sseu->slice_mask); s++)
> > - sseu_copy_subslices(&info->sseu, s,
> > - sseu->subslice_mask);
> > + sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s];
> > sseu->eu_total = sseu->eu_per_subslice *
> > intel_sseu_subslice_total(sseu);
> >
> > @@ -208,7 +196,6 @@ static void i915_print_sseu_info(struct seq_file *m,
> > const struct sseu_dev_info *sseu)
> > {
> > const char *type = is_available_info ? "Available" : "Enabled";
> > - int s;
> >
> > seq_printf(m, " %s Slice Mask: %04x\n", type,
> > sseu->slice_mask);
> > @@ -216,10 +203,7 @@ static void i915_print_sseu_info(struct seq_file *m,
> > hweight8(sseu->slice_mask));
> > seq_printf(m, " %s Subslice Total: %u\n", type,
> > intel_sseu_subslice_total(sseu));
> > - for (s = 0; s < fls(sseu->slice_mask); s++) {
> > - seq_printf(m, " %s Slice%i subslices: %u\n", type,
> > - s, intel_sseu_subslices_per_slice(sseu, s));
> > - }
> > + intel_sseu_print_ss_info(type, sseu, m);
> > seq_printf(m, " %s EU Total: %u\n", type,
> > sseu->eu_total);
> > seq_printf(m, " %s EU Per Subslice: %u\n", type,
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 73b59ea6fd3b..1bf62273e02d 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -948,8 +948,8 @@ gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> > * on s/ss combo, the read should be done with read_subslice_reg.
> > */
> > slice = ffs(sseu->slice_mask) - 1;
> > - GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
> > - subslice = ffs(intel_sseu_get_subslices(sseu, slice));
> > + GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw));
> > + subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice));
> > GEM_BUG_ON(!subslice);
> > subslice--;
> >
> > @@ -1087,11 +1087,10 @@ static void
> > icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> > {
> > const struct sseu_dev_info *sseu = >->info.sseu;
> > - unsigned int slice, subslice;
> > + unsigned int subslice;
> >
> > GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
> > GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
> > - slice = 0;
> >
> > /*
> > * Although a platform may have subslices, we need to always steer
> > @@ -1102,7 +1101,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> > * one of the higher subslices, we run the risk of reading back 0's or
> > * random garbage.
> > */
> > - subslice = __ffs(intel_sseu_get_subslices(sseu, slice));
> > + subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0));
> >
> > /*
> > * If the subslice we picked above also steers us to a valid L3 bank,
> > @@ -1112,7 +1111,7 @@ icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> > if (gt->info.l3bank_mask & BIT(subslice))
> > gt->steering_table[L3BANK] = NULL;
> >
> > - __add_mcr_wa(gt, wal, slice, subslice);
> > + __add_mcr_wa(gt, wal, 0, subslice);
> > }
> >
> > static void
> > @@ -1120,7 +1119,6 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> > {
> > const struct sseu_dev_info *sseu = >->info.sseu;
> > unsigned long slice, subslice = 0, slice_mask = 0;
> > - u64 dss_mask = 0;
> > u32 lncf_mask = 0;
> > int i;
> >
> > @@ -1151,8 +1149,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> > */
> >
> > /* Find the potential gslice candidates */
> > - dss_mask = intel_sseu_get_subslices(sseu, 0);
> > - slice_mask = intel_slicemask_from_dssmask(dss_mask, GEN_DSS_PER_GSLICE);
> > + slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask,
> > + GEN_DSS_PER_GSLICE);
> >
> > /*
> > * Find the potential LNCF candidates. Either LNCF within a valid
> > @@ -1177,9 +1175,8 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
> > }
> >
> > slice = __ffs(slice_mask);
> > - subslice = __ffs(dss_mask >> (slice * GEN_DSS_PER_GSLICE));
> > + subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice);
> > WARN_ON(subslice > GEN_DSS_PER_GSLICE);
> > - WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0);
> >
> > __add_mcr_wa(gt, wal, slice, subslice);
> >
> > @@ -2030,9 +2027,8 @@ engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> >
> > static bool needs_wa_1308578152(struct intel_engine_cs *engine)
> > {
> > - u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0);
> > -
> > - return (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0;
> > + return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >
> > + GEN_DSS_PER_GSLICE;
> > }
> >
> > static void
> > diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
> > index ac9767c56619..6fd15b39570c 100644
> > --- a/drivers/gpu/drm/i915/i915_getparam.c
> > +++ b/drivers/gpu/drm/i915/i915_getparam.c
> > @@ -162,8 +162,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
> > return -EINVAL;
> >
> > /* Only copy bits from the first slice */
> > - memcpy(&value, sseu->subslice_mask,
> > - min(sseu->ss_stride, (u8)sizeof(value)));
> > + value = intel_sseu_get_hsw_subslices(sseu, 0);
> > if (!value)
> > return -ENODEV;
> > break;
> > diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> > index 89c475d525b8..0094f67c63f2 100644
> > --- a/drivers/gpu/drm/i915/i915_query.c
> > +++ b/drivers/gpu/drm/i915/i915_query.c
> > @@ -31,10 +31,11 @@ static int copy_query_item(void *query_hdr, size_t query_sz,
> >
> > static int fill_topology_info(const struct sseu_dev_info *sseu,
> > struct drm_i915_query_item *query_item,
> > - const u8 *subslice_mask)
> > + intel_sseu_ss_mask_t subslice_mask)
> > {
> > struct drm_i915_query_topology_info topo;
> > u32 slice_length, subslice_length, eu_length, total_length;
> > + int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
> > int eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
> > int ret;
> >
> > @@ -44,7 +45,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
> > return -ENODEV;
> >
> > slice_length = sizeof(sseu->slice_mask);
> > - subslice_length = sseu->max_slices * sseu->ss_stride;
> > + subslice_length = sseu->max_slices * ss_stride;
> > eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
> > total_length = sizeof(topo) + slice_length + subslice_length +
> > eu_length;
> > @@ -60,7 +61,7 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
> > topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
> >
> > topo.subslice_offset = slice_length;
> > - topo.subslice_stride = sseu->ss_stride;
> > + topo.subslice_stride = ss_stride;
> > topo.eu_offset = slice_length + subslice_length;
> > topo.eu_stride = eu_stride;
> >
> > @@ -72,9 +73,9 @@ static int fill_topology_info(const struct sseu_dev_info *sseu,
> > &sseu->slice_mask, slice_length))
> > return -EFAULT;
> >
> > - if (copy_to_user(u64_to_user_ptr(query_item->data_ptr +
> > - sizeof(topo) + slice_length),
> > - subslice_mask, subslice_length))
> > + if (intel_sseu_copy_ssmask_to_user(u64_to_user_ptr(query_item->data_ptr +
> > + sizeof(topo) + slice_length),
> > + sseu))
> > return -EFAULT;
> >
> > if (intel_sseu_copy_eumask_to_user(u64_to_user_ptr(query_item->data_ptr +
> > --
> > 2.35.3
> >
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 36+ messages in thread
end of thread, other threads:[~2022-06-01 14:41 UTC | newest]
Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-20 23:04 [PATCH v4 0/6] i915: SSEU handling updates Matt Roper
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
2022-05-20 23:04 ` [PATCH v4 1/6] drm/i915/xehp: Use separate sseu init function Matt Roper
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
2022-05-20 23:04 ` [PATCH v4 2/6] drm/i915/xehp: Drop GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK Matt Roper
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
2022-05-20 23:04 ` [PATCH v4 3/6] drm/i915/sseu: Simplify gen11+ SSEU handling Matt Roper
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
2022-05-20 23:04 ` [PATCH v4 4/6] drm/i915/sseu: Don't try to store EU mask internally in UAPI format Matt Roper
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
2022-05-20 23:04 ` [PATCH v4 5/6] drm/i915/sseu: Disassociate internal subslice mask representation from uapi Matt Roper
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
2022-05-23 7:59 ` Tvrtko Ursulin
2022-05-23 7:59 ` [Intel-gfx] " Tvrtko Ursulin
2022-05-23 20:45 ` [PATCH v5 " Matt Roper
2022-05-23 20:45 ` [Intel-gfx] " Matt Roper
2022-06-01 8:18 ` Balasubramani Vivekanandan
2022-06-01 8:18 ` [Intel-gfx] " Balasubramani Vivekanandan
2022-06-01 14:40 ` Matt Roper
2022-06-01 14:40 ` [Intel-gfx] " Matt Roper
2022-05-20 23:04 ` [PATCH v4 6/6] drm/i915/pvc: Add SSEU changes Matt Roper
2022-05-20 23:04 ` [Intel-gfx] " Matt Roper
2022-05-20 23:46 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: SSEU handling updates Patchwork
2022-05-20 23:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-20 23:55 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-05-23 21:00 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: SSEU handling updates (rev2) Patchwork
2022-05-23 21:00 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-23 21:23 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-05-23 23:31 ` Matt Roper
2022-05-24 16:20 ` Vudum, Lakshminarayana
2022-05-24 2:51 ` Patchwork
2022-05-24 5:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-05-24 7:07 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-05-24 7:32 ` [PATCH v4 0/6] i915: SSEU handling updates Tvrtko Ursulin
2022-05-24 7:32 ` [Intel-gfx] " Tvrtko Ursulin
2022-05-24 16:12 ` [Intel-gfx] ✓ Fi.CI.IGT: success for i915: SSEU handling updates (rev2) Patchwork
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