* [PATCH v2 0/3] Cavium Octeon MIPS extensions
@ 2022-06-09 8:23 Pavel Dovgalyuk
2022-06-09 8:23 ` [PATCH v2 1/3] target/mips: introduce Cavium Octeon CPU model Pavel Dovgalyuk
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Pavel Dovgalyuk @ 2022-06-09 8:23 UTC (permalink / raw)
To: qemu-devel
Cc: pavel.dovgalyuk, f4bug, jiaxun.yang, aurelien, aleksandar.rikalo
The following series includes emulation of the platform-specific MIPS extension
for Cavium Octeon CPUS:
- basic Octeon vCPU model
- custom instruction decoder for Octeon
- implementation of arithmetic and logic instructions
v2 changes:
- simplified instruction decoding and translation (suggested by Richard Henderson)
---
Pavel Dovgalyuk (3):
target/mips: introduce Cavium Octeon CPU model
target/mips: implement Octeon-specific BBIT instructions
target/mips: implement Octeon-specific arithmetic instructions
target/mips/tcg/meson.build | 2 +
target/mips/tcg/octeon.decode | 41 ++++++
target/mips/tcg/octeon_translate.c | 201 +++++++++++++++++++++++++++++
target/mips/tcg/translate.c | 5 +
target/mips/tcg/translate.h | 1 +
5 files changed, 250 insertions(+)
create mode 100644 target/mips/tcg/octeon.decode
create mode 100644 target/mips/tcg/octeon_translate.c
--
Pavel Dovgalyuk
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 1/3] target/mips: introduce Cavium Octeon CPU model
2022-06-09 8:23 [PATCH v2 0/3] Cavium Octeon MIPS extensions Pavel Dovgalyuk
@ 2022-06-09 8:23 ` Pavel Dovgalyuk
2022-06-10 13:28 ` Philippe Mathieu-Daudé via
2022-06-09 8:23 ` [PATCH v2 2/3] target/mips: implement Octeon-specific BBIT instructions Pavel Dovgalyuk
2022-06-09 8:23 ` [PATCH v2 3/3] target/mips: implement Octeon-specific arithmetic instructions Pavel Dovgalyuk
2 siblings, 1 reply; 8+ messages in thread
From: Pavel Dovgalyuk @ 2022-06-09 8:23 UTC (permalink / raw)
To: qemu-devel
Cc: pavel.dovgalyuk, f4bug, jiaxun.yang, aurelien, aleksandar.rikalo
This patch adds Cavium Octeon vCPU for providing
Octeon-specific instructions.
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
--
v2 changes:
- vCPU name changed to Octeon68XX (suggested by Richard Henderson)
---
target/mips/cpu-defs.c.inc | 28 ++++++++++++++++++++++++++++
target/mips/mips-defs.h | 1 +
2 files changed, 29 insertions(+)
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index 582f940070..7f53c94ec8 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -921,6 +921,34 @@ const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
.mmu_type = MMU_TYPE_R4000,
},
+ {
+ /*
+ * Octeon 68xx with MIPS64 Cavium Octeon features.
+ */
+ .name = "Octeon68XX",
+ .CP0_PRid = 0x000D9100,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
+ (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) | (1 << CP0C3_DSPP) ,
+ .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) |
+ (0x3c << CP0C4_KScrExist) | (1U << CP0C4_MMUExtDef) |
+ (3U << CP0C4_MMUSizeExt),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .CP0_PageGrain = (1 << CP0PG_ELPA),
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x12F8FFFF,
+ .SEGBITS = 42,
+ .PABITS = 49,
+ .insn_flags = CPU_MIPS64R2 | INSN_OCTEON | ASE_DSP,
+ .mmu_type = MMU_TYPE_R4000,
+ },
#endif
};
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 0a12d982a7..a6cebe0265 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -42,6 +42,7 @@
#define INSN_LOONGSON2E 0x0000040000000000ULL
#define INSN_LOONGSON2F 0x0000080000000000ULL
#define INSN_LOONGSON3A 0x0000100000000000ULL
+#define INSN_OCTEON 0x0000200000000000ULL
/*
* bits 52-63: vendor-specific ASEs
*/
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 2/3] target/mips: implement Octeon-specific BBIT instructions
2022-06-09 8:23 [PATCH v2 0/3] Cavium Octeon MIPS extensions Pavel Dovgalyuk
2022-06-09 8:23 ` [PATCH v2 1/3] target/mips: introduce Cavium Octeon CPU model Pavel Dovgalyuk
@ 2022-06-09 8:23 ` Pavel Dovgalyuk
2022-06-09 14:19 ` Richard Henderson
2022-06-09 8:23 ` [PATCH v2 3/3] target/mips: implement Octeon-specific arithmetic instructions Pavel Dovgalyuk
2 siblings, 1 reply; 8+ messages in thread
From: Pavel Dovgalyuk @ 2022-06-09 8:23 UTC (permalink / raw)
To: qemu-devel
Cc: pavel.dovgalyuk, f4bug, jiaxun.yang, aurelien, aleksandar.rikalo
This patch introduces Octeon-specific decoder and implements
check-bit-and-jump instructions.
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
--
v2 changes:
- Changed insn field description and simplified the jumps
(suggested by Richard Henderson)
---
target/mips/tcg/meson.build | 2 ++
target/mips/tcg/octeon.decode | 15 ++++++++++++
target/mips/tcg/octeon_translate.c | 46 ++++++++++++++++++++++++++++++++++++
target/mips/tcg/translate.c | 5 ++++
target/mips/tcg/translate.h | 1 +
5 files changed, 69 insertions(+)
create mode 100644 target/mips/tcg/octeon.decode
create mode 100644 target/mips/tcg/octeon_translate.c
diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build
index 98003779ae..7ee969ec8f 100644
--- a/target/mips/tcg/meson.build
+++ b/target/mips/tcg/meson.build
@@ -3,6 +3,7 @@ gen = [
decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'),
decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
decodetree.process('vr54xx.decode', extra_args: '--decode=decode_ext_vr54xx'),
+ decodetree.process('octeon.decode', extra_args: '--decode=decode_ext_octeon'),
]
mips_ss.add(gen)
@@ -24,6 +25,7 @@ mips_ss.add(files(
))
mips_ss.add(when: 'TARGET_MIPS64', if_true: files(
'tx79_translate.c',
+ 'octeon_translate.c',
), if_false: files(
'mxu_translate.c',
))
diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode
new file mode 100644
index 0000000000..8062715578
--- /dev/null
+++ b/target/mips/tcg/octeon.decode
@@ -0,0 +1,15 @@
+# Octeon Architecture Module instruction set
+#
+# Copyright (C) 2022 Pavel Dovgalyuk
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+
+# Branch on bit set or clear
+# BBIT0 110010 ..... ..... ................
+# BBIT032 110110 ..... ..... ................
+# BBIT1 111010 ..... ..... ................
+# BBIT132 111110 ..... ..... ................
+
+%bbit_p 28:1 16:5
+BBIT 11 set:1 . 10 rs:5 ..... offset:16 p=%bbit_p
diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c
new file mode 100644
index 0000000000..1558f74a8e
--- /dev/null
+++ b/target/mips/tcg/octeon_translate.c
@@ -0,0 +1,46 @@
+/*
+ * Octeon-specific instructions translation routines
+ *
+ * Copyright (c) 2022 Pavel Dovgalyuk
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "tcg/tcg-op.h"
+#include "tcg/tcg-op-gvec.h"
+#include "exec/helper-gen.h"
+#include "translate.h"
+
+/* Include the auto-generated decoder. */
+#include "decode-octeon.c.inc"
+
+static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
+{
+ TCGv p;
+
+ if (ctx->hflags & MIPS_HFLAG_BMASK) {
+ LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
+ TARGET_FMT_lx "\n", ctx->base.pc_next);
+ generate_exception_end(ctx, EXCP_RI);
+ return true;
+ }
+
+ /* Load needed operands */
+ TCGv t0 = tcg_temp_new();
+ gen_load_gpr(t0, a->rs);
+
+ p = tcg_constant_tl(1ULL << a->p);
+ if (a->set) {
+ tcg_gen_and_tl(bcond, p, t0);
+ } else {
+ tcg_gen_andc_tl(bcond, p, t0);
+ }
+
+ ctx->hflags |= MIPS_HFLAG_BC;
+ ctx->btarget = ctx->base.pc_next + 4 + a->offset * 4;
+ ctx->hflags |= MIPS_HFLAG_BDS32;
+
+ tcg_temp_free(t0);
+ return true;
+}
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 6de5b66650..4f41a9b00a 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -15963,6 +15963,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->opcode)) {
return;
}
+#if defined(TARGET_MIPS64)
+ if (cpu_supports_isa(env, INSN_OCTEON) && decode_ext_octeon(ctx, ctx->opcode)) {
+ return;
+ }
+#endif
/* ISA extensions */
if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) {
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 9997fe2f3c..55053226ae 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -215,6 +215,7 @@ bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
bool decode_ext_txx9(DisasContext *ctx, uint32_t insn);
#if defined(TARGET_MIPS64)
bool decode_ext_tx79(DisasContext *ctx, uint32_t insn);
+bool decode_ext_octeon(DisasContext *ctx, uint32_t insn);
#endif
bool decode_ext_vr54xx(DisasContext *ctx, uint32_t insn);
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 3/3] target/mips: implement Octeon-specific arithmetic instructions
2022-06-09 8:23 [PATCH v2 0/3] Cavium Octeon MIPS extensions Pavel Dovgalyuk
2022-06-09 8:23 ` [PATCH v2 1/3] target/mips: introduce Cavium Octeon CPU model Pavel Dovgalyuk
2022-06-09 8:23 ` [PATCH v2 2/3] target/mips: implement Octeon-specific BBIT instructions Pavel Dovgalyuk
@ 2022-06-09 8:23 ` Pavel Dovgalyuk
2022-06-09 15:53 ` Richard Henderson
2 siblings, 1 reply; 8+ messages in thread
From: Pavel Dovgalyuk @ 2022-06-09 8:23 UTC (permalink / raw)
To: qemu-devel
Cc: pavel.dovgalyuk, f4bug, jiaxun.yang, aurelien, aleksandar.rikalo
This patch implements several Octeon-specific instructions:
- BADDU
- DMUL
- EXTS/EXTS32
- CINS/CINS32
- POP/DPOP
- SEQ/SEQI
- SNE/SNEI
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
--
v2 changes:
- Using existing tcg instructions for exts, cins, pop
(suggested by Richard Henderson)
---
target/mips/tcg/octeon.decode | 26 ++++++
target/mips/tcg/octeon_translate.c | 155 ++++++++++++++++++++++++++++++++++++
2 files changed, 181 insertions(+)
diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode
index 8062715578..8929ad088e 100644
--- a/target/mips/tcg/octeon.decode
+++ b/target/mips/tcg/octeon.decode
@@ -13,3 +13,29 @@
%bbit_p 28:1 16:5
BBIT 11 set:1 . 10 rs:5 ..... offset:16 p=%bbit_p
+
+# Arithmetic
+# BADDU rd, rs, rt
+# DMUL rd, rs, rt
+# EXTS rt, rs, p, lenm1
+# EXTS32 rt, rs, p, lenm1
+# CINS rt, rs, p, lenm1
+# CINS32 rt, rs, p, lenm1
+# DPOP rd, rs
+# POP rd, rs
+# SEQ rd, rs, rt
+# SEQI rt, rs, immediate
+# SNE rd, rs, rt
+# SNEI rt, rs, immediate
+
+@r3 ...... rs:5 rt:5 rd:5 ..... ......
+%bitfield_p 0:1 6:5
+@bitfield ...... rs:5 rt:5 lenm1:5 ..... ..... . p=%bitfield_p
+
+BADDU 011100 ..... ..... ..... 00000 101000 @r3
+DMUL 011100 ..... ..... ..... 00000 000011 @r3
+EXTS 011100 ..... ..... ..... ..... 11101 . @bitfield
+CINS 011100 ..... ..... ..... ..... 11001 . @bitfield
+POP 011100 rs:5 00000 rd:5 00000 10110 dw:1
+SEQNE 011100 rs:5 rt:5 rd:5 00000 10101 ne:1
+SEQNEI 011100 rs:5 rt:5 imm:s10 10111 ne:1
diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c
index 1558f74a8e..0470605e1e 100644
--- a/target/mips/tcg/octeon_translate.c
+++ b/target/mips/tcg/octeon_translate.c
@@ -44,3 +44,158 @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
tcg_temp_free(t0);
return true;
}
+
+static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a)
+{
+ TCGv t0, t1;
+
+ if (a->rt == 0) {
+ /* nop */
+ return true;
+ }
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ gen_load_gpr(t0, a->rs);
+ gen_load_gpr(t1, a->rt);
+
+ tcg_gen_add_tl(t0, t0, t1);
+ tcg_gen_andi_i64(cpu_gpr[a->rd], t0, 0xff);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+ return true;
+}
+
+static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a)
+{
+ TCGv t0, t1;
+
+ if (a->rt == 0) {
+ /* nop */
+ return true;
+ }
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ gen_load_gpr(t0, a->rs);
+ gen_load_gpr(t1, a->rt);
+
+ tcg_gen_mul_i64(cpu_gpr[a->rd], t0, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+ return true;
+}
+
+static bool trans_EXTS(DisasContext *ctx, arg_EXTS *a)
+{
+ TCGv t0;
+
+ if (a->rt == 0) {
+ /* nop */
+ return true;
+ }
+
+ t0 = tcg_temp_new();
+ gen_load_gpr(t0, a->rs);
+ tcg_gen_sextract_tl(t0, t0, a->p, a->lenm1);
+ gen_store_gpr(t0, a->rt);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_CINS(DisasContext *ctx, arg_CINS *a)
+{
+ TCGv t0;
+
+ if (a->rt == 0) {
+ /* nop */
+ return true;
+ }
+
+ t0 = tcg_temp_new();
+ gen_load_gpr(t0, a->rs);
+ tcg_gen_deposit_z_tl(t0, t0, a->p, a->lenm1);
+ gen_store_gpr(t0, a->rt);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_POP(DisasContext *ctx, arg_POP *a)
+{
+ TCGv t0;
+
+ if (a->rd == 0) {
+ /* nop */
+ return true;
+ }
+
+ t0 = tcg_temp_new();
+ gen_load_gpr(t0, a->rs);
+ if (!a->dw) {
+ tcg_gen_andi_i64(t0, t0, 0xffffffff);
+ }
+ tcg_gen_ctpop_tl(t0, t0);
+ gen_store_gpr(t0, a->rd);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool trans_SEQNE(DisasContext *ctx, arg_SEQNE *a)
+{
+ TCGv t0, t1;
+
+ if (a->rd == 0) {
+ /* nop */
+ return true;
+ }
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+
+ gen_load_gpr(t0, a->rs);
+ gen_load_gpr(t1, a->rt);
+
+ if (a->ne) {
+ tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr[a->rd], t1, t0);
+ } else {
+ tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0);
+ }
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+
+ return true;
+}
+
+static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a)
+{
+ TCGv t0;
+
+ if (a->rt == 0) {
+ /* nop */
+ return true;
+ }
+
+ t0 = tcg_temp_new();
+
+ gen_load_gpr(t0, a->rs);
+
+ /* Sign-extend to 64 bit value */
+ target_ulong imm = a->imm;
+ if (a->ne) {
+ tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr[a->rt], t0, imm);
+ } else {
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm);
+ }
+
+ tcg_temp_free(t0);
+
+ return true;
+}
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/3] target/mips: implement Octeon-specific BBIT instructions
2022-06-09 8:23 ` [PATCH v2 2/3] target/mips: implement Octeon-specific BBIT instructions Pavel Dovgalyuk
@ 2022-06-09 14:19 ` Richard Henderson
0 siblings, 0 replies; 8+ messages in thread
From: Richard Henderson @ 2022-06-09 14:19 UTC (permalink / raw)
To: Pavel Dovgalyuk, qemu-devel
Cc: f4bug, jiaxun.yang, aurelien, aleksandar.rikalo
On 6/9/22 01:23, Pavel Dovgalyuk wrote:
> This patch introduces Octeon-specific decoder and implements
> check-bit-and-jump instructions.
>
> Signed-off-by: Pavel Dovgalyuk<Pavel.Dovgalyuk@ispras.ru>
>
> --
>
> v2 changes:
> - Changed insn field description and simplified the jumps
> (suggested by Richard Henderson)
> ---
> target/mips/tcg/meson.build | 2 ++
> target/mips/tcg/octeon.decode | 15 ++++++++++++
> target/mips/tcg/octeon_translate.c | 46 ++++++++++++++++++++++++++++++++++++
> target/mips/tcg/translate.c | 5 ++++
> target/mips/tcg/translate.h | 1 +
> 5 files changed, 69 insertions(+)
> create mode 100644 target/mips/tcg/octeon.decode
> create mode 100644 target/mips/tcg/octeon_translate.c
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 3/3] target/mips: implement Octeon-specific arithmetic instructions
2022-06-09 8:23 ` [PATCH v2 3/3] target/mips: implement Octeon-specific arithmetic instructions Pavel Dovgalyuk
@ 2022-06-09 15:53 ` Richard Henderson
2022-06-14 5:55 ` Pavel Dovgalyuk
0 siblings, 1 reply; 8+ messages in thread
From: Richard Henderson @ 2022-06-09 15:53 UTC (permalink / raw)
To: Pavel Dovgalyuk, qemu-devel
Cc: f4bug, jiaxun.yang, aurelien, aleksandar.rikalo
On 6/9/22 01:23, Pavel Dovgalyuk wrote:
> +static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a)
> +{
> + TCGv t0, t1;
> +
> + if (a->rt == 0) {
> + /* nop */
> + return true;
> + }
I believe that we're standardizing on using gen_store_gpr, and not checking for r0 everywhere.
> +static bool trans_EXTS(DisasContext *ctx, arg_EXTS *a)
> +{
> + TCGv t0;
> +
> + if (a->rt == 0) {
> + /* nop */
> + return true;
> + }
> +
> + t0 = tcg_temp_new();
> + gen_load_gpr(t0, a->rs);
> + tcg_gen_sextract_tl(t0, t0, a->p, a->lenm1);
a->lenm1 + 1.
> + tcg_gen_deposit_z_tl(t0, t0, a->p, a->lenm1);
Likewise.
r~
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/3] target/mips: introduce Cavium Octeon CPU model
2022-06-09 8:23 ` [PATCH v2 1/3] target/mips: introduce Cavium Octeon CPU model Pavel Dovgalyuk
@ 2022-06-10 13:28 ` Philippe Mathieu-Daudé via
0 siblings, 0 replies; 8+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-06-10 13:28 UTC (permalink / raw)
To: Pavel Dovgalyuk, qemu-devel
Cc: jiaxun.yang, aurelien, aleksandar.rikalo, Aaron Williams, Stefan Roese
Hi Pavel,
On 9/6/22 10:23, Pavel Dovgalyuk wrote:
> This patch adds Cavium Octeon vCPU for providing
> Octeon-specific instructions.
>
> Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
>
> --
> v2 changes:
> - vCPU name changed to Octeon68XX (suggested by Richard Henderson)
> ---
> target/mips/cpu-defs.c.inc | 28 ++++++++++++++++++++++++++++
> target/mips/mips-defs.h | 1 +
> 2 files changed, 29 insertions(+)
>
> diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
> index 582f940070..7f53c94ec8 100644
> --- a/target/mips/cpu-defs.c.inc
> +++ b/target/mips/cpu-defs.c.inc
> @@ -921,6 +921,34 @@ const mips_def_t mips_defs[] =
> .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
> .mmu_type = MMU_TYPE_R4000,
> },
> + {
> + /*
> + * Octeon 68xx with MIPS64 Cavium Octeon features.
> + */
> + .name = "Octeon68XX",
> + .CP0_PRid = 0x000D9100,
> + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
> + (MMU_TYPE_R4000 << CP0C0_MT),
> + .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
> + (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
> + (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
> + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
> + .CP0_Config2 = MIPS_CONFIG2,
> + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) | (1 << CP0C3_DSPP) ,
> + .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) |
> + (0x3c << CP0C4_KScrExist) | (1U << CP0C4_MMUExtDef) |
> + (3U << CP0C4_MMUSizeExt),
> + .CP0_LLAddr_rw_bitmask = 0,
> + .CP0_LLAddr_shift = 4,
> + .CP0_PageGrain = (1 << CP0PG_ELPA),
> + .SYNCI_Step = 32,
> + .CCRes = 2,
> + .CP0_Status_rw_bitmask = 0x12F8FFFF,
> + .SEGBITS = 42,
> + .PABITS = 49,
> + .insn_flags = CPU_MIPS64R2 | INSN_OCTEON | ASE_DSP,
> + .mmu_type = MMU_TYPE_R4000,
> + },
>
> #endif
> };
^ This part should be the last patch of this series.
> diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
> index 0a12d982a7..a6cebe0265 100644
> --- a/target/mips/mips-defs.h
> +++ b/target/mips/mips-defs.h
> @@ -42,6 +42,7 @@
> #define INSN_LOONGSON2E 0x0000040000000000ULL
> #define INSN_LOONGSON2F 0x0000080000000000ULL
> #define INSN_LOONGSON3A 0x0000100000000000ULL
> +#define INSN_OCTEON 0x0000200000000000ULL
> /*
> * bits 52-63: vendor-specific ASEs
> */
>
This hunk ^ belongs to the next patch, but I'd rather split patch #2,
first part being similar to commit 9d00539239 ("target/mips:
Introduce decodetree structure for NEC Vr54xx extension").
The series would look like:
target/mips: introduce decodetree structure for Cavium Octeon extension
target/mips: implement Octeon-specific BBIT instructions
target/mips: implement Octeon-specific arithmetic instructions
target/mips: add Cavium Octeon68XX CPU model
Regards,
Phil.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 3/3] target/mips: implement Octeon-specific arithmetic instructions
2022-06-09 15:53 ` Richard Henderson
@ 2022-06-14 5:55 ` Pavel Dovgalyuk
0 siblings, 0 replies; 8+ messages in thread
From: Pavel Dovgalyuk @ 2022-06-14 5:55 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: f4bug, jiaxun.yang, aurelien, aleksandar.rikalo
On 09.06.2022 18:53, Richard Henderson wrote:
> On 6/9/22 01:23, Pavel Dovgalyuk wrote:
>> +static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a)
>> +{
>> + TCGv t0, t1;
>> +
>> + if (a->rt == 0) {
>> + /* nop */
>> + return true;
>> + }
>
> I believe that we're standardizing on using gen_store_gpr, and not
> checking for r0 everywhere.
I didn't remove this condition for making translation a bit faster.
Now there are no jumps or helpers, and I believe that optimizer
can remove everything in case of r0.
But if you insist, I'll remove this check.
>
>
>> +static bool trans_EXTS(DisasContext *ctx, arg_EXTS *a)
>> +{
>> + TCGv t0;
>> +
>> + if (a->rt == 0) {
>> + /* nop */
>> + return true;
>> + }
>> +
>> + t0 = tcg_temp_new();
>> + gen_load_gpr(t0, a->rs);
>> + tcg_gen_sextract_tl(t0, t0, a->p, a->lenm1);
>
> a->lenm1 + 1.
>
>> + tcg_gen_deposit_z_tl(t0, t0, a->p, a->lenm1);
>
> Likewise.
>
>
> r~
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-06-14 5:58 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-09 8:23 [PATCH v2 0/3] Cavium Octeon MIPS extensions Pavel Dovgalyuk
2022-06-09 8:23 ` [PATCH v2 1/3] target/mips: introduce Cavium Octeon CPU model Pavel Dovgalyuk
2022-06-10 13:28 ` Philippe Mathieu-Daudé via
2022-06-09 8:23 ` [PATCH v2 2/3] target/mips: implement Octeon-specific BBIT instructions Pavel Dovgalyuk
2022-06-09 14:19 ` Richard Henderson
2022-06-09 8:23 ` [PATCH v2 3/3] target/mips: implement Octeon-specific arithmetic instructions Pavel Dovgalyuk
2022-06-09 15:53 ` Richard Henderson
2022-06-14 5:55 ` Pavel Dovgalyuk
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