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* [PATCH] riscv: dts: microchip: re-add pdma to mpfs device tree
@ 2022-06-03  8:38 ` Conor Dooley
  0 siblings, 0 replies; 4+ messages in thread
From: Conor Dooley @ 2022-06-03  8:38 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, zong.li, devicetree, linux-riscv

PolarFire SoC /does/ have a SiFive pdma, despite what I suggested as a
conflict resolution to Zong. Somehow the entry fell through the cracks
between versions of my dt patches, so re-add it with Zong's updated
compatible & dma-channels property.

Fixes: c5094f371008 ("riscv: dts: microchip: refactor icicle kit device tree")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/boot/dts/microchip/mpfs.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index 8c3259134194..3095d08453a1 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -192,6 +192,15 @@ plic: interrupt-controller@c000000 {
 			riscv,ndev = <186>;
 		};
 
+		pdma: dma-controller@3000000 {
+			compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
+			reg = <0x0 0x3000000 0x0 0x8000>;
+			interrupt-parent = <&plic>;
+			interrupts = <5 6>, <7 8>, <9 10>, <11 12>;
+			dma-channels = <4>;
+			#dma-cells = <1>;
+		};
+
 		clkcfg: clkcfg@20002000 {
 			compatible = "microchip,mpfs-clkcfg";
 			reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
-- 
2.36.1


^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [PATCH] riscv: dts: microchip: re-add pdma to mpfs device tree
@ 2022-06-03  8:38 ` Conor Dooley
  0 siblings, 0 replies; 4+ messages in thread
From: Conor Dooley @ 2022-06-03  8:38 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt
  Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Conor Dooley,
	Daire McNamara, zong.li, devicetree, linux-riscv

PolarFire SoC /does/ have a SiFive pdma, despite what I suggested as a
conflict resolution to Zong. Somehow the entry fell through the cracks
between versions of my dt patches, so re-add it with Zong's updated
compatible & dma-channels property.

Fixes: c5094f371008 ("riscv: dts: microchip: refactor icicle kit device tree")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/boot/dts/microchip/mpfs.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index 8c3259134194..3095d08453a1 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -192,6 +192,15 @@ plic: interrupt-controller@c000000 {
 			riscv,ndev = <186>;
 		};
 
+		pdma: dma-controller@3000000 {
+			compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
+			reg = <0x0 0x3000000 0x0 0x8000>;
+			interrupt-parent = <&plic>;
+			interrupts = <5 6>, <7 8>, <9 10>, <11 12>;
+			dma-channels = <4>;
+			#dma-cells = <1>;
+		};
+
 		clkcfg: clkcfg@20002000 {
 			compatible = "microchip,mpfs-clkcfg";
 			reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
-- 
2.36.1


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linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [PATCH] riscv: dts: microchip: re-add pdma to mpfs device tree
  2022-06-03  8:38 ` Conor Dooley
@ 2022-06-12 19:57   ` Conor Dooley
  -1 siblings, 0 replies; 4+ messages in thread
From: Conor Dooley @ 2022-06-12 19:57 UTC (permalink / raw)
  To: krzk+dt, conor.dooley, palmer, robh+dt
  Cc: devicetree, linux-riscv, paul.walmsley, zong.li, palmer,
	daire.mcnamara, aou

From: Conor Dooley <conor.dooley@microchip.com>

On Fri, 3 Jun 2022 09:38:26 +0100, Conor Dooley wrote:
> PolarFire SoC /does/ have a SiFive pdma, despite what I suggested as a
> conflict resolution to Zong. Somehow the entry fell through the cracks
> between versions of my dt patches, so re-add it with Zong's updated
> compatible & dma-channels property.
> 
> 

Applied to dt-fixes, thanks!

[1/1] riscv: dts: microchip: re-add pdma to mpfs device tree
      https://git.kernel.org/conor/c/5e757deddd91

Thanks,
Conor.

^ permalink raw reply	[flat|nested] 4+ messages in thread
* Re: [PATCH] riscv: dts: microchip: re-add pdma to mpfs device tree
@ 2022-06-12 19:57   ` Conor Dooley
  0 siblings, 0 replies; 4+ messages in thread
From: Conor Dooley @ 2022-06-12 19:57 UTC (permalink / raw)
  To: krzk+dt, conor.dooley, palmer, robh+dt
  Cc: devicetree, linux-riscv, paul.walmsley, zong.li, palmer,
	daire.mcnamara, aou

From: Conor Dooley <conor.dooley@microchip.com>

On Fri, 3 Jun 2022 09:38:26 +0100, Conor Dooley wrote:
> PolarFire SoC /does/ have a SiFive pdma, despite what I suggested as a
> conflict resolution to Zong. Somehow the entry fell through the cracks
> between versions of my dt patches, so re-add it with Zong's updated
> compatible & dma-channels property.
> 
> 

Applied to dt-fixes, thanks!

[1/1] riscv: dts: microchip: re-add pdma to mpfs device tree
      https://git.kernel.org/conor/c/5e757deddd91

Thanks,
Conor.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-06-12 19:58 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-03  8:38 [PATCH] riscv: dts: microchip: re-add pdma to mpfs device tree Conor Dooley
2022-06-03  8:38 ` Conor Dooley
2022-06-12 19:57 ` Conor Dooley
2022-06-12 19:57   ` Conor Dooley

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