* [Intel-gfx] [PATCH] i915/pmu: Wire GuC backend to per-client busyness
@ 2022-06-14 0:46 Nerlige Ramappa, Umesh
2022-06-14 2:23 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (4 more replies)
0 siblings, 5 replies; 10+ messages in thread
From: Nerlige Ramappa, Umesh @ 2022-06-14 0:46 UTC (permalink / raw)
To: intel-gfx, John.C.Harrison
From: John Harrison <John.C.Harrison@Intel.com>
GuC provides engine_id and last_switch_in ticks for an active context in the
pphwsp. The context image provides a 32 bit total ticks which is the accumulated
by the context (a.k.a. context[CTX_TIMESTAMP]). This information is used to
calculate the context busyness as follows:
If the engine_id is valid, then busyness is the sum of accumulated total ticks
and active ticks. Active ticks is calculated with current gt time as reference.
If engine_id is invalid, busyness is equal to accumulated total ticks.
Since KMD (CPU) retrieves busyness data from 2 sources - GPU and GuC, a
potential race was highlighted in an earlier review that can lead to double
accounting of busyness. While the solution to this is a wip, busyness is still
usable for platforms running GuC submission.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
drivers/gpu/drm/i915/gt/intel_context.c | 11 +++-
drivers/gpu/drm/i915/gt/intel_context.h | 6 +-
drivers/gpu/drm/i915/gt/intel_context_types.h | 3 +
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 5 ++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 55 ++++++++++++++++++-
drivers/gpu/drm/i915/i915_drm_client.c | 6 +-
6 files changed, 75 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
index 4070cb5711d8..a49f313db911 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -576,16 +576,23 @@ void intel_context_bind_parent_child(struct intel_context *parent,
child->parallel.parent = parent;
}
-u64 intel_context_get_total_runtime_ns(const struct intel_context *ce)
+u64 intel_context_get_total_runtime_ns(struct intel_context *ce)
{
u64 total, active;
+ if (ce->ops->update_stats)
+ ce->ops->update_stats(ce);
+
total = ce->stats.runtime.total;
if (ce->ops->flags & COPS_RUNTIME_CYCLES)
total *= ce->engine->gt->clock_period_ns;
active = READ_ONCE(ce->stats.active);
- if (active)
+ /*
+ * GuC backend returns the actual time the context was active, so skip
+ * the calculation here for GuC.
+ */
+ if (active && !intel_engine_uses_guc(ce->engine))
active = intel_context_clock() - active;
return total + active;
diff --git a/drivers/gpu/drm/i915/gt/intel_context.h b/drivers/gpu/drm/i915/gt/intel_context.h
index b7d3214d2cdd..5fc7c19ab29b 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.h
+++ b/drivers/gpu/drm/i915/gt/intel_context.h
@@ -56,7 +56,7 @@ static inline bool intel_context_is_parent(struct intel_context *ce)
return !!ce->parallel.number_children;
}
-static inline bool intel_context_is_pinned(struct intel_context *ce);
+static inline bool intel_context_is_pinned(const struct intel_context *ce);
static inline struct intel_context *
intel_context_to_parent(struct intel_context *ce)
@@ -116,7 +116,7 @@ static inline int intel_context_lock_pinned(struct intel_context *ce)
* Returns: true if the context is currently pinned for use by the GPU.
*/
static inline bool
-intel_context_is_pinned(struct intel_context *ce)
+intel_context_is_pinned(const struct intel_context *ce)
{
return atomic_read(&ce->pin_count);
}
@@ -351,7 +351,7 @@ intel_context_clear_nopreempt(struct intel_context *ce)
clear_bit(CONTEXT_NOPREEMPT, &ce->flags);
}
-u64 intel_context_get_total_runtime_ns(const struct intel_context *ce);
+u64 intel_context_get_total_runtime_ns(struct intel_context *ce);
u64 intel_context_get_avg_runtime_ns(struct intel_context *ce);
static inline u64 intel_context_clock(void)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 09f82545789f..0a3290c99a31 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -55,6 +55,8 @@ struct intel_context_ops {
void (*sched_disable)(struct intel_context *ce);
+ void (*update_stats)(struct intel_context *ce);
+
void (*reset)(struct intel_context *ce);
void (*destroy)(struct kref *kref);
@@ -146,6 +148,7 @@ struct intel_context {
struct ewma_runtime avg;
u64 total;
u32 last;
+ u64 start_gt_clk;
I915_SELFTEST_DECLARE(u32 num_underflow);
I915_SELFTEST_DECLARE(u32 max_underflow);
} runtime;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index b3c9a9327f76..6231ad03e4eb 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -196,6 +196,11 @@ static inline u8 guc_class_to_engine_class(u8 guc_class)
return guc_class_engine_class_map[guc_class];
}
+/* Per context engine usage stats: */
+#define PPHWSP_GUC_CONTEXT_USAGE_STAMP_LO (0x500 / sizeof(u32))
+#define PPHWSP_GUC_CONTEXT_USAGE_STAMP_HI (PPHWSP_GUC_CONTEXT_USAGE_STAMP_LO + 1)
+#define PPHWSP_GUC_CONTEXT_USAGE_ENGINE_ID (PPHWSP_GUC_CONTEXT_USAGE_STAMP_HI + 1)
+
/* Work item for submitting workloads into work queue of GuC. */
struct guc_wq_item {
u32 header;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 5a1dfacf24ea..b86401144417 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -378,7 +378,7 @@ static inline void set_context_guc_id_invalid(struct intel_context *ce)
ce->guc_id.id = GUC_INVALID_CONTEXT_ID;
}
-static inline struct intel_guc *ce_to_guc(struct intel_context *ce)
+static inline struct intel_guc *ce_to_guc(const struct intel_context *ce)
{
return &ce->engine->gt->uc.guc;
}
@@ -1323,13 +1323,16 @@ static void __update_guc_busyness_stats(struct intel_guc *guc)
spin_unlock_irqrestore(&guc->timestamp.lock, flags);
}
+static void __guc_context_update_clks(struct intel_context *ce);
static void guc_timestamp_ping(struct work_struct *wrk)
{
struct intel_guc *guc = container_of(wrk, typeof(*guc),
timestamp.work.work);
struct intel_uc *uc = container_of(guc, typeof(*uc), guc);
struct intel_gt *gt = guc_to_gt(guc);
+ struct intel_context *ce;
intel_wakeref_t wakeref;
+ unsigned long index;
int srcu, ret;
/*
@@ -1343,6 +1346,10 @@ static void guc_timestamp_ping(struct work_struct *wrk)
with_intel_runtime_pm(>->i915->runtime_pm, wakeref)
__update_guc_busyness_stats(guc);
+ /* adjust context stats for overflow */
+ xa_for_each(&guc->context_lookup, index, ce)
+ __guc_context_update_clks(ce);
+
intel_gt_reset_unlock(gt, srcu);
mod_delayed_work(system_highpri_wq, &guc->timestamp.work,
@@ -1405,6 +1412,48 @@ void intel_guc_busyness_unpark(struct intel_gt *gt)
guc->timestamp.ping_delay);
}
+static void __guc_context_update_clks(struct intel_context *ce)
+{
+ struct intel_guc *guc = ce_to_guc(ce);
+ struct intel_gt *gt = ce->engine->gt;
+ u32 *pphwsp, last_switch, engine_id;
+ u64 start_gt_clk = 0, active = 0;
+ unsigned long flags;
+ ktime_t unused;
+
+ spin_lock_irqsave(&guc->timestamp.lock, flags);
+
+ pphwsp = ((void *)ce->lrc_reg_state) - LRC_STATE_OFFSET;
+ last_switch = READ_ONCE(pphwsp[PPHWSP_GUC_CONTEXT_USAGE_STAMP_LO]);
+ engine_id = READ_ONCE(pphwsp[PPHWSP_GUC_CONTEXT_USAGE_ENGINE_ID]);
+
+ guc_update_pm_timestamp(guc, &unused);
+
+ if (engine_id != 0xffffffff && last_switch) {
+ start_gt_clk = READ_ONCE(ce->stats.runtime.start_gt_clk);
+ __extend_last_switch(guc, &start_gt_clk, last_switch);
+ active = intel_gt_clock_interval_to_ns(gt, guc->timestamp.gt_stamp - start_gt_clk);
+ WRITE_ONCE(ce->stats.runtime.start_gt_clk, start_gt_clk);
+ WRITE_ONCE(ce->stats.active, active);
+ } else {
+ lrc_update_runtime(ce);
+ }
+
+ spin_unlock_irqrestore(&guc->timestamp.lock, flags);
+}
+
+static void guc_context_update_stats(struct intel_context *ce)
+{
+ if (!intel_context_pin_if_active(ce)) {
+ WRITE_ONCE(ce->stats.runtime.start_gt_clk, 0);
+ WRITE_ONCE(ce->stats.active, 0);
+ return;
+ }
+
+ __guc_context_update_clks(ce);
+ intel_context_unpin(ce);
+}
+
static inline bool
submission_disabled(struct intel_guc *guc)
{
@@ -2585,6 +2634,7 @@ static void guc_context_unpin(struct intel_context *ce)
{
struct intel_guc *guc = ce_to_guc(ce);
+ lrc_update_runtime(ce);
unpin_guc_id(guc, ce);
lrc_unpin(ce);
@@ -3183,6 +3233,7 @@ static void remove_from_context(struct i915_request *rq)
}
static const struct intel_context_ops guc_context_ops = {
+ .flags = COPS_RUNTIME_CYCLES,
.alloc = guc_context_alloc,
.pre_pin = guc_context_pre_pin,
@@ -3199,6 +3250,8 @@ static const struct intel_context_ops guc_context_ops = {
.sched_disable = guc_context_sched_disable,
+ .update_stats = guc_context_update_stats,
+
.reset = lrc_reset,
.destroy = guc_context_destroy,
diff --git a/drivers/gpu/drm/i915/i915_drm_client.c b/drivers/gpu/drm/i915/i915_drm_client.c
index 18d38cb59923..118db6f03f15 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.c
+++ b/drivers/gpu/drm/i915/i915_drm_client.c
@@ -146,11 +146,7 @@ void i915_drm_client_fdinfo(struct seq_file *m, struct file *f)
PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
seq_printf(m, "drm-client-id:\t%u\n", client->id);
- /*
- * Temporarily skip showing client engine information with GuC submission till
- * fetching engine busyness is implemented in the GuC submission backend
- */
- if (GRAPHICS_VER(i915) < 8 || intel_uc_uses_guc_submission(&i915->gt0.uc))
+ if (GRAPHICS_VER(i915) < 8)
return;
for (i = 0; i < ARRAY_SIZE(uabi_class_names); i++)
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915/pmu: Wire GuC backend to per-client busyness
2022-06-14 0:46 [Intel-gfx] [PATCH] i915/pmu: Wire GuC backend to per-client busyness Nerlige Ramappa, Umesh
@ 2022-06-14 2:23 ` Patchwork
2022-06-14 2:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2022-06-14 2:23 UTC (permalink / raw)
To: Umesh Nerlige Ramappa; +Cc: intel-gfx
== Series Details ==
Series: i915/pmu: Wire GuC backend to per-client busyness
URL : https://patchwork.freedesktop.org/series/105085/
State : warning
== Summary ==
Error: dim checkpatch failed
6fef335b9770 i915/pmu: Wire GuC backend to per-client busyness
-:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#6:
GuC provides engine_id and last_switch_in ticks for an active context in the
total: 0 errors, 1 warnings, 0 checks, 191 lines checked
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915/pmu: Wire GuC backend to per-client busyness
2022-06-14 0:46 [Intel-gfx] [PATCH] i915/pmu: Wire GuC backend to per-client busyness Nerlige Ramappa, Umesh
2022-06-14 2:23 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2022-06-14 2:23 ` Patchwork
2022-06-14 2:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2022-06-14 2:23 UTC (permalink / raw)
To: Umesh Nerlige Ramappa; +Cc: intel-gfx
== Series Details ==
Series: i915/pmu: Wire GuC backend to per-client busyness
URL : https://patchwork.freedesktop.org/series/105085/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for i915/pmu: Wire GuC backend to per-client busyness
2022-06-14 0:46 [Intel-gfx] [PATCH] i915/pmu: Wire GuC backend to per-client busyness Nerlige Ramappa, Umesh
2022-06-14 2:23 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2022-06-14 2:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-06-14 2:45 ` Patchwork
2022-06-14 13:30 ` [Intel-gfx] [PATCH] " Tvrtko Ursulin
2022-06-15 0:29 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
4 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2022-06-14 2:45 UTC (permalink / raw)
To: Umesh Nerlige Ramappa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8296 bytes --]
== Series Details ==
Series: i915/pmu: Wire GuC backend to per-client busyness
URL : https://patchwork.freedesktop.org/series/105085/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11755 -> Patchwork_105085v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/index.html
Participating hosts (44 -> 41)
------------------------------
Missing (3): fi-cml-u2 bat-adlm-1 bat-jsl-2
Known issues
------------
Here are the changes found in Patchwork_105085v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258: [PASS][1] -> [INCOMPLETE][2] ([i915#4785])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
- fi-bdw-5557u: NOTRUN -> [INCOMPLETE][3] ([i915#3921])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/fi-bdw-5557u/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][4] -> [DMESG-FAIL][5] ([i915#4528])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/fi-blb-e6850/igt@i915_selftest@live@requests.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/fi-blb-e6850/igt@i915_selftest@live@requests.html
* igt@kms_busy@basic@modeset:
- bat-adlp-4: [PASS][6] -> [DMESG-WARN][7] ([i915#3576])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/bat-adlp-4/igt@kms_busy@basic@modeset.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/bat-adlp-4/igt@kms_busy@basic@modeset.html
* igt@kms_flip@basic-flip-vs-dpms@a-edp1:
- fi-tgl-u2: [PASS][8] -> [DMESG-WARN][9] ([i915#402])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/fi-tgl-u2/igt@kms_flip@basic-flip-vs-dpms@a-edp1.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/fi-tgl-u2/igt@kms_flip@basic-flip-vs-dpms@a-edp1.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-kbl-guc: NOTRUN -> [SKIP][10] ([fdo#109271])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/fi-kbl-guc/igt@kms_force_connector_basic@force-load-detect.html
* igt@runner@aborted:
- fi-hsw-g3258: NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#4312])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/fi-hsw-g3258/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u: [DMESG-FAIL][12] ([i915#62]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@gem_contexts:
- fi-bdw-5557u: [INCOMPLETE][14] ([i915#5502]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@gt_heartbeat:
- {fi-jsl-1}: [DMESG-FAIL][16] ([i915#5334]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/fi-jsl-1/igt@i915_selftest@live@gt_heartbeat.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/fi-jsl-1/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [DMESG-FAIL][18] ([i915#4494] / [i915#4957]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
- bat-dg1-6: [DMESG-FAIL][20] ([i915#4494] / [i915#4957]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@late_gt_pm:
- fi-cfl-8109u: [DMESG-WARN][22] ([i915#5904]) -> [PASS][23] +29 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u: [DMESG-WARN][24] ([i915#5904] / [i915#62]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/fi-cfl-8109u/igt@i915_suspend@basic-s2idle-without-i915.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/fi-cfl-8109u/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@kms_busy@basic@flip:
- fi-tgl-u2: [DMESG-WARN][26] ([i915#402]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/fi-tgl-u2/igt@kms_busy@basic@flip.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/fi-tgl-u2/igt@kms_busy@basic@flip.html
* igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- bat-adlp-4: [DMESG-WARN][28] ([i915#3576]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
* igt@kms_flip@basic-flip-vs-modeset@b-edp1:
- {bat-adlp-6}: [DMESG-WARN][30] ([i915#3576]) -> [PASS][31] +2 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u: [DMESG-WARN][32] ([i915#62]) -> [PASS][33] +15 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5502]: https://gitlab.freedesktop.org/drm/intel/issues/5502
[i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
[i915#5904]: https://gitlab.freedesktop.org/drm/intel/issues/5904
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
Build changes
-------------
* Linux: CI_DRM_11755 -> Patchwork_105085v1
CI-20190529: 20190529
CI_DRM_11755: 65b93b94d6bc932ed60bb3fd9d68242db25b1f3b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6522: 5be5a1a1f168a59614101b77385f05f12ec7d30a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_105085v1: 65b93b94d6bc932ed60bb3fd9d68242db25b1f3b @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
f19933130bcc i915/pmu: Wire GuC backend to per-client busyness
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/index.html
[-- Attachment #2: Type: text/html, Size: 9874 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] i915/pmu: Wire GuC backend to per-client busyness
2022-06-14 0:46 [Intel-gfx] [PATCH] i915/pmu: Wire GuC backend to per-client busyness Nerlige Ramappa, Umesh
` (2 preceding siblings ...)
2022-06-14 2:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-06-14 13:30 ` Tvrtko Ursulin
2022-06-14 16:32 ` Umesh Nerlige Ramappa
2022-06-15 0:29 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
4 siblings, 1 reply; 10+ messages in thread
From: Tvrtko Ursulin @ 2022-06-14 13:30 UTC (permalink / raw)
To: Nerlige Ramappa, Umesh, intel-gfx, John.C.Harrison
On 14/06/2022 01:46, Nerlige Ramappa, Umesh wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> GuC provides engine_id and last_switch_in ticks for an active context in the
> pphwsp. The context image provides a 32 bit total ticks which is the accumulated
> by the context (a.k.a. context[CTX_TIMESTAMP]). This information is used to
> calculate the context busyness as follows:
>
> If the engine_id is valid, then busyness is the sum of accumulated total ticks
> and active ticks. Active ticks is calculated with current gt time as reference.
>
> If engine_id is invalid, busyness is equal to accumulated total ticks.
>
> Since KMD (CPU) retrieves busyness data from 2 sources - GPU and GuC, a
> potential race was highlighted in an earlier review that can lead to double
> accounting of busyness. While the solution to this is a wip, busyness is still
> usable for platforms running GuC submission.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_context.c | 11 +++-
> drivers/gpu/drm/i915/gt/intel_context.h | 6 +-
> drivers/gpu/drm/i915/gt/intel_context_types.h | 3 +
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 5 ++
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 55 ++++++++++++++++++-
> drivers/gpu/drm/i915/i915_drm_client.c | 6 +-
> 6 files changed, 75 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
> index 4070cb5711d8..a49f313db911 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context.c
> +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> @@ -576,16 +576,23 @@ void intel_context_bind_parent_child(struct intel_context *parent,
> child->parallel.parent = parent;
> }
>
> -u64 intel_context_get_total_runtime_ns(const struct intel_context *ce)
> +u64 intel_context_get_total_runtime_ns(struct intel_context *ce)
> {
> u64 total, active;
>
> + if (ce->ops->update_stats)
> + ce->ops->update_stats(ce);
> +
> total = ce->stats.runtime.total;
> if (ce->ops->flags & COPS_RUNTIME_CYCLES)
> total *= ce->engine->gt->clock_period_ns;
>
> active = READ_ONCE(ce->stats.active);
> - if (active)
> + /*
> + * GuC backend returns the actual time the context was active, so skip
> + * the calculation here for GuC.
> + */
> + if (active && !intel_engine_uses_guc(ce->engine))
What is the point of looking at ce->stats.active in GuC mode? I see that
guc_context_update_stats/__guc_context_update_clks touches it, but I
can't spot that there is a purpose to it. This is the only conditional
reading it but it is short-circuited in GuC case.
Also, since a GuC only vfunc (update_stats) has been added, I wonder why
not just fork the whole runtime query (ce->get_total_runtime_ns). I
think that would end up cleaner.
> active = intel_context_clock() - active;
>
> return total + active;
> diff --git a/drivers/gpu/drm/i915/gt/intel_context.h b/drivers/gpu/drm/i915/gt/intel_context.h
> index b7d3214d2cdd..5fc7c19ab29b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context.h
> +++ b/drivers/gpu/drm/i915/gt/intel_context.h
> @@ -56,7 +56,7 @@ static inline bool intel_context_is_parent(struct intel_context *ce)
> return !!ce->parallel.number_children;
> }
>
> -static inline bool intel_context_is_pinned(struct intel_context *ce);
> +static inline bool intel_context_is_pinned(const struct intel_context *ce);
>
> static inline struct intel_context *
> intel_context_to_parent(struct intel_context *ce)
> @@ -116,7 +116,7 @@ static inline int intel_context_lock_pinned(struct intel_context *ce)
> * Returns: true if the context is currently pinned for use by the GPU.
> */
> static inline bool
> -intel_context_is_pinned(struct intel_context *ce)
> +intel_context_is_pinned(const struct intel_context *ce)
> {
> return atomic_read(&ce->pin_count);
> }
> @@ -351,7 +351,7 @@ intel_context_clear_nopreempt(struct intel_context *ce)
> clear_bit(CONTEXT_NOPREEMPT, &ce->flags);
> }
>
> -u64 intel_context_get_total_runtime_ns(const struct intel_context *ce);
> +u64 intel_context_get_total_runtime_ns(struct intel_context *ce);
> u64 intel_context_get_avg_runtime_ns(struct intel_context *ce);
>
> static inline u64 intel_context_clock(void)
> diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h
> index 09f82545789f..0a3290c99a31 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
> @@ -55,6 +55,8 @@ struct intel_context_ops {
>
> void (*sched_disable)(struct intel_context *ce);
>
> + void (*update_stats)(struct intel_context *ce);
> +
> void (*reset)(struct intel_context *ce);
> void (*destroy)(struct kref *kref);
>
> @@ -146,6 +148,7 @@ struct intel_context {
> struct ewma_runtime avg;
> u64 total;
> u32 last;
> + u64 start_gt_clk;
> I915_SELFTEST_DECLARE(u32 num_underflow);
> I915_SELFTEST_DECLARE(u32 max_underflow);
> } runtime;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> index b3c9a9327f76..6231ad03e4eb 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> @@ -196,6 +196,11 @@ static inline u8 guc_class_to_engine_class(u8 guc_class)
> return guc_class_engine_class_map[guc_class];
> }
>
> +/* Per context engine usage stats: */
> +#define PPHWSP_GUC_CONTEXT_USAGE_STAMP_LO (0x500 / sizeof(u32))
> +#define PPHWSP_GUC_CONTEXT_USAGE_STAMP_HI (PPHWSP_GUC_CONTEXT_USAGE_STAMP_LO + 1)
> +#define PPHWSP_GUC_CONTEXT_USAGE_ENGINE_ID (PPHWSP_GUC_CONTEXT_USAGE_STAMP_HI + 1)
> +
> /* Work item for submitting workloads into work queue of GuC. */
> struct guc_wq_item {
> u32 header;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 5a1dfacf24ea..b86401144417 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -378,7 +378,7 @@ static inline void set_context_guc_id_invalid(struct intel_context *ce)
> ce->guc_id.id = GUC_INVALID_CONTEXT_ID;
> }
>
> -static inline struct intel_guc *ce_to_guc(struct intel_context *ce)
> +static inline struct intel_guc *ce_to_guc(const struct intel_context *ce)
> {
> return &ce->engine->gt->uc.guc;
> }
> @@ -1323,13 +1323,16 @@ static void __update_guc_busyness_stats(struct intel_guc *guc)
> spin_unlock_irqrestore(&guc->timestamp.lock, flags);
> }
>
> +static void __guc_context_update_clks(struct intel_context *ce);
> static void guc_timestamp_ping(struct work_struct *wrk)
> {
> struct intel_guc *guc = container_of(wrk, typeof(*guc),
> timestamp.work.work);
> struct intel_uc *uc = container_of(guc, typeof(*uc), guc);
> struct intel_gt *gt = guc_to_gt(guc);
> + struct intel_context *ce;
> intel_wakeref_t wakeref;
> + unsigned long index;
> int srcu, ret;
>
> /*
> @@ -1343,6 +1346,10 @@ static void guc_timestamp_ping(struct work_struct *wrk)
> with_intel_runtime_pm(>->i915->runtime_pm, wakeref)
> __update_guc_busyness_stats(guc);
>
> + /* adjust context stats for overflow */
> + xa_for_each(&guc->context_lookup, index, ce)
> + __guc_context_update_clks(ce);
> +
> intel_gt_reset_unlock(gt, srcu);
>
> mod_delayed_work(system_highpri_wq, &guc->timestamp.work,
> @@ -1405,6 +1412,48 @@ void intel_guc_busyness_unpark(struct intel_gt *gt)
> guc->timestamp.ping_delay);
> }
>
> +static void __guc_context_update_clks(struct intel_context *ce)
> +{
> + struct intel_guc *guc = ce_to_guc(ce);
> + struct intel_gt *gt = ce->engine->gt;
> + u32 *pphwsp, last_switch, engine_id;
> + u64 start_gt_clk = 0, active = 0;
No need to init these two.
> + unsigned long flags;
> + ktime_t unused;
> +
> + spin_lock_irqsave(&guc->timestamp.lock, flags);
> +
> + pphwsp = ((void *)ce->lrc_reg_state) - LRC_STATE_OFFSET;
> + last_switch = READ_ONCE(pphwsp[PPHWSP_GUC_CONTEXT_USAGE_STAMP_LO]);
> + engine_id = READ_ONCE(pphwsp[PPHWSP_GUC_CONTEXT_USAGE_ENGINE_ID]);
> +
> + guc_update_pm_timestamp(guc, &unused);
> +
> + if (engine_id != 0xffffffff && last_switch) {
> + start_gt_clk = READ_ONCE(ce->stats.runtime.start_gt_clk);
> + __extend_last_switch(guc, &start_gt_clk, last_switch);
> + active = intel_gt_clock_interval_to_ns(gt, guc->timestamp.gt_stamp - start_gt_clk);
> + WRITE_ONCE(ce->stats.runtime.start_gt_clk, start_gt_clk);
> + WRITE_ONCE(ce->stats.active, active);
> + } else {
> + lrc_update_runtime(ce);
Why is this called from here? Presumably it was called already from
guc_context_unpin if here code things context is not active. Or will be
called shortly, once context save is done.
Also, some comments here describing the double accounting race would be
good. Or if there are some already in the physical engine code just
reference that function.
Regards,
Tvrtko
> + }
> +
> + spin_unlock_irqrestore(&guc->timestamp.lock, flags);
> +}
> +
> +static void guc_context_update_stats(struct intel_context *ce)
> +{
> + if (!intel_context_pin_if_active(ce)) {
> + WRITE_ONCE(ce->stats.runtime.start_gt_clk, 0);
> + WRITE_ONCE(ce->stats.active, 0);
> + return;
> + }
> +
> + __guc_context_update_clks(ce);
> + intel_context_unpin(ce);
> +}
> +
> static inline bool
> submission_disabled(struct intel_guc *guc)
> {
> @@ -2585,6 +2634,7 @@ static void guc_context_unpin(struct intel_context *ce)
> {
> struct intel_guc *guc = ce_to_guc(ce);
>
> + lrc_update_runtime(ce);
> unpin_guc_id(guc, ce);
> lrc_unpin(ce);
>
> @@ -3183,6 +3233,7 @@ static void remove_from_context(struct i915_request *rq)
> }
>
> static const struct intel_context_ops guc_context_ops = {
> + .flags = COPS_RUNTIME_CYCLES,
> .alloc = guc_context_alloc,
>
> .pre_pin = guc_context_pre_pin,
> @@ -3199,6 +3250,8 @@ static const struct intel_context_ops guc_context_ops = {
>
> .sched_disable = guc_context_sched_disable,
>
> + .update_stats = guc_context_update_stats,
> +
> .reset = lrc_reset,
> .destroy = guc_context_destroy,
>
> diff --git a/drivers/gpu/drm/i915/i915_drm_client.c b/drivers/gpu/drm/i915/i915_drm_client.c
> index 18d38cb59923..118db6f03f15 100644
> --- a/drivers/gpu/drm/i915/i915_drm_client.c
> +++ b/drivers/gpu/drm/i915/i915_drm_client.c
> @@ -146,11 +146,7 @@ void i915_drm_client_fdinfo(struct seq_file *m, struct file *f)
> PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
> seq_printf(m, "drm-client-id:\t%u\n", client->id);
>
> - /*
> - * Temporarily skip showing client engine information with GuC submission till
> - * fetching engine busyness is implemented in the GuC submission backend
> - */
> - if (GRAPHICS_VER(i915) < 8 || intel_uc_uses_guc_submission(&i915->gt0.uc))
> + if (GRAPHICS_VER(i915) < 8)
> return;
>
> for (i = 0; i < ARRAY_SIZE(uabi_class_names); i++)
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] i915/pmu: Wire GuC backend to per-client busyness
2022-06-14 13:30 ` [Intel-gfx] [PATCH] " Tvrtko Ursulin
@ 2022-06-14 16:32 ` Umesh Nerlige Ramappa
2022-06-15 7:08 ` Tvrtko Ursulin
0 siblings, 1 reply; 10+ messages in thread
From: Umesh Nerlige Ramappa @ 2022-06-14 16:32 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
On Tue, Jun 14, 2022 at 02:30:42PM +0100, Tvrtko Ursulin wrote:
>
>On 14/06/2022 01:46, Nerlige Ramappa, Umesh wrote:
>>From: John Harrison <John.C.Harrison@Intel.com>
>>
>>GuC provides engine_id and last_switch_in ticks for an active context in the
>>pphwsp. The context image provides a 32 bit total ticks which is the accumulated
>>by the context (a.k.a. context[CTX_TIMESTAMP]). This information is used to
>>calculate the context busyness as follows:
>>
>>If the engine_id is valid, then busyness is the sum of accumulated total ticks
>>and active ticks. Active ticks is calculated with current gt time as reference.
>>
>>If engine_id is invalid, busyness is equal to accumulated total ticks.
>>
>>Since KMD (CPU) retrieves busyness data from 2 sources - GPU and GuC, a
>>potential race was highlighted in an earlier review that can lead to double
>>accounting of busyness. While the solution to this is a wip, busyness is still
>>usable for platforms running GuC submission.
>>
>>Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>>Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>>---
>> drivers/gpu/drm/i915/gt/intel_context.c | 11 +++-
>> drivers/gpu/drm/i915/gt/intel_context.h | 6 +-
>> drivers/gpu/drm/i915/gt/intel_context_types.h | 3 +
>> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 5 ++
>> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 55 ++++++++++++++++++-
>> drivers/gpu/drm/i915/i915_drm_client.c | 6 +-
>> 6 files changed, 75 insertions(+), 11 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
>>index 4070cb5711d8..a49f313db911 100644
>>--- a/drivers/gpu/drm/i915/gt/intel_context.c
>>+++ b/drivers/gpu/drm/i915/gt/intel_context.c
>>@@ -576,16 +576,23 @@ void intel_context_bind_parent_child(struct intel_context *parent,
>> child->parallel.parent = parent;
>> }
>>-u64 intel_context_get_total_runtime_ns(const struct intel_context *ce)
>>+u64 intel_context_get_total_runtime_ns(struct intel_context *ce)
>> {
>> u64 total, active;
>>+ if (ce->ops->update_stats)
>>+ ce->ops->update_stats(ce);
>>+
>> total = ce->stats.runtime.total;
>> if (ce->ops->flags & COPS_RUNTIME_CYCLES)
>> total *= ce->engine->gt->clock_period_ns;
>> active = READ_ONCE(ce->stats.active);
>>- if (active)
>>+ /*
>>+ * GuC backend returns the actual time the context was active, so skip
>>+ * the calculation here for GuC.
>>+ */
>>+ if (active && !intel_engine_uses_guc(ce->engine))
>
>What is the point of looking at ce->stats.active in GuC mode? I see
>that guc_context_update_stats/__guc_context_update_clks touches it,
>but I can't spot that there is a purpose to it. This is the only
>conditional reading it but it is short-circuited in GuC case.
>
>Also, since a GuC only vfunc (update_stats) has been added, I wonder
>why not just fork the whole runtime query (ce->get_total_runtime_ns).
>I think that would end up cleaner.
>
>> active = intel_context_clock() - active;
>> return total + active;
In case of GuC the active is used directly here since the active updated
in update_stats is equal to the active time of the context already. I
will look into separate vfunc.
>>diff --git a/drivers/gpu/drm/i915/gt/intel_context.h b/drivers/gpu/drm/i915/gt/intel_context.h
>>index b7d3214d2cdd..5fc7c19ab29b 100644
>>--- a/drivers/gpu/drm/i915/gt/intel_context.h
>>+++ b/drivers/gpu/drm/i915/gt/intel_context.h
>>@@ -56,7 +56,7 @@ static inline bool intel_context_is_parent(struct intel_context *ce)
>> return !!ce->parallel.number_children;
>> }
snip
>>+static void __guc_context_update_clks(struct intel_context *ce)
>>+{
>>+ struct intel_guc *guc = ce_to_guc(ce);
>>+ struct intel_gt *gt = ce->engine->gt;
>>+ u32 *pphwsp, last_switch, engine_id;
>>+ u64 start_gt_clk = 0, active = 0;
>
>No need to init these two.
>
>>+ unsigned long flags;
>>+ ktime_t unused;
>>+
>>+ spin_lock_irqsave(&guc->timestamp.lock, flags);
>>+
>>+ pphwsp = ((void *)ce->lrc_reg_state) - LRC_STATE_OFFSET;
>>+ last_switch = READ_ONCE(pphwsp[PPHWSP_GUC_CONTEXT_USAGE_STAMP_LO]);
>>+ engine_id = READ_ONCE(pphwsp[PPHWSP_GUC_CONTEXT_USAGE_ENGINE_ID]);
>>+
>>+ guc_update_pm_timestamp(guc, &unused);
>>+
>>+ if (engine_id != 0xffffffff && last_switch) {
>>+ start_gt_clk = READ_ONCE(ce->stats.runtime.start_gt_clk);
>>+ __extend_last_switch(guc, &start_gt_clk, last_switch);
>>+ active = intel_gt_clock_interval_to_ns(gt, guc->timestamp.gt_stamp - start_gt_clk);
>>+ WRITE_ONCE(ce->stats.runtime.start_gt_clk, start_gt_clk);
>>+ WRITE_ONCE(ce->stats.active, active);
>>+ } else {
>>+ lrc_update_runtime(ce);
>
>Why is this called from here? Presumably it was called already from
>guc_context_unpin if here code things context is not active. Or will
>be called shortly, once context save is done.
guc_context_unpin is only called in the path of ce->sched_disable. The
sched_disable is implemented in GuC (H2G message). Once the
corresponding G2H response is received, the context is actually
unpinned, eventually calling guc_context_unpin. Also the context may not
necessarily be disabled after each context exit.
>
>Also, some comments here describing the double accounting race would
>be good. Or if there are some already in the physical engine code just
>reference that function.
Will do,
Thanks,
Umesh
>
>Regards,
>
>Tvrtko
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for i915/pmu: Wire GuC backend to per-client busyness
2022-06-14 0:46 [Intel-gfx] [PATCH] i915/pmu: Wire GuC backend to per-client busyness Nerlige Ramappa, Umesh
` (3 preceding siblings ...)
2022-06-14 13:30 ` [Intel-gfx] [PATCH] " Tvrtko Ursulin
@ 2022-06-15 0:29 ` Patchwork
4 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2022-06-15 0:29 UTC (permalink / raw)
To: Umesh Nerlige Ramappa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 43779 bytes --]
== Series Details ==
Series: i915/pmu: Wire GuC backend to per-client busyness
URL : https://patchwork.freedesktop.org/series/105085/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11755_full -> Patchwork_105085v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (12 -> 12)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_105085v1_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@device_reset@unbind-reset-rebind:
- {shard-dg1}: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-dg1-16/igt@device_reset@unbind-reset-rebind.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-dg1-15/igt@device_reset@unbind-reset-rebind.html
* {igt@kms_cdclk@mode-transition-all-outputs}:
- shard-iclb: NOTRUN -> [SKIP][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb5/igt@kms_cdclk@mode-transition-all-outputs.html
Known issues
------------
Here are the changes found in Patchwork_105085v1_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-skl: ([PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [FAIL][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22]) ([i915#5032]) -> ([PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl10/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl9/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl9/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl9/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl7/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl7/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl6/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl6/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl5/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl4/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl4/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl4/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl3/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl3/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl2/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl1/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl1/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl1/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl10/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl9/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl9/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl9/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl7/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl7/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl7/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl7/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl6/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl6/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl6/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl4/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl4/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl4/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl3/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl3/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl3/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl2/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl2/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl1/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl1/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl10/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl10/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl10/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl10/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_ccs@block-copy-compressed:
- shard-iclb: NOTRUN -> [SKIP][47] ([i915#5327])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb2/igt@gem_ccs@block-copy-compressed.html
* igt@gem_ctx_persistence@hang:
- shard-skl: NOTRUN -> [SKIP][48] ([fdo#109271]) +368 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl9/igt@gem_ctx_persistence@hang.html
* igt@gem_ctx_persistence@smoketest:
- shard-snb: NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#1099])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-snb4/igt@gem_ctx_persistence@smoketest.html
* igt@gem_eio@in-flight-10ms:
- shard-skl: NOTRUN -> [TIMEOUT][50] ([i915#3063])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl1/igt@gem_eio@in-flight-10ms.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [PASS][51] -> [SKIP][52] ([i915#4525]) +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb2/igt@gem_exec_balancer@parallel-bb-first.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb5/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][53] -> [FAIL][54] ([i915#2842])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-apl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-apl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][55] ([i915#2842])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb4/igt@gem_exec_fair@basic-none@vcs1.html
- shard-kbl: [PASS][56] -> [FAIL][57] ([i915#2842]) +2 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-kbl7/igt@gem_exec_fair@basic-none@vcs1.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-kbl6/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-iclb: [PASS][58] -> [FAIL][59] ([i915#2842])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb7/igt@gem_exec_fair@basic-pace@rcs0.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb5/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_params@no-vebox:
- shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109283])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb5/igt@gem_exec_params@no-vebox.html
* igt@gem_lmem_swapping@basic:
- shard-skl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#4613]) +3 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl1/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@verify-random:
- shard-iclb: NOTRUN -> [SKIP][62] ([i915#4613])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb2/igt@gem_lmem_swapping@verify-random.html
* igt@gem_userptr_blits@invalid-mmap-offset-unsync:
- shard-iclb: NOTRUN -> [SKIP][63] ([i915#3297])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb2/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
* igt@i915_module_load@load:
- shard-skl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#6227])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl6/igt@i915_module_load@load.html
* igt@i915_pm_dc@dc6-psr:
- shard-skl: NOTRUN -> [FAIL][65] ([i915#454])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl6/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: NOTRUN -> [WARN][66] ([i915#2684])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb5/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_suspend@debugfs-reader:
- shard-kbl: [PASS][67] -> [INCOMPLETE][68] ([i915#3614])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-kbl7/igt@i915_suspend@debugfs-reader.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-kbl4/igt@i915_suspend@debugfs-reader.html
* igt@i915_suspend@fence-restore-untiled:
- shard-skl: [PASS][69] -> [INCOMPLETE][70] ([i915#4817] / [i915#4939])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl10/igt@i915_suspend@fence-restore-untiled.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl10/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][71] ([i915#5286]) +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb2/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][72] ([fdo#110725] / [fdo#111614])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb5/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][73] ([fdo#109271]) +39 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-apl3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][74] ([i915#3743]) +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl9/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][75] ([fdo#109278] / [i915#3886]) +2 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb2/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#3886]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-glk7/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#3886]) +11 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl2/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#3886])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-apl3/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_dg2_rc_ccs:
- shard-iclb: NOTRUN -> [SKIP][79] ([fdo#109278]) +13 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb5/igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_dg2_rc_ccs.html
* igt@kms_chamelium@dp-edid-change-during-suspend:
- shard-glk: NOTRUN -> [SKIP][80] ([fdo#109271] / [fdo#111827]) +2 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-glk7/igt@kms_chamelium@dp-edid-change-during-suspend.html
* igt@kms_chamelium@hdmi-edid-read:
- shard-snb: NOTRUN -> [SKIP][81] ([fdo#109271] / [fdo#111827]) +4 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-snb4/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_chamelium@hdmi-hpd:
- shard-iclb: NOTRUN -> [SKIP][82] ([fdo#109284] / [fdo#111827]) +5 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb5/igt@kms_chamelium@hdmi-hpd.html
* igt@kms_chamelium@hdmi-hpd-storm-disable:
- shard-apl: NOTRUN -> [SKIP][83] ([fdo#109271] / [fdo#111827]) +2 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-apl3/igt@kms_chamelium@hdmi-hpd-storm-disable.html
* igt@kms_color_chamelium@pipe-a-ctm-0-5:
- shard-skl: NOTRUN -> [SKIP][84] ([fdo#109271] / [fdo#111827]) +21 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl6/igt@kms_color_chamelium@pipe-a-ctm-0-5.html
* igt@kms_color_chamelium@pipe-d-ctm-negative:
- shard-iclb: NOTRUN -> [SKIP][85] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb5/igt@kms_color_chamelium@pipe-d-ctm-negative.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-apl: NOTRUN -> [DMESG-WARN][86] ([i915#180])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-apl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-512x170-random:
- shard-iclb: NOTRUN -> [SKIP][87] ([fdo#109278] / [fdo#109279]) +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb5/igt@kms_cursor_crc@pipe-c-cursor-512x170-random.html
* igt@kms_cursor_crc@pipe-d-cursor-128x128-onscreen:
- shard-skl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#1888])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl1/igt@kms_cursor_crc@pipe-d-cursor-128x128-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-64x21-rapid-movement:
- shard-glk: NOTRUN -> [SKIP][89] ([fdo#109271]) +28 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-glk7/igt@kms_cursor_crc@pipe-d-cursor-64x21-rapid-movement.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: NOTRUN -> [FAIL][90] ([i915#2346] / [i915#533])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_draw_crc@draw-method-rgb565-render-4tiled:
- shard-iclb: NOTRUN -> [SKIP][91] ([i915#5287])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb2/igt@kms_draw_crc@draw-method-rgb565-render-4tiled.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
- shard-iclb: NOTRUN -> [SKIP][92] ([fdo#109274])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb5/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-apl: [PASS][93] -> [DMESG-WARN][94] ([i915#180]) +3 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-apl1/igt@kms_flip@flip-vs-suspend@c-dp1.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-apl8/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
- shard-skl: NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#3701]) +2 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
- shard-glk: [PASS][96] -> [FAIL][97] ([i915#4911])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-glk7/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-onoff:
- shard-iclb: NOTRUN -> [SKIP][98] ([fdo#109280]) +12 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-onoff.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-iclb: NOTRUN -> [SKIP][99] ([i915#3555])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb5/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1:
- shard-kbl: [PASS][100] -> [FAIL][101] ([i915#1188]) +1 similar issue
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-kbl4/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-kbl7/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][102] ([fdo#109271] / [i915#533]) +2 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl1/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-skl: NOTRUN -> [FAIL][103] ([fdo#108145] / [i915#265])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-b-edp-1:
- shard-iclb: NOTRUN -> [SKIP][104] ([i915#5176]) +2 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb2/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-b-edp-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1:
- shard-iclb: [PASS][105] -> [SKIP][106] ([i915#5235]) +2 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb6/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html
* igt@kms_prime@basic-crc@first-to-second:
- shard-iclb: NOTRUN -> [SKIP][107] ([i915#1836])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb2/igt@kms_prime@basic-crc@first-to-second.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-tglb: NOTRUN -> [SKIP][108] ([i915#2920])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-tglb3/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
- shard-skl: NOTRUN -> [SKIP][109] ([fdo#109271] / [i915#658]) +1 similar issue
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl1/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: NOTRUN -> [SKIP][110] ([fdo#109441])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb5/igt@kms_psr@psr2_no_drrs.html
* igt@kms_psr@psr2_primary_render:
- shard-iclb: [PASS][111] -> [SKIP][112] ([fdo#109441]) +1 similar issue
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb2/igt@kms_psr@psr2_primary_render.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb5/igt@kms_psr@psr2_primary_render.html
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-snb: NOTRUN -> [SKIP][113] ([fdo#109271]) +78 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-snb4/igt@kms_psr@psr2_sprite_plane_onoff.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-iclb: [PASS][114] -> [SKIP][115] ([i915#5519])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_writeback@writeback-check-output:
- shard-skl: NOTRUN -> [SKIP][116] ([fdo#109271] / [i915#2437])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl2/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-iclb: NOTRUN -> [SKIP][117] ([i915#2437])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb2/igt@kms_writeback@writeback-invalid-parameters.html
* igt@nouveau_crc@pipe-c-source-outp-complete:
- shard-iclb: NOTRUN -> [SKIP][118] ([i915#2530])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb5/igt@nouveau_crc@pipe-c-source-outp-complete.html
* igt@nouveau_crc@pipe-d-source-outp-inactive:
- shard-iclb: NOTRUN -> [SKIP][119] ([fdo#109278] / [i915#2530])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb5/igt@nouveau_crc@pipe-d-source-outp-inactive.html
* igt@prime_nv_test@nv_write_i915_gtt_mmap_read:
- shard-iclb: NOTRUN -> [SKIP][120] ([fdo#109291]) +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb2/igt@prime_nv_test@nv_write_i915_gtt_mmap_read.html
* igt@sw_sync@sync_merge_same:
- shard-skl: NOTRUN -> [FAIL][121] ([i915#6140]) +1 similar issue
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl9/igt@sw_sync@sync_merge_same.html
* igt@sysfs_clients@create:
- shard-iclb: NOTRUN -> [SKIP][122] ([i915#2994])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb2/igt@sysfs_clients@create.html
* igt@sysfs_clients@split-10:
- shard-skl: NOTRUN -> [SKIP][123] ([fdo#109271] / [i915#2994]) +2 similar issues
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl9/igt@sysfs_clients@split-10.html
* igt@sysfs_clients@split-50:
- shard-glk: NOTRUN -> [SKIP][124] ([fdo#109271] / [i915#2994])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-glk7/igt@sysfs_clients@split-50.html
#### Possible fixes ####
* igt@core_setmaster@master-drop-set-user:
- shard-iclb: [INCOMPLETE][125] -> [PASS][126] +1 similar issue
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb4/igt@core_setmaster@master-drop-set-user.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb2/igt@core_setmaster@master-drop-set-user.html
* igt@drm_fdinfo@basics:
- {shard-dg1}: [SKIP][127] ([i915#5563]) -> [PASS][128] +1 similar issue
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-dg1-16/igt@drm_fdinfo@basics.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-dg1-19/igt@drm_fdinfo@basics.html
* igt@gem_eio@kms:
- shard-tglb: [FAIL][129] ([i915#5784]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-tglb1/igt@gem_eio@kms.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-tglb6/igt@gem_eio@kms.html
* igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-iclb: [SKIP][131] ([i915#4525]) -> [PASS][132] +2 similar issues
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb6/igt@gem_exec_balancer@parallel-keep-submit-fence.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb2/igt@gem_exec_balancer@parallel-keep-submit-fence.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [FAIL][133] ([i915#2842]) -> [PASS][134]
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-tglb7/igt@gem_exec_fair@basic-none-share@rcs0.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-tglb5/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl: [FAIL][135] ([i915#2842]) -> [PASS][136]
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-kbl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-kbl4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk: [FAIL][137] ([i915#2842]) -> [PASS][138]
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-glk5/igt@gem_exec_fair@basic-pace@rcs0.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-glk2/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][139] ([i915#2849]) -> [PASS][140]
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb4/igt@gem_exec_fair@basic-throttle@rcs0.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_workarounds@suspend-resume:
- shard-apl: [DMESG-WARN][141] ([i915#180]) -> [PASS][142] +2 similar issues
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-apl6/igt@gem_workarounds@suspend-resume.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-apl4/igt@gem_workarounds@suspend-resume.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [DMESG-WARN][143] ([i915#5566] / [i915#716]) -> [PASS][144]
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-glk7/igt@gen9_exec_parse@allowed-all.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-glk7/igt@gen9_exec_parse@allowed-all.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-snb: [DMESG-WARN][145] ([i915#6201]) -> [PASS][146]
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-snb7/igt@i915_module_load@reload-with-fault-injection.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-snb4/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][147] ([i915#454]) -> [PASS][148]
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- {shard-tglu}: [FAIL][149] ([i915#3825]) -> [PASS][150]
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-tglu-5/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-tglu-1/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- {shard-dg1}: [SKIP][151] ([i915#1397]) -> [PASS][152]
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-dg1-18/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-dg1-12/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
* igt@i915_pm_rps@basic-api:
- {shard-dg1}: [FAIL][153] ([i915#4032]) -> [PASS][154]
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-dg1-17/igt@i915_pm_rps@basic-api.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-dg1-13/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@hangcheck:
- {shard-dg1}: [DMESG-FAIL][155] ([i915#4494] / [i915#4957]) -> [PASS][156]
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-dg1-17/igt@i915_selftest@live@hangcheck.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-dg1-13/igt@i915_selftest@live@hangcheck.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-tglb: [FAIL][157] ([i915#3743]) -> [PASS][158]
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-tglb2/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-tglb1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [FAIL][159] ([i915#2346] / [i915#533]) -> [PASS][160]
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank@a-dp1:
- shard-kbl: [FAIL][161] ([i915#79]) -> [PASS][162]
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-kbl7/igt@kms_flip@flip-vs-expired-vblank@a-dp1.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-kbl4/igt@kms_flip@flip-vs-expired-vblank@a-dp1.html
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2:
- shard-glk: [FAIL][163] ([i915#79]) -> [PASS][164]
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-glk4/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
- shard-iclb: [SKIP][165] ([i915#3701]) -> [PASS][166]
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-iclb: [SKIP][167] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [PASS][168]
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb6/igt@kms_psr2_su@frontbuffer-xrgb8888.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][169] ([fdo#109441]) -> [PASS][170] +1 similar issue
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@perf_pmu@busy-double-start@rcs0:
- {shard-dg1}: [FAIL][171] ([i915#4349]) -> [PASS][172]
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-dg1-12/igt@perf_pmu@busy-double-start@rcs0.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-dg1-13/igt@perf_pmu@busy-double-start@rcs0.html
#### Warnings ####
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: [FAIL][173] ([i915#2852]) -> [FAIL][174] ([i915#2842])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][175] ([i915#658]) -> [SKIP][176] ([i915#588])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb6/igt@i915_pm_dc@dc3co-vpb-simulation.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-270:
- shard-skl: [SKIP][177] ([fdo#109271] / [i915#1888]) -> [SKIP][178] ([fdo#109271])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl2/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl1/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
* igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-skl: [SKIP][179] ([fdo#109271]) -> [SKIP][180] ([fdo#109271] / [i915#1888]) +1 similar issue
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl4/igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_mc_ccs.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-skl7/igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-iclb: [SKIP][181] ([i915#2920]) -> [SKIP][182] ([i915#658])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb5/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-iclb: [SKIP][183] ([fdo#111068] / [i915#658]) -> [SKIP][184] ([i915#2920])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb4/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2852]: https://gitlab.freedesktop.org/drm/intel/issues/2852
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3614]: https://gitlab.freedesktop.org/drm/intel/issues/3614
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4032]: https://gitlab.freedesktop.org/drm/intel/issues/4032
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
[i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4911]: https://gitlab.freedesktop.org/drm/intel/issues/4911
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5032]: https://gitlab.freedesktop.org/drm/intel/issues/5032
[i915#5174]: https://gitlab.freedesktop.org/drm/intel/issues/5174
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5266]: https://gitlab.freedesktop.org/drm/intel/issues/5266
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
[i915#5721]: https://gitlab.freedesktop.org/drm/intel/issues/5721
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#5923]: https://gitlab.freedesktop.org/drm/intel/issues/5923
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6140]: https://gitlab.freedesktop.org/drm/intel/issues/6140
[i915#6201]: https://gitlab.freedesktop.org/drm/intel/issues/6201
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_11755 -> Patchwork_105085v1
CI-20190529: 20190529
CI_DRM_11755: 65b93b94d6bc932ed60bb3fd9d68242db25b1f3b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6522: 5be5a1a1f168a59614101b77385f05f12ec7d30a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_105085v1: 65b93b94d6bc932ed60bb3fd9d68242db25b1f3b @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105085v1/index.html
[-- Attachment #2: Type: text/html, Size: 48886 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] i915/pmu: Wire GuC backend to per-client busyness
2022-06-14 16:32 ` Umesh Nerlige Ramappa
@ 2022-06-15 7:08 ` Tvrtko Ursulin
2022-06-15 17:42 ` Umesh Nerlige Ramappa
0 siblings, 1 reply; 10+ messages in thread
From: Tvrtko Ursulin @ 2022-06-15 7:08 UTC (permalink / raw)
To: Umesh Nerlige Ramappa; +Cc: intel-gfx
On 14/06/2022 17:32, Umesh Nerlige Ramappa wrote:
> On Tue, Jun 14, 2022 at 02:30:42PM +0100, Tvrtko Ursulin wrote:
>>
>> On 14/06/2022 01:46, Nerlige Ramappa, Umesh wrote:
>>> From: John Harrison <John.C.Harrison@Intel.com>
>>>
>>> GuC provides engine_id and last_switch_in ticks for an active context
>>> in the
>>> pphwsp. The context image provides a 32 bit total ticks which is the
>>> accumulated
>>> by the context (a.k.a. context[CTX_TIMESTAMP]). This information is
>>> used to
>>> calculate the context busyness as follows:
>>>
>>> If the engine_id is valid, then busyness is the sum of accumulated
>>> total ticks
>>> and active ticks. Active ticks is calculated with current gt time as
>>> reference.
>>>
>>> If engine_id is invalid, busyness is equal to accumulated total ticks.
>>>
>>> Since KMD (CPU) retrieves busyness data from 2 sources - GPU and GuC, a
>>> potential race was highlighted in an earlier review that can lead to
>>> double
>>> accounting of busyness. While the solution to this is a wip, busyness
>>> is still
>>> usable for platforms running GuC submission.
>>>
>>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>>> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/gt/intel_context.c | 11 +++-
>>> drivers/gpu/drm/i915/gt/intel_context.h | 6 +-
>>> drivers/gpu/drm/i915/gt/intel_context_types.h | 3 +
>>> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 5 ++
>>> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 55 ++++++++++++++++++-
>>> drivers/gpu/drm/i915/i915_drm_client.c | 6 +-
>>> 6 files changed, 75 insertions(+), 11 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
>>> b/drivers/gpu/drm/i915/gt/intel_context.c
>>> index 4070cb5711d8..a49f313db911 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_context.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_context.c
>>> @@ -576,16 +576,23 @@ void intel_context_bind_parent_child(struct
>>> intel_context *parent,
>>> child->parallel.parent = parent;
>>> }
>>> -u64 intel_context_get_total_runtime_ns(const struct intel_context *ce)
>>> +u64 intel_context_get_total_runtime_ns(struct intel_context *ce)
>>> {
>>> u64 total, active;
>>> + if (ce->ops->update_stats)
>>> + ce->ops->update_stats(ce);
>>> +
>>> total = ce->stats.runtime.total;
>>> if (ce->ops->flags & COPS_RUNTIME_CYCLES)
>>> total *= ce->engine->gt->clock_period_ns;
>>> active = READ_ONCE(ce->stats.active);
>>> - if (active)
>>> + /*
>>> + * GuC backend returns the actual time the context was active,
>>> so skip
>>> + * the calculation here for GuC.
>>> + */
>>> + if (active && !intel_engine_uses_guc(ce->engine))
>>
>> What is the point of looking at ce->stats.active in GuC mode? I see
>> that guc_context_update_stats/__guc_context_update_clks touches it,
>> but I can't spot that there is a purpose to it. This is the only
>> conditional reading it but it is short-circuited in GuC case.
>>
>> Also, since a GuC only vfunc (update_stats) has been added, I wonder
>> why not just fork the whole runtime query (ce->get_total_runtime_ns).
>> I think that would end up cleaner.
>>
>>> active = intel_context_clock() - active;
>>> return total + active;
>
> In case of GuC the active is used directly here since the active updated
> in update_stats is equal to the active time of the context already. I
> will look into separate vfunc.
Ah right, I misread something. But yes, I think a separate vfunc will
look cleaner. Another option (instead of vfunc) is a similar flag to
control the express the flavour of active?
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
>>> b/drivers/gpu/drm/i915/gt/intel_context.h
>>> index b7d3214d2cdd..5fc7c19ab29b 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_context.h
>>> +++ b/drivers/gpu/drm/i915/gt/intel_context.h
>>> @@ -56,7 +56,7 @@ static inline bool intel_context_is_parent(struct
>>> intel_context *ce)
>>> return !!ce->parallel.number_children;
>>> }
>
> snip
>
>>> +static void __guc_context_update_clks(struct intel_context *ce)
>>> +{
>>> + struct intel_guc *guc = ce_to_guc(ce);
>>> + struct intel_gt *gt = ce->engine->gt;
>>> + u32 *pphwsp, last_switch, engine_id;
>>> + u64 start_gt_clk = 0, active = 0;
>>
>> No need to init these two.
>>
>>> + unsigned long flags;
>>> + ktime_t unused;
>>> +
>>> + spin_lock_irqsave(&guc->timestamp.lock, flags);
>>> +
>>> + pphwsp = ((void *)ce->lrc_reg_state) - LRC_STATE_OFFSET;
>>> + last_switch = READ_ONCE(pphwsp[PPHWSP_GUC_CONTEXT_USAGE_STAMP_LO]);
>>> + engine_id = READ_ONCE(pphwsp[PPHWSP_GUC_CONTEXT_USAGE_ENGINE_ID]);
>>> +
>>> + guc_update_pm_timestamp(guc, &unused);
>>> +
>>> + if (engine_id != 0xffffffff && last_switch) {
>>> + start_gt_clk = READ_ONCE(ce->stats.runtime.start_gt_clk);
>>> + __extend_last_switch(guc, &start_gt_clk, last_switch);
>>> + active = intel_gt_clock_interval_to_ns(gt,
>>> guc->timestamp.gt_stamp - start_gt_clk);
>>> + WRITE_ONCE(ce->stats.runtime.start_gt_clk, start_gt_clk);
>>> + WRITE_ONCE(ce->stats.active, active);
>>> + } else {
>>> + lrc_update_runtime(ce);
>>
>> Why is this called from here? Presumably it was called already from
>> guc_context_unpin if here code things context is not active. Or will
>> be called shortly, once context save is done.
>
> guc_context_unpin is only called in the path of ce->sched_disable. The
> sched_disable is implemented in GuC (H2G message). Once the
> corresponding G2H response is received, the context is actually
> unpinned, eventually calling guc_context_unpin. Also the context may not
> necessarily be disabled after each context exit.
So if I understand correctly, lrc runtime is only updated if someone is
reading the busyness and not as part of normal context state transitions?
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] i915/pmu: Wire GuC backend to per-client busyness
2022-06-15 7:08 ` Tvrtko Ursulin
@ 2022-06-15 17:42 ` Umesh Nerlige Ramappa
2022-08-25 6:18 ` Dixit, Ashutosh
0 siblings, 1 reply; 10+ messages in thread
From: Umesh Nerlige Ramappa @ 2022-06-15 17:42 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
On Wed, Jun 15, 2022 at 08:08:40AM +0100, Tvrtko Ursulin wrote:
>
>On 14/06/2022 17:32, Umesh Nerlige Ramappa wrote:
>>On Tue, Jun 14, 2022 at 02:30:42PM +0100, Tvrtko Ursulin wrote:
>>>
>>>On 14/06/2022 01:46, Nerlige Ramappa, Umesh wrote:
>>>>From: John Harrison <John.C.Harrison@Intel.com>
>>>>
>>>>GuC provides engine_id and last_switch_in ticks for an active
>>>>context in the
>>>>pphwsp. The context image provides a 32 bit total ticks which is
>>>>the accumulated
>>>>by the context (a.k.a. context[CTX_TIMESTAMP]). This information
>>>>is used to
>>>>calculate the context busyness as follows:
>>>>
>>>>If the engine_id is valid, then busyness is the sum of
>>>>accumulated total ticks
>>>>and active ticks. Active ticks is calculated with current gt
>>>>time as reference.
>>>>
>>>>If engine_id is invalid, busyness is equal to accumulated total ticks.
>>>>
>>>>Since KMD (CPU) retrieves busyness data from 2 sources - GPU and GuC, a
>>>>potential race was highlighted in an earlier review that can
>>>>lead to double
>>>>accounting of busyness. While the solution to this is a wip,
>>>>busyness is still
>>>>usable for platforms running GuC submission.
>>>>
>>>>Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>>>>Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>>>>---
>>>> drivers/gpu/drm/i915/gt/intel_context.c | 11 +++-
>>>> drivers/gpu/drm/i915/gt/intel_context.h | 6 +-
>>>> drivers/gpu/drm/i915/gt/intel_context_types.h | 3 +
>>>> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 5 ++
>>>> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 55 ++++++++++++++++++-
>>>> drivers/gpu/drm/i915/i915_drm_client.c | 6 +-
>>>> 6 files changed, 75 insertions(+), 11 deletions(-)
>>>>
>>>>diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
>>>>b/drivers/gpu/drm/i915/gt/intel_context.c
>>>>index 4070cb5711d8..a49f313db911 100644
>>>>--- a/drivers/gpu/drm/i915/gt/intel_context.c
>>>>+++ b/drivers/gpu/drm/i915/gt/intel_context.c
>>>>@@ -576,16 +576,23 @@ void
>>>>intel_context_bind_parent_child(struct intel_context *parent,
>>>> child->parallel.parent = parent;
>>>> }
>>>>-u64 intel_context_get_total_runtime_ns(const struct intel_context *ce)
>>>>+u64 intel_context_get_total_runtime_ns(struct intel_context *ce)
>>>> {
>>>> u64 total, active;
>>>>+ if (ce->ops->update_stats)
>>>>+ ce->ops->update_stats(ce);
>>>>+
>>>> total = ce->stats.runtime.total;
>>>> if (ce->ops->flags & COPS_RUNTIME_CYCLES)
>>>> total *= ce->engine->gt->clock_period_ns;
>>>> active = READ_ONCE(ce->stats.active);
>>>>- if (active)
>>>>+ /*
>>>>+ * GuC backend returns the actual time the context was
>>>>active, so skip
>>>>+ * the calculation here for GuC.
>>>>+ */
>>>>+ if (active && !intel_engine_uses_guc(ce->engine))
>>>
>>>What is the point of looking at ce->stats.active in GuC mode? I
>>>see that guc_context_update_stats/__guc_context_update_clks
>>>touches it, but I can't spot that there is a purpose to it. This
>>>is the only conditional reading it but it is short-circuited in
>>>GuC case.
>>>
>>>Also, since a GuC only vfunc (update_stats) has been added, I
>>>wonder why not just fork the whole runtime query
>>>(ce->get_total_runtime_ns). I think that would end up cleaner.
>>>
>>>> active = intel_context_clock() - active;
>>>> return total + active;
>>
>>In case of GuC the active is used directly here since the active
>>updated in update_stats is equal to the active time of the context
>>already. I will look into separate vfunc.
>
>Ah right, I misread something. But yes, I think a separate vfunc will
>look cleaner. Another option (instead of vfunc) is a similar flag to
>control the express the flavour of active?
Flag does sound simpler. The guc context ops can have something like
COPS_RUNTIME_ACTIVE_TOTAL that means total active time.
>
>>>>diff --git a/drivers/gpu/drm/i915/gt/intel_context.h
>>>>b/drivers/gpu/drm/i915/gt/intel_context.h
>>>>index b7d3214d2cdd..5fc7c19ab29b 100644
>>>>--- a/drivers/gpu/drm/i915/gt/intel_context.h
>>>>+++ b/drivers/gpu/drm/i915/gt/intel_context.h
>>>>@@ -56,7 +56,7 @@ static inline bool
>>>>intel_context_is_parent(struct intel_context *ce)
>>>> return !!ce->parallel.number_children;
>>>> }
>>
>>snip
>>
>>>>+static void __guc_context_update_clks(struct intel_context *ce)
>>>>+{
>>>>+ struct intel_guc *guc = ce_to_guc(ce);
>>>>+ struct intel_gt *gt = ce->engine->gt;
>>>>+ u32 *pphwsp, last_switch, engine_id;
>>>>+ u64 start_gt_clk = 0, active = 0;
>>>
>>>No need to init these two.
>>>
>>>>+ unsigned long flags;
>>>>+ ktime_t unused;
>>>>+
>>>>+ spin_lock_irqsave(&guc->timestamp.lock, flags);
>>>>+
>>>>+ pphwsp = ((void *)ce->lrc_reg_state) - LRC_STATE_OFFSET;
>>>>+ last_switch = READ_ONCE(pphwsp[PPHWSP_GUC_CONTEXT_USAGE_STAMP_LO]);
>>>>+ engine_id = READ_ONCE(pphwsp[PPHWSP_GUC_CONTEXT_USAGE_ENGINE_ID]);
>>>>+
>>>>+ guc_update_pm_timestamp(guc, &unused);
>>>>+
>>>>+ if (engine_id != 0xffffffff && last_switch) {
>>>>+ start_gt_clk = READ_ONCE(ce->stats.runtime.start_gt_clk);
>>>>+ __extend_last_switch(guc, &start_gt_clk, last_switch);
>>>>+ active = intel_gt_clock_interval_to_ns(gt,
>>>>guc->timestamp.gt_stamp - start_gt_clk);
>>>>+ WRITE_ONCE(ce->stats.runtime.start_gt_clk, start_gt_clk);
>>>>+ WRITE_ONCE(ce->stats.active, active);
>>>>+ } else {
>>>>+ lrc_update_runtime(ce);
>>>
>>>Why is this called from here? Presumably it was called already
>>>from guc_context_unpin if here code things context is not active.
>>>Or will be called shortly, once context save is done.
>>
>>guc_context_unpin is only called in the path of ce->sched_disable.
>>The sched_disable is implemented in GuC (H2G message). Once the
>>corresponding G2H response is received, the context is actually
>>unpinned, eventually calling guc_context_unpin. Also the context may
>>not necessarily be disabled after each context exit.
>
>So if I understand correctly, lrc runtime is only updated if someone
>is reading the busyness and not as part of normal context state
>transitions?
If you mean context_in/out events (like csb interrupts), only GuC can
see those events. KMD has no visibility into that. These 3 paths call
lrc_update_runtime.
user query: (engine_id != 0xffffffff && last_switch) translates to GuC
being within context_in and context_out events, so updating it outside
of this window is one way to report the correct busyness.
worker: guc_timestamp_ping() also updates context stats (infrequently)
for all contexts primarily to take care of overflows.
context unpin: Existing code calls lrc_update_runtime only when
unpinning the context which takes care of accumulating busyness when
requests are retired.
Thanks,
Umesh
>
>Regards,
>
>Tvrtko
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] i915/pmu: Wire GuC backend to per-client busyness
2022-06-15 17:42 ` Umesh Nerlige Ramappa
@ 2022-08-25 6:18 ` Dixit, Ashutosh
0 siblings, 0 replies; 10+ messages in thread
From: Dixit, Ashutosh @ 2022-08-25 6:18 UTC (permalink / raw)
To: Umesh Nerlige Ramappa; +Cc: intel-gfx
On Wed, 15 Jun 2022 10:42:08 -0700, Umesh Nerlige Ramappa wrote:
>
> >>>> +static void __guc_context_update_clks(struct intel_context *ce)
> >>>> +{
> >>>> + struct intel_guc *guc = ce_to_guc(ce);
> >>>> + struct intel_gt *gt = ce->engine->gt;
> >>>> + u32 *pphwsp, last_switch, engine_id;
> >>>> + u64 start_gt_clk = 0, active = 0;
> >>>
> >>> No need to init these two.
> >>>
> >>>> + unsigned long flags;
> >>>> + ktime_t unused;
> >>>> +
> >>>> + spin_lock_irqsave(&guc->timestamp.lock, flags);
> >>>> +
> >>>> + pphwsp = ((void *)ce->lrc_reg_state) - LRC_STATE_OFFSET;
> >>>> + last_switch = READ_ONCE(pphwsp[PPHWSP_GUC_CONTEXT_USAGE_STAMP_LO]);
> >>>> + engine_id = READ_ONCE(pphwsp[PPHWSP_GUC_CONTEXT_USAGE_ENGINE_ID]);
> >>>> +
> >>>> + guc_update_pm_timestamp(guc, &unused);
> >>>> +
> >>>> + if (engine_id != 0xffffffff && last_switch) {
> >>>> + start_gt_clk = READ_ONCE(ce->stats.runtime.start_gt_clk);
> >>>> + __extend_last_switch(guc, &start_gt_clk, last_switch);
> >>>> + active = intel_gt_clock_interval_to_ns(gt,
> >>>> guc->timestamp.gt_stamp - start_gt_clk);
> >>>> + WRITE_ONCE(ce->stats.runtime.start_gt_clk, start_gt_clk);
> >>>> + WRITE_ONCE(ce->stats.active, active);
> >>>> + } else {
> >>>> + lrc_update_runtime(ce);
> >>>
> >>> Why is this called from here? Presumably it was called already from
> >>> guc_context_unpin if here code things context is not active. Or will be
> >>> called shortly, once context save is done.
> >>
> >> guc_context_unpin is only called in the path of ce->sched_disable. The
> >> sched_disable is implemented in GuC (H2G message). Once the
> >> corresponding G2H response is received, the context is actually
> >> unpinned, eventually calling guc_context_unpin. Also the context may not
> >> necessarily be disabled after each context exit.
> >
> > So if I understand correctly, lrc runtime is only updated if someone is
> > reading the busyness and not as part of normal context state transitions?
>
> If you mean context_in/out events (like csb interrupts), only GuC can see
> those events. KMD has no visibility into that. These 3 paths call
> lrc_update_runtime.
>
> user query: (engine_id != 0xffffffff && last_switch) translates to GuC
> being within context_in and context_out events, so updating it outside of
> this window is one way to report the correct busyness.
>
> worker: guc_timestamp_ping() also updates context stats (infrequently) for
> all contexts primarily to take care of overflows.
>
> context unpin: Existing code calls lrc_update_runtime only when unpinning
> the context which takes care of accumulating busyness when requests are
> retired.
Will adding lrc_update_runtime() to lrc_unpin() work?
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2022-08-25 7:21 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-14 0:46 [Intel-gfx] [PATCH] i915/pmu: Wire GuC backend to per-client busyness Nerlige Ramappa, Umesh
2022-06-14 2:23 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2022-06-14 2:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-06-14 2:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-06-14 13:30 ` [Intel-gfx] [PATCH] " Tvrtko Ursulin
2022-06-14 16:32 ` Umesh Nerlige Ramappa
2022-06-15 7:08 ` Tvrtko Ursulin
2022-06-15 17:42 ` Umesh Nerlige Ramappa
2022-08-25 6:18 ` Dixit, Ashutosh
2022-06-15 0:29 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.