* [PATCH v2 2/3] drm/msm/dpu: fix maxlinewidth for writeback block
2022-06-15 21:22 [PATCH v2 1/3] drm/msm/dpu: move intf and wb assignment to dpu_encoder_setup_display() Abhinav Kumar
@ 2022-06-15 21:22 ` Abhinav Kumar
2022-06-15 21:22 ` [PATCH v2 3/3] drm/msm/dpu: remove hard-coded linewidth limit for writeback Abhinav Kumar
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Abhinav Kumar @ 2022-06-15 21:22 UTC (permalink / raw)
To: freedreno
Cc: markyacoub, Abhinav Kumar, dri-devel, swboyd, seanpaul,
dmitry.baryshkov, quic_jesszhan, quic_aravindh
Writeback block for sm8250 was using the default maxlinewidth
of 2048. But this is not right as it supports upto 4096.
This should have no effect on most resolutions as we are
still limiting upto maxlinewidth of SSPP for adding the modes.
Fix the maxlinewidth for writeback block on sm8250.
Fixes: 53324b99bd7b ("add writeback blocks to the sm8250 DPU catalog")
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 400ebceb56bb..dd7537e32f88 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -1285,7 +1285,7 @@ static const struct dpu_intf_cfg qcm2290_intf[] = {
* Writeback blocks config
*************************************************************/
#define WB_BLK(_name, _id, _base, _features, _clk_ctrl, \
- __xin_id, vbif_id, _reg, _wb_done_bit) \
+ __xin_id, vbif_id, _reg, _max_linewidth, _wb_done_bit) \
{ \
.name = _name, .id = _id, \
.base = _base, .len = 0x2c8, \
@@ -1295,13 +1295,13 @@ static const struct dpu_intf_cfg qcm2290_intf[] = {
.clk_ctrl = _clk_ctrl, \
.xin_id = __xin_id, \
.vbif_idx = vbif_id, \
- .maxlinewidth = DEFAULT_DPU_LINE_WIDTH, \
+ .maxlinewidth = _max_linewidth, \
.intr_wb_done = DPU_IRQ_IDX(_reg, _wb_done_bit) \
}
static const struct dpu_wb_cfg sm8250_wb[] = {
WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6,
- VBIF_RT, MDP_SSPP_TOP0_INTR, 4),
+ VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4),
};
/*************************************************************
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v2 3/3] drm/msm/dpu: remove hard-coded linewidth limit for writeback
2022-06-15 21:22 [PATCH v2 1/3] drm/msm/dpu: move intf and wb assignment to dpu_encoder_setup_display() Abhinav Kumar
2022-06-15 21:22 ` [PATCH v2 2/3] drm/msm/dpu: fix maxlinewidth for writeback block Abhinav Kumar
@ 2022-06-15 21:22 ` Abhinav Kumar
2022-06-15 21:59 ` [PATCH v2 1/3] drm/msm/dpu: move intf and wb assignment to dpu_encoder_setup_display() Dmitry Baryshkov
2022-06-16 8:36 ` Dmitry Baryshkov
3 siblings, 0 replies; 5+ messages in thread
From: Abhinav Kumar @ 2022-06-15 21:22 UTC (permalink / raw)
To: freedreno
Cc: markyacoub, Abhinav Kumar, dri-devel, swboyd, seanpaul,
dmitry.baryshkov, quic_jesszhan, quic_aravindh
Remove the hard-coded limit for writeback and lets start using
the one from catalog instead.
Fixes: d7d0e73f7de3 ("introduce the dpu_encoder_phys_* for writeback")
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 59da348ff339..fc1d4fda69b5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -20,8 +20,6 @@
#include "dpu_crtc.h"
#include "disp/msm_disp_snapshot.h"
-#define DEFAULT_MAX_WRITEBACK_WIDTH 2048
-
#define to_dpu_encoder_phys_wb(x) \
container_of(x, struct dpu_encoder_phys_wb, base)
@@ -278,9 +276,9 @@ static int dpu_encoder_phys_wb_atomic_check(
DPU_ERROR("invalid fb h=%d, mode h=%d\n", fb->height,
mode->vdisplay);
return -EINVAL;
- } else if (fb->width > DEFAULT_MAX_WRITEBACK_WIDTH) {
+ } else if (fb->width > phys_enc->hw_wb->caps->maxlinewidth) {
DPU_ERROR("invalid fb w=%d, maxlinewidth=%u\n",
- fb->width, DEFAULT_MAX_WRITEBACK_WIDTH);
+ fb->width, phys_enc->hw_wb->caps->maxlinewidth);
return -EINVAL;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH v2 1/3] drm/msm/dpu: move intf and wb assignment to dpu_encoder_setup_display()
2022-06-15 21:22 [PATCH v2 1/3] drm/msm/dpu: move intf and wb assignment to dpu_encoder_setup_display() Abhinav Kumar
2022-06-15 21:22 ` [PATCH v2 2/3] drm/msm/dpu: fix maxlinewidth for writeback block Abhinav Kumar
2022-06-15 21:22 ` [PATCH v2 3/3] drm/msm/dpu: remove hard-coded linewidth limit for writeback Abhinav Kumar
@ 2022-06-15 21:59 ` Dmitry Baryshkov
2022-06-16 8:36 ` Dmitry Baryshkov
3 siblings, 0 replies; 5+ messages in thread
From: Dmitry Baryshkov @ 2022-06-15 21:59 UTC (permalink / raw)
To: Abhinav Kumar
Cc: markyacoub, dri-devel, swboyd, seanpaul, quic_jesszhan,
quic_aravindh, freedreno
On Thu, 16 Jun 2022 at 00:22, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>
> intf and wb resources are not dependent on the rm global
> state so need not be allocated during dpu_encoder_virt_atomic_mode_set().
>
> Move the allocation of intf and wb resources to dpu_encoder_setup_display()
> so that we can utilize the hw caps even during atomic_check() phase.
>
> Since dpu_encoder_setup_display() already has protection against
> setting invalid intf_idx and wb_idx, these checks can now
> be dropped as well.
>
> changes in v2:
> - add phys->hw_intf and phys->hw_wb checks back
>
> Fixes: e02a559a720f ("make changes to dpu_encoder to support virtual encoder")
> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 36 ++++++++++++++---------------
> 1 file changed, 18 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 3a462e327e0e..3be73211d631 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -1048,24 +1048,6 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
> phys->hw_pp = dpu_enc->hw_pp[i];
> phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);
>
> - if (phys->intf_idx >= INTF_0 && phys->intf_idx < INTF_MAX)
> - phys->hw_intf = dpu_rm_get_intf(&dpu_kms->rm, phys->intf_idx);
> -
> - if (phys->wb_idx >= WB_0 && phys->wb_idx < WB_MAX)
> - phys->hw_wb = dpu_rm_get_wb(&dpu_kms->rm, phys->wb_idx);
> -
> - if (!phys->hw_intf && !phys->hw_wb) {
> - DPU_ERROR_ENC(dpu_enc,
> - "no intf or wb block assigned at idx: %d\n", i);
> - return;
> - }
> -
> - if (phys->hw_intf && phys->hw_wb) {
> - DPU_ERROR_ENC(dpu_enc,
> - "invalid phys both intf and wb block at idx: %d\n", i);
> - return;
> - }
> -
> phys->cached_mode = crtc_state->adjusted_mode;
> if (phys->ops.atomic_mode_set)
> phys->ops.atomic_mode_set(phys, crtc_state, conn_state);
> @@ -2293,7 +2275,25 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
> struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
> atomic_set(&phys->vsync_cnt, 0);
> atomic_set(&phys->underrun_cnt, 0);
> +
> + if (phys->intf_idx >= INTF_0 && phys->intf_idx < INTF_MAX)
> + phys->hw_intf = dpu_rm_get_intf(&dpu_kms->rm, phys->intf_idx);
> +
> + if (phys->wb_idx >= WB_0 && phys->wb_idx < WB_MAX)
> + phys->hw_wb = dpu_rm_get_wb(&dpu_kms->rm, phys->wb_idx);
> +
> + if (!phys->hw_intf && !phys->hw_wb) {
> + DPU_ERROR_ENC(dpu_enc, "no intf or wb block assigned at idx: %d\n", i);
> + ret = -EINVAL;
> + }
> +
> + if (phys->hw_intf && phys->hw_wb) {
> + DPU_ERROR_ENC(dpu_enc,
> + "invalid phys both intf and wb block at idx: %d\n", i);
> + ret = -EINVAL;
> + }
> }
> +
> mutex_unlock(&dpu_enc->enc_lock);
>
> return ret;
> --
> 2.7.4
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v2 1/3] drm/msm/dpu: move intf and wb assignment to dpu_encoder_setup_display()
2022-06-15 21:22 [PATCH v2 1/3] drm/msm/dpu: move intf and wb assignment to dpu_encoder_setup_display() Abhinav Kumar
` (2 preceding siblings ...)
2022-06-15 21:59 ` [PATCH v2 1/3] drm/msm/dpu: move intf and wb assignment to dpu_encoder_setup_display() Dmitry Baryshkov
@ 2022-06-16 8:36 ` Dmitry Baryshkov
3 siblings, 0 replies; 5+ messages in thread
From: Dmitry Baryshkov @ 2022-06-16 8:36 UTC (permalink / raw)
To: Abhinav Kumar, freedreno
Cc: markyacoub, dri-devel, swboyd, seanpaul, quic_jesszhan, quic_aravindh
On 16/06/2022 00:22, Abhinav Kumar wrote:
> intf and wb resources are not dependent on the rm global
> state so need not be allocated during dpu_encoder_virt_atomic_mode_set().
>
> Move the allocation of intf and wb resources to dpu_encoder_setup_display()
> so that we can utilize the hw caps even during atomic_check() phase.
>
> Since dpu_encoder_setup_display() already has protection against
> setting invalid intf_idx and wb_idx, these checks can now
> be dropped as well.
>
> changes in v2:
> - add phys->hw_intf and phys->hw_wb checks back
>
> Fixes: e02a559a720f ("make changes to dpu_encoder to support virtual encoder")
Reviewed: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 36 ++++++++++++++---------------
> 1 file changed, 18 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 3a462e327e0e..3be73211d631 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -1048,24 +1048,6 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
> phys->hw_pp = dpu_enc->hw_pp[i];
> phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);
>
> - if (phys->intf_idx >= INTF_0 && phys->intf_idx < INTF_MAX)
> - phys->hw_intf = dpu_rm_get_intf(&dpu_kms->rm, phys->intf_idx);
> -
> - if (phys->wb_idx >= WB_0 && phys->wb_idx < WB_MAX)
> - phys->hw_wb = dpu_rm_get_wb(&dpu_kms->rm, phys->wb_idx);
> -
> - if (!phys->hw_intf && !phys->hw_wb) {
> - DPU_ERROR_ENC(dpu_enc,
> - "no intf or wb block assigned at idx: %d\n", i);
> - return;
> - }
> -
> - if (phys->hw_intf && phys->hw_wb) {
> - DPU_ERROR_ENC(dpu_enc,
> - "invalid phys both intf and wb block at idx: %d\n", i);
> - return;
> - }
> -
> phys->cached_mode = crtc_state->adjusted_mode;
> if (phys->ops.atomic_mode_set)
> phys->ops.atomic_mode_set(phys, crtc_state, conn_state);
> @@ -2293,7 +2275,25 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
> struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
> atomic_set(&phys->vsync_cnt, 0);
> atomic_set(&phys->underrun_cnt, 0);
> +
> + if (phys->intf_idx >= INTF_0 && phys->intf_idx < INTF_MAX)
> + phys->hw_intf = dpu_rm_get_intf(&dpu_kms->rm, phys->intf_idx);
> +
> + if (phys->wb_idx >= WB_0 && phys->wb_idx < WB_MAX)
> + phys->hw_wb = dpu_rm_get_wb(&dpu_kms->rm, phys->wb_idx);
> +
> + if (!phys->hw_intf && !phys->hw_wb) {
> + DPU_ERROR_ENC(dpu_enc, "no intf or wb block assigned at idx: %d\n", i);
> + ret = -EINVAL;
> + }
> +
> + if (phys->hw_intf && phys->hw_wb) {
> + DPU_ERROR_ENC(dpu_enc,
> + "invalid phys both intf and wb block at idx: %d\n", i);
> + ret = -EINVAL;
> + }
> }
> +
> mutex_unlock(&dpu_enc->enc_lock);
>
> return ret;
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 5+ messages in thread