* [PATCH 0/5] Bring up internal eMMC on Samsung Galaxy A8 (2018) @ 2022-06-01 23:37 ` David Virag 0 siblings, 0 replies; 38+ messages in thread From: David Virag @ 2022-06-01 23:37 UTC (permalink / raw) Cc: phone-devel, David Virag, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel This set adds support to the internal eMMC storage found on the Samsung Galaxy A8 (2018) (jackpotlte). It seems to work reliably for reads and writes. postmarketOS is able to boot off of it. The original kernel from samsung sets pinctrl options at runtime changing pin-drv levels automatically. Without this code, mmc seems to work the best with the lv3 setting on jackpotlte. David Virag (5): dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS dt-bindings: clock: Add indices for Exynos7885 TREX clocks clk: samsung: exynos7885: Implement CMU_FSYS domain clk: samsung: exynos7885: Add TREX clocks arm64: dts: exynos: Add internal eMMC support to jackpotlte .../clock/samsung,exynos7885-clock.yaml | 27 +++ .../boot/dts/exynos/exynos7885-jackpotlte.dts | 20 ++ arch/arm64/boot/dts/exynos/exynos7885.dtsi | 32 +++ drivers/clk/samsung/clk-exynos7885.c | 207 +++++++++++++++++- include/dt-bindings/clock/exynos7885.h | 54 ++++- 5 files changed, 324 insertions(+), 16 deletions(-) -- 2.36.1 ^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 0/5] Bring up internal eMMC on Samsung Galaxy A8 (2018) @ 2022-06-01 23:37 ` David Virag 0 siblings, 0 replies; 38+ messages in thread From: David Virag @ 2022-06-01 23:37 UTC (permalink / raw) Cc: phone-devel, David Virag, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel This set adds support to the internal eMMC storage found on the Samsung Galaxy A8 (2018) (jackpotlte). It seems to work reliably for reads and writes. postmarketOS is able to boot off of it. The original kernel from samsung sets pinctrl options at runtime changing pin-drv levels automatically. Without this code, mmc seems to work the best with the lv3 setting on jackpotlte. David Virag (5): dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS dt-bindings: clock: Add indices for Exynos7885 TREX clocks clk: samsung: exynos7885: Implement CMU_FSYS domain clk: samsung: exynos7885: Add TREX clocks arm64: dts: exynos: Add internal eMMC support to jackpotlte .../clock/samsung,exynos7885-clock.yaml | 27 +++ .../boot/dts/exynos/exynos7885-jackpotlte.dts | 20 ++ arch/arm64/boot/dts/exynos/exynos7885.dtsi | 32 +++ drivers/clk/samsung/clk-exynos7885.c | 207 +++++++++++++++++- include/dt-bindings/clock/exynos7885.h | 54 ++++- 5 files changed, 324 insertions(+), 16 deletions(-) -- 2.36.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 1/5] dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS 2022-06-01 23:37 ` David Virag @ 2022-06-01 23:37 ` David Virag -1 siblings, 0 replies; 38+ messages in thread From: David Virag @ 2022-06-01 23:37 UTC (permalink / raw) Cc: phone-devel, David Virag, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel CMU_FSYS clock domain provides clocks for MMC (MMC_CARD, MMC_EMBD, MMC_SDIO), and USB30DRD. Add clock indices and bindings documentation for CMU_FSYS domain. Signed-off-by: David Virag <virag.david003@gmail.com> --- .../clock/samsung,exynos7885-clock.yaml | 27 ++++++++++++++++ include/dt-bindings/clock/exynos7885.h | 31 ++++++++++++++++++- 2 files changed, 57 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml index 5073e569a47f..006d33a9e0f1 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml @@ -33,6 +33,7 @@ properties: enum: - samsung,exynos7885-cmu-top - samsung,exynos7885-cmu-core + - samsung,exynos7885-cmu-fsys - samsung,exynos7885-cmu-peri clocks: @@ -88,6 +89,32 @@ allOf: - const: dout_core_cci - const: dout_core_g3d + - if: + properties: + compatible: + contains: + const: samsung,exynos7885-cmu-fsys + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_FSYS bus clock (from CMU_TOP) + - description: MMC_CARD clock (from CMU_TOP) + - description: MMC_EMBD clock (from CMU_TOP) + - description: MMC_SDIO clock (from CMU_TOP) + - description: USB30DRD clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_fsys_bus + - const: dout_fsys_mmc_card + - const: dout_fsys_mmc_embd + - const: dout_fsys_mmc_sdio + - const: dout_fsys_usb30drd + - if: properties: compatible: diff --git a/include/dt-bindings/clock/exynos7885.h b/include/dt-bindings/clock/exynos7885.h index 1f8701691d62..d2e1483f93e4 100644 --- a/include/dt-bindings/clock/exynos7885.h +++ b/include/dt-bindings/clock/exynos7885.h @@ -54,7 +54,22 @@ #define CLK_GOUT_PERI_USI0 43 #define CLK_GOUT_PERI_USI1 44 #define CLK_GOUT_PERI_USI2 45 -#define TOP_NR_CLK 46 +#define CLK_MOUT_FSYS_BUS 46 +#define CLK_MOUT_FSYS_MMC_CARD 47 +#define CLK_MOUT_FSYS_MMC_EMBD 48 +#define CLK_MOUT_FSYS_MMC_SDIO 49 +#define CLK_MOUT_FSYS_USB30DRD 50 +#define CLK_DOUT_FSYS_BUS 51 +#define CLK_DOUT_FSYS_MMC_CARD 52 +#define CLK_DOUT_FSYS_MMC_EMBD 53 +#define CLK_DOUT_FSYS_MMC_SDIO 54 +#define CLK_DOUT_FSYS_USB30DRD 55 +#define CLK_GOUT_FSYS_BUS 56 +#define CLK_GOUT_FSYS_MMC_CARD 57 +#define CLK_GOUT_FSYS_MMC_EMBD 58 +#define CLK_GOUT_FSYS_MMC_SDIO 59 +#define CLK_GOUT_FSYS_USB30DRD 60 +#define TOP_NR_CLK 61 /* CMU_CORE */ #define CLK_MOUT_CORE_BUS_USER 1 @@ -112,4 +127,18 @@ #define CLK_GOUT_WDT1_PCLK 43 #define PERI_NR_CLK 44 +/* CMU_FSYS */ +#define CLK_MOUT_FSYS_BUS_USER 1 +#define CLK_MOUT_FSYS_MMC_CARD_USER 2 +#define CLK_MOUT_FSYS_MMC_EMBD_USER 3 +#define CLK_MOUT_FSYS_MMC_SDIO_USER 4 +#define CLK_MOUT_FSYS_USB30DRD_USER 4 +#define CLK_GOUT_MMC_CARD_ACLK 5 +#define CLK_GOUT_MMC_CARD_SDCLKIN 6 +#define CLK_GOUT_MMC_EMBD_ACLK 7 +#define CLK_GOUT_MMC_EMBD_SDCLKIN 8 +#define CLK_GOUT_MMC_SDIO_ACLK 9 +#define CLK_GOUT_MMC_SDIO_SDCLKIN 10 +#define FSYS_NR_CLK 11 + #endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */ -- 2.36.1 ^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 1/5] dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS @ 2022-06-01 23:37 ` David Virag 0 siblings, 0 replies; 38+ messages in thread From: David Virag @ 2022-06-01 23:37 UTC (permalink / raw) Cc: phone-devel, David Virag, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel CMU_FSYS clock domain provides clocks for MMC (MMC_CARD, MMC_EMBD, MMC_SDIO), and USB30DRD. Add clock indices and bindings documentation for CMU_FSYS domain. Signed-off-by: David Virag <virag.david003@gmail.com> --- .../clock/samsung,exynos7885-clock.yaml | 27 ++++++++++++++++ include/dt-bindings/clock/exynos7885.h | 31 ++++++++++++++++++- 2 files changed, 57 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml index 5073e569a47f..006d33a9e0f1 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml @@ -33,6 +33,7 @@ properties: enum: - samsung,exynos7885-cmu-top - samsung,exynos7885-cmu-core + - samsung,exynos7885-cmu-fsys - samsung,exynos7885-cmu-peri clocks: @@ -88,6 +89,32 @@ allOf: - const: dout_core_cci - const: dout_core_g3d + - if: + properties: + compatible: + contains: + const: samsung,exynos7885-cmu-fsys + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_FSYS bus clock (from CMU_TOP) + - description: MMC_CARD clock (from CMU_TOP) + - description: MMC_EMBD clock (from CMU_TOP) + - description: MMC_SDIO clock (from CMU_TOP) + - description: USB30DRD clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_fsys_bus + - const: dout_fsys_mmc_card + - const: dout_fsys_mmc_embd + - const: dout_fsys_mmc_sdio + - const: dout_fsys_usb30drd + - if: properties: compatible: diff --git a/include/dt-bindings/clock/exynos7885.h b/include/dt-bindings/clock/exynos7885.h index 1f8701691d62..d2e1483f93e4 100644 --- a/include/dt-bindings/clock/exynos7885.h +++ b/include/dt-bindings/clock/exynos7885.h @@ -54,7 +54,22 @@ #define CLK_GOUT_PERI_USI0 43 #define CLK_GOUT_PERI_USI1 44 #define CLK_GOUT_PERI_USI2 45 -#define TOP_NR_CLK 46 +#define CLK_MOUT_FSYS_BUS 46 +#define CLK_MOUT_FSYS_MMC_CARD 47 +#define CLK_MOUT_FSYS_MMC_EMBD 48 +#define CLK_MOUT_FSYS_MMC_SDIO 49 +#define CLK_MOUT_FSYS_USB30DRD 50 +#define CLK_DOUT_FSYS_BUS 51 +#define CLK_DOUT_FSYS_MMC_CARD 52 +#define CLK_DOUT_FSYS_MMC_EMBD 53 +#define CLK_DOUT_FSYS_MMC_SDIO 54 +#define CLK_DOUT_FSYS_USB30DRD 55 +#define CLK_GOUT_FSYS_BUS 56 +#define CLK_GOUT_FSYS_MMC_CARD 57 +#define CLK_GOUT_FSYS_MMC_EMBD 58 +#define CLK_GOUT_FSYS_MMC_SDIO 59 +#define CLK_GOUT_FSYS_USB30DRD 60 +#define TOP_NR_CLK 61 /* CMU_CORE */ #define CLK_MOUT_CORE_BUS_USER 1 @@ -112,4 +127,18 @@ #define CLK_GOUT_WDT1_PCLK 43 #define PERI_NR_CLK 44 +/* CMU_FSYS */ +#define CLK_MOUT_FSYS_BUS_USER 1 +#define CLK_MOUT_FSYS_MMC_CARD_USER 2 +#define CLK_MOUT_FSYS_MMC_EMBD_USER 3 +#define CLK_MOUT_FSYS_MMC_SDIO_USER 4 +#define CLK_MOUT_FSYS_USB30DRD_USER 4 +#define CLK_GOUT_MMC_CARD_ACLK 5 +#define CLK_GOUT_MMC_CARD_SDCLKIN 6 +#define CLK_GOUT_MMC_EMBD_ACLK 7 +#define CLK_GOUT_MMC_EMBD_SDCLKIN 8 +#define CLK_GOUT_MMC_SDIO_ACLK 9 +#define CLK_GOUT_MMC_SDIO_SDCLKIN 10 +#define FSYS_NR_CLK 11 + #endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */ -- 2.36.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH 1/5] dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS 2022-06-01 23:37 ` David Virag @ 2022-06-02 11:54 ` Krzysztof Kozlowski -1 siblings, 0 replies; 38+ messages in thread From: Krzysztof Kozlowski @ 2022-06-02 11:54 UTC (permalink / raw) To: David Virag Cc: phone-devel, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On 02/06/2022 01:37, David Virag wrote: > CMU_FSYS clock domain provides clocks for MMC (MMC_CARD, MMC_EMBD, > MMC_SDIO), and USB30DRD. > > Add clock indices and bindings documentation for CMU_FSYS domain. > > Signed-off-by: David Virag <virag.david003@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 1/5] dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS @ 2022-06-02 11:54 ` Krzysztof Kozlowski 0 siblings, 0 replies; 38+ messages in thread From: Krzysztof Kozlowski @ 2022-06-02 11:54 UTC (permalink / raw) To: David Virag Cc: phone-devel, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On 02/06/2022 01:37, David Virag wrote: > CMU_FSYS clock domain provides clocks for MMC (MMC_CARD, MMC_EMBD, > MMC_SDIO), and USB30DRD. > > Add clock indices and bindings documentation for CMU_FSYS domain. > > Signed-off-by: David Virag <virag.david003@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 1/5] dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS 2022-06-01 23:37 ` David Virag @ 2022-06-08 15:12 ` Krzysztof Kozlowski -1 siblings, 0 replies; 38+ messages in thread From: Krzysztof Kozlowski @ 2022-06-08 15:12 UTC (permalink / raw) To: Sylwester Nawrocki Cc: phone-devel, David Virag, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On 02/06/2022 01:37, David Virag wrote: > CMU_FSYS clock domain provides clocks for MMC (MMC_CARD, MMC_EMBD, > MMC_SDIO), and USB30DRD. > > Add clock indices and bindings documentation for CMU_FSYS domain. > > Signed-off-by: David Virag <virag.david003@gmail.com> > --- > .../clock/samsung,exynos7885-clock.yaml | 27 ++++++++++++++++ > include/dt-bindings/clock/exynos7885.h | 31 ++++++++++++++++++- It seems the clock IDs from bindings are used by both driver and DTS. Sylwester, can I take them to Samsung Soc and send you a pull request? Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 1/5] dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS @ 2022-06-08 15:12 ` Krzysztof Kozlowski 0 siblings, 0 replies; 38+ messages in thread From: Krzysztof Kozlowski @ 2022-06-08 15:12 UTC (permalink / raw) To: Sylwester Nawrocki Cc: phone-devel, David Virag, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On 02/06/2022 01:37, David Virag wrote: > CMU_FSYS clock domain provides clocks for MMC (MMC_CARD, MMC_EMBD, > MMC_SDIO), and USB30DRD. > > Add clock indices and bindings documentation for CMU_FSYS domain. > > Signed-off-by: David Virag <virag.david003@gmail.com> > --- > .../clock/samsung,exynos7885-clock.yaml | 27 ++++++++++++++++ > include/dt-bindings/clock/exynos7885.h | 31 ++++++++++++++++++- It seems the clock IDs from bindings are used by both driver and DTS. Sylwester, can I take them to Samsung Soc and send you a pull request? Best regards, Krzysztof ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 1/5] dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS 2022-06-08 15:12 ` Krzysztof Kozlowski @ 2022-06-20 10:31 ` Sylwester Nawrocki -1 siblings, 0 replies; 38+ messages in thread From: Sylwester Nawrocki @ 2022-06-20 10:31 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: phone-devel, David Virag, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On 08.06.2022 17:12, Krzysztof Kozlowski wrote: > On 02/06/2022 01:37, David Virag wrote: >> CMU_FSYS clock domain provides clocks for MMC (MMC_CARD, MMC_EMBD, >> MMC_SDIO), and USB30DRD. >> >> Add clock indices and bindings documentation for CMU_FSYS domain. >> >> Signed-off-by: David Virag <virag.david003@gmail.com> >> --- >> .../clock/samsung,exynos7885-clock.yaml | 27 ++++++++++++++++ >> include/dt-bindings/clock/exynos7885.h | 31 ++++++++++++++++++- > It seems the clock IDs from bindings are used by both driver and DTS. > Sylwester, can I take them to Samsung Soc and send you a pull request? Sure, let's do it that way. -- Regards, Sylwester ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 1/5] dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS @ 2022-06-20 10:31 ` Sylwester Nawrocki 0 siblings, 0 replies; 38+ messages in thread From: Sylwester Nawrocki @ 2022-06-20 10:31 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: phone-devel, David Virag, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On 08.06.2022 17:12, Krzysztof Kozlowski wrote: > On 02/06/2022 01:37, David Virag wrote: >> CMU_FSYS clock domain provides clocks for MMC (MMC_CARD, MMC_EMBD, >> MMC_SDIO), and USB30DRD. >> >> Add clock indices and bindings documentation for CMU_FSYS domain. >> >> Signed-off-by: David Virag <virag.david003@gmail.com> >> --- >> .../clock/samsung,exynos7885-clock.yaml | 27 ++++++++++++++++ >> include/dt-bindings/clock/exynos7885.h | 31 ++++++++++++++++++- > It seems the clock IDs from bindings are used by both driver and DTS. > Sylwester, can I take them to Samsung Soc and send you a pull request? Sure, let's do it that way. -- Regards, Sylwester _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 38+ messages in thread
[parent not found: <CGME20220620102819eucas1p2b03a01c45ca3d0d42ebb9542954f0a4a@eucas1p2.samsung.com>]
* Re: [PATCH 1/5] dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS [not found] ` <CGME20220620102819eucas1p2b03a01c45ca3d0d42ebb9542954f0a4a@eucas1p2.samsung.com> @ 2022-06-20 10:28 ` Sylwester Nawrocki 0 siblings, 0 replies; 38+ messages in thread From: Sylwester Nawrocki @ 2022-06-20 10:28 UTC (permalink / raw) To: David Virag Cc: phone-devel, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On 02.06.2022 01:37, David Virag wrote: > CMU_FSYS clock domain provides clocks for MMC (MMC_CARD, MMC_EMBD, > MMC_SDIO), and USB30DRD. > > Add clock indices and bindings documentation for CMU_FSYS domain. > > Signed-off-by: David Virag <virag.david003@gmail.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 1/5] dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS @ 2022-06-20 10:28 ` Sylwester Nawrocki 0 siblings, 0 replies; 38+ messages in thread From: Sylwester Nawrocki @ 2022-06-20 10:28 UTC (permalink / raw) To: David Virag Cc: phone-devel, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On 02.06.2022 01:37, David Virag wrote: > CMU_FSYS clock domain provides clocks for MMC (MMC_CARD, MMC_EMBD, > MMC_SDIO), and USB30DRD. > > Add clock indices and bindings documentation for CMU_FSYS domain. > > Signed-off-by: David Virag <virag.david003@gmail.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: (subset) [PATCH 1/5] dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS 2022-06-01 23:37 ` David Virag @ 2022-06-20 12:27 ` Krzysztof Kozlowski -1 siblings, 0 replies; 38+ messages in thread From: Krzysztof Kozlowski @ 2022-06-20 12:27 UTC (permalink / raw) To: David Virag Cc: Krzysztof Kozlowski, Stephen Boyd, Krzysztof Kozlowski, devicetree, Tomasz Figa, phone-devel, Sylwester Nawrocki, linux-samsung-soc, linux-clk, Michael Turquette, Alim Akhtar, linux-arm-kernel, Chanwoo Choi, Rob Herring, linux-kernel On Thu, 2 Jun 2022 01:37:39 +0200, David Virag wrote: > CMU_FSYS clock domain provides clocks for MMC (MMC_CARD, MMC_EMBD, > MMC_SDIO), and USB30DRD. > > Add clock indices and bindings documentation for CMU_FSYS domain. > > Applied, thanks! [1/5] dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS https://git.kernel.org/krzk/linux/c/cd268e309c29e9a8b15a47f684d848c1d57fe150 Best regards, -- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: (subset) [PATCH 1/5] dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS @ 2022-06-20 12:27 ` Krzysztof Kozlowski 0 siblings, 0 replies; 38+ messages in thread From: Krzysztof Kozlowski @ 2022-06-20 12:27 UTC (permalink / raw) To: David Virag Cc: Krzysztof Kozlowski, Stephen Boyd, Krzysztof Kozlowski, devicetree, Tomasz Figa, phone-devel, Sylwester Nawrocki, linux-samsung-soc, linux-clk, Michael Turquette, Alim Akhtar, linux-arm-kernel, Chanwoo Choi, Rob Herring, linux-kernel On Thu, 2 Jun 2022 01:37:39 +0200, David Virag wrote: > CMU_FSYS clock domain provides clocks for MMC (MMC_CARD, MMC_EMBD, > MMC_SDIO), and USB30DRD. > > Add clock indices and bindings documentation for CMU_FSYS domain. > > Applied, thanks! [1/5] dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS https://git.kernel.org/krzk/linux/c/cd268e309c29e9a8b15a47f684d848c1d57fe150 Best regards, -- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 2/5] dt-bindings: clock: Add indices for Exynos7885 TREX clocks 2022-06-01 23:37 ` David Virag @ 2022-06-01 23:37 ` David Virag -1 siblings, 0 replies; 38+ messages in thread From: David Virag @ 2022-06-01 23:37 UTC (permalink / raw) Cc: phone-devel, David Virag, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel TREX D Core and P core clocks seem to be related to the BTS (Bus Traffic Shaper) inside the Exynos7885 SoC, and are needed for the SoC to function correctly. Add indices for these clocks. Signed-off-by: David Virag <virag.david003@gmail.com> --- include/dt-bindings/clock/exynos7885.h | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/include/dt-bindings/clock/exynos7885.h b/include/dt-bindings/clock/exynos7885.h index d2e1483f93e4..8256e7430b63 100644 --- a/include/dt-bindings/clock/exynos7885.h +++ b/include/dt-bindings/clock/exynos7885.h @@ -72,14 +72,21 @@ #define TOP_NR_CLK 61 /* CMU_CORE */ -#define CLK_MOUT_CORE_BUS_USER 1 -#define CLK_MOUT_CORE_CCI_USER 2 -#define CLK_MOUT_CORE_G3D_USER 3 -#define CLK_MOUT_CORE_GIC 4 -#define CLK_DOUT_CORE_BUSP 5 -#define CLK_GOUT_CCI_ACLK 6 -#define CLK_GOUT_GIC400_CLK 7 -#define CORE_NR_CLK 8 +#define CLK_MOUT_CORE_BUS_USER 1 +#define CLK_MOUT_CORE_CCI_USER 2 +#define CLK_MOUT_CORE_G3D_USER 3 +#define CLK_MOUT_CORE_GIC 4 +#define CLK_DOUT_CORE_BUSP 5 +#define CLK_GOUT_CCI_ACLK 6 +#define CLK_GOUT_GIC400_CLK 7 +#define CLK_GOUT_TREX_D_CORE_ACLK 8 +#define CLK_GOUT_TREX_D_CORE_GCLK 9 +#define CLK_GOUT_TREX_D_CORE_PCLK 10 +#define CLK_GOUT_TREX_P_CORE_ACLK_P_CORE 11 +#define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE 12 +#define CLK_GOUT_TREX_P_CORE_PCLK 13 +#define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE 14 +#define CORE_NR_CLK 15 /* CMU_PERI */ #define CLK_MOUT_PERI_BUS_USER 1 -- 2.36.1 ^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 2/5] dt-bindings: clock: Add indices for Exynos7885 TREX clocks @ 2022-06-01 23:37 ` David Virag 0 siblings, 0 replies; 38+ messages in thread From: David Virag @ 2022-06-01 23:37 UTC (permalink / raw) Cc: phone-devel, David Virag, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel TREX D Core and P core clocks seem to be related to the BTS (Bus Traffic Shaper) inside the Exynos7885 SoC, and are needed for the SoC to function correctly. Add indices for these clocks. Signed-off-by: David Virag <virag.david003@gmail.com> --- include/dt-bindings/clock/exynos7885.h | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/include/dt-bindings/clock/exynos7885.h b/include/dt-bindings/clock/exynos7885.h index d2e1483f93e4..8256e7430b63 100644 --- a/include/dt-bindings/clock/exynos7885.h +++ b/include/dt-bindings/clock/exynos7885.h @@ -72,14 +72,21 @@ #define TOP_NR_CLK 61 /* CMU_CORE */ -#define CLK_MOUT_CORE_BUS_USER 1 -#define CLK_MOUT_CORE_CCI_USER 2 -#define CLK_MOUT_CORE_G3D_USER 3 -#define CLK_MOUT_CORE_GIC 4 -#define CLK_DOUT_CORE_BUSP 5 -#define CLK_GOUT_CCI_ACLK 6 -#define CLK_GOUT_GIC400_CLK 7 -#define CORE_NR_CLK 8 +#define CLK_MOUT_CORE_BUS_USER 1 +#define CLK_MOUT_CORE_CCI_USER 2 +#define CLK_MOUT_CORE_G3D_USER 3 +#define CLK_MOUT_CORE_GIC 4 +#define CLK_DOUT_CORE_BUSP 5 +#define CLK_GOUT_CCI_ACLK 6 +#define CLK_GOUT_GIC400_CLK 7 +#define CLK_GOUT_TREX_D_CORE_ACLK 8 +#define CLK_GOUT_TREX_D_CORE_GCLK 9 +#define CLK_GOUT_TREX_D_CORE_PCLK 10 +#define CLK_GOUT_TREX_P_CORE_ACLK_P_CORE 11 +#define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE 12 +#define CLK_GOUT_TREX_P_CORE_PCLK 13 +#define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE 14 +#define CORE_NR_CLK 15 /* CMU_PERI */ #define CLK_MOUT_PERI_BUS_USER 1 -- 2.36.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH 2/5] dt-bindings: clock: Add indices for Exynos7885 TREX clocks 2022-06-01 23:37 ` David Virag @ 2022-06-02 11:55 ` Krzysztof Kozlowski -1 siblings, 0 replies; 38+ messages in thread From: Krzysztof Kozlowski @ 2022-06-02 11:55 UTC (permalink / raw) To: David Virag Cc: phone-devel, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On 02/06/2022 01:37, David Virag wrote: > TREX D Core and P core clocks seem to be related to the BTS (Bus Traffic > Shaper) inside the Exynos7885 SoC, and are needed for the SoC to > function correctly. > > Add indices for these clocks. > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 2/5] dt-bindings: clock: Add indices for Exynos7885 TREX clocks @ 2022-06-02 11:55 ` Krzysztof Kozlowski 0 siblings, 0 replies; 38+ messages in thread From: Krzysztof Kozlowski @ 2022-06-02 11:55 UTC (permalink / raw) To: David Virag Cc: phone-devel, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On 02/06/2022 01:37, David Virag wrote: > TREX D Core and P core clocks seem to be related to the BTS (Bus Traffic > Shaper) inside the Exynos7885 SoC, and are needed for the SoC to > function correctly. > > Add indices for these clocks. > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: (subset) [PATCH 2/5] dt-bindings: clock: Add indices for Exynos7885 TREX clocks 2022-06-01 23:37 ` David Virag @ 2022-06-20 12:27 ` Krzysztof Kozlowski -1 siblings, 0 replies; 38+ messages in thread From: Krzysztof Kozlowski @ 2022-06-20 12:27 UTC (permalink / raw) To: David Virag Cc: Krzysztof Kozlowski, Stephen Boyd, devicetree, Krzysztof Kozlowski, Tomasz Figa, phone-devel, Sylwester Nawrocki, linux-samsung-soc, linux-clk, Michael Turquette, Alim Akhtar, linux-arm-kernel, Chanwoo Choi, Rob Herring, linux-kernel On Thu, 2 Jun 2022 01:37:40 +0200, David Virag wrote: > TREX D Core and P core clocks seem to be related to the BTS (Bus Traffic > Shaper) inside the Exynos7885 SoC, and are needed for the SoC to > function correctly. > > Add indices for these clocks. > > > [...] Applied, thanks! [2/5] dt-bindings: clock: Add indices for Exynos7885 TREX clocks https://git.kernel.org/krzk/linux/c/e756e932a3a16418cd8bad757b028bfb337b4a51 Best regards, -- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: (subset) [PATCH 2/5] dt-bindings: clock: Add indices for Exynos7885 TREX clocks @ 2022-06-20 12:27 ` Krzysztof Kozlowski 0 siblings, 0 replies; 38+ messages in thread From: Krzysztof Kozlowski @ 2022-06-20 12:27 UTC (permalink / raw) To: David Virag Cc: Krzysztof Kozlowski, Stephen Boyd, devicetree, Krzysztof Kozlowski, Tomasz Figa, phone-devel, Sylwester Nawrocki, linux-samsung-soc, linux-clk, Michael Turquette, Alim Akhtar, linux-arm-kernel, Chanwoo Choi, Rob Herring, linux-kernel On Thu, 2 Jun 2022 01:37:40 +0200, David Virag wrote: > TREX D Core and P core clocks seem to be related to the BTS (Bus Traffic > Shaper) inside the Exynos7885 SoC, and are needed for the SoC to > function correctly. > > Add indices for these clocks. > > > [...] Applied, thanks! [2/5] dt-bindings: clock: Add indices for Exynos7885 TREX clocks https://git.kernel.org/krzk/linux/c/e756e932a3a16418cd8bad757b028bfb337b4a51 Best regards, -- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 3/5] clk: samsung: exynos7885: Implement CMU_FSYS domain 2022-06-01 23:37 ` David Virag @ 2022-06-01 23:37 ` David Virag -1 siblings, 0 replies; 38+ messages in thread From: David Virag @ 2022-06-01 23:37 UTC (permalink / raw) Cc: phone-devel, David Virag, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel CMU_FSYS clock domain provides clocks for FSYS IP-core providing clocks for all MMC devices on Exynos7885, and USB30DRD. This patch includes: - Bus clocks in CMU_TOP needed for CMU_FSYS - All clocks in CMU_FSYS needed for MMC devices Signed-off-by: David Virag <virag.david003@gmail.com> --- drivers/clk/samsung/clk-exynos7885.c | 158 +++++++++++++++++++++++++++ 1 file changed, 158 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos7885.c b/drivers/clk/samsung/clk-exynos7885.c index 368c50badd15..302937025409 100644 --- a/drivers/clk/samsung/clk-exynos7885.c +++ b/drivers/clk/samsung/clk-exynos7885.c @@ -27,6 +27,11 @@ #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014 #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018 #define CLK_CON_MUX_MUX_CLKCMU_CORE_G3D 0x101c +#define CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS 0x1028 +#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD 0x102c +#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD 0x1030 +#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO 0x1034 +#define CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD 0x1038 #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1058 #define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0 0x105c #define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1 0x1060 @@ -39,6 +44,11 @@ #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x181c #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1820 #define CLK_CON_DIV_CLKCMU_CORE_G3D 0x1824 +#define CLK_CON_DIV_CLKCMU_FSYS_BUS 0x1844 +#define CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD 0x1848 +#define CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD 0x184c +#define CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO 0x1850 +#define CLK_CON_DIV_CLKCMU_FSYS_USB30DRD 0x1854 #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x1874 #define CLK_CON_DIV_CLKCMU_PERI_SPI0 0x1878 #define CLK_CON_DIV_CLKCMU_PERI_SPI1 0x187c @@ -59,6 +69,11 @@ #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020 #define CLK_CON_GAT_GATE_CLKCMU_CORE_G3D 0x2024 +#define CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS 0x2044 +#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD 0x2048 +#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD 0x204c +#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO 0x2050 +#define CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD 0x2054 #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x207c #define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0 0x2080 #define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1 0x2084 @@ -76,6 +91,11 @@ static const unsigned long top_clk_regs[] __initconst = { CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D, + CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS, + CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD, + CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD, + CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO, + CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0, CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1, @@ -88,6 +108,11 @@ static const unsigned long top_clk_regs[] __initconst = { CLK_CON_DIV_CLKCMU_CORE_BUS, CLK_CON_DIV_CLKCMU_CORE_CCI, CLK_CON_DIV_CLKCMU_CORE_G3D, + CLK_CON_DIV_CLKCMU_FSYS_BUS, + CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD, + CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD, + CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO, + CLK_CON_DIV_CLKCMU_FSYS_USB30DRD, CLK_CON_DIV_CLKCMU_PERI_BUS, CLK_CON_DIV_CLKCMU_PERI_SPI0, CLK_CON_DIV_CLKCMU_PERI_SPI1, @@ -108,6 +133,11 @@ static const unsigned long top_clk_regs[] __initconst = { CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D, + CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS, + CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD, + CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD, + CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO, + CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0, CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1, @@ -146,6 +176,13 @@ PNAME(mout_peri_usi0_p) = { "oscclk", "dout_shared0_div4" }; PNAME(mout_peri_usi1_p) = { "oscclk", "dout_shared0_div4" }; PNAME(mout_peri_usi2_p) = { "oscclk", "dout_shared0_div4" }; +/* List of parent clocks for Muxes in CMU_TOP: for CMU_FSYS */ +PNAME(mout_fsys_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" }; +PNAME(mout_fsys_mmc_card_p) = { "dout_shared0_div2", "dout_shared1_div2" }; +PNAME(mout_fsys_mmc_embd_p) = { "dout_shared0_div2", "dout_shared1_div2" }; +PNAME(mout_fsys_mmc_sdio_p) = { "dout_shared0_div2", "dout_shared1_div2" }; +PNAME(mout_fsys_usb30drd_p) = { "dout_shared0_div4", "dout_shared1_div4" }; + static const struct samsung_mux_clock top_mux_clks[] __initconst = { /* CORE */ MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p, @@ -174,6 +211,18 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = { CLK_CON_MUX_MUX_CLKCMU_PERI_USI1, 0, 1), MUX(CLK_MOUT_PERI_USI2, "mout_peri_usi2", mout_peri_usi2_p, CLK_CON_MUX_MUX_CLKCMU_PERI_USI2, 0, 1), + + /* FSYS */ + MUX(CLK_MOUT_FSYS_BUS, "mout_fsys_bus", mout_fsys_bus_p, + CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS, 0, 1), + MUX(CLK_MOUT_FSYS_MMC_CARD, "mout_fsys_mmc_card", mout_fsys_mmc_card_p, + CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD, 0, 1), + MUX(CLK_MOUT_FSYS_MMC_EMBD, "mout_fsys_mmc_embd", mout_fsys_mmc_embd_p, + CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD, 0, 1), + MUX(CLK_MOUT_FSYS_MMC_SDIO, "mout_fsys_mmc_sdio", mout_fsys_mmc_sdio_p, + CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO, 0, 1), + MUX(CLK_MOUT_FSYS_USB30DRD, "mout_fsys_usb30drd", mout_fsys_usb30drd_p, + CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD, 0, 1), }; static const struct samsung_div_clock top_div_clks[] __initconst = { @@ -220,6 +269,18 @@ static const struct samsung_div_clock top_div_clks[] __initconst = { CLK_CON_DIV_CLKCMU_PERI_USI1, 0, 4), DIV(CLK_DOUT_PERI_USI2, "dout_peri_usi2", "gout_peri_usi2", CLK_CON_DIV_CLKCMU_PERI_USI2, 0, 4), + + /* FSYS */ + DIV(CLK_DOUT_FSYS_BUS, "dout_fsys_bus", "gout_fsys_bus", + CLK_CON_DIV_CLKCMU_FSYS_BUS, 0, 4), + DIV(CLK_DOUT_FSYS_MMC_CARD, "dout_fsys_mmc_card", "gout_fsys_mmc_card", + CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD, 0, 9), + DIV(CLK_DOUT_FSYS_MMC_EMBD, "dout_fsys_mmc_embd", "gout_fsys_mmc_embd", + CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD, 0, 9), + DIV(CLK_DOUT_FSYS_MMC_SDIO, "dout_fsys_mmc_sdio", "gout_fsys_mmc_sdio", + CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO, 0, 9), + DIV(CLK_DOUT_FSYS_USB30DRD, "dout_fsys_usb30drd", "gout_fsys_usb30drd", + CLK_CON_DIV_CLKCMU_FSYS_USB30DRD, 0, 4), }; static const struct samsung_gate_clock top_gate_clks[] __initconst = { @@ -250,6 +311,18 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = { CLK_CON_GAT_GATE_CLKCMU_PERI_USI1, 21, 0, 0), GATE(CLK_GOUT_PERI_USI2, "gout_peri_usi2", "mout_peri_usi2", CLK_CON_GAT_GATE_CLKCMU_PERI_USI2, 21, 0, 0), + + /* FSYS */ + GATE(CLK_GOUT_FSYS_BUS, "gout_fsys_bus", "mout_fsys_bus", + CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS, 21, 0, 0), + GATE(CLK_GOUT_FSYS_MMC_CARD, "gout_fsys_mmc_card", "mout_fsys_mmc_card", + CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD, 21, 0, 0), + GATE(CLK_GOUT_FSYS_MMC_EMBD, "gout_fsys_mmc_embd", "mout_fsys_mmc_embd", + CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD, 21, 0, 0), + GATE(CLK_GOUT_FSYS_MMC_SDIO, "gout_fsys_mmc_sdio", "mout_fsys_mmc_sdio", + CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO, 21, 0, 0), + GATE(CLK_GOUT_FSYS_USB30DRD, "gout_fsys_usb30drd", "mout_fsys_usb30drd", + CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD, 21, 0, 0), }; static const struct samsung_cmu_info top_cmu_info __initconst = { @@ -560,6 +633,88 @@ static const struct samsung_cmu_info core_cmu_info __initconst = { .clk_name = "dout_core_bus", }; +/* ---- CMU_FSYS ------------------------------------------------------------ */ + +/* Register Offset definitions for CMU_FSYS (0x13400000) */ +#define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER 0x0100 +#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER 0x0120 +#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER 0x0140 +#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER 0x0160 +#define PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER 0x0180 +#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK 0x2030 +#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN 0x2034 +#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK 0x2038 +#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN 0x203c +#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK 0x2040 +#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN 0x2044 + +static const unsigned long fsys_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER, + PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER, + PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER, + PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER, + PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER, + CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK, + CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN, + CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK, + CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN, + CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK, + CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN, +}; + +/* List of parent clocks for Muxes in CMU_FSYS */ +PNAME(mout_fsys_bus_user_p) = { "oscclk", "dout_fsys_bus" }; +PNAME(mout_fsys_mmc_card_user_p) = { "oscclk", "dout_fsys_mmc_card" }; +PNAME(mout_fsys_mmc_embd_user_p) = { "oscclk", "dout_fsys_mmc_embd" }; +PNAME(mout_fsys_mmc_sdio_user_p) = { "oscclk", "dout_fsys_mmc_sdio" }; +PNAME(mout_fsys_usb30drd_user_p) = { "oscclk", "dout_fsys_usb30drd" }; + +static const struct samsung_mux_clock fsys_mux_clks[] __initconst = { + MUX(CLK_MOUT_FSYS_BUS_USER, "mout_fsys_bus_user", mout_fsys_bus_user_p, + PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER, 4, 1), + MUX_F(CLK_MOUT_FSYS_MMC_CARD_USER, "mout_fsys_mmc_card_user", + mout_fsys_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER, + 4, 1, CLK_SET_RATE_PARENT, 0), + MUX_F(CLK_MOUT_FSYS_MMC_EMBD_USER, "mout_fsys_mmc_embd_user", + mout_fsys_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER, + 4, 1, CLK_SET_RATE_PARENT, 0), + MUX_F(CLK_MOUT_FSYS_MMC_SDIO_USER, "mout_fsys_mmc_sdio_user", + mout_fsys_mmc_sdio_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER, + 4, 1, CLK_SET_RATE_PARENT, 0), + MUX_F(CLK_MOUT_FSYS_USB30DRD_USER, "mout_fsys_usb30drd_user", + mout_fsys_usb30drd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER, + 4, 1, CLK_SET_RATE_PARENT, 0), +}; + +static const struct samsung_gate_clock fsys_gate_clks[] __initconst = { + GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_fsys_bus_user", + CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK, 21, 0, 0), + GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", + "mout_fsys_mmc_card_user", CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN, + 21, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "mout_fsys_bus_user", + CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK, 21, 0, 0), + GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin", + "mout_fsys_mmc_embd_user", CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN, + 21, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MMC_SDIO_ACLK, "gout_mmc_sdio_aclk", "mout_fsys_bus_user", + CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK, 21, 0, 0), + GATE(CLK_GOUT_MMC_SDIO_SDCLKIN, "gout_mmc_sdio_sdclkin", + "mout_fsys_mmc_sdio_user", CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN, + 21, CLK_SET_RATE_PARENT, 0), +}; + +static const struct samsung_cmu_info fsys_cmu_info __initconst = { + .mux_clks = fsys_mux_clks, + .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks), + .gate_clks = fsys_gate_clks, + .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks), + .nr_clk_ids = FSYS_NR_CLK, + .clk_regs = fsys_clk_regs, + .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs), + .clk_name = "dout_fsys_bus", +}; + /* ---- platform_driver ----------------------------------------------------- */ static int __init exynos7885_cmu_probe(struct platform_device *pdev) @@ -577,6 +732,9 @@ static const struct of_device_id exynos7885_cmu_of_match[] = { { .compatible = "samsung,exynos7885-cmu-core", .data = &core_cmu_info, + }, { + .compatible = "samsung,exynos7885-cmu-fsys", + .data = &fsys_cmu_info, }, { }, }; -- 2.36.1 ^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 3/5] clk: samsung: exynos7885: Implement CMU_FSYS domain @ 2022-06-01 23:37 ` David Virag 0 siblings, 0 replies; 38+ messages in thread From: David Virag @ 2022-06-01 23:37 UTC (permalink / raw) Cc: phone-devel, David Virag, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel CMU_FSYS clock domain provides clocks for FSYS IP-core providing clocks for all MMC devices on Exynos7885, and USB30DRD. This patch includes: - Bus clocks in CMU_TOP needed for CMU_FSYS - All clocks in CMU_FSYS needed for MMC devices Signed-off-by: David Virag <virag.david003@gmail.com> --- drivers/clk/samsung/clk-exynos7885.c | 158 +++++++++++++++++++++++++++ 1 file changed, 158 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos7885.c b/drivers/clk/samsung/clk-exynos7885.c index 368c50badd15..302937025409 100644 --- a/drivers/clk/samsung/clk-exynos7885.c +++ b/drivers/clk/samsung/clk-exynos7885.c @@ -27,6 +27,11 @@ #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014 #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018 #define CLK_CON_MUX_MUX_CLKCMU_CORE_G3D 0x101c +#define CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS 0x1028 +#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD 0x102c +#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD 0x1030 +#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO 0x1034 +#define CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD 0x1038 #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1058 #define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0 0x105c #define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1 0x1060 @@ -39,6 +44,11 @@ #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x181c #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1820 #define CLK_CON_DIV_CLKCMU_CORE_G3D 0x1824 +#define CLK_CON_DIV_CLKCMU_FSYS_BUS 0x1844 +#define CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD 0x1848 +#define CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD 0x184c +#define CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO 0x1850 +#define CLK_CON_DIV_CLKCMU_FSYS_USB30DRD 0x1854 #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x1874 #define CLK_CON_DIV_CLKCMU_PERI_SPI0 0x1878 #define CLK_CON_DIV_CLKCMU_PERI_SPI1 0x187c @@ -59,6 +69,11 @@ #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020 #define CLK_CON_GAT_GATE_CLKCMU_CORE_G3D 0x2024 +#define CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS 0x2044 +#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD 0x2048 +#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD 0x204c +#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO 0x2050 +#define CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD 0x2054 #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x207c #define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0 0x2080 #define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1 0x2084 @@ -76,6 +91,11 @@ static const unsigned long top_clk_regs[] __initconst = { CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D, + CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS, + CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD, + CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD, + CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO, + CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0, CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1, @@ -88,6 +108,11 @@ static const unsigned long top_clk_regs[] __initconst = { CLK_CON_DIV_CLKCMU_CORE_BUS, CLK_CON_DIV_CLKCMU_CORE_CCI, CLK_CON_DIV_CLKCMU_CORE_G3D, + CLK_CON_DIV_CLKCMU_FSYS_BUS, + CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD, + CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD, + CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO, + CLK_CON_DIV_CLKCMU_FSYS_USB30DRD, CLK_CON_DIV_CLKCMU_PERI_BUS, CLK_CON_DIV_CLKCMU_PERI_SPI0, CLK_CON_DIV_CLKCMU_PERI_SPI1, @@ -108,6 +133,11 @@ static const unsigned long top_clk_regs[] __initconst = { CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D, + CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS, + CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD, + CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD, + CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO, + CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0, CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1, @@ -146,6 +176,13 @@ PNAME(mout_peri_usi0_p) = { "oscclk", "dout_shared0_div4" }; PNAME(mout_peri_usi1_p) = { "oscclk", "dout_shared0_div4" }; PNAME(mout_peri_usi2_p) = { "oscclk", "dout_shared0_div4" }; +/* List of parent clocks for Muxes in CMU_TOP: for CMU_FSYS */ +PNAME(mout_fsys_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" }; +PNAME(mout_fsys_mmc_card_p) = { "dout_shared0_div2", "dout_shared1_div2" }; +PNAME(mout_fsys_mmc_embd_p) = { "dout_shared0_div2", "dout_shared1_div2" }; +PNAME(mout_fsys_mmc_sdio_p) = { "dout_shared0_div2", "dout_shared1_div2" }; +PNAME(mout_fsys_usb30drd_p) = { "dout_shared0_div4", "dout_shared1_div4" }; + static const struct samsung_mux_clock top_mux_clks[] __initconst = { /* CORE */ MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p, @@ -174,6 +211,18 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = { CLK_CON_MUX_MUX_CLKCMU_PERI_USI1, 0, 1), MUX(CLK_MOUT_PERI_USI2, "mout_peri_usi2", mout_peri_usi2_p, CLK_CON_MUX_MUX_CLKCMU_PERI_USI2, 0, 1), + + /* FSYS */ + MUX(CLK_MOUT_FSYS_BUS, "mout_fsys_bus", mout_fsys_bus_p, + CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS, 0, 1), + MUX(CLK_MOUT_FSYS_MMC_CARD, "mout_fsys_mmc_card", mout_fsys_mmc_card_p, + CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD, 0, 1), + MUX(CLK_MOUT_FSYS_MMC_EMBD, "mout_fsys_mmc_embd", mout_fsys_mmc_embd_p, + CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD, 0, 1), + MUX(CLK_MOUT_FSYS_MMC_SDIO, "mout_fsys_mmc_sdio", mout_fsys_mmc_sdio_p, + CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO, 0, 1), + MUX(CLK_MOUT_FSYS_USB30DRD, "mout_fsys_usb30drd", mout_fsys_usb30drd_p, + CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD, 0, 1), }; static const struct samsung_div_clock top_div_clks[] __initconst = { @@ -220,6 +269,18 @@ static const struct samsung_div_clock top_div_clks[] __initconst = { CLK_CON_DIV_CLKCMU_PERI_USI1, 0, 4), DIV(CLK_DOUT_PERI_USI2, "dout_peri_usi2", "gout_peri_usi2", CLK_CON_DIV_CLKCMU_PERI_USI2, 0, 4), + + /* FSYS */ + DIV(CLK_DOUT_FSYS_BUS, "dout_fsys_bus", "gout_fsys_bus", + CLK_CON_DIV_CLKCMU_FSYS_BUS, 0, 4), + DIV(CLK_DOUT_FSYS_MMC_CARD, "dout_fsys_mmc_card", "gout_fsys_mmc_card", + CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD, 0, 9), + DIV(CLK_DOUT_FSYS_MMC_EMBD, "dout_fsys_mmc_embd", "gout_fsys_mmc_embd", + CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD, 0, 9), + DIV(CLK_DOUT_FSYS_MMC_SDIO, "dout_fsys_mmc_sdio", "gout_fsys_mmc_sdio", + CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO, 0, 9), + DIV(CLK_DOUT_FSYS_USB30DRD, "dout_fsys_usb30drd", "gout_fsys_usb30drd", + CLK_CON_DIV_CLKCMU_FSYS_USB30DRD, 0, 4), }; static const struct samsung_gate_clock top_gate_clks[] __initconst = { @@ -250,6 +311,18 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = { CLK_CON_GAT_GATE_CLKCMU_PERI_USI1, 21, 0, 0), GATE(CLK_GOUT_PERI_USI2, "gout_peri_usi2", "mout_peri_usi2", CLK_CON_GAT_GATE_CLKCMU_PERI_USI2, 21, 0, 0), + + /* FSYS */ + GATE(CLK_GOUT_FSYS_BUS, "gout_fsys_bus", "mout_fsys_bus", + CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS, 21, 0, 0), + GATE(CLK_GOUT_FSYS_MMC_CARD, "gout_fsys_mmc_card", "mout_fsys_mmc_card", + CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD, 21, 0, 0), + GATE(CLK_GOUT_FSYS_MMC_EMBD, "gout_fsys_mmc_embd", "mout_fsys_mmc_embd", + CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD, 21, 0, 0), + GATE(CLK_GOUT_FSYS_MMC_SDIO, "gout_fsys_mmc_sdio", "mout_fsys_mmc_sdio", + CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO, 21, 0, 0), + GATE(CLK_GOUT_FSYS_USB30DRD, "gout_fsys_usb30drd", "mout_fsys_usb30drd", + CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD, 21, 0, 0), }; static const struct samsung_cmu_info top_cmu_info __initconst = { @@ -560,6 +633,88 @@ static const struct samsung_cmu_info core_cmu_info __initconst = { .clk_name = "dout_core_bus", }; +/* ---- CMU_FSYS ------------------------------------------------------------ */ + +/* Register Offset definitions for CMU_FSYS (0x13400000) */ +#define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER 0x0100 +#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER 0x0120 +#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER 0x0140 +#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER 0x0160 +#define PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER 0x0180 +#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK 0x2030 +#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN 0x2034 +#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK 0x2038 +#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN 0x203c +#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK 0x2040 +#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN 0x2044 + +static const unsigned long fsys_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER, + PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER, + PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER, + PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER, + PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER, + CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK, + CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN, + CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK, + CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN, + CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK, + CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN, +}; + +/* List of parent clocks for Muxes in CMU_FSYS */ +PNAME(mout_fsys_bus_user_p) = { "oscclk", "dout_fsys_bus" }; +PNAME(mout_fsys_mmc_card_user_p) = { "oscclk", "dout_fsys_mmc_card" }; +PNAME(mout_fsys_mmc_embd_user_p) = { "oscclk", "dout_fsys_mmc_embd" }; +PNAME(mout_fsys_mmc_sdio_user_p) = { "oscclk", "dout_fsys_mmc_sdio" }; +PNAME(mout_fsys_usb30drd_user_p) = { "oscclk", "dout_fsys_usb30drd" }; + +static const struct samsung_mux_clock fsys_mux_clks[] __initconst = { + MUX(CLK_MOUT_FSYS_BUS_USER, "mout_fsys_bus_user", mout_fsys_bus_user_p, + PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER, 4, 1), + MUX_F(CLK_MOUT_FSYS_MMC_CARD_USER, "mout_fsys_mmc_card_user", + mout_fsys_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER, + 4, 1, CLK_SET_RATE_PARENT, 0), + MUX_F(CLK_MOUT_FSYS_MMC_EMBD_USER, "mout_fsys_mmc_embd_user", + mout_fsys_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER, + 4, 1, CLK_SET_RATE_PARENT, 0), + MUX_F(CLK_MOUT_FSYS_MMC_SDIO_USER, "mout_fsys_mmc_sdio_user", + mout_fsys_mmc_sdio_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER, + 4, 1, CLK_SET_RATE_PARENT, 0), + MUX_F(CLK_MOUT_FSYS_USB30DRD_USER, "mout_fsys_usb30drd_user", + mout_fsys_usb30drd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER, + 4, 1, CLK_SET_RATE_PARENT, 0), +}; + +static const struct samsung_gate_clock fsys_gate_clks[] __initconst = { + GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_fsys_bus_user", + CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK, 21, 0, 0), + GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", + "mout_fsys_mmc_card_user", CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN, + 21, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "mout_fsys_bus_user", + CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK, 21, 0, 0), + GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin", + "mout_fsys_mmc_embd_user", CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN, + 21, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MMC_SDIO_ACLK, "gout_mmc_sdio_aclk", "mout_fsys_bus_user", + CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK, 21, 0, 0), + GATE(CLK_GOUT_MMC_SDIO_SDCLKIN, "gout_mmc_sdio_sdclkin", + "mout_fsys_mmc_sdio_user", CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN, + 21, CLK_SET_RATE_PARENT, 0), +}; + +static const struct samsung_cmu_info fsys_cmu_info __initconst = { + .mux_clks = fsys_mux_clks, + .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks), + .gate_clks = fsys_gate_clks, + .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks), + .nr_clk_ids = FSYS_NR_CLK, + .clk_regs = fsys_clk_regs, + .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs), + .clk_name = "dout_fsys_bus", +}; + /* ---- platform_driver ----------------------------------------------------- */ static int __init exynos7885_cmu_probe(struct platform_device *pdev) @@ -577,6 +732,9 @@ static const struct of_device_id exynos7885_cmu_of_match[] = { { .compatible = "samsung,exynos7885-cmu-core", .data = &core_cmu_info, + }, { + .compatible = "samsung,exynos7885-cmu-fsys", + .data = &fsys_cmu_info, }, { }, }; -- 2.36.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH 3/5] clk: samsung: exynos7885: Implement CMU_FSYS domain 2022-06-01 23:37 ` David Virag @ 2022-06-02 11:56 ` Krzysztof Kozlowski -1 siblings, 0 replies; 38+ messages in thread From: Krzysztof Kozlowski @ 2022-06-02 11:56 UTC (permalink / raw) To: David Virag Cc: phone-devel, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On 02/06/2022 01:37, David Virag wrote: > CMU_FSYS clock domain provides clocks for FSYS IP-core providing clocks > for all MMC devices on Exynos7885, and USB30DRD. > > This patch includes: https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/submitting-patches.rst#L95 s/This patch includes:/Add:/ > - Bus clocks in CMU_TOP needed for CMU_FSYS > - All clocks in CMU_FSYS needed for MMC devices > > Signed-off-by: David Virag <virag.david003@gmail.com> > --- Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 3/5] clk: samsung: exynos7885: Implement CMU_FSYS domain @ 2022-06-02 11:56 ` Krzysztof Kozlowski 0 siblings, 0 replies; 38+ messages in thread From: Krzysztof Kozlowski @ 2022-06-02 11:56 UTC (permalink / raw) To: David Virag Cc: phone-devel, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On 02/06/2022 01:37, David Virag wrote: > CMU_FSYS clock domain provides clocks for FSYS IP-core providing clocks > for all MMC devices on Exynos7885, and USB30DRD. > > This patch includes: https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/submitting-patches.rst#L95 s/This patch includes:/Add:/ > - Bus clocks in CMU_TOP needed for CMU_FSYS > - All clocks in CMU_FSYS needed for MMC devices > > Signed-off-by: David Virag <virag.david003@gmail.com> > --- Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 4/5] clk: samsung: exynos7885: Add TREX clocks 2022-06-01 23:37 ` David Virag @ 2022-06-01 23:37 ` David Virag -1 siblings, 0 replies; 38+ messages in thread From: David Virag @ 2022-06-01 23:37 UTC (permalink / raw) Cc: phone-devel, David Virag, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel TREX D Core and P core clocks seem to be related to the BTS (Bus Traffic Shaper) inside the Exynos7885 SoC, and are needed for the SoC to function correctly. When clocks are cut from TREX D Core, the eMMC and the framebuffer stops working properly. Other unknown things may stop working as well. When clocks are cut from TREX P Core, the system locks up needing a hard reset. Add these clocks and mark them critical so that they are always on. Signed-off-by: David Virag <virag.david003@gmail.com> --- drivers/clk/samsung/clk-exynos7885.c | 49 ++++++++++++++++++++++++---- 1 file changed, 42 insertions(+), 7 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos7885.c b/drivers/clk/samsung/clk-exynos7885.c index 302937025409..0d2a950ed184 100644 --- a/drivers/clk/samsung/clk-exynos7885.c +++ b/drivers/clk/samsung/clk-exynos7885.c @@ -571,13 +571,20 @@ CLK_OF_DECLARE(exynos7885_cmu_peri, "samsung,exynos7885-cmu-peri", /* ---- CMU_CORE ------------------------------------------------------------ */ /* Register Offset definitions for CMU_CORE (0x12000000) */ -#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0100 -#define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0120 -#define PLL_CON0_MUX_CLKCMU_CORE_G3D_USER 0x0140 -#define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000 -#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 -#define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2054 -#define CLK_CON_GAT_GOUT_CORE_GIC400_CLK 0x2058 +#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0100 +#define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0120 +#define PLL_CON0_MUX_CLKCMU_CORE_G3D_USER 0x0140 +#define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000 +#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 +#define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2054 +#define CLK_CON_GAT_GOUT_CORE_GIC400_CLK 0x2058 +#define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK 0x215c +#define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK 0x2160 +#define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK 0x2164 +#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE 0x2168 +#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE 0x216c +#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK 0x2170 +#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE 0x2174 static const unsigned long core_clk_regs[] __initconst = { PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, @@ -587,6 +594,13 @@ static const unsigned long core_clk_regs[] __initconst = { CLK_CON_DIV_DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, CLK_CON_GAT_GOUT_CORE_GIC400_CLK, + CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK, + CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK, + CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK, + CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE, + CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE, + CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK, + CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE, }; /* List of parent clocks for Muxes in CMU_CORE */ @@ -618,6 +632,27 @@ static const struct samsung_gate_clock core_gate_clks[] __initconst = { /* GIC (interrupt controller) clock must be always running */ GATE(CLK_GOUT_GIC400_CLK, "gout_gic400_clk", "mout_core_gic", CLK_CON_GAT_GOUT_CORE_GIC400_CLK, 21, CLK_IS_CRITICAL, 0), + /* + * TREX D and P Core (seems to be related to "bus traffic shaper") + * clocks must always be running + */ + GATE(CLK_GOUT_TREX_D_CORE_ACLK, "gout_trex_d_core_aclk", "mout_core_bus_user", + CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK, 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_TREX_D_CORE_GCLK, "gout_trex_d_core_gclk", "mout_core_g3d_user", + CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK, 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_TREX_D_CORE_PCLK, "gout_trex_d_core_pclk", "dout_core_busp", + CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK, 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_TREX_P_CORE_ACLK_P_CORE, "gout_trex_p_core_aclk_p_core", + "mout_core_bus_user", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE, 21, + CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_TREX_P_CORE_CCLK_P_CORE, "gout_trex_p_core_cclk_p_core", + "mout_core_cci_user", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE, 21, + CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_TREX_P_CORE_PCLK, "gout_trex_p_core_pclk", "dout_core_busp", + CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK, 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_TREX_P_CORE_PCLK_P_CORE, "gout_trex_p_core_pclk_p_core", + "dout_core_busp", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE, 21, + CLK_IS_CRITICAL, 0), }; static const struct samsung_cmu_info core_cmu_info __initconst = { -- 2.36.1 ^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 4/5] clk: samsung: exynos7885: Add TREX clocks @ 2022-06-01 23:37 ` David Virag 0 siblings, 0 replies; 38+ messages in thread From: David Virag @ 2022-06-01 23:37 UTC (permalink / raw) Cc: phone-devel, David Virag, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel TREX D Core and P core clocks seem to be related to the BTS (Bus Traffic Shaper) inside the Exynos7885 SoC, and are needed for the SoC to function correctly. When clocks are cut from TREX D Core, the eMMC and the framebuffer stops working properly. Other unknown things may stop working as well. When clocks are cut from TREX P Core, the system locks up needing a hard reset. Add these clocks and mark them critical so that they are always on. Signed-off-by: David Virag <virag.david003@gmail.com> --- drivers/clk/samsung/clk-exynos7885.c | 49 ++++++++++++++++++++++++---- 1 file changed, 42 insertions(+), 7 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos7885.c b/drivers/clk/samsung/clk-exynos7885.c index 302937025409..0d2a950ed184 100644 --- a/drivers/clk/samsung/clk-exynos7885.c +++ b/drivers/clk/samsung/clk-exynos7885.c @@ -571,13 +571,20 @@ CLK_OF_DECLARE(exynos7885_cmu_peri, "samsung,exynos7885-cmu-peri", /* ---- CMU_CORE ------------------------------------------------------------ */ /* Register Offset definitions for CMU_CORE (0x12000000) */ -#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0100 -#define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0120 -#define PLL_CON0_MUX_CLKCMU_CORE_G3D_USER 0x0140 -#define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000 -#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 -#define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2054 -#define CLK_CON_GAT_GOUT_CORE_GIC400_CLK 0x2058 +#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0100 +#define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0120 +#define PLL_CON0_MUX_CLKCMU_CORE_G3D_USER 0x0140 +#define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000 +#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 +#define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2054 +#define CLK_CON_GAT_GOUT_CORE_GIC400_CLK 0x2058 +#define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK 0x215c +#define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK 0x2160 +#define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK 0x2164 +#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE 0x2168 +#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE 0x216c +#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK 0x2170 +#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE 0x2174 static const unsigned long core_clk_regs[] __initconst = { PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, @@ -587,6 +594,13 @@ static const unsigned long core_clk_regs[] __initconst = { CLK_CON_DIV_DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, CLK_CON_GAT_GOUT_CORE_GIC400_CLK, + CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK, + CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK, + CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK, + CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE, + CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE, + CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK, + CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE, }; /* List of parent clocks for Muxes in CMU_CORE */ @@ -618,6 +632,27 @@ static const struct samsung_gate_clock core_gate_clks[] __initconst = { /* GIC (interrupt controller) clock must be always running */ GATE(CLK_GOUT_GIC400_CLK, "gout_gic400_clk", "mout_core_gic", CLK_CON_GAT_GOUT_CORE_GIC400_CLK, 21, CLK_IS_CRITICAL, 0), + /* + * TREX D and P Core (seems to be related to "bus traffic shaper") + * clocks must always be running + */ + GATE(CLK_GOUT_TREX_D_CORE_ACLK, "gout_trex_d_core_aclk", "mout_core_bus_user", + CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK, 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_TREX_D_CORE_GCLK, "gout_trex_d_core_gclk", "mout_core_g3d_user", + CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK, 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_TREX_D_CORE_PCLK, "gout_trex_d_core_pclk", "dout_core_busp", + CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK, 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_TREX_P_CORE_ACLK_P_CORE, "gout_trex_p_core_aclk_p_core", + "mout_core_bus_user", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE, 21, + CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_TREX_P_CORE_CCLK_P_CORE, "gout_trex_p_core_cclk_p_core", + "mout_core_cci_user", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE, 21, + CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_TREX_P_CORE_PCLK, "gout_trex_p_core_pclk", "dout_core_busp", + CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK, 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_TREX_P_CORE_PCLK_P_CORE, "gout_trex_p_core_pclk_p_core", + "dout_core_busp", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE, 21, + CLK_IS_CRITICAL, 0), }; static const struct samsung_cmu_info core_cmu_info __initconst = { -- 2.36.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH 4/5] clk: samsung: exynos7885: Add TREX clocks 2022-06-01 23:37 ` David Virag @ 2022-06-02 11:56 ` Krzysztof Kozlowski -1 siblings, 0 replies; 38+ messages in thread From: Krzysztof Kozlowski @ 2022-06-02 11:56 UTC (permalink / raw) To: David Virag Cc: phone-devel, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On 02/06/2022 01:37, David Virag wrote: > TREX D Core and P core clocks seem to be related to the BTS (Bus Traffic > Shaper) inside the Exynos7885 SoC, and are needed for the SoC to > function correctly. > > When clocks are cut from TREX D Core, the eMMC and the framebuffer stops > working properly. Other unknown things may stop working as well. > > When clocks are cut from TREX P Core, the system locks up needing a hard > reset. > > Add these clocks and mark them critical so that they are always on. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 4/5] clk: samsung: exynos7885: Add TREX clocks @ 2022-06-02 11:56 ` Krzysztof Kozlowski 0 siblings, 0 replies; 38+ messages in thread From: Krzysztof Kozlowski @ 2022-06-02 11:56 UTC (permalink / raw) To: David Virag Cc: phone-devel, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On 02/06/2022 01:37, David Virag wrote: > TREX D Core and P core clocks seem to be related to the BTS (Bus Traffic > Shaper) inside the Exynos7885 SoC, and are needed for the SoC to > function correctly. > > When clocks are cut from TREX D Core, the eMMC and the framebuffer stops > working properly. Other unknown things may stop working as well. > > When clocks are cut from TREX P Core, the system locks up needing a hard > reset. > > Add these clocks and mark them critical so that they are always on. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 5/5] arm64: dts: exynos: Add internal eMMC support to jackpotlte 2022-06-01 23:37 ` David Virag @ 2022-06-01 23:37 ` David Virag -1 siblings, 0 replies; 38+ messages in thread From: David Virag @ 2022-06-01 23:37 UTC (permalink / raw) Cc: phone-devel, David Virag, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel Add the nodes relevant to provide clocks for Exynos7885 eMMC and to support eMMC. eMMC is the internal storage used in the Samsung Galaxy A8 (2018) (jackpotlte), and all other known devices using the Exynos7885 SoC. Signed-off-by: David Virag <virag.david003@gmail.com> --- .../boot/dts/exynos/exynos7885-jackpotlte.dts | 20 ++++++++++++ arch/arm64/boot/dts/exynos/exynos7885.dtsi | 32 +++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts index 4cf9aa25f618..5db9a81ac7bb 100644 --- a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts +++ b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts @@ -60,6 +60,26 @@ power-key { }; }; +&mmc_0 { + status = "okay"; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-highspeed; + non-removable; + mmc-hs400-enhanced-strobe; + card-detect-delay = <200>; + clock-frequency = <800000000>; + bus-width = <8>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <2 4>; + samsung,dw-mshc-hs400-timing = <0 2>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk_fast_slew_rate_3x &sd0_cmd &sd0_rdqs + &sd0_bus1 &sd0_bus4 &sd0_bus8>; +}; + &oscclk { clock-frequency = <26000000>; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi index 9c233c56558c..23c2e0bb0a2c 100644 --- a/arch/arm64/boot/dts/exynos/exynos7885.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi @@ -240,6 +240,25 @@ cmu_top: clock-controller@12060000 { clock-names = "oscclk"; }; + cmu_fsys: clock-controller@13400000 { + compatible = "samsung,exynos7885-cmu-fsys"; + reg = <0x13400000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_FSYS_BUS>, + <&cmu_top CLK_DOUT_FSYS_MMC_CARD>, + <&cmu_top CLK_DOUT_FSYS_MMC_EMBD>, + <&cmu_top CLK_DOUT_FSYS_MMC_SDIO>, + <&cmu_top CLK_DOUT_FSYS_USB30DRD>; + clock-names = "oscclk", + "dout_fsys_bus", + "dout_fsys_mmc_card", + "dout_fsys_mmc_embd", + "dout_fsys_mmc_sdio", + "dout_fsys_usb30drd"; + }; + pinctrl_alive: pinctrl@11cb0000 { compatible = "samsung,exynos7885-pinctrl"; reg = <0x11cb0000 0x1000>; @@ -274,6 +293,19 @@ pmu_system_controller: system-controller@11c80000 { reg = <0x11c80000 0x10000>; }; + mmc_0: mmc@13500000 { + compatible = "samsung,exynos7-dw-mshc-smu"; + reg = <0x13500000 0x2000>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_fsys CLK_GOUT_MMC_EMBD_ACLK>, + <&cmu_fsys CLK_GOUT_MMC_EMBD_SDCLKIN>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + serial_0: serial@13800000 { compatible = "samsung,exynos5433-uart"; reg = <0x13800000 0x100>; -- 2.36.1 ^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH 5/5] arm64: dts: exynos: Add internal eMMC support to jackpotlte @ 2022-06-01 23:37 ` David Virag 0 siblings, 0 replies; 38+ messages in thread From: David Virag @ 2022-06-01 23:37 UTC (permalink / raw) Cc: phone-devel, David Virag, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel Add the nodes relevant to provide clocks for Exynos7885 eMMC and to support eMMC. eMMC is the internal storage used in the Samsung Galaxy A8 (2018) (jackpotlte), and all other known devices using the Exynos7885 SoC. Signed-off-by: David Virag <virag.david003@gmail.com> --- .../boot/dts/exynos/exynos7885-jackpotlte.dts | 20 ++++++++++++ arch/arm64/boot/dts/exynos/exynos7885.dtsi | 32 +++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts index 4cf9aa25f618..5db9a81ac7bb 100644 --- a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts +++ b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts @@ -60,6 +60,26 @@ power-key { }; }; +&mmc_0 { + status = "okay"; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-highspeed; + non-removable; + mmc-hs400-enhanced-strobe; + card-detect-delay = <200>; + clock-frequency = <800000000>; + bus-width = <8>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <2 4>; + samsung,dw-mshc-hs400-timing = <0 2>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk_fast_slew_rate_3x &sd0_cmd &sd0_rdqs + &sd0_bus1 &sd0_bus4 &sd0_bus8>; +}; + &oscclk { clock-frequency = <26000000>; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi index 9c233c56558c..23c2e0bb0a2c 100644 --- a/arch/arm64/boot/dts/exynos/exynos7885.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi @@ -240,6 +240,25 @@ cmu_top: clock-controller@12060000 { clock-names = "oscclk"; }; + cmu_fsys: clock-controller@13400000 { + compatible = "samsung,exynos7885-cmu-fsys"; + reg = <0x13400000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_FSYS_BUS>, + <&cmu_top CLK_DOUT_FSYS_MMC_CARD>, + <&cmu_top CLK_DOUT_FSYS_MMC_EMBD>, + <&cmu_top CLK_DOUT_FSYS_MMC_SDIO>, + <&cmu_top CLK_DOUT_FSYS_USB30DRD>; + clock-names = "oscclk", + "dout_fsys_bus", + "dout_fsys_mmc_card", + "dout_fsys_mmc_embd", + "dout_fsys_mmc_sdio", + "dout_fsys_usb30drd"; + }; + pinctrl_alive: pinctrl@11cb0000 { compatible = "samsung,exynos7885-pinctrl"; reg = <0x11cb0000 0x1000>; @@ -274,6 +293,19 @@ pmu_system_controller: system-controller@11c80000 { reg = <0x11c80000 0x10000>; }; + mmc_0: mmc@13500000 { + compatible = "samsung,exynos7-dw-mshc-smu"; + reg = <0x13500000 0x2000>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_fsys CLK_GOUT_MMC_EMBD_ACLK>, + <&cmu_fsys CLK_GOUT_MMC_EMBD_SDCLKIN>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + serial_0: serial@13800000 { compatible = "samsung,exynos5433-uart"; reg = <0x13800000 0x100>; -- 2.36.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH 5/5] arm64: dts: exynos: Add internal eMMC support to jackpotlte 2022-06-01 23:37 ` David Virag @ 2022-06-02 12:01 ` Krzysztof Kozlowski -1 siblings, 0 replies; 38+ messages in thread From: Krzysztof Kozlowski @ 2022-06-02 12:01 UTC (permalink / raw) To: David Virag Cc: phone-devel, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On 02/06/2022 01:37, David Virag wrote: > Add the nodes relevant to provide clocks for Exynos7885 eMMC and to > support eMMC. eMMC is the internal storage used in the Samsung Galaxy A8 > (2018) (jackpotlte), and all other known devices using the Exynos7885 > SoC. > > Signed-off-by: David Virag <virag.david003@gmail.com> > --- > .../boot/dts/exynos/exynos7885-jackpotlte.dts | 20 ++++++++++++ > arch/arm64/boot/dts/exynos/exynos7885.dtsi | 32 +++++++++++++++++++ > 2 files changed, 52 insertions(+) > > diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts > index 4cf9aa25f618..5db9a81ac7bb 100644 > --- a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts > +++ b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts > @@ -60,6 +60,26 @@ power-key { > }; > }; > > +&mmc_0 { > + status = "okay"; > + mmc-hs200-1_8v; > + mmc-hs400-1_8v; > + cap-mmc-highspeed; > + non-removable; > + mmc-hs400-enhanced-strobe; > + card-detect-delay = <200>; > + clock-frequency = <800000000>; Is this real property for MMC? Neither mmc nor DW MSHC bindings mention it. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 5/5] arm64: dts: exynos: Add internal eMMC support to jackpotlte @ 2022-06-02 12:01 ` Krzysztof Kozlowski 0 siblings, 0 replies; 38+ messages in thread From: Krzysztof Kozlowski @ 2022-06-02 12:01 UTC (permalink / raw) To: David Virag Cc: phone-devel, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On 02/06/2022 01:37, David Virag wrote: > Add the nodes relevant to provide clocks for Exynos7885 eMMC and to > support eMMC. eMMC is the internal storage used in the Samsung Galaxy A8 > (2018) (jackpotlte), and all other known devices using the Exynos7885 > SoC. > > Signed-off-by: David Virag <virag.david003@gmail.com> > --- > .../boot/dts/exynos/exynos7885-jackpotlte.dts | 20 ++++++++++++ > arch/arm64/boot/dts/exynos/exynos7885.dtsi | 32 +++++++++++++++++++ > 2 files changed, 52 insertions(+) > > diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts > index 4cf9aa25f618..5db9a81ac7bb 100644 > --- a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts > +++ b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts > @@ -60,6 +60,26 @@ power-key { > }; > }; > > +&mmc_0 { > + status = "okay"; > + mmc-hs200-1_8v; > + mmc-hs400-1_8v; > + cap-mmc-highspeed; > + non-removable; > + mmc-hs400-enhanced-strobe; > + card-detect-delay = <200>; > + clock-frequency = <800000000>; Is this real property for MMC? Neither mmc nor DW MSHC bindings mention it. Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 5/5] arm64: dts: exynos: Add internal eMMC support to jackpotlte 2022-06-02 12:01 ` Krzysztof Kozlowski @ 2022-06-02 22:18 ` David Virag -1 siblings, 0 replies; 38+ messages in thread From: David Virag @ 2022-06-02 22:18 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: phone-devel, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On Thu, 2022-06-02 at 14:01 +0200, Krzysztof Kozlowski wrote: > On 02/06/2022 01:37, David Virag wrote: > > Add the nodes relevant to provide clocks for Exynos7885 eMMC and to > > support eMMC. eMMC is the internal storage used in the Samsung > > Galaxy A8 > > (2018) (jackpotlte), and all other known devices using the > > Exynos7885 > > SoC. > > > > Signed-off-by: David Virag <virag.david003@gmail.com> > > --- > > .../boot/dts/exynos/exynos7885-jackpotlte.dts | 20 ++++++++++++ > > arch/arm64/boot/dts/exynos/exynos7885.dtsi | 32 > > +++++++++++++++++++ > > 2 files changed, 52 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts > > b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts > > index 4cf9aa25f618..5db9a81ac7bb 100644 > > --- a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts > > +++ b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts > > @@ -60,6 +60,26 @@ power-key { > > }; > > }; > > > > +&mmc_0 { > > + status = "okay"; > > + mmc-hs200-1_8v; > > + mmc-hs400-1_8v; > > + cap-mmc-highspeed; > > + non-removable; > > + mmc-hs400-enhanced-strobe; > > + card-detect-delay = <200>; > > + clock-frequency = <800000000>; > > Is this real property for MMC? Neither mmc nor DW MSHC bindings > mention it. It is, but I don't remember trying without it. Seems like it is not documented then. It is used in dw_mmc.c in the following places: https://github.com/torvalds/linux/blob/master/drivers/mmc/host/dw_mmc.c#L3242-L3243 https://github.com/torvalds/linux/blob/master/drivers/mmc/host/dw_mmc.c#L3306-L3325 The Exynos850 device tree has the same property in it's mmc node. > > Best regards, > Krzysztof Best regards, David ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 5/5] arm64: dts: exynos: Add internal eMMC support to jackpotlte @ 2022-06-02 22:18 ` David Virag 0 siblings, 0 replies; 38+ messages in thread From: David Virag @ 2022-06-02 22:18 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: phone-devel, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On Thu, 2022-06-02 at 14:01 +0200, Krzysztof Kozlowski wrote: > On 02/06/2022 01:37, David Virag wrote: > > Add the nodes relevant to provide clocks for Exynos7885 eMMC and to > > support eMMC. eMMC is the internal storage used in the Samsung > > Galaxy A8 > > (2018) (jackpotlte), and all other known devices using the > > Exynos7885 > > SoC. > > > > Signed-off-by: David Virag <virag.david003@gmail.com> > > --- > > .../boot/dts/exynos/exynos7885-jackpotlte.dts | 20 ++++++++++++ > > arch/arm64/boot/dts/exynos/exynos7885.dtsi | 32 > > +++++++++++++++++++ > > 2 files changed, 52 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts > > b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts > > index 4cf9aa25f618..5db9a81ac7bb 100644 > > --- a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts > > +++ b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts > > @@ -60,6 +60,26 @@ power-key { > > }; > > }; > > > > +&mmc_0 { > > + status = "okay"; > > + mmc-hs200-1_8v; > > + mmc-hs400-1_8v; > > + cap-mmc-highspeed; > > + non-removable; > > + mmc-hs400-enhanced-strobe; > > + card-detect-delay = <200>; > > + clock-frequency = <800000000>; > > Is this real property for MMC? Neither mmc nor DW MSHC bindings > mention it. It is, but I don't remember trying without it. Seems like it is not documented then. It is used in dw_mmc.c in the following places: https://github.com/torvalds/linux/blob/master/drivers/mmc/host/dw_mmc.c#L3242-L3243 https://github.com/torvalds/linux/blob/master/drivers/mmc/host/dw_mmc.c#L3306-L3325 The Exynos850 device tree has the same property in it's mmc node. > > Best regards, > Krzysztof Best regards, David _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 5/5] arm64: dts: exynos: Add internal eMMC support to jackpotlte 2022-06-02 22:18 ` David Virag @ 2022-06-03 7:38 ` Krzysztof Kozlowski -1 siblings, 0 replies; 38+ messages in thread From: Krzysztof Kozlowski @ 2022-06-03 7:38 UTC (permalink / raw) To: David Virag Cc: phone-devel, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On 03/06/2022 00:18, David Virag wrote: > On Thu, 2022-06-02 at 14:01 +0200, Krzysztof Kozlowski wrote: >> On 02/06/2022 01:37, David Virag wrote: >>> Add the nodes relevant to provide clocks for Exynos7885 eMMC and to >>> support eMMC. eMMC is the internal storage used in the Samsung >>> Galaxy A8 >>> (2018) (jackpotlte), and all other known devices using the >>> Exynos7885 >>> SoC. >>> >>> Signed-off-by: David Virag <virag.david003@gmail.com> >>> --- >>> .../boot/dts/exynos/exynos7885-jackpotlte.dts | 20 ++++++++++++ >>> arch/arm64/boot/dts/exynos/exynos7885.dtsi | 32 >>> +++++++++++++++++++ >>> 2 files changed, 52 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts >>> b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts >>> index 4cf9aa25f618..5db9a81ac7bb 100644 >>> --- a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts >>> +++ b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts >>> @@ -60,6 +60,26 @@ power-key { >>> }; >>> }; >>> >>> +&mmc_0 { >>> + status = "okay"; >>> + mmc-hs200-1_8v; >>> + mmc-hs400-1_8v; >>> + cap-mmc-highspeed; >>> + non-removable; >>> + mmc-hs400-enhanced-strobe; >>> + card-detect-delay = <200>; >>> + clock-frequency = <800000000>; >> >> Is this real property for MMC? Neither mmc nor DW MSHC bindings >> mention it. > > It is, but I don't remember trying without it. Seems like it is not > documented then. It is used in dw_mmc.c in the following places: > > https://github.com/torvalds/linux/blob/master/drivers/mmc/host/dw_mmc.c#L3242-L3243 > > https://github.com/torvalds/linux/blob/master/drivers/mmc/host/dw_mmc.c#L3306-L3325 > > The Exynos850 device tree has the same property in it's mmc node. Indeed, it's fine then. I'll check the bindings and convert them to DT schema. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 5/5] arm64: dts: exynos: Add internal eMMC support to jackpotlte @ 2022-06-03 7:38 ` Krzysztof Kozlowski 0 siblings, 0 replies; 38+ messages in thread From: Krzysztof Kozlowski @ 2022-06-03 7:38 UTC (permalink / raw) To: David Virag Cc: phone-devel, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel On 03/06/2022 00:18, David Virag wrote: > On Thu, 2022-06-02 at 14:01 +0200, Krzysztof Kozlowski wrote: >> On 02/06/2022 01:37, David Virag wrote: >>> Add the nodes relevant to provide clocks for Exynos7885 eMMC and to >>> support eMMC. eMMC is the internal storage used in the Samsung >>> Galaxy A8 >>> (2018) (jackpotlte), and all other known devices using the >>> Exynos7885 >>> SoC. >>> >>> Signed-off-by: David Virag <virag.david003@gmail.com> >>> --- >>> .../boot/dts/exynos/exynos7885-jackpotlte.dts | 20 ++++++++++++ >>> arch/arm64/boot/dts/exynos/exynos7885.dtsi | 32 >>> +++++++++++++++++++ >>> 2 files changed, 52 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts >>> b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts >>> index 4cf9aa25f618..5db9a81ac7bb 100644 >>> --- a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts >>> +++ b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts >>> @@ -60,6 +60,26 @@ power-key { >>> }; >>> }; >>> >>> +&mmc_0 { >>> + status = "okay"; >>> + mmc-hs200-1_8v; >>> + mmc-hs400-1_8v; >>> + cap-mmc-highspeed; >>> + non-removable; >>> + mmc-hs400-enhanced-strobe; >>> + card-detect-delay = <200>; >>> + clock-frequency = <800000000>; >> >> Is this real property for MMC? Neither mmc nor DW MSHC bindings >> mention it. > > It is, but I don't remember trying without it. Seems like it is not > documented then. It is used in dw_mmc.c in the following places: > > https://github.com/torvalds/linux/blob/master/drivers/mmc/host/dw_mmc.c#L3242-L3243 > > https://github.com/torvalds/linux/blob/master/drivers/mmc/host/dw_mmc.c#L3306-L3325 > > The Exynos850 device tree has the same property in it's mmc node. Indeed, it's fine then. I'll check the bindings and convert them to DT schema. Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: (subset) [PATCH 5/5] arm64: dts: exynos: Add internal eMMC support to jackpotlte 2022-06-01 23:37 ` David Virag @ 2022-06-20 12:27 ` Krzysztof Kozlowski -1 siblings, 0 replies; 38+ messages in thread From: Krzysztof Kozlowski @ 2022-06-20 12:27 UTC (permalink / raw) To: David Virag Cc: Krzysztof Kozlowski, Stephen Boyd, Krzysztof Kozlowski, devicetree, Tomasz Figa, phone-devel, Sylwester Nawrocki, linux-samsung-soc, linux-clk, Michael Turquette, Alim Akhtar, linux-arm-kernel, Chanwoo Choi, Rob Herring, linux-kernel On Thu, 2 Jun 2022 01:37:43 +0200, David Virag wrote: > Add the nodes relevant to provide clocks for Exynos7885 eMMC and to > support eMMC. eMMC is the internal storage used in the Samsung Galaxy A8 > (2018) (jackpotlte), and all other known devices using the Exynos7885 > SoC. > > Applied, thanks! [5/5] arm64: dts: exynos: Add internal eMMC support to jackpotlte https://git.kernel.org/krzk/linux/c/ced37411d7f597129fecc0c3ca2324f44e33f4c8 Best regards, -- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: (subset) [PATCH 5/5] arm64: dts: exynos: Add internal eMMC support to jackpotlte @ 2022-06-20 12:27 ` Krzysztof Kozlowski 0 siblings, 0 replies; 38+ messages in thread From: Krzysztof Kozlowski @ 2022-06-20 12:27 UTC (permalink / raw) To: David Virag Cc: Krzysztof Kozlowski, Stephen Boyd, Krzysztof Kozlowski, devicetree, Tomasz Figa, phone-devel, Sylwester Nawrocki, linux-samsung-soc, linux-clk, Michael Turquette, Alim Akhtar, linux-arm-kernel, Chanwoo Choi, Rob Herring, linux-kernel On Thu, 2 Jun 2022 01:37:43 +0200, David Virag wrote: > Add the nodes relevant to provide clocks for Exynos7885 eMMC and to > support eMMC. eMMC is the internal storage used in the Samsung Galaxy A8 > (2018) (jackpotlte), and all other known devices using the Exynos7885 > SoC. > > Applied, thanks! [5/5] arm64: dts: exynos: Add internal eMMC support to jackpotlte https://git.kernel.org/krzk/linux/c/ced37411d7f597129fecc0c3ca2324f44e33f4c8 Best regards, -- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 38+ messages in thread
end of thread, other threads:[~2022-06-20 12:30 UTC | newest]
Thread overview: 38+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-01 23:37 [PATCH 0/5] Bring up internal eMMC on Samsung Galaxy A8 (2018) David Virag
2022-06-01 23:37 ` David Virag
2022-06-01 23:37 ` [PATCH 1/5] dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS David Virag
2022-06-01 23:37 ` David Virag
2022-06-02 11:54 ` Krzysztof Kozlowski
2022-06-02 11:54 ` Krzysztof Kozlowski
2022-06-08 15:12 ` Krzysztof Kozlowski
2022-06-08 15:12 ` Krzysztof Kozlowski
2022-06-20 10:31 ` Sylwester Nawrocki
2022-06-20 10:31 ` Sylwester Nawrocki
[not found] ` <CGME20220620102819eucas1p2b03a01c45ca3d0d42ebb9542954f0a4a@eucas1p2.samsung.com>
2022-06-20 10:28 ` Sylwester Nawrocki
2022-06-20 10:28 ` Sylwester Nawrocki
2022-06-20 12:27 ` (subset) " Krzysztof Kozlowski
2022-06-20 12:27 ` Krzysztof Kozlowski
2022-06-01 23:37 ` [PATCH 2/5] dt-bindings: clock: Add indices for Exynos7885 TREX clocks David Virag
2022-06-01 23:37 ` David Virag
2022-06-02 11:55 ` Krzysztof Kozlowski
2022-06-02 11:55 ` Krzysztof Kozlowski
2022-06-20 12:27 ` (subset) " Krzysztof Kozlowski
2022-06-20 12:27 ` Krzysztof Kozlowski
2022-06-01 23:37 ` [PATCH 3/5] clk: samsung: exynos7885: Implement CMU_FSYS domain David Virag
2022-06-01 23:37 ` David Virag
2022-06-02 11:56 ` Krzysztof Kozlowski
2022-06-02 11:56 ` Krzysztof Kozlowski
2022-06-01 23:37 ` [PATCH 4/5] clk: samsung: exynos7885: Add TREX clocks David Virag
2022-06-01 23:37 ` David Virag
2022-06-02 11:56 ` Krzysztof Kozlowski
2022-06-02 11:56 ` Krzysztof Kozlowski
2022-06-01 23:37 ` [PATCH 5/5] arm64: dts: exynos: Add internal eMMC support to jackpotlte David Virag
2022-06-01 23:37 ` David Virag
2022-06-02 12:01 ` Krzysztof Kozlowski
2022-06-02 12:01 ` Krzysztof Kozlowski
2022-06-02 22:18 ` David Virag
2022-06-02 22:18 ` David Virag
2022-06-03 7:38 ` Krzysztof Kozlowski
2022-06-03 7:38 ` Krzysztof Kozlowski
2022-06-20 12:27 ` (subset) " Krzysztof Kozlowski
2022-06-20 12:27 ` Krzysztof Kozlowski
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