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* [PATCH] perf/marvell_cn10k: Fix TAD PMU register offset
@ 2022-06-14 17:13 ` Tanmay Jagdale
  0 siblings, 0 replies; 4+ messages in thread
From: Tanmay Jagdale @ 2022-06-14 17:13 UTC (permalink / raw)
  To: will, mark.rutland
  Cc: linux-arm-kernel, linux-kernel, sgoutham, lcherian, bbhushan2,
	Tanmay Jagdale

The existing offset of TAD_PRF and TAD_PFC registers are incorrect.
Hence, fix with the right register offsets.

Also, drop read of TAD_PRF register in tad_pmu_event_counter_start()
since we don't have to preserve any bit fields and always write
an updated value.

Signed-off-by: Tanmay Jagdale <tanmay@marvell.com>
---
 drivers/perf/marvell_cn10k_tad_pmu.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/perf/marvell_cn10k_tad_pmu.c b/drivers/perf/marvell_cn10k_tad_pmu.c
index 282d3a071a67..664d49d5979e 100644
--- a/drivers/perf/marvell_cn10k_tad_pmu.c
+++ b/drivers/perf/marvell_cn10k_tad_pmu.c
@@ -18,9 +18,9 @@
 #include <linux/perf_event.h>
 #include <linux/platform_device.h>
 
-#define TAD_PFC_OFFSET		0x0
+#define TAD_PFC_OFFSET		0x800
 #define TAD_PFC(counter)	(TAD_PFC_OFFSET | (counter << 3))
-#define TAD_PRF_OFFSET		0x100
+#define TAD_PRF_OFFSET		0x900
 #define TAD_PRF(counter)	(TAD_PRF_OFFSET | (counter << 3))
 #define TAD_PRF_CNTSEL_MASK	0xFF
 #define TAD_MAX_COUNTERS	8
@@ -100,9 +100,7 @@ static void tad_pmu_event_counter_start(struct perf_event *event, int flags)
 	 * which sets TAD()_PRF()[CNTSEL] != 0
 	 */
 	for (i = 0; i < tad_pmu->region_cnt; i++) {
-		reg_val = readq_relaxed(tad_pmu->regions[i].base +
-					TAD_PRF(counter_idx));
-		reg_val |= (event_idx & 0xFF);
+		reg_val = event_idx & 0xFF;
 		writeq_relaxed(reg_val,	tad_pmu->regions[i].base +
 			       TAD_PRF(counter_idx));
 	}
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [PATCH] perf/marvell_cn10k: Fix TAD PMU register offset
@ 2022-06-14 17:13 ` Tanmay Jagdale
  0 siblings, 0 replies; 4+ messages in thread
From: Tanmay Jagdale @ 2022-06-14 17:13 UTC (permalink / raw)
  To: will, mark.rutland
  Cc: linux-arm-kernel, linux-kernel, sgoutham, lcherian, bbhushan2,
	Tanmay Jagdale

The existing offset of TAD_PRF and TAD_PFC registers are incorrect.
Hence, fix with the right register offsets.

Also, drop read of TAD_PRF register in tad_pmu_event_counter_start()
since we don't have to preserve any bit fields and always write
an updated value.

Signed-off-by: Tanmay Jagdale <tanmay@marvell.com>
---
 drivers/perf/marvell_cn10k_tad_pmu.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/perf/marvell_cn10k_tad_pmu.c b/drivers/perf/marvell_cn10k_tad_pmu.c
index 282d3a071a67..664d49d5979e 100644
--- a/drivers/perf/marvell_cn10k_tad_pmu.c
+++ b/drivers/perf/marvell_cn10k_tad_pmu.c
@@ -18,9 +18,9 @@
 #include <linux/perf_event.h>
 #include <linux/platform_device.h>
 
-#define TAD_PFC_OFFSET		0x0
+#define TAD_PFC_OFFSET		0x800
 #define TAD_PFC(counter)	(TAD_PFC_OFFSET | (counter << 3))
-#define TAD_PRF_OFFSET		0x100
+#define TAD_PRF_OFFSET		0x900
 #define TAD_PRF(counter)	(TAD_PRF_OFFSET | (counter << 3))
 #define TAD_PRF_CNTSEL_MASK	0xFF
 #define TAD_MAX_COUNTERS	8
@@ -100,9 +100,7 @@ static void tad_pmu_event_counter_start(struct perf_event *event, int flags)
 	 * which sets TAD()_PRF()[CNTSEL] != 0
 	 */
 	for (i = 0; i < tad_pmu->region_cnt; i++) {
-		reg_val = readq_relaxed(tad_pmu->regions[i].base +
-					TAD_PRF(counter_idx));
-		reg_val |= (event_idx & 0xFF);
+		reg_val = event_idx & 0xFF;
 		writeq_relaxed(reg_val,	tad_pmu->regions[i].base +
 			       TAD_PRF(counter_idx));
 	}
-- 
2.34.1


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linux-arm-kernel mailing list
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [PATCH] perf/marvell_cn10k: Fix TAD PMU register offset
  2022-06-14 17:13 ` Tanmay Jagdale
@ 2022-06-24 17:14   ` Will Deacon
  -1 siblings, 0 replies; 4+ messages in thread
From: Will Deacon @ 2022-06-24 17:14 UTC (permalink / raw)
  To: Tanmay Jagdale, mark.rutland
  Cc: catalin.marinas, kernel-team, Will Deacon, linux-kernel,
	lcherian, sgoutham, linux-arm-kernel, bbhushan2

On Tue, 14 Jun 2022 17:13:56 +0000, Tanmay Jagdale wrote:
> The existing offset of TAD_PRF and TAD_PFC registers are incorrect.
> Hence, fix with the right register offsets.
> 
> Also, drop read of TAD_PRF register in tad_pmu_event_counter_start()
> since we don't have to preserve any bit fields and always write
> an updated value.
> 
> [...]

Applied to will (for-next/perf), thanks!

[1/1] perf/marvell_cn10k: Fix TAD PMU register offset
      https://git.kernel.org/will/c/f5ebeb138fa6

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev

^ permalink raw reply	[flat|nested] 4+ messages in thread
* Re: [PATCH] perf/marvell_cn10k: Fix TAD PMU register offset
@ 2022-06-24 17:14   ` Will Deacon
  0 siblings, 0 replies; 4+ messages in thread
From: Will Deacon @ 2022-06-24 17:14 UTC (permalink / raw)
  To: Tanmay Jagdale, mark.rutland
  Cc: catalin.marinas, kernel-team, Will Deacon, linux-kernel,
	lcherian, sgoutham, linux-arm-kernel, bbhushan2

On Tue, 14 Jun 2022 17:13:56 +0000, Tanmay Jagdale wrote:
> The existing offset of TAD_PRF and TAD_PFC registers are incorrect.
> Hence, fix with the right register offsets.
> 
> Also, drop read of TAD_PRF register in tad_pmu_event_counter_start()
> since we don't have to preserve any bit fields and always write
> an updated value.
> 
> [...]

Applied to will (for-next/perf), thanks!

[1/1] perf/marvell_cn10k: Fix TAD PMU register offset
      https://git.kernel.org/will/c/f5ebeb138fa6

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-06-24 17:15 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-14 17:13 [PATCH] perf/marvell_cn10k: Fix TAD PMU register offset Tanmay Jagdale
2022-06-14 17:13 ` Tanmay Jagdale
2022-06-24 17:14 ` Will Deacon
2022-06-24 17:14   ` Will Deacon

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