* [Intel-gfx] [PATCH 0/9] drm/i915: Display info cleanup
@ 2022-06-23 13:08 Ville Syrjala
2022-06-23 13:08 ` [Intel-gfx] [PATCH 1/9] drm/i915: Move dbuf details to INTEL_INFO->display Ville Syrjala
` (13 more replies)
0 siblings, 14 replies; 16+ messages in thread
From: Ville Syrjala @ 2022-06-23 13:08 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Collect more stuff under INTEL_INFO->display, and clean up
some messy stuff in the related register macros.
Ville Syrjälä (9):
drm/i915: Move dbuf details to INTEL_INFO->display
drm/i195: Move pipe_offsets[] & co. to INTEL_INFO->display
drm/i915: Move display_mmio_offset under INTEL_INFO->display
drm/i915: Make pipe_offsets[] & co. u32
drm/i915: s/_CURSOR2/_MMIO_CURSOR2//
drm/i915: Use _MMIO_TRANS2() where appropriate
drm/i915: Use _MMIO_PIPE2() where appropriate
drm/i915: Get rid of XE_LPD_CURSOR_OFFSETS
drm/i915: Move the color stuff under INTEL_INFO->display
drivers/gpu/drm/i915/display/intel_color.c | 28 ++---
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
.../drm/i915/display/intel_display_power.c | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 112 +++++++++---------
drivers/gpu/drm/i915/i915_reg.h | 47 ++++----
drivers/gpu/drm/i915/intel_device_info.h | 39 +++---
drivers/gpu/drm/i915/intel_pm.c | 8 +-
7 files changed, 117 insertions(+), 121 deletions(-)
--
2.35.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 1/9] drm/i915: Move dbuf details to INTEL_INFO->display
2022-06-23 13:08 [Intel-gfx] [PATCH 0/9] drm/i915: Display info cleanup Ville Syrjala
@ 2022-06-23 13:08 ` Ville Syrjala
2022-06-23 13:08 ` [Intel-gfx] [PATCH 2/9] drm/i195: Move pipe_offsets[] & co. " Ville Syrjala
` (12 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjala @ 2022-06-23 13:08 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
DBUF is a display thing, so move it into the display
portion of the device info.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
.../gpu/drm/i915/display/intel_display_power.c | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 18 +++++++++---------
drivers/gpu/drm/i915/intel_device_info.h | 9 +++++----
drivers/gpu/drm/i915/intel_pm.c | 8 ++++----
5 files changed, 20 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 8610e17cc593..c896c1070211 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -193,7 +193,7 @@ enum plane_id {
#define for_each_dbuf_slice(__dev_priv, __slice) \
for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
- for_each_if(INTEL_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
+ for_each_if(INTEL_INFO(__dev_priv)->display.dbuf.slice_mask & BIT(__slice))
#define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
for_each_dbuf_slice((__dev_priv), (__slice)) \
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index fb17439bd4f8..a9cb27f1c964 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1038,7 +1038,7 @@ void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
- u8 slice_mask = INTEL_INFO(dev_priv)->dbuf.slice_mask;
+ u8 slice_mask = INTEL_INFO(dev_priv)->display.dbuf.slice_mask;
enum dbuf_slice slice;
drm_WARN(&dev_priv->drm, req_slices & ~slice_mask,
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 5e51fc29bb8b..212a958fd8bd 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -656,8 +656,8 @@ static const struct intel_device_info chv_info = {
.display.has_ipc = 1, \
.display.has_psr = 1, \
.display.has_psr_hw_tracking = 1, \
- .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
- .dbuf.slice_mask = BIT(DBUF_S1)
+ .display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
+ .display.dbuf.slice_mask = BIT(DBUF_S1)
#define SKL_PLATFORM \
GEN9_FEATURES, \
@@ -692,7 +692,7 @@ static const struct intel_device_info skl_gt4_info = {
#define GEN9_LP_FEATURES \
GEN(9), \
.is_lp = 1, \
- .dbuf.slice_mask = BIT(DBUF_S1), \
+ .display.dbuf.slice_mask = BIT(DBUF_S1), \
.display.has_hotplug = 1, \
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
@@ -730,14 +730,14 @@ static const struct intel_device_info skl_gt4_info = {
static const struct intel_device_info bxt_info = {
GEN9_LP_FEATURES,
PLATFORM(INTEL_BROXTON),
- .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
+ .display.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
};
static const struct intel_device_info glk_info = {
GEN9_LP_FEATURES,
PLATFORM(INTEL_GEMINILAKE),
.display.ver = 10,
- .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
+ .display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
GLK_COLORS,
};
@@ -827,8 +827,8 @@ static const struct intel_device_info cml_gt2_info = {
}, \
GEN(11), \
ICL_COLORS, \
- .dbuf.size = 2048, \
- .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
+ .display.dbuf.size = 2048, \
+ .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
.display.has_dsc = 1, \
.has_coherent_ggtt = false, \
.has_logical_ring_elsq = 1
@@ -951,8 +951,8 @@ static const struct intel_device_info adl_s_info = {
.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
DRM_COLOR_LUT_EQUAL_CHANNELS, \
}, \
- .dbuf.size = 4096, \
- .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
+ .display.dbuf.size = 4096, \
+ .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
BIT(DBUF_S4), \
.display.has_ddi = 1, \
.display.has_dmc = 1, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 08341174ee0a..a5f0e5eac6a6 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -231,15 +231,16 @@ struct intel_device_info {
u8 fbc_mask;
u8 abox_mask;
+ struct {
+ u16 size; /* in blocks */
+ u8 slice_mask;
+ } dbuf;
+
#define DEFINE_FLAG(name) u8 name:1
DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
} display;
- struct {
- u16 size; /* in blocks */
- u8 slice_mask;
- } dbuf;
/* Register offsets for the various display pipes and transcoders */
int pipe_offsets[I915_MAX_TRANSCODERS];
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9b7e93ca1ff9..f06babdb3a8c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4101,8 +4101,8 @@ static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry,
static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv)
{
- return INTEL_INFO(dev_priv)->dbuf.size /
- hweight8(INTEL_INFO(dev_priv)->dbuf.slice_mask);
+ return INTEL_INFO(dev_priv)->display.dbuf.size /
+ hweight8(INTEL_INFO(dev_priv)->display.dbuf.slice_mask);
}
static void
@@ -4121,7 +4121,7 @@ skl_ddb_entry_for_slices(struct drm_i915_private *dev_priv, u8 slice_mask,
ddb->end = fls(slice_mask) * slice_size;
WARN_ON(ddb->start >= ddb->end);
- WARN_ON(ddb->end > INTEL_INFO(dev_priv)->dbuf.size);
+ WARN_ON(ddb->end > INTEL_INFO(dev_priv)->display.dbuf.size);
}
static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask)
@@ -6096,7 +6096,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
"Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
old_dbuf_state->enabled_slices,
new_dbuf_state->enabled_slices,
- INTEL_INFO(dev_priv)->dbuf.slice_mask,
+ INTEL_INFO(dev_priv)->display.dbuf.slice_mask,
str_yes_no(old_dbuf_state->joined_mbus),
str_yes_no(new_dbuf_state->joined_mbus));
}
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 2/9] drm/i195: Move pipe_offsets[] & co. to INTEL_INFO->display
2022-06-23 13:08 [Intel-gfx] [PATCH 0/9] drm/i915: Display info cleanup Ville Syrjala
2022-06-23 13:08 ` [Intel-gfx] [PATCH 1/9] drm/i915: Move dbuf details to INTEL_INFO->display Ville Syrjala
@ 2022-06-23 13:08 ` Ville Syrjala
2022-06-23 13:08 ` [Intel-gfx] [PATCH 3/9] drm/i915: Move display_mmio_offset under INTEL_INFO->display Ville Syrjala
` (11 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjala @ 2022-06-23 13:08 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The display register offsets are display stuff so stick
into the display portion of the device info.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 44 ++++++++++++------------
drivers/gpu/drm/i915/i915_reg.h | 18 +++++-----
drivers/gpu/drm/i915/intel_device_info.h | 10 +++---
3 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 212a958fd8bd..50dd46981e86 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -38,43 +38,43 @@
.display.ver = (x)
#define I845_PIPE_OFFSETS \
- .pipe_offsets = { \
+ .display.pipe_offsets = { \
[TRANSCODER_A] = PIPE_A_OFFSET, \
}, \
- .trans_offsets = { \
+ .display.trans_offsets = { \
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
}
#define I9XX_PIPE_OFFSETS \
- .pipe_offsets = { \
+ .display.pipe_offsets = { \
[TRANSCODER_A] = PIPE_A_OFFSET, \
[TRANSCODER_B] = PIPE_B_OFFSET, \
}, \
- .trans_offsets = { \
+ .display.trans_offsets = { \
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
}
#define IVB_PIPE_OFFSETS \
- .pipe_offsets = { \
+ .display.pipe_offsets = { \
[TRANSCODER_A] = PIPE_A_OFFSET, \
[TRANSCODER_B] = PIPE_B_OFFSET, \
[TRANSCODER_C] = PIPE_C_OFFSET, \
}, \
- .trans_offsets = { \
+ .display.trans_offsets = { \
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
}
#define HSW_PIPE_OFFSETS \
- .pipe_offsets = { \
+ .display.pipe_offsets = { \
[TRANSCODER_A] = PIPE_A_OFFSET, \
[TRANSCODER_B] = PIPE_B_OFFSET, \
[TRANSCODER_C] = PIPE_C_OFFSET, \
[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
}, \
- .trans_offsets = { \
+ .display.trans_offsets = { \
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
@@ -82,44 +82,44 @@
}
#define CHV_PIPE_OFFSETS \
- .pipe_offsets = { \
+ .display.pipe_offsets = { \
[TRANSCODER_A] = PIPE_A_OFFSET, \
[TRANSCODER_B] = PIPE_B_OFFSET, \
[TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
}, \
- .trans_offsets = { \
+ .display.trans_offsets = { \
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
[TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
}
#define I845_CURSOR_OFFSETS \
- .cursor_offsets = { \
+ .display.cursor_offsets = { \
[PIPE_A] = CURSOR_A_OFFSET, \
}
#define I9XX_CURSOR_OFFSETS \
- .cursor_offsets = { \
+ .display.cursor_offsets = { \
[PIPE_A] = CURSOR_A_OFFSET, \
[PIPE_B] = CURSOR_B_OFFSET, \
}
#define CHV_CURSOR_OFFSETS \
- .cursor_offsets = { \
+ .display.cursor_offsets = { \
[PIPE_A] = CURSOR_A_OFFSET, \
[PIPE_B] = CURSOR_B_OFFSET, \
[PIPE_C] = CHV_CURSOR_C_OFFSET, \
}
#define IVB_CURSOR_OFFSETS \
- .cursor_offsets = { \
+ .display.cursor_offsets = { \
[PIPE_A] = CURSOR_A_OFFSET, \
[PIPE_B] = IVB_CURSOR_B_OFFSET, \
[PIPE_C] = IVB_CURSOR_C_OFFSET, \
}
#define TGL_CURSOR_OFFSETS \
- .cursor_offsets = { \
+ .display.cursor_offsets = { \
[PIPE_A] = CURSOR_A_OFFSET, \
[PIPE_B] = IVB_CURSOR_B_OFFSET, \
[PIPE_C] = IVB_CURSOR_C_OFFSET, \
@@ -809,7 +809,7 @@ static const struct intel_device_info cml_gt2_info = {
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
- .pipe_offsets = { \
+ .display.pipe_offsets = { \
[TRANSCODER_A] = PIPE_A_OFFSET, \
[TRANSCODER_B] = PIPE_B_OFFSET, \
[TRANSCODER_C] = PIPE_C_OFFSET, \
@@ -817,7 +817,7 @@ static const struct intel_device_info cml_gt2_info = {
[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
}, \
- .trans_offsets = { \
+ .display.trans_offsets = { \
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
@@ -862,7 +862,7 @@ static const struct intel_device_info jsl_info = {
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
- .pipe_offsets = { \
+ .display.pipe_offsets = { \
[TRANSCODER_A] = PIPE_A_OFFSET, \
[TRANSCODER_B] = PIPE_B_OFFSET, \
[TRANSCODER_C] = PIPE_C_OFFSET, \
@@ -870,7 +870,7 @@ static const struct intel_device_info jsl_info = {
[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
}, \
- .trans_offsets = { \
+ .display.trans_offsets = { \
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
@@ -938,7 +938,7 @@ static const struct intel_device_info adl_s_info = {
};
#define XE_LPD_CURSOR_OFFSETS \
- .cursor_offsets = { \
+ .display.cursor_offsets = { \
[PIPE_A] = CURSOR_A_OFFSET, \
[PIPE_B] = IVB_CURSOR_B_OFFSET, \
[PIPE_C] = IVB_CURSOR_C_OFFSET, \
@@ -967,7 +967,7 @@ static const struct intel_device_info adl_s_info = {
.display.has_psr = 1, \
.display.ver = 13, \
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
- .pipe_offsets = { \
+ .display.pipe_offsets = { \
[TRANSCODER_A] = PIPE_A_OFFSET, \
[TRANSCODER_B] = PIPE_B_OFFSET, \
[TRANSCODER_C] = PIPE_C_OFFSET, \
@@ -975,7 +975,7 @@ static const struct intel_device_info adl_s_info = {
[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
}, \
- .trans_offsets = { \
+ .display.trans_offsets = { \
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 932bd6aa4a0a..2ef3bd20e3b9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -161,16 +161,16 @@
* Device info offset array based helpers for groups of registers with unevenly
* spaced base offsets.
*/
-#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
- INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
- DISPLAY_MMIO_BASE(dev_priv))
-#define _TRANS2(tran, reg) (INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \
- INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
- DISPLAY_MMIO_BASE(dev_priv))
+#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.pipe_offsets[(pipe)] - \
+ INTEL_INFO(dev_priv)->display.pipe_offsets[PIPE_A] + \
+ DISPLAY_MMIO_BASE(dev_priv) + (reg))
+#define _TRANS2(tran, reg) (INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \
+ INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \
+ DISPLAY_MMIO_BASE(dev_priv) + (reg))
#define _MMIO_TRANS2(tran, reg) _MMIO(_TRANS2(tran, reg))
-#define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
- INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
- DISPLAY_MMIO_BASE(dev_priv))
+#define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \
+ INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \
+ DISPLAY_MMIO_BASE(dev_priv) + (reg))
#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
#define _MASKED_FIELD(mask, value) ({ \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index a5f0e5eac6a6..4ca8c83dca59 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -239,14 +239,14 @@ struct intel_device_info {
#define DEFINE_FLAG(name) u8 name:1
DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
+
+ /* Register offsets for the various display pipes and transcoders */
+ int pipe_offsets[I915_MAX_TRANSCODERS];
+ int trans_offsets[I915_MAX_TRANSCODERS];
+ int cursor_offsets[I915_MAX_PIPES];
} display;
- /* Register offsets for the various display pipes and transcoders */
- int pipe_offsets[I915_MAX_TRANSCODERS];
- int trans_offsets[I915_MAX_TRANSCODERS];
- int cursor_offsets[I915_MAX_PIPES];
-
struct color_luts {
u32 degamma_lut_size;
u32 gamma_lut_size;
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 3/9] drm/i915: Move display_mmio_offset under INTEL_INFO->display
2022-06-23 13:08 [Intel-gfx] [PATCH 0/9] drm/i915: Display info cleanup Ville Syrjala
2022-06-23 13:08 ` [Intel-gfx] [PATCH 1/9] drm/i915: Move dbuf details to INTEL_INFO->display Ville Syrjala
2022-06-23 13:08 ` [Intel-gfx] [PATCH 2/9] drm/i195: Move pipe_offsets[] & co. " Ville Syrjala
@ 2022-06-23 13:08 ` Ville Syrjala
2022-06-23 13:08 ` [Intel-gfx] [PATCH 4/9] drm/i915: Make pipe_offsets[] & co. u32 Ville Syrjala
` (10 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjala @ 2022-06-23 13:08 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The display register offsets are display stuff so stick
into the display portion of the device info.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_device_info.h | 5 +++--
3 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 50dd46981e86..b8219733f3b4 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -536,7 +536,7 @@ static const struct intel_device_info vlv_info = {
.has_snoop = true,
.has_coherent_ggtt = false,
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
- .display_mmio_offset = VLV_DISPLAY_BASE,
+ .display.mmio_offset = VLV_DISPLAY_BASE,
I9XX_PIPE_OFFSETS,
I9XX_CURSOR_OFFSETS,
I965_COLORS,
@@ -634,7 +634,7 @@ static const struct intel_device_info chv_info = {
.has_reset_engine = 1,
.has_snoop = true,
.has_coherent_ggtt = false,
- .display_mmio_offset = VLV_DISPLAY_BASE,
+ .display.mmio_offset = VLV_DISPLAY_BASE,
CHV_PIPE_OFFSETS,
CHV_CURSOR_OFFSETS,
CHV_COLORS,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2ef3bd20e3b9..c64cf302ccb7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -115,7 +115,7 @@
* #define GEN8_BAR _MMIO(0xb888)
*/
-#define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset)
+#define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display.mmio_offset)
/*
* Given the first two numbers __a and __b of arbitrarily many evenly spaced
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 4ca8c83dca59..e3b40f5782a4 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -214,8 +214,6 @@ struct intel_device_info {
u32 memory_regions; /* regions supported by the HW */
- u32 display_mmio_offset;
-
u8 gt; /* GT number, 0 if undefined */
#define DEFINE_FLAG(name) u8 name:1
@@ -240,6 +238,9 @@ struct intel_device_info {
DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
+ /* Global register offset for the display engine */
+ u32 mmio_offset;
+
/* Register offsets for the various display pipes and transcoders */
int pipe_offsets[I915_MAX_TRANSCODERS];
int trans_offsets[I915_MAX_TRANSCODERS];
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 4/9] drm/i915: Make pipe_offsets[] & co. u32
2022-06-23 13:08 [Intel-gfx] [PATCH 0/9] drm/i915: Display info cleanup Ville Syrjala
` (2 preceding siblings ...)
2022-06-23 13:08 ` [Intel-gfx] [PATCH 3/9] drm/i915: Move display_mmio_offset under INTEL_INFO->display Ville Syrjala
@ 2022-06-23 13:08 ` Ville Syrjala
2022-06-23 13:08 ` [Intel-gfx] [PATCH 5/9] drm/i915: s/_CURSOR2/_MMIO_CURSOR2// Ville Syrjala
` (9 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjala @ 2022-06-23 13:08 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Using a signed type for the register offsets doesn't really
make sense. Switch to u32.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_device_info.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index e3b40f5782a4..2be7ba78f123 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -242,9 +242,9 @@ struct intel_device_info {
u32 mmio_offset;
/* Register offsets for the various display pipes and transcoders */
- int pipe_offsets[I915_MAX_TRANSCODERS];
- int trans_offsets[I915_MAX_TRANSCODERS];
- int cursor_offsets[I915_MAX_PIPES];
+ u32 pipe_offsets[I915_MAX_TRANSCODERS];
+ u32 trans_offsets[I915_MAX_TRANSCODERS];
+ u32 cursor_offsets[I915_MAX_PIPES];
} display;
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 5/9] drm/i915: s/_CURSOR2/_MMIO_CURSOR2//
2022-06-23 13:08 [Intel-gfx] [PATCH 0/9] drm/i915: Display info cleanup Ville Syrjala
` (3 preceding siblings ...)
2022-06-23 13:08 ` [Intel-gfx] [PATCH 4/9] drm/i915: Make pipe_offsets[] & co. u32 Ville Syrjala
@ 2022-06-23 13:08 ` Ville Syrjala
2022-06-23 13:08 ` [Intel-gfx] [PATCH 6/9] drm/i915: Use _MMIO_TRANS2() where appropriate Ville Syrjala
` (8 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjala @ 2022-06-23 13:08 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The other similar macros have the _MMIO prefix, so give
it also to _CURSOR2.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c64cf302ccb7..b3fe01aaeba8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -168,7 +168,7 @@
INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \
DISPLAY_MMIO_BASE(dev_priv) + (reg))
#define _MMIO_TRANS2(tran, reg) _MMIO(_TRANS2(tran, reg))
-#define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \
+#define _MMIO_CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \
INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \
DISPLAY_MMIO_BASE(dev_priv) + (reg))
@@ -4328,12 +4328,12 @@
#define _CURBBASE_IVB 0x71084
#define _CURBPOS_IVB 0x71088
-#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
-#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
-#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
-#define CURSIZE(pipe) _CURSOR2(pipe, _CURASIZE)
-#define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
-#define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
+#define CURCNTR(pipe) _MMIO_CURSOR2(pipe, _CURACNTR)
+#define CURBASE(pipe) _MMIO_CURSOR2(pipe, _CURABASE)
+#define CURPOS(pipe) _MMIO_CURSOR2(pipe, _CURAPOS)
+#define CURSIZE(pipe) _MMIO_CURSOR2(pipe, _CURASIZE)
+#define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(pipe, _CUR_FBC_CTL_A)
+#define CURSURFLIVE(pipe) _MMIO_CURSOR2(pipe, _CURASURFLIVE)
#define CURSOR_A_OFFSET 0x70080
#define CURSOR_B_OFFSET 0x700c0
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 6/9] drm/i915: Use _MMIO_TRANS2() where appropriate
2022-06-23 13:08 [Intel-gfx] [PATCH 0/9] drm/i915: Display info cleanup Ville Syrjala
` (4 preceding siblings ...)
2022-06-23 13:08 ` [Intel-gfx] [PATCH 5/9] drm/i915: s/_CURSOR2/_MMIO_CURSOR2// Ville Syrjala
@ 2022-06-23 13:08 ` Ville Syrjala
2022-06-23 13:08 ` [Intel-gfx] [PATCH 7/9] drm/i915: Use _MMIO_PIPE2() " Ville Syrjala
` (7 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjala @ 2022-06-23 13:08 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Stop hand rolling _MMIO_TRANS2() and just use the real thing.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 19 +++++++++----------
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b3fe01aaeba8..8bcde74e9217 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -164,10 +164,9 @@
#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.pipe_offsets[(pipe)] - \
INTEL_INFO(dev_priv)->display.pipe_offsets[PIPE_A] + \
DISPLAY_MMIO_BASE(dev_priv) + (reg))
-#define _TRANS2(tran, reg) (INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \
- INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \
- DISPLAY_MMIO_BASE(dev_priv) + (reg))
-#define _MMIO_TRANS2(tran, reg) _MMIO(_TRANS2(tran, reg))
+#define _MMIO_TRANS2(tran, reg) _MMIO(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \
+ INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \
+ DISPLAY_MMIO_BASE(dev_priv) + (reg))
#define _MMIO_CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \
INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \
DISPLAY_MMIO_BASE(dev_priv) + (reg))
@@ -2171,7 +2170,7 @@
*/
#define _SRD_CTL_A 0x60800
#define _SRD_CTL_EDP 0x6f800
-#define EDP_PSR_CTL(tran) _MMIO(_TRANS2(tran, _SRD_CTL_A))
+#define EDP_PSR_CTL(tran) _MMIO_TRANS2(tran, _SRD_CTL_A)
#define EDP_PSR_ENABLE (1 << 31)
#define BDW_PSR_SINGLE_FRAME (1 << 30)
#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */
@@ -2217,11 +2216,11 @@
#define _SRD_AUX_DATA_A 0x60814
#define _SRD_AUX_DATA_EDP 0x6f814
-#define EDP_PSR_AUX_DATA(tran, i) _MMIO(_TRANS2(tran, _SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */
+#define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) + 4) /* 5 registers */
#define _SRD_STATUS_A 0x60840
#define _SRD_STATUS_EDP 0x6f840
-#define EDP_PSR_STATUS(tran) _MMIO(_TRANS2(tran, _SRD_STATUS_A))
+#define EDP_PSR_STATUS(tran) _MMIO_TRANS2(tran, _SRD_STATUS_A)
#define EDP_PSR_STATUS_STATE_MASK (7 << 29)
#define EDP_PSR_STATUS_STATE_SHIFT 29
#define EDP_PSR_STATUS_STATE_IDLE (0 << 29)
@@ -2248,13 +2247,13 @@
#define _SRD_PERF_CNT_A 0x60844
#define _SRD_PERF_CNT_EDP 0x6f844
-#define EDP_PSR_PERF_CNT(tran) _MMIO(_TRANS2(tran, _SRD_PERF_CNT_A))
+#define EDP_PSR_PERF_CNT(tran) _MMIO_TRANS2(tran, _SRD_PERF_CNT_A)
#define EDP_PSR_PERF_CNT_MASK 0xffffff
/* PSR_MASK on SKL+ */
#define _SRD_DEBUG_A 0x60860
#define _SRD_DEBUG_EDP 0x6f860
-#define EDP_PSR_DEBUG(tran) _MMIO(_TRANS2(tran, _SRD_DEBUG_A))
+#define EDP_PSR_DEBUG(tran) _MMIO_TRANS2(tran, _SRD_DEBUG_A)
#define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28)
#define EDP_PSR_DEBUG_MASK_LPSP (1 << 27)
#define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26)
@@ -2329,7 +2328,7 @@
#define _PSR2_SU_STATUS_A 0x60914
#define _PSR2_SU_STATUS_EDP 0x6f914
-#define _PSR2_SU_STATUS(tran, index) _MMIO(_TRANS2(tran, _PSR2_SU_STATUS_A) + (index) * 4)
+#define _PSR2_SU_STATUS(tran, index) _MMIO_TRANS2(tran, _PSR2_SU_STATUS_A + (index) * 4)
#define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3))
#define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10)
#define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 7/9] drm/i915: Use _MMIO_PIPE2() where appropriate
2022-06-23 13:08 [Intel-gfx] [PATCH 0/9] drm/i915: Display info cleanup Ville Syrjala
` (5 preceding siblings ...)
2022-06-23 13:08 ` [Intel-gfx] [PATCH 6/9] drm/i915: Use _MMIO_TRANS2() where appropriate Ville Syrjala
@ 2022-06-23 13:08 ` Ville Syrjala
2022-06-23 13:08 ` [Intel-gfx] [PATCH 8/9] drm/i915: Get rid of XE_LPD_CURSOR_OFFSETS Ville Syrjala
` (6 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjala @ 2022-06-23 13:08 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Stop hand rolling _MMIO_TRANS2() and just use the real thing.
Note that this register isn't even used atm, hence why this
builds despite the _PIPE2() macro not actually existing.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8bcde74e9217..36505c75e6b5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4407,7 +4407,7 @@
#define DSPLINOFF(plane) DSPADDR(plane)
#define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET)
#define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE)
-#define DSPGAMC(plane, i) _MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
+#define DSPGAMC(plane, i) _MMIO_PIPE2(plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
/* CHV pipe B blender and primary plane */
#define _CHV_BLEND_A 0x60a00
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 8/9] drm/i915: Get rid of XE_LPD_CURSOR_OFFSETS
2022-06-23 13:08 [Intel-gfx] [PATCH 0/9] drm/i915: Display info cleanup Ville Syrjala
` (6 preceding siblings ...)
2022-06-23 13:08 ` [Intel-gfx] [PATCH 7/9] drm/i915: Use _MMIO_PIPE2() " Ville Syrjala
@ 2022-06-23 13:08 ` Ville Syrjala
2022-06-23 13:09 ` [Intel-gfx] [PATCH 9/9] drm/i915: Move the color stuff under INTEL_INFO->display Ville Syrjala
` (5 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjala @ 2022-06-23 13:08 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
XE_LPD_CURSOR_OFFSETS is a duplicate of TGL_CURSOR_OFFSETS.
Just use the latter.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 10 +---------
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b8219733f3b4..7bc944271371 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -937,14 +937,6 @@ static const struct intel_device_info adl_s_info = {
.dma_mask_size = 39,
};
-#define XE_LPD_CURSOR_OFFSETS \
- .display.cursor_offsets = { \
- [PIPE_A] = CURSOR_A_OFFSET, \
- [PIPE_B] = IVB_CURSOR_B_OFFSET, \
- [PIPE_C] = IVB_CURSOR_C_OFFSET, \
- [PIPE_D] = TGL_CURSOR_D_OFFSET, \
- }
-
#define XE_LPD_FEATURES \
.display.abox_mask = GENMASK(1, 0), \
.color = { .degamma_lut_size = 128, .gamma_lut_size = 1024, \
@@ -983,7 +975,7 @@ static const struct intel_device_info adl_s_info = {
[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
}, \
- XE_LPD_CURSOR_OFFSETS
+ TGL_CURSOR_OFFSETS
static const struct intel_device_info adl_p_info = {
GEN12_FEATURES,
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 9/9] drm/i915: Move the color stuff under INTEL_INFO->display
2022-06-23 13:08 [Intel-gfx] [PATCH 0/9] drm/i915: Display info cleanup Ville Syrjala
` (7 preceding siblings ...)
2022-06-23 13:08 ` [Intel-gfx] [PATCH 8/9] drm/i915: Get rid of XE_LPD_CURSOR_OFFSETS Ville Syrjala
@ 2022-06-23 13:09 ` Ville Syrjala
2022-06-23 14:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Display info cleanup Patchwork
` (4 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjala @ 2022-06-23 13:09 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The LUTs are a display feature so move the details into
the display portion of the device info.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 28 ++++++++--------
drivers/gpu/drm/i915/i915_pci.c | 38 ++++++++++++----------
drivers/gpu/drm/i915/intel_device_info.h | 15 ++++-----
3 files changed, 42 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index a27ce874a9e8..194b0a9f2efe 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -852,7 +852,7 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
- int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
+ int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;
const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
/*
@@ -894,7 +894,7 @@ static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_stat
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
- int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
+ int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;
/*
* When setting the auto-increment bit, the hardware seems to
@@ -1346,10 +1346,10 @@ static int check_luts(const struct intel_crtc_state *crtc_state)
return -EINVAL;
}
- degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
- gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
- degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests;
- gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests;
+ degamma_length = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;
+ gamma_length = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
+ degamma_tests = INTEL_INFO(dev_priv)->display.color.degamma_lut_tests;
+ gamma_tests = INTEL_INFO(dev_priv)->display.color.gamma_lut_tests;
if (check_lut_size(degamma_lut, degamma_length) ||
check_lut_size(gamma_lut, gamma_length))
@@ -1885,7 +1885,7 @@ static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
struct drm_color_lut *lut;
@@ -1928,7 +1928,7 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
struct drm_color_lut *lut;
@@ -1989,7 +1989,7 @@ static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
struct drm_color_lut *lut;
@@ -2040,7 +2040,7 @@ static struct drm_property_blob *bdw_read_lut_10(struct intel_crtc *crtc,
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
int i, hw_lut_size = ivb_lut_10_size(prec_index);
- int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ int lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
struct drm_color_lut *lut;
@@ -2093,7 +2093,7 @@ static struct drm_property_blob *
icl_read_lut_multi_segment(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
struct drm_color_lut *lut;
@@ -2230,7 +2230,7 @@ static const struct intel_color_funcs ilk_color_funcs = {
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- bool has_ctm = INTEL_INFO(dev_priv)->color.degamma_lut_size != 0;
+ bool has_ctm = INTEL_INFO(dev_priv)->display.color.degamma_lut_size != 0;
drm_mode_crtc_set_gamma_size(&crtc->base, 256);
@@ -2261,7 +2261,7 @@ void intel_color_init(struct intel_crtc *crtc)
}
drm_crtc_enable_color_mgmt(&crtc->base,
- INTEL_INFO(dev_priv)->color.degamma_lut_size,
+ INTEL_INFO(dev_priv)->display.color.degamma_lut_size,
has_ctm,
- INTEL_INFO(dev_priv)->color.gamma_lut_size);
+ INTEL_INFO(dev_priv)->display.color.gamma_lut_size);
}
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 7bc944271371..0cdd6513fbb7 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -127,30 +127,33 @@
}
#define I9XX_COLORS \
- .color = { .gamma_lut_size = 256 }
+ .display.color = { .gamma_lut_size = 256 }
#define I965_COLORS \
- .color = { .gamma_lut_size = 129, \
+ .display.color = { .gamma_lut_size = 129, \
.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
}
#define ILK_COLORS \
- .color = { .gamma_lut_size = 1024 }
+ .display.color = { .gamma_lut_size = 1024 }
#define IVB_COLORS \
- .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
+ .display.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
#define CHV_COLORS \
- .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
- .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
- .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
+ .display.color = { \
+ .degamma_lut_size = 65, .gamma_lut_size = 257, \
+ .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
+ .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
}
#define GLK_COLORS \
- .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
- .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
- DRM_COLOR_LUT_EQUAL_CHANNELS, \
+ .display.color = { \
+ .degamma_lut_size = 33, .gamma_lut_size = 1024, \
+ .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
+ DRM_COLOR_LUT_EQUAL_CHANNELS, \
}
#define ICL_COLORS \
- .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145, \
- .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
- DRM_COLOR_LUT_EQUAL_CHANNELS, \
- .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
+ .display.color = { \
+ .degamma_lut_size = 33, .gamma_lut_size = 262145, \
+ .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
+ DRM_COLOR_LUT_EQUAL_CHANNELS, \
+ .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
}
/* Keep in gen based order, and chronological order within a gen */
@@ -939,9 +942,10 @@ static const struct intel_device_info adl_s_info = {
#define XE_LPD_FEATURES \
.display.abox_mask = GENMASK(1, 0), \
- .color = { .degamma_lut_size = 128, .gamma_lut_size = 1024, \
- .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
- DRM_COLOR_LUT_EQUAL_CHANNELS, \
+ .display.color = { \
+ .degamma_lut_size = 128, .gamma_lut_size = 1024, \
+ .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
+ DRM_COLOR_LUT_EQUAL_CHANNELS, \
}, \
.display.dbuf.size = 4096, \
.display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 2be7ba78f123..1c150cd7dceb 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -245,15 +245,14 @@ struct intel_device_info {
u32 pipe_offsets[I915_MAX_TRANSCODERS];
u32 trans_offsets[I915_MAX_TRANSCODERS];
u32 cursor_offsets[I915_MAX_PIPES];
+
+ struct {
+ u32 degamma_lut_size;
+ u32 gamma_lut_size;
+ u32 degamma_lut_tests;
+ u32 gamma_lut_tests;
+ } color;
} display;
-
-
- struct color_luts {
- u32 degamma_lut_size;
- u32 gamma_lut_size;
- u32 degamma_lut_tests;
- u32 gamma_lut_tests;
- } color;
};
struct intel_runtime_info {
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Display info cleanup
2022-06-23 13:08 [Intel-gfx] [PATCH 0/9] drm/i915: Display info cleanup Ville Syrjala
` (8 preceding siblings ...)
2022-06-23 13:09 ` [Intel-gfx] [PATCH 9/9] drm/i915: Move the color stuff under INTEL_INFO->display Ville Syrjala
@ 2022-06-23 14:10 ` Patchwork
2022-06-23 14:10 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2022-06-23 14:10 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Display info cleanup
URL : https://patchwork.freedesktop.org/series/105544/
State : warning
== Summary ==
Error: dim checkpatch failed
bcf8c9fff0b4 drm/i915: Move dbuf details to INTEL_INFO->display
1822c399b492 drm/i195: Move pipe_offsets[] & co. to INTEL_INFO->display
-:203: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#203: FILE: drivers/gpu/drm/i915/i915_reg.h:168:
+ INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \
-:209: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#209: FILE: drivers/gpu/drm/i915/i915_reg.h:171:
+#define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \
-:210: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#210: FILE: drivers/gpu/drm/i915/i915_reg.h:172:
+ INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \
total: 0 errors, 3 warnings, 0 checks, 201 lines checked
0b9b527d78fb drm/i915: Move display_mmio_offset under INTEL_INFO->display
2b9625c946c8 drm/i915: Make pipe_offsets[] & co. u32
b48f7d430d90 drm/i915: s/_CURSOR2/_MMIO_CURSOR2//
-:23: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#23: FILE: drivers/gpu/drm/i915/i915_reg.h:171:
+#define _MMIO_CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \
total: 0 errors, 1 warnings, 0 checks, 26 lines checked
817a86fd09fc drm/i915: Use _MMIO_TRANS2() where appropriate
-:25: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#25: FILE: drivers/gpu/drm/i915/i915_reg.h:167:
+#define _MMIO_TRANS2(tran, reg) _MMIO(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \
-:26: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#26: FILE: drivers/gpu/drm/i915/i915_reg.h:168:
+ INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \
-:45: WARNING:LONG_LINE_COMMENT: line length of 111 exceeds 100 columns
#45: FILE: drivers/gpu/drm/i915/i915_reg.h:2219:
+#define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) + 4) /* 5 registers */
total: 0 errors, 3 warnings, 0 checks, 57 lines checked
cc0551e0e69b drm/i915: Use _MMIO_PIPE2() where appropriate
-:24: WARNING:LONG_LINE_COMMENT: line length of 106 exceeds 100 columns
#24: FILE: drivers/gpu/drm/i915/i915_reg.h:4410:
+#define DSPGAMC(plane, i) _MMIO_PIPE2(plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
total: 0 errors, 1 warnings, 0 checks, 8 lines checked
b17e4cf055d2 drm/i915: Get rid of XE_LPD_CURSOR_OFFSETS
0321c1ce5e8e drm/i915: Move the color stuff under INTEL_INFO->display
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Display info cleanup
2022-06-23 13:08 [Intel-gfx] [PATCH 0/9] drm/i915: Display info cleanup Ville Syrjala
` (9 preceding siblings ...)
2022-06-23 14:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Display info cleanup Patchwork
@ 2022-06-23 14:10 ` Patchwork
2022-06-23 14:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2022-06-23 14:10 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Display info cleanup
URL : https://patchwork.freedesktop.org/series/105544/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Display info cleanup
2022-06-23 13:08 [Intel-gfx] [PATCH 0/9] drm/i915: Display info cleanup Ville Syrjala
` (10 preceding siblings ...)
2022-06-23 14:10 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-06-23 14:35 ` Patchwork
2022-06-23 18:27 ` [Intel-gfx] [PATCH 0/9] " Jani Nikula
2022-06-27 14:29 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
13 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2022-06-23 14:35 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 11720 bytes --]
== Series Details ==
Series: drm/i915: Display info cleanup
URL : https://patchwork.freedesktop.org/series/105544/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11797 -> Patchwork_105544v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/index.html
Participating hosts (36 -> 37)
------------------------------
Additional (3): bat-adln-1 fi-rkl-11600 bat-jsl-1
Missing (2): fi-cfl-guc fi-bdw-samus
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_105544v1:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_mocs:
- {bat-adln-1}: NOTRUN -> [DMESG-FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/bat-adln-1/igt@i915_selftest@live@gt_mocs.html
Known issues
------------
Here are the changes found in Patchwork_105544v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-rkl-11600: NOTRUN -> [SKIP][2] ([i915#2190])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/fi-rkl-11600/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-rkl-11600: NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/fi-rkl-11600/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_tiled_pread_basic:
- fi-rkl-11600: NOTRUN -> [SKIP][4] ([i915#3282])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- fi-rkl-11600: NOTRUN -> [SKIP][5] ([i915#3012])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/fi-rkl-11600/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_selftest@live@gt_engines:
- bat-dg1-6: [PASS][6] -> [INCOMPLETE][7] ([i915#4418])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@gtt:
- fi-bdw-5557u: [PASS][8] -> [DMESG-FAIL][9] ([i915#3674])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/fi-bdw-5557u/igt@i915_selftest@live@gtt.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/fi-bdw-5557u/igt@i915_selftest@live@gtt.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [PASS][10] -> [INCOMPLETE][11] ([i915#4785])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
- bat-dg1-5: [PASS][12] -> [DMESG-FAIL][13] ([i915#4494] / [i915#4957])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
- fi-bdw-5557u: NOTRUN -> [INCOMPLETE][14] ([i915#3921])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/fi-bdw-5557u/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510: [PASS][15] -> [DMESG-FAIL][16] ([i915#4528])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/fi-pnv-d510/igt@i915_selftest@live@requests.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/fi-pnv-d510/igt@i915_selftest@live@requests.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: NOTRUN -> [INCOMPLETE][17] ([i915#5982])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-blb-e6850: NOTRUN -> [SKIP][18] ([fdo#109271])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/fi-blb-e6850/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-rkl-11600: NOTRUN -> [SKIP][19] ([fdo#111827]) +7 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/fi-rkl-11600/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-rkl-11600: NOTRUN -> [SKIP][20] ([i915#4103])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/fi-rkl-11600/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html
* igt@kms_flip@basic-plain-flip@a-edp1:
- fi-tgl-u2: [PASS][21] -> [DMESG-WARN][22] ([i915#402]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/fi-tgl-u2/igt@kms_flip@basic-plain-flip@a-edp1.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/fi-tgl-u2/igt@kms_flip@basic-plain-flip@a-edp1.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-rkl-11600: NOTRUN -> [SKIP][23] ([fdo#109285] / [i915#4098])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/fi-rkl-11600/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_psr@sprite_plane_onoff:
- fi-rkl-11600: NOTRUN -> [SKIP][24] ([i915#1072]) +3 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/fi-rkl-11600/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-rkl-11600: NOTRUN -> [SKIP][25] ([i915#3555] / [i915#4098])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/fi-rkl-11600/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-read:
- fi-rkl-11600: NOTRUN -> [SKIP][26] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/fi-rkl-11600/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-userptr:
- fi-rkl-11600: NOTRUN -> [SKIP][27] ([fdo#109295] / [i915#3301] / [i915#3708])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/fi-rkl-11600/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-hsw-4770: NOTRUN -> [FAIL][28] ([fdo#109271] / [i915#4312] / [i915#5594] / [i915#6246])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/fi-hsw-4770/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@smem:
- {fi-ehl-2}: [DMESG-WARN][29] ([i915#5122]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html
* igt@i915_selftest@live@gem_contexts:
- fi-bdw-5557u: [INCOMPLETE][31] ([i915#5502]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [DMESG-FAIL][33] ([i915#4528]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/fi-blb-e6850/igt@i915_selftest@live@requests.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/fi-blb-e6850/igt@i915_selftest@live@requests.html
* igt@kms_busy@basic@modeset:
- fi-tgl-u2: [DMESG-WARN][35] ([i915#402]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/fi-tgl-u2/igt@kms_busy@basic@modeset.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/fi-tgl-u2/igt@kms_busy@basic@modeset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3003]: https://gitlab.freedesktop.org/drm/intel/issues/3003
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3674]: https://gitlab.freedesktop.org/drm/intel/issues/3674
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
[i915#5502]: https://gitlab.freedesktop.org/drm/intel/issues/5502
[i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594
[i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
[i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982
[i915#6246]: https://gitlab.freedesktop.org/drm/intel/issues/6246
Build changes
-------------
* Linux: CI_DRM_11797 -> Patchwork_105544v1
CI-20190529: 20190529
CI_DRM_11797: c8c7034b2d49cd9833263fb7aa764c8d4f3f0043 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6541: 02153f109bd422d93cfce7f5aa9d7b0e22fab13c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_105544v1: c8c7034b2d49cd9833263fb7aa764c8d4f3f0043 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
215d0bd94d99 drm/i915: Move the color stuff under INTEL_INFO->display
520c2a0aae22 drm/i915: Get rid of XE_LPD_CURSOR_OFFSETS
f2405e28d21f drm/i915: Use _MMIO_PIPE2() where appropriate
cf6512573bcf drm/i915: Use _MMIO_TRANS2() where appropriate
9f4471d13919 drm/i915: s/_CURSOR2/_MMIO_CURSOR2//
4378045e09a8 drm/i915: Make pipe_offsets[] & co. u32
0aad4c73bcdb drm/i915: Move display_mmio_offset under INTEL_INFO->display
db0e15b98519 drm/i195: Move pipe_offsets[] & co. to INTEL_INFO->display
d4772f954823 drm/i915: Move dbuf details to INTEL_INFO->display
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/index.html
[-- Attachment #2: Type: text/html, Size: 13082 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 0/9] drm/i915: Display info cleanup
2022-06-23 13:08 [Intel-gfx] [PATCH 0/9] drm/i915: Display info cleanup Ville Syrjala
` (11 preceding siblings ...)
2022-06-23 14:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-06-23 18:27 ` Jani Nikula
2022-06-23 18:29 ` Jani Nikula
2022-06-27 14:29 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
13 siblings, 1 reply; 16+ messages in thread
From: Jani Nikula @ 2022-06-23 18:27 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Thu, 23 Jun 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Collect more stuff under INTEL_INFO->display, and clean up
> some messy stuff in the related register macros.
Makes me wonder if we should have DISPLAY_INFO(i915) macro that returns
a pointer to the display sub-struct.
Anyway, the series is
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> Ville Syrjälä (9):
> drm/i915: Move dbuf details to INTEL_INFO->display
> drm/i195: Move pipe_offsets[] & co. to INTEL_INFO->display
> drm/i915: Move display_mmio_offset under INTEL_INFO->display
> drm/i915: Make pipe_offsets[] & co. u32
> drm/i915: s/_CURSOR2/_MMIO_CURSOR2//
> drm/i915: Use _MMIO_TRANS2() where appropriate
> drm/i915: Use _MMIO_PIPE2() where appropriate
> drm/i915: Get rid of XE_LPD_CURSOR_OFFSETS
> drm/i915: Move the color stuff under INTEL_INFO->display
>
> drivers/gpu/drm/i915/display/intel_color.c | 28 ++---
> drivers/gpu/drm/i915/display/intel_display.h | 2 +-
> .../drm/i915/display/intel_display_power.c | 2 +-
> drivers/gpu/drm/i915/i915_pci.c | 112 +++++++++---------
> drivers/gpu/drm/i915/i915_reg.h | 47 ++++----
> drivers/gpu/drm/i915/intel_device_info.h | 39 +++---
> drivers/gpu/drm/i915/intel_pm.c | 8 +-
> 7 files changed, 117 insertions(+), 121 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 0/9] drm/i915: Display info cleanup
2022-06-23 18:27 ` [Intel-gfx] [PATCH 0/9] " Jani Nikula
@ 2022-06-23 18:29 ` Jani Nikula
0 siblings, 0 replies; 16+ messages in thread
From: Jani Nikula @ 2022-06-23 18:29 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Thu, 23 Jun 2022, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Thu, 23 Jun 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Collect more stuff under INTEL_INFO->display, and clean up
>> some messy stuff in the related register macros.
>
> Makes me wonder if we should have DISPLAY_INFO(i915) macro that returns
> a pointer to the display sub-struct.
>
> Anyway, the series is
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
PS. Here's a somewhat related device info cleanup:
https://patchwork.freedesktop.org/series/105358/
>
>
>>
>> Ville Syrjälä (9):
>> drm/i915: Move dbuf details to INTEL_INFO->display
>> drm/i195: Move pipe_offsets[] & co. to INTEL_INFO->display
>> drm/i915: Move display_mmio_offset under INTEL_INFO->display
>> drm/i915: Make pipe_offsets[] & co. u32
>> drm/i915: s/_CURSOR2/_MMIO_CURSOR2//
>> drm/i915: Use _MMIO_TRANS2() where appropriate
>> drm/i915: Use _MMIO_PIPE2() where appropriate
>> drm/i915: Get rid of XE_LPD_CURSOR_OFFSETS
>> drm/i915: Move the color stuff under INTEL_INFO->display
>>
>> drivers/gpu/drm/i915/display/intel_color.c | 28 ++---
>> drivers/gpu/drm/i915/display/intel_display.h | 2 +-
>> .../drm/i915/display/intel_display_power.c | 2 +-
>> drivers/gpu/drm/i915/i915_pci.c | 112 +++++++++---------
>> drivers/gpu/drm/i915/i915_reg.h | 47 ++++----
>> drivers/gpu/drm/i915/intel_device_info.h | 39 +++---
>> drivers/gpu/drm/i915/intel_pm.c | 8 +-
>> 7 files changed, 117 insertions(+), 121 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Display info cleanup
2022-06-23 13:08 [Intel-gfx] [PATCH 0/9] drm/i915: Display info cleanup Ville Syrjala
` (12 preceding siblings ...)
2022-06-23 18:27 ` [Intel-gfx] [PATCH 0/9] " Jani Nikula
@ 2022-06-27 14:29 ` Patchwork
13 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2022-06-27 14:29 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 41972 bytes --]
== Series Details ==
Series: drm/i915: Display info cleanup
URL : https://patchwork.freedesktop.org/series/105544/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11797_full -> Patchwork_105544v1_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_105544v1_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_105544v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_105544v1_full:
### IGT changes ###
#### Warnings ####
* igt@gem_pwrite@basic-exhaustion:
- shard-tglb: [WARN][1] ([i915#2658]) -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-tglb6/igt@gem_pwrite@basic-exhaustion.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-tglb7/igt@gem_pwrite@basic-exhaustion.html
Known issues
------------
Here are the changes found in Patchwork_105544v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [PASS][3] -> [FAIL][4] ([i915#6268])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-tglb7/igt@gem_ctx_exec@basic-nohangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-tglb2/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +4 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-kbl6/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_ctx_persistence@hang:
- shard-skl: NOTRUN -> [SKIP][7] ([fdo#109271]) +390 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl3/igt@gem_ctx_persistence@hang.html
* igt@gem_exec_fair@basic-deadline:
- shard-skl: NOTRUN -> [FAIL][8] ([i915#6141])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl9/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][9] ([i915#2842]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-iclb2/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk: [PASS][10] -> [FAIL][11] ([i915#2842])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-glk7/igt@gem_exec_fair@basic-pace@rcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-glk9/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [PASS][12] -> [FAIL][13] ([i915#2842])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_lmem_swapping@heavy-verify-multi:
- shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +4 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl7/igt@gem_lmem_swapping@heavy-verify-multi.html
* igt@gem_lmem_swapping@verify-random:
- shard-apl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-apl3/igt@gem_lmem_swapping@verify-random.html
* igt@gem_pwrite@basic-exhaustion:
- shard-glk: NOTRUN -> [WARN][16] ([i915#2658])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-glk5/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_render_copy@y-tiled-to-vebox-y-tiled:
- shard-glk: NOTRUN -> [SKIP][17] ([fdo#109271]) +4 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-glk5/igt@gem_render_copy@y-tiled-to-vebox-y-tiled.html
* igt@gem_userptr_blits@input-checking:
- shard-glk: NOTRUN -> [DMESG-WARN][18] ([i915#4991])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-glk5/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@vma-merge:
- shard-kbl: NOTRUN -> [FAIL][19] ([i915#3318])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-kbl7/igt@gem_userptr_blits@vma-merge.html
- shard-skl: NOTRUN -> [FAIL][20] ([i915#3318])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl3/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@allowed-single:
- shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#5566] / [i915#716])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-kbl7/igt@gen9_exec_parse@allowed-single.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-kbl6/igt@gen9_exec_parse@allowed-single.html
- shard-glk: [PASS][23] -> [DMESG-WARN][24] ([i915#5566] / [i915#716])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-glk5/igt@gen9_exec_parse@allowed-single.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-glk1/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-kbl: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#658])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-kbl7/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_selftest@live@gt_pm:
- shard-skl: NOTRUN -> [DMESG-FAIL][26] ([i915#1886])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl7/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [PASS][27] -> [INCOMPLETE][28] ([i915#3921])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-snb4/igt@i915_selftest@live@hangcheck.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-snb6/igt@i915_selftest@live@hangcheck.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][29] ([i915#3743]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl7/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][30] ([i915#3763])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3886]) +19 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl1/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3886]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-kbl7/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3886]) +2 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-apl3/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@dp-crc-multiple:
- shard-apl: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +3 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-apl3/igt@kms_chamelium@dp-crc-multiple.html
* igt@kms_chamelium@hdmi-crc-multiple:
- shard-skl: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +25 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl6/igt@kms_chamelium@hdmi-crc-multiple.html
* igt@kms_color@pipe-b-deep-color:
- shard-kbl: NOTRUN -> [SKIP][36] ([fdo#109271]) +67 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-kbl7/igt@kms_color@pipe-b-deep-color.html
* igt@kms_color_chamelium@pipe-a-gamma:
- shard-kbl: NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827]) +2 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-kbl7/igt@kms_color_chamelium@pipe-a-gamma.html
* igt@kms_dither@fb-8bpc-vs-panel-8bpc@pipe-a-hdmi-a-1:
- shard-glk: [PASS][38] -> [SKIP][39] ([fdo#109271])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-glk2/igt@kms_dither@fb-8bpc-vs-panel-8bpc@pipe-a-hdmi-a-1.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-glk8/igt@kms_dither@fb-8bpc-vs-panel-8bpc@pipe-a-hdmi-a-1.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [PASS][40] -> [FAIL][41] ([i915#4767])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-apl2/igt@kms_fbcon_fbt@fbc-suspend.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-apl3/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-apl: NOTRUN -> [SKIP][42] ([fdo#109271]) +29 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-apl3/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-skl: [PASS][43] -> [FAIL][44] ([i915#79])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [PASS][45] -> [DMESG-WARN][46] ([i915#180])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-skl: NOTRUN -> [FAIL][47] ([fdo#108145] / [i915#265]) +2 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][48] -> [FAIL][49] ([fdo#108145] / [i915#265])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1:
- shard-iclb: [PASS][50] -> [SKIP][51] ([i915#5235]) +8 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-iclb5/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-apl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#658])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-apl3/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-skl: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#658]) +4 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl3/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-iclb: [PASS][54] -> [SKIP][55] ([fdo#109642] / [fdo#111068] / [i915#658])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-iclb2/igt@kms_psr2_su@page_flip-xrgb8888.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-iclb1/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][56] -> [SKIP][57] ([fdo#109441]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_sysfs_edid_timing:
- shard-skl: NOTRUN -> [FAIL][58] ([IGT#2])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl9/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-skl: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#533])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl7/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-skl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#2437]) +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl4/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf@polling-parameterized:
- shard-glk: [PASS][61] -> [FAIL][62] ([i915#5639])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-glk9/igt@perf@polling-parameterized.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-glk7/igt@perf@polling-parameterized.html
* igt@sw_sync@sync_multi_timeline_wait:
- shard-skl: NOTRUN -> [FAIL][63] ([i915#6140]) +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl3/igt@sw_sync@sync_multi_timeline_wait.html
* igt@sysfs_clients@fair-0:
- shard-kbl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#2994]) +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-kbl7/igt@sysfs_clients@fair-0.html
* igt@sysfs_clients@pidname:
- shard-skl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#2994]) +4 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl1/igt@sysfs_clients@pidname.html
* igt@sysfs_clients@split-25:
- shard-apl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#2994])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-apl3/igt@sysfs_clients@split-25.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-apl: [DMESG-WARN][67] ([i915#180]) -> [PASS][68] +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-apl4/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-apl3/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-tglb: [TIMEOUT][69] ([i915#3063]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-tglb6/igt@gem_eio@in-flight-contexts-10ms.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-tglb3/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_exec_fair@basic-flow@rcs0:
- {shard-rkl}: [FAIL][71] ([i915#2842]) -> [PASS][72] +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-rkl-1/igt@gem_exec_fair@basic-flow@rcs0.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-rkl-5/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- {shard-tglu}: [FAIL][73] ([i915#2842]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-tglu-3/igt@gem_exec_fair@basic-none-share@rcs0.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-tglu-6/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-glk: [FAIL][75] ([i915#2842]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-glk1/igt@gem_exec_fair@basic-none-vip@rcs0.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-glk5/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl: [FAIL][77] ([i915#2842]) -> [PASS][78] +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-kbl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-kbl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][79] ([i915#2849]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_reloc@basic-write-read:
- {shard-rkl}: [SKIP][81] ([i915#3281]) -> [PASS][82] +7 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-rkl-6/igt@gem_exec_reloc@basic-write-read.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-rkl-5/igt@gem_exec_reloc@basic-write-read.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][83] ([i915#2190]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-tglb7/igt@gem_huc_copy@huc-copy.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-tglb1/igt@gem_huc_copy@huc-copy.html
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- {shard-rkl}: [SKIP][85] ([i915#3282]) -> [PASS][86] +10 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-rkl-6/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-rkl-5/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [DMESG-WARN][87] ([i915#180]) -> [PASS][88] +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-kbl6/igt@gem_workarounds@suspend-resume-fd.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-kbl7/igt@gem_workarounds@suspend-resume-fd.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [DMESG-WARN][89] ([i915#5566] / [i915#716]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-glk9/igt@gen9_exec_parse@allowed-all.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-glk5/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@shadow-peek:
- {shard-rkl}: [SKIP][91] ([i915#2527]) -> [PASS][92] +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-rkl-1/igt@gen9_exec_parse@shadow-peek.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-rkl-5/igt@gen9_exec_parse@shadow-peek.html
* igt@i915_pm_dc@dc6-dpms:
- {shard-rkl}: [SKIP][93] ([i915#3361]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-rkl-5/igt@i915_pm_dc@dc6-dpms.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-rkl-1/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rps@min-max-config-idle:
- {shard-rkl}: [FAIL][95] ([i915#4016]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-rkl-1/igt@i915_pm_rps@min-max-config-idle.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-rkl-5/igt@i915_pm_rps@min-max-config-idle.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- {shard-rkl}: [SKIP][97] ([i915#1845] / [i915#4098]) -> [PASS][98] +9 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-rkl-1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-rkl-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_color@pipe-a-ctm-0-5:
- {shard-rkl}: [SKIP][99] ([i915#1149] / [i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-rkl-1/igt@kms_color@pipe-a-ctm-0-5.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-rkl-6/igt@kms_color@pipe-a-ctm-0-5.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled:
- {shard-rkl}: [SKIP][101] ([fdo#111314] / [i915#4098] / [i915#4369]) -> [PASS][102] +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-rkl-1/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-rkl-6/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][103] ([i915#79]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
- shard-glk: [FAIL][105] ([i915#4911]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-glk3/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- {shard-rkl}: [SKIP][107] ([i915#1849] / [i915#4098]) -> [PASS][108] +9 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-suspend.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_hdr@bpc-switch@pipe-a-dp-1:
- shard-kbl: [FAIL][109] ([i915#1188]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-kbl4/igt@kms_hdr@bpc-switch@pipe-a-dp-1.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-kbl7/igt@kms_hdr@bpc-switch@pipe-a-dp-1.html
* igt@kms_invalid_mode@zero-clock:
- {shard-rkl}: [SKIP][111] ([i915#4278]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-rkl-1/igt@kms_invalid_mode@zero-clock.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-rkl-6/igt@kms_invalid_mode@zero-clock.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-a-edp-1:
- shard-iclb: [SKIP][113] ([i915#5176]) -> [PASS][114] +2 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-iclb2/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-a-edp-1.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-iclb1/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-a-edp-1.html
* igt@kms_psr@primary_blt:
- {shard-rkl}: [SKIP][115] ([i915#1072]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-rkl-1/igt@kms_psr@primary_blt.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-rkl-6/igt@kms_psr@primary_blt.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-tglb: [SKIP][117] ([i915#5519]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-tglb5/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-tglb6/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_universal_plane@universal-plane-pipe-a-sanity:
- {shard-rkl}: [SKIP][119] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-rkl-1/igt@kms_universal_plane@universal-plane-pipe-a-sanity.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-rkl-6/igt@kms_universal_plane@universal-plane-pipe-a-sanity.html
* igt@perf@gen12-mi-rpc:
- {shard-rkl}: [SKIP][121] ([fdo#109289]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-rkl-5/igt@perf@gen12-mi-rpc.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-rkl-1/igt@perf@gen12-mi-rpc.html
* igt@perf@polling-parameterized:
- shard-tglb: [FAIL][123] ([i915#5639]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-tglb6/igt@perf@polling-parameterized.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-tglb3/igt@perf@polling-parameterized.html
* igt@perf@polling-small-buf:
- {shard-rkl}: [FAIL][125] ([i915#1722]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-rkl-1/igt@perf@polling-small-buf.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-rkl-6/igt@perf@polling-small-buf.html
* igt@perf_pmu@module-unload:
- {shard-tglu}: [FAIL][127] -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-tglu-3/igt@perf_pmu@module-unload.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-tglu-6/igt@perf_pmu@module-unload.html
* igt@prime_vgem@coherency-gtt:
- {shard-rkl}: [SKIP][129] ([fdo#109295] / [fdo#111656] / [i915#3708]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-rkl-1/igt@prime_vgem@coherency-gtt.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-rkl-5/igt@prime_vgem@coherency-gtt.html
#### Warnings ####
* igt@gem_eio@unwedge-stress:
- shard-tglb: [FAIL][131] ([i915#5784]) -> [TIMEOUT][132] ([i915#3063])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-tglb5/igt@gem_eio@unwedge-stress.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-tglb6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [FAIL][133] ([i915#6117]) -> [SKIP][134] ([i915#4525])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-iclb4/igt@gem_exec_balancer@parallel-ordering.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-iclb6/igt@gem_exec_balancer@parallel-ordering.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-iclb: [SKIP][135] -> [SKIP][136] ([fdo#110892])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-iclb2/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-iclb1/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_content_protection@srm:
- shard-kbl: [INCOMPLETE][137] -> [TIMEOUT][138] ([i915#1319])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-kbl1/igt@kms_content_protection@srm.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-kbl4/igt@kms_content_protection@srm.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-iclb: [SKIP][139] ([i915#658]) -> [SKIP][140] ([i915#2920])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-iclb5/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-iclb: [SKIP][141] ([fdo#111068] / [i915#658]) -> [SKIP][142] ([i915#2920])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-iclb5/igt@kms_psr2_sf@cursor-plane-update-sf.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-iclb2/igt@kms_psr2_sf@cursor-plane-update-sf.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-iclb: [SKIP][143] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [FAIL][144] ([i915#5939])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-iclb5/igt@kms_psr2_su@page_flip-nv12.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-iclb2/igt@kms_psr2_su@page_flip-nv12.html
* igt@runner@aborted:
- shard-skl: ([FAIL][145], [FAIL][146], [FAIL][147]) ([i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][148], [FAIL][149], [FAIL][150], [FAIL][151], [FAIL][152], [FAIL][153]) ([i915#2029] / [i915#3002] / [i915#4312] / [i915#5257])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-skl6/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-skl4/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-skl9/igt@runner@aborted.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl3/igt@runner@aborted.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl3/igt@runner@aborted.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl3/igt@runner@aborted.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl7/igt@runner@aborted.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl4/igt@runner@aborted.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-skl9/igt@runner@aborted.html
- shard-kbl: ([FAIL][154], [FAIL][155], [FAIL][156], [FAIL][157], [FAIL][158], [FAIL][159]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#92]) -> ([FAIL][160], [FAIL][161], [FAIL][162], [FAIL][163], [FAIL][164], [FAIL][165], [FAIL][166]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#716] / [i915#92])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-kbl3/igt@runner@aborted.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-kbl6/igt@runner@aborted.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-kbl6/igt@runner@aborted.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-kbl6/igt@runner@aborted.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-kbl4/igt@runner@aborted.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11797/shard-kbl7/igt@runner@aborted.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-kbl6/igt@runner@aborted.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-kbl6/igt@runner@aborted.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-kbl6/igt@runner@aborted.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-kbl6/igt@runner@aborted.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-kbl7/igt@runner@aborted.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-kbl1/igt@runner@aborted.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/shard-kbl4/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#110892]: https://bugs.freedesktop.org/show_bug.cgi?id=110892
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3763]: https://gitlab.freedesktop.org/drm/intel/issues/3763
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842
[i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4883]: https://gitlab.freedesktop.org/drm/intel/issues/4883
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4911]: https://gitlab.freedesktop.org/drm/intel/issues/4911
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
[i915#6011]: https://gitlab.freedesktop.org/drm/intel/issues/6011
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6140]: https://gitlab.freedesktop.org/drm/intel/issues/6140
[i915#6141]: https://gitlab.freedesktop.org/drm/intel/issues/6141
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
[i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
Build changes
-------------
* Linux: CI_DRM_11797 -> Patchwork_105544v1
CI-20190529: 20190529
CI_DRM_11797: c8c7034b2d49cd9833263fb7aa764c8d4f3f0043 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6541: 02153f109bd422d93cfce7f5aa9d7b0e22fab13c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_105544v1: c8c7034b2d49cd9833263fb7aa764c8d4f3f0043 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105544v1/index.html
[-- Attachment #2: Type: text/html, Size: 46510 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2022-06-27 14:29 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-23 13:08 [Intel-gfx] [PATCH 0/9] drm/i915: Display info cleanup Ville Syrjala
2022-06-23 13:08 ` [Intel-gfx] [PATCH 1/9] drm/i915: Move dbuf details to INTEL_INFO->display Ville Syrjala
2022-06-23 13:08 ` [Intel-gfx] [PATCH 2/9] drm/i195: Move pipe_offsets[] & co. " Ville Syrjala
2022-06-23 13:08 ` [Intel-gfx] [PATCH 3/9] drm/i915: Move display_mmio_offset under INTEL_INFO->display Ville Syrjala
2022-06-23 13:08 ` [Intel-gfx] [PATCH 4/9] drm/i915: Make pipe_offsets[] & co. u32 Ville Syrjala
2022-06-23 13:08 ` [Intel-gfx] [PATCH 5/9] drm/i915: s/_CURSOR2/_MMIO_CURSOR2// Ville Syrjala
2022-06-23 13:08 ` [Intel-gfx] [PATCH 6/9] drm/i915: Use _MMIO_TRANS2() where appropriate Ville Syrjala
2022-06-23 13:08 ` [Intel-gfx] [PATCH 7/9] drm/i915: Use _MMIO_PIPE2() " Ville Syrjala
2022-06-23 13:08 ` [Intel-gfx] [PATCH 8/9] drm/i915: Get rid of XE_LPD_CURSOR_OFFSETS Ville Syrjala
2022-06-23 13:09 ` [Intel-gfx] [PATCH 9/9] drm/i915: Move the color stuff under INTEL_INFO->display Ville Syrjala
2022-06-23 14:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Display info cleanup Patchwork
2022-06-23 14:10 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-06-23 14:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-06-23 18:27 ` [Intel-gfx] [PATCH 0/9] " Jani Nikula
2022-06-23 18:29 ` Jani Nikula
2022-06-27 14:29 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
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