* [PATCH] clk: qcom: gcc-sc8280xp: use phy-mux clock for PCIe
@ 2022-06-28 8:57 Johan Hovold
2022-07-03 3:56 ` Bjorn Andersson
0 siblings, 1 reply; 2+ messages in thread
From: Johan Hovold @ 2022-06-28 8:57 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, Michael Turquette, Stephen Boyd, linux-arm-msm,
linux-clk, linux-kernel, Johan Hovold
Use the new phy-mux clock implementation for the PCIe pipe clock muxes
so that the pipe clock source is set to the QMP PHY PLL when the
downstream pipe clock is enabled and restored to the always-on XO when
it is again disabled.
This is needed to prevent the corresponding GDSC from hanging when
enabling or disabling the PCIe power domain, something which requires a
ticking source.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
drivers/clk/qcom/gcc-sc8280xp.c | 121 ++++++++------------------------
1 file changed, 31 insertions(+), 90 deletions(-)
diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c
index f186ddf6954e..a2f3ffcc5849 100644
--- a/drivers/clk/qcom/gcc-sc8280xp.c
+++ b/drivers/clk/qcom/gcc-sc8280xp.c
@@ -20,6 +20,7 @@
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
+#include "clk-regmap-phy-mux.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
@@ -82,11 +83,6 @@ enum {
P_GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC,
P_GCC_USB4_PHY_PIPEGMUX_CLK_SRC,
P_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC,
- P_PCIE_2A_PIPE_CLK,
- P_PCIE_2B_PIPE_CLK,
- P_PCIE_3A_PIPE_CLK,
- P_PCIE_3B_PIPE_CLK,
- P_PCIE_4_PIPE_CLK,
P_QUSB4PHY_1_GCC_USB4_RX0_CLK,
P_QUSB4PHY_1_GCC_USB4_RX1_CLK,
P_QUSB4PHY_GCC_USB4_RX0_CLK,
@@ -351,56 +347,6 @@ static const struct clk_parent_data gcc_parent_data_9[] = {
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
-static const struct parent_map gcc_parent_map_10[] = {
- { P_PCIE_2A_PIPE_CLK, 0 },
- { P_BI_TCXO, 2 },
-};
-
-static const struct clk_parent_data gcc_parent_data_10[] = {
- { .index = DT_PCIE_2A_PIPE_CLK },
- { .index = DT_BI_TCXO },
-};
-
-static const struct parent_map gcc_parent_map_11[] = {
- { P_PCIE_2B_PIPE_CLK, 0 },
- { P_BI_TCXO, 2 },
-};
-
-static const struct clk_parent_data gcc_parent_data_11[] = {
- { .index = DT_PCIE_2B_PIPE_CLK },
- { .index = DT_BI_TCXO },
-};
-
-static const struct parent_map gcc_parent_map_12[] = {
- { P_PCIE_3A_PIPE_CLK, 0 },
- { P_BI_TCXO, 2 },
-};
-
-static const struct clk_parent_data gcc_parent_data_12[] = {
- { .index = DT_PCIE_3A_PIPE_CLK },
- { .index = DT_BI_TCXO },
-};
-
-static const struct parent_map gcc_parent_map_13[] = {
- { P_PCIE_3B_PIPE_CLK, 0 },
- { P_BI_TCXO, 2 },
-};
-
-static const struct clk_parent_data gcc_parent_data_13[] = {
- { .index = DT_PCIE_3B_PIPE_CLK },
- { .index = DT_BI_TCXO },
-};
-
-static const struct parent_map gcc_parent_map_14[] = {
- { P_PCIE_4_PIPE_CLK, 0 },
- { P_BI_TCXO, 2 },
-};
-
-static const struct clk_parent_data gcc_parent_data_14[] = {
- { .index = DT_PCIE_4_PIPE_CLK },
- { .index = DT_BI_TCXO },
-};
-
static const struct parent_map gcc_parent_map_15[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
@@ -741,77 +687,72 @@ static const struct clk_parent_data gcc_parent_data_41[] = {
{ .index = DT_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK },
};
-static struct clk_regmap_mux gcc_pcie_2a_pipe_clk_src = {
+static struct clk_regmap_phy_mux gcc_pcie_2a_pipe_clk_src = {
.reg = 0x9d05c,
- .shift = 0,
- .width = 2,
- .parent_map = gcc_parent_map_10,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2a_pipe_clk_src",
- .parent_data = gcc_parent_data_10,
- .num_parents = ARRAY_SIZE(gcc_parent_data_10),
- .ops = &clk_regmap_mux_closest_ops,
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_PCIE_2A_PIPE_CLK,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_phy_mux_ops,
},
},
};
-static struct clk_regmap_mux gcc_pcie_2b_pipe_clk_src = {
+static struct clk_regmap_phy_mux gcc_pcie_2b_pipe_clk_src = {
.reg = 0x9e05c,
- .shift = 0,
- .width = 2,
- .parent_map = gcc_parent_map_11,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_2b_pipe_clk_src",
- .parent_data = gcc_parent_data_11,
- .num_parents = ARRAY_SIZE(gcc_parent_data_11),
- .ops = &clk_regmap_mux_closest_ops,
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_PCIE_2B_PIPE_CLK,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_phy_mux_ops,
},
},
};
-static struct clk_regmap_mux gcc_pcie_3a_pipe_clk_src = {
+static struct clk_regmap_phy_mux gcc_pcie_3a_pipe_clk_src = {
.reg = 0xa005c,
- .shift = 0,
- .width = 2,
- .parent_map = gcc_parent_map_12,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3a_pipe_clk_src",
- .parent_data = gcc_parent_data_12,
- .num_parents = ARRAY_SIZE(gcc_parent_data_12),
- .ops = &clk_regmap_mux_closest_ops,
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_PCIE_3A_PIPE_CLK,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_phy_mux_ops,
},
},
};
-static struct clk_regmap_mux gcc_pcie_3b_pipe_clk_src = {
+static struct clk_regmap_phy_mux gcc_pcie_3b_pipe_clk_src = {
.reg = 0xa205c,
- .shift = 0,
- .width = 2,
- .parent_map = gcc_parent_map_13,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_3b_pipe_clk_src",
- .parent_data = gcc_parent_data_13,
- .num_parents = ARRAY_SIZE(gcc_parent_data_13),
- .ops = &clk_regmap_mux_closest_ops,
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_PCIE_3B_PIPE_CLK,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_phy_mux_ops,
},
},
};
-static struct clk_regmap_mux gcc_pcie_4_pipe_clk_src = {
+static struct clk_regmap_phy_mux gcc_pcie_4_pipe_clk_src = {
.reg = 0x6b05c,
- .shift = 0,
- .width = 2,
- .parent_map = gcc_parent_map_14,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_4_pipe_clk_src",
- .parent_data = gcc_parent_data_14,
- .num_parents = ARRAY_SIZE(gcc_parent_data_14),
- .ops = &clk_regmap_mux_closest_ops,
+ .parent_data = &(const struct clk_parent_data){
+ .index = DT_PCIE_4_PIPE_CLK,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_phy_mux_ops,
},
},
};
--
2.35.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] clk: qcom: gcc-sc8280xp: use phy-mux clock for PCIe
2022-06-28 8:57 [PATCH] clk: qcom: gcc-sc8280xp: use phy-mux clock for PCIe Johan Hovold
@ 2022-07-03 3:56 ` Bjorn Andersson
0 siblings, 0 replies; 2+ messages in thread
From: Bjorn Andersson @ 2022-07-03 3:56 UTC (permalink / raw)
To: Johan Hovold
Cc: linux-clk, Michael Turquette, Andy Gross, linux-arm-msm,
linux-kernel, Stephen Boyd
On Tue, 28 Jun 2022 10:57:07 +0200, Johan Hovold wrote:
> Use the new phy-mux clock implementation for the PCIe pipe clock muxes
> so that the pipe clock source is set to the QMP PHY PLL when the
> downstream pipe clock is enabled and restored to the always-on XO when
> it is again disabled.
>
> This is needed to prevent the corresponding GDSC from hanging when
> enabling or disabling the PCIe power domain, something which requires a
> ticking source.
>
> [...]
Applied, thanks!
[1/1] clk: qcom: gcc-sc8280xp: use phy-mux clock for PCIe
commit: 9410fb940114444f37a0b787bd84077b61d76bf6
Best regards,
--
Bjorn Andersson <bjorn.andersson@linaro.org>
^ permalink raw reply [flat|nested] 2+ messages in thread
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