* [PATCH] powerpc/fsl-pci: Fix Class Code of PCIe Root Port
@ 2022-07-06 10:10 ` Pali Rohár
0 siblings, 0 replies; 9+ messages in thread
From: Pali Rohár @ 2022-07-06 10:10 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras, Bjorn Helgaas
Cc: linuxppc-dev, linux-pci, linux-kernel
By default old pre-3.0 Freescale PCIe controllers reports invalid PCI Class
Code 0x0b20 for PCIe Root Port. It can be seen by lspci -b output on P2020
board which has this pre-3.0 controller:
$ lspci -bvnn
00:00.0 Power PC [0b20]: Freescale Semiconductor Inc P2020E [1957:0070] (rev 21)
!!! Invalid class 0b20 for header type 01
Capabilities: [4c] Express Root Port (Slot-), MSI 00
Fix this issue by programming correct PCI Class Code 0x0604 for PCIe Root
Port to the Freescale specific PCIe register 0x474.
With this change lspci -b output is:
$ lspci -bvnn
00:00.0 PCI bridge [0604]: Freescale Semiconductor Inc P2020E [1957:0070] (rev 21) (prog-if 00 [Normal decode])
Capabilities: [4c] Express Root Port (Slot-), MSI 00
Without any "Invalid class" error. So class code was properly reflected
into standard (read-only) PCI register 0x08.
Same fix is already implemented in U-Boot pcie_fsl.c driver in commit:
http://source.denx.de/u-boot/u-boot/-/commit/d18d06ac35229345a0af80977a408cfbe1d1015b
Fix activated by U-Boot stay active also after booting Linux kernel.
But boards which use older U-Boot version without that fix are affected and
still require this fix.
So implement this class code fix also in kernel fsl_pci.c driver.
Cc: stable@vger.kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
---
arch/powerpc/sysdev/fsl_pci.c | 8 ++++++++
arch/powerpc/sysdev/fsl_pci.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 1011cfea2e32..bfbb8c8fc9aa 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -521,6 +521,7 @@ int fsl_add_bridge(struct platform_device *pdev, int is_primary)
struct resource rsrc;
const int *bus_range;
u8 hdr_type, progif;
+ u32 class_code;
struct device_node *dev;
struct ccsr_pci __iomem *pci;
u16 temp;
@@ -594,6 +595,13 @@ int fsl_add_bridge(struct platform_device *pdev, int is_primary)
PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
if (fsl_pcie_check_link(hose))
hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
+ /* Fix Class Code to PCI_CLASS_BRIDGE_PCI_NORMAL for pre-3.0 controller */
+ if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) {
+ early_read_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, &class_code);
+ class_code &= 0xff;
+ class_code |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
+ early_write_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, class_code);
+ }
} else {
/*
* Set PBFR(PCI Bus Function Register)[10] = 1 to
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index cdbde2e0c96e..093a875d7d1e 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -18,6 +18,7 @@ struct platform_device;
#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
#define PCIE_LTSSM_L0 0x16 /* L0 state */
+#define PCIE_FSL_CSR_CLASSCODE 0x474 /* FSL GPEX CSR */
#define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
#define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
#define PIWAR_EN 0x80000000 /* Enable */
--
2.20.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH] powerpc/fsl-pci: Fix Class Code of PCIe Root Port
@ 2022-07-06 10:10 ` Pali Rohár
0 siblings, 0 replies; 9+ messages in thread
From: Pali Rohár @ 2022-07-06 10:10 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras, Bjorn Helgaas
Cc: linux-pci, linuxppc-dev, linux-kernel
By default old pre-3.0 Freescale PCIe controllers reports invalid PCI Class
Code 0x0b20 for PCIe Root Port. It can be seen by lspci -b output on P2020
board which has this pre-3.0 controller:
$ lspci -bvnn
00:00.0 Power PC [0b20]: Freescale Semiconductor Inc P2020E [1957:0070] (rev 21)
!!! Invalid class 0b20 for header type 01
Capabilities: [4c] Express Root Port (Slot-), MSI 00
Fix this issue by programming correct PCI Class Code 0x0604 for PCIe Root
Port to the Freescale specific PCIe register 0x474.
With this change lspci -b output is:
$ lspci -bvnn
00:00.0 PCI bridge [0604]: Freescale Semiconductor Inc P2020E [1957:0070] (rev 21) (prog-if 00 [Normal decode])
Capabilities: [4c] Express Root Port (Slot-), MSI 00
Without any "Invalid class" error. So class code was properly reflected
into standard (read-only) PCI register 0x08.
Same fix is already implemented in U-Boot pcie_fsl.c driver in commit:
http://source.denx.de/u-boot/u-boot/-/commit/d18d06ac35229345a0af80977a408cfbe1d1015b
Fix activated by U-Boot stay active also after booting Linux kernel.
But boards which use older U-Boot version without that fix are affected and
still require this fix.
So implement this class code fix also in kernel fsl_pci.c driver.
Cc: stable@vger.kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
---
arch/powerpc/sysdev/fsl_pci.c | 8 ++++++++
arch/powerpc/sysdev/fsl_pci.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 1011cfea2e32..bfbb8c8fc9aa 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -521,6 +521,7 @@ int fsl_add_bridge(struct platform_device *pdev, int is_primary)
struct resource rsrc;
const int *bus_range;
u8 hdr_type, progif;
+ u32 class_code;
struct device_node *dev;
struct ccsr_pci __iomem *pci;
u16 temp;
@@ -594,6 +595,13 @@ int fsl_add_bridge(struct platform_device *pdev, int is_primary)
PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
if (fsl_pcie_check_link(hose))
hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
+ /* Fix Class Code to PCI_CLASS_BRIDGE_PCI_NORMAL for pre-3.0 controller */
+ if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) {
+ early_read_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, &class_code);
+ class_code &= 0xff;
+ class_code |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
+ early_write_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, class_code);
+ }
} else {
/*
* Set PBFR(PCI Bus Function Register)[10] = 1 to
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index cdbde2e0c96e..093a875d7d1e 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -18,6 +18,7 @@ struct platform_device;
#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
#define PCIE_LTSSM_L0 0x16 /* L0 state */
+#define PCIE_FSL_CSR_CLASSCODE 0x474 /* FSL GPEX CSR */
#define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
#define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
#define PIWAR_EN 0x80000000 /* Enable */
--
2.20.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH] powerpc/fsl-pci: Fix Class Code of PCIe Root Port
2022-07-06 10:10 ` Pali Rohár
@ 2022-07-21 22:18 ` Pali Rohár
-1 siblings, 0 replies; 9+ messages in thread
From: Pali Rohár @ 2022-07-21 22:18 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras, Bjorn Helgaas
Cc: linuxppc-dev, linux-pci, linux-kernel
PING?
On Wednesday 06 July 2022 12:10:43 Pali Rohár wrote:
> By default old pre-3.0 Freescale PCIe controllers reports invalid PCI Class
> Code 0x0b20 for PCIe Root Port. It can be seen by lspci -b output on P2020
> board which has this pre-3.0 controller:
>
> $ lspci -bvnn
> 00:00.0 Power PC [0b20]: Freescale Semiconductor Inc P2020E [1957:0070] (rev 21)
> !!! Invalid class 0b20 for header type 01
> Capabilities: [4c] Express Root Port (Slot-), MSI 00
>
> Fix this issue by programming correct PCI Class Code 0x0604 for PCIe Root
> Port to the Freescale specific PCIe register 0x474.
>
> With this change lspci -b output is:
>
> $ lspci -bvnn
> 00:00.0 PCI bridge [0604]: Freescale Semiconductor Inc P2020E [1957:0070] (rev 21) (prog-if 00 [Normal decode])
> Capabilities: [4c] Express Root Port (Slot-), MSI 00
>
> Without any "Invalid class" error. So class code was properly reflected
> into standard (read-only) PCI register 0x08.
>
> Same fix is already implemented in U-Boot pcie_fsl.c driver in commit:
> http://source.denx.de/u-boot/u-boot/-/commit/d18d06ac35229345a0af80977a408cfbe1d1015b
>
> Fix activated by U-Boot stay active also after booting Linux kernel.
> But boards which use older U-Boot version without that fix are affected and
> still require this fix.
>
> So implement this class code fix also in kernel fsl_pci.c driver.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Pali Rohár <pali@kernel.org>
> ---
> arch/powerpc/sysdev/fsl_pci.c | 8 ++++++++
> arch/powerpc/sysdev/fsl_pci.h | 1 +
> 2 files changed, 9 insertions(+)
>
> diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
> index 1011cfea2e32..bfbb8c8fc9aa 100644
> --- a/arch/powerpc/sysdev/fsl_pci.c
> +++ b/arch/powerpc/sysdev/fsl_pci.c
> @@ -521,6 +521,7 @@ int fsl_add_bridge(struct platform_device *pdev, int is_primary)
> struct resource rsrc;
> const int *bus_range;
> u8 hdr_type, progif;
> + u32 class_code;
> struct device_node *dev;
> struct ccsr_pci __iomem *pci;
> u16 temp;
> @@ -594,6 +595,13 @@ int fsl_add_bridge(struct platform_device *pdev, int is_primary)
> PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
> if (fsl_pcie_check_link(hose))
> hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
> + /* Fix Class Code to PCI_CLASS_BRIDGE_PCI_NORMAL for pre-3.0 controller */
> + if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) {
> + early_read_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, &class_code);
> + class_code &= 0xff;
> + class_code |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
> + early_write_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, class_code);
> + }
> } else {
> /*
> * Set PBFR(PCI Bus Function Register)[10] = 1 to
> diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
> index cdbde2e0c96e..093a875d7d1e 100644
> --- a/arch/powerpc/sysdev/fsl_pci.h
> +++ b/arch/powerpc/sysdev/fsl_pci.h
> @@ -18,6 +18,7 @@ struct platform_device;
>
> #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
> #define PCIE_LTSSM_L0 0x16 /* L0 state */
> +#define PCIE_FSL_CSR_CLASSCODE 0x474 /* FSL GPEX CSR */
> #define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
> #define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
> #define PIWAR_EN 0x80000000 /* Enable */
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] powerpc/fsl-pci: Fix Class Code of PCIe Root Port
@ 2022-07-21 22:18 ` Pali Rohár
0 siblings, 0 replies; 9+ messages in thread
From: Pali Rohár @ 2022-07-21 22:18 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras, Bjorn Helgaas
Cc: linux-pci, linuxppc-dev, linux-kernel
PING?
On Wednesday 06 July 2022 12:10:43 Pali Rohár wrote:
> By default old pre-3.0 Freescale PCIe controllers reports invalid PCI Class
> Code 0x0b20 for PCIe Root Port. It can be seen by lspci -b output on P2020
> board which has this pre-3.0 controller:
>
> $ lspci -bvnn
> 00:00.0 Power PC [0b20]: Freescale Semiconductor Inc P2020E [1957:0070] (rev 21)
> !!! Invalid class 0b20 for header type 01
> Capabilities: [4c] Express Root Port (Slot-), MSI 00
>
> Fix this issue by programming correct PCI Class Code 0x0604 for PCIe Root
> Port to the Freescale specific PCIe register 0x474.
>
> With this change lspci -b output is:
>
> $ lspci -bvnn
> 00:00.0 PCI bridge [0604]: Freescale Semiconductor Inc P2020E [1957:0070] (rev 21) (prog-if 00 [Normal decode])
> Capabilities: [4c] Express Root Port (Slot-), MSI 00
>
> Without any "Invalid class" error. So class code was properly reflected
> into standard (read-only) PCI register 0x08.
>
> Same fix is already implemented in U-Boot pcie_fsl.c driver in commit:
> http://source.denx.de/u-boot/u-boot/-/commit/d18d06ac35229345a0af80977a408cfbe1d1015b
>
> Fix activated by U-Boot stay active also after booting Linux kernel.
> But boards which use older U-Boot version without that fix are affected and
> still require this fix.
>
> So implement this class code fix also in kernel fsl_pci.c driver.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Pali Rohár <pali@kernel.org>
> ---
> arch/powerpc/sysdev/fsl_pci.c | 8 ++++++++
> arch/powerpc/sysdev/fsl_pci.h | 1 +
> 2 files changed, 9 insertions(+)
>
> diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
> index 1011cfea2e32..bfbb8c8fc9aa 100644
> --- a/arch/powerpc/sysdev/fsl_pci.c
> +++ b/arch/powerpc/sysdev/fsl_pci.c
> @@ -521,6 +521,7 @@ int fsl_add_bridge(struct platform_device *pdev, int is_primary)
> struct resource rsrc;
> const int *bus_range;
> u8 hdr_type, progif;
> + u32 class_code;
> struct device_node *dev;
> struct ccsr_pci __iomem *pci;
> u16 temp;
> @@ -594,6 +595,13 @@ int fsl_add_bridge(struct platform_device *pdev, int is_primary)
> PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
> if (fsl_pcie_check_link(hose))
> hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
> + /* Fix Class Code to PCI_CLASS_BRIDGE_PCI_NORMAL for pre-3.0 controller */
> + if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) {
> + early_read_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, &class_code);
> + class_code &= 0xff;
> + class_code |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
> + early_write_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, class_code);
> + }
> } else {
> /*
> * Set PBFR(PCI Bus Function Register)[10] = 1 to
> diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
> index cdbde2e0c96e..093a875d7d1e 100644
> --- a/arch/powerpc/sysdev/fsl_pci.h
> +++ b/arch/powerpc/sysdev/fsl_pci.h
> @@ -18,6 +18,7 @@ struct platform_device;
>
> #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
> #define PCIE_LTSSM_L0 0x16 /* L0 state */
> +#define PCIE_FSL_CSR_CLASSCODE 0x474 /* FSL GPEX CSR */
> #define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
> #define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
> #define PIWAR_EN 0x80000000 /* Enable */
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] powerpc/fsl-pci: Fix Class Code of PCIe Root Port
2022-07-06 10:10 ` Pali Rohár
@ 2022-07-22 19:42 ` Bjorn Helgaas
-1 siblings, 0 replies; 9+ messages in thread
From: Bjorn Helgaas @ 2022-07-22 19:42 UTC (permalink / raw)
To: Pali Rohár
Cc: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
Bjorn Helgaas, linux-pci, linuxppc-dev, linux-kernel
On Wed, Jul 06, 2022 at 12:10:43PM +0200, Pali Rohár wrote:
> By default old pre-3.0 Freescale PCIe controllers reports invalid PCI Class
> Code 0x0b20 for PCIe Root Port. It can be seen by lspci -b output on P2020
> board which has this pre-3.0 controller:
>
> $ lspci -bvnn
> 00:00.0 Power PC [0b20]: Freescale Semiconductor Inc P2020E [1957:0070] (rev 21)
> !!! Invalid class 0b20 for header type 01
> Capabilities: [4c] Express Root Port (Slot-), MSI 00
>
> Fix this issue by programming correct PCI Class Code 0x0604 for PCIe Root
> Port to the Freescale specific PCIe register 0x474.
>
> With this change lspci -b output is:
>
> $ lspci -bvnn
> 00:00.0 PCI bridge [0604]: Freescale Semiconductor Inc P2020E [1957:0070] (rev 21) (prog-if 00 [Normal decode])
> Capabilities: [4c] Express Root Port (Slot-), MSI 00
>
> Without any "Invalid class" error. So class code was properly reflected
> into standard (read-only) PCI register 0x08.
>
> Same fix is already implemented in U-Boot pcie_fsl.c driver in commit:
> http://source.denx.de/u-boot/u-boot/-/commit/d18d06ac35229345a0af80977a408cfbe1d1015b
>
> Fix activated by U-Boot stay active also after booting Linux kernel.
> But boards which use older U-Boot version without that fix are affected and
> still require this fix.
>
> So implement this class code fix also in kernel fsl_pci.c driver.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Pali Rohár <pali@kernel.org>
I assume the powerpc folks will take care of this.
> ---
> arch/powerpc/sysdev/fsl_pci.c | 8 ++++++++
> arch/powerpc/sysdev/fsl_pci.h | 1 +
> 2 files changed, 9 insertions(+)
>
> diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
> index 1011cfea2e32..bfbb8c8fc9aa 100644
> --- a/arch/powerpc/sysdev/fsl_pci.c
> +++ b/arch/powerpc/sysdev/fsl_pci.c
> @@ -521,6 +521,7 @@ int fsl_add_bridge(struct platform_device *pdev, int is_primary)
> struct resource rsrc;
> const int *bus_range;
> u8 hdr_type, progif;
> + u32 class_code;
> struct device_node *dev;
> struct ccsr_pci __iomem *pci;
> u16 temp;
> @@ -594,6 +595,13 @@ int fsl_add_bridge(struct platform_device *pdev, int is_primary)
> PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
> if (fsl_pcie_check_link(hose))
> hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
> + /* Fix Class Code to PCI_CLASS_BRIDGE_PCI_NORMAL for pre-3.0 controller */
> + if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) {
> + early_read_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, &class_code);
> + class_code &= 0xff;
> + class_code |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
> + early_write_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, class_code);
> + }
> } else {
> /*
> * Set PBFR(PCI Bus Function Register)[10] = 1 to
> diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
> index cdbde2e0c96e..093a875d7d1e 100644
> --- a/arch/powerpc/sysdev/fsl_pci.h
> +++ b/arch/powerpc/sysdev/fsl_pci.h
> @@ -18,6 +18,7 @@ struct platform_device;
>
> #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
> #define PCIE_LTSSM_L0 0x16 /* L0 state */
> +#define PCIE_FSL_CSR_CLASSCODE 0x474 /* FSL GPEX CSR */
> #define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
> #define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
> #define PIWAR_EN 0x80000000 /* Enable */
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] powerpc/fsl-pci: Fix Class Code of PCIe Root Port
@ 2022-07-22 19:42 ` Bjorn Helgaas
0 siblings, 0 replies; 9+ messages in thread
From: Bjorn Helgaas @ 2022-07-22 19:42 UTC (permalink / raw)
To: Pali Rohár
Cc: linux-kernel, Paul Mackerras, linux-pci, Bjorn Helgaas, linuxppc-dev
On Wed, Jul 06, 2022 at 12:10:43PM +0200, Pali Rohár wrote:
> By default old pre-3.0 Freescale PCIe controllers reports invalid PCI Class
> Code 0x0b20 for PCIe Root Port. It can be seen by lspci -b output on P2020
> board which has this pre-3.0 controller:
>
> $ lspci -bvnn
> 00:00.0 Power PC [0b20]: Freescale Semiconductor Inc P2020E [1957:0070] (rev 21)
> !!! Invalid class 0b20 for header type 01
> Capabilities: [4c] Express Root Port (Slot-), MSI 00
>
> Fix this issue by programming correct PCI Class Code 0x0604 for PCIe Root
> Port to the Freescale specific PCIe register 0x474.
>
> With this change lspci -b output is:
>
> $ lspci -bvnn
> 00:00.0 PCI bridge [0604]: Freescale Semiconductor Inc P2020E [1957:0070] (rev 21) (prog-if 00 [Normal decode])
> Capabilities: [4c] Express Root Port (Slot-), MSI 00
>
> Without any "Invalid class" error. So class code was properly reflected
> into standard (read-only) PCI register 0x08.
>
> Same fix is already implemented in U-Boot pcie_fsl.c driver in commit:
> http://source.denx.de/u-boot/u-boot/-/commit/d18d06ac35229345a0af80977a408cfbe1d1015b
>
> Fix activated by U-Boot stay active also after booting Linux kernel.
> But boards which use older U-Boot version without that fix are affected and
> still require this fix.
>
> So implement this class code fix also in kernel fsl_pci.c driver.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Pali Rohár <pali@kernel.org>
I assume the powerpc folks will take care of this.
> ---
> arch/powerpc/sysdev/fsl_pci.c | 8 ++++++++
> arch/powerpc/sysdev/fsl_pci.h | 1 +
> 2 files changed, 9 insertions(+)
>
> diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
> index 1011cfea2e32..bfbb8c8fc9aa 100644
> --- a/arch/powerpc/sysdev/fsl_pci.c
> +++ b/arch/powerpc/sysdev/fsl_pci.c
> @@ -521,6 +521,7 @@ int fsl_add_bridge(struct platform_device *pdev, int is_primary)
> struct resource rsrc;
> const int *bus_range;
> u8 hdr_type, progif;
> + u32 class_code;
> struct device_node *dev;
> struct ccsr_pci __iomem *pci;
> u16 temp;
> @@ -594,6 +595,13 @@ int fsl_add_bridge(struct platform_device *pdev, int is_primary)
> PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
> if (fsl_pcie_check_link(hose))
> hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
> + /* Fix Class Code to PCI_CLASS_BRIDGE_PCI_NORMAL for pre-3.0 controller */
> + if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) {
> + early_read_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, &class_code);
> + class_code &= 0xff;
> + class_code |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
> + early_write_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, class_code);
> + }
> } else {
> /*
> * Set PBFR(PCI Bus Function Register)[10] = 1 to
> diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
> index cdbde2e0c96e..093a875d7d1e 100644
> --- a/arch/powerpc/sysdev/fsl_pci.h
> +++ b/arch/powerpc/sysdev/fsl_pci.h
> @@ -18,6 +18,7 @@ struct platform_device;
>
> #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
> #define PCIE_LTSSM_L0 0x16 /* L0 state */
> +#define PCIE_FSL_CSR_CLASSCODE 0x474 /* FSL GPEX CSR */
> #define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
> #define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
> #define PIWAR_EN 0x80000000 /* Enable */
> --
> 2.20.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] powerpc/fsl-pci: Fix Class Code of PCIe Root Port
2022-07-22 19:42 ` Bjorn Helgaas
@ 2022-07-25 12:24 ` Michael Ellerman
-1 siblings, 0 replies; 9+ messages in thread
From: Michael Ellerman @ 2022-07-25 12:24 UTC (permalink / raw)
To: Bjorn Helgaas, Pali Rohár
Cc: Benjamin Herrenschmidt, Paul Mackerras, Bjorn Helgaas, linux-pci,
linuxppc-dev, linux-kernel
Bjorn Helgaas <helgaas@kernel.org> writes:
> On Wed, Jul 06, 2022 at 12:10:43PM +0200, Pali Rohár wrote:
>> By default old pre-3.0 Freescale PCIe controllers reports invalid PCI Class
>> Code 0x0b20 for PCIe Root Port. It can be seen by lspci -b output on P2020
>> board which has this pre-3.0 controller:
>>
>> $ lspci -bvnn
>> 00:00.0 Power PC [0b20]: Freescale Semiconductor Inc P2020E [1957:0070] (rev 21)
>> !!! Invalid class 0b20 for header type 01
>> Capabilities: [4c] Express Root Port (Slot-), MSI 00
>>
>> Fix this issue by programming correct PCI Class Code 0x0604 for PCIe Root
>> Port to the Freescale specific PCIe register 0x474.
>>
>> With this change lspci -b output is:
>>
>> $ lspci -bvnn
>> 00:00.0 PCI bridge [0604]: Freescale Semiconductor Inc P2020E [1957:0070] (rev 21) (prog-if 00 [Normal decode])
>> Capabilities: [4c] Express Root Port (Slot-), MSI 00
>>
>> Without any "Invalid class" error. So class code was properly reflected
>> into standard (read-only) PCI register 0x08.
>>
>> Same fix is already implemented in U-Boot pcie_fsl.c driver in commit:
>> http://source.denx.de/u-boot/u-boot/-/commit/d18d06ac35229345a0af80977a408cfbe1d1015b
>>
>> Fix activated by U-Boot stay active also after booting Linux kernel.
>> But boards which use older U-Boot version without that fix are affected and
>> still require this fix.
>>
>> So implement this class code fix also in kernel fsl_pci.c driver.
>>
>> Cc: stable@vger.kernel.org
>> Signed-off-by: Pali Rohár <pali@kernel.org>
>
> I assume the powerpc folks will take care of this.
Will do.
cheers
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] powerpc/fsl-pci: Fix Class Code of PCIe Root Port
@ 2022-07-25 12:24 ` Michael Ellerman
0 siblings, 0 replies; 9+ messages in thread
From: Michael Ellerman @ 2022-07-25 12:24 UTC (permalink / raw)
To: Bjorn Helgaas, Pali Rohár
Cc: linux-kernel, Paul Mackerras, linux-pci, Bjorn Helgaas, linuxppc-dev
Bjorn Helgaas <helgaas@kernel.org> writes:
> On Wed, Jul 06, 2022 at 12:10:43PM +0200, Pali Rohár wrote:
>> By default old pre-3.0 Freescale PCIe controllers reports invalid PCI Class
>> Code 0x0b20 for PCIe Root Port. It can be seen by lspci -b output on P2020
>> board which has this pre-3.0 controller:
>>
>> $ lspci -bvnn
>> 00:00.0 Power PC [0b20]: Freescale Semiconductor Inc P2020E [1957:0070] (rev 21)
>> !!! Invalid class 0b20 for header type 01
>> Capabilities: [4c] Express Root Port (Slot-), MSI 00
>>
>> Fix this issue by programming correct PCI Class Code 0x0604 for PCIe Root
>> Port to the Freescale specific PCIe register 0x474.
>>
>> With this change lspci -b output is:
>>
>> $ lspci -bvnn
>> 00:00.0 PCI bridge [0604]: Freescale Semiconductor Inc P2020E [1957:0070] (rev 21) (prog-if 00 [Normal decode])
>> Capabilities: [4c] Express Root Port (Slot-), MSI 00
>>
>> Without any "Invalid class" error. So class code was properly reflected
>> into standard (read-only) PCI register 0x08.
>>
>> Same fix is already implemented in U-Boot pcie_fsl.c driver in commit:
>> http://source.denx.de/u-boot/u-boot/-/commit/d18d06ac35229345a0af80977a408cfbe1d1015b
>>
>> Fix activated by U-Boot stay active also after booting Linux kernel.
>> But boards which use older U-Boot version without that fix are affected and
>> still require this fix.
>>
>> So implement this class code fix also in kernel fsl_pci.c driver.
>>
>> Cc: stable@vger.kernel.org
>> Signed-off-by: Pali Rohár <pali@kernel.org>
>
> I assume the powerpc folks will take care of this.
Will do.
cheers
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] powerpc/fsl-pci: Fix Class Code of PCIe Root Port
2022-07-06 10:10 ` Pali Rohár
` (2 preceding siblings ...)
(?)
@ 2022-07-29 13:02 ` Michael Ellerman
-1 siblings, 0 replies; 9+ messages in thread
From: Michael Ellerman @ 2022-07-29 13:02 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Pali Rohár, Bjorn Helgaas
Cc: linux-pci, linuxppc-dev, linux-kernel
On Wed, 6 Jul 2022 12:10:43 +0200, Pali Rohár wrote:
> By default old pre-3.0 Freescale PCIe controllers reports invalid PCI Class
> Code 0x0b20 for PCIe Root Port. It can be seen by lspci -b output on P2020
> board which has this pre-3.0 controller:
>
> $ lspci -bvnn
> 00:00.0 Power PC [0b20]: Freescale Semiconductor Inc P2020E [1957:0070] (rev 21)
> !!! Invalid class 0b20 for header type 01
> Capabilities: [4c] Express Root Port (Slot-), MSI 00
>
> [...]
Applied to powerpc/next.
[1/1] powerpc/fsl-pci: Fix Class Code of PCIe Root Port
https://git.kernel.org/powerpc/c/0c551abfa004ce154d487d91777bf221c808a64f
cheers
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-07-29 13:21 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-07-06 10:10 [PATCH] powerpc/fsl-pci: Fix Class Code of PCIe Root Port Pali Rohár
2022-07-06 10:10 ` Pali Rohár
2022-07-21 22:18 ` Pali Rohár
2022-07-21 22:18 ` Pali Rohár
2022-07-22 19:42 ` Bjorn Helgaas
2022-07-22 19:42 ` Bjorn Helgaas
2022-07-25 12:24 ` Michael Ellerman
2022-07-25 12:24 ` Michael Ellerman
2022-07-29 13:02 ` Michael Ellerman
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