* [PATCH 0/2] Add DP MST DSC support to i915 @ 2022-08-15 17:35 ` Stanislav Lisovskiy 0 siblings, 0 replies; 8+ messages in thread From: Stanislav Lisovskiy @ 2022-08-15 17:35 UTC (permalink / raw) To: intel-gfx Cc: Stanislav.Lisovskiy, jani.nikula, manasi.d.navare, jani.saarinen, dri-devel Currently we have only DSC support for DP SST. Stanislav Lisovskiy (2): drm: Add missing DP DSC extended capability definitions. drm/i915: Add DSC support to MST path drivers/gpu/drm/i915/display/intel_dp.c | 76 ++++------ drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 157 ++++++++++++++++++++ include/drm/display/drm_dp.h | 10 +- 4 files changed, 215 insertions(+), 45 deletions(-) -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH 0/2] Add DP MST DSC support to i915 @ 2022-08-15 17:35 ` Stanislav Lisovskiy 0 siblings, 0 replies; 8+ messages in thread From: Stanislav Lisovskiy @ 2022-08-15 17:35 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, dri-devel Currently we have only DSC support for DP SST. Stanislav Lisovskiy (2): drm: Add missing DP DSC extended capability definitions. drm/i915: Add DSC support to MST path drivers/gpu/drm/i915/display/intel_dp.c | 76 ++++------ drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 157 ++++++++++++++++++++ include/drm/display/drm_dp.h | 10 +- 4 files changed, 215 insertions(+), 45 deletions(-) -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] drm: Add missing DP DSC extended capability definitions. 2022-08-15 17:35 ` [Intel-gfx] " Stanislav Lisovskiy @ 2022-08-15 17:35 ` Stanislav Lisovskiy -1 siblings, 0 replies; 8+ messages in thread From: Stanislav Lisovskiy @ 2022-08-15 17:35 UTC (permalink / raw) To: intel-gfx Cc: Stanislav.Lisovskiy, jani.nikula, manasi.d.navare, jani.saarinen, dri-devel Adding DP DSC register definitions, we might need for further DSC implementation, supporting MST and DP branch pass-through mode. v2: - Fixed checkpatch comment warning v3: - Removed function which is not yet used(Jani Nikula) Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- include/drm/display/drm_dp.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 9e3aff7e68bb..0d05e3172f96 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -239,6 +239,9 @@ #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) +# define DP_DSC_PASS_THROUGH_IS_SUPPORTED (1 << 1) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP (1 << 2) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3) #define DP_DSC_REV 0x061 # define DP_DSC_MAJOR_MASK (0xf << 0) @@ -277,12 +280,15 @@ #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) +# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1) #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 +# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK 0x06 +# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY 0x08 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 # define DP_DSC_RGB (1 << 0) @@ -344,11 +350,13 @@ # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) #define DP_DSC_BITS_PER_PIXEL_INC 0x06F +# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f +# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 -# define DP_DSC_BITS_PER_PIXEL_1 0x4 +# define DP_DSC_BITS_PER_PIXEL_1_1 0x4 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED 1 -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm: Add missing DP DSC extended capability definitions. @ 2022-08-15 17:35 ` Stanislav Lisovskiy 0 siblings, 0 replies; 8+ messages in thread From: Stanislav Lisovskiy @ 2022-08-15 17:35 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, dri-devel Adding DP DSC register definitions, we might need for further DSC implementation, supporting MST and DP branch pass-through mode. v2: - Fixed checkpatch comment warning v3: - Removed function which is not yet used(Jani Nikula) Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- include/drm/display/drm_dp.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 9e3aff7e68bb..0d05e3172f96 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -239,6 +239,9 @@ #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) +# define DP_DSC_PASS_THROUGH_IS_SUPPORTED (1 << 1) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP (1 << 2) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3) #define DP_DSC_REV 0x061 # define DP_DSC_MAJOR_MASK (0xf << 0) @@ -277,12 +280,15 @@ #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) +# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1) #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 +# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK 0x06 +# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY 0x08 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 # define DP_DSC_RGB (1 << 0) @@ -344,11 +350,13 @@ # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) #define DP_DSC_BITS_PER_PIXEL_INC 0x06F +# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f +# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 -# define DP_DSC_BITS_PER_PIXEL_1 0x4 +# define DP_DSC_BITS_PER_PIXEL_1_1 0x4 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED 1 -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path 2022-08-15 17:35 ` [Intel-gfx] " Stanislav Lisovskiy @ 2022-08-15 17:35 ` Stanislav Lisovskiy -1 siblings, 0 replies; 8+ messages in thread From: Stanislav Lisovskiy @ 2022-08-15 17:35 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula, dri-devel Whenever we are not able to get enough timeslots for required PBN, let's try to allocate those using DSC, just same way as we do for SST. v2: Removed intel_dp_mst_dsc_compute_config and refactored intel_dp_dsc_compute_config to support timeslots as a parameter(Ville Syrjälä) v3: - Rebased - Added a debug to see that we at least try reserving VCPI slots using DSC, because currently its not visible from the logs, thus making debugging more tricky. - Moved timeslots to numerator, where it should be. v4: - Call drm_dp_mst_atomic_check already during link config computation, because we need to know already by this moment if uncompressed amount of VCPI slots needed can fit, otherwise we need to use DSC. (thanks to Vinod Govindapillai for pointing this out) Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 76 ++++------ drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 157 ++++++++++++++++++++ 3 files changed, 206 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 32292c0be2bd..1f6dc52251c2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -116,7 +116,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) } static void intel_dp_unset_edid(struct intel_dp *intel_dp); -static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); /* Is link rate UHBR and thus 128b/132b? */ bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) @@ -687,11 +686,12 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915) return 6144 * 8; } -static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, - u32 link_clock, u32 lane_count, - u32 mode_clock, u32 mode_hdisplay, - bool bigjoiner, - u32 pipe_bpp) +u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, + u32 link_clock, u32 lane_count, + u32 mode_clock, u32 mode_hdisplay, + bool bigjoiner, + u32 pipe_bpp, + u32 timeslots) { u32 bits_per_pixel, max_bpp_small_joiner_ram; int i; @@ -702,8 +702,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, * for SST -> TimeSlotsPerMTP is 1, * for MST -> TimeSlotsPerMTP has to be calculated */ - bits_per_pixel = (link_clock * lane_count * 8) / + bits_per_pixel = (link_clock * lane_count * 8) * timeslots / intel_dp_mode_to_fec_clock(mode_clock); + drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel); /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / @@ -752,9 +753,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, return bits_per_pixel << 4; } -static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, - int mode_clock, int mode_hdisplay, - bool bigjoiner) +u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, + int mode_clock, int mode_hdisplay, + bool bigjoiner) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); u8 min_slice_count, i; @@ -961,8 +962,8 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, return MODE_OK; } -static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, - int hdisplay, int clock) +bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, + int hdisplay, int clock) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -1049,7 +1050,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, target_clock, mode->hdisplay, bigjoiner, - pipe_bpp) >> 4; + pipe_bpp, 1) >> 4; dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, target_clock, @@ -1354,7 +1355,7 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, return -EINVAL; } -static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) +int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); int i, num_bpc; @@ -1444,10 +1445,11 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, return drm_dsc_compute_rc_parameters(vdsc_cfg); } -static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state, - struct link_config_limits *limits) +int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state, + struct link_config_limits *limits, + int timeslots) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); @@ -1498,7 +1500,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, adjusted_mode->crtc_clock, adjusted_mode->crtc_hdisplay, pipe_config->bigjoiner_pipes, - pipe_bpp); + pipe_bpp, + timeslots); dsc_dp_slice_count = intel_dp_dsc_get_slice_count(intel_dp, adjusted_mode->crtc_clock, @@ -1510,41 +1513,26 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, return -EINVAL; } pipe_config->dsc.compressed_bpp = min_t(u16, - dsc_max_output_bpp >> 4, - pipe_config->pipe_bpp); + dsc_max_output_bpp >> 4, + pipe_config->pipe_bpp); pipe_config->dsc.slice_count = dsc_dp_slice_count; + drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n", + pipe_config->dsc.compressed_bpp, + pipe_config->dsc.slice_count); } - - /* As of today we support DSC for only RGB */ - if (intel_dp->force_dsc_bpp) { - if (intel_dp->force_dsc_bpp >= 8 && - intel_dp->force_dsc_bpp < pipe_bpp) { - drm_dbg_kms(&dev_priv->drm, - "DSC BPP forced to %d", - intel_dp->force_dsc_bpp); - pipe_config->dsc.compressed_bpp = - intel_dp->force_dsc_bpp; - } else { - drm_dbg_kms(&dev_priv->drm, - "Invalid DSC BPP %d", - intel_dp->force_dsc_bpp); - } - } - /* * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate * is greater than the maximum Cdclock and if slice count is even * then we need to use 2 VDSC instances. */ - if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq || - pipe_config->bigjoiner_pipes) { - if (pipe_config->dsc.slice_count < 2) { + if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) { + if (pipe_config->dsc.slice_count > 1) { + pipe_config->dsc.dsc_split = true; + } else { drm_dbg_kms(&dev_priv->drm, "Cannot split stream to use 2 VDSC instances\n"); return -EINVAL; } - - pipe_config->dsc.dsc_split = true; } ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config); @@ -1633,7 +1621,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, str_yes_no(ret), str_yes_no(joiner_needs_dsc), str_yes_no(intel_dp->force_dsc_en)); ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, - conn_state, &limits); + conn_state, &limits, 1); if (ret < 0) return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index a54902c713a3..c6539a6915e9 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -56,6 +56,11 @@ void intel_dp_encoder_flush_work(struct drm_encoder *encoder); int intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state); +int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state, + struct link_config_limits *limits, + int timeslots); bool intel_dp_is_edp(struct intel_dp *intel_dp); bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); @@ -96,6 +101,18 @@ void intel_read_dp_sdp(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, unsigned int type); bool intel_digital_port_connected(struct intel_encoder *encoder); +int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); +u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, + u32 link_clock, u32 lane_count, + u32 mode_clock, u32 mode_hdisplay, + bool bigjoiner, + u32 pipe_bpp, + u32 timeslots); +u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, + int mode_clock, int mode_hdisplay, + bool bigjoiner); +bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, + int hdisplay, int clock); static inline unsigned int intel_dp_unused_lane_mask(int lane_count) { diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 14d2a64193b2..b4d68c324e68 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -99,6 +99,84 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, return 0; } +static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + struct link_config_limits *limits) +{ + struct drm_atomic_state *state = crtc_state->uapi.state; + struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); + struct intel_dp *intel_dp = &intel_mst->primary->dp; + struct intel_connector *connector = + to_intel_connector(conn_state->connector); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + bool constant_n = drm_dp_has_quirk(&intel_dp->desc, + DP_DPCD_QUIRK_CONSTANT_N); + int bpp, slots = -EINVAL; + int i, num_bpc; + u8 dsc_bpc[3] = {0}; + int min_bpp, max_bpp; + u8 dsc_max_bpc; + + crtc_state->lane_count = limits->max_lane_count; + crtc_state->port_clock = limits->max_rate; + + /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ + if (DISPLAY_VER(i915) >= 12) + dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc); + else + dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc); + + max_bpp = min_t(u8, dsc_max_bpc * 3, limits->max_bpp); + min_bpp = limits->min_bpp; + + num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, + dsc_bpc); + for (i = 0; i < num_bpc; i++) { + if (max_bpp >= dsc_bpc[i] * 3) + if (min_bpp > dsc_bpc[i] * 3) + min_bpp = dsc_bpc[i] * 3; + } + + drm_dbg_kms(&i915->drm, "DSC Sink supported min bpp %d max bpp %d\n", + min_bpp, max_bpp); + + for (bpp = max_bpp; bpp >= min_bpp; bpp -= 2 * 3) { + crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, + bpp << 4, + true); + + slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr, + connector->port, + crtc_state->pbn, 0); + + drm_dbg_kms(&i915->drm, "Trying bpp %d got %d pbn %d slots\n", + bpp, crtc_state->pbn, slots); + + if (slots == -EDEADLK) + return slots; + if (slots >= 0) + break; + } + + if (slots < 0) { + drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n", + slots); + return slots; + } + + intel_link_compute_m_n(crtc_state->pipe_bpp, + crtc_state->lane_count, + adjusted_mode->crtc_clock, + crtc_state->port_clock, + &crtc_state->dp_m_n, + constant_n, crtc_state->fec_enable); + crtc_state->dp_m_n.tu = slots; + + return 0; +} static int intel_dp_mst_update_slots(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) @@ -127,6 +205,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, struct drm_connector_state *conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct drm_atomic_state *state = pipe_config->uapi.state; struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); struct intel_dp *intel_dp = &intel_mst->primary->dp; struct intel_connector *connector = @@ -175,6 +254,38 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, ret = intel_dp_mst_compute_link_config(encoder, pipe_config, conn_state, &limits); + + if (ret == -EDEADLK) + return ret; + + /* + * We need to check if VCPI slots allocated can actually fit already + * here, to decide whether we use DSC or not. + * If either intel_dp_mst_compute_link_config or that one fails, + * then we try DSC as last resort. + */ + if (!ret) + ret = drm_dp_mst_atomic_check(state); + + /* enable compression if the mode doesn't fit available BW */ + drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en); + if (ret || intel_dp->force_dsc_en) { + /* + * Try to get at least some timeslots and then see, if + * we can fit there with DSC. + */ + drm_dbg_kms(&dev_priv->drm, "Trying to find VCPI slots in DSC mode\n"); + + ret = intel_dp_dsc_mst_compute_link_config(encoder, pipe_config, + conn_state, &limits); + if (ret < 0) + return ret; + + ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, + conn_state, &limits, + pipe_config->dp_m_n.tu); + } + if (ret) return ret; @@ -713,6 +824,10 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; int max_rate, mode_rate, max_lanes, max_link_clock; int ret; + bool dsc = false, bigjoiner = false; + u16 dsc_max_output_bpp = 0; + u8 dsc_slice_count = 0; + int target_clock = mode->clock; if (drm_connector_is_unregistered(connector)) { *status = MODE_ERROR; @@ -750,6 +865,48 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, return 0; } + if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) { + bigjoiner = true; + max_dotclk *= 2; + } + + if (DISPLAY_VER(dev_priv) >= 10 && + drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { + /* + * TBD pass the connector BPC, + * for now U8_MAX so that max BPC on that platform would be picked + */ + int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); + + if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { + dsc_max_output_bpp = + intel_dp_dsc_get_output_bpp(dev_priv, + max_link_clock, + max_lanes, + target_clock, + mode->hdisplay, + bigjoiner, + pipe_bpp, 1) >> 4; + dsc_slice_count = + intel_dp_dsc_get_slice_count(intel_dp, + target_clock, + mode->hdisplay, + bigjoiner); + } + + dsc = dsc_max_output_bpp && dsc_slice_count; + } + + /* + * Big joiner configuration needs DSC for TGL which is not true for + * XE_LPD where uncompressed joiner is supported. + */ + if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc) + return MODE_CLOCK_HIGH; + + if (mode_rate > max_rate && !dsc) + return MODE_CLOCK_HIGH; + *status = intel_mode_valid_max_plane_size(dev_priv, mode, false); return 0; } -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2] drm/i915: Add DSC support to MST path @ 2022-08-15 17:35 ` Stanislav Lisovskiy 0 siblings, 0 replies; 8+ messages in thread From: Stanislav Lisovskiy @ 2022-08-15 17:35 UTC (permalink / raw) To: intel-gfx Cc: Stanislav.Lisovskiy, jani.nikula, manasi.d.navare, jani.saarinen, dri-devel Whenever we are not able to get enough timeslots for required PBN, let's try to allocate those using DSC, just same way as we do for SST. v2: Removed intel_dp_mst_dsc_compute_config and refactored intel_dp_dsc_compute_config to support timeslots as a parameter(Ville Syrjälä) v3: - Rebased - Added a debug to see that we at least try reserving VCPI slots using DSC, because currently its not visible from the logs, thus making debugging more tricky. - Moved timeslots to numerator, where it should be. v4: - Call drm_dp_mst_atomic_check already during link config computation, because we need to know already by this moment if uncompressed amount of VCPI slots needed can fit, otherwise we need to use DSC. (thanks to Vinod Govindapillai for pointing this out) Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 76 ++++------ drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 157 ++++++++++++++++++++ 3 files changed, 206 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 32292c0be2bd..1f6dc52251c2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -116,7 +116,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) } static void intel_dp_unset_edid(struct intel_dp *intel_dp); -static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); /* Is link rate UHBR and thus 128b/132b? */ bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) @@ -687,11 +686,12 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915) return 6144 * 8; } -static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, - u32 link_clock, u32 lane_count, - u32 mode_clock, u32 mode_hdisplay, - bool bigjoiner, - u32 pipe_bpp) +u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, + u32 link_clock, u32 lane_count, + u32 mode_clock, u32 mode_hdisplay, + bool bigjoiner, + u32 pipe_bpp, + u32 timeslots) { u32 bits_per_pixel, max_bpp_small_joiner_ram; int i; @@ -702,8 +702,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, * for SST -> TimeSlotsPerMTP is 1, * for MST -> TimeSlotsPerMTP has to be calculated */ - bits_per_pixel = (link_clock * lane_count * 8) / + bits_per_pixel = (link_clock * lane_count * 8) * timeslots / intel_dp_mode_to_fec_clock(mode_clock); + drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel); /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / @@ -752,9 +753,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, return bits_per_pixel << 4; } -static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, - int mode_clock, int mode_hdisplay, - bool bigjoiner) +u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, + int mode_clock, int mode_hdisplay, + bool bigjoiner) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); u8 min_slice_count, i; @@ -961,8 +962,8 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, return MODE_OK; } -static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, - int hdisplay, int clock) +bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, + int hdisplay, int clock) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -1049,7 +1050,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, target_clock, mode->hdisplay, bigjoiner, - pipe_bpp) >> 4; + pipe_bpp, 1) >> 4; dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, target_clock, @@ -1354,7 +1355,7 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, return -EINVAL; } -static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) +int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); int i, num_bpc; @@ -1444,10 +1445,11 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, return drm_dsc_compute_rc_parameters(vdsc_cfg); } -static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state, - struct link_config_limits *limits) +int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state, + struct link_config_limits *limits, + int timeslots) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); @@ -1498,7 +1500,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, adjusted_mode->crtc_clock, adjusted_mode->crtc_hdisplay, pipe_config->bigjoiner_pipes, - pipe_bpp); + pipe_bpp, + timeslots); dsc_dp_slice_count = intel_dp_dsc_get_slice_count(intel_dp, adjusted_mode->crtc_clock, @@ -1510,41 +1513,26 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, return -EINVAL; } pipe_config->dsc.compressed_bpp = min_t(u16, - dsc_max_output_bpp >> 4, - pipe_config->pipe_bpp); + dsc_max_output_bpp >> 4, + pipe_config->pipe_bpp); pipe_config->dsc.slice_count = dsc_dp_slice_count; + drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n", + pipe_config->dsc.compressed_bpp, + pipe_config->dsc.slice_count); } - - /* As of today we support DSC for only RGB */ - if (intel_dp->force_dsc_bpp) { - if (intel_dp->force_dsc_bpp >= 8 && - intel_dp->force_dsc_bpp < pipe_bpp) { - drm_dbg_kms(&dev_priv->drm, - "DSC BPP forced to %d", - intel_dp->force_dsc_bpp); - pipe_config->dsc.compressed_bpp = - intel_dp->force_dsc_bpp; - } else { - drm_dbg_kms(&dev_priv->drm, - "Invalid DSC BPP %d", - intel_dp->force_dsc_bpp); - } - } - /* * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate * is greater than the maximum Cdclock and if slice count is even * then we need to use 2 VDSC instances. */ - if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq || - pipe_config->bigjoiner_pipes) { - if (pipe_config->dsc.slice_count < 2) { + if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) { + if (pipe_config->dsc.slice_count > 1) { + pipe_config->dsc.dsc_split = true; + } else { drm_dbg_kms(&dev_priv->drm, "Cannot split stream to use 2 VDSC instances\n"); return -EINVAL; } - - pipe_config->dsc.dsc_split = true; } ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config); @@ -1633,7 +1621,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, str_yes_no(ret), str_yes_no(joiner_needs_dsc), str_yes_no(intel_dp->force_dsc_en)); ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, - conn_state, &limits); + conn_state, &limits, 1); if (ret < 0) return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index a54902c713a3..c6539a6915e9 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -56,6 +56,11 @@ void intel_dp_encoder_flush_work(struct drm_encoder *encoder); int intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state); +int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state, + struct link_config_limits *limits, + int timeslots); bool intel_dp_is_edp(struct intel_dp *intel_dp); bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); @@ -96,6 +101,18 @@ void intel_read_dp_sdp(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, unsigned int type); bool intel_digital_port_connected(struct intel_encoder *encoder); +int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); +u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, + u32 link_clock, u32 lane_count, + u32 mode_clock, u32 mode_hdisplay, + bool bigjoiner, + u32 pipe_bpp, + u32 timeslots); +u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, + int mode_clock, int mode_hdisplay, + bool bigjoiner); +bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, + int hdisplay, int clock); static inline unsigned int intel_dp_unused_lane_mask(int lane_count) { diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 14d2a64193b2..b4d68c324e68 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -99,6 +99,84 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, return 0; } +static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + struct link_config_limits *limits) +{ + struct drm_atomic_state *state = crtc_state->uapi.state; + struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); + struct intel_dp *intel_dp = &intel_mst->primary->dp; + struct intel_connector *connector = + to_intel_connector(conn_state->connector); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + bool constant_n = drm_dp_has_quirk(&intel_dp->desc, + DP_DPCD_QUIRK_CONSTANT_N); + int bpp, slots = -EINVAL; + int i, num_bpc; + u8 dsc_bpc[3] = {0}; + int min_bpp, max_bpp; + u8 dsc_max_bpc; + + crtc_state->lane_count = limits->max_lane_count; + crtc_state->port_clock = limits->max_rate; + + /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ + if (DISPLAY_VER(i915) >= 12) + dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc); + else + dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc); + + max_bpp = min_t(u8, dsc_max_bpc * 3, limits->max_bpp); + min_bpp = limits->min_bpp; + + num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, + dsc_bpc); + for (i = 0; i < num_bpc; i++) { + if (max_bpp >= dsc_bpc[i] * 3) + if (min_bpp > dsc_bpc[i] * 3) + min_bpp = dsc_bpc[i] * 3; + } + + drm_dbg_kms(&i915->drm, "DSC Sink supported min bpp %d max bpp %d\n", + min_bpp, max_bpp); + + for (bpp = max_bpp; bpp >= min_bpp; bpp -= 2 * 3) { + crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, + bpp << 4, + true); + + slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr, + connector->port, + crtc_state->pbn, 0); + + drm_dbg_kms(&i915->drm, "Trying bpp %d got %d pbn %d slots\n", + bpp, crtc_state->pbn, slots); + + if (slots == -EDEADLK) + return slots; + if (slots >= 0) + break; + } + + if (slots < 0) { + drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n", + slots); + return slots; + } + + intel_link_compute_m_n(crtc_state->pipe_bpp, + crtc_state->lane_count, + adjusted_mode->crtc_clock, + crtc_state->port_clock, + &crtc_state->dp_m_n, + constant_n, crtc_state->fec_enable); + crtc_state->dp_m_n.tu = slots; + + return 0; +} static int intel_dp_mst_update_slots(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) @@ -127,6 +205,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, struct drm_connector_state *conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct drm_atomic_state *state = pipe_config->uapi.state; struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); struct intel_dp *intel_dp = &intel_mst->primary->dp; struct intel_connector *connector = @@ -175,6 +254,38 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, ret = intel_dp_mst_compute_link_config(encoder, pipe_config, conn_state, &limits); + + if (ret == -EDEADLK) + return ret; + + /* + * We need to check if VCPI slots allocated can actually fit already + * here, to decide whether we use DSC or not. + * If either intel_dp_mst_compute_link_config or that one fails, + * then we try DSC as last resort. + */ + if (!ret) + ret = drm_dp_mst_atomic_check(state); + + /* enable compression if the mode doesn't fit available BW */ + drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en); + if (ret || intel_dp->force_dsc_en) { + /* + * Try to get at least some timeslots and then see, if + * we can fit there with DSC. + */ + drm_dbg_kms(&dev_priv->drm, "Trying to find VCPI slots in DSC mode\n"); + + ret = intel_dp_dsc_mst_compute_link_config(encoder, pipe_config, + conn_state, &limits); + if (ret < 0) + return ret; + + ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, + conn_state, &limits, + pipe_config->dp_m_n.tu); + } + if (ret) return ret; @@ -713,6 +824,10 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; int max_rate, mode_rate, max_lanes, max_link_clock; int ret; + bool dsc = false, bigjoiner = false; + u16 dsc_max_output_bpp = 0; + u8 dsc_slice_count = 0; + int target_clock = mode->clock; if (drm_connector_is_unregistered(connector)) { *status = MODE_ERROR; @@ -750,6 +865,48 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, return 0; } + if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) { + bigjoiner = true; + max_dotclk *= 2; + } + + if (DISPLAY_VER(dev_priv) >= 10 && + drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { + /* + * TBD pass the connector BPC, + * for now U8_MAX so that max BPC on that platform would be picked + */ + int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); + + if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { + dsc_max_output_bpp = + intel_dp_dsc_get_output_bpp(dev_priv, + max_link_clock, + max_lanes, + target_clock, + mode->hdisplay, + bigjoiner, + pipe_bpp, 1) >> 4; + dsc_slice_count = + intel_dp_dsc_get_slice_count(intel_dp, + target_clock, + mode->hdisplay, + bigjoiner); + } + + dsc = dsc_max_output_bpp && dsc_slice_count; + } + + /* + * Big joiner configuration needs DSC for TGL which is not true for + * XE_LPD where uncompressed joiner is supported. + */ + if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc) + return MODE_CLOCK_HIGH; + + if (mode_rate > max_rate && !dsc) + return MODE_CLOCK_HIGH; + *status = intel_mode_valid_max_plane_size(dev_priv, mode, false); return 0; } -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Add DP MST DSC support to i915 (rev6) 2022-08-15 17:35 ` [Intel-gfx] " Stanislav Lisovskiy ` (2 preceding siblings ...) (?) @ 2022-08-15 18:55 ` Patchwork -1 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2022-08-15 18:55 UTC (permalink / raw) To: Stanislav Lisovskiy; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 6525 bytes --] == Series Details == Series: Add DP MST DSC support to i915 (rev6) URL : https://patchwork.freedesktop.org/series/101492/ State : success == Summary == CI Bug Log - changes from CI_DRM_11989 -> Patchwork_101492v6 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/index.html Participating hosts (29 -> 29) ------------------------------ Additional (1): bat-dg2-9 Missing (1): bat-rpls-2 Known issues ------------ Here are the changes found in Patchwork_101492v6 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live@gt_heartbeat: - fi-bdw-5557u: [PASS][1] -> [DMESG-FAIL][2] ([i915#5334]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@hangcheck: - bat-dg1-6: [PASS][3] -> [DMESG-FAIL][4] ([i915#4494] / [i915#4957]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/bat-dg1-6/igt@i915_selftest@live@hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/bat-dg1-6/igt@i915_selftest@live@hangcheck.html * igt@i915_suspend@basic-s2idle-without-i915: - fi-bdw-gvtdvm: NOTRUN -> [INCOMPLETE][5] ([i915#4817]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/fi-bdw-gvtdvm/igt@i915_suspend@basic-s2idle-without-i915.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-bsw-kefka: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/fi-bsw-kefka/igt@kms_chamelium@common-hpd-after-suspend.html - fi-apl-guc: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/fi-apl-guc/igt@kms_chamelium@common-hpd-after-suspend.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions: - fi-bsw-kefka: [PASS][8] -> [FAIL][9] ([i915#6298]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html #### Possible fixes #### * igt@i915_selftest@live@execlists: - fi-bdw-gvtdvm: [INCOMPLETE][10] ([i915#2940]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/fi-bdw-gvtdvm/igt@i915_selftest@live@execlists.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/fi-bdw-gvtdvm/igt@i915_selftest@live@execlists.html - fi-bsw-kefka: [INCOMPLETE][12] ([i915#2940]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/fi-bsw-kefka/igt@i915_selftest@live@execlists.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/fi-bsw-kefka/igt@i915_selftest@live@execlists.html * igt@i915_selftest@live@hangcheck: - {fi-ehl-2}: [INCOMPLETE][14] ([i915#6106]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/fi-ehl-2/igt@i915_selftest@live@hangcheck.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/fi-ehl-2/igt@i915_selftest@live@hangcheck.html * igt@i915_selftest@live@reset: - fi-apl-guc: [INCOMPLETE][16] -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/fi-apl-guc/igt@i915_selftest@live@reset.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/fi-apl-guc/igt@i915_selftest@live@reset.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940 [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215 [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494 [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579 [i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817 [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873 [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957 [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190 [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#6106]: https://gitlab.freedesktop.org/drm/intel/issues/6106 [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298 Build changes ------------- * Linux: CI_DRM_11989 -> Patchwork_101492v6 CI-20190529: 20190529 CI_DRM_11989: 8953e41fa70d4507c6f5508e030347f7eda3ba8a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6625: d47beef9b01595f721c584070940c95be1cf11e8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_101492v6: 8953e41fa70d4507c6f5508e030347f7eda3ba8a @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 29c2d35807d3 drm/i915: Add DSC support to MST path aa6602a6db13 drm: Add missing DP DSC extended capability definitions. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/index.html [-- Attachment #2: Type: text/html, Size: 6357 bytes --] ^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Add DP MST DSC support to i915 (rev6) 2022-08-15 17:35 ` [Intel-gfx] " Stanislav Lisovskiy ` (3 preceding siblings ...) (?) @ 2022-08-16 5:13 ` Patchwork -1 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2022-08-16 5:13 UTC (permalink / raw) To: Stanislav Lisovskiy; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 29467 bytes --] == Series Details == Series: Add DP MST DSC support to i915 (rev6) URL : https://patchwork.freedesktop.org/series/101492/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11989_full -> Patchwork_101492v6_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_101492v6_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_101492v6_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 12) ------------------------------ Additional (2): shard-dg1 shard-tglu Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_101492v6_full: ### IGT changes ### #### Possible regressions #### * igt@device_reset@unbind-reset-rebind: - shard-apl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-apl3/igt@device_reset@unbind-reset-rebind.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-apl7/igt@device_reset@unbind-reset-rebind.html #### Warnings #### * igt@gem_eio@in-flight-suspend: - shard-apl: [DMESG-WARN][3] ([i915#180]) -> [CRASH][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-apl1/igt@gem_eio@in-flight-suspend.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-apl6/igt@gem_eio@in-flight-suspend.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@i915_pm_freq_mult@media-freq@gt0: - {shard-tglu}: NOTRUN -> [SKIP][5] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-tglu-2/igt@i915_pm_freq_mult@media-freq@gt0.html * igt@kms_vblank@pipe-c-ts-continuation-modeset-hang: - {shard-dg1}: NOTRUN -> [SKIP][6] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-dg1-17/igt@kms_vblank@pipe-c-ts-continuation-modeset-hang.html Known issues ------------ Here are the changes found in Patchwork_101492v6_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +6 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vcs0.html * igt@gem_exec_balancer@parallel-contexts: - shard-iclb: [PASS][9] -> [SKIP][10] ([i915#4525]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-iclb1/igt@gem_exec_balancer@parallel-contexts.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-iclb8/igt@gem_exec_balancer@parallel-contexts.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-tglb2/igt@gem_exec_fair@basic-pace-solo@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-tglb3/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#2842]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-kbl7/igt@gem_exec_fair@basic-pace@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-kbl4/igt@gem_exec_fair@basic-pace@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][15] ([i915#2842]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs1.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][16] -> [FAIL][17] ([i915#2842]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-iclb2/igt@gem_exec_fair@basic-throttle@rcs0.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@gem_lmem_swapping@heavy-multi: - shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-skl7/igt@gem_lmem_swapping@heavy-multi.html * igt@i915_pm_dc@dc9-dpms: - shard-iclb: [PASS][19] -> [SKIP][20] ([i915#4281]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-iclb6/igt@i915_pm_dc@dc9-dpms.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html * igt@i915_selftest@live@gt_pm: - shard-skl: NOTRUN -> [DMESG-FAIL][21] ([i915#1886]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-skl7/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@hangcheck: - shard-snb: [PASS][22] -> [INCOMPLETE][23] ([i915#3921]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-snb7/igt@i915_selftest@live@hangcheck.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-snb2/igt@i915_selftest@live@hangcheck.html * igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1: - shard-skl: [PASS][24] -> [FAIL][25] ([i915#2521]) +1 similar issue [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-skl10/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-skl1/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc: - shard-skl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3886]) +2 similar issues [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-skl7/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html * igt@kms_cdclk@mode-transition-all-outputs: - shard-apl: NOTRUN -> [SKIP][27] ([fdo#109271]) +18 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-apl3/igt@kms_cdclk@mode-transition-all-outputs.html * igt@kms_chamelium@dp-edid-read: - shard-skl: NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111827]) +1 similar issue [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-skl7/igt@kms_chamelium@dp-edid-read.html * igt@kms_chamelium@dp-frame-dump: - shard-apl: NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-apl3/igt@kms_chamelium@dp-frame-dump.html * igt@kms_flip@2x-flip-vs-expired-vblank: - shard-skl: NOTRUN -> [SKIP][30] ([fdo#109271]) +30 similar issues [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-skl10/igt@kms_flip@2x-flip-vs-expired-vblank.html * igt@kms_flip@flip-vs-expired-vblank@a-edp1: - shard-skl: [PASS][31] -> [FAIL][32] ([i915#2122]) +2 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-skl9/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html * igt@kms_flip@flip-vs-expired-vblank@c-edp1: - shard-skl: [PASS][33] -> [FAIL][34] ([i915#79]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-skl9/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html * igt@kms_flip@flip-vs-suspend@c-dp1: - shard-apl: [PASS][35] -> [DMESG-WARN][36] ([i915#180]) +4 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-apl4/igt@kms_flip@flip-vs-suspend@c-dp1.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-apl3/igt@kms_flip@flip-vs-suspend@c-dp1.html * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling@pipe-a-default-mode: - shard-iclb: NOTRUN -> [SKIP][37] ([i915#2672]) +5 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode: - shard-iclb: NOTRUN -> [SKIP][38] ([i915#2672] / [i915#3555]) +1 similar issue [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode.html * igt@kms_plane_alpha_blend@pipe-c-alpha-basic: - shard-apl: NOTRUN -> [FAIL][39] ([fdo#108145] / [i915#265]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-apl3/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1: - shard-iclb: [PASS][40] -> [SKIP][41] ([i915#5176]) +1 similar issue [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-iclb5/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-iclb3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1: - shard-iclb: [PASS][42] -> [SKIP][43] ([i915#5235]) +2 similar issues [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-iclb7/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-iclb2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-edp-1.html * igt@kms_psr2_su@page_flip-xrgb8888: - shard-apl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#658]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-apl3/igt@kms_psr2_su@page_flip-xrgb8888.html * igt@kms_psr@psr2_sprite_render: - shard-iclb: [PASS][45] -> [SKIP][46] ([fdo#109441]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-iclb2/igt@kms_psr@psr2_sprite_render.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-iclb5/igt@kms_psr@psr2_sprite_render.html * igt@sysfs_clients@split-50: - shard-apl: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#2994]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-apl3/igt@sysfs_clients@split-50.html #### Possible fixes #### * igt@gem_eio@in-flight-1us: - shard-skl: [TIMEOUT][48] ([i915#3063]) -> [PASS][49] [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-skl7/igt@gem_eio@in-flight-1us.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-skl10/igt@gem_eio@in-flight-1us.html * igt@gem_exec_balancer@parallel-out-fence: - shard-iclb: [SKIP][50] ([i915#4525]) -> [PASS][51] [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-iclb5/igt@gem_exec_balancer@parallel-out-fence.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-iclb4/igt@gem_exec_balancer@parallel-out-fence.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-apl: [FAIL][52] ([i915#2842]) -> [PASS][53] [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-apl1/igt@gem_exec_fair@basic-pace-share@rcs0.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-apl1/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-glk: [FAIL][54] ([i915#2842]) -> [PASS][55] [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-glk6/igt@gem_exec_fair@basic-pace@rcs0.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-glk9/igt@gem_exec_fair@basic-pace@rcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [FAIL][56] ([i915#2842]) -> [PASS][57] +1 similar issue [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-kbl7/igt@gem_exec_fair@basic-pace@vecs0.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html * igt@gem_exec_suspend@basic-s3@smem: - shard-apl: [DMESG-WARN][58] ([i915#180]) -> [PASS][59] [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-apl3/igt@gem_exec_suspend@basic-s3@smem.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-apl3/igt@gem_exec_suspend@basic-s3@smem.html * igt@i915_pm_rpm@i2c: - shard-apl: [DMESG-WARN][60] ([i915#62]) -> [PASS][61] +43 similar issues [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-apl4/igt@i915_pm_rpm@i2c.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-apl4/igt@i915_pm_rpm@i2c.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip: - shard-iclb: [FAIL][62] ([i915#1888]) -> [PASS][63] [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-iclb1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-iclb6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html * igt@kms_flip@flip-vs-suspend@a-dp1: - shard-kbl: [DMESG-WARN][64] ([i915#180]) -> [PASS][65] [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-kbl4/igt@kms_flip@flip-vs-suspend@a-dp1.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-kbl7/igt@kms_flip@flip-vs-suspend@a-dp1.html * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-edp-1: - shard-skl: [INCOMPLETE][66] ([i915#4939]) -> [PASS][67] [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-skl7/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-edp-1.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-skl7/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-edp-1.html * igt@kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [SKIP][68] ([fdo#109441]) -> [PASS][69] [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-iclb7/igt@kms_psr@psr2_primary_mmap_gtt.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html * igt@kms_psr_stress_test@flip-primary-invalidate-overlay: - shard-tglb: [SKIP][70] ([i915#5519]) -> [PASS][71] [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-tglb2/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-tglb7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html - shard-iclb: [SKIP][72] ([i915#5519]) -> [PASS][73] +1 similar issue [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-iclb1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-iclb8/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html #### Warnings #### * igt@gem_eio@unwedge-stress: - shard-tglb: [TIMEOUT][74] ([i915#3063]) -> [FAIL][75] ([i915#5784]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-tglb7/igt@gem_eio@unwedge-stress.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-tglb2/igt@gem_eio@unwedge-stress.html * igt@gem_exec_balancer@parallel-ordering: - shard-iclb: [SKIP][76] ([i915#4525]) -> [FAIL][77] ([i915#6117]) [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-iclb7/igt@gem_exec_balancer@parallel-ordering.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max: - shard-apl: [DMESG-FAIL][78] ([fdo#108145] / [i915#62]) -> [FAIL][79] ([fdo#108145] / [i915#265]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-apl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-apl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html * igt@kms_psr2_sf@plane-move-sf-dmg-area: - shard-iclb: [SKIP][80] ([i915#2920]) -> [SKIP][81] ([fdo#111068] / [i915#658]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-iclb5/igt@kms_psr2_sf@plane-move-sf-dmg-area.html * igt@runner@aborted: - shard-apl: ([FAIL][82], [FAIL][83], [FAIL][84], [FAIL][85]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][86], [FAIL][87], [FAIL][88]) ([i915#180] / [i915#4312] / [i915#5257]) [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-apl1/igt@runner@aborted.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-apl4/igt@runner@aborted.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-apl3/igt@runner@aborted.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11989/shard-apl4/igt@runner@aborted.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-apl8/igt@runner@aborted.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-apl3/igt@runner@aborted.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/shard-apl3/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303 [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307 [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312 [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313 [fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644 [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054 [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283 [i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755 [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410 [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433 [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681 [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705 [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280 [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856 [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002 [i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063 [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299 [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323 [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361 [i915#3376]: https://gitlab.freedesktop.org/drm/intel/issues/3376 [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469 [i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528 [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742 [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804 [i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826 [i915#3828]: https://gitlab.freedesktop.org/drm/intel/issues/3828 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 [i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938 [i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952 [i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966 [i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016 [i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036 [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349 [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387 [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525 [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771 [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812 [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833 [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852 [i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853 [i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855 [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859 [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860 [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873 [i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874 [i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877 [i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879 [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880 [i915#4883]: https://gitlab.freedesktop.org/drm/intel/issues/4883 [i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893 [i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939 [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287 [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288 [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289 [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439 [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461 [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519 [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563 [i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723 [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784 [i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982 [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227 [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230 [i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245 [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268 [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301 [i915#6331]: https://gitlab.freedesktop.org/drm/intel/issues/6331 [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334 [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335 [i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344 [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433 [i915#6463]: https://gitlab.freedesktop.org/drm/intel/issues/6463 [i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493 [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 Build changes ------------- * Linux: CI_DRM_11989 -> Patchwork_101492v6 CI-20190529: 20190529 CI_DRM_11989: 8953e41fa70d4507c6f5508e030347f7eda3ba8a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6625: d47beef9b01595f721c584070940c95be1cf11e8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_101492v6: 8953e41fa70d4507c6f5508e030347f7eda3ba8a @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v6/index.html [-- Attachment #2: Type: text/html, Size: 25836 bytes --] ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-08-16 5:13 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-08-15 17:35 [PATCH 0/2] Add DP MST DSC support to i915 Stanislav Lisovskiy 2022-08-15 17:35 ` [Intel-gfx] " Stanislav Lisovskiy 2022-08-15 17:35 ` [PATCH 1/2] drm: Add missing DP DSC extended capability definitions Stanislav Lisovskiy 2022-08-15 17:35 ` [Intel-gfx] " Stanislav Lisovskiy 2022-08-15 17:35 ` [Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path Stanislav Lisovskiy 2022-08-15 17:35 ` Stanislav Lisovskiy 2022-08-15 18:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Add DP MST DSC support to i915 (rev6) Patchwork 2022-08-16 5:13 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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