All of lore.kernel.org
 help / color / mirror / Atom feed
* [Intel-gfx] [PATCH 0/3] Enable YCbCr420 for VDSC
@ 2022-09-21 10:55 Kandpal, Suraj
  2022-09-21 10:55 ` [Intel-gfx] [PATCH 1/3] drm/i915/dp: Check if DSC supports the given output_format Kandpal, Suraj
                   ` (9 more replies)
  0 siblings, 10 replies; 18+ messages in thread
From: Kandpal, Suraj @ 2022-09-21 10:55 UTC (permalink / raw)
  To: intel-gfx

This patch series aims to enable the YCbCr420 format
for DSC. Changes are mostly compute params related for
hdmi,dp and dsi along with the addition of new rc_tables
for native_420 and corresponding changes to macros used to
fetch them.

Ankit Nautiyal (1):
  drm/i915/dp: Check if DSC supports the given output_format

Suraj Kandpal (2):
  drm/i915/vdsc: Enable YCbCr420 for VDSC
  drm/i915/display: Fill in native_420 field

 drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
 drivers/gpu/drm/i915/display/intel_dp.c       |  32 ++-
 .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
 .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     |  20 +-
 5 files changed, 224 insertions(+), 21 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH v4 0/4] Enable YCbCr420 for VDSC
@ 2022-10-14 15:26 Suraj Kandpal
  2022-10-14 16:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
  0 siblings, 1 reply; 18+ messages in thread
From: Suraj Kandpal @ 2022-10-14 15:26 UTC (permalink / raw)
  To: intel-gfx

This patch series aims to enable the YCbCr420 format
for DSC. Changes are mostly compute params related for
hdmi,dp and dsi along with the addition of new rc_tables
for native_420 and corresponding changes to macros used to
fetch them.

---v2
-adding fields missed for vdsc_cfg [Vandita]
-adding corresponding registers and writing to the [Vandita]

---v3
-adding 11 bit left shift missed in nsl_bpg_offset calculation

---v4
-adding display version check before writing in new pps register

Ankit Nautiyal (1):
  drm/i915/dp: Check if DSC supports the given output_format

Kandpal, Suraj (2):
  drm/i915: Adding the new registers for DSC
  drm/i915: Fill in native_420 field

Suraj Kandpal (1):
  drm/i915: Enable YCbCr420 for VDSC

 drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
 drivers/gpu/drm/i915/display/intel_dp.c       |  32 ++-
 .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
 .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     |  78 +++++++-
 drivers/gpu/drm/i915/i915_reg.h               |  28 +++
 6 files changed, 308 insertions(+), 23 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH v5 0/8] Enable YCbCr420 for VDSC
@ 2022-10-28 11:19 Swati Sharma
  2022-10-28 14:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
  0 siblings, 1 reply; 18+ messages in thread
From: Swati Sharma @ 2022-10-28 11:19 UTC (permalink / raw)
  To: intel-gfx

This patch series aims to enable the YCbCr420 format
for DSC. Changes are mostly compute params related for
hdmi,dp and dsi along with the addition of new rc_tables
for native_420 and corresponding changes to macros used to
fetch them.

---v2
-adding fields missed for vdsc_cfg [Vandita]
-adding corresponding registers and writing to the [Vandita]

---v3
-adding 11 bit left shift missed in nsl_bpg_offset calculation

---v4
-adding display version check before writing in new pps register

---v5
-added helper to check if sink supports given format with DSC
-added debugfs entry to enforce DSC with YCbCr420 format only

Ankit Nautiyal (2):
  drm/dp_helper: Add helper to check if the sink supports given format
    with DSC
  drm/i915/dp: Check if DSC supports the given output_format

Suraj Kandpal (3):
  drm/i915: Adding the new registers for DSC
  drm/i915: Enable YCbCr420 for VDSC
  drm/i915: Fill in native_420 field

Swati Sharma (3):
  drm/i915/dsc: Add debugfs entry to validate DSC YCbCr420
  drm/i915/dsc: Allow DSC only with YCbCr420 format when forced from
    debugfs
  drm/i915: Code styling fixes

 drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
 .../drm/i915/display/intel_display_debugfs.c  |  90 ++++++++-
 .../drm/i915/display/intel_display_types.h    |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  34 +++-
 .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
 .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     |  78 +++++++-
 drivers/gpu/drm/i915/i915_reg.h               |  28 +++
 include/drm/display/drm_dp_helper.h           |   6 +
 9 files changed, 404 insertions(+), 26 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH v5 0/8] Enable YCbCr420 for VDSC
@ 2022-11-07  7:39 Suraj Kandpal
  2022-11-07  9:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
  0 siblings, 1 reply; 18+ messages in thread
From: Suraj Kandpal @ 2022-11-07  7:39 UTC (permalink / raw)
  To: intel-gfx

This patch series aims to enable the YCbCr420 format
for DSC. Changes are mostly compute params related for
hdmi,dp and dsi along with the addition of new rc_tables
for native_420 and corresponding changes to macros used to
fetch them.

---v2
-adding fields missed for vdsc_cfg [Vandita]
-adding corresponding registers and writing to the [Vandita]

---v3
-adding 11 bit left shift missed in nsl_bpg_offset calculation

---v4
-adding display version check before writing in new pps register

---v5
-added helper to check if sink supports given format with DSC
-added debugfs entry to enforce DSC with YCbCr420 format only

Ankit Nautiyal (2):
  drm/dp_helper: Add helper to check if the sink supports given format
    with DSC
  drm/i915/dp: Check if DSC supports the given output_format

Suraj Kandpal (3):
  drm/i915: Adding the new registers for DSC
  drm/i915: Enable YCbCr420 for VDSC
  drm/i915: Fill in native_420 field

Swati Sharma (3):
  drm/i915/dsc: Add debugfs entry to validate DSC YCbCr420
  drm/i915/dsc: Allow DSC only with YCbCr420 format when forced from
    debugfs
  drm/i915: Code styling fixes

 drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
 .../drm/i915/display/intel_display_debugfs.c  |  91 ++++++++-
 .../drm/i915/display/intel_display_types.h    |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  35 +++-
 .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
 .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     |  78 +++++++-
 drivers/gpu/drm/i915/i915_reg.h               |  28 +++
 include/drm/display/drm_dp_helper.h           |   6 +
 9 files changed, 406 insertions(+), 26 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH v7 0/6] Enable YCbCr420 for VDSC
@ 2023-01-13  5:52 Suraj Kandpal
  2023-01-13  6:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
  0 siblings, 1 reply; 18+ messages in thread
From: Suraj Kandpal @ 2023-01-13  5:52 UTC (permalink / raw)
  To: intel-gfx

This patch series aims to enable the YCbCr420 format
for DSC. Changes are mostly compute params related for
hdmi,dp and dsi along with the addition of new rc_tables
for native_420 and corresponding changes to macros used to
fetch them.

---v2
-add fields missed for vdsc_cfg [Vandita]
-add corresponding registers and writing to the [Vandita]

---v3
-add 11 bit left shift missed in nsl_bpg_offset calculation

---v4
-add display version check before writing in new pps register

---v5
-add helper to check if sink supports given format with DSC
-add debugfs entry to enforce DSC with YCbCr420 format only

--v6
-add patch to check dsc slice design requirement [Vandita]

--v7
-fix function name to intel_slice_dimensions_valid [Jani]
-remove full bspec link just add the ref number [Jani]
-remove patches for debug fs will float them as a seprate series
-Add more description for YUV420 Enablement [Vandita]

Ankit Nautiyal (2):
  drm/dp_helper: Add helper to check if the sink supports given format
    with DSC
  drm/i915/dp: Check if DSC supports the given output_format

Suraj Kandpal (4):
  drm/i915: Adding the new registers for DSC
  drm/i915: Enable YCbCr420 for VDSC
  drm/i915: Fill in native_420 field
  drm/i915/vdsc: Check slice design requirement

 drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
 drivers/gpu/drm/i915/display/intel_dp.c       |  33 +++-
 .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
 .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 106 +++++++++-
 drivers/gpu/drm/i915/i915_reg.h               |  28 +++
 include/drm/display/drm_dp_helper.h           |   7 +
 7 files changed, 345 insertions(+), 22 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH v8 0/6] Enable YCbCr420 for VDSC
@ 2023-01-18  5:59 Suraj Kandpal
  2023-01-18  6:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
  0 siblings, 1 reply; 18+ messages in thread
From: Suraj Kandpal @ 2023-01-18  5:59 UTC (permalink / raw)
  To: intel-gfx

This patch series aims to enable the YCbCr420 format
for DSC. Changes are mostly compute params related for
hdmi,dp and dsi along with the addition of new rc_tables
for native_420 and corresponding changes to macros used to
fetch them.

---v2
-add fields missed for vdsc_cfg [Vandita]
-add corresponding registers and writing to the [Vandita]

---v3
-add 11 bit left shift missed in nsl_bpg_offset calculation

---v4
-add display version check before writing in new pps register

---v5
-add helper to check if sink supports given format with DSC
-add debugfs entry to enforce DSC with YCbCr420 format only

--v6
-add patch to check dsc slice design requirement [Vandita]

--v7
-fix function name to intel_slice_dimensions_valid [Jani]
-remove full bspec link just add the ref number [Jani]
-remove patches for debug fs will float them as a seprate series
-Add more description for YUV420 Enablement [Vandita]

--v8
-fix slice width and height 2's multiple check
-fix minimum pixel requirement in slice check

Ankit Nautiyal (2):
  drm/dp_helper: Add helper to check if the sink supports given format
    with DSC
  drm/i915/dp: Check if DSC supports the given output_format

Suraj Kandpal (4):
  drm/i915: Adding the new registers for DSC
  drm/i915: Enable YCbCr420 for VDSC
  drm/i915: Fill in native_420 field
  drm/i915/vdsc: Check slice design requirement

 drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
 drivers/gpu/drm/i915/display/intel_dp.c       |  33 +++-
 .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
 .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 106 +++++++++-
 drivers/gpu/drm/i915/i915_reg.h               |  28 +++
 include/drm/display/drm_dp_helper.h           |   7 +
 7 files changed, 345 insertions(+), 22 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH v9 0/7] Enable YCbCr420 for VDSC
@ 2023-02-07  7:44 Suraj Kandpal
  2023-02-07  8:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
  0 siblings, 1 reply; 18+ messages in thread
From: Suraj Kandpal @ 2023-02-07  7:44 UTC (permalink / raw)
  To: intel-gfx

This patch series aims to enable the YCbCr420 format
for DSC. Changes are mostly compute params related for
hdmi,dp and dsi along with the addition of new rc_tables
for native_420 and corresponding changes to macros used to
fetch them.

---v2
-add fields missed for vdsc_cfg [Vandita]
-add corresponding registers and writing to the [Vandita]

---v3
-add 11 bit left shift missed in nsl_bpg_offset calculation

---v4
-add display version check before writing in new pps register

---v5
-add helper to check if sink supports given format with DSC
-add debugfs entry to enforce DSC with YCbCr420 format only

--v6
-add patch to check dsc slice design requirement [Vandita]

--v7
-fix function name to intel_slice_dimensions_valid [Jani]
-remove full bspec link just add the ref number [Jani]
-remove patches for debug fs will float them as a seprate series
-Add more description for YUV420 Enablement [Vandita]

--v8
-fix slice width and height 2's multiple check
-fix minimum pixel requirement in slice check

--v9 
-Add debugfs entry to validate output format

Ankit Nautiyal (2):
  drm/dp_helper: Add helper to check if the sink supports given format
    with DSC
  drm/i915/dp: Check if DSC supports the given output_format

Suraj Kandpal (4):
  drm/i915: Adding the new registers for DSC
  drm/i915: Enable YCbCr420 for VDSC
  drm/i915: Fill in native_420 field
  drm/i915/vdsc: Check slice design requirement

Swati Sharma (1):
  drm/i915/dsc: Add debugfs entry to validate DSC output formats

 drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
 .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
 .../drm/i915/display/intel_crtc_state_dump.h  |   2 +
 .../drm/i915/display/intel_display_debugfs.c  |  77 ++++++++
 .../drm/i915/display/intel_display_types.h    |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  44 ++++-
 .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
 .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 106 +++++++++-
 drivers/gpu/drm/i915/i915_reg.h               |  28 +++
 include/drm/display/drm_dp_helper.h           |   7 +
 11 files changed, 438 insertions(+), 24 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 18+ messages in thread

end of thread, other threads:[~2023-02-07  8:27 UTC | newest]

Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-21 10:55 [Intel-gfx] [PATCH 0/3] Enable YCbCr420 for VDSC Kandpal, Suraj
2022-09-21 10:55 ` [Intel-gfx] [PATCH 1/3] drm/i915/dp: Check if DSC supports the given output_format Kandpal, Suraj
2022-09-21 10:55 ` [Intel-gfx] [PATCH 2/3] drm/i915/vdsc: Enable YCbCr420 for VDSC Kandpal, Suraj
2022-09-21 10:55 ` [Intel-gfx] [PATCH 3/3] drm/i915/display: Fill in native_420 field Kandpal, Suraj
2022-10-10  6:21   ` Kulkarni, Vandita
2022-09-21 11:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable YCbCr420 for VDSC Patchwork
2022-09-21 11:56 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-09-21 12:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-21 13:22 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-09-26  8:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable YCbCr420 for VDSC (rev2) Patchwork
2022-09-26  9:05 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-26 11:06 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-10-14 15:26 [Intel-gfx] [PATCH v4 0/4] Enable YCbCr420 for VDSC Suraj Kandpal
2022-10-14 16:39 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2022-10-28 11:19 [Intel-gfx] [PATCH v5 0/8] " Swati Sharma
2022-10-28 14:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2022-11-07  7:39 [Intel-gfx] [PATCH v5 0/8] " Suraj Kandpal
2022-11-07  9:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2023-01-13  5:52 [Intel-gfx] [PATCH v7 0/6] " Suraj Kandpal
2023-01-13  6:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2023-01-18  5:59 [Intel-gfx] [PATCH v8 0/6] " Suraj Kandpal
2023-01-18  6:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2023-02-07  7:44 [Intel-gfx] [PATCH v9 0/7] " Suraj Kandpal
2023-02-07  8:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.