* [Intel-gfx] [PATCH 0/3] Add _PICK_EVEN_RANGES
@ 2022-10-12 4:51 ` Lucas De Marchi
0 siblings, 0 replies; 20+ messages in thread
From: Lucas De Marchi @ 2022-10-12 4:51 UTC (permalink / raw)
To: intel-gfx, dri-devel, Lucas De Marchi
Add a new macro, _PICK_EVEN_RANGES, that supports using 2 address
ranges. This should cover most of our needs for _MMIO_PLL3 and such.
To show what is achieved with the new macro, convert some PLL-related
macros to use it instead of _MMIO_PLL3.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
Lucas De Marchi (3):
drm/i915: Add _PICK_EVEN_RANGES()
drm/i915: Fix coding style on DPLL*_ENABLE defines
drm/i915: Convert pll macros to _PICK_EVEN_RANGES
drivers/gpu/drm/i915/i915_reg.h | 91 +++++++++++++++++++++++------------------
1 file changed, 52 insertions(+), 39 deletions(-)
---
base-commit: caaf8c4c270b6b9ce1b8610b4eea888190fc087f
change-id: 20221011-pick-even-ranges-76ad8a5007e9
Best regards,
--
Lucas De Marchi <lucas.demarchi@intel.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 0/3] Add _PICK_EVEN_RANGES
@ 2022-10-12 4:51 ` Lucas De Marchi
0 siblings, 0 replies; 20+ messages in thread
From: Lucas De Marchi @ 2022-10-12 4:51 UTC (permalink / raw)
To: intel-gfx, dri-devel, Lucas De Marchi; +Cc: Anusha Srivatsa
Add a new macro, _PICK_EVEN_RANGES, that supports using 2 address
ranges. This should cover most of our needs for _MMIO_PLL3 and such.
To show what is achieved with the new macro, convert some PLL-related
macros to use it instead of _MMIO_PLL3.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
Lucas De Marchi (3):
drm/i915: Add _PICK_EVEN_RANGES()
drm/i915: Fix coding style on DPLL*_ENABLE defines
drm/i915: Convert pll macros to _PICK_EVEN_RANGES
drivers/gpu/drm/i915/i915_reg.h | 91 +++++++++++++++++++++++------------------
1 file changed, 52 insertions(+), 39 deletions(-)
---
base-commit: caaf8c4c270b6b9ce1b8610b4eea888190fc087f
change-id: 20221011-pick-even-ranges-76ad8a5007e9
Best regards,
--
Lucas De Marchi <lucas.demarchi@intel.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 1/3] drm/i915: Add _PICK_EVEN_RANGES()
2022-10-12 4:51 ` Lucas De Marchi
@ 2022-10-12 4:51 ` Lucas De Marchi
-1 siblings, 0 replies; 20+ messages in thread
From: Lucas De Marchi @ 2022-10-12 4:51 UTC (permalink / raw)
To: intel-gfx, dri-devel, Lucas De Marchi
It's a constant pattern in the driver to need to use 2 ranges of MMIOs
based on port, phy, pll, etc. When that happens, instead of using
_PICK_EVEN(), _PICK() needs to be used. Using _PICK() is discouraged
due to some reasons like:
1) It increases the code size since the array is declared in each
call site
2) Developers need to be careful not to incur an out-of-bounds array
access
3) Developers need to be careful that the indexes match the
table. For that it may be that the table needs to contain
holes, making (1) even worse.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
(cherry picked from commit 55a65ca6e5d8f7f46fe4cf29c76a9f1b4ddef5ce)
---
drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3edfbe92c6dd..d157dd693e41 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -126,10 +126,24 @@
#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
/*
- * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
+ * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced addres offsets. The
+ * @__use_first_range argument selects if the first or second range should be
+ * used. It's usually in the form like ``(pll) < n``, in which ``n`` is the
+ * number of registers in the first range. Example::
*
- * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
+ * #define _FOO_A 0xf000
+ * #define _FOO_B 0xf004
+ * #define _FOO_C 0xf008
+ * #define _SUPER_FOO_A 0xa000
+ * #define _SUPER_FOO_B 0xaf00
+ * #define FOO(x) _MMIO(_PICK_EVEN_RANGES(x, (x) < 3, \
+ * _FOO_A, _FOO_B, \
+ * _SUPER_FOO_A, _SUPER_FOO_B))
*/
+#define _PICK_EVEN_RANGES(__index, __use_first_range, __a, __b, __c, __d) \
+ ((__use_first_range) ? _PICK_EVEN(__index, __a, __b) : \
+ _PICK_EVEN(__index, __c, __d))
+
#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
/*
--
b4 0.10.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 1/3] drm/i915: Add _PICK_EVEN_RANGES()
@ 2022-10-12 4:51 ` Lucas De Marchi
0 siblings, 0 replies; 20+ messages in thread
From: Lucas De Marchi @ 2022-10-12 4:51 UTC (permalink / raw)
To: intel-gfx, dri-devel, Lucas De Marchi; +Cc: Anusha Srivatsa
It's a constant pattern in the driver to need to use 2 ranges of MMIOs
based on port, phy, pll, etc. When that happens, instead of using
_PICK_EVEN(), _PICK() needs to be used. Using _PICK() is discouraged
due to some reasons like:
1) It increases the code size since the array is declared in each
call site
2) Developers need to be careful not to incur an out-of-bounds array
access
3) Developers need to be careful that the indexes match the
table. For that it may be that the table needs to contain
holes, making (1) even worse.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
(cherry picked from commit 55a65ca6e5d8f7f46fe4cf29c76a9f1b4ddef5ce)
---
drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3edfbe92c6dd..d157dd693e41 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -126,10 +126,24 @@
#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
/*
- * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
+ * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced addres offsets. The
+ * @__use_first_range argument selects if the first or second range should be
+ * used. It's usually in the form like ``(pll) < n``, in which ``n`` is the
+ * number of registers in the first range. Example::
*
- * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
+ * #define _FOO_A 0xf000
+ * #define _FOO_B 0xf004
+ * #define _FOO_C 0xf008
+ * #define _SUPER_FOO_A 0xa000
+ * #define _SUPER_FOO_B 0xaf00
+ * #define FOO(x) _MMIO(_PICK_EVEN_RANGES(x, (x) < 3, \
+ * _FOO_A, _FOO_B, \
+ * _SUPER_FOO_A, _SUPER_FOO_B))
*/
+#define _PICK_EVEN_RANGES(__index, __use_first_range, __a, __b, __c, __d) \
+ ((__use_first_range) ? _PICK_EVEN(__index, __a, __b) : \
+ _PICK_EVEN(__index, __c, __d))
+
#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
/*
--
b4 0.10.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 2/3] drm/i915: Fix coding style on DPLL*_ENABLE defines
2022-10-12 4:51 ` Lucas De Marchi
@ 2022-10-12 4:51 ` Lucas De Marchi
-1 siblings, 0 replies; 20+ messages in thread
From: Lucas De Marchi @ 2022-10-12 4:51 UTC (permalink / raw)
To: intel-gfx, dri-devel, Lucas De Marchi; +Cc: Anusha Srivatsa
Abide by the rules in the top of the header: 2 spaces for bitfield,
prefix offsets with underscore and prefer the use of REG_BIT().
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
(cherry picked from commit c5545ec37a7f5b928f3f6e3993f1f24b9e70ba32)
---
drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d157dd693e41..ad8f839046f5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7305,20 +7305,20 @@ enum skl_power_gate {
ADLS_DPCLKA_DDIK_SEL_MASK)
/* ICL PLL */
-#define DPLL0_ENABLE 0x46010
-#define DPLL1_ENABLE 0x46014
+#define _DPLL0_ENABLE 0x46010
+#define _DPLL1_ENABLE 0x46014
#define _ADLS_DPLL2_ENABLE 0x46018
#define _ADLS_DPLL3_ENABLE 0x46030
-#define PLL_ENABLE (1 << 31)
-#define PLL_LOCK (1 << 30)
-#define PLL_POWER_ENABLE (1 << 27)
-#define PLL_POWER_STATE (1 << 26)
-#define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+#define PLL_ENABLE REG_BIT(31)
+#define PLL_LOCK REG_BIT(30)
+#define PLL_POWER_ENABLE REG_BIT(27)
+#define PLL_POWER_STATE REG_BIT(26)
+#define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
_ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
#define _DG2_PLL3_ENABLE 0x4601C
-#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
_ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE)
#define TBT_PLL_ENABLE _MMIO(0x46020)
@@ -7327,12 +7327,12 @@ enum skl_power_gate {
#define _MG_PLL2_ENABLE 0x46034
#define _MG_PLL3_ENABLE 0x46038
#define _MG_PLL4_ENABLE 0x4603C
-/* Bits are the same as DPLL0_ENABLE */
+/* Bits are the same as _DPLL0_ENABLE */
#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
_MG_PLL2_ENABLE)
/* DG1 PLL */
-#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
_MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
/* ADL-P Type C PLL */
--
b4 0.10.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915: Fix coding style on DPLL*_ENABLE defines
@ 2022-10-12 4:51 ` Lucas De Marchi
0 siblings, 0 replies; 20+ messages in thread
From: Lucas De Marchi @ 2022-10-12 4:51 UTC (permalink / raw)
To: intel-gfx, dri-devel, Lucas De Marchi
Abide by the rules in the top of the header: 2 spaces for bitfield,
prefix offsets with underscore and prefer the use of REG_BIT().
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
(cherry picked from commit c5545ec37a7f5b928f3f6e3993f1f24b9e70ba32)
---
drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d157dd693e41..ad8f839046f5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7305,20 +7305,20 @@ enum skl_power_gate {
ADLS_DPCLKA_DDIK_SEL_MASK)
/* ICL PLL */
-#define DPLL0_ENABLE 0x46010
-#define DPLL1_ENABLE 0x46014
+#define _DPLL0_ENABLE 0x46010
+#define _DPLL1_ENABLE 0x46014
#define _ADLS_DPLL2_ENABLE 0x46018
#define _ADLS_DPLL3_ENABLE 0x46030
-#define PLL_ENABLE (1 << 31)
-#define PLL_LOCK (1 << 30)
-#define PLL_POWER_ENABLE (1 << 27)
-#define PLL_POWER_STATE (1 << 26)
-#define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+#define PLL_ENABLE REG_BIT(31)
+#define PLL_LOCK REG_BIT(30)
+#define PLL_POWER_ENABLE REG_BIT(27)
+#define PLL_POWER_STATE REG_BIT(26)
+#define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
_ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
#define _DG2_PLL3_ENABLE 0x4601C
-#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
_ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE)
#define TBT_PLL_ENABLE _MMIO(0x46020)
@@ -7327,12 +7327,12 @@ enum skl_power_gate {
#define _MG_PLL2_ENABLE 0x46034
#define _MG_PLL3_ENABLE 0x46038
#define _MG_PLL4_ENABLE 0x4603C
-/* Bits are the same as DPLL0_ENABLE */
+/* Bits are the same as _DPLL0_ENABLE */
#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
_MG_PLL2_ENABLE)
/* DG1 PLL */
-#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
_MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
/* ADL-P Type C PLL */
--
b4 0.10.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915: Convert pll macros to _PICK_EVEN_RANGES
2022-10-12 4:51 ` Lucas De Marchi
@ 2022-10-12 4:51 ` Lucas De Marchi
-1 siblings, 0 replies; 20+ messages in thread
From: Lucas De Marchi @ 2022-10-12 4:51 UTC (permalink / raw)
To: intel-gfx, dri-devel, Lucas De Marchi
Avoid the array lookup, converting the PLL macros after ICL to
_PICK_EVEN_RANGES. This provides the following reduction in code size:
$ size build64/drivers/gpu/drm/i915/i915.o{.old,.new}
text data bss dec hex filename
3570297 131232 6824 3708353 3895c1 build64/drivers/gpu/drm/i915/i915.o.old
3569686 131232 6824 3707742 38935e build64/drivers/gpu/drm/i915/i915.o.new
At the same time it's safer, avoiding out-of-bounds array access.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
(cherry picked from commit 592d15e3d72009bfb9f7a933c292510f8564a4cf)
---
drivers/gpu/drm/i915/i915_reg.h | 59 ++++++++++++++++++++---------------------
1 file changed, 29 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ad8f839046f5..df30bcc53489 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7313,13 +7313,15 @@ enum skl_power_gate {
#define PLL_LOCK REG_BIT(30)
#define PLL_POWER_ENABLE REG_BIT(27)
#define PLL_POWER_STATE REG_BIT(26)
-#define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
- _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
+#define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 3, \
+ _DPLL0_ENABLE, _DPLL1_ENABLE, \
+ _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE))
#define _DG2_PLL3_ENABLE 0x4601C
-#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
- _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE)
+#define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 3, \
+ _DPLL0_ENABLE, _DPLL1_ENABLE, \
+ _DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE))
#define TBT_PLL_ENABLE _MMIO(0x46020)
@@ -7332,8 +7334,9 @@ enum skl_power_gate {
_MG_PLL2_ENABLE)
/* DG1 PLL */
-#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
- _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
+#define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \
+ _DPLL0_ENABLE, _DPLL1_ENABLE, \
+ _MG_PLL1_ENABLE, _MG_PLL2_ENABLE))
/* ADL-P Type C PLL */
#define PORTTC1_PLL_ENABLE 0x46038
@@ -7393,9 +7396,9 @@ enum skl_power_gate {
#define _TGL_DPLL0_CFGCR0 0x164284
#define _TGL_DPLL1_CFGCR0 0x16428C
#define _TGL_TBTPLL_CFGCR0 0x16429C
-#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
- _TGL_DPLL1_CFGCR0, \
- _TGL_TBTPLL_CFGCR0)
+#define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \
+ _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
+ _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0))
#define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
_TGL_DPLL1_CFGCR0)
@@ -7408,40 +7411,36 @@ enum skl_power_gate {
#define _TGL_DPLL0_CFGCR1 0x164288
#define _TGL_DPLL1_CFGCR1 0x164290
#define _TGL_TBTPLL_CFGCR1 0x1642A0
-#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
- _TGL_DPLL1_CFGCR1, \
- _TGL_TBTPLL_CFGCR1)
+#define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \
+ _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
+ _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1))
#define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
_TGL_DPLL1_CFGCR1)
#define _DG1_DPLL2_CFGCR0 0x16C284
#define _DG1_DPLL3_CFGCR0 0x16C28C
-#define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
- _TGL_DPLL1_CFGCR0, \
- _DG1_DPLL2_CFGCR0, \
- _DG1_DPLL3_CFGCR0)
+#define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \
+ _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
+ _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0))
#define _DG1_DPLL2_CFGCR1 0x16C288
#define _DG1_DPLL3_CFGCR1 0x16C290
-#define DG1_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
- _TGL_DPLL1_CFGCR1, \
- _DG1_DPLL2_CFGCR1, \
- _DG1_DPLL3_CFGCR1)
+#define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \
+ _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
+ _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1))
/* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
-#define _ADLS_DPLL3_CFGCR0 0x1642C0
#define _ADLS_DPLL4_CFGCR0 0x164294
-#define ADLS_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
- _TGL_DPLL1_CFGCR0, \
- _ADLS_DPLL4_CFGCR0, \
- _ADLS_DPLL3_CFGCR0)
+#define _ADLS_DPLL3_CFGCR0 0x1642C0
+#define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \
+ _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
+ _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0))
-#define _ADLS_DPLL3_CFGCR1 0x1642C4
#define _ADLS_DPLL4_CFGCR1 0x164298
-#define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
- _TGL_DPLL1_CFGCR1, \
- _ADLS_DPLL4_CFGCR1, \
- _ADLS_DPLL3_CFGCR1)
+#define _ADLS_DPLL3_CFGCR1 0x1642C4
+#define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \
+ _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
+ _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1))
#define _DKL_PHY1_BASE 0x168000
#define _DKL_PHY2_BASE 0x169000
--
b4 0.10.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/3] drm/i915: Convert pll macros to _PICK_EVEN_RANGES
@ 2022-10-12 4:51 ` Lucas De Marchi
0 siblings, 0 replies; 20+ messages in thread
From: Lucas De Marchi @ 2022-10-12 4:51 UTC (permalink / raw)
To: intel-gfx, dri-devel, Lucas De Marchi; +Cc: Anusha Srivatsa
Avoid the array lookup, converting the PLL macros after ICL to
_PICK_EVEN_RANGES. This provides the following reduction in code size:
$ size build64/drivers/gpu/drm/i915/i915.o{.old,.new}
text data bss dec hex filename
3570297 131232 6824 3708353 3895c1 build64/drivers/gpu/drm/i915/i915.o.old
3569686 131232 6824 3707742 38935e build64/drivers/gpu/drm/i915/i915.o.new
At the same time it's safer, avoiding out-of-bounds array access.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
(cherry picked from commit 592d15e3d72009bfb9f7a933c292510f8564a4cf)
---
drivers/gpu/drm/i915/i915_reg.h | 59 ++++++++++++++++++++---------------------
1 file changed, 29 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ad8f839046f5..df30bcc53489 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7313,13 +7313,15 @@ enum skl_power_gate {
#define PLL_LOCK REG_BIT(30)
#define PLL_POWER_ENABLE REG_BIT(27)
#define PLL_POWER_STATE REG_BIT(26)
-#define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
- _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
+#define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 3, \
+ _DPLL0_ENABLE, _DPLL1_ENABLE, \
+ _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE))
#define _DG2_PLL3_ENABLE 0x4601C
-#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
- _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE)
+#define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 3, \
+ _DPLL0_ENABLE, _DPLL1_ENABLE, \
+ _DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE))
#define TBT_PLL_ENABLE _MMIO(0x46020)
@@ -7332,8 +7334,9 @@ enum skl_power_gate {
_MG_PLL2_ENABLE)
/* DG1 PLL */
-#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
- _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
+#define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \
+ _DPLL0_ENABLE, _DPLL1_ENABLE, \
+ _MG_PLL1_ENABLE, _MG_PLL2_ENABLE))
/* ADL-P Type C PLL */
#define PORTTC1_PLL_ENABLE 0x46038
@@ -7393,9 +7396,9 @@ enum skl_power_gate {
#define _TGL_DPLL0_CFGCR0 0x164284
#define _TGL_DPLL1_CFGCR0 0x16428C
#define _TGL_TBTPLL_CFGCR0 0x16429C
-#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
- _TGL_DPLL1_CFGCR0, \
- _TGL_TBTPLL_CFGCR0)
+#define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \
+ _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
+ _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0))
#define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
_TGL_DPLL1_CFGCR0)
@@ -7408,40 +7411,36 @@ enum skl_power_gate {
#define _TGL_DPLL0_CFGCR1 0x164288
#define _TGL_DPLL1_CFGCR1 0x164290
#define _TGL_TBTPLL_CFGCR1 0x1642A0
-#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
- _TGL_DPLL1_CFGCR1, \
- _TGL_TBTPLL_CFGCR1)
+#define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \
+ _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
+ _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1))
#define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
_TGL_DPLL1_CFGCR1)
#define _DG1_DPLL2_CFGCR0 0x16C284
#define _DG1_DPLL3_CFGCR0 0x16C28C
-#define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
- _TGL_DPLL1_CFGCR0, \
- _DG1_DPLL2_CFGCR0, \
- _DG1_DPLL3_CFGCR0)
+#define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \
+ _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
+ _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0))
#define _DG1_DPLL2_CFGCR1 0x16C288
#define _DG1_DPLL3_CFGCR1 0x16C290
-#define DG1_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
- _TGL_DPLL1_CFGCR1, \
- _DG1_DPLL2_CFGCR1, \
- _DG1_DPLL3_CFGCR1)
+#define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \
+ _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
+ _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1))
/* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
-#define _ADLS_DPLL3_CFGCR0 0x1642C0
#define _ADLS_DPLL4_CFGCR0 0x164294
-#define ADLS_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
- _TGL_DPLL1_CFGCR0, \
- _ADLS_DPLL4_CFGCR0, \
- _ADLS_DPLL3_CFGCR0)
+#define _ADLS_DPLL3_CFGCR0 0x1642C0
+#define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \
+ _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
+ _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0))
-#define _ADLS_DPLL3_CFGCR1 0x1642C4
#define _ADLS_DPLL4_CFGCR1 0x164298
-#define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
- _TGL_DPLL1_CFGCR1, \
- _ADLS_DPLL4_CFGCR1, \
- _ADLS_DPLL3_CFGCR1)
+#define _ADLS_DPLL3_CFGCR1 0x1642C4
+#define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \
+ _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
+ _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1))
#define _DKL_PHY1_BASE 0x168000
#define _DKL_PHY2_BASE 0x169000
--
b4 0.10.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 1/3] drm/i915: Add _PICK_EVEN_RANGES()
2022-10-12 4:51 ` Lucas De Marchi
@ 2022-10-12 5:13 ` Lucas De Marchi
-1 siblings, 0 replies; 20+ messages in thread
From: Lucas De Marchi @ 2022-10-12 5:13 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Anusha Srivatsa
On Tue, Oct 11, 2022 at 09:51:08PM -0700, Lucas De Marchi wrote:
>It's a constant pattern in the driver to need to use 2 ranges of MMIOs
>based on port, phy, pll, etc. When that happens, instead of using
>_PICK_EVEN(), _PICK() needs to be used. Using _PICK() is discouraged
>due to some reasons like:
>
> 1) It increases the code size since the array is declared in each
> call site
> 2) Developers need to be careful not to incur an out-of-bounds array
> access
> 3) Developers need to be careful that the indexes match the
> table. For that it may be that the table needs to contain
> holes, making (1) even worse.
>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>(cherry picked from commit 55a65ca6e5d8f7f46fe4cf29c76a9f1b4ddef5ce)
>---
> drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++++++--
> 1 file changed, 16 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 3edfbe92c6dd..d157dd693e41 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -126,10 +126,24 @@
> #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
>
> /*
>- * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
>+ * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced addres offsets. The
>+ * @__use_first_range argument selects if the first or second range should be
>+ * used. It's usually in the form like ``(pll) < n``, in which ``n`` is the
>+ * number of registers in the first range. Example::
> *
>- * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
>+ * #define _FOO_A 0xf000
>+ * #define _FOO_B 0xf004
>+ * #define _FOO_C 0xf008
>+ * #define _SUPER_FOO_A 0xa000
>+ * #define _SUPER_FOO_B 0xaf00
>+ * #define FOO(x) _MMIO(_PICK_EVEN_RANGES(x, (x) < 3, \
>+ * _FOO_A, _FOO_B, \
>+ * _SUPER_FOO_A, _SUPER_FOO_B))
> */
>+#define _PICK_EVEN_RANGES(__index, __use_first_range, __a, __b, __c, __d) \
>+ ((__use_first_range) ? _PICK_EVEN(__index, __a, __b) : \
>+ _PICK_EVEN(__index, __c, __d))
humn.. I tried to simplify this with a "__use_first_range" but now this
is broken as the index doesn't start on zero for the second range. This
should actually be something like:
#define _PICK_EVEN_RANGES(__index, __c_idx, __a, __b, __c, __d) \
((__index < __c_idx) ? _PICK_EVEN(__index, __a, __b) : \
_PICK_EVEN((__index) - __c_idx, __c, __d))
Lucas De Marchi
>+
> #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
>
> /*
>
>--
>b4 0.10.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915: Add _PICK_EVEN_RANGES()
@ 2022-10-12 5:13 ` Lucas De Marchi
0 siblings, 0 replies; 20+ messages in thread
From: Lucas De Marchi @ 2022-10-12 5:13 UTC (permalink / raw)
To: intel-gfx, dri-devel
On Tue, Oct 11, 2022 at 09:51:08PM -0700, Lucas De Marchi wrote:
>It's a constant pattern in the driver to need to use 2 ranges of MMIOs
>based on port, phy, pll, etc. When that happens, instead of using
>_PICK_EVEN(), _PICK() needs to be used. Using _PICK() is discouraged
>due to some reasons like:
>
> 1) It increases the code size since the array is declared in each
> call site
> 2) Developers need to be careful not to incur an out-of-bounds array
> access
> 3) Developers need to be careful that the indexes match the
> table. For that it may be that the table needs to contain
> holes, making (1) even worse.
>
>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>(cherry picked from commit 55a65ca6e5d8f7f46fe4cf29c76a9f1b4ddef5ce)
>---
> drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++++++--
> 1 file changed, 16 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 3edfbe92c6dd..d157dd693e41 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -126,10 +126,24 @@
> #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
>
> /*
>- * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
>+ * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced addres offsets. The
>+ * @__use_first_range argument selects if the first or second range should be
>+ * used. It's usually in the form like ``(pll) < n``, in which ``n`` is the
>+ * number of registers in the first range. Example::
> *
>- * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
>+ * #define _FOO_A 0xf000
>+ * #define _FOO_B 0xf004
>+ * #define _FOO_C 0xf008
>+ * #define _SUPER_FOO_A 0xa000
>+ * #define _SUPER_FOO_B 0xaf00
>+ * #define FOO(x) _MMIO(_PICK_EVEN_RANGES(x, (x) < 3, \
>+ * _FOO_A, _FOO_B, \
>+ * _SUPER_FOO_A, _SUPER_FOO_B))
> */
>+#define _PICK_EVEN_RANGES(__index, __use_first_range, __a, __b, __c, __d) \
>+ ((__use_first_range) ? _PICK_EVEN(__index, __a, __b) : \
>+ _PICK_EVEN(__index, __c, __d))
humn.. I tried to simplify this with a "__use_first_range" but now this
is broken as the index doesn't start on zero for the second range. This
should actually be something like:
#define _PICK_EVEN_RANGES(__index, __c_idx, __a, __b, __c, __d) \
((__index < __c_idx) ? _PICK_EVEN(__index, __a, __b) : \
_PICK_EVEN((__index) - __c_idx, __c, __d))
Lucas De Marchi
>+
> #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
>
> /*
>
>--
>b4 0.10.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add _PICK_EVEN_RANGES
2022-10-12 4:51 ` Lucas De Marchi
` (3 preceding siblings ...)
(?)
@ 2022-10-12 5:30 ` Patchwork
-1 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2022-10-12 5:30 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Add _PICK_EVEN_RANGES
URL : https://patchwork.freedesktop.org/series/109606/
State : warning
== Summary ==
Error: dim checkpatch failed
8dea49b8c4d8 drm/i915: Add _PICK_EVEN_RANGES()
-:31: WARNING:TYPO_SPELLING: 'addres' may be misspelled - perhaps 'address'?
#31: FILE: drivers/gpu/drm/i915/i915_reg.h:129:
+ * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced addres offsets. The
^^^^^^
-:46: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__index' - possible side-effects?
#46: FILE: drivers/gpu/drm/i915/i915_reg.h:143:
+#define _PICK_EVEN_RANGES(__index, __use_first_range, __a, __b, __c, __d) \
+ ((__use_first_range) ? _PICK_EVEN(__index, __a, __b) : \
+ _PICK_EVEN(__index, __c, __d))
total: 0 errors, 1 warnings, 1 checks, 26 lines checked
62193904a042 drm/i915: Fix coding style on DPLL*_ENABLE defines
7c57067c784b drm/i915: Convert pll macros to _PICK_EVEN_RANGES
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#11:
3570297 131232 6824 3708353 3895c1 build64/drivers/gpu/drm/i915/i915.o.old
-:29: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pll' - possible side-effects?
#29: FILE: drivers/gpu/drm/i915/i915_reg.h:7316:
+#define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 3, \
+ _DPLL0_ENABLE, _DPLL1_ENABLE, \
+ _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE))
-:37: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pll' - possible side-effects?
#37: FILE: drivers/gpu/drm/i915/i915_reg.h:7322:
+#define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 3, \
+ _DPLL0_ENABLE, _DPLL1_ENABLE, \
+ _DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE))
-:49: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pll' - possible side-effects?
#49: FILE: drivers/gpu/drm/i915/i915_reg.h:7337:
+#define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \
+ _DPLL0_ENABLE, _DPLL1_ENABLE, \
+ _MG_PLL1_ENABLE, _MG_PLL2_ENABLE))
-:62: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pll' - possible side-effects?
#62: FILE: drivers/gpu/drm/i915/i915_reg.h:7399:
+#define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \
+ _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
+ _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0))
-:75: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pll' - possible side-effects?
#75: FILE: drivers/gpu/drm/i915/i915_reg.h:7414:
+#define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \
+ _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
+ _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1))
-:87: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pll' - possible side-effects?
#87: FILE: drivers/gpu/drm/i915/i915_reg.h:7422:
+#define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \
+ _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
+ _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0))
-:97: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pll' - possible side-effects?
#97: FILE: drivers/gpu/drm/i915/i915_reg.h:7428:
+#define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \
+ _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
+ _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1))
-:109: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pll' - possible side-effects?
#109: FILE: drivers/gpu/drm/i915/i915_reg.h:7435:
+#define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \
+ _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
+ _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0))
-:120: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pll' - possible side-effects?
#120: FILE: drivers/gpu/drm/i915/i915_reg.h:7441:
+#define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2, \
+ _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
+ _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1))
total: 0 errors, 1 warnings, 9 checks, 99 lines checked
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add _PICK_EVEN_RANGES
2022-10-12 4:51 ` Lucas De Marchi
` (4 preceding siblings ...)
(?)
@ 2022-10-12 5:30 ` Patchwork
-1 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2022-10-12 5:30 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Add _PICK_EVEN_RANGES
URL : https://patchwork.freedesktop.org/series/109606/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Add _PICK_EVEN_RANGES
2022-10-12 4:51 ` Lucas De Marchi
` (5 preceding siblings ...)
(?)
@ 2022-10-12 5:52 ` Patchwork
-1 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2022-10-12 5:52 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5842 bytes --]
== Series Details ==
Series: Add _PICK_EVEN_RANGES
URL : https://patchwork.freedesktop.org/series/109606/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12235 -> Patchwork_109606v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/index.html
Participating hosts (46 -> 42)
------------------------------
Missing (4): fi-ctg-p8600 bat-atsm-1 fi-tgl-dsi bat-jsl-3
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_109606v1:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@slpc:
- {bat-adlp-6}: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/bat-adlp-6/igt@i915_selftest@live@slpc.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/bat-adlp-6/igt@i915_selftest@live@slpc.html
Known issues
------------
Here are the changes found in Patchwork_109606v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gt_timelines:
- fi-icl-u2: [PASS][3] -> [INCOMPLETE][4] ([i915#4890] / [i915#7057])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/fi-icl-u2/igt@i915_selftest@live@gt_timelines.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/fi-icl-u2/igt@i915_selftest@live@gt_timelines.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-bdw-5557u: [PASS][5] -> [INCOMPLETE][6] ([i915#146] / [i915#6712])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/fi-bdw-5557u/igt@i915_suspend@basic-s3-without-i915.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/fi-bdw-5557u/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/fi-hsw-4770/igt@kms_chamelium@common-hpd-after-suspend.html
- fi-rkl-11600: NOTRUN -> [SKIP][8] ([fdo#111827])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/fi-rkl-11600/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@runner@aborted:
- fi-icl-u2: NOTRUN -> [FAIL][9] ([i915#4312] / [i915#4991])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/fi-icl-u2/igt@runner@aborted.html
#### Possible fixes ####
* igt@fbdev@read:
- {bat-rpls-2}: [SKIP][10] ([i915#2582]) -> [PASS][11] +4 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/bat-rpls-2/igt@fbdev@read.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/bat-rpls-2/igt@fbdev@read.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [INCOMPLETE][12] ([i915#4785]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [INCOMPLETE][14] ([i915#5982]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4890]: https://gitlab.freedesktop.org/drm/intel/issues/4890
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5278]: https://gitlab.freedesktop.org/drm/intel/issues/5278
[i915#5537]: https://gitlab.freedesktop.org/drm/intel/issues/5537
[i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6471]: https://gitlab.freedesktop.org/drm/intel/issues/6471
[i915#6712]: https://gitlab.freedesktop.org/drm/intel/issues/6712
[i915#6818]: https://gitlab.freedesktop.org/drm/intel/issues/6818
[i915#7029]: https://gitlab.freedesktop.org/drm/intel/issues/7029
[i915#7031]: https://gitlab.freedesktop.org/drm/intel/issues/7031
[i915#7057]: https://gitlab.freedesktop.org/drm/intel/issues/7057
Build changes
-------------
* Linux: CI_DRM_12235 -> Patchwork_109606v1
CI-20190529: 20190529
CI_DRM_12235: caaf8c4c270b6b9ce1b8610b4eea888190fc087f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7009: cf55acdeea3747c668074a8734029364960e5f5e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_109606v1: caaf8c4c270b6b9ce1b8610b4eea888190fc087f @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
182d8a3b487c drm/i915: Convert pll macros to _PICK_EVEN_RANGES
8f451e640415 drm/i915: Fix coding style on DPLL*_ENABLE defines
f3a8b8b1018c drm/i915: Add _PICK_EVEN_RANGES()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/index.html
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Add _PICK_EVEN_RANGES
2022-10-12 4:51 ` Lucas De Marchi
` (6 preceding siblings ...)
(?)
@ 2022-10-12 7:45 ` Patchwork
-1 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2022-10-12 7:45 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 37204 bytes --]
== Series Details ==
Series: Add _PICK_EVEN_RANGES
URL : https://patchwork.freedesktop.org/series/109606/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12235_full -> Patchwork_109606v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_109606v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_109606v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_109606v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@execlists:
- shard-skl: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl1/igt@i915_selftest@live@execlists.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl3/igt@i915_selftest@live@execlists.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-skl: NOTRUN -> [INCOMPLETE][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
Known issues
------------
Here are the changes found in Patchwork_109606v1_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-skl: ([PASS][4], [PASS][5], [PASS][6], [PASS][7], [FAIL][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28]) ([i915#5032]) -> ([PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl7/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl7/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl7/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl7/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl9/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl9/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl9/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl9/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl1/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl1/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl3/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl3/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl3/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl1/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl10/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl3/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl6/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl6/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl1/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl10/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl6/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl10/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl10/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl6/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl7/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl6/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl6/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl6/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl6/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl7/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl7/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl7/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl7/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl9/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl9/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl9/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl9/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl9/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl3/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl1/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl1/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl10/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl10/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl10/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl10/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl3/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl1/boot.html
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@display-2x:
- shard-iclb: NOTRUN -> [SKIP][51] ([i915#1839])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@feature_discovery@display-2x.html
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-skl: NOTRUN -> [SKIP][52] ([fdo#109271]) +72 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl1/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
* igt@gem_ctx_persistence@hang:
- shard-snb: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#1099])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-snb5/igt@gem_ctx_persistence@hang.html
* igt@gem_eio@reset-stress:
- shard-tglb: [PASS][54] -> [FAIL][55] ([i915#5784])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-tglb7/igt@gem_eio@reset-stress.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-tglb5/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [PASS][56] -> [SKIP][57] ([i915#4525])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-iclb1/igt@gem_exec_balancer@parallel-bb-first.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb5/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_fair@basic-none:
- shard-snb: NOTRUN -> [SKIP][58] ([fdo#109271]) +58 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-snb5/igt@gem_exec_fair@basic-none.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: NOTRUN -> [FAIL][59] ([i915#2842])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][60] -> [FAIL][61] ([i915#2842])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-glk1/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][62] -> [SKIP][63] ([i915#2190])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-tglb5/igt@gem_huc_copy@huc-copy.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-tglb7/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@massive-random:
- shard-iclb: NOTRUN -> [SKIP][64] ([i915#4613])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@gem_lmem_swapping@massive-random.html
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-apl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#4613])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-apl2/igt@gem_lmem_swapping@parallel-random-verify.html
* igt@gem_lmem_swapping@verify-random-ccs:
- shard-skl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#4613]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl1/igt@gem_lmem_swapping@verify-random-ccs.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-iclb: NOTRUN -> [SKIP][67] ([i915#4270])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@gem_pxp@regular-baseline-src-copy-readible.html
* igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs:
- shard-iclb: NOTRUN -> [SKIP][68] ([i915#768])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs.html
* igt@gem_userptr_blits@input-checking:
- shard-snb: NOTRUN -> [DMESG-WARN][69] ([i915#4991])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-snb5/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@unsync-unmap-after-close:
- shard-iclb: NOTRUN -> [SKIP][70] ([i915#3297]) +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@gem_userptr_blits@unsync-unmap-after-close.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [PASS][71] -> [DMESG-WARN][72] ([i915#5566] / [i915#716])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-glk3/igt@gen9_exec_parse@allowed-all.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-glk7/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-iclb: NOTRUN -> [SKIP][73] ([i915#2856])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@gen9_exec_parse@bb-start-cmd.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: NOTRUN -> [SKIP][74] ([i915#658])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [PASS][75] -> [SKIP][76] ([i915#4281])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-iclb8/igt@i915_pm_dc@dc9-dpms.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
- shard-apl: NOTRUN -> [FAIL][77] ([i915#4275])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-apl2/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- shard-iclb: NOTRUN -> [SKIP][78] ([fdo#110892])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
* igt@i915_suspend@debugfs-reader:
- shard-apl: [PASS][79] -> [DMESG-WARN][80] ([i915#180]) +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-apl3/igt@i915_suspend@debugfs-reader.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-apl3/igt@i915_suspend@debugfs-reader.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: NOTRUN -> [DMESG-WARN][81] ([i915#180])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-apl1/igt@i915_suspend@sysfs-reader.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1:
- shard-skl: [PASS][82] -> [FAIL][83] ([i915#2521])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl3/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl6/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
* igt@kms_big_fb@4-tiled-addfb:
- shard-iclb: NOTRUN -> [SKIP][84] ([i915#5286])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@kms_big_fb@4-tiled-addfb.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][85] ([fdo#110725] / [fdo#111614]) +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
- shard-iclb: NOTRUN -> [SKIP][86] ([fdo#110723])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#3886]) +3 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl1/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][88] ([fdo#109278] / [i915#3886]) +2 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
- shard-apl: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#3886]) +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-apl1/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_cdclk@plane-scaling:
- shard-iclb: NOTRUN -> [SKIP][90] ([i915#3742])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@kms_cdclk@plane-scaling.html
* igt@kms_chamelium@dp-frame-dump:
- shard-apl: NOTRUN -> [SKIP][91] ([fdo#109271] / [fdo#111827]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-apl2/igt@kms_chamelium@dp-frame-dump.html
* igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
- shard-snb: NOTRUN -> [SKIP][92] ([fdo#109271] / [fdo#111827])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-snb5/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
* igt@kms_chamelium@vga-frame-dump:
- shard-iclb: NOTRUN -> [SKIP][93] ([fdo#109284] / [fdo#111827])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@kms_chamelium@vga-frame-dump.html
* igt@kms_chamelium@vga-hpd-without-ddc:
- shard-skl: NOTRUN -> [SKIP][94] ([fdo#109271] / [fdo#111827]) +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl1/igt@kms_chamelium@vga-hpd-without-ddc.html
* igt@kms_cursor_crc@cursor-offscreen-32x10:
- shard-iclb: NOTRUN -> [SKIP][95] ([i915#3555]) +5 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@kms_cursor_crc@cursor-offscreen-32x10.html
* igt@kms_cursor_edge_walk@right-edge@pipe-a-hdmi-a-1-256x256:
- shard-glk: [PASS][96] -> [DMESG-FAIL][97] ([i915#118])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-glk9/igt@kms_cursor_edge_walk@right-edge@pipe-a-hdmi-a-1-256x256.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-glk8/igt@kms_cursor_edge_walk@right-edge@pipe-a-hdmi-a-1-256x256.html
* igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible:
- shard-iclb: NOTRUN -> [SKIP][98] ([fdo#109274]) +1 similar issue
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-skl: [PASS][99] -> [FAIL][100] ([i915#79])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@d-edp1:
- shard-tglb: [PASS][101] -> [DMESG-WARN][102] ([i915#2411] / [i915#2867])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-tglb5/igt@kms_flip@flip-vs-suspend-interruptible@d-edp1.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-tglb3/igt@kms_flip@flip-vs-suspend-interruptible@d-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][103] ([i915#2587] / [i915#2672]) +1 similar issue
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb8/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][104] ([i915#2672]) +2 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][105] ([i915#2672] / [i915#3555])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-cpu:
- shard-iclb: NOTRUN -> [SKIP][106] ([fdo#109280]) +8 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
- shard-apl: NOTRUN -> [SKIP][107] ([fdo#109271]) +34 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-apl2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-skl: [PASS][108] -> [INCOMPLETE][109] ([i915#1982] / [i915#4939])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl7/igt@kms_frontbuffer_tracking@psr-suspend.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl9/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-dp-1:
- shard-apl: NOTRUN -> [FAIL][110] ([i915#4573]) +2 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-apl2/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-dp-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1:
- shard-iclb: [PASS][111] -> [SKIP][112] ([i915#5235]) +2 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-iclb3/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html
* igt@kms_prime@d3hot:
- shard-iclb: NOTRUN -> [SKIP][113] ([i915#6524])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@kms_prime@d3hot.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-skl: NOTRUN -> [SKIP][114] ([fdo#109271] / [i915#658])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl10/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-apl: NOTRUN -> [SKIP][115] ([fdo#109271] / [i915#658]) +1 similar issue
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-apl2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr@psr2_primary_blt:
- shard-iclb: NOTRUN -> [SKIP][116] ([fdo#109441])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@kms_psr@psr2_primary_blt.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][117] -> [SKIP][118] ([fdo#109441]) +2 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_vblank@pipe-d-wait-forked-busy:
- shard-iclb: NOTRUN -> [SKIP][119] ([fdo#109278]) +5 similar issues
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@kms_vblank@pipe-d-wait-forked-busy.html
* igt@perf@blocking:
- shard-skl: [PASS][120] -> [FAIL][121] ([i915#1542])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl6/igt@perf@blocking.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl9/igt@perf@blocking.html
* igt@perf@short-reads:
- shard-skl: [PASS][122] -> [FAIL][123] ([i915#51])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl1/igt@perf@short-reads.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl3/igt@perf@short-reads.html
* igt@sysfs_clients@fair-7:
- shard-iclb: NOTRUN -> [SKIP][124] ([i915#2994])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@sysfs_clients@fair-7.html
#### Possible fixes ####
* igt@gem_exec_balancer@parallel:
- shard-iclb: [SKIP][125] ([i915#4525]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-iclb3/igt@gem_exec_balancer@parallel.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb2/igt@gem_exec_balancer@parallel.html
* igt@gem_exec_capture@pi@rcs0:
- shard-skl: [INCOMPLETE][127] ([i915#3371]) -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl1/igt@gem_exec_capture@pi@rcs0.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl10/igt@gem_exec_capture@pi@rcs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [DMESG-WARN][129] ([i915#5566] / [i915#716]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-apl7/igt@gen9_exec_parse@allowed-single.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-apl2/igt@gen9_exec_parse@allowed-single.html
- shard-glk: [DMESG-WARN][131] ([i915#5566] / [i915#716]) -> [PASS][132]
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-glk9/igt@gen9_exec_parse@allowed-single.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-glk8/igt@gen9_exec_parse@allowed-single.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-skl: [DMESG-WARN][133] ([i915#1982]) -> [PASS][134]
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl3/igt@i915_module_load@reload-with-fault-injection.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl6/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_addfb_basic@legacy-format:
- shard-iclb: [INCOMPLETE][135] ([i915#7017] / [i915#7057]) -> [PASS][136]
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-iclb2/igt@kms_addfb_basic@legacy-format.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb8/igt@kms_addfb_basic@legacy-format.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1:
- shard-skl: [FAIL][137] ([i915#2521]) -> [PASS][138]
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl3/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl6/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html
* igt@kms_cursor_crc@cursor-random-64x21@pipe-a-edp-1:
- shard-iclb: [DMESG-FAIL][139] -> [PASS][140]
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-iclb7/igt@kms_cursor_crc@cursor-random-64x21@pipe-a-edp-1.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@kms_cursor_crc@cursor-random-64x21@pipe-a-edp-1.html
* igt@kms_cursor_crc@cursor-random-64x21@pipe-b-edp-1:
- shard-iclb: [FAIL][141] ([i915#1888]) -> [PASS][142] +1 similar issue
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-iclb7/igt@kms_cursor_crc@cursor-random-64x21@pipe-b-edp-1.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@kms_cursor_crc@cursor-random-64x21@pipe-b-edp-1.html
* igt@kms_cursor_crc@cursor-random-64x21@pipe-c-edp-1:
- shard-iclb: [FAIL][143] -> [PASS][144]
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-iclb7/igt@kms_cursor_crc@cursor-random-64x21@pipe-c-edp-1.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb1/igt@kms_cursor_crc@cursor-random-64x21@pipe-c-edp-1.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic:
- shard-skl: [FAIL][145] ([i915#2346]) -> [PASS][146]
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor@atomic.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor@atomic.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [FAIL][147] ([i915#79]) -> [PASS][148] +2 similar issues
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode:
- shard-iclb: [SKIP][149] ([i915#3555]) -> [PASS][150]
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-apl: [DMESG-WARN][151] ([i915#180]) -> [PASS][152] +1 similar issue
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1:
- shard-iclb: [SKIP][153] ([i915#5176]) -> [PASS][154] +2 similar issues
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-iclb2/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb8/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][155] ([fdo#109441]) -> [PASS][156] +1 similar issue
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-iclb3/igt@kms_psr@psr2_no_drrs.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@perf@polling-parameterized:
- shard-skl: [FAIL][157] ([i915#5639]) -> [PASS][158]
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl10/igt@perf@polling-parameterized.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl1/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-skl: [INCOMPLETE][159] -> [FAIL][160] ([i915#2346])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-iclb: [SKIP][161] ([i915#658]) -> [SKIP][162] ([i915#2920])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-iclb3/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-iclb: [SKIP][163] ([i915#2920]) -> [SKIP][164] ([i915#658])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb3/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-iclb: [SKIP][165] ([fdo#111068] / [i915#658]) -> [SKIP][166] ([i915#2920])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-iclb7/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@runner@aborted:
- shard-apl: ([FAIL][167], [FAIL][168], [FAIL][169], [FAIL][170], [FAIL][171]) ([fdo#109271] / [i915#3002] / [i915#4312]) -> ([FAIL][172], [FAIL][173], [FAIL][174], [FAIL][175], [FAIL][176]) ([i915#180] / [i915#3002] / [i915#4312])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-apl2/igt@runner@aborted.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-apl2/igt@runner@aborted.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-apl7/igt@runner@aborted.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-apl8/igt@runner@aborted.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12235/shard-apl8/igt@runner@aborted.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-apl8/igt@runner@aborted.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-apl2/igt@runner@aborted.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-apl2/igt@runner@aborted.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-apl1/igt@runner@aborted.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/shard-apl3/igt@runner@aborted.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#110892]: https://bugs.freedesktop.org/show_bug.cgi?id=110892
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3371]: https://gitlab.freedesktop.org/drm/intel/issues/3371
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4275]: https://gitlab.freedesktop.org/drm/intel/issues/4275
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5032]: https://gitlab.freedesktop.org/drm/intel/issues/5032
[i915#51]: https://gitlab.freedesktop.org/drm/intel/issues/51
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#7017]: https://gitlab.freedesktop.org/drm/intel/issues/7017
[i915#7057]: https://gitlab.freedesktop.org/drm/intel/issues/7057
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12235 -> Patchwork_109606v1
CI-20190529: 20190529
CI_DRM_12235: caaf8c4c270b6b9ce1b8610b4eea888190fc087f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7009: cf55acdeea3747c668074a8734029364960e5f5e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_109606v1: caaf8c4c270b6b9ce1b8610b4eea888190fc087f @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109606v1/index.html
[-- Attachment #2: Type: text/html, Size: 43486 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 0/3] Add _PICK_EVEN_RANGES
2022-10-12 4:51 ` Lucas De Marchi
@ 2022-10-12 8:51 ` Jani Nikula
-1 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2022-10-12 8:51 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx, dri-devel, Lucas De Marchi; +Cc: Anusha Srivatsa
On Tue, 11 Oct 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> Add a new macro, _PICK_EVEN_RANGES, that supports using 2 address
> ranges. This should cover most of our needs for _MMIO_PLL3 and such.
> To show what is achieved with the new macro, convert some PLL-related
> macros to use it instead of _MMIO_PLL3.
While there's nothing particularly wrong about the solution when looked
at in isolation, I do have pretty strong reservations on the whole.
We have:
1) _PICK_EVEN() used in _PIPE() and friends
2) _PICK() used in _MMIO_PIPE3() and friends
3) ->pipe_offsets[] etc. adjustment used in _MMIO_PIPE2() and friends
4) ->ddi_index[] mapping proposed in [1]
5) _PICK_EVEN_RANGES() proposed here
Originally we only had the first one, when the hardware was
simpler. Every single addition since then made sense at the time, but if
we add 4 & 5 to the mix, I think it's just too many options.
I think it's time to take a step back and figure out if there's a more
generic approach that could be used.
BR,
Jani.
[1] https://patchwork.freedesktop.org/series/108833/
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 0/3] Add _PICK_EVEN_RANGES
@ 2022-10-12 8:51 ` Jani Nikula
0 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2022-10-12 8:51 UTC (permalink / raw)
To: Lucas De Marchi, intel-gfx, dri-devel, Lucas De Marchi
On Tue, 11 Oct 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> Add a new macro, _PICK_EVEN_RANGES, that supports using 2 address
> ranges. This should cover most of our needs for _MMIO_PLL3 and such.
> To show what is achieved with the new macro, convert some PLL-related
> macros to use it instead of _MMIO_PLL3.
While there's nothing particularly wrong about the solution when looked
at in isolation, I do have pretty strong reservations on the whole.
We have:
1) _PICK_EVEN() used in _PIPE() and friends
2) _PICK() used in _MMIO_PIPE3() and friends
3) ->pipe_offsets[] etc. adjustment used in _MMIO_PIPE2() and friends
4) ->ddi_index[] mapping proposed in [1]
5) _PICK_EVEN_RANGES() proposed here
Originally we only had the first one, when the hardware was
simpler. Every single addition since then made sense at the time, but if
we add 4 & 5 to the mix, I think it's just too many options.
I think it's time to take a step back and figure out if there's a more
generic approach that could be used.
BR,
Jani.
[1] https://patchwork.freedesktop.org/series/108833/
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 0/3] Add _PICK_EVEN_RANGES
2022-10-12 8:51 ` [Intel-gfx] " Jani Nikula
@ 2022-10-12 19:05 ` Lucas De Marchi
-1 siblings, 0 replies; 20+ messages in thread
From: Lucas De Marchi @ 2022-10-12 19:05 UTC (permalink / raw)
To: Jani Nikula
Cc: intel-gfx, Anusha Srivatsa, dri-devel, balasubramani.vivekanandan
On Wed, Oct 12, 2022 at 11:51:48AM +0300, Jani Nikula wrote:
>On Tue, 11 Oct 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> Add a new macro, _PICK_EVEN_RANGES, that supports using 2 address
>> ranges. This should cover most of our needs for _MMIO_PLL3 and such.
>> To show what is achieved with the new macro, convert some PLL-related
>> macros to use it instead of _MMIO_PLL3.
>
>While there's nothing particularly wrong about the solution when looked
>at in isolation, I do have pretty strong reservations on the whole.
>
>We have:
>
>1) _PICK_EVEN() used in _PIPE() and friends
>
>2) _PICK() used in _MMIO_PIPE3() and friends
>
>3) ->pipe_offsets[] etc. adjustment used in _MMIO_PIPE2() and friends
>
>4) ->ddi_index[] mapping proposed in [1]
>
>5) _PICK_EVEN_RANGES() proposed here
>
>Originally we only had the first one, when the hardware was
>simpler. Every single addition since then made sense at the time, but if
>we add 4 & 5 to the mix, I think it's just too many options.
>
>I think it's time to take a step back and figure out if there's a more
>generic approach that could be used.
true... I actually see this as replacing most of the uses of _PICK()
and giving and extra benefit of removing the worry we are doing
out-of-bounds array access. It also allows to more easily move ranges
for new platforms, which is my intention here.
So I think that we could have something like this if changing it to
something else means a bigger refactor. Talking about a big refactor, I
still think my series from a few years back would make sense:
drm/i915/display: start description-based ddi initialization
(https://lore.kernel.org/all/20191223195850.25997-1-lucas.demarchi@intel.com/)
I think that got stalled due to initialization in the intel_ddi.c trying
too much to group together the if/else ladder. But the overall intention
of the patch series I believe is still valid today:
(...) create a table-based initialization approach in
which I keep the useful indexes for each platform: these indexes work
similarly to what we have on the pll part. "enum port" is mostly a
"driver thing" and when all the conversions take place, it would allow
us to stop using the port as indexes to register or register bits. "enum
tc_port", "enum phy", etc are not meaningful numbers from the spec POV
and change with every other platform.
+Bala who apparently is going to a similar approach in the ddi_index
approach.
Other possible approaches hat come to mind (just dumping some thoughts,
with no actual code/poc):
1) Inside display strut we have:
struct {
u8 version;
union {
struct {
i915_reg_t foo;
i915_reg_t bar;
i915_reg_t bla;
} v1;
struct {
i915_reg_t xyz;
i915_reg_t ijk;
} v2;
}
} regs;
instead of vesion it could be the "first platform to use it" like we
currently have. Those registers would then be initialized during module
bind and then we stop doing these conversions to map a platform to a
register offset. It still needs some per-platform change for the
bitfields though.
idea would be then to enforce using the right struct inside the union by
splitting the code in differen compilation units. One platform can
evolve from the other with the same compilation unit as long as it is
backward-compatible, i.e. we can add more registers, change offsets,
etc. But if the HW interface completely changes, it would need to use a
different version.
2) Looking around what other teams do. In mesa the registers are actually
maintained in a xml. Example: gen12.xml
<register name="HIZ_CHICKEN" length="1" num="0x7018">
<field name="HZ Depth Test LE/GE Optimization Disable" start="13" end="13" type="bool"/>
<field name="HZ Depth Test LE/GE Optimization Disable Mask" start="29" end="29" type="bool"/>
</register>
In code it's used like this:
reg.HZDepthTestLEGEOptimizationDisable = true;
3) Kind of going in the same direction, but more in the kernel side. Maybe
switching to regmap?
I think one of the things that block this kind of refactors is having to
bring them back to all the previous platforms. Maybe going back only
until HAS_DDI() would be a good approach. Or maybe even spliting it on
DISPLAY_VER == 12? That might help more radical changes.
Lucas De Marchi
>
>
>BR,
>Jani.
>
>
>[1] https://patchwork.freedesktop.org/series/108833/
>
>--
>Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 0/3] Add _PICK_EVEN_RANGES
@ 2022-10-12 19:05 ` Lucas De Marchi
0 siblings, 0 replies; 20+ messages in thread
From: Lucas De Marchi @ 2022-10-12 19:05 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, dri-devel
On Wed, Oct 12, 2022 at 11:51:48AM +0300, Jani Nikula wrote:
>On Tue, 11 Oct 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> Add a new macro, _PICK_EVEN_RANGES, that supports using 2 address
>> ranges. This should cover most of our needs for _MMIO_PLL3 and such.
>> To show what is achieved with the new macro, convert some PLL-related
>> macros to use it instead of _MMIO_PLL3.
>
>While there's nothing particularly wrong about the solution when looked
>at in isolation, I do have pretty strong reservations on the whole.
>
>We have:
>
>1) _PICK_EVEN() used in _PIPE() and friends
>
>2) _PICK() used in _MMIO_PIPE3() and friends
>
>3) ->pipe_offsets[] etc. adjustment used in _MMIO_PIPE2() and friends
>
>4) ->ddi_index[] mapping proposed in [1]
>
>5) _PICK_EVEN_RANGES() proposed here
>
>Originally we only had the first one, when the hardware was
>simpler. Every single addition since then made sense at the time, but if
>we add 4 & 5 to the mix, I think it's just too many options.
>
>I think it's time to take a step back and figure out if there's a more
>generic approach that could be used.
true... I actually see this as replacing most of the uses of _PICK()
and giving and extra benefit of removing the worry we are doing
out-of-bounds array access. It also allows to more easily move ranges
for new platforms, which is my intention here.
So I think that we could have something like this if changing it to
something else means a bigger refactor. Talking about a big refactor, I
still think my series from a few years back would make sense:
drm/i915/display: start description-based ddi initialization
(https://lore.kernel.org/all/20191223195850.25997-1-lucas.demarchi@intel.com/)
I think that got stalled due to initialization in the intel_ddi.c trying
too much to group together the if/else ladder. But the overall intention
of the patch series I believe is still valid today:
(...) create a table-based initialization approach in
which I keep the useful indexes for each platform: these indexes work
similarly to what we have on the pll part. "enum port" is mostly a
"driver thing" and when all the conversions take place, it would allow
us to stop using the port as indexes to register or register bits. "enum
tc_port", "enum phy", etc are not meaningful numbers from the spec POV
and change with every other platform.
+Bala who apparently is going to a similar approach in the ddi_index
approach.
Other possible approaches hat come to mind (just dumping some thoughts,
with no actual code/poc):
1) Inside display strut we have:
struct {
u8 version;
union {
struct {
i915_reg_t foo;
i915_reg_t bar;
i915_reg_t bla;
} v1;
struct {
i915_reg_t xyz;
i915_reg_t ijk;
} v2;
}
} regs;
instead of vesion it could be the "first platform to use it" like we
currently have. Those registers would then be initialized during module
bind and then we stop doing these conversions to map a platform to a
register offset. It still needs some per-platform change for the
bitfields though.
idea would be then to enforce using the right struct inside the union by
splitting the code in differen compilation units. One platform can
evolve from the other with the same compilation unit as long as it is
backward-compatible, i.e. we can add more registers, change offsets,
etc. But if the HW interface completely changes, it would need to use a
different version.
2) Looking around what other teams do. In mesa the registers are actually
maintained in a xml. Example: gen12.xml
<register name="HIZ_CHICKEN" length="1" num="0x7018">
<field name="HZ Depth Test LE/GE Optimization Disable" start="13" end="13" type="bool"/>
<field name="HZ Depth Test LE/GE Optimization Disable Mask" start="29" end="29" type="bool"/>
</register>
In code it's used like this:
reg.HZDepthTestLEGEOptimizationDisable = true;
3) Kind of going in the same direction, but more in the kernel side. Maybe
switching to regmap?
I think one of the things that block this kind of refactors is having to
bring them back to all the previous platforms. Maybe going back only
until HAS_DDI() would be a good approach. Or maybe even spliting it on
DISPLAY_VER == 12? That might help more radical changes.
Lucas De Marchi
>
>
>BR,
>Jani.
>
>
>[1] https://patchwork.freedesktop.org/series/108833/
>
>--
>Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 0/3] Add _PICK_EVEN_RANGES
2022-10-12 19:05 ` [Intel-gfx] " Lucas De Marchi
(?)
@ 2022-10-22 6:45 ` Lucas De Marchi
2022-11-11 15:22 ` Jani Nikula
-1 siblings, 1 reply; 20+ messages in thread
From: Lucas De Marchi @ 2022-10-22 6:45 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, dri-devel
On Wed, Oct 12, 2022 at 12:05:31PM -0700, Lucas De Marchi wrote:
>On Wed, Oct 12, 2022 at 11:51:48AM +0300, Jani Nikula wrote:
>>On Tue, 11 Oct 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>>>Add a new macro, _PICK_EVEN_RANGES, that supports using 2 address
>>>ranges. This should cover most of our needs for _MMIO_PLL3 and such.
>>>To show what is achieved with the new macro, convert some PLL-related
>>>macros to use it instead of _MMIO_PLL3.
>>
>>While there's nothing particularly wrong about the solution when looked
>>at in isolation, I do have pretty strong reservations on the whole.
>>
>>We have:
>>
>>1) _PICK_EVEN() used in _PIPE() and friends
>>
>>2) _PICK() used in _MMIO_PIPE3() and friends
>>
>>3) ->pipe_offsets[] etc. adjustment used in _MMIO_PIPE2() and friends
>>
>>4) ->ddi_index[] mapping proposed in [1]
>>
>>5) _PICK_EVEN_RANGES() proposed here
>>
>>Originally we only had the first one, when the hardware was
>>simpler. Every single addition since then made sense at the time, but if
>>we add 4 & 5 to the mix, I think it's just too many options.
>>
>>I think it's time to take a step back and figure out if there's a more
>>generic approach that could be used.
>
>true... I actually see this as replacing most of the uses of _PICK()
>and giving and extra benefit of removing the worry we are doing
>out-of-bounds array access. It also allows to more easily move ranges
>for new platforms, which is my intention here.
Jani, any feedback here or in the possible things to do below? I'd like
to get a sketch of whatever solution we think could be the right
direction during next week.
thanks
Lucas De Marchi
>
>So I think that we could have something like this if changing it to
>something else means a bigger refactor. Talking about a big refactor, I
>still think my series from a few years back would make sense:
>
>drm/i915/display: start description-based ddi initialization
>(https://lore.kernel.org/all/20191223195850.25997-1-lucas.demarchi@intel.com/)
>
>I think that got stalled due to initialization in the intel_ddi.c trying
>too much to group together the if/else ladder. But the overall intention
>of the patch series I believe is still valid today:
>
> (...) create a table-based initialization approach in
> which I keep the useful indexes for each platform: these indexes work
> similarly to what we have on the pll part. "enum port" is mostly a
> "driver thing" and when all the conversions take place, it would allow
> us to stop using the port as indexes to register or register bits. "enum
> tc_port", "enum phy", etc are not meaningful numbers from the spec POV
> and change with every other platform.
>
>+Bala who apparently is going to a similar approach in the ddi_index
>approach.
>
>Other possible approaches hat come to mind (just dumping some thoughts,
>with no actual code/poc):
>
>1) Inside display strut we have:
>
> struct {
> u8 version;
> union {
> struct {
> i915_reg_t foo;
> i915_reg_t bar;
> i915_reg_t bla;
> } v1;
> struct {
> i915_reg_t xyz;
> i915_reg_t ijk;
> } v2;
> }
> } regs;
>
>instead of vesion it could be the "first platform to use it" like we
>currently have. Those registers would then be initialized during module
>bind and then we stop doing these conversions to map a platform to a
>register offset. It still needs some per-platform change for the
>bitfields though.
>
>idea would be then to enforce using the right struct inside the union by
>splitting the code in differen compilation units. One platform can
>evolve from the other with the same compilation unit as long as it is
>backward-compatible, i.e. we can add more registers, change offsets,
>etc. But if the HW interface completely changes, it would need to use a
>different version.
>
>2) Looking around what other teams do. In mesa the registers are actually
>maintained in a xml. Example: gen12.xml
>
><register name="HIZ_CHICKEN" length="1" num="0x7018">
> <field name="HZ Depth Test LE/GE Optimization Disable" start="13" end="13" type="bool"/>
> <field name="HZ Depth Test LE/GE Optimization Disable Mask" start="29" end="29" type="bool"/>
></register>
>
>In code it's used like this:
>
>reg.HZDepthTestLEGEOptimizationDisable = true;
>
>3) Kind of going in the same direction, but more in the kernel side. Maybe
>switching to regmap?
>
>
>I think one of the things that block this kind of refactors is having to
>bring them back to all the previous platforms. Maybe going back only
>until HAS_DDI() would be a good approach. Or maybe even spliting it on
>DISPLAY_VER == 12? That might help more radical changes.
>
>
>Lucas De Marchi
>
>>
>>
>>BR,
>>Jani.
>>
>>
>>[1] https://patchwork.freedesktop.org/series/108833/
>>
>>--
>>Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 0/3] Add _PICK_EVEN_RANGES
2022-10-22 6:45 ` Lucas De Marchi
@ 2022-11-11 15:22 ` Jani Nikula
0 siblings, 0 replies; 20+ messages in thread
From: Jani Nikula @ 2022-11-11 15:22 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, dri-devel
On Fri, 21 Oct 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Wed, Oct 12, 2022 at 12:05:31PM -0700, Lucas De Marchi wrote:
>>On Wed, Oct 12, 2022 at 11:51:48AM +0300, Jani Nikula wrote:
>>>On Tue, 11 Oct 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>>>>Add a new macro, _PICK_EVEN_RANGES, that supports using 2 address
>>>>ranges. This should cover most of our needs for _MMIO_PLL3 and such.
>>>>To show what is achieved with the new macro, convert some PLL-related
>>>>macros to use it instead of _MMIO_PLL3.
>>>
>>>While there's nothing particularly wrong about the solution when looked
>>>at in isolation, I do have pretty strong reservations on the whole.
>>>
>>>We have:
>>>
>>>1) _PICK_EVEN() used in _PIPE() and friends
>>>
>>>2) _PICK() used in _MMIO_PIPE3() and friends
>>>
>>>3) ->pipe_offsets[] etc. adjustment used in _MMIO_PIPE2() and friends
>>>
>>>4) ->ddi_index[] mapping proposed in [1]
>>>
>>>5) _PICK_EVEN_RANGES() proposed here
>>>
>>>Originally we only had the first one, when the hardware was
>>>simpler. Every single addition since then made sense at the time, but if
>>>we add 4 & 5 to the mix, I think it's just too many options.
>>>
>>>I think it's time to take a step back and figure out if there's a more
>>>generic approach that could be used.
>>
>>true... I actually see this as replacing most of the uses of _PICK()
>>and giving and extra benefit of removing the worry we are doing
>>out-of-bounds array access. It also allows to more easily move ranges
>>for new platforms, which is my intention here.
>
> Jani, any feedback here or in the possible things to do below? I'd like
> to get a sketch of whatever solution we think could be the right
> direction during next week.
Considering that I basically stalled this but couldn't provide a
decision on a concrete better path forward either,
Acked-by: Jani Nikula <jani.nikula@intel.com>
on the original approach here. Needs a rebase, but it doesn't block us
from the other ideas later either.
Thanks, and sorry,
Jani.
>
> thanks
> Lucas De Marchi
>
>>
>>So I think that we could have something like this if changing it to
>>something else means a bigger refactor. Talking about a big refactor, I
>>still think my series from a few years back would make sense:
>>
>>drm/i915/display: start description-based ddi initialization
>>(https://lore.kernel.org/all/20191223195850.25997-1-lucas.demarchi@intel.com/)
>>
>>I think that got stalled due to initialization in the intel_ddi.c trying
>>too much to group together the if/else ladder. But the overall intention
>>of the patch series I believe is still valid today:
>>
>> (...) create a table-based initialization approach in
>> which I keep the useful indexes for each platform: these indexes work
>> similarly to what we have on the pll part. "enum port" is mostly a
>> "driver thing" and when all the conversions take place, it would allow
>> us to stop using the port as indexes to register or register bits. "enum
>> tc_port", "enum phy", etc are not meaningful numbers from the spec POV
>> and change with every other platform.
>>
>>+Bala who apparently is going to a similar approach in the ddi_index
>>approach.
>>
>>Other possible approaches hat come to mind (just dumping some thoughts,
>>with no actual code/poc):
>>
>>1) Inside display strut we have:
>>
>> struct {
>> u8 version;
>> union {
>> struct {
>> i915_reg_t foo;
>> i915_reg_t bar;
>> i915_reg_t bla;
>> } v1;
>> struct {
>> i915_reg_t xyz;
>> i915_reg_t ijk;
>> } v2;
>> }
>> } regs;
>>
>>instead of vesion it could be the "first platform to use it" like we
>>currently have. Those registers would then be initialized during module
>>bind and then we stop doing these conversions to map a platform to a
>>register offset. It still needs some per-platform change for the
>>bitfields though.
>>
>>idea would be then to enforce using the right struct inside the union by
>>splitting the code in differen compilation units. One platform can
>>evolve from the other with the same compilation unit as long as it is
>>backward-compatible, i.e. we can add more registers, change offsets,
>>etc. But if the HW interface completely changes, it would need to use a
>>different version.
>>
>>2) Looking around what other teams do. In mesa the registers are actually
>>maintained in a xml. Example: gen12.xml
>>
>><register name="HIZ_CHICKEN" length="1" num="0x7018">
>> <field name="HZ Depth Test LE/GE Optimization Disable" start="13" end="13" type="bool"/>
>> <field name="HZ Depth Test LE/GE Optimization Disable Mask" start="29" end="29" type="bool"/>
>></register>
>>
>>In code it's used like this:
>>
>>reg.HZDepthTestLEGEOptimizationDisable = true;
>>
>>3) Kind of going in the same direction, but more in the kernel side. Maybe
>>switching to regmap?
>>
>>
>>I think one of the things that block this kind of refactors is having to
>>bring them back to all the previous platforms. Maybe going back only
>>until HAS_DDI() would be a good approach. Or maybe even spliting it on
>>DISPLAY_VER == 12? That might help more radical changes.
>>
>>
>>Lucas De Marchi
>>
>>>
>>>
>>>BR,
>>>Jani.
>>>
>>>
>>>[1] https://patchwork.freedesktop.org/series/108833/
>>>
>>>--
>>>Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2022-11-11 15:22 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-12 4:51 [Intel-gfx] [PATCH 0/3] Add _PICK_EVEN_RANGES Lucas De Marchi
2022-10-12 4:51 ` Lucas De Marchi
2022-10-12 4:51 ` [Intel-gfx] [PATCH 1/3] drm/i915: Add _PICK_EVEN_RANGES() Lucas De Marchi
2022-10-12 4:51 ` Lucas De Marchi
2022-10-12 5:13 ` Lucas De Marchi
2022-10-12 5:13 ` [Intel-gfx] " Lucas De Marchi
2022-10-12 4:51 ` [PATCH 2/3] drm/i915: Fix coding style on DPLL*_ENABLE defines Lucas De Marchi
2022-10-12 4:51 ` [Intel-gfx] " Lucas De Marchi
2022-10-12 4:51 ` [Intel-gfx] [PATCH 3/3] drm/i915: Convert pll macros to _PICK_EVEN_RANGES Lucas De Marchi
2022-10-12 4:51 ` Lucas De Marchi
2022-10-12 5:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add _PICK_EVEN_RANGES Patchwork
2022-10-12 5:30 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-10-12 5:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-12 7:45 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-10-12 8:51 ` [PATCH 0/3] " Jani Nikula
2022-10-12 8:51 ` [Intel-gfx] " Jani Nikula
2022-10-12 19:05 ` Lucas De Marchi
2022-10-12 19:05 ` [Intel-gfx] " Lucas De Marchi
2022-10-22 6:45 ` Lucas De Marchi
2022-11-11 15:22 ` Jani Nikula
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