* [PATCH] drm/i915/slpc: Use platform limits for min/max frequency
@ 2022-10-12 18:26 ` Vinay Belgaumkar
0 siblings, 0 replies; 10+ messages in thread
From: Vinay Belgaumkar @ 2022-10-12 18:26 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Vinay Belgaumkar
GuC will set the min/max frequencies to theoretical max on
ATS-M. This will break kernel ABI, so limit min/max frequency
to RP0(platform max) instead.
Also modify the SLPC selftest to update the min frequency
when we have a server part so that we can iterate between
platform min and max.
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
---
drivers/gpu/drm/i915/gt/selftest_slpc.c | 40 +++++++++++++------
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 29 ++++++++++++++
.../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 3 ++
3 files changed, 60 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c b/drivers/gpu/drm/i915/gt/selftest_slpc.c
index 4c6e9257e593..1f84362af737 100644
--- a/drivers/gpu/drm/i915/gt/selftest_slpc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_slpc.c
@@ -234,6 +234,7 @@ static int run_test(struct intel_gt *gt, int test_type)
enum intel_engine_id id;
struct igt_spinner spin;
u32 slpc_min_freq, slpc_max_freq;
+ u32 saved_min_freq;
int err = 0;
if (!intel_uc_uses_guc_slpc(>->uc))
@@ -252,20 +253,35 @@ static int run_test(struct intel_gt *gt, int test_type)
return -EIO;
}
- /*
- * FIXME: With efficient frequency enabled, GuC can request
- * frequencies higher than the SLPC max. While this is fixed
- * in GuC, we level set these tests with RPn as min.
- */
- err = slpc_set_min_freq(slpc, slpc->min_freq);
- if (err)
- return err;
-
if (slpc->min_freq == slpc->rp0_freq) {
- pr_err("Min/Max are fused to the same value\n");
- return -EINVAL;
+ /* Servers will have min/max clamped to RP0 */
+ if (slpc->min_is_rpmax) {
+ err = slpc_set_min_freq(slpc, slpc->min_freq);
+ if (err) {
+ pr_err("Unable to update min freq on server part");
+ return err;
+ }
+
+ } else {
+ pr_err("Min/Max are fused to the same value\n");
+ return -EINVAL;
+ }
+ } else {
+ /*
+ * FIXME: With efficient frequency enabled, GuC can request
+ * frequencies higher than the SLPC max. While this is fixed
+ * in GuC, we level set these tests with RPn as min.
+ */
+ err = slpc_set_min_freq(slpc, slpc->min_freq);
+ if (err)
+ return err;
}
+ saved_min_freq = slpc_min_freq;
+
+ /* New temp min freq = RPn */
+ slpc_min_freq = slpc->min_freq;
+
intel_gt_pm_wait_for_idle(gt);
intel_gt_pm_get(gt);
for_each_engine(engine, gt, id) {
@@ -347,7 +363,7 @@ static int run_test(struct intel_gt *gt, int test_type)
/* Restore min/max frequencies */
slpc_set_max_freq(slpc, slpc_max_freq);
- slpc_set_min_freq(slpc, slpc_min_freq);
+ slpc_set_min_freq(slpc, saved_min_freq);
if (igt_flush_test(gt->i915))
err = -EIO;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index fdd895f73f9f..11613d373a49 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -263,6 +263,7 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
slpc->max_freq_softlimit = 0;
slpc->min_freq_softlimit = 0;
+ slpc->min_is_rpmax = false;
slpc->boost_freq = 0;
atomic_set(&slpc->num_waiters, 0);
@@ -588,6 +589,31 @@ static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
return 0;
}
+static bool is_slpc_min_freq_rpmax(struct intel_guc_slpc *slpc)
+{
+ int slpc_min_freq;
+
+ if (intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq))
+ return false;
+
+ if (slpc_min_freq > slpc->rp0_freq)
+ return true;
+ else
+ return false;
+}
+
+static void update_server_min_softlimit(struct intel_guc_slpc *slpc)
+{
+ /* For server parts, SLPC min will be at RPMax.
+ * Use min softlimit to clamp it to RP0 instead.
+ */
+ if (is_slpc_min_freq_rpmax(slpc) &&
+ !slpc->min_freq_softlimit) {
+ slpc->min_is_rpmax = true;
+ slpc->min_freq_softlimit = slpc->rp0_freq;
+ }
+}
+
static int slpc_use_fused_rp0(struct intel_guc_slpc *slpc)
{
/* Force SLPC to used platform rp0 */
@@ -647,6 +673,9 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
slpc_get_rp_values(slpc);
+ /* Handle the case where min=max=RPmax */
+ update_server_min_softlimit(slpc);
+
/* Set SLPC max limit to RP0 */
ret = slpc_use_fused_rp0(slpc);
if (unlikely(ret)) {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
index 73d208123528..a6ef53b04e04 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
@@ -19,6 +19,9 @@ struct intel_guc_slpc {
bool supported;
bool selected;
+ /* Indicates this is a server part */
+ bool min_is_rpmax;
+
/* platform frequency limits */
u32 min_freq;
u32 rp0_freq;
--
2.35.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/slpc: Use platform limits for min/max frequency
@ 2022-10-12 18:26 ` Vinay Belgaumkar
0 siblings, 0 replies; 10+ messages in thread
From: Vinay Belgaumkar @ 2022-10-12 18:26 UTC (permalink / raw)
To: intel-gfx, dri-devel
GuC will set the min/max frequencies to theoretical max on
ATS-M. This will break kernel ABI, so limit min/max frequency
to RP0(platform max) instead.
Also modify the SLPC selftest to update the min frequency
when we have a server part so that we can iterate between
platform min and max.
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
---
drivers/gpu/drm/i915/gt/selftest_slpc.c | 40 +++++++++++++------
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 29 ++++++++++++++
.../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 3 ++
3 files changed, 60 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c b/drivers/gpu/drm/i915/gt/selftest_slpc.c
index 4c6e9257e593..1f84362af737 100644
--- a/drivers/gpu/drm/i915/gt/selftest_slpc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_slpc.c
@@ -234,6 +234,7 @@ static int run_test(struct intel_gt *gt, int test_type)
enum intel_engine_id id;
struct igt_spinner spin;
u32 slpc_min_freq, slpc_max_freq;
+ u32 saved_min_freq;
int err = 0;
if (!intel_uc_uses_guc_slpc(>->uc))
@@ -252,20 +253,35 @@ static int run_test(struct intel_gt *gt, int test_type)
return -EIO;
}
- /*
- * FIXME: With efficient frequency enabled, GuC can request
- * frequencies higher than the SLPC max. While this is fixed
- * in GuC, we level set these tests with RPn as min.
- */
- err = slpc_set_min_freq(slpc, slpc->min_freq);
- if (err)
- return err;
-
if (slpc->min_freq == slpc->rp0_freq) {
- pr_err("Min/Max are fused to the same value\n");
- return -EINVAL;
+ /* Servers will have min/max clamped to RP0 */
+ if (slpc->min_is_rpmax) {
+ err = slpc_set_min_freq(slpc, slpc->min_freq);
+ if (err) {
+ pr_err("Unable to update min freq on server part");
+ return err;
+ }
+
+ } else {
+ pr_err("Min/Max are fused to the same value\n");
+ return -EINVAL;
+ }
+ } else {
+ /*
+ * FIXME: With efficient frequency enabled, GuC can request
+ * frequencies higher than the SLPC max. While this is fixed
+ * in GuC, we level set these tests with RPn as min.
+ */
+ err = slpc_set_min_freq(slpc, slpc->min_freq);
+ if (err)
+ return err;
}
+ saved_min_freq = slpc_min_freq;
+
+ /* New temp min freq = RPn */
+ slpc_min_freq = slpc->min_freq;
+
intel_gt_pm_wait_for_idle(gt);
intel_gt_pm_get(gt);
for_each_engine(engine, gt, id) {
@@ -347,7 +363,7 @@ static int run_test(struct intel_gt *gt, int test_type)
/* Restore min/max frequencies */
slpc_set_max_freq(slpc, slpc_max_freq);
- slpc_set_min_freq(slpc, slpc_min_freq);
+ slpc_set_min_freq(slpc, saved_min_freq);
if (igt_flush_test(gt->i915))
err = -EIO;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index fdd895f73f9f..11613d373a49 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -263,6 +263,7 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
slpc->max_freq_softlimit = 0;
slpc->min_freq_softlimit = 0;
+ slpc->min_is_rpmax = false;
slpc->boost_freq = 0;
atomic_set(&slpc->num_waiters, 0);
@@ -588,6 +589,31 @@ static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
return 0;
}
+static bool is_slpc_min_freq_rpmax(struct intel_guc_slpc *slpc)
+{
+ int slpc_min_freq;
+
+ if (intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq))
+ return false;
+
+ if (slpc_min_freq > slpc->rp0_freq)
+ return true;
+ else
+ return false;
+}
+
+static void update_server_min_softlimit(struct intel_guc_slpc *slpc)
+{
+ /* For server parts, SLPC min will be at RPMax.
+ * Use min softlimit to clamp it to RP0 instead.
+ */
+ if (is_slpc_min_freq_rpmax(slpc) &&
+ !slpc->min_freq_softlimit) {
+ slpc->min_is_rpmax = true;
+ slpc->min_freq_softlimit = slpc->rp0_freq;
+ }
+}
+
static int slpc_use_fused_rp0(struct intel_guc_slpc *slpc)
{
/* Force SLPC to used platform rp0 */
@@ -647,6 +673,9 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
slpc_get_rp_values(slpc);
+ /* Handle the case where min=max=RPmax */
+ update_server_min_softlimit(slpc);
+
/* Set SLPC max limit to RP0 */
ret = slpc_use_fused_rp0(slpc);
if (unlikely(ret)) {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
index 73d208123528..a6ef53b04e04 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
@@ -19,6 +19,9 @@ struct intel_guc_slpc {
bool supported;
bool selected;
+ /* Indicates this is a server part */
+ bool min_is_rpmax;
+
/* platform frequency limits */
u32 min_freq;
u32 rp0_freq;
--
2.35.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/slpc: Use platform limits for min/max frequency
2022-10-12 18:26 ` [Intel-gfx] " Vinay Belgaumkar
(?)
@ 2022-10-12 19:04 ` Patchwork
-1 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2022-10-12 19:04 UTC (permalink / raw)
To: Vinay Belgaumkar; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4673 bytes --]
== Series Details ==
Series: drm/i915/slpc: Use platform limits for min/max frequency
URL : https://patchwork.freedesktop.org/series/109632/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12238 -> Patchwork_109632v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/index.html
Participating hosts (45 -> 42)
------------------------------
Missing (3): fi-ctg-p8600 fi-hsw-4770 bat-atsm-1
Known issues
------------
Here are the changes found in Patchwork_109632v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [PASS][1] -> [INCOMPLETE][2] ([i915#5982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rpls-2}: [DMESG-WARN][3] ([i915#6434]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/bat-rpls-2/igt@gem_exec_suspend@basic-s0@smem.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/bat-rpls-2/igt@gem_exec_suspend@basic-s0@smem.html
- {bat-adlm-1}: [DMESG-WARN][5] ([i915#2867]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_exec_suspend@basic-s3@lmem0:
- {bat-dg2-11}: [DMESG-WARN][7] ([i915#6816]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/bat-dg2-11/igt@gem_exec_suspend@basic-s3@lmem0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/bat-dg2-11/igt@gem_exec_suspend@basic-s3@lmem0.html
* igt@i915_module_load@reload:
- {bat-rpls-2}: [DMESG-WARN][9] ([i915#5537]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/bat-rpls-2/igt@i915_module_load@reload.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/bat-rpls-2/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@basic-rte:
- {bat-rplp-1}: [DMESG-WARN][11] ([i915#7077]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/bat-rplp-1/igt@i915_pm_rpm@basic-rte.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/bat-rplp-1/igt@i915_pm_rpm@basic-rte.html
* igt@i915_suspend@basic-s2idle-without-i915:
- {bat-rpls-2}: [FAIL][13] ([i915#6559]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/bat-rpls-2/igt@i915_suspend@basic-s2idle-without-i915.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/bat-rpls-2/igt@i915_suspend@basic-s2idle-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5537]: https://gitlab.freedesktop.org/drm/intel/issues/5537
[i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982
[i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
[i915#6559]: https://gitlab.freedesktop.org/drm/intel/issues/6559
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6816]: https://gitlab.freedesktop.org/drm/intel/issues/6816
[i915#7077]: https://gitlab.freedesktop.org/drm/intel/issues/7077
Build changes
-------------
* Linux: CI_DRM_12238 -> Patchwork_109632v1
CI-20190529: 20190529
CI_DRM_12238: 87844a66c86d81ccc88314bd68b9f7292d6b32a5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7012: ca6f5bdd537d26692c4b1ca011b8c4f227d95703 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_109632v1: 87844a66c86d81ccc88314bd68b9f7292d6b32a5 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
028dc35da1a2 drm/i915/slpc: Use platform limits for min/max frequency
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/index.html
[-- Attachment #2: Type: text/html, Size: 5102 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/slpc: Use platform limits for min/max frequency
2022-10-12 18:26 ` [Intel-gfx] " Vinay Belgaumkar
(?)
(?)
@ 2022-10-13 2:30 ` Patchwork
-1 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2022-10-13 2:30 UTC (permalink / raw)
To: Vinay Belgaumkar; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 24849 bytes --]
== Series Details ==
Series: drm/i915/slpc: Use platform limits for min/max frequency
URL : https://patchwork.freedesktop.org/series/109632/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12238_full -> Patchwork_109632v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_109632v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_109632v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_109632v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_legacy@flip-vs-cursor@varying-size:
- shard-skl: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor@varying-size.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor@varying-size.html
Known issues
------------
Here are the changes found in Patchwork_109632v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@dmabuf@all@dma_fence_chain:
- shard-skl: NOTRUN -> [INCOMPLETE][3] ([i915#6949])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-skl1/igt@dmabuf@all@dma_fence_chain.html
* igt@gem_eio@reset-stress:
- shard-tglb: [PASS][4] -> [FAIL][5] ([i915#5784])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-tglb3/igt@gem_eio@reset-stress.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-tglb2/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [PASS][6] -> [SKIP][7] ([i915#4525])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-iclb2/igt@gem_exec_balancer@parallel-keep-in-fence.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-iclb3/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][8] ([i915#2842]) +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-iclb1/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: NOTRUN -> [FAIL][9] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-glk1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_lmem_swapping@massive-random:
- shard-glk: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-glk3/igt@gem_lmem_swapping@massive-random.html
* igt@gem_userptr_blits@input-checking:
- shard-skl: NOTRUN -> [DMESG-WARN][11] ([i915#4991])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-skl1/igt@gem_userptr_blits@input-checking.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][12] -> [DMESG-WARN][13] ([i915#180]) +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-apl6/igt@gem_workarounds@suspend-resume-context.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][14] -> [DMESG-WARN][15] ([i915#5566] / [i915#716])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-apl6/igt@gen9_exec_parse@allowed-single.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-apl7/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- shard-glk: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#1937])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-glk1/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rps@engine-order:
- shard-glk: [PASS][17] -> [FAIL][18] ([i915#6537])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-glk8/igt@i915_pm_rps@engine-order.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-glk6/igt@i915_pm_rps@engine-order.html
* igt@i915_pm_sseu@full-enable:
- shard-skl: [PASS][19] -> [FAIL][20] ([i915#3524])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-skl6/igt@i915_pm_sseu@full-enable.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-skl3/igt@i915_pm_sseu@full-enable.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1:
- shard-skl: [PASS][21] -> [FAIL][22] ([i915#2521]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-skl6/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-skl10/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#3886]) +7 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-glk3/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_color_chamelium@ctm-0-50:
- shard-skl: NOTRUN -> [SKIP][24] ([fdo#109271] / [fdo#111827])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-skl1/igt@kms_color_chamelium@ctm-0-50.html
* igt@kms_color_chamelium@ctm-limited-range:
- shard-glk: NOTRUN -> [SKIP][25] ([fdo#109271] / [fdo#111827]) +8 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-glk1/igt@kms_color_chamelium@ctm-limited-range.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-glk: [PASS][26] -> [FAIL][27] ([i915#2346])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor@legacy:
- shard-skl: [PASS][28] -> [FAIL][29] ([i915#2346]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor@legacy.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor@legacy.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][30] -> [FAIL][31] ([i915#79])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
* igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][32] ([i915#3555])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][33] ([i915#2672] / [i915#3555])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][34] ([i915#2672]) +2 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-valid-mode:
- shard-glk: [PASS][35] -> [FAIL][36] ([i915#1888])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-glk2/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-valid-mode.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-glk2/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][37] ([i915#2587] / [i915#2672]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-iclb6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-skl: [PASS][38] -> [DMESG-WARN][39] ([i915#1982])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-pgflip-blt:
- shard-skl: NOTRUN -> [SKIP][40] ([fdo#109271]) +8 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-skl1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-pgflip-blt.html
* igt@kms_plane_alpha_blend@alpha-basic@pipe-c-hdmi-a-1:
- shard-glk: NOTRUN -> [FAIL][41] ([i915#4573]) +2 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-glk1/igt@kms_plane_alpha_blend@alpha-basic@pipe-c-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1:
- shard-iclb: [PASS][42] -> [SKIP][43] ([i915#5235]) +2 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-iclb8/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-skl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#658])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-skl1/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-glk: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#658]) +3 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-glk3/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-p010@pipe-b-edp-1:
- shard-iclb: NOTRUN -> [FAIL][46] ([i915#5939]) +2 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-iclb2/igt@kms_psr2_su@page_flip-p010@pipe-b-edp-1.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][47] -> [SKIP][48] ([fdo#109441]) +2 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-iclb3/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
- shard-glk: NOTRUN -> [SKIP][49] ([fdo#109271]) +108 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-glk5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-skl: [PASS][50] -> [INCOMPLETE][51] ([i915#4939])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-skl7/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-skl10/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
* igt@perf@blocking:
- shard-skl: [PASS][52] -> [FAIL][53] ([i915#1542])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-skl3/igt@perf@blocking.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-skl1/igt@perf@blocking.html
* igt@perf@polling-parameterized:
- shard-skl: [PASS][54] -> [FAIL][55] ([i915#5639])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-skl6/igt@perf@polling-parameterized.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-skl10/igt@perf@polling-parameterized.html
* igt@sysfs_clients@recycle:
- shard-glk: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#2994]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-glk5/igt@sysfs_clients@recycle.html
#### Possible fixes ####
* igt@gem_exec_balancer@parallel-contexts:
- shard-iclb: [SKIP][57] ([i915#4525]) -> [PASS][58] +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-iclb8/igt@gem_exec_balancer@parallel-contexts.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-iclb2/igt@gem_exec_balancer@parallel-contexts.html
* igt@gen9_exec_parse@bb-large:
- shard-apl: [TIMEOUT][59] ([i915#4639]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-apl1/igt@gen9_exec_parse@bb-large.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-apl6/igt@gen9_exec_parse@bb-large.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-skl: [DMESG-FAIL][61] ([i915#5334]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-skl10/igt@i915_selftest@live@gt_heartbeat.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-skl9/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- shard-tglb: [DMESG-WARN][63] ([i915#5591]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-tglb5/igt@i915_selftest@live@hangcheck.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-tglb2/igt@i915_selftest@live@hangcheck.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1:
- shard-skl: [FAIL][65] ([i915#2521]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-skl6/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-skl10/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-glk: [FAIL][67] ([i915#2346]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][69] ([i915#2122]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-glk5/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-glk7/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@dpms-vs-vblank-race-interruptible@b-edp1:
- shard-skl: [FAIL][71] ([i915#407]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-skl9/igt@kms_flip@dpms-vs-vblank-race-interruptible@b-edp1.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-skl3/igt@kms_flip@dpms-vs-vblank-race-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-skl: [FAIL][73] ([i915#79]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [FAIL][75] ([i915#2122]) -> [PASS][76] +2 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode:
- shard-iclb: [SKIP][77] ([i915#3555]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1:
- shard-iclb: [SKIP][79] ([i915#5235]) -> [PASS][80] +2 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-iclb6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
* igt@kms_psr@psr2_primary_blt:
- shard-iclb: [SKIP][81] ([fdo#109441]) -> [PASS][82] +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-iclb8/igt@kms_psr@psr2_primary_blt.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-iclb2/igt@kms_psr@psr2_primary_blt.html
* igt@kms_rmfb@close-fd@pipe-a-edp-1:
- shard-skl: [DMESG-WARN][83] ([i915#1982]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-skl6/igt@kms_rmfb@close-fd@pipe-a-edp-1.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-skl10/igt@kms_rmfb@close-fd@pipe-a-edp-1.html
* igt@perf@polling-parameterized:
- shard-iclb: [FAIL][85] ([i915#5639]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-iclb1/igt@perf@polling-parameterized.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-iclb8/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-iclb: [SKIP][87] ([i915#658]) -> [SKIP][88] ([i915#2920]) +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-iclb8/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf:
- shard-iclb: [SKIP][89] ([i915#2920]) -> [SKIP][90] ([i915#658])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-iclb3/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
* igt@runner@aborted:
- shard-apl: ([FAIL][91], [FAIL][92], [FAIL][93]) ([i915#180] / [i915#3002] / [i915#4312]) -> ([FAIL][94], [FAIL][95], [FAIL][96], [FAIL][97], [FAIL][98], [FAIL][99]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-apl8/igt@runner@aborted.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-apl7/igt@runner@aborted.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12238/shard-apl3/igt@runner@aborted.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-apl7/igt@runner@aborted.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-apl1/igt@runner@aborted.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-apl7/igt@runner@aborted.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-apl8/igt@runner@aborted.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-apl8/igt@runner@aborted.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/shard-apl6/igt@runner@aborted.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3524]: https://gitlab.freedesktop.org/drm/intel/issues/3524
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#407]: https://gitlab.freedesktop.org/drm/intel/issues/407
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4639]: https://gitlab.freedesktop.org/drm/intel/issues/4639
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
[i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
[i915#6537]: https://gitlab.freedesktop.org/drm/intel/issues/6537
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6949]: https://gitlab.freedesktop.org/drm/intel/issues/6949
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12238 -> Patchwork_109632v1
CI-20190529: 20190529
CI_DRM_12238: 87844a66c86d81ccc88314bd68b9f7292d6b32a5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7012: ca6f5bdd537d26692c4b1ca011b8c4f227d95703 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_109632v1: 87844a66c86d81ccc88314bd68b9f7292d6b32a5 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109632v1/index.html
[-- Attachment #2: Type: text/html, Size: 29505 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/slpc: Use platform limits for min/max frequency
2022-10-12 18:26 ` [Intel-gfx] " Vinay Belgaumkar
` (2 preceding siblings ...)
(?)
@ 2022-10-13 11:34 ` Tauro, Riana
2022-10-13 15:28 ` Belgaumkar, Vinay
-1 siblings, 1 reply; 10+ messages in thread
From: Tauro, Riana @ 2022-10-13 11:34 UTC (permalink / raw)
To: Vinay Belgaumkar, intel-gfx, dri-devel
On 10/12/2022 11:56 PM, Vinay Belgaumkar wrote:
> GuC will set the min/max frequencies to theoretical max on
> ATS-M. This will break kernel ABI, so limit min/max frequency
> to RP0(platform max) instead.
>
> Also modify the SLPC selftest to update the min frequency
> when we have a server part so that we can iterate between
> platform min and max.
>
> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> ---
> drivers/gpu/drm/i915/gt/selftest_slpc.c | 40 +++++++++++++------
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 29 ++++++++++++++
> .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 3 ++
> 3 files changed, 60 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c b/drivers/gpu/drm/i915/gt/selftest_slpc.c
> index 4c6e9257e593..1f84362af737 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_slpc.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_slpc.c
> @@ -234,6 +234,7 @@ static int run_test(struct intel_gt *gt, int test_type)
> enum intel_engine_id id;
> struct igt_spinner spin;
> u32 slpc_min_freq, slpc_max_freq;
> + u32 saved_min_freq;
> int err = 0;
>
> if (!intel_uc_uses_guc_slpc(>->uc))
> @@ -252,20 +253,35 @@ static int run_test(struct intel_gt *gt, int test_type)
> return -EIO;
> }
>
> - /*
> - * FIXME: With efficient frequency enabled, GuC can request
> - * frequencies higher than the SLPC max. While this is fixed
> - * in GuC, we level set these tests with RPn as min.
> - */
> - err = slpc_set_min_freq(slpc, slpc->min_freq);
> - if (err)
> - return err;
> -
> if (slpc->min_freq == slpc->rp0_freq) {
This has to be (slpc_min_freq == slpc_max_freq) instead of
(slpc->min_freq == slpc->rp0_freq).
Servers will have min/max softlimits clamped to RP0
Thanks
Riana
> - pr_err("Min/Max are fused to the same value\n");
> - return -EINVAL;
> + /* Servers will have min/max clamped to RP0 */
> + if (slpc->min_is_rpmax) {
> + err = slpc_set_min_freq(slpc, slpc->min_freq);
> + if (err) {
> + pr_err("Unable to update min freq on server part");
> + return err;
> + }
> +
> + } else {
> + pr_err("Min/Max are fused to the same value\n");
> + return -EINVAL;
> + }
> + } else {
> + /*
> + * FIXME: With efficient frequency enabled, GuC can request
> + * frequencies higher than the SLPC max. While this is fixed
> + * in GuC, we level set these tests with RPn as min.
> + */
> + err = slpc_set_min_freq(slpc, slpc->min_freq);
> + if (err)
> + return err;
> }
>
> + saved_min_freq = slpc_min_freq;
> +
> + /* New temp min freq = RPn */
> + slpc_min_freq = slpc->min_freq;
> +
> intel_gt_pm_wait_for_idle(gt);
> intel_gt_pm_get(gt);
> for_each_engine(engine, gt, id) {
> @@ -347,7 +363,7 @@ static int run_test(struct intel_gt *gt, int test_type)
>
> /* Restore min/max frequencies */
> slpc_set_max_freq(slpc, slpc_max_freq);
> - slpc_set_min_freq(slpc, slpc_min_freq);
> + slpc_set_min_freq(slpc, saved_min_freq);
>
> if (igt_flush_test(gt->i915))
> err = -EIO;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> index fdd895f73f9f..11613d373a49 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> @@ -263,6 +263,7 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
>
> slpc->max_freq_softlimit = 0;
> slpc->min_freq_softlimit = 0;
> + slpc->min_is_rpmax = false;
>
> slpc->boost_freq = 0;
> atomic_set(&slpc->num_waiters, 0);
> @@ -588,6 +589,31 @@ static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
> return 0;
> }
>
> +static bool is_slpc_min_freq_rpmax(struct intel_guc_slpc *slpc)
> +{
> + int slpc_min_freq;
> +
> + if (intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq))
> + return false;
> +
> + if (slpc_min_freq > slpc->rp0_freq)
> + return true;
> + else
> + return false;
> +}
> +
> +static void update_server_min_softlimit(struct intel_guc_slpc *slpc)
> +{
> + /* For server parts, SLPC min will be at RPMax.
> + * Use min softlimit to clamp it to RP0 instead.
> + */
> + if (is_slpc_min_freq_rpmax(slpc) &&
> + !slpc->min_freq_softlimit) {
> + slpc->min_is_rpmax = true;
> + slpc->min_freq_softlimit = slpc->rp0_freq;
> + }
> +}
> +
> static int slpc_use_fused_rp0(struct intel_guc_slpc *slpc)
> {
> /* Force SLPC to used platform rp0 */
> @@ -647,6 +673,9 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
>
> slpc_get_rp_values(slpc);
>
> + /* Handle the case where min=max=RPmax */
> + update_server_min_softlimit(slpc);
> +
> /* Set SLPC max limit to RP0 */
> ret = slpc_use_fused_rp0(slpc);
> if (unlikely(ret)) {
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
> index 73d208123528..a6ef53b04e04 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
> @@ -19,6 +19,9 @@ struct intel_guc_slpc {
> bool supported;
> bool selected;
>
> + /* Indicates this is a server part */
> + bool min_is_rpmax;
> +
> /* platform frequency limits */
> u32 min_freq;
> u32 rp0_freq;
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/i915/slpc: Use platform limits for min/max frequency
2022-10-12 18:26 ` [Intel-gfx] " Vinay Belgaumkar
@ 2022-10-13 15:14 ` Das, Nirmoy
-1 siblings, 0 replies; 10+ messages in thread
From: Das, Nirmoy @ 2022-10-13 15:14 UTC (permalink / raw)
To: Vinay Belgaumkar, intel-gfx, dri-devel
On 10/12/2022 8:26 PM, Vinay Belgaumkar wrote:
> GuC will set the min/max frequencies to theoretical max on
> ATS-M. This will break kernel ABI, so limit min/max frequency
> to RP0(platform max) instead.
>
> Also modify the SLPC selftest to update the min frequency
> when we have a server part so that we can iterate between
> platform min and max.
>
> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> ---
> drivers/gpu/drm/i915/gt/selftest_slpc.c | 40 +++++++++++++------
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 29 ++++++++++++++
> .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 3 ++
> 3 files changed, 60 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c b/drivers/gpu/drm/i915/gt/selftest_slpc.c
> index 4c6e9257e593..1f84362af737 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_slpc.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_slpc.c
> @@ -234,6 +234,7 @@ static int run_test(struct intel_gt *gt, int test_type)
> enum intel_engine_id id;
> struct igt_spinner spin;
> u32 slpc_min_freq, slpc_max_freq;
> + u32 saved_min_freq;
> int err = 0;
>
> if (!intel_uc_uses_guc_slpc(>->uc))
> @@ -252,20 +253,35 @@ static int run_test(struct intel_gt *gt, int test_type)
> return -EIO;
> }
>
> - /*
> - * FIXME: With efficient frequency enabled, GuC can request
> - * frequencies higher than the SLPC max. While this is fixed
> - * in GuC, we level set these tests with RPn as min.
> - */
> - err = slpc_set_min_freq(slpc, slpc->min_freq);
> - if (err)
> - return err;
> -
> if (slpc->min_freq == slpc->rp0_freq) {
> - pr_err("Min/Max are fused to the same value\n");
> - return -EINVAL;
> + /* Servers will have min/max clamped to RP0 */
This should be "server parts". Tested the patch with Riana's suggested
changes.
Acked-by: Nirmoy Das <nirmoy.das@intel.com> with above changes.
Nirmoy
> + if (slpc->min_is_rpmax) {
> + err = slpc_set_min_freq(slpc, slpc->min_freq);
> + if (err) {
> + pr_err("Unable to update min freq on server part");
> + return err;
> + }
> +
> + } else {
> + pr_err("Min/Max are fused to the same value\n");
> + return -EINVAL;
> + }
> + } else {
> + /*
> + * FIXME: With efficient frequency enabled, GuC can request
> + * frequencies higher than the SLPC max. While this is fixed
> + * in GuC, we level set these tests with RPn as min.
> + */
> + err = slpc_set_min_freq(slpc, slpc->min_freq);
> + if (err)
> + return err;
> }
>
> + saved_min_freq = slpc_min_freq;
> +
> + /* New temp min freq = RPn */
> + slpc_min_freq = slpc->min_freq;
> +
> intel_gt_pm_wait_for_idle(gt);
> intel_gt_pm_get(gt);
> for_each_engine(engine, gt, id) {
> @@ -347,7 +363,7 @@ static int run_test(struct intel_gt *gt, int test_type)
>
> /* Restore min/max frequencies */
> slpc_set_max_freq(slpc, slpc_max_freq);
> - slpc_set_min_freq(slpc, slpc_min_freq);
> + slpc_set_min_freq(slpc, saved_min_freq);
>
> if (igt_flush_test(gt->i915))
> err = -EIO;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> index fdd895f73f9f..11613d373a49 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> @@ -263,6 +263,7 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
>
> slpc->max_freq_softlimit = 0;
> slpc->min_freq_softlimit = 0;
> + slpc->min_is_rpmax = false;
>
> slpc->boost_freq = 0;
> atomic_set(&slpc->num_waiters, 0);
> @@ -588,6 +589,31 @@ static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
> return 0;
> }
>
> +static bool is_slpc_min_freq_rpmax(struct intel_guc_slpc *slpc)
> +{
> + int slpc_min_freq;
> +
> + if (intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq))
> + return false;
> +
> + if (slpc_min_freq > slpc->rp0_freq)
> + return true;
> + else
> + return false;
> +}
> +
> +static void update_server_min_softlimit(struct intel_guc_slpc *slpc)
> +{
> + /* For server parts, SLPC min will be at RPMax.
> + * Use min softlimit to clamp it to RP0 instead.
> + */
> + if (is_slpc_min_freq_rpmax(slpc) &&
> + !slpc->min_freq_softlimit) {
> + slpc->min_is_rpmax = true;
> + slpc->min_freq_softlimit = slpc->rp0_freq;
> + }
> +}
> +
> static int slpc_use_fused_rp0(struct intel_guc_slpc *slpc)
> {
> /* Force SLPC to used platform rp0 */
> @@ -647,6 +673,9 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
>
> slpc_get_rp_values(slpc);
>
> + /* Handle the case where min=max=RPmax */
> + update_server_min_softlimit(slpc);
> +
> /* Set SLPC max limit to RP0 */
> ret = slpc_use_fused_rp0(slpc);
> if (unlikely(ret)) {
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
> index 73d208123528..a6ef53b04e04 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
> @@ -19,6 +19,9 @@ struct intel_guc_slpc {
> bool supported;
> bool selected;
>
> + /* Indicates this is a server part */
> + bool min_is_rpmax;
> +
> /* platform frequency limits */
> u32 min_freq;
> u32 rp0_freq;
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/slpc: Use platform limits for min/max frequency
@ 2022-10-13 15:14 ` Das, Nirmoy
0 siblings, 0 replies; 10+ messages in thread
From: Das, Nirmoy @ 2022-10-13 15:14 UTC (permalink / raw)
To: Vinay Belgaumkar, intel-gfx, dri-devel
On 10/12/2022 8:26 PM, Vinay Belgaumkar wrote:
> GuC will set the min/max frequencies to theoretical max on
> ATS-M. This will break kernel ABI, so limit min/max frequency
> to RP0(platform max) instead.
>
> Also modify the SLPC selftest to update the min frequency
> when we have a server part so that we can iterate between
> platform min and max.
>
> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> ---
> drivers/gpu/drm/i915/gt/selftest_slpc.c | 40 +++++++++++++------
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 29 ++++++++++++++
> .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 3 ++
> 3 files changed, 60 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c b/drivers/gpu/drm/i915/gt/selftest_slpc.c
> index 4c6e9257e593..1f84362af737 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_slpc.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_slpc.c
> @@ -234,6 +234,7 @@ static int run_test(struct intel_gt *gt, int test_type)
> enum intel_engine_id id;
> struct igt_spinner spin;
> u32 slpc_min_freq, slpc_max_freq;
> + u32 saved_min_freq;
> int err = 0;
>
> if (!intel_uc_uses_guc_slpc(>->uc))
> @@ -252,20 +253,35 @@ static int run_test(struct intel_gt *gt, int test_type)
> return -EIO;
> }
>
> - /*
> - * FIXME: With efficient frequency enabled, GuC can request
> - * frequencies higher than the SLPC max. While this is fixed
> - * in GuC, we level set these tests with RPn as min.
> - */
> - err = slpc_set_min_freq(slpc, slpc->min_freq);
> - if (err)
> - return err;
> -
> if (slpc->min_freq == slpc->rp0_freq) {
> - pr_err("Min/Max are fused to the same value\n");
> - return -EINVAL;
> + /* Servers will have min/max clamped to RP0 */
This should be "server parts". Tested the patch with Riana's suggested
changes.
Acked-by: Nirmoy Das <nirmoy.das@intel.com> with above changes.
Nirmoy
> + if (slpc->min_is_rpmax) {
> + err = slpc_set_min_freq(slpc, slpc->min_freq);
> + if (err) {
> + pr_err("Unable to update min freq on server part");
> + return err;
> + }
> +
> + } else {
> + pr_err("Min/Max are fused to the same value\n");
> + return -EINVAL;
> + }
> + } else {
> + /*
> + * FIXME: With efficient frequency enabled, GuC can request
> + * frequencies higher than the SLPC max. While this is fixed
> + * in GuC, we level set these tests with RPn as min.
> + */
> + err = slpc_set_min_freq(slpc, slpc->min_freq);
> + if (err)
> + return err;
> }
>
> + saved_min_freq = slpc_min_freq;
> +
> + /* New temp min freq = RPn */
> + slpc_min_freq = slpc->min_freq;
> +
> intel_gt_pm_wait_for_idle(gt);
> intel_gt_pm_get(gt);
> for_each_engine(engine, gt, id) {
> @@ -347,7 +363,7 @@ static int run_test(struct intel_gt *gt, int test_type)
>
> /* Restore min/max frequencies */
> slpc_set_max_freq(slpc, slpc_max_freq);
> - slpc_set_min_freq(slpc, slpc_min_freq);
> + slpc_set_min_freq(slpc, saved_min_freq);
>
> if (igt_flush_test(gt->i915))
> err = -EIO;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> index fdd895f73f9f..11613d373a49 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> @@ -263,6 +263,7 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
>
> slpc->max_freq_softlimit = 0;
> slpc->min_freq_softlimit = 0;
> + slpc->min_is_rpmax = false;
>
> slpc->boost_freq = 0;
> atomic_set(&slpc->num_waiters, 0);
> @@ -588,6 +589,31 @@ static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
> return 0;
> }
>
> +static bool is_slpc_min_freq_rpmax(struct intel_guc_slpc *slpc)
> +{
> + int slpc_min_freq;
> +
> + if (intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq))
> + return false;
> +
> + if (slpc_min_freq > slpc->rp0_freq)
> + return true;
> + else
> + return false;
> +}
> +
> +static void update_server_min_softlimit(struct intel_guc_slpc *slpc)
> +{
> + /* For server parts, SLPC min will be at RPMax.
> + * Use min softlimit to clamp it to RP0 instead.
> + */
> + if (is_slpc_min_freq_rpmax(slpc) &&
> + !slpc->min_freq_softlimit) {
> + slpc->min_is_rpmax = true;
> + slpc->min_freq_softlimit = slpc->rp0_freq;
> + }
> +}
> +
> static int slpc_use_fused_rp0(struct intel_guc_slpc *slpc)
> {
> /* Force SLPC to used platform rp0 */
> @@ -647,6 +673,9 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
>
> slpc_get_rp_values(slpc);
>
> + /* Handle the case where min=max=RPmax */
> + update_server_min_softlimit(slpc);
> +
> /* Set SLPC max limit to RP0 */
> ret = slpc_use_fused_rp0(slpc);
> if (unlikely(ret)) {
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
> index 73d208123528..a6ef53b04e04 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
> @@ -19,6 +19,9 @@ struct intel_guc_slpc {
> bool supported;
> bool selected;
>
> + /* Indicates this is a server part */
> + bool min_is_rpmax;
> +
> /* platform frequency limits */
> u32 min_freq;
> u32 rp0_freq;
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/slpc: Use platform limits for min/max frequency
2022-10-13 11:34 ` [Intel-gfx] [PATCH] " Tauro, Riana
@ 2022-10-13 15:28 ` Belgaumkar, Vinay
0 siblings, 0 replies; 10+ messages in thread
From: Belgaumkar, Vinay @ 2022-10-13 15:28 UTC (permalink / raw)
To: Tauro, Riana, intel-gfx, dri-devel
On 10/13/2022 4:34 AM, Tauro, Riana wrote:
>
>
> On 10/12/2022 11:56 PM, Vinay Belgaumkar wrote:
>> GuC will set the min/max frequencies to theoretical max on
>> ATS-M. This will break kernel ABI, so limit min/max frequency
>> to RP0(platform max) instead.
>>
>> Also modify the SLPC selftest to update the min frequency
>> when we have a server part so that we can iterate between
>> platform min and max.
>>
>> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/selftest_slpc.c | 40 +++++++++++++------
>> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 29 ++++++++++++++
>> .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 3 ++
>> 3 files changed, 60 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c
>> b/drivers/gpu/drm/i915/gt/selftest_slpc.c
>> index 4c6e9257e593..1f84362af737 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_slpc.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_slpc.c
>> @@ -234,6 +234,7 @@ static int run_test(struct intel_gt *gt, int
>> test_type)
>> enum intel_engine_id id;
>> struct igt_spinner spin;
>> u32 slpc_min_freq, slpc_max_freq;
>> + u32 saved_min_freq;
>> int err = 0;
>> if (!intel_uc_uses_guc_slpc(>->uc))
>> @@ -252,20 +253,35 @@ static int run_test(struct intel_gt *gt, int
>> test_type)
>> return -EIO;
>> }
>> - /*
>> - * FIXME: With efficient frequency enabled, GuC can request
>> - * frequencies higher than the SLPC max. While this is fixed
>> - * in GuC, we level set these tests with RPn as min.
>> - */
>> - err = slpc_set_min_freq(slpc, slpc->min_freq);
>> - if (err)
>> - return err;
>> -
>> if (slpc->min_freq == slpc->rp0_freq) {
> This has to be (slpc_min_freq == slpc_max_freq) instead of
> (slpc->min_freq == slpc->rp0_freq).
>
> Servers will have min/max softlimits clamped to RP0
Agree. will send out v2.
Thanks,
Vinay.
>
> Thanks
> Riana
>> - pr_err("Min/Max are fused to the same value\n");
>> - return -EINVAL;
>> + /* Servers will have min/max clamped to RP0 */
>> + if (slpc->min_is_rpmax) {
>> + err = slpc_set_min_freq(slpc, slpc->min_freq);
>> + if (err) {
>> + pr_err("Unable to update min freq on server part");
>> + return err;
>> + }
>> +
>> + } else {
>> + pr_err("Min/Max are fused to the same value\n");
>> + return -EINVAL;
>> + }
>> + } else {
>> + /*
>> + * FIXME: With efficient frequency enabled, GuC can request
>> + * frequencies higher than the SLPC max. While this is fixed
>> + * in GuC, we level set these tests with RPn as min.
>> + */
>> + err = slpc_set_min_freq(slpc, slpc->min_freq);
>> + if (err)
>> + return err;
>> }
>> + saved_min_freq = slpc_min_freq;
>> +
>> + /* New temp min freq = RPn */
>> + slpc_min_freq = slpc->min_freq;
>> +
>> intel_gt_pm_wait_for_idle(gt);
>> intel_gt_pm_get(gt);
>> for_each_engine(engine, gt, id) {
>> @@ -347,7 +363,7 @@ static int run_test(struct intel_gt *gt, int
>> test_type)
>> /* Restore min/max frequencies */
>> slpc_set_max_freq(slpc, slpc_max_freq);
>> - slpc_set_min_freq(slpc, slpc_min_freq);
>> + slpc_set_min_freq(slpc, saved_min_freq);
>> if (igt_flush_test(gt->i915))
>> err = -EIO;
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> index fdd895f73f9f..11613d373a49 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> @@ -263,6 +263,7 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
>> slpc->max_freq_softlimit = 0;
>> slpc->min_freq_softlimit = 0;
>> + slpc->min_is_rpmax = false;
>> slpc->boost_freq = 0;
>> atomic_set(&slpc->num_waiters, 0);
>> @@ -588,6 +589,31 @@ static int slpc_set_softlimits(struct
>> intel_guc_slpc *slpc)
>> return 0;
>> }
>> +static bool is_slpc_min_freq_rpmax(struct intel_guc_slpc *slpc)
>> +{
>> + int slpc_min_freq;
>> +
>> + if (intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq))
>> + return false;
>> +
>> + if (slpc_min_freq > slpc->rp0_freq)
>> + return true;
>> + else
>> + return false;
>> +}
>> +
>> +static void update_server_min_softlimit(struct intel_guc_slpc *slpc)
>> +{
>> + /* For server parts, SLPC min will be at RPMax.
>> + * Use min softlimit to clamp it to RP0 instead.
>> + */
>> + if (is_slpc_min_freq_rpmax(slpc) &&
>> + !slpc->min_freq_softlimit) {
>> + slpc->min_is_rpmax = true;
>> + slpc->min_freq_softlimit = slpc->rp0_freq;
>> + }
>> +}
>> +
>> static int slpc_use_fused_rp0(struct intel_guc_slpc *slpc)
>> {
>> /* Force SLPC to used platform rp0 */
>> @@ -647,6 +673,9 @@ int intel_guc_slpc_enable(struct intel_guc_slpc
>> *slpc)
>> slpc_get_rp_values(slpc);
>> + /* Handle the case where min=max=RPmax */
>> + update_server_min_softlimit(slpc);
>> +
>> /* Set SLPC max limit to RP0 */
>> ret = slpc_use_fused_rp0(slpc);
>> if (unlikely(ret)) {
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>> index 73d208123528..a6ef53b04e04 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>> @@ -19,6 +19,9 @@ struct intel_guc_slpc {
>> bool supported;
>> bool selected;
>> + /* Indicates this is a server part */
>> + bool min_is_rpmax;
>> +
>> /* platform frequency limits */
>> u32 min_freq;
>> u32 rp0_freq;
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/i915/slpc: Use platform limits for min/max frequency
2022-10-13 15:14 ` [Intel-gfx] " Das, Nirmoy
@ 2022-10-13 15:56 ` Belgaumkar, Vinay
-1 siblings, 0 replies; 10+ messages in thread
From: Belgaumkar, Vinay @ 2022-10-13 15:56 UTC (permalink / raw)
To: Das, Nirmoy, intel-gfx, dri-devel
On 10/13/2022 8:14 AM, Das, Nirmoy wrote:
>
> On 10/12/2022 8:26 PM, Vinay Belgaumkar wrote:
>> GuC will set the min/max frequencies to theoretical max on
>> ATS-M. This will break kernel ABI, so limit min/max frequency
>> to RP0(platform max) instead.
>>
>> Also modify the SLPC selftest to update the min frequency
>> when we have a server part so that we can iterate between
>> platform min and max.
>>
>> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/selftest_slpc.c | 40 +++++++++++++------
>> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 29 ++++++++++++++
>> .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 3 ++
>> 3 files changed, 60 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c
>> b/drivers/gpu/drm/i915/gt/selftest_slpc.c
>> index 4c6e9257e593..1f84362af737 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_slpc.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_slpc.c
>> @@ -234,6 +234,7 @@ static int run_test(struct intel_gt *gt, int
>> test_type)
>> enum intel_engine_id id;
>> struct igt_spinner spin;
>> u32 slpc_min_freq, slpc_max_freq;
>> + u32 saved_min_freq;
>> int err = 0;
>> if (!intel_uc_uses_guc_slpc(>->uc))
>> @@ -252,20 +253,35 @@ static int run_test(struct intel_gt *gt, int
>> test_type)
>> return -EIO;
>> }
>> - /*
>> - * FIXME: With efficient frequency enabled, GuC can request
>> - * frequencies higher than the SLPC max. While this is fixed
>> - * in GuC, we level set these tests with RPn as min.
>> - */
>> - err = slpc_set_min_freq(slpc, slpc->min_freq);
>> - if (err)
>> - return err;
>> -
>> if (slpc->min_freq == slpc->rp0_freq) {
>> - pr_err("Min/Max are fused to the same value\n");
>> - return -EINVAL;
>> + /* Servers will have min/max clamped to RP0 */
>
>
> This should be "server parts". Tested the patch with Riana's suggested
> changes.
>
> Acked-by: Nirmoy Das <nirmoy.das@intel.com> with above changes.
Thanks, v2 sent with corrections.
Vinay.
>
>
> Nirmoy
>
>> + if (slpc->min_is_rpmax) {
>> + err = slpc_set_min_freq(slpc, slpc->min_freq);
>> + if (err) {
>> + pr_err("Unable to update min freq on server part");
>> + return err;
>> + }
>> +
>> + } else {
>> + pr_err("Min/Max are fused to the same value\n");
>> + return -EINVAL;
>> + }
>> + } else {
>> + /*
>> + * FIXME: With efficient frequency enabled, GuC can request
>> + * frequencies higher than the SLPC max. While this is fixed
>> + * in GuC, we level set these tests with RPn as min.
>> + */
>> + err = slpc_set_min_freq(slpc, slpc->min_freq);
>> + if (err)
>> + return err;
>> }
>> + saved_min_freq = slpc_min_freq;
>> +
>> + /* New temp min freq = RPn */
>> + slpc_min_freq = slpc->min_freq;
>> +
>> intel_gt_pm_wait_for_idle(gt);
>> intel_gt_pm_get(gt);
>> for_each_engine(engine, gt, id) {
>> @@ -347,7 +363,7 @@ static int run_test(struct intel_gt *gt, int
>> test_type)
>> /* Restore min/max frequencies */
>> slpc_set_max_freq(slpc, slpc_max_freq);
>> - slpc_set_min_freq(slpc, slpc_min_freq);
>> + slpc_set_min_freq(slpc, saved_min_freq);
>> if (igt_flush_test(gt->i915))
>> err = -EIO;
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> index fdd895f73f9f..11613d373a49 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> @@ -263,6 +263,7 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
>> slpc->max_freq_softlimit = 0;
>> slpc->min_freq_softlimit = 0;
>> + slpc->min_is_rpmax = false;
>> slpc->boost_freq = 0;
>> atomic_set(&slpc->num_waiters, 0);
>> @@ -588,6 +589,31 @@ static int slpc_set_softlimits(struct
>> intel_guc_slpc *slpc)
>> return 0;
>> }
>> +static bool is_slpc_min_freq_rpmax(struct intel_guc_slpc *slpc)
>> +{
>> + int slpc_min_freq;
>> +
>> + if (intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq))
>> + return false;
>> +
>> + if (slpc_min_freq > slpc->rp0_freq)
>> + return true;
>> + else
>> + return false;
>> +}
>> +
>> +static void update_server_min_softlimit(struct intel_guc_slpc *slpc)
>> +{
>> + /* For server parts, SLPC min will be at RPMax.
>> + * Use min softlimit to clamp it to RP0 instead.
>> + */
>> + if (is_slpc_min_freq_rpmax(slpc) &&
>> + !slpc->min_freq_softlimit) {
>> + slpc->min_is_rpmax = true;
>> + slpc->min_freq_softlimit = slpc->rp0_freq;
>> + }
>> +}
>> +
>> static int slpc_use_fused_rp0(struct intel_guc_slpc *slpc)
>> {
>> /* Force SLPC to used platform rp0 */
>> @@ -647,6 +673,9 @@ int intel_guc_slpc_enable(struct intel_guc_slpc
>> *slpc)
>> slpc_get_rp_values(slpc);
>> + /* Handle the case where min=max=RPmax */
>> + update_server_min_softlimit(slpc);
>> +
>> /* Set SLPC max limit to RP0 */
>> ret = slpc_use_fused_rp0(slpc);
>> if (unlikely(ret)) {
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>> index 73d208123528..a6ef53b04e04 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>> @@ -19,6 +19,9 @@ struct intel_guc_slpc {
>> bool supported;
>> bool selected;
>> + /* Indicates this is a server part */
>> + bool min_is_rpmax;
>> +
>> /* platform frequency limits */
>> u32 min_freq;
>> u32 rp0_freq;
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/slpc: Use platform limits for min/max frequency
@ 2022-10-13 15:56 ` Belgaumkar, Vinay
0 siblings, 0 replies; 10+ messages in thread
From: Belgaumkar, Vinay @ 2022-10-13 15:56 UTC (permalink / raw)
To: Das, Nirmoy, intel-gfx, dri-devel
On 10/13/2022 8:14 AM, Das, Nirmoy wrote:
>
> On 10/12/2022 8:26 PM, Vinay Belgaumkar wrote:
>> GuC will set the min/max frequencies to theoretical max on
>> ATS-M. This will break kernel ABI, so limit min/max frequency
>> to RP0(platform max) instead.
>>
>> Also modify the SLPC selftest to update the min frequency
>> when we have a server part so that we can iterate between
>> platform min and max.
>>
>> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/selftest_slpc.c | 40 +++++++++++++------
>> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 29 ++++++++++++++
>> .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 3 ++
>> 3 files changed, 60 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c
>> b/drivers/gpu/drm/i915/gt/selftest_slpc.c
>> index 4c6e9257e593..1f84362af737 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_slpc.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_slpc.c
>> @@ -234,6 +234,7 @@ static int run_test(struct intel_gt *gt, int
>> test_type)
>> enum intel_engine_id id;
>> struct igt_spinner spin;
>> u32 slpc_min_freq, slpc_max_freq;
>> + u32 saved_min_freq;
>> int err = 0;
>> if (!intel_uc_uses_guc_slpc(>->uc))
>> @@ -252,20 +253,35 @@ static int run_test(struct intel_gt *gt, int
>> test_type)
>> return -EIO;
>> }
>> - /*
>> - * FIXME: With efficient frequency enabled, GuC can request
>> - * frequencies higher than the SLPC max. While this is fixed
>> - * in GuC, we level set these tests with RPn as min.
>> - */
>> - err = slpc_set_min_freq(slpc, slpc->min_freq);
>> - if (err)
>> - return err;
>> -
>> if (slpc->min_freq == slpc->rp0_freq) {
>> - pr_err("Min/Max are fused to the same value\n");
>> - return -EINVAL;
>> + /* Servers will have min/max clamped to RP0 */
>
>
> This should be "server parts". Tested the patch with Riana's suggested
> changes.
>
> Acked-by: Nirmoy Das <nirmoy.das@intel.com> with above changes.
Thanks, v2 sent with corrections.
Vinay.
>
>
> Nirmoy
>
>> + if (slpc->min_is_rpmax) {
>> + err = slpc_set_min_freq(slpc, slpc->min_freq);
>> + if (err) {
>> + pr_err("Unable to update min freq on server part");
>> + return err;
>> + }
>> +
>> + } else {
>> + pr_err("Min/Max are fused to the same value\n");
>> + return -EINVAL;
>> + }
>> + } else {
>> + /*
>> + * FIXME: With efficient frequency enabled, GuC can request
>> + * frequencies higher than the SLPC max. While this is fixed
>> + * in GuC, we level set these tests with RPn as min.
>> + */
>> + err = slpc_set_min_freq(slpc, slpc->min_freq);
>> + if (err)
>> + return err;
>> }
>> + saved_min_freq = slpc_min_freq;
>> +
>> + /* New temp min freq = RPn */
>> + slpc_min_freq = slpc->min_freq;
>> +
>> intel_gt_pm_wait_for_idle(gt);
>> intel_gt_pm_get(gt);
>> for_each_engine(engine, gt, id) {
>> @@ -347,7 +363,7 @@ static int run_test(struct intel_gt *gt, int
>> test_type)
>> /* Restore min/max frequencies */
>> slpc_set_max_freq(slpc, slpc_max_freq);
>> - slpc_set_min_freq(slpc, slpc_min_freq);
>> + slpc_set_min_freq(slpc, saved_min_freq);
>> if (igt_flush_test(gt->i915))
>> err = -EIO;
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> index fdd895f73f9f..11613d373a49 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> @@ -263,6 +263,7 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
>> slpc->max_freq_softlimit = 0;
>> slpc->min_freq_softlimit = 0;
>> + slpc->min_is_rpmax = false;
>> slpc->boost_freq = 0;
>> atomic_set(&slpc->num_waiters, 0);
>> @@ -588,6 +589,31 @@ static int slpc_set_softlimits(struct
>> intel_guc_slpc *slpc)
>> return 0;
>> }
>> +static bool is_slpc_min_freq_rpmax(struct intel_guc_slpc *slpc)
>> +{
>> + int slpc_min_freq;
>> +
>> + if (intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq))
>> + return false;
>> +
>> + if (slpc_min_freq > slpc->rp0_freq)
>> + return true;
>> + else
>> + return false;
>> +}
>> +
>> +static void update_server_min_softlimit(struct intel_guc_slpc *slpc)
>> +{
>> + /* For server parts, SLPC min will be at RPMax.
>> + * Use min softlimit to clamp it to RP0 instead.
>> + */
>> + if (is_slpc_min_freq_rpmax(slpc) &&
>> + !slpc->min_freq_softlimit) {
>> + slpc->min_is_rpmax = true;
>> + slpc->min_freq_softlimit = slpc->rp0_freq;
>> + }
>> +}
>> +
>> static int slpc_use_fused_rp0(struct intel_guc_slpc *slpc)
>> {
>> /* Force SLPC to used platform rp0 */
>> @@ -647,6 +673,9 @@ int intel_guc_slpc_enable(struct intel_guc_slpc
>> *slpc)
>> slpc_get_rp_values(slpc);
>> + /* Handle the case where min=max=RPmax */
>> + update_server_min_softlimit(slpc);
>> +
>> /* Set SLPC max limit to RP0 */
>> ret = slpc_use_fused_rp0(slpc);
>> if (unlikely(ret)) {
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>> index 73d208123528..a6ef53b04e04 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>> @@ -19,6 +19,9 @@ struct intel_guc_slpc {
>> bool supported;
>> bool selected;
>> + /* Indicates this is a server part */
>> + bool min_is_rpmax;
>> +
>> /* platform frequency limits */
>> u32 min_freq;
>> u32 rp0_freq;
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2022-10-13 15:56 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-12 18:26 [PATCH] drm/i915/slpc: Use platform limits for min/max frequency Vinay Belgaumkar
2022-10-12 18:26 ` [Intel-gfx] " Vinay Belgaumkar
2022-10-12 19:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2022-10-13 2:30 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-10-13 11:34 ` [Intel-gfx] [PATCH] " Tauro, Riana
2022-10-13 15:28 ` Belgaumkar, Vinay
2022-10-13 15:14 ` Das, Nirmoy
2022-10-13 15:14 ` [Intel-gfx] " Das, Nirmoy
2022-10-13 15:56 ` Belgaumkar, Vinay
2022-10-13 15:56 ` [Intel-gfx] " Belgaumkar, Vinay
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