* [PATCH 0/5] i915: CAGF and RC6 changes for MTL
@ 2022-10-24 20:24 ` Ashutosh Dixit
0 siblings, 0 replies; 19+ messages in thread
From: Ashutosh Dixit @ 2022-10-24 20:24 UTC (permalink / raw)
To: intel-gfx; +Cc: Badal Nilawar, dri-devel, Rodrigo Vivi
This series includes the code changes to get CAGF, RC State and C6
Residency of MTL.
v3: Included "Use GEN12 RPSTAT register" patch
v4:
- Rebased
- Dropped "Use GEN12 RPSTAT register" patch from this series
going to send separate series for it
v5:
- Included "drm/i915/gt: Change RC6 residency functions to accept register
ID's" based on code review feedback
v6:
- Addressed Jani N's review comments on "drm/i915/gt: Change RC6 residency
functions to accept register ID's"
- Re-add "drm/i915: Use GEN12_RPSTAT register for GT freq" to this series
v7: Rebuild, identical to v6
v8:
- Add "drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf" to the series
(based on Rodrigo's review) to consistently use REG_FIELD_GET
- Minor changes to other patches, please see individual patches for changelogs
v9: Rebuild, identical to v8
v10: Address review comments from Rodrigo on Patch 5
v11: Change state name for MTL_CC0 to RC0 in Patch 5
Ashutosh Dixit (2):
drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf
drm/i915/gt: Use RC6 residency types as arguments to residency
functions
Badal Nilawar (2):
drm/i915/mtl: Modify CAGF functions for MTL
drm/i915/mtl: C6 residency and C state type for MTL SAMedia
Don Hiatt (1):
drm/i915: Use GEN12_RPSTAT register for GT freq
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 88 ++++++++++++++-----
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 22 +++--
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 12 +--
drivers/gpu/drm/i915/gt/intel_rc6.c | 64 +++++++++-----
drivers/gpu/drm/i915/gt/intel_rc6.h | 11 ++-
drivers/gpu/drm/i915/gt/intel_rc6_types.h | 15 +++-
drivers/gpu/drm/i915/gt/intel_rps.c | 51 ++++++++---
drivers/gpu/drm/i915/gt/intel_rps.h | 2 +
drivers/gpu/drm/i915/gt/selftest_rc6.c | 6 +-
drivers/gpu/drm/i915/i915_pmu.c | 9 +-
10 files changed, 198 insertions(+), 82 deletions(-)
--
2.38.0
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH 0/5] i915: CAGF and RC6 changes for MTL
@ 2022-10-24 20:24 ` Ashutosh Dixit
0 siblings, 0 replies; 19+ messages in thread
From: Ashutosh Dixit @ 2022-10-24 20:24 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Rodrigo Vivi
This series includes the code changes to get CAGF, RC State and C6
Residency of MTL.
v3: Included "Use GEN12 RPSTAT register" patch
v4:
- Rebased
- Dropped "Use GEN12 RPSTAT register" patch from this series
going to send separate series for it
v5:
- Included "drm/i915/gt: Change RC6 residency functions to accept register
ID's" based on code review feedback
v6:
- Addressed Jani N's review comments on "drm/i915/gt: Change RC6 residency
functions to accept register ID's"
- Re-add "drm/i915: Use GEN12_RPSTAT register for GT freq" to this series
v7: Rebuild, identical to v6
v8:
- Add "drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf" to the series
(based on Rodrigo's review) to consistently use REG_FIELD_GET
- Minor changes to other patches, please see individual patches for changelogs
v9: Rebuild, identical to v8
v10: Address review comments from Rodrigo on Patch 5
v11: Change state name for MTL_CC0 to RC0 in Patch 5
Ashutosh Dixit (2):
drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf
drm/i915/gt: Use RC6 residency types as arguments to residency
functions
Badal Nilawar (2):
drm/i915/mtl: Modify CAGF functions for MTL
drm/i915/mtl: C6 residency and C state type for MTL SAMedia
Don Hiatt (1):
drm/i915: Use GEN12_RPSTAT register for GT freq
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 88 ++++++++++++++-----
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 22 +++--
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 12 +--
drivers/gpu/drm/i915/gt/intel_rc6.c | 64 +++++++++-----
drivers/gpu/drm/i915/gt/intel_rc6.h | 11 ++-
drivers/gpu/drm/i915/gt/intel_rc6_types.h | 15 +++-
drivers/gpu/drm/i915/gt/intel_rps.c | 51 ++++++++---
drivers/gpu/drm/i915/gt/intel_rps.h | 2 +
drivers/gpu/drm/i915/gt/selftest_rc6.c | 6 +-
drivers/gpu/drm/i915/i915_pmu.c | 9 +-
10 files changed, 198 insertions(+), 82 deletions(-)
--
2.38.0
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 1/5] drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf
2022-10-24 20:24 ` [Intel-gfx] " Ashutosh Dixit
@ 2022-10-24 20:24 ` Ashutosh Dixit
-1 siblings, 0 replies; 19+ messages in thread
From: Ashutosh Dixit @ 2022-10-24 20:24 UTC (permalink / raw)
To: intel-gfx; +Cc: Badal Nilawar, dri-devel, Rodrigo Vivi
Instead of masks/shifts settle on REG_FIELD_GET as the standard way to
extract reg fields. This allows future patches touching this code to also
consistently use REG_FIELD_GET and friends.
Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 12 ++++--------
drivers/gpu/drm/i915/gt/intel_rps.c | 11 +++++------
3 files changed, 10 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 40d0a3be42acf..979e602946549 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -307,7 +307,7 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p)
drm_printf(p, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
MEMSTAT_VID_SHIFT);
drm_printf(p, "Current P-state: %d\n",
- (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
+ REG_FIELD_GET(MEMSTAT_PSTATE_MASK, rgvstat));
} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
u32 rpmodectl, freq_sts;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 36d95b79022c0..35c039573294c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -794,12 +794,9 @@
#define GEN6_RP_DOWN_TIMEOUT _MMIO(0xa010)
#define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xa014)
#define GEN6_RPSTAT1 _MMIO(0xa01c)
-#define GEN6_CAGF_SHIFT 8
-#define HSW_CAGF_SHIFT 7
-#define GEN9_CAGF_SHIFT 23
-#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
-#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
-#define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
+#define GEN6_CAGF_MASK REG_GENMASK(14, 8)
+#define HSW_CAGF_MASK REG_GENMASK(13, 7)
+#define GEN9_CAGF_MASK REG_GENMASK(31, 23)
#define GEN6_RP_CONTROL _MMIO(0xa024)
#define GEN6_RP_MEDIA_TURBO (1 << 11)
#define GEN6_RP_MEDIA_MODE_MASK (3 << 9)
@@ -1370,8 +1367,7 @@
#define MEMSTAT_ILK _MMIO(0x111f8)
#define MEMSTAT_VID_MASK 0x7f00
#define MEMSTAT_VID_SHIFT 8
-#define MEMSTAT_PSTATE_MASK 0x00f8
-#define MEMSTAT_PSTATE_SHIFT 3
+#define MEMSTAT_PSTATE_MASK REG_GENMASK(7, 3)
#define MEMSTAT_MON_ACTV (1 << 2)
#define MEMSTAT_SRC_CTL_MASK 0x0003
#define MEMSTAT_SRC_CTL_CORE 0
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 070005dd0da47..5061b5b3cece7 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2072,16 +2072,15 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
u32 cagf;
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
- cagf = (rpstat >> 8) & 0xff;
+ cagf = REG_FIELD_GET(RPE_MASK, rpstat);
else if (GRAPHICS_VER(i915) >= 9)
- cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
+ cagf = REG_FIELD_GET(GEN9_CAGF_MASK, rpstat);
else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
- cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
+ cagf = REG_FIELD_GET(HSW_CAGF_MASK, rpstat);
else if (GRAPHICS_VER(i915) >= 6)
- cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
+ cagf = REG_FIELD_GET(GEN6_CAGF_MASK, rpstat);
else
- cagf = gen5_invert_freq(rps, (rpstat & MEMSTAT_PSTATE_MASK) >>
- MEMSTAT_PSTATE_SHIFT);
+ cagf = gen5_invert_freq(rps, REG_FIELD_GET(MEMSTAT_PSTATE_MASK, rpstat));
return cagf;
}
--
2.38.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH 1/5] drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf
@ 2022-10-24 20:24 ` Ashutosh Dixit
0 siblings, 0 replies; 19+ messages in thread
From: Ashutosh Dixit @ 2022-10-24 20:24 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Rodrigo Vivi
Instead of masks/shifts settle on REG_FIELD_GET as the standard way to
extract reg fields. This allows future patches touching this code to also
consistently use REG_FIELD_GET and friends.
Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 12 ++++--------
drivers/gpu/drm/i915/gt/intel_rps.c | 11 +++++------
3 files changed, 10 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 40d0a3be42acf..979e602946549 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -307,7 +307,7 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p)
drm_printf(p, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
MEMSTAT_VID_SHIFT);
drm_printf(p, "Current P-state: %d\n",
- (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
+ REG_FIELD_GET(MEMSTAT_PSTATE_MASK, rgvstat));
} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
u32 rpmodectl, freq_sts;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 36d95b79022c0..35c039573294c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -794,12 +794,9 @@
#define GEN6_RP_DOWN_TIMEOUT _MMIO(0xa010)
#define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xa014)
#define GEN6_RPSTAT1 _MMIO(0xa01c)
-#define GEN6_CAGF_SHIFT 8
-#define HSW_CAGF_SHIFT 7
-#define GEN9_CAGF_SHIFT 23
-#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
-#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
-#define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
+#define GEN6_CAGF_MASK REG_GENMASK(14, 8)
+#define HSW_CAGF_MASK REG_GENMASK(13, 7)
+#define GEN9_CAGF_MASK REG_GENMASK(31, 23)
#define GEN6_RP_CONTROL _MMIO(0xa024)
#define GEN6_RP_MEDIA_TURBO (1 << 11)
#define GEN6_RP_MEDIA_MODE_MASK (3 << 9)
@@ -1370,8 +1367,7 @@
#define MEMSTAT_ILK _MMIO(0x111f8)
#define MEMSTAT_VID_MASK 0x7f00
#define MEMSTAT_VID_SHIFT 8
-#define MEMSTAT_PSTATE_MASK 0x00f8
-#define MEMSTAT_PSTATE_SHIFT 3
+#define MEMSTAT_PSTATE_MASK REG_GENMASK(7, 3)
#define MEMSTAT_MON_ACTV (1 << 2)
#define MEMSTAT_SRC_CTL_MASK 0x0003
#define MEMSTAT_SRC_CTL_CORE 0
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 070005dd0da47..5061b5b3cece7 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2072,16 +2072,15 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
u32 cagf;
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
- cagf = (rpstat >> 8) & 0xff;
+ cagf = REG_FIELD_GET(RPE_MASK, rpstat);
else if (GRAPHICS_VER(i915) >= 9)
- cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
+ cagf = REG_FIELD_GET(GEN9_CAGF_MASK, rpstat);
else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
- cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
+ cagf = REG_FIELD_GET(HSW_CAGF_MASK, rpstat);
else if (GRAPHICS_VER(i915) >= 6)
- cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
+ cagf = REG_FIELD_GET(GEN6_CAGF_MASK, rpstat);
else
- cagf = gen5_invert_freq(rps, (rpstat & MEMSTAT_PSTATE_MASK) >>
- MEMSTAT_PSTATE_SHIFT);
+ cagf = gen5_invert_freq(rps, REG_FIELD_GET(MEMSTAT_PSTATE_MASK, rpstat));
return cagf;
}
--
2.38.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 2/5] drm/i915: Use GEN12_RPSTAT register for GT freq
2022-10-24 20:24 ` [Intel-gfx] " Ashutosh Dixit
@ 2022-10-24 20:24 ` Ashutosh Dixit
-1 siblings, 0 replies; 19+ messages in thread
From: Ashutosh Dixit @ 2022-10-24 20:24 UTC (permalink / raw)
To: intel-gfx; +Cc: Badal Nilawar, dri-devel, Rodrigo Vivi
From: Don Hiatt <don.hiatt@intel.com>
On GEN12+ use GEN12_RPSTAT register to get actual resolved GT
freq. GEN12_RPSTAT does not require a forcewake and will return 0 freq if
GT is in RC6.
v2:
- Fixed review comments(Ashutosh)
- Added function intel_rps_read_rpstat_fw to read RPSTAT without
forcewake, required especially for GEN6_RPSTAT1 (Ashutosh, Tvrtko)
v3:
- Updated commit title and message for more clarity (Ashutosh)
- Replaced intel_rps_read_rpstat with direct read to GEN12_RPSTAT1 in
read_cagf (Ashutosh)
v4: Remove GEN12_CAGF_SHIFT and use REG_FIELD_GET (Rodrigo)
Cc: Don Hiatt <donhiatt@gmail.com>
Cc: Andi Shyti <andi.shyti@intel.com>
Signed-off-by: Don Hiatt <don.hiatt@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_rps.c | 32 +++++++++++++++++++++----
drivers/gpu/drm/i915/gt/intel_rps.h | 2 ++
drivers/gpu/drm/i915/i915_pmu.c | 3 +--
4 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 35c039573294c..f8c4f758ac0b1 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1539,6 +1539,7 @@
#define GEN12_RPSTAT1 _MMIO(0x1381b4)
#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)
+#define GEN12_CAGF_MASK REG_GENMASK(19, 11)
#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
#define GEN11_CSME (31)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 5061b5b3cece7..02f69cbae5162 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2066,12 +2066,34 @@ void intel_rps_sanitize(struct intel_rps *rps)
rps_disable_interrupts(rps);
}
+u32 intel_rps_read_rpstat_fw(struct intel_rps *rps)
+{
+ struct drm_i915_private *i915 = rps_to_i915(rps);
+ i915_reg_t rpstat;
+
+ rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1;
+
+ return intel_uncore_read_fw(rps_to_gt(rps)->uncore, rpstat);
+}
+
+u32 intel_rps_read_rpstat(struct intel_rps *rps)
+{
+ struct drm_i915_private *i915 = rps_to_i915(rps);
+ i915_reg_t rpstat;
+
+ rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1;
+
+ return intel_uncore_read(rps_to_gt(rps)->uncore, rpstat);
+}
+
u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
u32 cagf;
- if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ if (GRAPHICS_VER(i915) >= 12)
+ cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat);
+ else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
cagf = REG_FIELD_GET(RPE_MASK, rpstat);
else if (GRAPHICS_VER(i915) >= 9)
cagf = REG_FIELD_GET(GEN9_CAGF_MASK, rpstat);
@@ -2091,7 +2113,9 @@ static u32 read_cagf(struct intel_rps *rps)
struct intel_uncore *uncore = rps_to_uncore(rps);
u32 freq;
- if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
+ if (GRAPHICS_VER(i915) >= 12) {
+ freq = intel_uncore_read(uncore, GEN12_RPSTAT1);
+ } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
vlv_punit_get(i915);
freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
vlv_punit_put(i915);
@@ -2257,7 +2281,7 @@ static void rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
- rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
+ rpstat = intel_rps_read_rpstat(rps);
rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
@@ -2392,7 +2416,7 @@ static void slpc_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
drm_printf(p, "PM MASK=0x%08x\n", pm_mask);
drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n",
rps->pm_intrmsk_mbz);
- drm_printf(p, "RPSTAT1: 0x%08x\n", intel_uncore_read(uncore, GEN6_RPSTAT1));
+ drm_printf(p, "RPSTAT1: 0x%08x\n", intel_rps_read_rpstat(rps));
drm_printf(p, "RPNSWREQ: %dMHz\n", intel_rps_get_requested_frequency(rps));
drm_printf(p, "Lowest (RPN) frequency: %dMHz\n",
intel_gpu_freq(rps, caps.min_freq));
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h
index 110300dfd4383..9e1cad9ba0e9c 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -48,6 +48,8 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps);
u32 intel_rps_get_rpn_frequency(struct intel_rps *rps);
u32 intel_rps_read_punit_req(struct intel_rps *rps);
u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps);
+u32 intel_rps_read_rpstat(struct intel_rps *rps);
+u32 intel_rps_read_rpstat_fw(struct intel_rps *rps);
void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps);
void intel_rps_raise_unslice(struct intel_rps *rps);
void intel_rps_lower_unslice(struct intel_rps *rps);
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 958b37123bf12..67140a87182f8 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -371,7 +371,6 @@ static void
frequency_sample(struct intel_gt *gt, unsigned int period_ns)
{
struct drm_i915_private *i915 = gt->i915;
- struct intel_uncore *uncore = gt->uncore;
struct i915_pmu *pmu = &i915->pmu;
struct intel_rps *rps = >->rps;
@@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns)
* case we assume the system is running at the intended
* frequency. Fortunately, the read should rarely fail!
*/
- val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1);
+ val = intel_rps_read_rpstat_fw(rps);
if (val)
val = intel_rps_get_cagf(rps, val);
else
--
2.38.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH 2/5] drm/i915: Use GEN12_RPSTAT register for GT freq
@ 2022-10-24 20:24 ` Ashutosh Dixit
0 siblings, 0 replies; 19+ messages in thread
From: Ashutosh Dixit @ 2022-10-24 20:24 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Rodrigo Vivi
From: Don Hiatt <don.hiatt@intel.com>
On GEN12+ use GEN12_RPSTAT register to get actual resolved GT
freq. GEN12_RPSTAT does not require a forcewake and will return 0 freq if
GT is in RC6.
v2:
- Fixed review comments(Ashutosh)
- Added function intel_rps_read_rpstat_fw to read RPSTAT without
forcewake, required especially for GEN6_RPSTAT1 (Ashutosh, Tvrtko)
v3:
- Updated commit title and message for more clarity (Ashutosh)
- Replaced intel_rps_read_rpstat with direct read to GEN12_RPSTAT1 in
read_cagf (Ashutosh)
v4: Remove GEN12_CAGF_SHIFT and use REG_FIELD_GET (Rodrigo)
Cc: Don Hiatt <donhiatt@gmail.com>
Cc: Andi Shyti <andi.shyti@intel.com>
Signed-off-by: Don Hiatt <don.hiatt@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_rps.c | 32 +++++++++++++++++++++----
drivers/gpu/drm/i915/gt/intel_rps.h | 2 ++
drivers/gpu/drm/i915/i915_pmu.c | 3 +--
4 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 35c039573294c..f8c4f758ac0b1 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1539,6 +1539,7 @@
#define GEN12_RPSTAT1 _MMIO(0x1381b4)
#define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)
+#define GEN12_CAGF_MASK REG_GENMASK(19, 11)
#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
#define GEN11_CSME (31)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 5061b5b3cece7..02f69cbae5162 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2066,12 +2066,34 @@ void intel_rps_sanitize(struct intel_rps *rps)
rps_disable_interrupts(rps);
}
+u32 intel_rps_read_rpstat_fw(struct intel_rps *rps)
+{
+ struct drm_i915_private *i915 = rps_to_i915(rps);
+ i915_reg_t rpstat;
+
+ rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1;
+
+ return intel_uncore_read_fw(rps_to_gt(rps)->uncore, rpstat);
+}
+
+u32 intel_rps_read_rpstat(struct intel_rps *rps)
+{
+ struct drm_i915_private *i915 = rps_to_i915(rps);
+ i915_reg_t rpstat;
+
+ rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1;
+
+ return intel_uncore_read(rps_to_gt(rps)->uncore, rpstat);
+}
+
u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
u32 cagf;
- if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ if (GRAPHICS_VER(i915) >= 12)
+ cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat);
+ else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
cagf = REG_FIELD_GET(RPE_MASK, rpstat);
else if (GRAPHICS_VER(i915) >= 9)
cagf = REG_FIELD_GET(GEN9_CAGF_MASK, rpstat);
@@ -2091,7 +2113,9 @@ static u32 read_cagf(struct intel_rps *rps)
struct intel_uncore *uncore = rps_to_uncore(rps);
u32 freq;
- if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
+ if (GRAPHICS_VER(i915) >= 12) {
+ freq = intel_uncore_read(uncore, GEN12_RPSTAT1);
+ } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
vlv_punit_get(i915);
freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
vlv_punit_put(i915);
@@ -2257,7 +2281,7 @@ static void rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
- rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
+ rpstat = intel_rps_read_rpstat(rps);
rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
@@ -2392,7 +2416,7 @@ static void slpc_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
drm_printf(p, "PM MASK=0x%08x\n", pm_mask);
drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n",
rps->pm_intrmsk_mbz);
- drm_printf(p, "RPSTAT1: 0x%08x\n", intel_uncore_read(uncore, GEN6_RPSTAT1));
+ drm_printf(p, "RPSTAT1: 0x%08x\n", intel_rps_read_rpstat(rps));
drm_printf(p, "RPNSWREQ: %dMHz\n", intel_rps_get_requested_frequency(rps));
drm_printf(p, "Lowest (RPN) frequency: %dMHz\n",
intel_gpu_freq(rps, caps.min_freq));
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h
index 110300dfd4383..9e1cad9ba0e9c 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -48,6 +48,8 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps);
u32 intel_rps_get_rpn_frequency(struct intel_rps *rps);
u32 intel_rps_read_punit_req(struct intel_rps *rps);
u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps);
+u32 intel_rps_read_rpstat(struct intel_rps *rps);
+u32 intel_rps_read_rpstat_fw(struct intel_rps *rps);
void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps);
void intel_rps_raise_unslice(struct intel_rps *rps);
void intel_rps_lower_unslice(struct intel_rps *rps);
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 958b37123bf12..67140a87182f8 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -371,7 +371,6 @@ static void
frequency_sample(struct intel_gt *gt, unsigned int period_ns)
{
struct drm_i915_private *i915 = gt->i915;
- struct intel_uncore *uncore = gt->uncore;
struct i915_pmu *pmu = &i915->pmu;
struct intel_rps *rps = >->rps;
@@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns)
* case we assume the system is running at the intended
* frequency. Fortunately, the read should rarely fail!
*/
- val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1);
+ val = intel_rps_read_rpstat_fw(rps);
if (val)
val = intel_rps_get_cagf(rps, val);
else
--
2.38.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 3/5] drm/i915/mtl: Modify CAGF functions for MTL
2022-10-24 20:24 ` [Intel-gfx] " Ashutosh Dixit
@ 2022-10-24 20:24 ` Ashutosh Dixit
-1 siblings, 0 replies; 19+ messages in thread
From: Ashutosh Dixit @ 2022-10-24 20:24 UTC (permalink / raw)
To: intel-gfx; +Cc: Badal Nilawar, dri-devel, Rodrigo Vivi
From: Badal Nilawar <badal.nilawar@intel.com>
Update CAGF functions for MTL to get actual resolved frequency of 3D and
SAMedia.
v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR)
Move MTL branches in cagf functions to top (MattR)
Fix commit message (Andi)
v3: Added comment about registers not needing forcewake for Gen12+ and
returning 0 freq in RC6
v4: Use REG_FIELD_GET and uncore (Rodrigo)
Bspec: 66300
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4 ++++
drivers/gpu/drm/i915/gt/intel_rps.c | 12 ++++++++++--
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index f8c4f758ac0b1..d8dbd0ac3b064 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -21,6 +21,10 @@
*/
#define PERF_REG(offset) _MMIO(offset)
+/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
+#define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60)
+#define MTL_CAGF_MASK REG_GENMASK(8, 0)
+
/* RPM unit config (Gen8+) */
#define RPM_CONFIG0 _MMIO(0xd00)
#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 02f69cbae5162..eb3343a217947 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2091,7 +2091,9 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
struct drm_i915_private *i915 = rps_to_i915(rps);
u32 cagf;
- if (GRAPHICS_VER(i915) >= 12)
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+ cagf = REG_FIELD_GET(MTL_CAGF_MASK, rpstat);
+ else if (GRAPHICS_VER(i915) >= 12)
cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat);
else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
cagf = REG_FIELD_GET(RPE_MASK, rpstat);
@@ -2113,7 +2115,13 @@ static u32 read_cagf(struct intel_rps *rps)
struct intel_uncore *uncore = rps_to_uncore(rps);
u32 freq;
- if (GRAPHICS_VER(i915) >= 12) {
+ /*
+ * For Gen12+ reading freq from HW does not need a forcewake and
+ * registers will return 0 freq when GT is in RC6
+ */
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
+ freq = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1);
+ } else if (GRAPHICS_VER(i915) >= 12) {
freq = intel_uncore_read(uncore, GEN12_RPSTAT1);
} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
vlv_punit_get(i915);
--
2.38.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH 3/5] drm/i915/mtl: Modify CAGF functions for MTL
@ 2022-10-24 20:24 ` Ashutosh Dixit
0 siblings, 0 replies; 19+ messages in thread
From: Ashutosh Dixit @ 2022-10-24 20:24 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Rodrigo Vivi
From: Badal Nilawar <badal.nilawar@intel.com>
Update CAGF functions for MTL to get actual resolved frequency of 3D and
SAMedia.
v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR)
Move MTL branches in cagf functions to top (MattR)
Fix commit message (Andi)
v3: Added comment about registers not needing forcewake for Gen12+ and
returning 0 freq in RC6
v4: Use REG_FIELD_GET and uncore (Rodrigo)
Bspec: 66300
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4 ++++
drivers/gpu/drm/i915/gt/intel_rps.c | 12 ++++++++++--
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index f8c4f758ac0b1..d8dbd0ac3b064 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -21,6 +21,10 @@
*/
#define PERF_REG(offset) _MMIO(offset)
+/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
+#define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60)
+#define MTL_CAGF_MASK REG_GENMASK(8, 0)
+
/* RPM unit config (Gen8+) */
#define RPM_CONFIG0 _MMIO(0xd00)
#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 02f69cbae5162..eb3343a217947 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2091,7 +2091,9 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
struct drm_i915_private *i915 = rps_to_i915(rps);
u32 cagf;
- if (GRAPHICS_VER(i915) >= 12)
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+ cagf = REG_FIELD_GET(MTL_CAGF_MASK, rpstat);
+ else if (GRAPHICS_VER(i915) >= 12)
cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat);
else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
cagf = REG_FIELD_GET(RPE_MASK, rpstat);
@@ -2113,7 +2115,13 @@ static u32 read_cagf(struct intel_rps *rps)
struct intel_uncore *uncore = rps_to_uncore(rps);
u32 freq;
- if (GRAPHICS_VER(i915) >= 12) {
+ /*
+ * For Gen12+ reading freq from HW does not need a forcewake and
+ * registers will return 0 freq when GT is in RC6
+ */
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
+ freq = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1);
+ } else if (GRAPHICS_VER(i915) >= 12) {
freq = intel_uncore_read(uncore, GEN12_RPSTAT1);
} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
vlv_punit_get(i915);
--
2.38.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 4/5] drm/i915/gt: Use RC6 residency types as arguments to residency functions
2022-10-24 20:24 ` [Intel-gfx] " Ashutosh Dixit
@ 2022-10-24 20:24 ` Ashutosh Dixit
-1 siblings, 0 replies; 19+ messages in thread
From: Ashutosh Dixit @ 2022-10-24 20:24 UTC (permalink / raw)
To: intel-gfx; +Cc: Badal Nilawar, dri-devel, Rodrigo Vivi
Previously RC6 residency functions directly accepted RC6 residency register
MMIO offsets (there are four RC6 residency registers). This worked but
required an assumption on the residency register layout so was not future
proof.
Therefore change RC6 residency functions to accept RC6 residency types
instead of register MMIO offsets. The knowledge of register offsets as well
as ID to offset mapping is now maintained solely in intel_rc6 and can be
tailored for different platforms and different register layouts as need
arises.
v2: Address review comments by Jani N
- Change residency functions to accept RC6 residency types instead of
register ID's
- s/intel_rc6_print_rc5_res/intel_rc6_print_residency/
- Remove "const enum" in function arguments
- Naming: intel_rc6_* for enum
- Use INTEL_RC6_RES_MAX and other minor changes
v3: Don't include intel_rc6_types.h in intel_rc6.h (Jani)
Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Suggested-by: Jani Nikula <jani.nikula@linux.intel.com>
Reported-by: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 27 +++------
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 12 ++--
drivers/gpu/drm/i915/gt/intel_rc6.c | 55 +++++++++++--------
drivers/gpu/drm/i915/gt/intel_rc6.h | 11 ++--
drivers/gpu/drm/i915/gt/intel_rc6_types.h | 15 ++++-
drivers/gpu/drm/i915/gt/selftest_rc6.c | 6 +-
drivers/gpu/drm/i915/i915_pmu.c | 6 +-
7 files changed, 72 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 979e602946549..5d6b346831393 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -83,19 +83,6 @@ static int fw_domains_show(struct seq_file *m, void *data)
}
DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(fw_domains);
-static void print_rc6_res(struct seq_file *m,
- const char *title,
- const i915_reg_t reg)
-{
- struct intel_gt *gt = m->private;
- intel_wakeref_t wakeref;
-
- with_intel_runtime_pm(gt->uncore->rpm, wakeref)
- seq_printf(m, "%s %u (%llu us)\n", title,
- intel_uncore_read(gt->uncore, reg),
- intel_rc6_residency_us(>->rc6, reg));
-}
-
static int vlv_drpc(struct seq_file *m)
{
struct intel_gt *gt = m->private;
@@ -115,8 +102,8 @@ static int vlv_drpc(struct seq_file *m)
seq_printf(m, "Media Power Well: %s\n",
(pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
- print_rc6_res(m, "Render RC6 residency since boot:", GEN6_GT_GFX_RC6);
- print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
+ intel_rc6_print_residency(m, "Render RC6 residency since boot:", INTEL_RC6_RES_RC6);
+ intel_rc6_print_residency(m, "Media RC6 residency since boot:", INTEL_RC6_RES_VLV_MEDIA);
return fw_domains_show(m, NULL);
}
@@ -192,11 +179,11 @@ static int gen6_drpc(struct seq_file *m)
}
/* Not exactly sure what this is */
- print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
- GEN6_GT_GFX_RC6_LOCKED);
- print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
- print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
- print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
+ intel_rc6_print_residency(m, "RC6 \"Locked to RPn\" residency since boot:",
+ INTEL_RC6_RES_RC6_LOCKED);
+ intel_rc6_print_residency(m, "RC6 residency since boot:", INTEL_RC6_RES_RC6);
+ intel_rc6_print_residency(m, "RC6+ residency since boot:", INTEL_RC6_RES_RC6p);
+ intel_rc6_print_residency(m, "RC6++ residency since boot:", INTEL_RC6_RES_RC6pp);
if (GRAPHICS_VER(i915) <= 7) {
seq_printf(m, "RC6 voltage: %dmV\n",
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index 9041609523697..19a60000e052c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -93,13 +93,13 @@ sysfs_gt_attribute_r_func(struct device *dev, struct device_attribute *attr,
sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MAX)
#ifdef CONFIG_PM
-static u32 get_residency(struct intel_gt *gt, i915_reg_t reg)
+static u32 get_residency(struct intel_gt *gt, enum intel_rc6_res_type id)
{
intel_wakeref_t wakeref;
u64 res = 0;
with_intel_runtime_pm(gt->uncore->rpm, wakeref)
- res = intel_rc6_residency_us(>->rc6, reg);
+ res = intel_rc6_residency_us(>->rc6, id);
return DIV_ROUND_CLOSEST_ULL(res, 1000);
}
@@ -123,7 +123,7 @@ static ssize_t rc6_enable_show(struct device *dev,
static u32 __rc6_residency_ms_show(struct intel_gt *gt)
{
- return get_residency(gt, GEN6_GT_GFX_RC6);
+ return get_residency(gt, INTEL_RC6_RES_RC6);
}
static ssize_t rc6_residency_ms_show(struct device *dev,
@@ -138,7 +138,7 @@ static ssize_t rc6_residency_ms_show(struct device *dev,
static u32 __rc6p_residency_ms_show(struct intel_gt *gt)
{
- return get_residency(gt, GEN6_GT_GFX_RC6p);
+ return get_residency(gt, INTEL_RC6_RES_RC6p);
}
static ssize_t rc6p_residency_ms_show(struct device *dev,
@@ -153,7 +153,7 @@ static ssize_t rc6p_residency_ms_show(struct device *dev,
static u32 __rc6pp_residency_ms_show(struct intel_gt *gt)
{
- return get_residency(gt, GEN6_GT_GFX_RC6pp);
+ return get_residency(gt, INTEL_RC6_RES_RC6pp);
}
static ssize_t rc6pp_residency_ms_show(struct device *dev,
@@ -168,7 +168,7 @@ static ssize_t rc6pp_residency_ms_show(struct device *dev,
static u32 __media_rc6_residency_ms_show(struct intel_gt *gt)
{
- return get_residency(gt, VLV_GT_MEDIA_RC6);
+ return get_residency(gt, INTEL_RC6_RES_VLV_MEDIA);
}
static ssize_t media_rc6_residency_ms_show(struct device *dev,
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index f8d0523f4c18e..6db4e60d5fba5 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -551,6 +551,14 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
}
+static void rc6_res_reg_init(struct intel_rc6 *rc6)
+{
+ rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED;
+ rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6;
+ rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p;
+ rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp;
+}
+
void intel_rc6_init(struct intel_rc6 *rc6)
{
struct drm_i915_private *i915 = rc6_to_i915(rc6);
@@ -562,6 +570,8 @@ void intel_rc6_init(struct intel_rc6 *rc6)
if (!rc6_supported(rc6))
return;
+ rc6_res_reg_init(rc6);
+
if (IS_CHERRYVIEW(i915))
err = chv_rc6_init(rc6);
else if (IS_VALLEYVIEW(i915))
@@ -736,31 +746,19 @@ static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg)
return lower | (u64)upper << 8;
}
-u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
+u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id)
{
struct drm_i915_private *i915 = rc6_to_i915(rc6);
struct intel_uncore *uncore = rc6_to_uncore(rc6);
u64 time_hw, prev_hw, overflow_hw;
+ i915_reg_t reg = rc6->res_reg[id];
unsigned int fw_domains;
unsigned long flags;
- unsigned int i;
u32 mul, div;
if (!rc6->supported)
return 0;
- /*
- * Store previous hw counter values for counter wrap-around handling.
- *
- * There are only four interesting registers and they live next to each
- * other so we can use the relative address, compared to the smallest
- * one as the index into driver storage.
- */
- i = (i915_mmio_reg_offset(reg) -
- i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);
- if (drm_WARN_ON_ONCE(&i915->drm, i >= ARRAY_SIZE(rc6->cur_residency)))
- return 0;
-
fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
spin_lock_irqsave(&uncore->lock, flags);
@@ -789,11 +787,11 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
/*
* Counter wrap handling.
*
- * But relying on a sufficient frequency of queries otherwise counters
- * can still wrap.
+ * Store previous hw counter values for counter wrap-around handling. But
+ * relying on a sufficient frequency of queries otherwise counters can still wrap.
*/
- prev_hw = rc6->prev_hw_residency[i];
- rc6->prev_hw_residency[i] = time_hw;
+ prev_hw = rc6->prev_hw_residency[id];
+ rc6->prev_hw_residency[id] = time_hw;
/* RC6 delta from last sample. */
if (time_hw >= prev_hw)
@@ -802,8 +800,8 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
time_hw += overflow_hw - prev_hw;
/* Add delta to RC6 extended raw driver copy. */
- time_hw += rc6->cur_residency[i];
- rc6->cur_residency[i] = time_hw;
+ time_hw += rc6->cur_residency[id];
+ rc6->cur_residency[id] = time_hw;
intel_uncore_forcewake_put__locked(uncore, fw_domains);
spin_unlock_irqrestore(&uncore->lock, flags);
@@ -811,9 +809,22 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
return mul_u64_u32_div(time_hw, mul, div);
}
-u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg)
+u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id)
+{
+ return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, id), 1000);
+}
+
+void intel_rc6_print_residency(struct seq_file *m, const char *title,
+ enum intel_rc6_res_type id)
{
- return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, reg), 1000);
+ struct intel_gt *gt = m->private;
+ i915_reg_t reg = gt->rc6.res_reg[id];
+ intel_wakeref_t wakeref;
+
+ with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+ seq_printf(m, "%s %u (%llu us)\n", title,
+ intel_uncore_read(gt->uncore, reg),
+ intel_rc6_residency_us(>->rc6, id));
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.h b/drivers/gpu/drm/i915/gt/intel_rc6.h
index b6fea71afc223..456fa668a2769 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.h
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.h
@@ -6,10 +6,11 @@
#ifndef INTEL_RC6_H
#define INTEL_RC6_H
-#include "i915_reg_defs.h"
+#include <linux/types.h>
-struct intel_engine_cs;
+enum intel_rc6_res_type;
struct intel_rc6;
+struct seq_file;
void intel_rc6_init(struct intel_rc6 *rc6);
void intel_rc6_fini(struct intel_rc6 *rc6);
@@ -21,7 +22,9 @@ void intel_rc6_sanitize(struct intel_rc6 *rc6);
void intel_rc6_enable(struct intel_rc6 *rc6);
void intel_rc6_disable(struct intel_rc6 *rc6);
-u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, i915_reg_t reg);
-u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg);
+u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id);
+u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id);
+void intel_rc6_print_residency(struct seq_file *m, const char *title,
+ enum intel_rc6_res_type id);
#endif /* INTEL_RC6_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6_types.h b/drivers/gpu/drm/i915/gt/intel_rc6_types.h
index e747492b2f46e..fa23c4dce00b4 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_rc6_types.h
@@ -13,9 +13,20 @@
struct drm_i915_gem_object;
+/* RC6 residency types */
+enum intel_rc6_res_type {
+ INTEL_RC6_RES_RC6_LOCKED,
+ INTEL_RC6_RES_RC6,
+ INTEL_RC6_RES_RC6p,
+ INTEL_RC6_RES_RC6pp,
+ INTEL_RC6_RES_MAX,
+ INTEL_RC6_RES_VLV_MEDIA = INTEL_RC6_RES_RC6p,
+};
+
struct intel_rc6 {
- u64 prev_hw_residency[4];
- u64 cur_residency[4];
+ i915_reg_t res_reg[INTEL_RC6_RES_MAX];
+ u64 prev_hw_residency[INTEL_RC6_RES_MAX];
+ u64 cur_residency[INTEL_RC6_RES_MAX];
u32 ctl_enable;
diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
index 8c70b7e120749..2ceeadecc639c 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
@@ -19,11 +19,11 @@ static u64 rc6_residency(struct intel_rc6 *rc6)
/* XXX VLV_GT_MEDIA_RC6? */
- result = intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6);
+ result = intel_rc6_residency_ns(rc6, INTEL_RC6_RES_RC6);
if (HAS_RC6p(rc6_to_i915(rc6)))
- result += intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6p);
+ result += intel_rc6_residency_ns(rc6, INTEL_RC6_RES_RC6p);
if (HAS_RC6pp(rc6_to_i915(rc6)))
- result += intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6pp);
+ result += intel_rc6_residency_ns(rc6, INTEL_RC6_RES_RC6pp);
return result;
}
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 67140a87182f8..52531ab28c5f5 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -148,13 +148,13 @@ static u64 __get_rc6(struct intel_gt *gt)
struct drm_i915_private *i915 = gt->i915;
u64 val;
- val = intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6);
+ val = intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6);
if (HAS_RC6p(i915))
- val += intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6p);
+ val += intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6p);
if (HAS_RC6pp(i915))
- val += intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6pp);
+ val += intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6pp);
return val;
}
--
2.38.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH 4/5] drm/i915/gt: Use RC6 residency types as arguments to residency functions
@ 2022-10-24 20:24 ` Ashutosh Dixit
0 siblings, 0 replies; 19+ messages in thread
From: Ashutosh Dixit @ 2022-10-24 20:24 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Rodrigo Vivi
Previously RC6 residency functions directly accepted RC6 residency register
MMIO offsets (there are four RC6 residency registers). This worked but
required an assumption on the residency register layout so was not future
proof.
Therefore change RC6 residency functions to accept RC6 residency types
instead of register MMIO offsets. The knowledge of register offsets as well
as ID to offset mapping is now maintained solely in intel_rc6 and can be
tailored for different platforms and different register layouts as need
arises.
v2: Address review comments by Jani N
- Change residency functions to accept RC6 residency types instead of
register ID's
- s/intel_rc6_print_rc5_res/intel_rc6_print_residency/
- Remove "const enum" in function arguments
- Naming: intel_rc6_* for enum
- Use INTEL_RC6_RES_MAX and other minor changes
v3: Don't include intel_rc6_types.h in intel_rc6.h (Jani)
Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Suggested-by: Jani Nikula <jani.nikula@linux.intel.com>
Reported-by: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 27 +++------
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 12 ++--
drivers/gpu/drm/i915/gt/intel_rc6.c | 55 +++++++++++--------
drivers/gpu/drm/i915/gt/intel_rc6.h | 11 ++--
drivers/gpu/drm/i915/gt/intel_rc6_types.h | 15 ++++-
drivers/gpu/drm/i915/gt/selftest_rc6.c | 6 +-
drivers/gpu/drm/i915/i915_pmu.c | 6 +-
7 files changed, 72 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 979e602946549..5d6b346831393 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -83,19 +83,6 @@ static int fw_domains_show(struct seq_file *m, void *data)
}
DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(fw_domains);
-static void print_rc6_res(struct seq_file *m,
- const char *title,
- const i915_reg_t reg)
-{
- struct intel_gt *gt = m->private;
- intel_wakeref_t wakeref;
-
- with_intel_runtime_pm(gt->uncore->rpm, wakeref)
- seq_printf(m, "%s %u (%llu us)\n", title,
- intel_uncore_read(gt->uncore, reg),
- intel_rc6_residency_us(>->rc6, reg));
-}
-
static int vlv_drpc(struct seq_file *m)
{
struct intel_gt *gt = m->private;
@@ -115,8 +102,8 @@ static int vlv_drpc(struct seq_file *m)
seq_printf(m, "Media Power Well: %s\n",
(pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
- print_rc6_res(m, "Render RC6 residency since boot:", GEN6_GT_GFX_RC6);
- print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
+ intel_rc6_print_residency(m, "Render RC6 residency since boot:", INTEL_RC6_RES_RC6);
+ intel_rc6_print_residency(m, "Media RC6 residency since boot:", INTEL_RC6_RES_VLV_MEDIA);
return fw_domains_show(m, NULL);
}
@@ -192,11 +179,11 @@ static int gen6_drpc(struct seq_file *m)
}
/* Not exactly sure what this is */
- print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
- GEN6_GT_GFX_RC6_LOCKED);
- print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
- print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
- print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
+ intel_rc6_print_residency(m, "RC6 \"Locked to RPn\" residency since boot:",
+ INTEL_RC6_RES_RC6_LOCKED);
+ intel_rc6_print_residency(m, "RC6 residency since boot:", INTEL_RC6_RES_RC6);
+ intel_rc6_print_residency(m, "RC6+ residency since boot:", INTEL_RC6_RES_RC6p);
+ intel_rc6_print_residency(m, "RC6++ residency since boot:", INTEL_RC6_RES_RC6pp);
if (GRAPHICS_VER(i915) <= 7) {
seq_printf(m, "RC6 voltage: %dmV\n",
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index 9041609523697..19a60000e052c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -93,13 +93,13 @@ sysfs_gt_attribute_r_func(struct device *dev, struct device_attribute *attr,
sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MAX)
#ifdef CONFIG_PM
-static u32 get_residency(struct intel_gt *gt, i915_reg_t reg)
+static u32 get_residency(struct intel_gt *gt, enum intel_rc6_res_type id)
{
intel_wakeref_t wakeref;
u64 res = 0;
with_intel_runtime_pm(gt->uncore->rpm, wakeref)
- res = intel_rc6_residency_us(>->rc6, reg);
+ res = intel_rc6_residency_us(>->rc6, id);
return DIV_ROUND_CLOSEST_ULL(res, 1000);
}
@@ -123,7 +123,7 @@ static ssize_t rc6_enable_show(struct device *dev,
static u32 __rc6_residency_ms_show(struct intel_gt *gt)
{
- return get_residency(gt, GEN6_GT_GFX_RC6);
+ return get_residency(gt, INTEL_RC6_RES_RC6);
}
static ssize_t rc6_residency_ms_show(struct device *dev,
@@ -138,7 +138,7 @@ static ssize_t rc6_residency_ms_show(struct device *dev,
static u32 __rc6p_residency_ms_show(struct intel_gt *gt)
{
- return get_residency(gt, GEN6_GT_GFX_RC6p);
+ return get_residency(gt, INTEL_RC6_RES_RC6p);
}
static ssize_t rc6p_residency_ms_show(struct device *dev,
@@ -153,7 +153,7 @@ static ssize_t rc6p_residency_ms_show(struct device *dev,
static u32 __rc6pp_residency_ms_show(struct intel_gt *gt)
{
- return get_residency(gt, GEN6_GT_GFX_RC6pp);
+ return get_residency(gt, INTEL_RC6_RES_RC6pp);
}
static ssize_t rc6pp_residency_ms_show(struct device *dev,
@@ -168,7 +168,7 @@ static ssize_t rc6pp_residency_ms_show(struct device *dev,
static u32 __media_rc6_residency_ms_show(struct intel_gt *gt)
{
- return get_residency(gt, VLV_GT_MEDIA_RC6);
+ return get_residency(gt, INTEL_RC6_RES_VLV_MEDIA);
}
static ssize_t media_rc6_residency_ms_show(struct device *dev,
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index f8d0523f4c18e..6db4e60d5fba5 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -551,6 +551,14 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
}
+static void rc6_res_reg_init(struct intel_rc6 *rc6)
+{
+ rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED;
+ rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6;
+ rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p;
+ rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp;
+}
+
void intel_rc6_init(struct intel_rc6 *rc6)
{
struct drm_i915_private *i915 = rc6_to_i915(rc6);
@@ -562,6 +570,8 @@ void intel_rc6_init(struct intel_rc6 *rc6)
if (!rc6_supported(rc6))
return;
+ rc6_res_reg_init(rc6);
+
if (IS_CHERRYVIEW(i915))
err = chv_rc6_init(rc6);
else if (IS_VALLEYVIEW(i915))
@@ -736,31 +746,19 @@ static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg)
return lower | (u64)upper << 8;
}
-u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
+u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id)
{
struct drm_i915_private *i915 = rc6_to_i915(rc6);
struct intel_uncore *uncore = rc6_to_uncore(rc6);
u64 time_hw, prev_hw, overflow_hw;
+ i915_reg_t reg = rc6->res_reg[id];
unsigned int fw_domains;
unsigned long flags;
- unsigned int i;
u32 mul, div;
if (!rc6->supported)
return 0;
- /*
- * Store previous hw counter values for counter wrap-around handling.
- *
- * There are only four interesting registers and they live next to each
- * other so we can use the relative address, compared to the smallest
- * one as the index into driver storage.
- */
- i = (i915_mmio_reg_offset(reg) -
- i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);
- if (drm_WARN_ON_ONCE(&i915->drm, i >= ARRAY_SIZE(rc6->cur_residency)))
- return 0;
-
fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
spin_lock_irqsave(&uncore->lock, flags);
@@ -789,11 +787,11 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
/*
* Counter wrap handling.
*
- * But relying on a sufficient frequency of queries otherwise counters
- * can still wrap.
+ * Store previous hw counter values for counter wrap-around handling. But
+ * relying on a sufficient frequency of queries otherwise counters can still wrap.
*/
- prev_hw = rc6->prev_hw_residency[i];
- rc6->prev_hw_residency[i] = time_hw;
+ prev_hw = rc6->prev_hw_residency[id];
+ rc6->prev_hw_residency[id] = time_hw;
/* RC6 delta from last sample. */
if (time_hw >= prev_hw)
@@ -802,8 +800,8 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
time_hw += overflow_hw - prev_hw;
/* Add delta to RC6 extended raw driver copy. */
- time_hw += rc6->cur_residency[i];
- rc6->cur_residency[i] = time_hw;
+ time_hw += rc6->cur_residency[id];
+ rc6->cur_residency[id] = time_hw;
intel_uncore_forcewake_put__locked(uncore, fw_domains);
spin_unlock_irqrestore(&uncore->lock, flags);
@@ -811,9 +809,22 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
return mul_u64_u32_div(time_hw, mul, div);
}
-u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg)
+u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id)
+{
+ return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, id), 1000);
+}
+
+void intel_rc6_print_residency(struct seq_file *m, const char *title,
+ enum intel_rc6_res_type id)
{
- return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, reg), 1000);
+ struct intel_gt *gt = m->private;
+ i915_reg_t reg = gt->rc6.res_reg[id];
+ intel_wakeref_t wakeref;
+
+ with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+ seq_printf(m, "%s %u (%llu us)\n", title,
+ intel_uncore_read(gt->uncore, reg),
+ intel_rc6_residency_us(>->rc6, id));
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.h b/drivers/gpu/drm/i915/gt/intel_rc6.h
index b6fea71afc223..456fa668a2769 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.h
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.h
@@ -6,10 +6,11 @@
#ifndef INTEL_RC6_H
#define INTEL_RC6_H
-#include "i915_reg_defs.h"
+#include <linux/types.h>
-struct intel_engine_cs;
+enum intel_rc6_res_type;
struct intel_rc6;
+struct seq_file;
void intel_rc6_init(struct intel_rc6 *rc6);
void intel_rc6_fini(struct intel_rc6 *rc6);
@@ -21,7 +22,9 @@ void intel_rc6_sanitize(struct intel_rc6 *rc6);
void intel_rc6_enable(struct intel_rc6 *rc6);
void intel_rc6_disable(struct intel_rc6 *rc6);
-u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, i915_reg_t reg);
-u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg);
+u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id);
+u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id);
+void intel_rc6_print_residency(struct seq_file *m, const char *title,
+ enum intel_rc6_res_type id);
#endif /* INTEL_RC6_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6_types.h b/drivers/gpu/drm/i915/gt/intel_rc6_types.h
index e747492b2f46e..fa23c4dce00b4 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_rc6_types.h
@@ -13,9 +13,20 @@
struct drm_i915_gem_object;
+/* RC6 residency types */
+enum intel_rc6_res_type {
+ INTEL_RC6_RES_RC6_LOCKED,
+ INTEL_RC6_RES_RC6,
+ INTEL_RC6_RES_RC6p,
+ INTEL_RC6_RES_RC6pp,
+ INTEL_RC6_RES_MAX,
+ INTEL_RC6_RES_VLV_MEDIA = INTEL_RC6_RES_RC6p,
+};
+
struct intel_rc6 {
- u64 prev_hw_residency[4];
- u64 cur_residency[4];
+ i915_reg_t res_reg[INTEL_RC6_RES_MAX];
+ u64 prev_hw_residency[INTEL_RC6_RES_MAX];
+ u64 cur_residency[INTEL_RC6_RES_MAX];
u32 ctl_enable;
diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
index 8c70b7e120749..2ceeadecc639c 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
@@ -19,11 +19,11 @@ static u64 rc6_residency(struct intel_rc6 *rc6)
/* XXX VLV_GT_MEDIA_RC6? */
- result = intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6);
+ result = intel_rc6_residency_ns(rc6, INTEL_RC6_RES_RC6);
if (HAS_RC6p(rc6_to_i915(rc6)))
- result += intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6p);
+ result += intel_rc6_residency_ns(rc6, INTEL_RC6_RES_RC6p);
if (HAS_RC6pp(rc6_to_i915(rc6)))
- result += intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6pp);
+ result += intel_rc6_residency_ns(rc6, INTEL_RC6_RES_RC6pp);
return result;
}
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 67140a87182f8..52531ab28c5f5 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -148,13 +148,13 @@ static u64 __get_rc6(struct intel_gt *gt)
struct drm_i915_private *i915 = gt->i915;
u64 val;
- val = intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6);
+ val = intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6);
if (HAS_RC6p(i915))
- val += intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6p);
+ val += intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6p);
if (HAS_RC6pp(i915))
- val += intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6pp);
+ val += intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6pp);
return val;
}
--
2.38.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 5/5] drm/i915/mtl: C6 residency and C state type for MTL SAMedia
2022-10-24 20:24 ` [Intel-gfx] " Ashutosh Dixit
@ 2022-10-24 20:24 ` Ashutosh Dixit
-1 siblings, 0 replies; 19+ messages in thread
From: Ashutosh Dixit @ 2022-10-24 20:24 UTC (permalink / raw)
To: intel-gfx; +Cc: Badal Nilawar, dri-devel, Rodrigo Vivi
From: Badal Nilawar <badal.nilawar@intel.com>
Add support for C6 residency and C state type for MTL SAMedia. Also add
mtl_drpc.
v2: Fixed review comments (Ashutosh)
v3: Sort registers and fix whitespace errors in intel_gt_regs.h (Matt R)
Remove MTL_CC_SHIFT (Ashutosh)
Adapt to RC6 residency register code refactor (Jani N)
v4: Move MTL branch to top in drpc_show
v5: Use FORCEWAKE_MT identical to gen6_drpc (Ashutosh)
v6: Add MISSING_CASE for gt_core_status switch statement (Rodrigo)
Change state name for MTL_CC0 to C0 (from "on") (Rodrigo)
v7: Change state name for MTL_CC0 to RC0 (Rodrigo)
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 59 ++++++++++++++++++-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 ++
drivers/gpu/drm/i915/gt/intel_rc6.c | 17 ++++--
3 files changed, 76 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 5d6b346831393..83df4cd5e06cb 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -256,6 +256,61 @@ static int ilk_drpc(struct seq_file *m)
return 0;
}
+static int mtl_drpc(struct seq_file *m)
+{
+ struct intel_gt *gt = m->private;
+ struct intel_uncore *uncore = gt->uncore;
+ u32 gt_core_status, rcctl1, mt_fwake_req;
+ u32 mtl_powergate_enable = 0, mtl_powergate_status = 0;
+
+ mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
+ gt_core_status = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1);
+
+ rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
+ mtl_powergate_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE);
+ mtl_powergate_status = intel_uncore_read(uncore,
+ GEN9_PWRGT_DOMAIN_STATUS);
+
+ seq_printf(m, "RC6 Enabled: %s\n",
+ str_yes_no(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
+ if (gt->type == GT_MEDIA) {
+ seq_printf(m, "Media Well Gating Enabled: %s\n",
+ str_yes_no(mtl_powergate_enable & GEN9_MEDIA_PG_ENABLE));
+ } else {
+ seq_printf(m, "Render Well Gating Enabled: %s\n",
+ str_yes_no(mtl_powergate_enable & GEN9_RENDER_PG_ENABLE));
+ }
+
+ seq_puts(m, "Current RC state: ");
+ switch (REG_FIELD_GET(MTL_CC_MASK, gt_core_status)) {
+ case MTL_CC0:
+ seq_puts(m, "RC0\n");
+ break;
+ case MTL_CC6:
+ seq_puts(m, "RC6\n");
+ break;
+ default:
+ MISSING_CASE(REG_FIELD_GET(MTL_CC_MASK, gt_core_status));
+ seq_puts(m, "Unknown\n");
+ break;
+ }
+
+ seq_printf(m, "Multi-threaded Forcewake Request: 0x%x\n", mt_fwake_req);
+ if (gt->type == GT_MEDIA)
+ seq_printf(m, "Media Power Well: %s\n",
+ (mtl_powergate_status &
+ GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
+ else
+ seq_printf(m, "Render Power Well: %s\n",
+ (mtl_powergate_status &
+ GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
+
+ /* Works for both render and media gt's */
+ intel_rc6_print_residency(m, "RC6 residency since boot:", INTEL_RC6_RES_RC6);
+
+ return fw_domains_show(m, NULL);
+}
+
static int drpc_show(struct seq_file *m, void *unused)
{
struct intel_gt *gt = m->private;
@@ -264,7 +319,9 @@ static int drpc_show(struct seq_file *m, void *unused)
int err = -ENODEV;
with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
- if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+ err = mtl_drpc(m);
+ else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
err = vlv_drpc(m);
else if (GRAPHICS_VER(i915) >= 6)
err = gen6_drpc(m);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index d8dbd0ac3b064..a0ddaf243593c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -24,6 +24,9 @@
/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
#define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60)
#define MTL_CAGF_MASK REG_GENMASK(8, 0)
+#define MTL_CC0 0x0
+#define MTL_CC6 0x3
+#define MTL_CC_MASK REG_GENMASK(12, 9)
/* RPM unit config (Gen8+) */
#define RPM_CONFIG0 _MMIO(0xd00)
@@ -1512,6 +1515,8 @@
#define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
#define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
+#define MTL_MEDIA_MC6 _MMIO(0x138048)
+
#define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 6db4e60d5fba5..2ee4051e4d961 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -553,10 +553,19 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
static void rc6_res_reg_init(struct intel_rc6 *rc6)
{
- rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED;
- rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6;
- rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p;
- rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp;
+ memset(rc6->res_reg, INVALID_MMIO_REG.reg, sizeof(rc6->res_reg));
+
+ switch (rc6_to_gt(rc6)->type) {
+ case GT_MEDIA:
+ rc6->res_reg[INTEL_RC6_RES_RC6] = MTL_MEDIA_MC6;
+ break;
+ default:
+ rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED;
+ rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6;
+ rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p;
+ rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp;
+ break;
+ }
}
void intel_rc6_init(struct intel_rc6 *rc6)
--
2.38.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH 5/5] drm/i915/mtl: C6 residency and C state type for MTL SAMedia
@ 2022-10-24 20:24 ` Ashutosh Dixit
0 siblings, 0 replies; 19+ messages in thread
From: Ashutosh Dixit @ 2022-10-24 20:24 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Rodrigo Vivi
From: Badal Nilawar <badal.nilawar@intel.com>
Add support for C6 residency and C state type for MTL SAMedia. Also add
mtl_drpc.
v2: Fixed review comments (Ashutosh)
v3: Sort registers and fix whitespace errors in intel_gt_regs.h (Matt R)
Remove MTL_CC_SHIFT (Ashutosh)
Adapt to RC6 residency register code refactor (Jani N)
v4: Move MTL branch to top in drpc_show
v5: Use FORCEWAKE_MT identical to gen6_drpc (Ashutosh)
v6: Add MISSING_CASE for gt_core_status switch statement (Rodrigo)
Change state name for MTL_CC0 to C0 (from "on") (Rodrigo)
v7: Change state name for MTL_CC0 to RC0 (Rodrigo)
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 59 ++++++++++++++++++-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 ++
drivers/gpu/drm/i915/gt/intel_rc6.c | 17 ++++--
3 files changed, 76 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 5d6b346831393..83df4cd5e06cb 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -256,6 +256,61 @@ static int ilk_drpc(struct seq_file *m)
return 0;
}
+static int mtl_drpc(struct seq_file *m)
+{
+ struct intel_gt *gt = m->private;
+ struct intel_uncore *uncore = gt->uncore;
+ u32 gt_core_status, rcctl1, mt_fwake_req;
+ u32 mtl_powergate_enable = 0, mtl_powergate_status = 0;
+
+ mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
+ gt_core_status = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1);
+
+ rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
+ mtl_powergate_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE);
+ mtl_powergate_status = intel_uncore_read(uncore,
+ GEN9_PWRGT_DOMAIN_STATUS);
+
+ seq_printf(m, "RC6 Enabled: %s\n",
+ str_yes_no(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
+ if (gt->type == GT_MEDIA) {
+ seq_printf(m, "Media Well Gating Enabled: %s\n",
+ str_yes_no(mtl_powergate_enable & GEN9_MEDIA_PG_ENABLE));
+ } else {
+ seq_printf(m, "Render Well Gating Enabled: %s\n",
+ str_yes_no(mtl_powergate_enable & GEN9_RENDER_PG_ENABLE));
+ }
+
+ seq_puts(m, "Current RC state: ");
+ switch (REG_FIELD_GET(MTL_CC_MASK, gt_core_status)) {
+ case MTL_CC0:
+ seq_puts(m, "RC0\n");
+ break;
+ case MTL_CC6:
+ seq_puts(m, "RC6\n");
+ break;
+ default:
+ MISSING_CASE(REG_FIELD_GET(MTL_CC_MASK, gt_core_status));
+ seq_puts(m, "Unknown\n");
+ break;
+ }
+
+ seq_printf(m, "Multi-threaded Forcewake Request: 0x%x\n", mt_fwake_req);
+ if (gt->type == GT_MEDIA)
+ seq_printf(m, "Media Power Well: %s\n",
+ (mtl_powergate_status &
+ GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
+ else
+ seq_printf(m, "Render Power Well: %s\n",
+ (mtl_powergate_status &
+ GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
+
+ /* Works for both render and media gt's */
+ intel_rc6_print_residency(m, "RC6 residency since boot:", INTEL_RC6_RES_RC6);
+
+ return fw_domains_show(m, NULL);
+}
+
static int drpc_show(struct seq_file *m, void *unused)
{
struct intel_gt *gt = m->private;
@@ -264,7 +319,9 @@ static int drpc_show(struct seq_file *m, void *unused)
int err = -ENODEV;
with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
- if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+ err = mtl_drpc(m);
+ else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
err = vlv_drpc(m);
else if (GRAPHICS_VER(i915) >= 6)
err = gen6_drpc(m);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index d8dbd0ac3b064..a0ddaf243593c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -24,6 +24,9 @@
/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
#define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60)
#define MTL_CAGF_MASK REG_GENMASK(8, 0)
+#define MTL_CC0 0x0
+#define MTL_CC6 0x3
+#define MTL_CC_MASK REG_GENMASK(12, 9)
/* RPM unit config (Gen8+) */
#define RPM_CONFIG0 _MMIO(0xd00)
@@ -1512,6 +1515,8 @@
#define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
#define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
+#define MTL_MEDIA_MC6 _MMIO(0x138048)
+
#define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 6db4e60d5fba5..2ee4051e4d961 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -553,10 +553,19 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
static void rc6_res_reg_init(struct intel_rc6 *rc6)
{
- rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED;
- rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6;
- rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p;
- rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp;
+ memset(rc6->res_reg, INVALID_MMIO_REG.reg, sizeof(rc6->res_reg));
+
+ switch (rc6_to_gt(rc6)->type) {
+ case GT_MEDIA:
+ rc6->res_reg[INTEL_RC6_RES_RC6] = MTL_MEDIA_MC6;
+ break;
+ default:
+ rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED;
+ rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6;
+ rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p;
+ rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp;
+ break;
+ }
}
void intel_rc6_init(struct intel_rc6 *rc6)
--
2.38.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: CAGF and RC6 changes for MTL (rev11)
2022-10-24 20:24 ` [Intel-gfx] " Ashutosh Dixit
` (5 preceding siblings ...)
(?)
@ 2022-10-25 1:03 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2022-10-25 1:03 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev11)
URL : https://patchwork.freedesktop.org/series/108156/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: CAGF and RC6 changes for MTL (rev11)
2022-10-24 20:24 ` [Intel-gfx] " Ashutosh Dixit
` (6 preceding siblings ...)
(?)
@ 2022-10-25 1:25 ` Patchwork
2022-10-25 17:25 ` Dixit, Ashutosh
-1 siblings, 1 reply; 19+ messages in thread
From: Patchwork @ 2022-10-25 1:25 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8780 bytes --]
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev11)
URL : https://patchwork.freedesktop.org/series/108156/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12288 -> Patchwork_108156v11
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_108156v11 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_108156v11, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/index.html
Participating hosts (41 -> 40)
------------------------------
Additional (1): bat-atsm-1
Missing (2): fi-ctg-p8600 fi-icl-u2
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_108156v11:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_parallel@engines@contexts:
- fi-bsw-nick: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-bsw-nick/igt@gem_exec_parallel@engines@contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-bsw-nick/igt@gem_exec_parallel@engines@contexts.html
* igt@i915_selftest@live@hugepages:
- fi-cfl-8109u: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-cfl-8109u/igt@i915_selftest@live@hugepages.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-cfl-8109u/igt@i915_selftest@live@hugepages.html
- fi-skl-guc: [PASS][5] -> [DMESG-FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-skl-guc/igt@i915_selftest@live@hugepages.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-skl-guc/igt@i915_selftest@live@hugepages.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: NOTRUN -> [INCOMPLETE][7]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@hugepages:
- {fi-tgl-dsi}: NOTRUN -> [DMESG-FAIL][8]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-tgl-dsi/igt@i915_selftest@live@hugepages.html
- {bat-rpls-2}: [PASS][9] -> [DMESG-FAIL][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/bat-rpls-2/igt@i915_selftest@live@hugepages.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/bat-rpls-2/igt@i915_selftest@live@hugepages.html
Known issues
------------
Here are the changes found in Patchwork_108156v11 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gt_lrc:
- fi-rkl-guc: [PASS][11] -> [INCOMPLETE][12] ([i915#4983])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-hsw-4770/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@runner@aborted:
- fi-cfl-8109u: NOTRUN -> [FAIL][14] ([i915#4312])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-cfl-8109u/igt@runner@aborted.html
- fi-skl-guc: NOTRUN -> [FAIL][15] ([i915#4312])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-skl-guc/igt@runner@aborted.html
- fi-bsw-nick: NOTRUN -> [FAIL][16] ([i915#4312])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-bsw-nick/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_huc_copy@huc-copy:
- {bat-dg2-8}: [FAIL][17] ([i915#7029]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/bat-dg2-8/igt@gem_huc_copy@huc-copy.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/bat-dg2-8/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_rpm@basic-rte:
- {bat-rplp-1}: [DMESG-WARN][19] -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/bat-rplp-1/igt@i915_pm_rpm@basic-rte.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/bat-rplp-1/igt@i915_pm_rpm@basic-rte.html
* igt@i915_selftest@live@gt_lrc:
- {fi-tgl-dsi}: [INCOMPLETE][21] ([i915#6856] / [i915#7125]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-tgl-dsi/igt@i915_selftest@live@gt_lrc.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-tgl-dsi/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [INCOMPLETE][23] ([i915#4785]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@hugepages:
- fi-rkl-11600: [DMESG-FAIL][25] -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-rkl-11600/igt@i915_selftest@live@hugepages.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-rkl-11600/igt@i915_selftest@live@hugepages.html
- {fi-ehl-2}: [DMESG-FAIL][27] -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-ehl-2/igt@i915_selftest@live@hugepages.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-ehl-2/igt@i915_selftest@live@hugepages.html
- {bat-adlm-1}: [DMESG-FAIL][29] -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/bat-adlm-1/igt@i915_selftest@live@hugepages.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/bat-adlm-1/igt@i915_selftest@live@hugepages.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5537]: https://gitlab.freedesktop.org/drm/intel/issues/5537
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6856]: https://gitlab.freedesktop.org/drm/intel/issues/6856
[i915#7029]: https://gitlab.freedesktop.org/drm/intel/issues/7029
[i915#7030]: https://gitlab.freedesktop.org/drm/intel/issues/7030
[i915#7125]: https://gitlab.freedesktop.org/drm/intel/issues/7125
Build changes
-------------
* Linux: CI_DRM_12288 -> Patchwork_108156v11
CI-20190529: 20190529
CI_DRM_12288: 61a92db3f6785121281a51f95960a3282d47117d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7025: f8b8e0713f87460a2c050ec8fe18fa487f98e228 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108156v11: 61a92db3f6785121281a51f95960a3282d47117d @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
4bcf0b00c0e3 drm/i915/mtl: C6 residency and C state type for MTL SAMedia
71ca40ed31ec drm/i915/gt: Use RC6 residency types as arguments to residency functions
a40fb583e653 drm/i915/mtl: Modify CAGF functions for MTL
2015f26e0a91 drm/i915: Use GEN12_RPSTAT register for GT freq
7af6ffffca3d drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/index.html
[-- Attachment #2: Type: text/html, Size: 9198 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: CAGF and RC6 changes for MTL (rev11)
2022-10-25 1:25 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2022-10-25 17:25 ` Dixit, Ashutosh
2022-10-27 5:41 ` Vudum, Lakshminarayana
0 siblings, 1 reply; 19+ messages in thread
From: Dixit, Ashutosh @ 2022-10-25 17:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Lakshminarayana Vudum
On Mon, 24 Oct 2022 18:25:06 -0700, Patchwork wrote:
>
Hi Lakshmi,
The below failures are unrelated to this series.
Thanks.
--
Ashutosh
> Patch Details
>
> Series: i915: CAGF and RC6 changes for MTL (rev11)
> URL: https://patchwork.freedesktop.org/series/108156/
> State: failure
> Details: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/index.html
>
> CI Bug Log - changes from CI_DRM_12288 -> Patchwork_108156v11
>
> Summary
>
> FAILURE
>
> Serious unknown changes coming with Patchwork_108156v11 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_108156v11, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/index.html
>
> Participating hosts (41 -> 40)
>
> Additional (1): bat-atsm-1
> Missing (2): fi-ctg-p8600 fi-icl-u2
>
> Possible new issues
>
> Here are the unknown changes that may have been introduced in Patchwork_108156v11:
>
> IGT changes
>
> Possible regressions
>
> • igt@gem_exec_parallel@engines@contexts:
>
> □ fi-bsw-nick: PASS -> INCOMPLETE
> • igt@i915_selftest@live@hugepages:
>
> □ fi-cfl-8109u: PASS -> DMESG-FAIL
>
> □ fi-skl-guc: PASS -> DMESG-FAIL
>
> • igt@i915_suspend@basic-s3-without-i915:
>
> □ fi-rkl-11600: NOTRUN -> INCOMPLETE
>
> Suppressed
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: CAGF and RC6 changes for MTL (rev11)
2022-10-24 20:24 ` [Intel-gfx] " Ashutosh Dixit
` (7 preceding siblings ...)
(?)
@ 2022-10-26 22:34 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2022-10-26 22:34 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 10281 bytes --]
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev11)
URL : https://patchwork.freedesktop.org/series/108156/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12288 -> Patchwork_108156v11
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_108156v11 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_108156v11, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/index.html
Participating hosts (41 -> 41)
------------------------------
Additional (2): fi-kbl-soraka bat-atsm-1
Missing (2): fi-ctg-p8600 fi-icl-u2
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_108156v11:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@gtt:
- fi-kbl-soraka: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@i915_selftest@live@gtt.html
Known issues
------------
Here are the changes found in Patchwork_108156v11 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_gttfill@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271]) +9 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@gem_exec_gttfill@basic.html
* igt@gem_exec_parallel@engines@contexts:
- fi-bsw-nick: [PASS][3] -> [INCOMPLETE][4] ([i915#7311])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-bsw-nick/igt@gem_exec_parallel@engines@contexts.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-bsw-nick/igt@gem_exec_parallel@engines@contexts.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][7] ([i915#5334])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_lrc:
- fi-rkl-guc: [PASS][8] -> [INCOMPLETE][9] ([i915#4983])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][10] ([i915#1886])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hugepages:
- fi-cfl-8109u: [PASS][11] -> [DMESG-FAIL][12] ([i915#7311])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-cfl-8109u/igt@i915_selftest@live@hugepages.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-cfl-8109u/igt@i915_selftest@live@hugepages.html
- fi-skl-guc: [PASS][13] -> [DMESG-FAIL][14] ([i915#7311])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-skl-guc/igt@i915_selftest@live@hugepages.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-skl-guc/igt@i915_selftest@live@hugepages.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: NOTRUN -> [INCOMPLETE][15] ([i915#4817])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-hsw-4770/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +7 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@runner@aborted:
- fi-cfl-8109u: NOTRUN -> [FAIL][18] ([i915#4312])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-cfl-8109u/igt@runner@aborted.html
- fi-skl-guc: NOTRUN -> [FAIL][19] ([i915#4312])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-skl-guc/igt@runner@aborted.html
- fi-bsw-nick: NOTRUN -> [FAIL][20] ([i915#4312])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-bsw-nick/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_huc_copy@huc-copy:
- {bat-dg2-8}: [FAIL][21] ([i915#7029]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/bat-dg2-8/igt@gem_huc_copy@huc-copy.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/bat-dg2-8/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_rpm@basic-rte:
- {bat-rplp-1}: [DMESG-WARN][23] ([i915#7077]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/bat-rplp-1/igt@i915_pm_rpm@basic-rte.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/bat-rplp-1/igt@i915_pm_rpm@basic-rte.html
* igt@i915_selftest@live@gt_lrc:
- {fi-tgl-dsi}: [INCOMPLETE][25] ([i915#6856] / [i915#7125]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-tgl-dsi/igt@i915_selftest@live@gt_lrc.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-tgl-dsi/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [INCOMPLETE][27] ([i915#4785]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@hugepages:
- fi-rkl-11600: [DMESG-FAIL][29] ([i915#7311]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-rkl-11600/igt@i915_selftest@live@hugepages.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-rkl-11600/igt@i915_selftest@live@hugepages.html
- {fi-ehl-2}: [DMESG-FAIL][31] ([i915#7311]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-ehl-2/igt@i915_selftest@live@hugepages.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-ehl-2/igt@i915_selftest@live@hugepages.html
- {bat-adlm-1}: [DMESG-FAIL][33] ([i915#7311]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/bat-adlm-1/igt@i915_selftest@live@hugepages.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/bat-adlm-1/igt@i915_selftest@live@hugepages.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5537]: https://gitlab.freedesktop.org/drm/intel/issues/5537
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6856]: https://gitlab.freedesktop.org/drm/intel/issues/6856
[i915#7029]: https://gitlab.freedesktop.org/drm/intel/issues/7029
[i915#7030]: https://gitlab.freedesktop.org/drm/intel/issues/7030
[i915#7077]: https://gitlab.freedesktop.org/drm/intel/issues/7077
[i915#7125]: https://gitlab.freedesktop.org/drm/intel/issues/7125
[i915#7311]: https://gitlab.freedesktop.org/drm/intel/issues/7311
Build changes
-------------
* Linux: CI_DRM_12288 -> Patchwork_108156v11
CI-20190529: 20190529
CI_DRM_12288: 61a92db3f6785121281a51f95960a3282d47117d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7025: f8b8e0713f87460a2c050ec8fe18fa487f98e228 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108156v11: 61a92db3f6785121281a51f95960a3282d47117d @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
4bcf0b00c0e3 drm/i915/mtl: C6 residency and C state type for MTL SAMedia
71ca40ed31ec drm/i915/gt: Use RC6 residency types as arguments to residency functions
a40fb583e653 drm/i915/mtl: Modify CAGF functions for MTL
2015f26e0a91 drm/i915: Use GEN12_RPSTAT register for GT freq
7af6ffffca3d drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/index.html
[-- Attachment #2: Type: text/html, Size: 11518 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for i915: CAGF and RC6 changes for MTL (rev11)
2022-10-24 20:24 ` [Intel-gfx] " Ashutosh Dixit
` (8 preceding siblings ...)
(?)
@ 2022-10-27 4:23 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2022-10-27 4:23 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 9871 bytes --]
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev11)
URL : https://patchwork.freedesktop.org/series/108156/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12288 -> Patchwork_108156v11
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/index.html
Participating hosts (41 -> 41)
------------------------------
Additional (2): fi-kbl-soraka bat-atsm-1
Missing (2): fi-ctg-p8600 fi-icl-u2
Known issues
------------
Here are the changes found in Patchwork_108156v11 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_gttfill@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +9 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@gem_exec_gttfill@basic.html
* igt@gem_exec_parallel@engines@contexts:
- fi-bsw-nick: [PASS][2] -> [INCOMPLETE][3] ([i915#7311])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-bsw-nick/igt@gem_exec_parallel@engines@contexts.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-bsw-nick/igt@gem_exec_parallel@engines@contexts.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][6] ([i915#5334])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_lrc:
- fi-rkl-guc: [PASS][7] -> [INCOMPLETE][8] ([i915#4983])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][9] ([i915#1886])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@gtt:
- fi-kbl-soraka: NOTRUN -> [INCOMPLETE][10] ([i915#7319])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@i915_selftest@live@gtt.html
* igt@i915_selftest@live@hugepages:
- fi-cfl-8109u: [PASS][11] -> [DMESG-FAIL][12] ([i915#7311])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-cfl-8109u/igt@i915_selftest@live@hugepages.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-cfl-8109u/igt@i915_selftest@live@hugepages.html
- fi-skl-guc: [PASS][13] -> [DMESG-FAIL][14] ([i915#7311])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-skl-guc/igt@i915_selftest@live@hugepages.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-skl-guc/igt@i915_selftest@live@hugepages.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: NOTRUN -> [INCOMPLETE][15] ([i915#4817])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-hsw-4770/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +7 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-kbl-soraka/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@runner@aborted:
- fi-cfl-8109u: NOTRUN -> [FAIL][18] ([i915#4312])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-cfl-8109u/igt@runner@aborted.html
- fi-skl-guc: NOTRUN -> [FAIL][19] ([i915#4312])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-skl-guc/igt@runner@aborted.html
- fi-bsw-nick: NOTRUN -> [FAIL][20] ([i915#4312])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-bsw-nick/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_huc_copy@huc-copy:
- {bat-dg2-8}: [FAIL][21] ([i915#7029]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/bat-dg2-8/igt@gem_huc_copy@huc-copy.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/bat-dg2-8/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_rpm@basic-rte:
- {bat-rplp-1}: [DMESG-WARN][23] ([i915#7077]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/bat-rplp-1/igt@i915_pm_rpm@basic-rte.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/bat-rplp-1/igt@i915_pm_rpm@basic-rte.html
* igt@i915_selftest@live@gt_lrc:
- {fi-tgl-dsi}: [INCOMPLETE][25] ([i915#6856] / [i915#7125]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-tgl-dsi/igt@i915_selftest@live@gt_lrc.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-tgl-dsi/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [INCOMPLETE][27] ([i915#4785]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@hugepages:
- fi-rkl-11600: [DMESG-FAIL][29] ([i915#7311]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-rkl-11600/igt@i915_selftest@live@hugepages.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-rkl-11600/igt@i915_selftest@live@hugepages.html
- {fi-ehl-2}: [DMESG-FAIL][31] ([i915#7311]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/fi-ehl-2/igt@i915_selftest@live@hugepages.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/fi-ehl-2/igt@i915_selftest@live@hugepages.html
- {bat-adlm-1}: [DMESG-FAIL][33] ([i915#7311]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/bat-adlm-1/igt@i915_selftest@live@hugepages.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/bat-adlm-1/igt@i915_selftest@live@hugepages.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5537]: https://gitlab.freedesktop.org/drm/intel/issues/5537
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6856]: https://gitlab.freedesktop.org/drm/intel/issues/6856
[i915#7029]: https://gitlab.freedesktop.org/drm/intel/issues/7029
[i915#7030]: https://gitlab.freedesktop.org/drm/intel/issues/7030
[i915#7077]: https://gitlab.freedesktop.org/drm/intel/issues/7077
[i915#7125]: https://gitlab.freedesktop.org/drm/intel/issues/7125
[i915#7311]: https://gitlab.freedesktop.org/drm/intel/issues/7311
[i915#7319]: https://gitlab.freedesktop.org/drm/intel/issues/7319
Build changes
-------------
* Linux: CI_DRM_12288 -> Patchwork_108156v11
CI-20190529: 20190529
CI_DRM_12288: 61a92db3f6785121281a51f95960a3282d47117d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7025: f8b8e0713f87460a2c050ec8fe18fa487f98e228 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108156v11: 61a92db3f6785121281a51f95960a3282d47117d @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
4bcf0b00c0e3 drm/i915/mtl: C6 residency and C state type for MTL SAMedia
71ca40ed31ec drm/i915/gt: Use RC6 residency types as arguments to residency functions
a40fb583e653 drm/i915/mtl: Modify CAGF functions for MTL
2015f26e0a91 drm/i915: Use GEN12_RPSTAT register for GT freq
7af6ffffca3d drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/index.html
[-- Attachment #2: Type: text/html, Size: 11096 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: CAGF and RC6 changes for MTL (rev11)
2022-10-25 17:25 ` Dixit, Ashutosh
@ 2022-10-27 5:41 ` Vudum, Lakshminarayana
0 siblings, 0 replies; 19+ messages in thread
From: Vudum, Lakshminarayana @ 2022-10-27 5:41 UTC (permalink / raw)
To: Dixit, Ashutosh, intel-gfx
Re-reported.
-----Original Message-----
From: Dixit, Ashutosh <ashutosh.dixit@intel.com>
Sent: Tuesday, October 25, 2022 10:26 AM
To: intel-gfx@lists.freedesktop.org
Cc: Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>
Subject: Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: CAGF and RC6 changes for MTL (rev11)
On Mon, 24 Oct 2022 18:25:06 -0700, Patchwork wrote:
>
Hi Lakshmi,
The below failures are unrelated to this series.
Thanks.
--
Ashutosh
> Patch Details
>
> Series: i915: CAGF and RC6 changes for MTL (rev11)
> URL: https://patchwork.freedesktop.org/series/108156/
> State: failure
> Details:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/index.htm
> l
>
> CI Bug Log - changes from CI_DRM_12288 -> Patchwork_108156v11
>
> Summary
>
> FAILURE
>
> Serious unknown changes coming with Patchwork_108156v11 absolutely
> need to be verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_108156v11, please notify your bug team to
> allow them to document this new failure mode, which will reduce false positives in CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/index.htm
> l
>
> Participating hosts (41 -> 40)
>
> Additional (1): bat-atsm-1
> Missing (2): fi-ctg-p8600 fi-icl-u2
>
> Possible new issues
>
> Here are the unknown changes that may have been introduced in Patchwork_108156v11:
>
> IGT changes
>
> Possible regressions
>
> • igt@gem_exec_parallel@engines@contexts:
>
> □ fi-bsw-nick: PASS -> INCOMPLETE
> • igt@i915_selftest@live@hugepages:
>
> □ fi-cfl-8109u: PASS -> DMESG-FAIL
>
> □ fi-skl-guc: PASS -> DMESG-FAIL
>
> • igt@i915_suspend@basic-s3-without-i915:
>
> □ fi-rkl-11600: NOTRUN -> INCOMPLETE
>
> Suppressed
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: CAGF and RC6 changes for MTL (rev11)
2022-10-24 20:24 ` [Intel-gfx] " Ashutosh Dixit
` (9 preceding siblings ...)
(?)
@ 2022-10-27 15:58 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2022-10-27 15:58 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 49040 bytes --]
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev11)
URL : https://patchwork.freedesktop.org/series/108156/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12288_full -> Patchwork_108156v11_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_108156v11_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_108156v11_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 11)
------------------------------
Additional (2): shard-rkl shard-dg1
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_108156v11_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rps@waitboost:
- shard-tglb: [PASS][1] -> [FAIL][2] +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-tglb6/igt@i915_pm_rps@waitboost.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb1/igt@i915_pm_rps@waitboost.html
* igt@kms_cursor_legacy@cursor-vs-flip@varying-size:
- shard-skl: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl4/igt@kms_cursor_legacy@cursor-vs-flip@varying-size.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl2/igt@kms_cursor_legacy@cursor-vs-flip@varying-size.html
Known issues
------------
Here are the changes found in Patchwork_108156v11_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-skl: ([PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [FAIL][26], [PASS][27], [PASS][28], [PASS][29]) ([i915#5032]) -> ([PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl10/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl10/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl10/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl9/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl9/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl9/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl9/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl7/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl7/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl7/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl7/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl6/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl6/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl6/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl6/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl6/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl4/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl4/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl4/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl4/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl3/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl3/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl3/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl10/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl10/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl9/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl9/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl9/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl7/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl7/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl6/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl6/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl6/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl6/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl5/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl5/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl4/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl4/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl4/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl3/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl3/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl2/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl1/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl1/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl10/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl10/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_ccs@block-copy-inplace:
- shard-tglb: NOTRUN -> [SKIP][51] ([i915#3555] / [i915#5325])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb6/igt@gem_ccs@block-copy-inplace.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-tglb: NOTRUN -> [FAIL][52] ([i915#2842])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb1/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-skl: NOTRUN -> [SKIP][53] ([fdo#109271]) +39 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl3/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][54] -> [FAIL][55] ([i915#2842])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb2/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_gttfill@all:
- shard-apl: [PASS][56] -> [INCOMPLETE][57] ([i915#7311])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-apl2/igt@gem_exec_gttfill@all.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-apl2/igt@gem_exec_gttfill@all.html
* igt@gem_exec_schedule@wide@rcs0:
- shard-glk: [PASS][58] -> [FAIL][59] ([i915#7185])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-glk8/igt@gem_exec_schedule@wide@rcs0.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-glk2/igt@gem_exec_schedule@wide@rcs0.html
* igt@gem_userptr_blits@coherency-sync:
- shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109290])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb3/igt@gem_userptr_blits@coherency-sync.html
- shard-tglb: NOTRUN -> [SKIP][61] ([fdo#110542])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb2/igt@gem_userptr_blits@coherency-sync.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-tglb: NOTRUN -> [SKIP][62] ([i915#3297]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb1/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gen7_exec_parse@load-register-reg:
- shard-tglb: NOTRUN -> [SKIP][63] ([fdo#109289]) +2 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb6/igt@gen7_exec_parse@load-register-reg.html
* igt@gen7_exec_parse@oacontrol-tracking:
- shard-iclb: NOTRUN -> [SKIP][64] ([fdo#109289])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb3/igt@gen7_exec_parse@oacontrol-tracking.html
* igt@gen9_exec_parse@cmd-crossing-page:
- shard-tglb: NOTRUN -> [SKIP][65] ([i915#2527] / [i915#2856]) +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb6/igt@gen9_exec_parse@cmd-crossing-page.html
* igt@gen9_exec_parse@shadow-peek:
- shard-iclb: NOTRUN -> [SKIP][66] ([i915#2856])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb3/igt@gen9_exec_parse@shadow-peek.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][67] -> [FAIL][68] ([i915#3989] / [i915#454])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb2/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-tglb: NOTRUN -> [SKIP][69] ([fdo#111644] / [i915#1397] / [i915#2411])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb6/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-tglb: NOTRUN -> [SKIP][70] ([i915#5286]) +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb1/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-glk: NOTRUN -> [SKIP][71] ([fdo#109271]) +16 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-glk6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-tglb: NOTRUN -> [SKIP][72] ([fdo#111615]) +2 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs_cc:
- shard-tglb: NOTRUN -> [SKIP][73] ([i915#6095]) +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb2/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs_cc.html
- shard-iclb: NOTRUN -> [SKIP][74] ([fdo#109278])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb3/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][75] ([i915#3689] / [i915#3886]) +3 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb6/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][76] ([fdo#109278] / [i915#3886]) +3 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb3/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#3886]) +2 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl3/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#3886]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-apl3/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#3886]) +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-glk6/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][80] ([fdo#111615] / [i915#3689]) +3 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb1/igt@kms_ccs@pipe-c-ccs-on-another-bo-yf_tiled_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_dg2_rc_ccs:
- shard-tglb: NOTRUN -> [SKIP][81] ([i915#3689] / [i915#6095])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb6/igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_dg2_rc_ccs.html
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][82] ([i915#3689]) +6 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb6/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_ccs.html
* igt@kms_cdclk@mode-transition-all-outputs:
- shard-tglb: NOTRUN -> [SKIP][83] ([i915#3742])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb1/igt@kms_cdclk@mode-transition-all-outputs.html
* igt@kms_chamelium@hdmi-aspect-ratio:
- shard-iclb: NOTRUN -> [SKIP][84] ([fdo#109284] / [fdo#111827])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb3/igt@kms_chamelium@hdmi-aspect-ratio.html
* igt@kms_chamelium@hdmi-crc-nonplanar-formats:
- shard-apl: NOTRUN -> [SKIP][85] ([fdo#109271] / [fdo#111827])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-apl3/igt@kms_chamelium@hdmi-crc-nonplanar-formats.html
- shard-glk: NOTRUN -> [SKIP][86] ([fdo#109271] / [fdo#111827])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-glk6/igt@kms_chamelium@hdmi-crc-nonplanar-formats.html
* igt@kms_chamelium@vga-hpd:
- shard-tglb: NOTRUN -> [SKIP][87] ([fdo#109284] / [fdo#111827]) +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb6/igt@kms_chamelium@vga-hpd.html
* igt@kms_chamelium@vga-hpd-with-enabled-mode:
- shard-skl: NOTRUN -> [SKIP][88] ([fdo#109271] / [fdo#111827])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl3/igt@kms_chamelium@vga-hpd-with-enabled-mode.html
* igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1:
- shard-tglb: [PASS][89] -> [INCOMPLETE][90] ([i915#2411])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-tglb8/igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb3/igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1.html
* igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
- shard-tglb: NOTRUN -> [SKIP][91] ([fdo#109274] / [fdo#111825])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb6/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_flip@2x-plain-flip-fb-recreate:
- shard-tglb: NOTRUN -> [SKIP][92] ([fdo#109274] / [fdo#111825] / [i915#3637])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb1/igt@kms_flip@2x-plain-flip-fb-recreate.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][93] -> [FAIL][94] ([i915#2122])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-glk7/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-glk3/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [PASS][95] -> [FAIL][96] ([i915#2122])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-skl: [PASS][97] -> [FAIL][98] ([i915#79])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
- shard-tglb: NOTRUN -> [SKIP][99] ([i915#2587] / [i915#2672])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][100] ([i915#2672]) +5 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][101] ([i915#2587] / [i915#2672]) +3 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][102] ([i915#3555])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][103] ([i915#2672] / [i915#3555])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-tglb: NOTRUN -> [SKIP][104] ([i915#6497]) +3 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite:
- shard-tglb: NOTRUN -> [SKIP][105] ([fdo#109280] / [fdo#111825]) +10 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite.html
* igt@kms_hdr@static-toggle-suspend:
- shard-tglb: NOTRUN -> [SKIP][106] ([i915#3555])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb6/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_plane_lowres@tiling-none@pipe-a-edp-1:
- shard-iclb: NOTRUN -> [SKIP][107] ([i915#3536]) +2 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb3/igt@kms_plane_lowres@tiling-none@pipe-a-edp-1.html
* igt@kms_plane_lowres@tiling-none@pipe-c-edp-1:
- shard-tglb: NOTRUN -> [SKIP][108] ([i915#3536]) +3 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb2/igt@kms_plane_lowres@tiling-none@pipe-c-edp-1.html
* igt@kms_plane_scaling@invalid-num-scalers@pipe-a-edp-1-invalid-num-scalers:
- shard-skl: NOTRUN -> [SKIP][109] ([fdo#109271] / [i915#5776]) +2 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl3/igt@kms_plane_scaling@invalid-num-scalers@pipe-a-edp-1-invalid-num-scalers.html
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-a-dp-1:
- shard-apl: NOTRUN -> [SKIP][110] ([fdo#109271]) +32 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-apl3/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-a-dp-1.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1:
- shard-iclb: [PASS][111] -> [SKIP][112] ([i915#5176]) +2 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-iclb7/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb2/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-d-edp-1:
- shard-tglb: NOTRUN -> [SKIP][113] ([i915#5176]) +3 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb6/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-d-edp-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-edp-1:
- shard-tglb: NOTRUN -> [SKIP][114] ([i915#5235]) +3 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-edp-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1:
- shard-iclb: [PASS][115] -> [SKIP][116] ([i915#5235]) +2 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-iclb1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-tglb: NOTRUN -> [SKIP][117] ([i915#2920]) +1 similar issue
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-tglb: NOTRUN -> [SKIP][118] ([i915#7037])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb1/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][119] -> [SKIP][120] ([fdo#109441])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb7/igt@kms_psr@psr2_cursor_render.html
* igt@kms_psr@psr2_primary_blt:
- shard-tglb: NOTRUN -> [FAIL][121] ([i915#132] / [i915#3467]) +1 similar issue
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb2/igt@kms_psr@psr2_primary_blt.html
- shard-iclb: NOTRUN -> [SKIP][122] ([fdo#109441])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb3/igt@kms_psr@psr2_primary_blt.html
* igt@kms_writeback@writeback-check-output:
- shard-skl: NOTRUN -> [SKIP][123] ([fdo#109271] / [i915#2437])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl3/igt@kms_writeback@writeback-check-output.html
* igt@prime_vgem@basic-userptr:
- shard-tglb: NOTRUN -> [SKIP][124] ([fdo#109295] / [i915#3301])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb1/igt@prime_vgem@basic-userptr.html
* igt@sysfs_clients@split-25:
- shard-apl: NOTRUN -> [SKIP][125] ([fdo#109271] / [i915#2994])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-apl3/igt@sysfs_clients@split-25.html
- shard-glk: NOTRUN -> [SKIP][126] ([fdo#109271] / [i915#2994])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-glk6/igt@sysfs_clients@split-25.html
* igt@sysfs_heartbeat_interval@mixed@bcs0:
- shard-skl: NOTRUN -> [FAIL][127] ([i915#1731]) +2 similar issues
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl3/igt@sysfs_heartbeat_interval@mixed@bcs0.html
#### Possible fixes ####
* igt@gem_eio@reset-stress:
- shard-tglb: [FAIL][128] ([i915#5784]) -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-tglb2/igt@gem_eio@reset-stress.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb8/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@parallel-contexts:
- shard-iclb: [SKIP][130] ([i915#4525]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-iclb7/igt@gem_exec_balancer@parallel-contexts.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb2/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][132] ([i915#2842]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][134] ([i915#2842]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_mmap_gtt@medium-copy-odd:
- shard-glk: [DMESG-WARN][136] ([i915#7311]) -> [PASS][137]
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-glk7/igt@gem_mmap_gtt@medium-copy-odd.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-glk6/igt@gem_mmap_gtt@medium-copy-odd.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- shard-skl: [WARN][138] ([i915#1804]) -> [PASS][139]
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl7/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl7/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
* igt@i915_pm_rps@engine-order:
- shard-apl: [FAIL][140] ([i915#6537]) -> [PASS][141]
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-apl3/igt@i915_pm_rps@engine-order.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-apl7/igt@i915_pm_rps@engine-order.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1:
- shard-skl: [FAIL][142] ([i915#2521]) -> [PASS][143] +1 similar issue
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl4/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl1/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
* igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1:
- shard-apl: [DMESG-WARN][144] ([i915#180]) -> [PASS][145]
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-apl2/igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-apl3/igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: [FAIL][146] ([i915#4767]) -> [PASS][147]
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl6/igt@kms_fbcon_fbt@psr-suspend.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl4/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2:
- shard-glk: [FAIL][148] ([i915#79]) -> [PASS][149] +1 similar issue
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-glk6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [FAIL][150] ([i915#79]) -> [PASS][151] +1 similar issue
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:
- shard-skl: [DMESG-WARN][152] ([i915#1982]) -> [PASS][153]
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-skl4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][154] ([fdo#109441]) -> [PASS][155] +1 similar issue
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-iclb1/igt@kms_psr@psr2_no_drrs.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
#### Warnings ####
* igt@gem_pwrite@basic-exhaustion:
- shard-tglb: [WARN][156] ([i915#2658]) -> [INCOMPLETE][157] ([i915#7248])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-tglb1/igt@gem_pwrite@basic-exhaustion.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-tglb6/igt@gem_pwrite@basic-exhaustion.html
- shard-glk: [INCOMPLETE][158] ([i915#7248]) -> [INCOMPLETE][159] ([i915#7248] / [i915#7311])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-glk2/igt@gem_pwrite@basic-exhaustion.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-glk8/igt@gem_pwrite@basic-exhaustion.html
* igt@i915_pm_rc6_residency@rc6-idle@rcs0:
- shard-iclb: [FAIL][160] ([i915#2684]) -> [WARN][161] ([i915#2684])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-iclb8/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb6/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
- shard-iclb: [SKIP][162] ([fdo#111068] / [i915#658]) -> [SKIP][163] ([i915#2920]) +1 similar issue
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-iclb1/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-iclb: [SKIP][164] ([i915#2920]) -> [SKIP][165] ([i915#658]) +1 similar issue
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@runner@aborted:
- shard-iclb: ([FAIL][166], [FAIL][167], [FAIL][168], [FAIL][169], [FAIL][170], [FAIL][171], [FAIL][172], [FAIL][173]) ([i915#3002] / [i915#4312]) -> ([FAIL][174], [FAIL][175], [FAIL][176], [FAIL][177], [FAIL][178], [FAIL][179], [FAIL][180], [FAIL][181]) ([i915#3002] / [i915#4312] / [i915#7300])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-iclb7/igt@runner@aborted.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-iclb6/igt@runner@aborted.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-iclb6/igt@runner@aborted.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-iclb6/igt@runner@aborted.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-iclb2/igt@runner@aborted.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-iclb6/igt@runner@aborted.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-iclb3/igt@runner@aborted.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12288/shard-iclb7/igt@runner@aborted.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb8/igt@runner@aborted.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb5/igt@runner@aborted.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb3/igt@runner@aborted.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb8/igt@runner@aborted.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb3/igt@runner@aborted.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb8/igt@runner@aborted.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb8/igt@runner@aborted.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/shard-iclb2/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109290]: https://bugs.freedesktop.org/show_bug.cgi?id=109290
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3467]: https://gitlab.freedesktop.org/drm/intel/issues/3467
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3810]: https://gitlab.freedesktop.org/drm/intel/issues/3810
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874
[i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5032]: https://gitlab.freedesktop.org/drm/intel/issues/5032
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5776]: https://gitlab.freedesktop.org/drm/intel/issues/5776
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6032]: https://gitlab.freedesktop.org/drm/intel/issues/6032
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6251]: https://gitlab.freedesktop.org/drm/intel/issues/6251
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#6537]: https://gitlab.freedesktop.org/drm/intel/issues/6537
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6928]: https://gitlab.freedesktop.org/drm/intel/issues/6928
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7142]: https://gitlab.freedesktop.org/drm/intel/issues/7142
[i915#7185]: https://gitlab.freedesktop.org/drm/intel/issues/7185
[i915#7247]: https://gitlab.freedesktop.org/drm/intel/issues/7247
[i915#7248]: https://gitlab.freedesktop.org/drm/intel/issues/7248
[i915#7300]: https://gitlab.freedesktop.org/drm/intel/issues/7300
[i915#7311]: https://gitlab.freedesktop.org/drm/intel/issues/7311
[i915#7316]: https://gitlab.freedesktop.org/drm/intel/issues/7316
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_12288 -> Patchwork_108156v11
CI-20190529: 20190529
CI_DRM_12288: 61a92db3f6785121281a51f95960a3282d47117d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7025: f8b8e0713f87460a2c050ec8fe18fa487f98e228 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108156v11: 61a92db3f6785121281a51f95960a3282d47117d @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v11/index.html
[-- Attachment #2: Type: text/html, Size: 47511 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2022-10-27 15:58 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-24 20:24 [PATCH 0/5] i915: CAGF and RC6 changes for MTL Ashutosh Dixit
2022-10-24 20:24 ` [Intel-gfx] " Ashutosh Dixit
2022-10-24 20:24 ` [PATCH 1/5] drm/i915/rps: Prefer REG_FIELD_GET in intel_rps_get_cagf Ashutosh Dixit
2022-10-24 20:24 ` [Intel-gfx] " Ashutosh Dixit
2022-10-24 20:24 ` [PATCH 2/5] drm/i915: Use GEN12_RPSTAT register for GT freq Ashutosh Dixit
2022-10-24 20:24 ` [Intel-gfx] " Ashutosh Dixit
2022-10-24 20:24 ` [PATCH 3/5] drm/i915/mtl: Modify CAGF functions for MTL Ashutosh Dixit
2022-10-24 20:24 ` [Intel-gfx] " Ashutosh Dixit
2022-10-24 20:24 ` [PATCH 4/5] drm/i915/gt: Use RC6 residency types as arguments to residency functions Ashutosh Dixit
2022-10-24 20:24 ` [Intel-gfx] " Ashutosh Dixit
2022-10-24 20:24 ` [PATCH 5/5] drm/i915/mtl: C6 residency and C state type for MTL SAMedia Ashutosh Dixit
2022-10-24 20:24 ` [Intel-gfx] " Ashutosh Dixit
2022-10-25 1:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: CAGF and RC6 changes for MTL (rev11) Patchwork
2022-10-25 1:25 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-10-25 17:25 ` Dixit, Ashutosh
2022-10-27 5:41 ` Vudum, Lakshminarayana
2022-10-26 22:34 ` Patchwork
2022-10-27 4:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-27 15:58 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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