[PATCH v3] riscv: support update_mmu_tlb()

[PATCH v3] riscv: support update_mmu_tlb()

[Jinyu Tang]

Add macro definition to support update_mmu_tlb() for riscv,
this function is from commit:7df676974359 ("mm/memory.c:Update
local TLB if PTE entry exists").

update_mmu_tlb() is used when a thread notice that other cpu thread
has handled the fault and changed the PTE. For MIPS, it's worth to
do that,this cpu thread will trap in tlb fault again otherwise.

For RISCV, it's also better to flush local tlb than do nothing in
update_mmu_tlb(). There are two kinds of page fault that have
update_mmu_tlb() inside:

1.page fault which PTE is NOT none, only protection check error,
like write protection fault. If updata_mmu_tlb() is empty, after
finsh page fault this time and re-execute, cpu will find address
but protection checked error in tlb again. So this will cause
another page fault. PTE in memory is good now,so update_mmu_cache()
in handle_pte_fault() will be executed. If updata_mmu_tlb() is not
empty flush local tlb, cpu won't find this address in tlb next time,
and get entry in physical memory, so it won't cause another page
fault.

2.page fault which PTE is none or swapped.
For this case, this cpu thread won't cause another page fault,cpu
will have tlb miss when re-execute, and get entry in memory
directly. But "set pte in phycial memory and flush local tlb" is
pratice in Linux, it's better to flush local tlb if it find entry
in phycial memory has changed.

Maybe it's same for other ARCH which can't detect PTE changed and
update it in local tlb automatically.

Signed-off-by: Jinyu Tang <tjytimi@163.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
v2 -> v3:
Explain why it should do this.Thanks for Conor Dooley's Advice.

v1 -> v2:
Change the format with the help from Andrew Jones and Conor Dooley
 
 arch/riscv/include/asm/pgtable.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 7ec936910a96..c61ae83aadee 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -418,6 +418,9 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
 	local_flush_tlb_page(address);
 }
 
+#define __HAVE_ARCH_UPDATE_MMU_TLB
+#define update_mmu_tlb update_mmu_cache
+
 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
 		unsigned long address, pmd_t *pmdp)
 {
-- 
2.30.2


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[PATCH v3] riscv: support update_mmu_tlb()

[Jinyu Tang]

Add macro definition to support update_mmu_tlb() for riscv,
this function is from commit:7df676974359 ("mm/memory.c:Update
local TLB if PTE entry exists").

update_mmu_tlb() is used when a thread notice that other cpu thread
has handled the fault and changed the PTE. For MIPS, it's worth to
do that,this cpu thread will trap in tlb fault again otherwise.

For RISCV, it's also better to flush local tlb than do nothing in
update_mmu_tlb(). There are two kinds of page fault that have
update_mmu_tlb() inside:

1.page fault which PTE is NOT none, only protection check error,
like write protection fault. If updata_mmu_tlb() is empty, after
finsh page fault this time and re-execute, cpu will find address
but protection checked error in tlb again. So this will cause
another page fault. PTE in memory is good now,so update_mmu_cache()
in handle_pte_fault() will be executed. If updata_mmu_tlb() is not
empty flush local tlb, cpu won't find this address in tlb next time,
and get entry in physical memory, so it won't cause another page
fault.

2.page fault which PTE is none or swapped.
For this case, this cpu thread won't cause another page fault,cpu
will have tlb miss when re-execute, and get entry in memory
directly. But "set pte in phycial memory and flush local tlb" is
pratice in Linux, it's better to flush local tlb if it find entry
in phycial memory has changed.

Maybe it's same for other ARCH which can't detect PTE changed and
update it in local tlb automatically.

Signed-off-by: Jinyu Tang <tjytimi@163.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
v2 -> v3:
Explain why it should do this.Thanks for Conor Dooley's Advice.

v1 -> v2:
Change the format with the help from Andrew Jones and Conor Dooley
 
 arch/riscv/include/asm/pgtable.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 7ec936910a96..c61ae83aadee 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -418,6 +418,9 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
 	local_flush_tlb_page(address);
 }
 
+#define __HAVE_ARCH_UPDATE_MMU_TLB
+#define update_mmu_tlb update_mmu_cache
+
 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
 		unsigned long address, pmd_t *pmdp)
 {
-- 
2.30.2

Re: [PATCH v3] riscv: support update_mmu_tlb()

[Palmer Dabbelt]

On Sun, 9 Oct 2022 21:45:03 +0800, Jinyu Tang wrote:
> Add macro definition to support update_mmu_tlb() for riscv,
> this function is from commit:7df676974359 ("mm/memory.c:Update
> local TLB if PTE entry exists").
> 
> update_mmu_tlb() is used when a thread notice that other cpu thread
> has handled the fault and changed the PTE. For MIPS, it's worth to
> do that,this cpu thread will trap in tlb fault again otherwise.
> 
> [...]

Applied, thanks!

[1/1] riscv: support update_mmu_tlb()
      https://git.kernel.org/palmer/c/1b52861f0e04

Best regards,
-- 
Palmer Dabbelt <palmer@rivosinc.com>

Re: [PATCH v3] riscv: support update_mmu_tlb()

[Palmer Dabbelt]

On Sun, 9 Oct 2022 21:45:03 +0800, Jinyu Tang wrote:
> Add macro definition to support update_mmu_tlb() for riscv,
> this function is from commit:7df676974359 ("mm/memory.c:Update
> local TLB if PTE entry exists").
> 
> update_mmu_tlb() is used when a thread notice that other cpu thread
> has handled the fault and changed the PTE. For MIPS, it's worth to
> do that,this cpu thread will trap in tlb fault again otherwise.
> 
> [...]

Applied, thanks!

[1/1] riscv: support update_mmu_tlb()
      https://git.kernel.org/palmer/c/1b52861f0e04

Best regards,
-- 
Palmer Dabbelt <palmer@rivosinc.com>

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