[PATCH] target/mips: enable LBX/LWX/* instructions for Octeon

[PATCH] target/mips: enable LBX/LWX/* instructions for Octeon

[Pavel Dovgalyuk]

This patch changes condition and function name for enabling
indexed load instructions for Octeon vCPUs. Octeons do not
have DSP extension, but implement LBX-and-others.

Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
---
 target/mips/tcg/translate.c |   10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index c3f92ea652..6248143c62 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -12173,12 +12173,16 @@ enum {
 #include "nanomips_translate.c.inc"
 
 /* MIPSDSP functions. */
-static void gen_mipsdsp_ld(DisasContext *ctx, uint32_t opc,
+
+/* Indexed load is not for DSP only */
+static void gen_mips_lx(DisasContext *ctx, uint32_t opc,
                            int rd, int base, int offset)
 {
     TCGv t0;
 
-    check_dsp(ctx);
+    if (!(ctx->insn_flags & INSN_OCTEON)) {
+        check_dsp(ctx);
+    }
     t0 = tcg_temp_new();
 
     if (base == 0) {
@@ -14523,7 +14527,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
         case OPC_LBUX:
         case OPC_LHX:
         case OPC_LWX:
-            gen_mipsdsp_ld(ctx, op2, rd, rs, rt);
+            gen_mips_lx(ctx, op2, rd, rs, rt);
             break;
         default:            /* Invalid */
             MIPS_INVAL("MASK LX");

Re: [PATCH] target/mips: enable LBX/LWX/* instructions for Octeon

[Philippe Mathieu-Daudé]

On 1/11/22 06:29, Pavel Dovgalyuk wrote:
> This patch changes condition and function name for enabling
> indexed load instructions for Octeon vCPUs. Octeons do not
> have DSP extension, but implement LBX-and-others.
> 
> Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
> ---
>   target/mips/tcg/translate.c |   10 +++++++---
>   1 file changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
> index c3f92ea652..6248143c62 100644
> --- a/target/mips/tcg/translate.c
> +++ b/target/mips/tcg/translate.c
> @@ -12173,12 +12173,16 @@ enum {
>   #include "nanomips_translate.c.inc"
>   
>   /* MIPSDSP functions. */
> -static void gen_mipsdsp_ld(DisasContext *ctx, uint32_t opc,
> +
> +/* Indexed load is not for DSP only */
> +static void gen_mips_lx(DisasContext *ctx, uint32_t opc,
>                              int rd, int base, int offset)
>   {
>       TCGv t0;
>   
> -    check_dsp(ctx);
> +    if (!(ctx->insn_flags & INSN_OCTEON)) {

Ideally we'd need to check CP0 reg 9 select 7 bit 12 (USEUN in
Cavium Control) is set, otherwise these instrs are a NOP.

I presume QEMU Octeon emulation expects CvmCtl[USEUN] to be set
to be more useful; therefore:

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

> +        check_dsp(ctx);
> +    }
>       t0 = tcg_temp_new();
>   
>       if (base == 0) {
> @@ -14523,7 +14527,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
>           case OPC_LBUX:
>           case OPC_LHX:
>           case OPC_LWX:
> -            gen_mipsdsp_ld(ctx, op2, rd, rs, rt);
> +            gen_mips_lx(ctx, op2, rd, rs, rt);
>               break;
>           default:            /* Invalid */
>               MIPS_INVAL("MASK LX");
> 

Re: [PATCH] target/mips: enable LBX/LWX/* instructions for Octeon

[Philippe Mathieu-Daudé]

On 1/11/22 06:29, Pavel Dovgalyuk wrote:
> This patch changes condition and function name for enabling
> indexed load instructions for Octeon vCPUs. Octeons do not
> have DSP extension, but implement LBX-and-others.
> 
> Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
> ---
>   target/mips/tcg/translate.c |   10 +++++++---
>   1 file changed, 7 insertions(+), 3 deletions(-)

Queued to mips-fixes, thanks.