* [PATCH 0/4] Initial SDM670 and Pixel 3a support
@ 2022-11-01 23:57 Richard Acayan
2022-11-01 23:57 ` [PATCH 1/4] dt-bindings: arm: cpus: add qcom kryo 360 compatible Richard Acayan
` (3 more replies)
0 siblings, 4 replies; 16+ messages in thread
From: Richard Acayan @ 2022-11-01 23:57 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Robin Murphy, Chanho Park,
Thierry Reding, Stephan Gerhold, Lorenzo Pieralisi, Robert Marko,
Das Srinagesh, devicetree, linux-kernel, linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel
Do not apply this series yet. It is only for review comments. It can be
applied once the "qcom,sdm670-smmu-500" compatible string gets added (or
now if you don't care about handling an unnecessary quirk).
This adds the device trees and bindings to support the Qualcomm
Snapdragon 670 and Google Pixel 3a. This patch series, specifically the
last patch, depends on:
[PATCH v4 0/3] SDM670 Global Clocks
https://lore.kernel.org/all/20220914013922.198778-1-mailingradian@gmail.com/T/
[PATCH v2 0/2] RPMh Support for PM660 and PM660L
https://lore.kernel.org/all/20220920223331.150635-1-mailingradian@gmail.com/T/
[PATCH v2 0/2] SDM670 RPMh Clocks
https://lore.kernel.org/all/20220920223734.151135-1-mailingradian@gmail.com/T/
[PATCH v2 0/2] SDM670 USB 2.0 support
https://lore.kernel.org/all/20220922024656.178529-1-mailingradian@gmail.com/T/
[PATCH 0/2] SDM670 SDHCI support
https://lore.kernel.org/all/20220923014322.33620-1-mailingradian@gmail.com/T/
[PATCH v2 0/2] SDM670 Power Domains
https://lore.kernel.org/all/20221004221130.14076-1-mailingradian@gmail.com/T/
[PATCH v10 0/3] SDM670 Pin Control Driver
https://lore.kernel.org/all/20221014001934.4995-1-mailingradian@gmail.com/T/
[PATCH v6 0/4] SDM670 GPI DMA support
https://lore.kernel.org/all/20221018005740.23952-1-mailingradian@gmail.com/T/
[RFC PATCH 0/9] iommy/arm-smmu-qcom: Rework Qualcomm SMMU bindings and implementation
https://lore.kernel.org/linux-iommu/73eee2ed-f8ee-f136-2853-34b27c099644@quicinc.com/T/
Richard Acayan (4):
dt-bindings: arm: cpus: add qcom kryo 360 compatible
dt-bindings: arm: qcom: add sdm670 and pixel 3a compatible
dt-bindings: firmware: scm: add sdm670 compatible
arm64: dts: qcom: add sdm670 and pixel 3a device trees
.../devicetree/bindings/arm/cpus.yaml | 1 +
.../devicetree/bindings/arm/qcom.yaml | 6 +
.../bindings/firmware/qcom,scm.yaml | 1 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/sdm670-google-sargo.dts | 519 +++++++
arch/arm64/boot/dts/qcom/sdm670.dtsi | 1216 +++++++++++++++++
6 files changed, 1744 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
create mode 100644 arch/arm64/boot/dts/qcom/sdm670.dtsi
P.S.: Thank you to all the maintainers and reviewers who went through
everything and made helpful comments!
--
2.38.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/4] dt-bindings: arm: cpus: add qcom kryo 360 compatible
2022-11-01 23:57 [PATCH 0/4] Initial SDM670 and Pixel 3a support Richard Acayan
@ 2022-11-01 23:57 ` Richard Acayan
2022-11-02 17:36 ` Rob Herring
2022-11-01 23:57 ` [PATCH 2/4] dt-bindings: arm: qcom: add sdm670 and pixel 3a compatible Richard Acayan
` (2 subsequent siblings)
3 siblings, 1 reply; 16+ messages in thread
From: Richard Acayan @ 2022-11-01 23:57 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Robin Murphy, Chanho Park,
Thierry Reding, Stephan Gerhold, Lorenzo Pieralisi, Robert Marko,
Das Srinagesh, devicetree, linux-kernel, linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel
The Snapdragon 670 uses CPUs named Kryo 360 silver and Kryo 360 gold.
Add the compatible string in the documentation.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
---
Documentation/devicetree/bindings/arm/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index 5c13b73e4d57..1247e9a975c9 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -178,6 +178,7 @@ properties:
- qcom,kryo250
- qcom,kryo260
- qcom,kryo280
+ - qcom,kryo360
- qcom,kryo385
- qcom,kryo468
- qcom,kryo485
--
2.38.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/4] dt-bindings: arm: qcom: add sdm670 and pixel 3a compatible
2022-11-01 23:57 [PATCH 0/4] Initial SDM670 and Pixel 3a support Richard Acayan
2022-11-01 23:57 ` [PATCH 1/4] dt-bindings: arm: cpus: add qcom kryo 360 compatible Richard Acayan
@ 2022-11-01 23:57 ` Richard Acayan
2022-11-02 17:37 ` Rob Herring
2022-11-01 23:57 ` [PATCH 3/4] dt-bindings: firmware: scm: add sdm670 compatible Richard Acayan
2022-11-01 23:57 ` [PATCH 4/4] arm64: dts: qcom: add sdm670 and pixel 3a device trees Richard Acayan
3 siblings, 1 reply; 16+ messages in thread
From: Richard Acayan @ 2022-11-01 23:57 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Robin Murphy, Chanho Park,
Thierry Reding, Stephan Gerhold, Lorenzo Pieralisi, Robert Marko,
Das Srinagesh, devicetree, linux-kernel, linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel
The Snapdragon 670 and Pixel 3a initial device trees are about to be
added. Add the compatible strings for the board.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 207e28260206..f9eddc22d4a4 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -51,6 +51,7 @@ description: |
sdm632
sdm636
sdm660
+ sdm670
sdm845
sdx55
sdx65
@@ -654,6 +655,11 @@ properties:
- xiaomi,lavender
- const: qcom,sdm660
+ - items:
+ - enum:
+ - google,sargo
+ - const: qcom,sdm670
+
- items:
- enum:
- qcom,sdx55-mtp
--
2.38.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 3/4] dt-bindings: firmware: scm: add sdm670 compatible
2022-11-01 23:57 [PATCH 0/4] Initial SDM670 and Pixel 3a support Richard Acayan
2022-11-01 23:57 ` [PATCH 1/4] dt-bindings: arm: cpus: add qcom kryo 360 compatible Richard Acayan
2022-11-01 23:57 ` [PATCH 2/4] dt-bindings: arm: qcom: add sdm670 and pixel 3a compatible Richard Acayan
@ 2022-11-01 23:57 ` Richard Acayan
2022-11-02 17:37 ` Rob Herring
2022-11-02 17:51 ` Guru Das Srinagesh
2022-11-01 23:57 ` [PATCH 4/4] arm64: dts: qcom: add sdm670 and pixel 3a device trees Richard Acayan
3 siblings, 2 replies; 16+ messages in thread
From: Richard Acayan @ 2022-11-01 23:57 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Robin Murphy, Chanho Park,
Thierry Reding, Stephan Gerhold, Lorenzo Pieralisi, Robert Marko,
Das Srinagesh, devicetree, linux-kernel, linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel
The Snapdragon 670 uses SCM as for PSCI power management. Document the
appropriate compatible string for it.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
---
Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
index be1b5746eddb..25688571ee7c 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
@@ -41,6 +41,7 @@ properties:
- qcom,scm-sc7180
- qcom,scm-sc7280
- qcom,scm-sc8280xp
+ - qcom,scm-sdm670
- qcom,scm-sdm845
- qcom,scm-sdx55
- qcom,scm-sdx65
--
2.38.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 4/4] arm64: dts: qcom: add sdm670 and pixel 3a device trees
2022-11-01 23:57 [PATCH 0/4] Initial SDM670 and Pixel 3a support Richard Acayan
` (2 preceding siblings ...)
2022-11-01 23:57 ` [PATCH 3/4] dt-bindings: firmware: scm: add sdm670 compatible Richard Acayan
@ 2022-11-01 23:57 ` Richard Acayan
2022-11-02 2:19 ` Richard Acayan
` (3 more replies)
3 siblings, 4 replies; 16+ messages in thread
From: Richard Acayan @ 2022-11-01 23:57 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Robin Murphy, Chanho Park,
Thierry Reding, Stephan Gerhold, Lorenzo Pieralisi, Robert Marko,
Das Srinagesh, devicetree, linux-kernel, linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel
The Qualcomm Snapdragon 670 has been out for a while. Add a device tree
for it and the Google Pixel 3a as the first device.
The Pixel 3a has the same bootloader issue as the Pixel 3 and will not work
on Android 10 bootloaders or later until it gets fixed for the Pixel 3.
SoC Initial Features:
- power management
- clocks
- pinctrl
- eMMC
- USB 2.0
- GENI I2C
- IOMMU
- RPMh
- interrupts
Device-Specific Initial Features:
- side buttons (keys)
- regulators
- touchscreen
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/sdm670-google-sargo.dts | 519 +++++++
arch/arm64/boot/dts/qcom/sdm670.dtsi | 1216 +++++++++++++++++
3 files changed, 1736 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
create mode 100644 arch/arm64/boot/dts/qcom/sdm670.dtsi
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index b0558d3389e5..4eb5d8829efb 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -124,6 +124,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm632-fairphone-fp3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
new file mode 100644
index 000000000000..fa3dee78e442
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
@@ -0,0 +1,519 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device tree for Google Pixel 3a, adapted from google-blueline device tree,
+ * xiaomi-lavender device tree, and oneplus-common device tree.
+ *
+ * Copyright (c) 2022, Richard Acayan. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include "sdm670.dtsi"
+#include "pm660.dtsi"
+#include "pm660l.dtsi"
+
+/delete-node/ &mpss_region;
+/delete-node/ &venus_mem;
+/delete-node/ &wlan_msa_mem;
+/delete-node/ &cdsp_mem;
+/delete-node/ &mba_region;
+/delete-node/ &adsp_mem;
+/delete-node/ &ipa_fw_mem;
+/delete-node/ &ipa_gsi_mem;
+/delete-node/ &gpu_mem;
+
+/ {
+ model = "Google Pixel 3a";
+ compatible = "google,sargo", "qcom,sdm670";
+ qcom,board-id = <0x00041e05 0>;
+ qcom,msm-id = <321 0x20001>;
+
+ aliases { };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer@9c000000 {
+ compatible = "simple-framebuffer";
+ reg = <0x0 0x9c000000 0x0 (1080 * 2220 * 4)>;
+ width = <1080>;
+ height = <2220>;
+ stride = <(1080 * 4)>;
+ format = "a8r8g8b8";
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ mpss_region: mpss@8b000000 {
+ reg = <0 0x8b000000 0 0x9800000>;
+ no-map;
+ };
+
+ venus_mem: venus@94800000 {
+ reg = <0 0x94800000 0 0x500000>;
+ no-map;
+ };
+
+ wlan_msa_mem: wlan-msa@94d00000 {
+ reg = <0 0x94d00000 0 0x100000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp@94e00000 {
+ reg = <0 0x94e00000 0 0x800000>;
+ no-map;
+ };
+
+ mba_region: mba@95600000 {
+ reg = <0 0x95600000 0 0x200000>;
+ no-map;
+ };
+
+ adsp_mem: adsp@95800000 {
+ reg = <0 0x95800000 0 0x2200000>;
+ no-map;
+ };
+
+ ipa_fw_mem: ipa-fw@97a00000 {
+ reg = <0 0x97a00000 0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: ipa-gsi@97a10000 {
+ reg = <0 0x97a10000 0 0x5000>;
+ no-map;
+ };
+
+ gpu_mem: gpu@97a15000 {
+ reg = <0 0x97a15000 0 0x2000>;
+ no-map;
+ };
+
+ framebuffer-region@9c000000 {
+ reg = <0 0x9c000000 0 0x2400000>;
+ no-map;
+ };
+
+ /* Also includes ramoops regions */
+ debug_info_mem: debug-info@a1800000 {
+ reg = <0 0xa1800000 0 0x411000>;
+ no-map;
+ };
+ };
+
+ /*
+ * Supply map from xiaomi-lavender specifies this as the supply for
+ * ldob1, ldob9, ldob10, ldoa2, and ldoa3, while downstream specifies
+ * this as a power domain. Set this as a fixed regulator with the same
+ * voltage as lavender until display is needed to avoid unneccessarily
+ * using a deprecated binding (regulator-fixed-domain).
+ */
+ vreg_s2b_1p05: vreg-s2b-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s2b";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3312000>;
+ regulator-max-microvolt = <3312000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&vol_up_pin>;
+
+ key-vol-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ /*
+ * The touchscreen regulator seems to be controlled somehow by a gpio.
+ * Model it as a fixed regulator and keep it on. Without schematics we
+ * don't know how this is actually wired up...
+ */
+ ts_1p8_supply: ts-1p8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "ts_1p8_supply";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&pm660_gpios 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&apps_rsc {
+ pm660l-regulators {
+ compatible = "qcom,pm660l-rpmh-regulators";
+ qcom,pmic-id = "b";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+
+ vdd-l1-l9-l10-supply = <&vreg_s2b_1p05>;
+ vdd-l2-supply = <&vreg_bob>;
+ vdd-l3-l5-l7-l8-supply = <&vreg_bob>;
+ vdd-l4-l6-supply = <&vreg_bob>;
+ vdd-bob-supply = <&vph_pwr>;
+
+ /* LDOs */
+ vreg_l1b_0p89: ldo1 {
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <900000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l2b_2p38: ldo2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l3b_2p93: ldo3 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l4b_2p96: ldo4 {
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l5b_2p96: ldo5 {
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l6b_3p15: ldo6 {
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l7b_3p1: ldo7 {
+ regulator-min-microvolt = <3088000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l8b_3p3: ldo8 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ /*
+ * Downstream specifies a fixed voltage of 3.312 V, but the
+ * PMIC4 BOB ranges don't support that. Widen the range a
+ * little to avoid adding a new BOB regulator type.
+ */
+ vreg_bob: bob {
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3328000>;
+ regulator-enable-ramp-delay = <500>;
+ };
+ };
+
+ pm660-regulators {
+ compatible = "qcom,pm660-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+
+ vdd-l1-l6-l7-supply = <&vreg_s6a_1p29>;
+ vdd-l2-l3-supply = <&vreg_s2b_1p05>;
+ vdd-l5-supply = <&vreg_s2b_1p05>;
+ vdd-l8-l9-l10-l11-l12-l13-l14-supply = <&vreg_s4a_1p92>;
+ vdd-l15-l16-l17-l18-l19-supply = <&vreg_bob>;
+
+ /*
+ * S1A (FTAPC0), S2A (FTAPC1), S3A (HFAPC1) are managed
+ * by the Core Power Reduction hardened (CPRh) and the
+ * Operating State Manager (OSM) HW automatically.
+ */
+
+ vreg_s4a_1p92: smps4 {
+ regulator-min-microvolt = <1808000>;
+ regulator-max-microvolt = <2040000>;
+ regulator-enable-ramp-delay = <200>;
+ };
+
+ vreg_s6a_1p29: smps6 {
+ regulator-min-microvolt = <1224000>;
+ regulator-max-microvolt = <1352000>;
+ regulator-enable-ramp-delay = <150>;
+ };
+
+ /* LDOs */
+ vreg_l1a_1p225: ldo1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l2a_1p0: ldo2 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l3a_1p0: ldo3 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l5a_0p8: ldo5 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l6a_1p28: ldo6 {
+ regulator-min-microvolt = <1248000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l7a_1p2: ldo7 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l8a_1p8: ldo8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l9a_1p8: ldo9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l10a_1p8: ldo10 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l11a_1p8: ldo11 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l12a_1p8: ldo12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l13a_1p8: ldo13 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l14a_1p8: ldo14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l15a_2p38: ldo15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l16a_2p7: ldo16 {
+ regulator-min-microvolt = <2696000>;
+ regulator-max-microvolt = <2696000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l17a_2p38: ldo17 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+
+ vreg_l19a_3p3: ldo19 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-enable-ramp-delay = <250>;
+ };
+ };
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&i2c9 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ synaptics-rmi4-i2c@20 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x20>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_default>;
+
+ /* VDD supply isn't specified, bind it to power */
+ vdd-supply = <&vph_pwr>;
+ vio-supply = <&ts_1p8_supply>;
+
+ syna,reset-delay-ms = <200>;
+ syna,startup-delay-ms = <200>;
+
+ rmi4-f01@1 {
+ reg = <0x01>;
+ syna,nosleep-mode = <1>;
+ };
+
+ rmi4-f12@12 {
+ reg = <0x12>;
+ touchscreen-x-mm = <62>;
+ touchscreen-y-mm = <127>;
+ syna,sensor-type = <1>;
+ };
+ };
+};
+
+&gcc {
+ protected-clocks = <GCC_QSPI_CORE_CLK>,
+ <GCC_QSPI_CORE_CLK_SRC>,
+ <GCC_QSPI_CNOC_PERIPH_AHB_CLK>;
+};
+
+&pm660l_gpios {
+ vol_up_pin: vol-up-state {
+ pins = "gpio7";
+ function = "normal";
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
+ input-enable;
+ bias-pull-up;
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ status = "okay";
+ linux,code = <KEY_VOLUMEDOWN>;
+};
+
+&sdhc_1 {
+ status = "okay";
+ supports-cqe;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-ddr-1_8v;
+
+ qcom,ddr-config = <0xc3040873>;
+
+ vmmc-supply = <&vreg_l4b_2p96>;
+ vqmmc-supply = <&vreg_l8a_1p8>;
+};
+
+&tlmm {
+ gpio-reserved-ranges = <0 4>, <81 4>;
+
+ touchscreen_default: ts-default-state {
+ ts-reset-pins {
+ pins = "gpio99";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ output-high;
+ };
+
+ ts-irq-pins {
+ pins = "gpio125";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ ts-switch-pins {
+ pins = "gpio135";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+};
+
+&usb_1_hsphy {
+ status = "okay";
+
+ vdd-supply = <&vreg_l1b_0p89>;
+ vdda-pll-supply = <&vreg_l10a_1p8>;
+ vdda-phy-dpdm-supply = <&vreg_l7b_3p1>;
+};
+
+&usb_1 {
+ status = "okay";
+
+ qcom,select-utmi-as-pipe-clk;
+};
+
+&usb_1_dwc3 {
+ /* Only peripheral works for now */
+ dr_mode = "peripheral";
+
+ /* Do not assume that sdm670.dtsi will never support USB 3.0 */
+ phys = <&usb_1_hsphy>;
+ phy-names = "usb2-phy";
+ maximum-speed = "high-speed";
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
new file mode 100644
index 000000000000..4450ece839a0
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -0,0 +1,1216 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SDM670 SoC device tree source, adapted from SDM845 SoC device tree
+ *
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Richard Acayan. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy-qcom-qusb2.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases { };
+
+ chosen { };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0 0x80000000 0 0>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hyp_mem: hyp-mem@85700000 {
+ reg = <0 0x85700000 0 0x600000>;
+ no-map;
+ };
+
+ xbl_mem: xbl-mem@85e00000 {
+ reg = <0 0x85e00000 0 0x100000>;
+ no-map;
+ };
+
+ aop_mem: aop-mem@85fc0000 {
+ reg = <0 0x85fc0000 0 0x20000>;
+ no-map;
+ };
+
+ aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x0 0x85fe0000 0 0x20000>;
+ no-map;
+ };
+
+ camera_mem: camera-mem@8ab00000 {
+ reg = <0 0x8ab00000 0 0x500000>;
+ no-map;
+ };
+
+ mpss_region: mpss@8b000000 {
+ reg = <0 0x8b000000 0 0x7e00000>;
+ no-map;
+ };
+
+ venus_mem: venus@92e00000 {
+ reg = <0 0x92e00000 0 0x500000>;
+ no-map;
+ };
+
+ wlan_msa_mem: wlan-msa@93300000 {
+ reg = <0 0x93300000 0 0x100000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp@93400000 {
+ reg = <0 0x93400000 0 0x800000>;
+ no-map;
+ };
+
+ mba_region: mba@93c00000 {
+ reg = <0 0x93c00000 0 0x200000>;
+ no-map;
+ };
+
+ adsp_mem: adsp@93e00000 {
+ reg = <0 0x93e00000 0 0x1e00000>;
+ no-map;
+ };
+
+ ipa_fw_mem: ipa-fw@95c00000 {
+ reg = <0 0x95c00000 0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: ipa-gsi@95c10000 {
+ reg = <0 0x95c10000 0 0x5000>;
+ no-map;
+ };
+
+ gpu_mem: gpu@95c15000 {
+ reg = <0 0x95c15000 0 0x2000>;
+ no-map;
+ };
+
+ spss_mem: spss@97b00000 {
+ reg = <0 0x97b00000 0 0x100000>;
+ no-map;
+ };
+
+ qseecom_mem: qseecom@9e400000 {
+ reg = <0 0x9e400000 0 0x1400000>;
+ no-map;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,kryo360";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ power-domains = <&CPU_PD0>;
+ power-domain-names = "psci";
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ L3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,kryo360";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ power-domains = <&CPU_PD1>;
+ power-domain-names = "psci";
+ next-level-cache = <&L2_100>;
+ L2_100: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "qcom,kryo360";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ power-domains = <&CPU_PD2>;
+ power-domain-names = "psci";
+ next-level-cache = <&L2_200>;
+ L2_200: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "qcom,kryo360";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ power-domains = <&CPU_PD3>;
+ power-domain-names = "psci";
+ next-level-cache = <&L2_300>;
+ L2_300: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU4: cpu@400 {
+ device_type = "cpu";
+ compatible = "qcom,kryo360";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ power-domains = <&CPU_PD4>;
+ power-domain-names = "psci";
+ next-level-cache = <&L2_400>;
+ L2_400: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU5: cpu@500 {
+ device_type = "cpu";
+ compatible = "qcom,kryo360";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ power-domains = <&CPU_PD5>;
+ power-domain-names = "psci";
+ next-level-cache = <&L2_500>;
+ L2_500: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU6: cpu@600 {
+ device_type = "cpu";
+ compatible = "qcom,kryo360";
+ reg = <0x0 0x600>;
+ enable-method = "psci";
+ power-domains = <&CPU_PD6>;
+ power-domain-names = "psci";
+ next-level-cache = <&L2_600>;
+ L2_600: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU7: cpu@700 {
+ device_type = "cpu";
+ compatible = "qcom,kryo360";
+ reg = <0x0 0x700>;
+ enable-method = "psci";
+ power-domains = <&CPU_PD7>;
+ power-domain-names = "psci";
+ next-level-cache = <&L2_700>;
+ L2_700: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+
+ core4 {
+ cpu = <&CPU4>;
+ };
+
+ core5 {
+ cpu = <&CPU5>;
+ };
+
+ core6 {
+ cpu = <&CPU6>;
+ };
+
+ core7 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "little-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <702>;
+ exit-latency-us = <915>;
+ min-residency-us = <1617>;
+ local-timer-stop;
+ };
+
+ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "big-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <526>;
+ exit-latency-us = <1854>;
+ min-residency-us = <2380>;
+ local-timer-stop;
+ };
+ };
+
+ domain-idle-states {
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x4100c244>;
+ entry-latency-us = <3263>;
+ exit-latency-us = <6562>;
+ min-residency-us = <9825>;
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <38400000>;
+ clock-output-names = "xo_board";
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32764>;
+ };
+ };
+
+ firmware {
+ scm {
+ compatible = "qcom,scm-sdm670", "qcom,scm";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+
+ CPU_PD0: power-domain-cpu0 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD1: power-domain-cpu1 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD2: power-domain-cpu2 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD3: power-domain-cpu3 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD4: power-domain-cpu4 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD5: power-domain-cpu5 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
+ };
+
+ CPU_PD6: power-domain-cpu6 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ };
+
+ CPU_PD7: power-domain-cpu7 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&BIG_CPU_SLEEP_0>;
+ };
+
+ CLUSTER_PD: power-domain-cluster {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&CLUSTER_SLEEP_0>;
+ };
+ };
+
+ soc: soc@0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0 0 0 0x10 0>;
+ dma-ranges = <0 0 0 0 0x10 0>;
+ compatible = "simple-bus";
+
+ gcc: clock-controller@100000 {
+ compatible = "qcom,gcc-sdm670";
+ reg = <0 0x00100000 0 0x1f0000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>;
+ clock-names = "bi_tcxo",
+ "bi_tcxo_ao",
+ "sleep_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ sdhc_1: mmc@7c4000 {
+ compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0 0x007c4000 0 0x1000>,
+ <0 0x007c5000 0 0x1000>,
+ <0 0x007c8000 0 0x8000>;
+ reg-names = "hc", "cqhci", "ice";
+
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
+ clock-names = "iface", "core", "xo", "ice", "bus";
+
+ iommus = <&apps_smmu 0x140 0xf>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc1_state_on>;
+ pinctrl-1 = <&sdc1_state_off>;
+ power-domains = <&rpmhpd SDM670_CX>;
+
+ bus-width = <8>;
+ non-removable;
+
+ status = "disabled";
+ };
+
+ gpi_dma0: dma-controller@800000 {
+ #dma-cells = <3>;
+ compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
+ reg = <0 0x00800000 0 0x60000>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <13>;
+ dma-channel-mask = <0xfa>;
+ iommus = <&apps_smmu 0x0016 0x0>;
+ status = "disabled";
+ };
+
+ qupv3_id_0: geniqup@8c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0 0x008c0000 0 0x6000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ iommus = <&apps_smmu 0x3 0x0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
+ interconnect-names = "qup-core";
+ status = "disabled";
+
+ i2c0: i2c@880000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00880000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c0_default>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c1: i2c@884000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00884000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c1_default>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c2: i2c@888000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00888000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c2_default>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c3: i2c@88c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x0088c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c3_default>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c4: i2c@890000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00890000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c4_default>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c5: i2c@894000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00894000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c5_default>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c6: i2c@898000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00898000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c6_default>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c7: i2c@89c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x0089c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c7_default>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 7 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+ };
+
+ gpi_dma1: dma-controller@a00000 {
+ #dma-cells = <3>;
+ compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
+ reg = <0 0x00a00000 0 0x60000>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <13>;
+ dma-channel-mask = <0xfa>;
+ iommus = <&apps_smmu 0x06d6 0x0>;
+ status = "disabled";
+ };
+
+ qupv3_id_1: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0 0x00ac0000 0 0x6000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ iommus = <&apps_smmu 0x6c3 0x0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ i2c8: i2c@a80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a80000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c8_default>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c9: i2c@a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a84000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c9_default>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c10: i2c@a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a88000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c10_default>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c11: i2c@a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a8c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c11_default>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c12: i2c@a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a90000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c12_default>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c13: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a94000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c13_default>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c14: i2c@a98000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a98000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c14_default>;
+ interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c15: i2c@a9c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a9c000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c15_default>;
+ interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SDM670_CX>;
+ dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 7 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+ };
+
+ tlmm: pinctrl@3400000 {
+ compatible = "qcom,sdm670-tlmm";
+ reg = <0 0x03400000 0 0xc00000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 151>;
+
+ qup_i2c0_default: qup-i2c0-default-state {
+ pins = "gpio0", "gpio1";
+ function = "qup0";
+ };
+
+ qup_i2c1_default: qup-i2c1-default-state {
+ pins = "gpio17", "gpio18";
+ function = "qup1";
+ };
+
+ qup_i2c2_default: qup-i2c2-default-state {
+ pins = "gpio27", "gpio28";
+ function = "qup2";
+ };
+
+ qup_i2c3_default: qup-i2c3-default-state {
+ pins = "gpio41", "gpio42";
+ function = "qup3";
+ };
+
+ qup_i2c4_default: qup-i2c4-default-state {
+ pins = "gpio89", "gpio90";
+ function = "qup4";
+ };
+
+ qup_i2c5_default: qup-i2c5-default-state {
+ pins = "gpio85", "gpio86";
+ function = "qup5";
+ };
+
+ qup_i2c6_default: qup-i2c6-default-state {
+ pins = "gpio45", "gpio46";
+ function = "qup6";
+ };
+
+ qup_i2c7_default: qup-i2c7-default-state {
+ pins = "gpio93", "gpio94";
+ function = "qup7";
+ };
+
+ qup_i2c8_default: qup-i2c8-default-state {
+ pins = "gpio65", "gpio66";
+ function = "qup8";
+ };
+
+ qup_i2c9_default: qup-i2c9-default-state {
+ pins = "gpio6", "gpio7";
+ function = "qup9";
+ };
+
+ qup_i2c10_default: qup-i2c10-default-state {
+ pins = "gpio55", "gpio56";
+ function = "qup10";
+ };
+
+ qup_i2c11_default: qup-i2c11-default-state {
+ pins = "gpio31", "gpio32";
+ function = "qup11";
+ };
+
+ qup_i2c12_default: qup-i2c12-default-state {
+ pins = "gpio49", "gpio50";
+ function = "qup12";
+ };
+
+ qup_i2c13_default: qup-i2c13-default-state {
+ pins = "gpio105", "gpio106";
+ function = "qup13";
+ };
+
+ qup_i2c14_default: qup-i2c14-default-state {
+ pins = "gpio33", "gpio34";
+ function = "qup14";
+ };
+
+ qup_i2c15_default: qup-i2c15-default-state {
+ pins = "gpio81", "gpio82";
+ function = "qup15";
+ };
+
+ sdc1_state_on: sdc1-on-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ rclk-pins {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc1_state_off: sdc1-off-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ rclk-pins {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+ };
+
+ usb_1_hsphy: phy@88e2000 {
+ compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy";
+ reg = <0 0x088e2000 0 0x400>;
+ status = "disabled";
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+ };
+
+ usb_1: usb@a6f8800 {
+ compatible = "qcom,sdm670-dwc3", "qcom,dwc3";
+ reg = <0 0x0a6f8800 0 0x400>;
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-ranges;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <150000000>;
+
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hs_phy_irq", "ss_phy_irq",
+ "dm_hs_phy_irq", "dp_hs_phy_irq";
+
+ power-domains = <&gcc USB30_PRIM_GDSC>;
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+ usb_1_dwc3: usb@a600000 {
+ compatible = "snps,dwc3";
+ reg = <0 0x0a600000 0 0xcd00>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x740 0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ phys = <&usb_1_hsphy>;
+ phy-names = "usb2-phy";
+ };
+ };
+
+ spmi_bus: spmi@c440000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0 0x0c440000 0 0x1100>,
+ <0 0x0c600000 0 0x2000000>,
+ <0 0x0e600000 0 0x100000>,
+ <0 0x0e700000 0 0xa0000>,
+ <0 0x0c40a000 0 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+
+ apps_smmu: iommu@15000000 {
+ /*
+ * The hardware tolerates the SDM845 reset quirk. The
+ * iommu maintainers aren't responding to any patches
+ * that would add support for new platforms. Set this
+ * compatible so this dtsi is valid and functional.
+ */
+ compatible = "qcom,sdm845-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+ reg = <0 0x15000000 0 0x80000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ apps_rsc: rsc@179c0000 {
+ label = "apps_rsc";
+ compatible = "qcom,rpmh-rsc";
+ reg = <0 0x179c0000 0 0x10000>,
+ <0 0x179d0000 0 0x10000>,
+ <0 0x179e0000 0 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 2>,
+ <SLEEP_TCS 3>,
+ <WAKE_TCS 3>,
+ <CONTROL_TCS 1>;
+
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,sdm670-rpmh-clk";
+ #clock-cells = <1>;
+ clock-names = "xo";
+ clocks = <&xo_board>;
+ };
+
+ rpmhpd: power-controller {
+ compatible = "qcom,sdm670-rpmhpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmhpd_opp_table>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp1 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ rpmhpd_opp_min_svs: opp2 {
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+
+ rpmhpd_opp_low_svs: opp3 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ rpmhpd_opp_svs: opp4 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ rpmhpd_opp_svs_l1: opp5 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ rpmhpd_opp_nom: opp6 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ rpmhpd_opp_nom_l1: opp7 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ rpmhpd_opp_nom_l2: opp8 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+ };
+
+ rpmhpd_opp_turbo: opp9 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ rpmhpd_opp_turbo_l1: opp10 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+ };
+ };
+ };
+
+ intc: interrupt-controller@17a00000 {
+ compatible = "arm,gic-v3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0 0x17a00000 0 0x10000>, /* GICD */
+ <0 0x17a60000 0 0x100000>; /* GICR * 8 */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+};
--
2.38.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 4/4] arm64: dts: qcom: add sdm670 and pixel 3a device trees
2022-11-01 23:57 ` [PATCH 4/4] arm64: dts: qcom: add sdm670 and pixel 3a device trees Richard Acayan
@ 2022-11-02 2:19 ` Richard Acayan
2022-11-02 20:26 ` Konrad Dybcio
` (2 subsequent siblings)
3 siblings, 0 replies; 16+ messages in thread
From: Richard Acayan @ 2022-11-02 2:19 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Robin Murphy, Chanho Park,
Thierry Reding, Stephan Gerhold, Lorenzo Pieralisi, Robert Marko,
Das Srinagesh, devicetree, linux-kernel, linux-arm-msm
On Tue, Nov 01, 2022 at 07:57:22PM -0400, Richard Acayan wrote:
> The Qualcomm Snapdragon 670 has been out for a while. Add a device tree
> for it and the Google Pixel 3a as the first device.
>
> The Pixel 3a has the same bootloader issue as the Pixel 3 and will not work
> on Android 10 bootloaders or later until it gets fixed for the Pixel 3.
>
> SoC Initial Features:
> - power management
> - clocks
> - pinctrl
> - eMMC
> - USB 2.0
> - GENI I2C
> - IOMMU
> - RPMh
> - interrupts
>
> Device-Specific Initial Features:
> - side buttons (keys)
> - regulators
> - touchscreen
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> .../boot/dts/qcom/sdm670-google-sargo.dts | 519 +++++++
> arch/arm64/boot/dts/qcom/sdm670.dtsi | 1216 +++++++++++++++++
> 3 files changed, 1736 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
> create mode 100644 arch/arm64/boot/dts/qcom/sdm670.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index b0558d3389e5..4eb5d8829efb 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -124,6 +124,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm632-fairphone-fp3.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
> diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
> new file mode 100644
> index 000000000000..fa3dee78e442
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
> @@ -0,0 +1,519 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device tree for Google Pixel 3a, adapted from google-blueline device tree,
> + * xiaomi-lavender device tree, and oneplus-common device tree.
> + *
> + * Copyright (c) 2022, Richard Acayan. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include "sdm670.dtsi"
> +#include "pm660.dtsi"
> +#include "pm660l.dtsi"
> +
> +/delete-node/ &mpss_region;
> +/delete-node/ &venus_mem;
> +/delete-node/ &wlan_msa_mem;
> +/delete-node/ &cdsp_mem;
> +/delete-node/ &mba_region;
> +/delete-node/ &adsp_mem;
> +/delete-node/ &ipa_fw_mem;
> +/delete-node/ &ipa_gsi_mem;
> +/delete-node/ &gpu_mem;
> +
> +/ {
> + model = "Google Pixel 3a";
> + compatible = "google,sargo", "qcom,sdm670";
> + qcom,board-id = <0x00041e05 0>;
> + qcom,msm-id = <321 0x20001>;
> +
> + aliases { };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + framebuffer@9c000000 {
> + compatible = "simple-framebuffer";
> + reg = <0x0 0x9c000000 0x0 (1080 * 2220 * 4)>;
> + width = <1080>;
> + height = <2220>;
> + stride = <(1080 * 4)>;
> + format = "a8r8g8b8";
> + };
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + mpss_region: mpss@8b000000 {
> + reg = <0 0x8b000000 0 0x9800000>;
> + no-map;
> + };
> +
> + venus_mem: venus@94800000 {
> + reg = <0 0x94800000 0 0x500000>;
> + no-map;
> + };
> +
> + wlan_msa_mem: wlan-msa@94d00000 {
> + reg = <0 0x94d00000 0 0x100000>;
> + no-map;
> + };
> +
> + cdsp_mem: cdsp@94e00000 {
> + reg = <0 0x94e00000 0 0x800000>;
> + no-map;
> + };
> +
> + mba_region: mba@95600000 {
> + reg = <0 0x95600000 0 0x200000>;
> + no-map;
> + };
> +
> + adsp_mem: adsp@95800000 {
> + reg = <0 0x95800000 0 0x2200000>;
> + no-map;
> + };
> +
> + ipa_fw_mem: ipa-fw@97a00000 {
> + reg = <0 0x97a00000 0 0x10000>;
> + no-map;
> + };
> +
> + ipa_gsi_mem: ipa-gsi@97a10000 {
> + reg = <0 0x97a10000 0 0x5000>;
> + no-map;
> + };
> +
> + gpu_mem: gpu@97a15000 {
> + reg = <0 0x97a15000 0 0x2000>;
> + no-map;
> + };
> +
> + framebuffer-region@9c000000 {
> + reg = <0 0x9c000000 0 0x2400000>;
> + no-map;
> + };
> +
> + /* Also includes ramoops regions */
> + debug_info_mem: debug-info@a1800000 {
> + reg = <0 0xa1800000 0 0x411000>;
> + no-map;
> + };
> + };
> +
> + /*
> + * Supply map from xiaomi-lavender specifies this as the supply for
> + * ldob1, ldob9, ldob10, ldoa2, and ldoa3, while downstream specifies
> + * this as a power domain. Set this as a fixed regulator with the same
> + * voltage as lavender until display is needed to avoid unneccessarily
> + * using a deprecated binding (regulator-fixed-domain).
> + */
> + vreg_s2b_1p05: vreg-s2b-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vreg_s2b";
> + regulator-min-microvolt = <1050000>;
> + regulator-max-microvolt = <1050000>;
> + };
> +
> + vph_pwr: vph-pwr-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vph_pwr";
> + regulator-min-microvolt = <3312000>;
> + regulator-max-microvolt = <3312000>;
> +
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + autorepeat;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&vol_up_pin>;
> +
> + key-vol-up {
> + label = "Volume Up";
> + linux,code = <KEY_VOLUMEUP>;
> + gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>;
> + };
> + };
> +
> + /*
> + * The touchscreen regulator seems to be controlled somehow by a gpio.
> + * Model it as a fixed regulator and keep it on. Without schematics we
> + * don't know how this is actually wired up...
> + */
> + ts_1p8_supply: ts-1p8-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "ts_1p8_supply";
> +
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> +
> + gpio = <&pm660_gpios 12 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +};
> +
> +&apps_rsc {
> + pm660l-regulators {
> + compatible = "qcom,pm660l-rpmh-regulators";
> + qcom,pmic-id = "b";
> +
> + vdd-s1-supply = <&vph_pwr>;
> + vdd-s2-supply = <&vph_pwr>;
> + vdd-s3-s4-supply = <&vph_pwr>;
> + vdd-s5-supply = <&vph_pwr>;
> +
> + vdd-l1-l9-l10-supply = <&vreg_s2b_1p05>;
> + vdd-l2-supply = <&vreg_bob>;
> + vdd-l3-l5-l7-l8-supply = <&vreg_bob>;
> + vdd-l4-l6-supply = <&vreg_bob>;
> + vdd-bob-supply = <&vph_pwr>;
> +
> + /* LDOs */
> + vreg_l1b_0p89: ldo1 {
Oh, I should change these names back, since PM660(L) device trees put
the same voltage in the name no matter what. This was originally the
average of the minimum and maximum.
vreg_l1b_0p925
> + regulator-min-microvolt = <880000>;
> + regulator-max-microvolt = <900000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l2b_2p38: ldo2 {
vreg_l2b_2p95
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <2960000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l3b_2p93: ldo3 {
vreg_l3b_3p0
> + regulator-min-microvolt = <2850000>;
> + regulator-max-microvolt = <3008000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l4b_2p96: ldo4 {
vreg_l4b_2p95
> + regulator-min-microvolt = <2960000>;
> + regulator-max-microvolt = <2960000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l5b_2p96: ldo5 {
vreg_l5b_2p95
> + regulator-min-microvolt = <2960000>;
> + regulator-max-microvolt = <2960000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l6b_3p15: ldo6 {
vreg_l6b_3p3
> + regulator-min-microvolt = <3008000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l7b_3p1: ldo7 {
vreg_l7b_3p125
> + regulator-min-microvolt = <3088000>;
> + regulator-max-microvolt = <3100000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l8b_3p3: ldo8 {
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3312000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + /*
> + * Downstream specifies a fixed voltage of 3.312 V, but the
> + * PMIC4 BOB ranges don't support that. Widen the range a
> + * little to avoid adding a new BOB regulator type.
> + */
> + vreg_bob: bob {
> + regulator-min-microvolt = <3296000>;
> + regulator-max-microvolt = <3328000>;
> + regulator-enable-ramp-delay = <500>;
> + };
> + };
> +
> + pm660-regulators {
> + compatible = "qcom,pm660-rpmh-regulators";
> + qcom,pmic-id = "a";
> +
> + vdd-s1-supply = <&vph_pwr>;
> + vdd-s2-supply = <&vph_pwr>;
> + vdd-s3-supply = <&vph_pwr>;
> + vdd-s4-supply = <&vph_pwr>;
> + vdd-s5-supply = <&vph_pwr>;
> + vdd-s6-supply = <&vph_pwr>;
> +
> + vdd-l1-l6-l7-supply = <&vreg_s6a_1p29>;
> + vdd-l2-l3-supply = <&vreg_s2b_1p05>;
> + vdd-l5-supply = <&vreg_s2b_1p05>;
> + vdd-l8-l9-l10-l11-l12-l13-l14-supply = <&vreg_s4a_1p92>;
> + vdd-l15-l16-l17-l18-l19-supply = <&vreg_bob>;
> +
> + /*
> + * S1A (FTAPC0), S2A (FTAPC1), S3A (HFAPC1) are managed
> + * by the Core Power Reduction hardened (CPRh) and the
> + * Operating State Manager (OSM) HW automatically.
> + */
> +
> + vreg_s4a_1p92: smps4 {
vreg_s4a_2p04
> + regulator-min-microvolt = <1808000>;
> + regulator-max-microvolt = <2040000>;
> + regulator-enable-ramp-delay = <200>;
> + };
> +
> + vreg_s6a_1p29: smps6 {
vreg_s6a_0p87
What? This is a big difference.
> + regulator-min-microvolt = <1224000>;
> + regulator-max-microvolt = <1352000>;
> + regulator-enable-ramp-delay = <150>;
> + };
> +
> + /* LDOs */
> + vreg_l1a_1p225: ldo1 {
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1250000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l2a_1p0: ldo2 {
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l3a_1p0: ldo3 {
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l5a_0p8: ldo5 {
vreg_l5a_0p848
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l6a_1p28: ldo6 {
vreg_l6a_1p3
> + regulator-min-microvolt = <1248000>;
> + regulator-max-microvolt = <1304000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l7a_1p2: ldo7 {
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l8a_1p8: ldo8 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l9a_1p8: ldo9 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l10a_1p8: ldo10 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l11a_1p8: ldo11 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l12a_1p8: ldo12 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l13a_1p8: ldo13 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l14a_1p8: ldo14 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l15a_2p38: ldo15 {
vreg_l15a_1p8
Unlike when I made the comment above, this seems normal.
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <2950000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l16a_2p7: ldo16 {
> + regulator-min-microvolt = <2696000>;
> + regulator-max-microvolt = <2696000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l17a_2p38: ldo17 {
vreg_l17a_1p8
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <2950000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l19a_3p3: ldo19 {
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3312000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> + };
> +};
> +
> +&gpi_dma1 {
> + status = "okay";
> +};
> +
> +&qupv3_id_1 {
> + status = "okay";
> +};
> +
> +&i2c9 {
> + status = "okay";
> + clock-frequency = <100000>;
> +
> + synaptics-rmi4-i2c@20 {
> + compatible = "syna,rmi4-i2c";
> + reg = <0x20>;
> + #address-cells = <0x1>;
> + #size-cells = <0x0>;
> + interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&touchscreen_default>;
> +
> + /* VDD supply isn't specified, bind it to power */
Hmm, maybe I should use a fixed regulator instead, or maybe there's a
regulator that this really needs.
> + vdd-supply = <&vph_pwr>;
> + vio-supply = <&ts_1p8_supply>;
> +
> + syna,reset-delay-ms = <200>;
> + syna,startup-delay-ms = <200>;
> +
> + rmi4-f01@1 {
> + reg = <0x01>;
> + syna,nosleep-mode = <1>;
> + };
> +
> + rmi4-f12@12 {
> + reg = <0x12>;
> + touchscreen-x-mm = <62>;
> + touchscreen-y-mm = <127>;
> + syna,sensor-type = <1>;
> + };
> + };
> +};
> +
> +&gcc {
> + protected-clocks = <GCC_QSPI_CORE_CLK>,
> + <GCC_QSPI_CORE_CLK_SRC>,
> + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>;
> +};
> +
> +&pm660l_gpios {
> + vol_up_pin: vol-up-state {
> + pins = "gpio7";
> + function = "normal";
> + qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
> + input-enable;
> + bias-pull-up;
> + };
> +};
> +
> +&pon_pwrkey {
> + status = "okay";
> +};
> +
> +&pon_resin {
> + status = "okay";
> + linux,code = <KEY_VOLUMEDOWN>;
> +};
> +
> +&sdhc_1 {
> + status = "okay";
> + supports-cqe;
> + mmc-hs200-1_8v;
> + mmc-hs400-1_8v;
> + mmc-ddr-1_8v;
> +
> + qcom,ddr-config = <0xc3040873>;
> +
> + vmmc-supply = <&vreg_l4b_2p96>;
> + vqmmc-supply = <&vreg_l8a_1p8>;
> +};
> +
> +&tlmm {
> + gpio-reserved-ranges = <0 4>, <81 4>;
> +
> + touchscreen_default: ts-default-state {
> + ts-reset-pins {
> + pins = "gpio99";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + output-high;
> + };
> +
> + ts-irq-pins {
> + pins = "gpio125";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + ts-switch-pins {
> + pins = "gpio135";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + output-low;
> + };
> + };
> +};
> +
> +&usb_1_hsphy {
> + status = "okay";
> +
> + vdd-supply = <&vreg_l1b_0p89>;
> + vdda-pll-supply = <&vreg_l10a_1p8>;
> + vdda-phy-dpdm-supply = <&vreg_l7b_3p1>;
> +};
> +
> +&usb_1 {
> + status = "okay";
> +
> + qcom,select-utmi-as-pipe-clk;
> +};
> +
> +&usb_1_dwc3 {
> + /* Only peripheral works for now */
> + dr_mode = "peripheral";
> +
> + /* Do not assume that sdm670.dtsi will never support USB 3.0 */
> + phys = <&usb_1_hsphy>;
> + phy-names = "usb2-phy";
> + maximum-speed = "high-speed";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
> new file mode 100644
> index 000000000000..4450ece839a0
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
> @@ -0,0 +1,1216 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SDM670 SoC device tree source, adapted from SDM845 SoC device tree
> + *
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2022, Richard Acayan. All rights reserved.
> + */
> +
> +#include <dt-bindings/clock/qcom,gcc-sdm845.h>
> +#include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/dma/qcom-gpi.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/phy/phy-qcom-qusb2.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases { };
> +
> + chosen { };
> +
> + memory@80000000 {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the size */
> + reg = <0 0x80000000 0 0>;
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + hyp_mem: hyp-mem@85700000 {
> + reg = <0 0x85700000 0 0x600000>;
> + no-map;
> + };
> +
> + xbl_mem: xbl-mem@85e00000 {
> + reg = <0 0x85e00000 0 0x100000>;
> + no-map;
> + };
> +
> + aop_mem: aop-mem@85fc0000 {
> + reg = <0 0x85fc0000 0 0x20000>;
> + no-map;
> + };
> +
> + aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
> + compatible = "qcom,cmd-db";
> + reg = <0x0 0x85fe0000 0 0x20000>;
> + no-map;
> + };
> +
> + camera_mem: camera-mem@8ab00000 {
> + reg = <0 0x8ab00000 0 0x500000>;
> + no-map;
> + };
> +
> + mpss_region: mpss@8b000000 {
> + reg = <0 0x8b000000 0 0x7e00000>;
> + no-map;
> + };
> +
> + venus_mem: venus@92e00000 {
> + reg = <0 0x92e00000 0 0x500000>;
> + no-map;
> + };
> +
> + wlan_msa_mem: wlan-msa@93300000 {
> + reg = <0 0x93300000 0 0x100000>;
> + no-map;
> + };
> +
> + cdsp_mem: cdsp@93400000 {
> + reg = <0 0x93400000 0 0x800000>;
> + no-map;
> + };
> +
> + mba_region: mba@93c00000 {
> + reg = <0 0x93c00000 0 0x200000>;
> + no-map;
> + };
> +
> + adsp_mem: adsp@93e00000 {
> + reg = <0 0x93e00000 0 0x1e00000>;
> + no-map;
> + };
> +
> + ipa_fw_mem: ipa-fw@95c00000 {
> + reg = <0 0x95c00000 0 0x10000>;
> + no-map;
> + };
> +
> + ipa_gsi_mem: ipa-gsi@95c10000 {
> + reg = <0 0x95c10000 0 0x5000>;
> + no-map;
> + };
> +
> + gpu_mem: gpu@95c15000 {
> + reg = <0 0x95c15000 0 0x2000>;
> + no-map;
> + };
> +
> + spss_mem: spss@97b00000 {
> + reg = <0 0x97b00000 0 0x100000>;
> + no-map;
> + };
> +
> + qseecom_mem: qseecom@9e400000 {
> + reg = <0 0x9e400000 0 0x1400000>;
> + no-map;
> + };
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD0>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_0>;
> + L2_0: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + L3_0: l3-cache {
> + compatible = "cache";
> + };
> + };
> + };
> +
> + CPU1: cpu@100 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD1>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_100>;
> + L2_100: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU2: cpu@200 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x200>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD2>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_200>;
> + L2_200: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU3: cpu@300 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x300>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD3>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_300>;
> + L2_300: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU4: cpu@400 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x400>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD4>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_400>;
> + L2_400: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU5: cpu@500 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x500>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD5>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_500>;
> + L2_500: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU6: cpu@600 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x600>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD6>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_600>;
> + L2_600: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU7: cpu@700 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x700>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD7>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_700>;
> + L2_700: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&CPU0>;
> + };
> +
> + core1 {
> + cpu = <&CPU1>;
> + };
> +
> + core2 {
> + cpu = <&CPU2>;
> + };
> +
> + core3 {
> + cpu = <&CPU3>;
> + };
> +
> + core4 {
> + cpu = <&CPU4>;
> + };
> +
> + core5 {
> + cpu = <&CPU5>;
> + };
> +
> + core6 {
> + cpu = <&CPU6>;
> + };
> +
> + core7 {
> + cpu = <&CPU7>;
> + };
> + };
> + };
> +
> + idle-states {
> + entry-method = "psci";
> +
> + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
> + compatible = "arm,idle-state";
> + idle-state-name = "little-rail-power-collapse";
> + arm,psci-suspend-param = <0x40000004>;
> + entry-latency-us = <702>;
> + exit-latency-us = <915>;
> + min-residency-us = <1617>;
> + local-timer-stop;
> + };
> +
> + BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
> + compatible = "arm,idle-state";
> + idle-state-name = "big-rail-power-collapse";
> + arm,psci-suspend-param = <0x40000004>;
> + entry-latency-us = <526>;
> + exit-latency-us = <1854>;
> + min-residency-us = <2380>;
> + local-timer-stop;
> + };
> + };
> +
> + domain-idle-states {
> + CLUSTER_SLEEP_0: cluster-sleep-0 {
> + compatible = "domain-idle-state";
> + arm,psci-suspend-param = <0x4100c244>;
> + entry-latency-us = <3263>;
> + exit-latency-us = <6562>;
> + min-residency-us = <9825>;
> + };
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + clocks {
> + xo_board: xo-board {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <38400000>;
> + clock-output-names = "xo_board";
> + };
> +
> + sleep_clk: sleep-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32764>;
> + };
> + };
> +
> + firmware {
> + scm {
> + compatible = "qcom,scm-sdm670", "qcom,scm";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> +
> + CPU_PD0: power-domain-cpu0 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD1: power-domain-cpu1 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD2: power-domain-cpu2 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD3: power-domain-cpu3 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD4: power-domain-cpu4 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD5: power-domain-cpu5 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD6: power-domain-cpu6 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD7: power-domain-cpu7 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
> + };
> +
> + CLUSTER_PD: power-domain-cluster {
> + #power-domain-cells = <0>;
> + domain-idle-states = <&CLUSTER_SLEEP_0>;
> + };
> + };
> +
> + soc: soc@0 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0 0 0 0 0x10 0>;
> + dma-ranges = <0 0 0 0 0x10 0>;
> + compatible = "simple-bus";
> +
> + gcc: clock-controller@100000 {
> + compatible = "qcom,gcc-sdm670";
> + reg = <0 0x00100000 0 0x1f0000>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&rpmhcc RPMH_CXO_CLK_A>,
> + <&sleep_clk>;
> + clock-names = "bi_tcxo",
> + "bi_tcxo_ao",
> + "sleep_clk";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> + sdhc_1: mmc@7c4000 {
> + compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0 0x007c4000 0 0x1000>,
> + <0 0x007c5000 0 0x1000>,
> + <0 0x007c8000 0 0x8000>;
> + reg-names = "hc", "cqhci", "ice";
> +
> + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> + <&gcc GCC_SDCC1_APPS_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_SDCC1_ICE_CORE_CLK>,
> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
> + clock-names = "iface", "core", "xo", "ice", "bus";
> +
> + iommus = <&apps_smmu 0x140 0xf>;
> +
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&sdc1_state_on>;
> + pinctrl-1 = <&sdc1_state_off>;
> + power-domains = <&rpmhpd SDM670_CX>;
> +
> + bus-width = <8>;
> + non-removable;
> +
> + status = "disabled";
> + };
> +
> + gpi_dma0: dma-controller@800000 {
> + #dma-cells = <3>;
> + compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
> + reg = <0 0x00800000 0 0x60000>;
> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
> + dma-channels = <13>;
> + dma-channel-mask = <0xfa>;
> + iommus = <&apps_smmu 0x0016 0x0>;
> + status = "disabled";
> + };
> +
> + qupv3_id_0: geniqup@8c0000 {
> + compatible = "qcom,geni-se-qup";
> + reg = <0 0x008c0000 0 0x6000>;
> + clock-names = "m-ahb", "s-ahb";
> + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
> + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
> + iommus = <&apps_smmu 0x3 0x0>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
> + interconnect-names = "qup-core";
> + status = "disabled";
> +
> + i2c0: i2c@880000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00880000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c0_default>;
> + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 0 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c1: i2c@884000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00884000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c1_default>;
> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 1 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c2: i2c@888000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00888000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c2_default>;
> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 2 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c3: i2c@88c000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x0088c000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c3_default>;
> + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 3 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c4: i2c@890000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00890000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c4_default>;
> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 4 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c5: i2c@894000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00894000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c5_default>;
> + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 5 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c6: i2c@898000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00898000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c6_default>;
> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 6 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c7: i2c@89c000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x0089c000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c7_default>;
> + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 7 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> + };
> +
> + gpi_dma1: dma-controller@a00000 {
> + #dma-cells = <3>;
> + compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
> + reg = <0 0x00a00000 0 0x60000>;
> + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
> + dma-channels = <13>;
> + dma-channel-mask = <0xfa>;
> + iommus = <&apps_smmu 0x06d6 0x0>;
> + status = "disabled";
> + };
> +
> + qupv3_id_1: geniqup@ac0000 {
> + compatible = "qcom,geni-se-qup";
> + reg = <0 0x00ac0000 0 0x6000>;
> + clock-names = "m-ahb", "s-ahb";
> + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
> + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> + iommus = <&apps_smmu 0x6c3 0x0>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + i2c8: i2c@a80000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a80000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c8_default>;
> + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 0 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c9: i2c@a84000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a84000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c9_default>;
> + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 1 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c10: i2c@a88000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a88000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c10_default>;
> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 2 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c11: i2c@a8c000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a8c000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c11_default>;
> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 3 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c12: i2c@a90000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a90000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c12_default>;
> + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 4 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c13: i2c@a94000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a94000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c13_default>;
> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 5 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c14: i2c@a98000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a98000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c14_default>;
> + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 6 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c15: i2c@a9c000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a9c000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c15_default>;
> + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 7 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> + };
> +
> + tlmm: pinctrl@3400000 {
> + compatible = "qcom,sdm670-tlmm";
> + reg = <0 0x03400000 0 0xc00000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-ranges = <&tlmm 0 0 151>;
> +
> + qup_i2c0_default: qup-i2c0-default-state {
> + pins = "gpio0", "gpio1";
> + function = "qup0";
> + };
> +
> + qup_i2c1_default: qup-i2c1-default-state {
> + pins = "gpio17", "gpio18";
> + function = "qup1";
> + };
> +
> + qup_i2c2_default: qup-i2c2-default-state {
> + pins = "gpio27", "gpio28";
> + function = "qup2";
> + };
> +
> + qup_i2c3_default: qup-i2c3-default-state {
> + pins = "gpio41", "gpio42";
> + function = "qup3";
> + };
> +
> + qup_i2c4_default: qup-i2c4-default-state {
> + pins = "gpio89", "gpio90";
> + function = "qup4";
> + };
> +
> + qup_i2c5_default: qup-i2c5-default-state {
> + pins = "gpio85", "gpio86";
> + function = "qup5";
> + };
> +
> + qup_i2c6_default: qup-i2c6-default-state {
> + pins = "gpio45", "gpio46";
> + function = "qup6";
> + };
> +
> + qup_i2c7_default: qup-i2c7-default-state {
> + pins = "gpio93", "gpio94";
> + function = "qup7";
> + };
> +
> + qup_i2c8_default: qup-i2c8-default-state {
> + pins = "gpio65", "gpio66";
> + function = "qup8";
> + };
> +
> + qup_i2c9_default: qup-i2c9-default-state {
> + pins = "gpio6", "gpio7";
> + function = "qup9";
> + };
> +
> + qup_i2c10_default: qup-i2c10-default-state {
> + pins = "gpio55", "gpio56";
> + function = "qup10";
> + };
> +
> + qup_i2c11_default: qup-i2c11-default-state {
> + pins = "gpio31", "gpio32";
> + function = "qup11";
> + };
> +
> + qup_i2c12_default: qup-i2c12-default-state {
> + pins = "gpio49", "gpio50";
> + function = "qup12";
> + };
> +
> + qup_i2c13_default: qup-i2c13-default-state {
> + pins = "gpio105", "gpio106";
> + function = "qup13";
> + };
> +
> + qup_i2c14_default: qup-i2c14-default-state {
> + pins = "gpio33", "gpio34";
> + function = "qup14";
> + };
> +
> + qup_i2c15_default: qup-i2c15-default-state {
> + pins = "gpio81", "gpio82";
> + function = "qup15";
> + };
> +
> + sdc1_state_on: sdc1-on-state {
> + clk-pins {
> + pins = "sdc1_clk";
> + bias-disable;
> + drive-strength = <16>;
> + };
> +
> + cmd-pins {
> + pins = "sdc1_cmd";
> + bias-pull-up;
> + drive-strength = <10>;
> + };
> +
> + data-pins {
> + pins = "sdc1_data";
> + bias-pull-up;
> + drive-strength = <10>;
> + };
> +
> + rclk-pins {
> + pins = "sdc1_rclk";
> + bias-pull-down;
> + };
> + };
> +
> + sdc1_state_off: sdc1-off-state {
> + clk-pins {
> + pins = "sdc1_clk";
> + bias-disable;
> + drive-strength = <2>;
> + };
> +
> + cmd-pins {
> + pins = "sdc1_cmd";
> + bias-pull-up;
> + drive-strength = <2>;
> + };
> +
> + data-pins {
> + pins = "sdc1_data";
> + bias-pull-up;
> + drive-strength = <2>;
> + };
> +
> + rclk-pins {
> + pins = "sdc1_rclk";
> + bias-pull-down;
> + };
> + };
> + };
> +
> + usb_1_hsphy: phy@88e2000 {
> + compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy";
> + reg = <0 0x088e2000 0 0x400>;
> + status = "disabled";
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "cfg_ahb", "ref";
> +
> + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> + };
> +
> + usb_1: usb@a6f8800 {
> + compatible = "qcom,sdm670-dwc3", "qcom,dwc3";
> + reg = <0 0x0a6f8800 0 0x400>;
> + status = "disabled";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + dma-ranges;
> +
> + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_MASTER_CLK>,
> + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
> + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
> + clock-names = "cfg_noc",
> + "core",
> + "iface",
> + "sleep",
> + "mock_utmi";
> +
> + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB30_PRIM_MASTER_CLK>;
> + assigned-clock-rates = <19200000>, <150000000>;
> +
> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hs_phy_irq", "ss_phy_irq",
> + "dm_hs_phy_irq", "dp_hs_phy_irq";
> +
> + power-domains = <&gcc USB30_PRIM_GDSC>;
> +
> + resets = <&gcc GCC_USB30_PRIM_BCR>;
> +
> + usb_1_dwc3: usb@a600000 {
> + compatible = "snps,dwc3";
> + reg = <0 0x0a600000 0 0xcd00>;
> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> + iommus = <&apps_smmu 0x740 0>;
> + snps,dis_u2_susphy_quirk;
> + snps,dis_enblslpm_quirk;
> + phys = <&usb_1_hsphy>;
> + phy-names = "usb2-phy";
> + };
> + };
> +
> + spmi_bus: spmi@c440000 {
> + compatible = "qcom,spmi-pmic-arb";
> + reg = <0 0x0c440000 0 0x1100>,
> + <0 0x0c600000 0 0x2000000>,
> + <0 0x0e600000 0 0x100000>,
> + <0 0x0e700000 0 0xa0000>,
> + <0 0x0c40a000 0 0x26000>;
> + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> + interrupt-names = "periph_irq";
> + interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
> + qcom,ee = <0>;
> + qcom,channel = <0>;
> + #address-cells = <2>;
> + #size-cells = <0>;
> + interrupt-controller;
> + #interrupt-cells = <4>;
> + };
> +
> + apps_smmu: iommu@15000000 {
> + /*
> + * The hardware tolerates the SDM845 reset quirk. The
> + * iommu maintainers aren't responding to any patches
> + * that would add support for new platforms. Set this
> + * compatible so this dtsi is valid and functional.
> + */
> + compatible = "qcom,sdm845-smmu-500", "qcom,smmu-500", "arm,mmu-500";
> + reg = <0 0x15000000 0 0x80000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <1>;
> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + apps_rsc: rsc@179c0000 {
> + label = "apps_rsc";
> + compatible = "qcom,rpmh-rsc";
> + reg = <0 0x179c0000 0 0x10000>,
> + <0 0x179d0000 0 0x10000>,
> + <0 0x179e0000 0 0x10000>;
> + reg-names = "drv-0", "drv-1", "drv-2";
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + qcom,tcs-offset = <0xd00>;
> + qcom,drv-id = <2>;
> + qcom,tcs-config = <ACTIVE_TCS 2>,
> + <SLEEP_TCS 3>,
> + <WAKE_TCS 3>,
> + <CONTROL_TCS 1>;
> +
> + apps_bcm_voter: bcm-voter {
> + compatible = "qcom,bcm-voter";
> + };
> +
> + rpmhcc: clock-controller {
> + compatible = "qcom,sdm670-rpmh-clk";
> + #clock-cells = <1>;
> + clock-names = "xo";
> + clocks = <&xo_board>;
> + };
> +
> + rpmhpd: power-controller {
> + compatible = "qcom,sdm670-rpmhpd";
> + #power-domain-cells = <1>;
> + operating-points-v2 = <&rpmhpd_opp_table>;
> +
> + rpmhpd_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + rpmhpd_opp_ret: opp1 {
> + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
> + };
> +
> + rpmhpd_opp_min_svs: opp2 {
> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> + };
> +
> + rpmhpd_opp_low_svs: opp3 {
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + };
> +
> + rpmhpd_opp_svs: opp4 {
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> + };
> +
> + rpmhpd_opp_svs_l1: opp5 {
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> + };
> +
> + rpmhpd_opp_nom: opp6 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> + };
> +
> + rpmhpd_opp_nom_l1: opp7 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> + };
> +
> + rpmhpd_opp_nom_l2: opp8 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
> + };
> +
> + rpmhpd_opp_turbo: opp9 {
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> + };
> +
> + rpmhpd_opp_turbo_l1: opp10 {
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> + };
> + };
> + };
> + };
> +
> + intc: interrupt-controller@17a00000 {
> + compatible = "arm,gic-v3";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0 0x17a00000 0 0x10000>, /* GICD */
> + <0 0x17a60000 0 0x100000>; /* GICR * 8 */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +};
> --
> 2.38.1
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/4] dt-bindings: arm: cpus: add qcom kryo 360 compatible
2022-11-01 23:57 ` [PATCH 1/4] dt-bindings: arm: cpus: add qcom kryo 360 compatible Richard Acayan
@ 2022-11-02 17:36 ` Rob Herring
0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2022-11-02 17:36 UTC (permalink / raw)
To: Richard Acayan
Cc: devicetree, Robin Murphy, Thierry Reding,
~postmarketos/upstreaming, Andy Gross, Vinod Koul, Konrad Dybcio,
linux-kernel, Robert Marko, Chanho Park, Das Srinagesh,
Rob Herring, Lorenzo Pieralisi, Stephan Gerhold, linux-arm-msm,
phone-devel, Bjorn Andersson, Krzysztof Kozlowski
On Tue, 01 Nov 2022 19:57:19 -0400, Richard Acayan wrote:
> The Snapdragon 670 uses CPUs named Kryo 360 silver and Kryo 360 gold.
> Add the compatible string in the documentation.
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
> Documentation/devicetree/bindings/arm/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/4] dt-bindings: arm: qcom: add sdm670 and pixel 3a compatible
2022-11-01 23:57 ` [PATCH 2/4] dt-bindings: arm: qcom: add sdm670 and pixel 3a compatible Richard Acayan
@ 2022-11-02 17:37 ` Rob Herring
0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2022-11-02 17:37 UTC (permalink / raw)
To: Richard Acayan
Cc: linux-arm-msm, Stephan Gerhold, Bjorn Andersson,
~postmarketos/upstreaming, Andy Gross, Konrad Dybcio,
Rob Herring, Chanho Park, Vinod Koul, Robin Murphy,
Lorenzo Pieralisi, phone-devel, Thierry Reding,
Krzysztof Kozlowski, linux-kernel, Das Srinagesh, devicetree,
Robert Marko
On Tue, 01 Nov 2022 19:57:20 -0400, Richard Acayan wrote:
> The Snapdragon 670 and Pixel 3a initial device trees are about to be
> added. Add the compatible strings for the board.
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
> Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/4] dt-bindings: firmware: scm: add sdm670 compatible
2022-11-01 23:57 ` [PATCH 3/4] dt-bindings: firmware: scm: add sdm670 compatible Richard Acayan
@ 2022-11-02 17:37 ` Rob Herring
2022-11-02 17:51 ` Guru Das Srinagesh
1 sibling, 0 replies; 16+ messages in thread
From: Rob Herring @ 2022-11-02 17:37 UTC (permalink / raw)
To: Richard Acayan
Cc: Krzysztof Kozlowski, devicetree, Stephan Gerhold, Das Srinagesh,
linux-arm-msm, phone-devel, ~postmarketos/upstreaming,
Lorenzo Pieralisi, Thierry Reding, Rob Herring, Robert Marko,
Andy Gross, Chanho Park, linux-kernel, Konrad Dybcio,
Bjorn Andersson, Vinod Koul, Robin Murphy
On Tue, 01 Nov 2022 19:57:21 -0400, Richard Acayan wrote:
> The Snapdragon 670 uses SCM as for PSCI power management. Document the
> appropriate compatible string for it.
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
> Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/4] dt-bindings: firmware: scm: add sdm670 compatible
2022-11-01 23:57 ` [PATCH 3/4] dt-bindings: firmware: scm: add sdm670 compatible Richard Acayan
2022-11-02 17:37 ` Rob Herring
@ 2022-11-02 17:51 ` Guru Das Srinagesh
1 sibling, 0 replies; 16+ messages in thread
From: Guru Das Srinagesh @ 2022-11-02 17:51 UTC (permalink / raw)
To: Richard Acayan
Cc: Rob Herring, Krzysztof Kozlowski, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Robin Murphy, Chanho Park,
Thierry Reding, Stephan Gerhold, Lorenzo Pieralisi, Robert Marko,
devicetree, linux-kernel, linux-arm-msm,
~postmarketos/upstreaming, phone-devel
On Nov 01 2022 19:57, Richard Acayan wrote:
> The Snapdragon 670 uses SCM as for PSCI power management. Document the
> appropriate compatible string for it.
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Guru Das Srinagesh <quic_gurus@quicinc.com>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 4/4] arm64: dts: qcom: add sdm670 and pixel 3a device trees
2022-11-01 23:57 ` [PATCH 4/4] arm64: dts: qcom: add sdm670 and pixel 3a device trees Richard Acayan
2022-11-02 2:19 ` Richard Acayan
@ 2022-11-02 20:26 ` Konrad Dybcio
2022-11-02 20:30 ` Krzysztof Kozlowski
2022-11-03 0:53 ` Richard Acayan
2022-11-03 1:19 ` Richard Acayan
2022-11-03 20:34 ` kernel test robot
3 siblings, 2 replies; 16+ messages in thread
From: Konrad Dybcio @ 2022-11-02 20:26 UTC (permalink / raw)
To: Richard Acayan, Rob Herring, Krzysztof Kozlowski, Andy Gross,
Bjorn Andersson, Vinod Koul, Robin Murphy, Chanho Park,
Thierry Reding, Stephan Gerhold, Lorenzo Pieralisi, Robert Marko,
Das Srinagesh, devicetree, linux-kernel, linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel
On 02/11/2022 00:57, Richard Acayan wrote:
> The Qualcomm Snapdragon 670 has been out for a while. Add a device tree
> for it and the Google Pixel 3a as the first device.
>
> The Pixel 3a has the same bootloader issue as the Pixel 3 and will not work
> on Android 10 bootloaders or later until it gets fixed for the Pixel 3.
>
> SoC Initial Features:
> - power management
> - clocks
> - pinctrl
> - eMMC
> - USB 2.0
> - GENI I2C
> - IOMMU
> - RPMh
> - interrupts
>
> Device-Specific Initial Features:
> - side buttons (keys)
> - regulators
> - touchscreen
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> .../boot/dts/qcom/sdm670-google-sargo.dts | 519 +++++++
> arch/arm64/boot/dts/qcom/sdm670.dtsi | 1216 +++++++++++++++++
> 3 files changed, 1736 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
> create mode 100644 arch/arm64/boot/dts/qcom/sdm670.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index b0558d3389e5..4eb5d8829efb 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -124,6 +124,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm632-fairphone-fp3.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
> diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
> new file mode 100644
> index 000000000000..fa3dee78e442
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
> @@ -0,0 +1,519 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device tree for Google Pixel 3a, adapted from google-blueline device tree,
> + * xiaomi-lavender device tree, and oneplus-common device tree.
> + *
> + * Copyright (c) 2022, Richard Acayan. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include "sdm670.dtsi"
> +#include "pm660.dtsi"
> +#include "pm660l.dtsi"
> +
> +/delete-node/ &mpss_region;
> +/delete-node/ &venus_mem;
> +/delete-node/ &wlan_msa_mem;
> +/delete-node/ &cdsp_mem;
> +/delete-node/ &mba_region;
> +/delete-node/ &adsp_mem;
> +/delete-node/ &ipa_fw_mem;
> +/delete-node/ &ipa_gsi_mem;
> +/delete-node/ &gpu_mem;
> +
> +/ {
> + model = "Google Pixel 3a";
> + compatible = "google,sargo", "qcom,sdm670";
> + qcom,board-id = <0x00041e05 0>;
> + qcom,msm-id = <321 0x20001>;
> +
> + aliases { };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + framebuffer@9c000000 {
> + compatible = "simple-framebuffer";
> + reg = <0x0 0x9c000000 0x0 (1080 * 2220 * 4)>;
> + width = <1080>;
> + height = <2220>;
> + stride = <(1080 * 4)>;
> + format = "a8r8g8b8";
> + };
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + mpss_region: mpss@8b000000 {
Please call the nodes memory@
> + reg = <0 0x8b000000 0 0x9800000>;
> + no-map;
> + };
> +
> + venus_mem: venus@94800000 {
> + reg = <0 0x94800000 0 0x500000>;
> + no-map;
> + };
> +
> + wlan_msa_mem: wlan-msa@94d00000 {
> + reg = <0 0x94d00000 0 0x100000>;
> + no-map;
> + };
> +
> + cdsp_mem: cdsp@94e00000 {
> + reg = <0 0x94e00000 0 0x800000>;
> + no-map;
> + };
> +
> + mba_region: mba@95600000 {
> + reg = <0 0x95600000 0 0x200000>;
> + no-map;
> + };
> +
> + adsp_mem: adsp@95800000 {
> + reg = <0 0x95800000 0 0x2200000>;
> + no-map;
> + };
> +
> + ipa_fw_mem: ipa-fw@97a00000 {
> + reg = <0 0x97a00000 0 0x10000>;
> + no-map;
> + };
> +
> + ipa_gsi_mem: ipa-gsi@97a10000 {
> + reg = <0 0x97a10000 0 0x5000>;
> + no-map;
> + };
> +
> + gpu_mem: gpu@97a15000 {
> + reg = <0 0x97a15000 0 0x2000>;
> + no-map;
> + };
> +
> + framebuffer-region@9c000000 {
> + reg = <0 0x9c000000 0 0x2400000>;
> + no-map;
> + };
> +
> + /* Also includes ramoops regions */
Isn't that counter-intuitive? Linux won't see it as ramoops then.
> + debug_info_mem: debug-info@a1800000 {
> + reg = <0 0xa1800000 0 0x411000>;
> + no-map;
> + };
> + };
> +
> + /*
> + * Supply map from xiaomi-lavender specifies this as the supply for
> + * ldob1, ldob9, ldob10, ldoa2, and ldoa3, while downstream specifies
> + * this as a power domain. Set this as a fixed regulator with the same
> + * voltage as lavender until display is needed to avoid unneccessarily
> + * using a deprecated binding (regulator-fixed-domain).
> + */
> + vreg_s2b_1p05: vreg-s2b-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vreg_s2b";
> + regulator-min-microvolt = <1050000>;
> + regulator-max-microvolt = <1050000>;
> + };
> +
> + vph_pwr: vph-pwr-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vph_pwr";
> + regulator-min-microvolt = <3312000>;
> + regulator-max-microvolt = <3312000>;
> +
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + autorepeat;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&vol_up_pin>;
> +
> + key-vol-up {
> + label = "Volume Up";
> + linux,code = <KEY_VOLUMEUP>;
> + gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>;
> + };
> + };
> +
> + /*
> + * The touchscreen regulator seems to be controlled somehow by a gpio.
> + * Model it as a fixed regulator and keep it on. Without schematics we
> + * don't know how this is actually wired up...
> + */
> + ts_1p8_supply: ts-1p8-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "ts_1p8_supply";
> +
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> +
> + gpio = <&pm660_gpios 12 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +};
> +
> +&apps_rsc {
> + pm660l-regulators {
New bindings changes dictate use of regulator-0 regulator-1 etc
node names. Also, is there any particular reason PMIC_B goes before
PMIC_A?
> + compatible = "qcom,pm660l-rpmh-regulators";
> + qcom,pmic-id = "b";
> +
> + vdd-s1-supply = <&vph_pwr>;
> + vdd-s2-supply = <&vph_pwr>;
> + vdd-s3-s4-supply = <&vph_pwr>;
> + vdd-s5-supply = <&vph_pwr>;
> +
> + vdd-l1-l9-l10-supply = <&vreg_s2b_1p05>;
> + vdd-l2-supply = <&vreg_bob>;
> + vdd-l3-l5-l7-l8-supply = <&vreg_bob>;
> + vdd-l4-l6-supply = <&vreg_bob>;
> + vdd-bob-supply = <&vph_pwr>;
> +
> + /* LDOs */
> + vreg_l1b_0p89: ldo1 {
> + regulator-min-microvolt = <880000>;
> + regulator-max-microvolt = <900000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l2b_2p38: ldo2 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <2960000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l3b_2p93: ldo3 {
> + regulator-min-microvolt = <2850000>;
> + regulator-max-microvolt = <3008000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l4b_2p96: ldo4 {
> + regulator-min-microvolt = <2960000>;
> + regulator-max-microvolt = <2960000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l5b_2p96: ldo5 {
> + regulator-min-microvolt = <2960000>;
> + regulator-max-microvolt = <2960000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l6b_3p15: ldo6 {
> + regulator-min-microvolt = <3008000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l7b_3p1: ldo7 {
> + regulator-min-microvolt = <3088000>;
> + regulator-max-microvolt = <3100000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l8b_3p3: ldo8 {
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3312000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + /*
> + * Downstream specifies a fixed voltage of 3.312 V, but the
> + * PMIC4 BOB ranges don't support that. Widen the range a
> + * little to avoid adding a new BOB regulator type.
Maybe the upstream driver is wrong then. Could somebody with docs
recheck that?
And also pm8350 & pm8350c ranges while at it, pretty please?
> + */
> + vreg_bob: bob {
> + regulator-min-microvolt = <3296000>;
> + regulator-max-microvolt = <3328000>;
> + regulator-enable-ramp-delay = <500>;
> + };
> + };
> +
> + pm660-regulators {
> + compatible = "qcom,pm660-rpmh-regulators";
> + qcom,pmic-id = "a";
> +
> + vdd-s1-supply = <&vph_pwr>;
> + vdd-s2-supply = <&vph_pwr>;
> + vdd-s3-supply = <&vph_pwr>;
> + vdd-s4-supply = <&vph_pwr>;
> + vdd-s5-supply = <&vph_pwr>;
> + vdd-s6-supply = <&vph_pwr>;
> +
> + vdd-l1-l6-l7-supply = <&vreg_s6a_1p29>;
> + vdd-l2-l3-supply = <&vreg_s2b_1p05>;
> + vdd-l5-supply = <&vreg_s2b_1p05>;
> + vdd-l8-l9-l10-l11-l12-l13-l14-supply = <&vreg_s4a_1p92>;
> + vdd-l15-l16-l17-l18-l19-supply = <&vreg_bob>;
> +
> + /*
> + * S1A (FTAPC0), S2A (FTAPC1), S3A (HFAPC1) are managed
> + * by the Core Power Reduction hardened (CPRh) and the
> + * Operating State Manager (OSM) HW automatically.
> + */
> +
> + vreg_s4a_1p92: smps4 {
> + regulator-min-microvolt = <1808000>;
> + regulator-max-microvolt = <2040000>;
> + regulator-enable-ramp-delay = <200>;
> + };
> +
> + vreg_s6a_1p29: smps6 {
> + regulator-min-microvolt = <1224000>;
> + regulator-max-microvolt = <1352000>;
> + regulator-enable-ramp-delay = <150>;
> + };
> +
> + /* LDOs */
> + vreg_l1a_1p225: ldo1 {
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1250000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l2a_1p0: ldo2 {
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l3a_1p0: ldo3 {
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l5a_0p8: ldo5 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l6a_1p28: ldo6 {
> + regulator-min-microvolt = <1248000>;
> + regulator-max-microvolt = <1304000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l7a_1p2: ldo7 {
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l8a_1p8: ldo8 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l9a_1p8: ldo9 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l10a_1p8: ldo10 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l11a_1p8: ldo11 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l12a_1p8: ldo12 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l13a_1p8: ldo13 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l14a_1p8: ldo14 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l15a_2p38: ldo15 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <2950000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l16a_2p7: ldo16 {
> + regulator-min-microvolt = <2696000>;
> + regulator-max-microvolt = <2696000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l17a_2p38: ldo17 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <2950000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l19a_3p3: ldo19 {
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3312000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> + };
> +};
> +
> +&gpi_dma1 {
> + status = "okay";
> +};
> +
> +&qupv3_id_1 {
> + status = "okay";
> +};
Please sort the & references alphabetically.
> +
> +&i2c9 {
> + status = "okay";
status should be the last property (still before subnodes - otherwise
you'll get a DTC error).
This applies to all occurences.
> + clock-frequency = <100000>;
> +
> + synaptics-rmi4-i2c@20 {
> + compatible = "syna,rmi4-i2c";
> + reg = <0x20>;
> + #address-cells = <0x1>;
> + #size-cells = <0x0>;
> + interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&touchscreen_default>;
> +
> + /* VDD supply isn't specified, bind it to power */
I don't think it would explode if you just removed it then?
> + vdd-supply = <&vph_pwr>;
> + vio-supply = <&ts_1p8_supply>;
> +
> + syna,reset-delay-ms = <200>;
> + syna,startup-delay-ms = <200>;
> +
> + rmi4-f01@1 {
> + reg = <0x01>;
> + syna,nosleep-mode = <1>;
> + };
> +
> + rmi4-f12@12 {
> + reg = <0x12>;
> + touchscreen-x-mm = <62>;
> + touchscreen-y-mm = <127>;
> + syna,sensor-type = <1>;
> + };
> + };
> +};
> +
> +&gcc {
> + protected-clocks = <GCC_QSPI_CORE_CLK>,
> + <GCC_QSPI_CORE_CLK_SRC>,
> + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>;
> +};
> +
> +&pm660l_gpios {
> + vol_up_pin: vol-up-state {
> + pins = "gpio7";
> + function = "normal";
> + qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
> + input-enable;
> + bias-pull-up;
> + };
> +};
> +
> +&pon_pwrkey {
> + status = "okay";
> +};
> +
> +&pon_resin {
> + status = "okay";
> + linux,code = <KEY_VOLUMEDOWN>;
> +};
> +
> +&sdhc_1 {
> + status = "okay";
> + supports-cqe;
> + mmc-hs200-1_8v;
> + mmc-hs400-1_8v;
> + mmc-ddr-1_8v;
> +
> + qcom,ddr-config = <0xc3040873>;
> +
> + vmmc-supply = <&vreg_l4b_2p96>;
> + vqmmc-supply = <&vreg_l8a_1p8>;
> +};
> +
> +&tlmm {
> + gpio-reserved-ranges = <0 4>, <81 4>;
> +
> + touchscreen_default: ts-default-state {
> + ts-reset-pins {
> + pins = "gpio99";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + output-high;
> + };
> +
> + ts-irq-pins {
> + pins = "gpio125";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + ts-switch-pins {
> + pins = "gpio135";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + output-low;
> + };
> + };
> +};
> +
> +&usb_1_hsphy {
> + status = "okay";
> +
> + vdd-supply = <&vreg_l1b_0p89>;
> + vdda-pll-supply = <&vreg_l10a_1p8>;
> + vdda-phy-dpdm-supply = <&vreg_l7b_3p1>;
> +};
> +
> +&usb_1 {
> + status = "okay";
> +
> + qcom,select-utmi-as-pipe-clk;
> +};
> +
> +&usb_1_dwc3 {
> + /* Only peripheral works for now */
> + dr_mode = "peripheral";
> +
> + /* Do not assume that sdm670.dtsi will never support USB 3.0 */
> + phys = <&usb_1_hsphy>;
> + phy-names = "usb2-phy";
> + maximum-speed = "high-speed";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
> new file mode 100644
> index 000000000000..4450ece839a0
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
> @@ -0,0 +1,1216 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SDM670 SoC device tree source, adapted from SDM845 SoC device tree
> + *
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2022, Richard Acayan. All rights reserved.
> + */
> +
> +#include <dt-bindings/clock/qcom,gcc-sdm845.h>
> +#include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/dma/qcom-gpi.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/phy/phy-qcom-qusb2.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases { };
> +
> + chosen { };
> +
> + memory@80000000 {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the size */
> + reg = <0 0x80000000 0 0>;
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + hyp_mem: hyp-mem@85700000 {
> + reg = <0 0x85700000 0 0x600000>;
> + no-map;
> + };
> +
> + xbl_mem: xbl-mem@85e00000 {
> + reg = <0 0x85e00000 0 0x100000>;
> + no-map;
> + };
> +
> + aop_mem: aop-mem@85fc0000 {
> + reg = <0 0x85fc0000 0 0x20000>;
> + no-map;
> + };
> +
> + aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
> + compatible = "qcom,cmd-db";
> + reg = <0x0 0x85fe0000 0 0x20000>;
> + no-map;
> + };
> +
> + camera_mem: camera-mem@8ab00000 {
> + reg = <0 0x8ab00000 0 0x500000>;
> + no-map;
> + };
> +
> + mpss_region: mpss@8b000000 {
> + reg = <0 0x8b000000 0 0x7e00000>;
> + no-map;
> + };
> +
> + venus_mem: venus@92e00000 {
> + reg = <0 0x92e00000 0 0x500000>;
> + no-map;
> + };
> +
> + wlan_msa_mem: wlan-msa@93300000 {
> + reg = <0 0x93300000 0 0x100000>;
> + no-map;
> + };
> +
> + cdsp_mem: cdsp@93400000 {
> + reg = <0 0x93400000 0 0x800000>;
> + no-map;
> + };
> +
> + mba_region: mba@93c00000 {
> + reg = <0 0x93c00000 0 0x200000>;
> + no-map;
> + };
> +
> + adsp_mem: adsp@93e00000 {
> + reg = <0 0x93e00000 0 0x1e00000>;
> + no-map;
> + };
> +
> + ipa_fw_mem: ipa-fw@95c00000 {
> + reg = <0 0x95c00000 0 0x10000>;
> + no-map;
> + };
> +
> + ipa_gsi_mem: ipa-gsi@95c10000 {
> + reg = <0 0x95c10000 0 0x5000>;
> + no-map;
> + };
> +
> + gpu_mem: gpu@95c15000 {
> + reg = <0 0x95c15000 0 0x2000>;
> + no-map;
> + };
> +
> + spss_mem: spss@97b00000 {
> + reg = <0 0x97b00000 0 0x100000>;
> + no-map;
> + };
> +
> + qseecom_mem: qseecom@9e400000 {
> + reg = <0 0x9e400000 0 0x1400000>;
> + no-map;
> + };
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD0>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_0>;
> + L2_0: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + L3_0: l3-cache {
> + compatible = "cache";
> + };
> + };
> + };
> +
> + CPU1: cpu@100 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD1>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_100>;
> + L2_100: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU2: cpu@200 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x200>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD2>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_200>;
> + L2_200: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU3: cpu@300 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x300>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD3>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_300>;
> + L2_300: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU4: cpu@400 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x400>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD4>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_400>;
> + L2_400: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU5: cpu@500 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x500>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD5>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_500>;
> + L2_500: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU6: cpu@600 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x600>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD6>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_600>;
> + L2_600: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU7: cpu@700 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x700>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD7>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_700>;
> + L2_700: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&CPU0>;
> + };
> +
> + core1 {
> + cpu = <&CPU1>;
> + };
> +
> + core2 {
> + cpu = <&CPU2>;
> + };
> +
> + core3 {
> + cpu = <&CPU3>;
> + };
> +
> + core4 {
> + cpu = <&CPU4>;
> + };
> +
> + core5 {
> + cpu = <&CPU5>;
> + };
> +
> + core6 {
> + cpu = <&CPU6>;
> + };
> +
> + core7 {
> + cpu = <&CPU7>;
> + };
> + };
> + };
> +
> + idle-states {
> + entry-method = "psci";
> +
> + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
> + compatible = "arm,idle-state";
> + idle-state-name = "little-rail-power-collapse";
> + arm,psci-suspend-param = <0x40000004>;
> + entry-latency-us = <702>;
> + exit-latency-us = <915>;
> + min-residency-us = <1617>;
> + local-timer-stop;
> + };
> +
> + BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
> + compatible = "arm,idle-state";
> + idle-state-name = "big-rail-power-collapse";
> + arm,psci-suspend-param = <0x40000004>;
> + entry-latency-us = <526>;
> + exit-latency-us = <1854>;
> + min-residency-us = <2380>;
> + local-timer-stop;
> + };
> + };
> +
> + domain-idle-states {
> + CLUSTER_SLEEP_0: cluster-sleep-0 {
> + compatible = "domain-idle-state";
> + arm,psci-suspend-param = <0x4100c244>;
> + entry-latency-us = <3263>;
> + exit-latency-us = <6562>;
> + min-residency-us = <9825>;
> + };
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + clocks {
Please sort nodes alphabetically.
> + xo_board: xo-board {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <38400000>;
clock-frequency should be moved to the board DTS to indicate it's not
a part of the SoC itself, but rather it sits on the board.
> + clock-output-names = "xo_board";
This should actually not be necessary, if you pass "xo" to rpmcc..
> + };
> +
> + sleep_clk: sleep-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32764>;
> + };
> + };
> +
> + firmware {
> + scm {
> + compatible = "qcom,scm-sdm670", "qcom,scm";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> +
> + CPU_PD0: power-domain-cpu0 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD1: power-domain-cpu1 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD2: power-domain-cpu2 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD3: power-domain-cpu3 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD4: power-domain-cpu4 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD5: power-domain-cpu5 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD6: power-domain-cpu6 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD7: power-domain-cpu7 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
> + };
> +
> + CLUSTER_PD: power-domain-cluster {
> + #power-domain-cells = <0>;
> + domain-idle-states = <&CLUSTER_SLEEP_0>;
> + };
> + };
> +
> + soc: soc@0 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0 0 0 0 0x10 0>;
> + dma-ranges = <0 0 0 0 0x10 0>;
> + compatible = "simple-bus";
> +
> + gcc: clock-controller@100000 {
> + compatible = "qcom,gcc-sdm670";
> + reg = <0 0x00100000 0 0x1f0000>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&rpmhcc RPMH_CXO_CLK_A>,
> + <&sleep_clk>;
> + clock-names = "bi_tcxo",
> + "bi_tcxo_ao",
> + "sleep_clk";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> + sdhc_1: mmc@7c4000 {
> + compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0 0x007c4000 0 0x1000>,
> + <0 0x007c5000 0 0x1000>,
> + <0 0x007c8000 0 0x8000>;
> + reg-names = "hc", "cqhci", "ice";
> +
> + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> + <&gcc GCC_SDCC1_APPS_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_SDCC1_ICE_CORE_CLK>,
> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
> + clock-names = "iface", "core", "xo", "ice", "bus";
> +
> + iommus = <&apps_smmu 0x140 0xf>;
> +
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&sdc1_state_on>;
> + pinctrl-1 = <&sdc1_state_off>;
> + power-domains = <&rpmhpd SDM670_CX>;
> +
> + bus-width = <8>;
> + non-removable;
> +
> + status = "disabled";
> + };
> +
> + gpi_dma0: dma-controller@800000 {
> + #dma-cells = <3>;
> + compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
> + reg = <0 0x00800000 0 0x60000>;
> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
> + dma-channels = <13>;
> + dma-channel-mask = <0xfa>;
> + iommus = <&apps_smmu 0x0016 0x0>;
> + status = "disabled";
> + };
> +
> + qupv3_id_0: geniqup@8c0000 {
> + compatible = "qcom,geni-se-qup";
> + reg = <0 0x008c0000 0 0x6000>;
> + clock-names = "m-ahb", "s-ahb";
> + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
> + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
> + iommus = <&apps_smmu 0x3 0x0>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
> + interconnect-names = "qup-core";
> + status = "disabled";
> +
> + i2c0: i2c@880000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00880000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c0_default>;
> + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 0 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c1: i2c@884000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00884000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c1_default>;
> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 1 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c2: i2c@888000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00888000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c2_default>;
> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 2 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c3: i2c@88c000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x0088c000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c3_default>;
> + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 3 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c4: i2c@890000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00890000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c4_default>;
> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 4 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c5: i2c@894000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00894000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c5_default>;
> + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 5 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c6: i2c@898000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00898000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c6_default>;
> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 6 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c7: i2c@89c000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x0089c000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c7_default>;
> + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 7 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> + };
> +
> + gpi_dma1: dma-controller@a00000 {
> + #dma-cells = <3>;
> + compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
> + reg = <0 0x00a00000 0 0x60000>;
> + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
> + dma-channels = <13>;
> + dma-channel-mask = <0xfa>;
> + iommus = <&apps_smmu 0x06d6 0x0>;
> + status = "disabled";
> + };
> +
> + qupv3_id_1: geniqup@ac0000 {
> + compatible = "qcom,geni-se-qup";
> + reg = <0 0x00ac0000 0 0x6000>;
> + clock-names = "m-ahb", "s-ahb";
> + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
> + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> + iommus = <&apps_smmu 0x6c3 0x0>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + i2c8: i2c@a80000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a80000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c8_default>;
> + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 0 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c9: i2c@a84000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a84000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c9_default>;
> + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 1 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c10: i2c@a88000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a88000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c10_default>;
> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 2 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c11: i2c@a8c000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a8c000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c11_default>;
> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 3 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c12: i2c@a90000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a90000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c12_default>;
> + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 4 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c13: i2c@a94000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a94000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c13_default>;
> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 5 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c14: i2c@a98000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a98000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c14_default>;
> + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 6 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c15: i2c@a9c000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a9c000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c15_default>;
> + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 7 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> + };
> +
> + tlmm: pinctrl@3400000 {
> + compatible = "qcom,sdm670-tlmm";
> + reg = <0 0x03400000 0 0xc00000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-ranges = <&tlmm 0 0 151>;
> +
> + qup_i2c0_default: qup-i2c0-default-state {
> + pins = "gpio0", "gpio1";
> + function = "qup0";
> + };
> +
> + qup_i2c1_default: qup-i2c1-default-state {
> + pins = "gpio17", "gpio18";
> + function = "qup1";
> + };
> +
> + qup_i2c2_default: qup-i2c2-default-state {
> + pins = "gpio27", "gpio28";
> + function = "qup2";
> + };
> +
> + qup_i2c3_default: qup-i2c3-default-state {
> + pins = "gpio41", "gpio42";
> + function = "qup3";
> + };
> +
> + qup_i2c4_default: qup-i2c4-default-state {
> + pins = "gpio89", "gpio90";
> + function = "qup4";
> + };
> +
> + qup_i2c5_default: qup-i2c5-default-state {
> + pins = "gpio85", "gpio86";
> + function = "qup5";
> + };
> +
> + qup_i2c6_default: qup-i2c6-default-state {
> + pins = "gpio45", "gpio46";
> + function = "qup6";
> + };
> +
> + qup_i2c7_default: qup-i2c7-default-state {
> + pins = "gpio93", "gpio94";
> + function = "qup7";
> + };
> +
> + qup_i2c8_default: qup-i2c8-default-state {
> + pins = "gpio65", "gpio66";
> + function = "qup8";
> + };
> +
> + qup_i2c9_default: qup-i2c9-default-state {
> + pins = "gpio6", "gpio7";
> + function = "qup9";
> + };
> +
> + qup_i2c10_default: qup-i2c10-default-state {
> + pins = "gpio55", "gpio56";
> + function = "qup10";
> + };
> +
> + qup_i2c11_default: qup-i2c11-default-state {
> + pins = "gpio31", "gpio32";
> + function = "qup11";
> + };
> +
> + qup_i2c12_default: qup-i2c12-default-state {
> + pins = "gpio49", "gpio50";
> + function = "qup12";
> + };
> +
> + qup_i2c13_default: qup-i2c13-default-state {
> + pins = "gpio105", "gpio106";
> + function = "qup13";
> + };
> +
> + qup_i2c14_default: qup-i2c14-default-state {
> + pins = "gpio33", "gpio34";
> + function = "qup14";
> + };
> +
> + qup_i2c15_default: qup-i2c15-default-state {
> + pins = "gpio81", "gpio82";
> + function = "qup15";
> + };
> +
> + sdc1_state_on: sdc1-on-state {
> + clk-pins {
> + pins = "sdc1_clk";
> + bias-disable;
> + drive-strength = <16>;
> + };
> +
> + cmd-pins {
> + pins = "sdc1_cmd";
> + bias-pull-up;
> + drive-strength = <10>;
> + };
> +
> + data-pins {
> + pins = "sdc1_data";
> + bias-pull-up;
> + drive-strength = <10>;
> + };
> +
> + rclk-pins {
> + pins = "sdc1_rclk";
> + bias-pull-down;
> + };
> + };
> +
> + sdc1_state_off: sdc1-off-state {
> + clk-pins {
> + pins = "sdc1_clk";
> + bias-disable;
> + drive-strength = <2>;
> + };
> +
> + cmd-pins {
> + pins = "sdc1_cmd";
> + bias-pull-up;
> + drive-strength = <2>;
> + };
> +
> + data-pins {
> + pins = "sdc1_data";
> + bias-pull-up;
> + drive-strength = <2>;
> + };
> +
> + rclk-pins {
> + pins = "sdc1_rclk";
> + bias-pull-down;
> + };
> + };
> + };
> +
> + usb_1_hsphy: phy@88e2000 {
> + compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy";
> + reg = <0 0x088e2000 0 0x400>;
> + status = "disabled";
Status last, please.
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "cfg_ahb", "ref";
> +
> + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> + };
> +
> + usb_1: usb@a6f8800 {
> + compatible = "qcom,sdm670-dwc3", "qcom,dwc3";
> + reg = <0 0x0a6f8800 0 0x400>;
> + status = "disabled";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + dma-ranges;
> +
> + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_MASTER_CLK>,
> + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
> + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
> + clock-names = "cfg_noc",
> + "core",
> + "iface",
> + "sleep",
> + "mock_utmi";
> +
> + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB30_PRIM_MASTER_CLK>;
> + assigned-clock-rates = <19200000>, <150000000>;
> +
> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hs_phy_irq", "ss_phy_irq",
> + "dm_hs_phy_irq", "dp_hs_phy_irq";
> +
> + power-domains = <&gcc USB30_PRIM_GDSC>;
> +
> + resets = <&gcc GCC_USB30_PRIM_BCR>;
> +
> + usb_1_dwc3: usb@a600000 {
> + compatible = "snps,dwc3";
> + reg = <0 0x0a600000 0 0xcd00>;
> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> + iommus = <&apps_smmu 0x740 0>;
> + snps,dis_u2_susphy_quirk;
> + snps,dis_enblslpm_quirk;
> + phys = <&usb_1_hsphy>;
> + phy-names = "usb2-phy";
> + };
> + };
> +
> + spmi_bus: spmi@c440000 {
> + compatible = "qcom,spmi-pmic-arb";
> + reg = <0 0x0c440000 0 0x1100>,
> + <0 0x0c600000 0 0x2000000>,
> + <0 0x0e600000 0 0x100000>,
> + <0 0x0e700000 0 0xa0000>,
> + <0 0x0c40a000 0 0x26000>;
> + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> + interrupt-names = "periph_irq";
> + interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
> + qcom,ee = <0>;
> + qcom,channel = <0>;
> + #address-cells = <2>;
> + #size-cells = <0>;
> + interrupt-controller;
> + #interrupt-cells = <4>;
> + };
> +
> + apps_smmu: iommu@15000000 {
> + /*
> + * The hardware tolerates the SDM845 reset quirk. The
> + * iommu maintainers aren't responding to any patches
> + * that would add support for new platforms. Set this
> + * compatible so this dtsi is valid and functional.
Not sure if this is the right approach. SDM670 is more or less a factory
reject 845,
but the software stack may be hiding some differences..
Konrad
> + */
> + compatible = "qcom,sdm845-smmu-500", "qcom,smmu-500", "arm,mmu-500";
> + reg = <0 0x15000000 0 0x80000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <1>;
> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + apps_rsc: rsc@179c0000 {
> + label = "apps_rsc";
> + compatible = "qcom,rpmh-rsc";
> + reg = <0 0x179c0000 0 0x10000>,
> + <0 0x179d0000 0 0x10000>,
> + <0 0x179e0000 0 0x10000>;
> + reg-names = "drv-0", "drv-1", "drv-2";
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + qcom,tcs-offset = <0xd00>;
> + qcom,drv-id = <2>;
> + qcom,tcs-config = <ACTIVE_TCS 2>,
> + <SLEEP_TCS 3>,
> + <WAKE_TCS 3>,
> + <CONTROL_TCS 1>;
> +
> + apps_bcm_voter: bcm-voter {
> + compatible = "qcom,bcm-voter";
> + };
> +
> + rpmhcc: clock-controller {
> + compatible = "qcom,sdm670-rpmh-clk";
> + #clock-cells = <1>;
> + clock-names = "xo";
> + clocks = <&xo_board>;
> + };
> +
> + rpmhpd: power-controller {
> + compatible = "qcom,sdm670-rpmhpd";
> + #power-domain-cells = <1>;
> + operating-points-v2 = <&rpmhpd_opp_table>;
> +
> + rpmhpd_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + rpmhpd_opp_ret: opp1 {
> + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
> + };
> +
> + rpmhpd_opp_min_svs: opp2 {
> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> + };
> +
> + rpmhpd_opp_low_svs: opp3 {
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + };
> +
> + rpmhpd_opp_svs: opp4 {
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> + };
> +
> + rpmhpd_opp_svs_l1: opp5 {
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> + };
> +
> + rpmhpd_opp_nom: opp6 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> + };
> +
> + rpmhpd_opp_nom_l1: opp7 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> + };
> +
> + rpmhpd_opp_nom_l2: opp8 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
> + };
> +
> + rpmhpd_opp_turbo: opp9 {
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> + };
> +
> + rpmhpd_opp_turbo_l1: opp10 {
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> + };
> + };
> + };
> + };
> +
> + intc: interrupt-controller@17a00000 {
> + compatible = "arm,gic-v3";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0 0x17a00000 0 0x10000>, /* GICD */
> + <0 0x17a60000 0 0x100000>; /* GICR * 8 */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +};
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 4/4] arm64: dts: qcom: add sdm670 and pixel 3a device trees
2022-11-02 20:26 ` Konrad Dybcio
@ 2022-11-02 20:30 ` Krzysztof Kozlowski
2022-11-02 20:44 ` Konrad Dybcio
2022-11-03 0:53 ` Richard Acayan
1 sibling, 1 reply; 16+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-02 20:30 UTC (permalink / raw)
To: Konrad Dybcio, Richard Acayan, Rob Herring, Krzysztof Kozlowski,
Andy Gross, Bjorn Andersson, Vinod Koul, Robin Murphy,
Chanho Park, Thierry Reding, Stephan Gerhold, Lorenzo Pieralisi,
Robert Marko, Das Srinagesh, devicetree, linux-kernel,
linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel
On 02/11/2022 16:26, Konrad Dybcio wrote:
>
> On 02/11/2022 00:57, Richard Acayan wrote:
>> The Qualcomm Snapdragon 670 has been out for a while. Add a device tree
>> for it and the Google Pixel 3a as the first device.
>>
>> The Pixel 3a has the same bootloader issue as the Pixel 3 and will not work
>> on Android 10 bootloaders or later until it gets fixed for the Pixel 3.
>>
>> SoC Initial Features:
>> - power management
>> - clocks
>> - pinctrl
>> - eMMC
>> - USB 2.0
>> - GENI I2C
>> - IOMMU
>> - RPMh
>> - interrupts
>>
>> Device-Specific Initial Features:
>> - side buttons (keys)
>> - regulators
>> - touchscreen
>>
>> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 1 +
>> .../boot/dts/qcom/sdm670-google-sargo.dts | 519 +++++++
>> arch/arm64/boot/dts/qcom/sdm670.dtsi | 1216 +++++++++++++++++
>> 3 files changed, 1736 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/sdm670.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index b0558d3389e5..4eb5d8829efb 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -124,6 +124,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm632-fairphone-fp3.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
>> new file mode 100644
>> index 000000000000..fa3dee78e442
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
>> @@ -0,0 +1,519 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Device tree for Google Pixel 3a, adapted from google-blueline device tree,
>> + * xiaomi-lavender device tree, and oneplus-common device tree.
>> + *
>> + * Copyright (c) 2022, Richard Acayan. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/input/input.h>
>> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
>> +#include <dt-bindings/power/qcom-rpmpd.h>
>> +#include "sdm670.dtsi"
>> +#include "pm660.dtsi"
>> +#include "pm660l.dtsi"
>> +
>> +/delete-node/ &mpss_region;
>> +/delete-node/ &venus_mem;
>> +/delete-node/ &wlan_msa_mem;
>> +/delete-node/ &cdsp_mem;
>> +/delete-node/ &mba_region;
>> +/delete-node/ &adsp_mem;
>> +/delete-node/ &ipa_fw_mem;
>> +/delete-node/ &ipa_gsi_mem;
>> +/delete-node/ &gpu_mem;
>> +
>> +/ {
>> + model = "Google Pixel 3a";
>> + compatible = "google,sargo", "qcom,sdm670";
>> + qcom,board-id = <0x00041e05 0>;
>> + qcom,msm-id = <321 0x20001>;
>> +
>> + aliases { };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> +
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + framebuffer@9c000000 {
>> + compatible = "simple-framebuffer";
>> + reg = <0x0 0x9c000000 0x0 (1080 * 2220 * 4)>;
>> + width = <1080>;
>> + height = <2220>;
>> + stride = <(1080 * 4)>;
>> + format = "a8r8g8b8";
>> + };
>> + };
>> +
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + mpss_region: mpss@8b000000 {
>
> Please call the nodes memory@
I think the actual recommendation is to use the purpose as name:
https://lore.kernel.org/linux-arm-msm/CAL_Jsq+66j8Y5y+PQ+mezkaxN1pfHFKz524YUF4Lz_OU5E-mZQ@mail.gmail.com/
https://devicetree-specification.readthedocs.io/en/latest/chapter3-devicenodes.html#reserved-memory-child-nodes
(second paragraph)
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 4/4] arm64: dts: qcom: add sdm670 and pixel 3a device trees
2022-11-02 20:30 ` Krzysztof Kozlowski
@ 2022-11-02 20:44 ` Konrad Dybcio
0 siblings, 0 replies; 16+ messages in thread
From: Konrad Dybcio @ 2022-11-02 20:44 UTC (permalink / raw)
To: Krzysztof Kozlowski, Richard Acayan, Rob Herring,
Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Vinod Koul,
Robin Murphy, Chanho Park, Thierry Reding, Stephan Gerhold,
Lorenzo Pieralisi, Robert Marko, Das Srinagesh, devicetree,
linux-kernel, linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel
On 02/11/2022 21:30, Krzysztof Kozlowski wrote:
> On 02/11/2022 16:26, Konrad Dybcio wrote:
>> On 02/11/2022 00:57, Richard Acayan wrote:
>>> The Qualcomm Snapdragon 670 has been out for a while. Add a device tree
>>> for it and the Google Pixel 3a as the first device.
>>>
>>> The Pixel 3a has the same bootloader issue as the Pixel 3 and will not work
>>> on Android 10 bootloaders or later until it gets fixed for the Pixel 3.
>>>
>>> SoC Initial Features:
>>> - power management
>>> - clocks
>>> - pinctrl
>>> - eMMC
>>> - USB 2.0
>>> - GENI I2C
>>> - IOMMU
>>> - RPMh
>>> - interrupts
>>>
>>> Device-Specific Initial Features:
>>> - side buttons (keys)
>>> - regulators
>>> - touchscreen
>>>
>>> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/Makefile | 1 +
>>> .../boot/dts/qcom/sdm670-google-sargo.dts | 519 +++++++
>>> arch/arm64/boot/dts/qcom/sdm670.dtsi | 1216 +++++++++++++++++
>>> 3 files changed, 1736 insertions(+)
>>> create mode 100644 arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
>>> create mode 100644 arch/arm64/boot/dts/qcom/sdm670.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>>> index b0558d3389e5..4eb5d8829efb 100644
>>> --- a/arch/arm64/boot/dts/qcom/Makefile
>>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>>> @@ -124,6 +124,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb
>>> dtb-$(CONFIG_ARCH_QCOM) += sdm632-fairphone-fp3.dtb
>>> dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb
>>> dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb
>>> +dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb
>>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
>>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
>>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
>>> diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
>>> new file mode 100644
>>> index 000000000000..fa3dee78e442
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
>>> @@ -0,0 +1,519 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Device tree for Google Pixel 3a, adapted from google-blueline device tree,
>>> + * xiaomi-lavender device tree, and oneplus-common device tree.
>>> + *
>>> + * Copyright (c) 2022, Richard Acayan. All rights reserved.
>>> + */
>>> +
>>> +/dts-v1/;
>>> +
>>> +#include <dt-bindings/gpio/gpio.h>
>>> +#include <dt-bindings/input/input.h>
>>> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
>>> +#include <dt-bindings/power/qcom-rpmpd.h>
>>> +#include "sdm670.dtsi"
>>> +#include "pm660.dtsi"
>>> +#include "pm660l.dtsi"
>>> +
>>> +/delete-node/ &mpss_region;
>>> +/delete-node/ &venus_mem;
>>> +/delete-node/ &wlan_msa_mem;
>>> +/delete-node/ &cdsp_mem;
>>> +/delete-node/ &mba_region;
>>> +/delete-node/ &adsp_mem;
>>> +/delete-node/ &ipa_fw_mem;
>>> +/delete-node/ &ipa_gsi_mem;
>>> +/delete-node/ &gpu_mem;
>>> +
>>> +/ {
>>> + model = "Google Pixel 3a";
>>> + compatible = "google,sargo", "qcom,sdm670";
>>> + qcom,board-id = <0x00041e05 0>;
>>> + qcom,msm-id = <321 0x20001>;
>>> +
>>> + aliases { };
>>> +
>>> + chosen {
>>> + stdout-path = "serial0:115200n8";
>>> +
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + ranges;
>>> +
>>> + framebuffer@9c000000 {
>>> + compatible = "simple-framebuffer";
>>> + reg = <0x0 0x9c000000 0x0 (1080 * 2220 * 4)>;
>>> + width = <1080>;
>>> + height = <2220>;
>>> + stride = <(1080 * 4)>;
>>> + format = "a8r8g8b8";
>>> + };
>>> + };
>>> +
>>> + reserved-memory {
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> +
>>> + mpss_region: mpss@8b000000 {
>> Please call the nodes memory@
> I think the actual recommendation is to use the purpose as name:
>
> https://lore.kernel.org/linux-arm-msm/CAL_Jsq+66j8Y5y+PQ+mezkaxN1pfHFKz524YUF4Lz_OU5E-mZQ@mail.gmail.com/
>
> https://devicetree-specification.readthedocs.io/en/latest/chapter3-devicenodes.html#reserved-memory-child-nodes
> (second paragraph)
Ok, my bad.
Konrad
>
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 4/4] arm64: dts: qcom: add sdm670 and pixel 3a device trees
2022-11-02 20:26 ` Konrad Dybcio
2022-11-02 20:30 ` Krzysztof Kozlowski
@ 2022-11-03 0:53 ` Richard Acayan
1 sibling, 0 replies; 16+ messages in thread
From: Richard Acayan @ 2022-11-03 0:53 UTC (permalink / raw)
To: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Andy Gross,
Bjorn Andersson, Vinod Koul, Robin Murphy, Chanho Park,
Thierry Reding, Stephan Gerhold, Lorenzo Pieralisi, Robert Marko,
Das Srinagesh, devicetree, linux-kernel, linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel, Richard Acayan
On Wed, Nov 02, 2022 at 09:26:13PM +0100, Konrad Dybcio wrote:
> On 02/11/2022 00:57, Richard Acayan wrote:
>> The Qualcomm Snapdragon 670 has been out for a while. Add a device tree
>> for it and the Google Pixel 3a as the first device.
>>
>> The Pixel 3a has the same bootloader issue as the Pixel 3 and will not work
>> on Android 10 bootloaders or later until it gets fixed for the Pixel 3.
>>
>> SoC Initial Features:
>> - power management
>> - clocks
>> - pinctrl
>> - eMMC
>> - USB 2.0
>> - GENI I2C
>> - IOMMU
>> - RPMh
>> - interrupts
>>
>> Device-Specific Initial Features:
>> - side buttons (keys)
>> - regulators
>> - touchscreen
>>
>> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 1 +
>> .../boot/dts/qcom/sdm670-google-sargo.dts | 519 +++++++
>> arch/arm64/boot/dts/qcom/sdm670.dtsi | 1216 +++++++++++++++++
>> 3 files changed, 1736 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/sdm670.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index b0558d3389e5..4eb5d8829efb 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -124,6 +124,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm632-fairphone-fp3.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
>> new file mode 100644
>> index 000000000000..fa3dee78e442
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
>> @@ -0,0 +1,519 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Device tree for Google Pixel 3a, adapted from google-blueline device tree,
>> + * xiaomi-lavender device tree, and oneplus-common device tree.
>> + *
>> + * Copyright (c) 2022, Richard Acayan. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/input/input.h>
>> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
>> +#include <dt-bindings/power/qcom-rpmpd.h>
>> +#include "sdm670.dtsi"
>> +#include "pm660.dtsi"
>> +#include "pm660l.dtsi"
>> +
>> +/delete-node/ &mpss_region;
>> +/delete-node/ &venus_mem;
>> +/delete-node/ &wlan_msa_mem;
>> +/delete-node/ &cdsp_mem;
>> +/delete-node/ &mba_region;
>> +/delete-node/ &adsp_mem;
>> +/delete-node/ &ipa_fw_mem;
>> +/delete-node/ &ipa_gsi_mem;
>> +/delete-node/ &gpu_mem;
>> +
>> +/ {
>> + model = "Google Pixel 3a";
>> + compatible = "google,sargo", "qcom,sdm670";
>> + qcom,board-id = <0x00041e05 0>;
>> + qcom,msm-id = <321 0x20001>;
>> +
>> + aliases { };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> +
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + framebuffer@9c000000 {
>> + compatible = "simple-framebuffer";
>> + reg = <0x0 0x9c000000 0x0 (1080 * 2220 * 4)>;
>> + width = <1080>;
>> + height = <2220>;
>> + stride = <(1080 * 4)>;
>> + format = "a8r8g8b8";
>> + };
>> + };
>> +
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + mpss_region: mpss@8b000000 {
>
> Please call the nodes memory@
Ignoring.
>
>
>> + reg = <0 0x8b000000 0 0x9800000>;
>> + no-map;
>> + };
>> +
>> + venus_mem: venus@94800000 {
>> + reg = <0 0x94800000 0 0x500000>;
>> + no-map;
>> + };
>> +
>> + wlan_msa_mem: wlan-msa@94d00000 {
>> + reg = <0 0x94d00000 0 0x100000>;
>> + no-map;
>> + };
>> +
>> + cdsp_mem: cdsp@94e00000 {
>> + reg = <0 0x94e00000 0 0x800000>;
>> + no-map;
>> + };
>> +
>> + mba_region: mba@95600000 {
>> + reg = <0 0x95600000 0 0x200000>;
>> + no-map;
>> + };
>> +
>> + adsp_mem: adsp@95800000 {
>> + reg = <0 0x95800000 0 0x2200000>;
>> + no-map;
>> + };
>> +
>> + ipa_fw_mem: ipa-fw@97a00000 {
>> + reg = <0 0x97a00000 0 0x10000>;
>> + no-map;
>> + };
>> +
>> + ipa_gsi_mem: ipa-gsi@97a10000 {
>> + reg = <0 0x97a10000 0 0x5000>;
>> + no-map;
>> + };
>> +
>> + gpu_mem: gpu@97a15000 {
>> + reg = <0 0x97a15000 0 0x2000>;
>> + no-map;
>> + };
>> +
>> + framebuffer-region@9c000000 {
>> + reg = <0 0x9c000000 0 0x2400000>;
>> + no-map;
>> + };
>> +
>> + /* Also includes ramoops regions */
>
> Isn't that counter-intuitive? Linux won't see it as ramoops then.
Well, if it doesn't work, I don't want to pretend that it does.
The last time I tested ramoops time I tested ramoops was when there was
no simplefb, usb, or mmc. I could only test ramoops with an Android
recovery, and it didn't seem to function. I'll test the ramoops region
again before the next version and add it if it works.
>
>
>> + debug_info_mem: debug-info@a1800000 {
>> + reg = <0 0xa1800000 0 0x411000>;
>> + no-map;
>> + };
>> + };
>> +
>> + /*
>> + * Supply map from xiaomi-lavender specifies this as the supply for
>> + * ldob1, ldob9, ldob10, ldoa2, and ldoa3, while downstream specifies
>> + * this as a power domain. Set this as a fixed regulator with the same
>> + * voltage as lavender until display is needed to avoid unneccessarily
>> + * using a deprecated binding (regulator-fixed-domain).
>> + */
>> + vreg_s2b_1p05: vreg-s2b-regulator {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vreg_s2b";
>> + regulator-min-microvolt = <1050000>;
>> + regulator-max-microvolt = <1050000>;
>> + };
>> +
>> + vph_pwr: vph-pwr-regulator {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vph_pwr";
>> + regulator-min-microvolt = <3312000>;
>> + regulator-max-microvolt = <3312000>;
>> +
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + gpio-keys {
>> + compatible = "gpio-keys";
>> + autorepeat;
>> +
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&vol_up_pin>;
>> +
>> + key-vol-up {
>> + label = "Volume Up";
>> + linux,code = <KEY_VOLUMEUP>;
>> + gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>;
>> + };
>> + };
>> +
>> + /*
>> + * The touchscreen regulator seems to be controlled somehow by a gpio.
>> + * Model it as a fixed regulator and keep it on. Without schematics we
>> + * don't know how this is actually wired up...
>> + */
>> + ts_1p8_supply: ts-1p8-regulator {
>> + compatible = "regulator-fixed";
>> + regulator-name = "ts_1p8_supply";
>> +
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> +
>> + gpio = <&pm660_gpios 12 GPIO_ACTIVE_HIGH>;
>> + enable-active-high;
>> + };
>> +};
>> +
>> +&apps_rsc {
>> + pm660l-regulators {
>
> New bindings changes dictate use of regulator-0 regulator-1 etc
>
> node names. Also, is there any particular reason PMIC_B goes before
>
> PMIC_A?
Renamed for v2.
If I remember correctly, the reason was that bob supplies other
regulators. You couldn't probe a regulator when I was putting this
together. Something must have changed on next, but these can be in their
proper order now.
>
>
>> + compatible = "qcom,pm660l-rpmh-regulators";
>> + qcom,pmic-id = "b";
>> +
>> + vdd-s1-supply = <&vph_pwr>;
>> + vdd-s2-supply = <&vph_pwr>;
>> + vdd-s3-s4-supply = <&vph_pwr>;
>> + vdd-s5-supply = <&vph_pwr>;
>> +
>> + vdd-l1-l9-l10-supply = <&vreg_s2b_1p05>;
>> + vdd-l2-supply = <&vreg_bob>;
>> + vdd-l3-l5-l7-l8-supply = <&vreg_bob>;
>> + vdd-l4-l6-supply = <&vreg_bob>;
>> + vdd-bob-supply = <&vph_pwr>;
>> +
>> + /* LDOs */
>> + vreg_l1b_0p89: ldo1 {
>> + regulator-min-microvolt = <880000>;
>> + regulator-max-microvolt = <900000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + vreg_l2b_2p38: ldo2 {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <2960000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + vreg_l3b_2p93: ldo3 {
>> + regulator-min-microvolt = <2850000>;
>> + regulator-max-microvolt = <3008000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + vreg_l4b_2p96: ldo4 {
>> + regulator-min-microvolt = <2960000>;
>> + regulator-max-microvolt = <2960000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + vreg_l5b_2p96: ldo5 {
>> + regulator-min-microvolt = <2960000>;
>> + regulator-max-microvolt = <2960000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + vreg_l6b_3p15: ldo6 {
>> + regulator-min-microvolt = <3008000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + vreg_l7b_3p1: ldo7 {
>> + regulator-min-microvolt = <3088000>;
>> + regulator-max-microvolt = <3100000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + vreg_l8b_3p3: ldo8 {
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3312000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + /*
>> + * Downstream specifies a fixed voltage of 3.312 V, but the
>> + * PMIC4 BOB ranges don't support that. Widen the range a
>> + * little to avoid adding a new BOB regulator type.
>
> Maybe the upstream driver is wrong then. Could somebody with docs recheck
> that?
I'm not sure if this is relevant, but the RPM regulator driver doesn't
support 3.312 V either.
>
> And also pm8350 & pm8350c ranges while at it, pretty please?
>
>
>> + */
>> + vreg_bob: bob {
>> + regulator-min-microvolt = <3296000>;
>> + regulator-max-microvolt = <3328000>;
>> + regulator-enable-ramp-delay = <500>;
>> + };
>> + };
>> +
>> + pm660-regulators {
>> + compatible = "qcom,pm660-rpmh-regulators";
>> + qcom,pmic-id = "a";
>> +
>> + vdd-s1-supply = <&vph_pwr>;
>> + vdd-s2-supply = <&vph_pwr>;
>> + vdd-s3-supply = <&vph_pwr>;
>> + vdd-s4-supply = <&vph_pwr>;
>> + vdd-s5-supply = <&vph_pwr>;
>> + vdd-s6-supply = <&vph_pwr>;
>> +
>> + vdd-l1-l6-l7-supply = <&vreg_s6a_1p29>;
>> + vdd-l2-l3-supply = <&vreg_s2b_1p05>;
>> + vdd-l5-supply = <&vreg_s2b_1p05>;
>> + vdd-l8-l9-l10-l11-l12-l13-l14-supply = <&vreg_s4a_1p92>;
>> + vdd-l15-l16-l17-l18-l19-supply = <&vreg_bob>;
>> +
>> + /*
>> + * S1A (FTAPC0), S2A (FTAPC1), S3A (HFAPC1) are managed
>> + * by the Core Power Reduction hardened (CPRh) and the
>> + * Operating State Manager (OSM) HW automatically.
>> + */
>> +
>> + vreg_s4a_1p92: smps4 {
>> + regulator-min-microvolt = <1808000>;
>> + regulator-max-microvolt = <2040000>;
>> + regulator-enable-ramp-delay = <200>;
>> + };
>> +
>> + vreg_s6a_1p29: smps6 {
>> + regulator-min-microvolt = <1224000>;
>> + regulator-max-microvolt = <1352000>;
>> + regulator-enable-ramp-delay = <150>;
>> + };
>> +
>> + /* LDOs */
>> + vreg_l1a_1p225: ldo1 {
>> + regulator-min-microvolt = <1200000>;
>> + regulator-max-microvolt = <1250000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + vreg_l2a_1p0: ldo2 {
>> + regulator-min-microvolt = <1000000>;
>> + regulator-max-microvolt = <1000000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + vreg_l3a_1p0: ldo3 {
>> + regulator-min-microvolt = <1000000>;
>> + regulator-max-microvolt = <1000000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + vreg_l5a_0p8: ldo5 {
>> + regulator-min-microvolt = <800000>;
>> + regulator-max-microvolt = <800000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + vreg_l6a_1p28: ldo6 {
>> + regulator-min-microvolt = <1248000>;
>> + regulator-max-microvolt = <1304000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + vreg_l7a_1p2: ldo7 {
>> + regulator-min-microvolt = <1200000>;
>> + regulator-max-microvolt = <1200000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + vreg_l8a_1p8: ldo8 {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + vreg_l9a_1p8: ldo9 {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + vreg_l10a_1p8: ldo10 {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + vreg_l11a_1p8: ldo11 {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + vreg_l12a_1p8: ldo12 {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + vreg_l13a_1p8: ldo13 {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + vreg_l14a_1p8: ldo14 {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + vreg_l15a_2p38: ldo15 {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <2950000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + vreg_l16a_2p7: ldo16 {
>> + regulator-min-microvolt = <2696000>;
>> + regulator-max-microvolt = <2696000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + vreg_l17a_2p38: ldo17 {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <2950000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> +
>> + vreg_l19a_3p3: ldo19 {
>> + regulator-min-microvolt = <3000000>;
>> + regulator-max-microvolt = <3312000>;
>> + regulator-enable-ramp-delay = <250>;
>> + };
>> + };
>> +};
>> +
>> +&gpi_dma1 {
>> + status = "okay";
>> +};
>> +
>> +&qupv3_id_1 {
>> + status = "okay";
>> +};
>
> Please sort the & references alphabetically.
Sorted for v2.
>
>
>> +
>> +&i2c9 {
>> + status = "okay";
>
> status should be the last property (still before subnodes - otherwise you'll
> get a DTC error).
>
> This applies to all occurences.
Moved.
>
>
>> + clock-frequency = <100000>;
>> +
>> + synaptics-rmi4-i2c@20 {
>> + compatible = "syna,rmi4-i2c";
>> + reg = <0x20>;
>> + #address-cells = <0x1>;
>> + #size-cells = <0x0>;
>> + interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>;
>> +
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&touchscreen_default>;
>> +
>> + /* VDD supply isn't specified, bind it to power */
>
> I don't think it would explode if you just removed it then?
Confirmed and removed for v2.
>
>
>> + vdd-supply = <&vph_pwr>;
>> + vio-supply = <&ts_1p8_supply>;
>> +
>> + syna,reset-delay-ms = <200>;
>> + syna,startup-delay-ms = <200>;
>> +
>> + rmi4-f01@1 {
>> + reg = <0x01>;
>> + syna,nosleep-mode = <1>;
>> + };
>> +
>> + rmi4-f12@12 {
>> + reg = <0x12>;
>> + touchscreen-x-mm = <62>;
>> + touchscreen-y-mm = <127>;
>> + syna,sensor-type = <1>;
>> + };
>> + };
>> +};
>> +
>> +&gcc {
>> + protected-clocks = <GCC_QSPI_CORE_CLK>,
>> + <GCC_QSPI_CORE_CLK_SRC>,
>> + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>;
>> +};
>> +
>> +&pm660l_gpios {
>> + vol_up_pin: vol-up-state {
>> + pins = "gpio7";
>> + function = "normal";
>> + qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
>> + input-enable;
>> + bias-pull-up;
>> + };
>> +};
>> +
>> +&pon_pwrkey {
>> + status = "okay";
>> +};
>> +
>> +&pon_resin {
>> + status = "okay";
>> + linux,code = <KEY_VOLUMEDOWN>;
>> +};
>> +
>> +&sdhc_1 {
>> + status = "okay";
>> + supports-cqe;
>> + mmc-hs200-1_8v;
>> + mmc-hs400-1_8v;
>> + mmc-ddr-1_8v;
>> +
>> + qcom,ddr-config = <0xc3040873>;
>> +
>> + vmmc-supply = <&vreg_l4b_2p96>;
>> + vqmmc-supply = <&vreg_l8a_1p8>;
>> +};
>> +
>> +&tlmm {
>> + gpio-reserved-ranges = <0 4>, <81 4>;
>> +
>> + touchscreen_default: ts-default-state {
>> + ts-reset-pins {
>> + pins = "gpio99";
>> + function = "gpio";
>> + drive-strength = <2>;
>> + bias-pull-up;
>> + output-high;
>> + };
>> +
>> + ts-irq-pins {
>> + pins = "gpio125";
>> + function = "gpio";
>> + drive-strength = <2>;
>> + bias-disable;
>> + };
>> +
>> + ts-switch-pins {
>> + pins = "gpio135";
>> + function = "gpio";
>> + drive-strength = <2>;
>> + bias-disable;
>> + output-low;
>> + };
>> + };
>> +};
>> +
>> +&usb_1_hsphy {
>> + status = "okay";
>> +
>> + vdd-supply = <&vreg_l1b_0p89>;
>> + vdda-pll-supply = <&vreg_l10a_1p8>;
>> + vdda-phy-dpdm-supply = <&vreg_l7b_3p1>;
>> +};
>> +
>> +&usb_1 {
>> + status = "okay";
>> +
>> + qcom,select-utmi-as-pipe-clk;
>> +};
>> +
>> +&usb_1_dwc3 {
>> + /* Only peripheral works for now */
>> + dr_mode = "peripheral";
>> +
>> + /* Do not assume that sdm670.dtsi will never support USB 3.0 */
>> + phys = <&usb_1_hsphy>;
>> + phy-names = "usb2-phy";
>> + maximum-speed = "high-speed";
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
>> new file mode 100644
>> index 000000000000..4450ece839a0
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
>> @@ -0,0 +1,1216 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * SDM670 SoC device tree source, adapted from SDM845 SoC device tree
>> + *
>> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2022, Richard Acayan. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/clock/qcom,gcc-sdm845.h>
>> +#include <dt-bindings/clock/qcom,rpmh.h>
>> +#include <dt-bindings/dma/qcom-gpi.h>
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/phy/phy-qcom-qusb2.h>
>> +#include <dt-bindings/power/qcom-rpmpd.h>
>> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
>> +
>> +/ {
>> + interrupt-parent = <&intc>;
>> +
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + aliases { };
>> +
>> + chosen { };
>> +
>> + memory@80000000 {
>> + device_type = "memory";
>> + /* We expect the bootloader to fill in the size */
>> + reg = <0 0x80000000 0 0>;
>> + };
>> +
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + hyp_mem: hyp-mem@85700000 {
>> + reg = <0 0x85700000 0 0x600000>;
>> + no-map;
>> + };
>> +
>> + xbl_mem: xbl-mem@85e00000 {
>> + reg = <0 0x85e00000 0 0x100000>;
>> + no-map;
>> + };
>> +
>> + aop_mem: aop-mem@85fc0000 {
>> + reg = <0 0x85fc0000 0 0x20000>;
>> + no-map;
>> + };
>> +
>> + aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
>> + compatible = "qcom,cmd-db";
>> + reg = <0x0 0x85fe0000 0 0x20000>;
>> + no-map;
>> + };
>> +
>> + camera_mem: camera-mem@8ab00000 {
>> + reg = <0 0x8ab00000 0 0x500000>;
>> + no-map;
>> + };
>> +
>> + mpss_region: mpss@8b000000 {
>> + reg = <0 0x8b000000 0 0x7e00000>;
>> + no-map;
>> + };
>> +
>> + venus_mem: venus@92e00000 {
>> + reg = <0 0x92e00000 0 0x500000>;
>> + no-map;
>> + };
>> +
>> + wlan_msa_mem: wlan-msa@93300000 {
>> + reg = <0 0x93300000 0 0x100000>;
>> + no-map;
>> + };
>> +
>> + cdsp_mem: cdsp@93400000 {
>> + reg = <0 0x93400000 0 0x800000>;
>> + no-map;
>> + };
>> +
>> + mba_region: mba@93c00000 {
>> + reg = <0 0x93c00000 0 0x200000>;
>> + no-map;
>> + };
>> +
>> + adsp_mem: adsp@93e00000 {
>> + reg = <0 0x93e00000 0 0x1e00000>;
>> + no-map;
>> + };
>> +
>> + ipa_fw_mem: ipa-fw@95c00000 {
>> + reg = <0 0x95c00000 0 0x10000>;
>> + no-map;
>> + };
>> +
>> + ipa_gsi_mem: ipa-gsi@95c10000 {
>> + reg = <0 0x95c10000 0 0x5000>;
>> + no-map;
>> + };
>> +
>> + gpu_mem: gpu@95c15000 {
>> + reg = <0 0x95c15000 0 0x2000>;
>> + no-map;
>> + };
>> +
>> + spss_mem: spss@97b00000 {
>> + reg = <0 0x97b00000 0 0x100000>;
>> + no-map;
>> + };
>> +
>> + qseecom_mem: qseecom@9e400000 {
>> + reg = <0 0x9e400000 0 0x1400000>;
>> + no-map;
>> + };
>> + };
>> +
>> + cpus {
>> + #address-cells = <2>;
>> + #size-cells = <0>;
>> +
>> + CPU0: cpu@0 {
>> + device_type = "cpu";
>> + compatible = "qcom,kryo360";
>> + reg = <0x0 0x0>;
>> + enable-method = "psci";
>> + power-domains = <&CPU_PD0>;
>> + power-domain-names = "psci";
>> + next-level-cache = <&L2_0>;
>> + L2_0: l2-cache {
>> + compatible = "cache";
>> + next-level-cache = <&L3_0>;
>> + L3_0: l3-cache {
>> + compatible = "cache";
>> + };
>> + };
>> + };
>> +
>> + CPU1: cpu@100 {
>> + device_type = "cpu";
>> + compatible = "qcom,kryo360";
>> + reg = <0x0 0x100>;
>> + enable-method = "psci";
>> + power-domains = <&CPU_PD1>;
>> + power-domain-names = "psci";
>> + next-level-cache = <&L2_100>;
>> + L2_100: l2-cache {
>> + compatible = "cache";
>> + next-level-cache = <&L3_0>;
>> + };
>> + };
>> +
>> + CPU2: cpu@200 {
>> + device_type = "cpu";
>> + compatible = "qcom,kryo360";
>> + reg = <0x0 0x200>;
>> + enable-method = "psci";
>> + power-domains = <&CPU_PD2>;
>> + power-domain-names = "psci";
>> + next-level-cache = <&L2_200>;
>> + L2_200: l2-cache {
>> + compatible = "cache";
>> + next-level-cache = <&L3_0>;
>> + };
>> + };
>> +
>> + CPU3: cpu@300 {
>> + device_type = "cpu";
>> + compatible = "qcom,kryo360";
>> + reg = <0x0 0x300>;
>> + enable-method = "psci";
>> + power-domains = <&CPU_PD3>;
>> + power-domain-names = "psci";
>> + next-level-cache = <&L2_300>;
>> + L2_300: l2-cache {
>> + compatible = "cache";
>> + next-level-cache = <&L3_0>;
>> + };
>> + };
>> +
>> + CPU4: cpu@400 {
>> + device_type = "cpu";
>> + compatible = "qcom,kryo360";
>> + reg = <0x0 0x400>;
>> + enable-method = "psci";
>> + power-domains = <&CPU_PD4>;
>> + power-domain-names = "psci";
>> + next-level-cache = <&L2_400>;
>> + L2_400: l2-cache {
>> + compatible = "cache";
>> + next-level-cache = <&L3_0>;
>> + };
>> + };
>> +
>> + CPU5: cpu@500 {
>> + device_type = "cpu";
>> + compatible = "qcom,kryo360";
>> + reg = <0x0 0x500>;
>> + enable-method = "psci";
>> + power-domains = <&CPU_PD5>;
>> + power-domain-names = "psci";
>> + next-level-cache = <&L2_500>;
>> + L2_500: l2-cache {
>> + compatible = "cache";
>> + next-level-cache = <&L3_0>;
>> + };
>> + };
>> +
>> + CPU6: cpu@600 {
>> + device_type = "cpu";
>> + compatible = "qcom,kryo360";
>> + reg = <0x0 0x600>;
>> + enable-method = "psci";
>> + power-domains = <&CPU_PD6>;
>> + power-domain-names = "psci";
>> + next-level-cache = <&L2_600>;
>> + L2_600: l2-cache {
>> + compatible = "cache";
>> + next-level-cache = <&L3_0>;
>> + };
>> + };
>> +
>> + CPU7: cpu@700 {
>> + device_type = "cpu";
>> + compatible = "qcom,kryo360";
>> + reg = <0x0 0x700>;
>> + enable-method = "psci";
>> + power-domains = <&CPU_PD7>;
>> + power-domain-names = "psci";
>> + next-level-cache = <&L2_700>;
>> + L2_700: l2-cache {
>> + compatible = "cache";
>> + next-level-cache = <&L3_0>;
>> + };
>> + };
>> +
>> + cpu-map {
>> + cluster0 {
>> + core0 {
>> + cpu = <&CPU0>;
>> + };
>> +
>> + core1 {
>> + cpu = <&CPU1>;
>> + };
>> +
>> + core2 {
>> + cpu = <&CPU2>;
>> + };
>> +
>> + core3 {
>> + cpu = <&CPU3>;
>> + };
>> +
>> + core4 {
>> + cpu = <&CPU4>;
>> + };
>> +
>> + core5 {
>> + cpu = <&CPU5>;
>> + };
>> +
>> + core6 {
>> + cpu = <&CPU6>;
>> + };
>> +
>> + core7 {
>> + cpu = <&CPU7>;
>> + };
>> + };
>> + };
>> +
>> + idle-states {
>> + entry-method = "psci";
>> +
>> + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
>> + compatible = "arm,idle-state";
>> + idle-state-name = "little-rail-power-collapse";
>> + arm,psci-suspend-param = <0x40000004>;
>> + entry-latency-us = <702>;
>> + exit-latency-us = <915>;
>> + min-residency-us = <1617>;
>> + local-timer-stop;
>> + };
>> +
>> + BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
>> + compatible = "arm,idle-state";
>> + idle-state-name = "big-rail-power-collapse";
>> + arm,psci-suspend-param = <0x40000004>;
>> + entry-latency-us = <526>;
>> + exit-latency-us = <1854>;
>> + min-residency-us = <2380>;
>> + local-timer-stop;
>> + };
>> + };
>> +
>> + domain-idle-states {
>> + CLUSTER_SLEEP_0: cluster-sleep-0 {
>> + compatible = "domain-idle-state";
>> + arm,psci-suspend-param = <0x4100c244>;
>> + entry-latency-us = <3263>;
>> + exit-latency-us = <6562>;
>> + min-residency-us = <9825>;
>> + };
>> + };
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
>> + <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
>> + <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
>> + <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
>> + };
>> +
>> + clocks {
>
> Please sort nodes alphabetically.
Sorted for next version.
>
>
>> + xo_board: xo-board {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <38400000>;
>
> clock-frequency should be moved to the board DTS to indicate it's not
>
> a part of the SoC itself, but rather it sits on the board.
I don't know if you got this, because it wasn't sent to you directly,
but this thread suggests that the entire clocks should perhaps move:
https://lore.kernel.org/linux-arm-msm/bb2e92c8-8e19-8840-c1ec-8c7ef667fdbf@quicinc.com/
Full context:
https://lore.kernel.org/linux-arm-msm/Y1GCs6uCz5o9az+v@gerhold.net/
Should I move the entire clocks node?
>
>
>> + clock-output-names = "xo_board";
>
> This should actually not be necessary, if you pass "xo" to rpmcc..
Confirmed, it is not.
>
>
>
>> + };
>> +
>> + sleep_clk: sleep-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <32764>;
>> + };
>> + };
>> +
>> + firmware {
>> + scm {
>> + compatible = "qcom,scm-sdm670", "qcom,scm";
>> + };
>> + };
>> +
>> + psci {
>> + compatible = "arm,psci-1.0";
>> + method = "smc";
>> +
>> + CPU_PD0: power-domain-cpu0 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> + };
>> +
>> + CPU_PD1: power-domain-cpu1 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> + };
>> +
>> + CPU_PD2: power-domain-cpu2 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> + };
>> +
>> + CPU_PD3: power-domain-cpu3 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> + };
>> +
>> + CPU_PD4: power-domain-cpu4 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> + };
>> +
>> + CPU_PD5: power-domain-cpu5 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> + };
>> +
>> + CPU_PD6: power-domain-cpu6 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
>> + };
>> +
>> + CPU_PD7: power-domain-cpu7 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
>> + };
>> +
>> + CLUSTER_PD: power-domain-cluster {
>> + #power-domain-cells = <0>;
>> + domain-idle-states = <&CLUSTER_SLEEP_0>;
>> + };
>> + };
>> +
>> + soc: soc@0 {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges = <0 0 0 0 0x10 0>;
>> + dma-ranges = <0 0 0 0 0x10 0>;
>> + compatible = "simple-bus";
>> +
>> + gcc: clock-controller@100000 {
>> + compatible = "qcom,gcc-sdm670";
>> + reg = <0 0x00100000 0 0x1f0000>;
>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
>> + <&rpmhcc RPMH_CXO_CLK_A>,
>> + <&sleep_clk>;
>> + clock-names = "bi_tcxo",
>> + "bi_tcxo_ao",
>> + "sleep_clk";
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + };
>> +
>> + sdhc_1: mmc@7c4000 {
>> + compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5";
>> + reg = <0 0x007c4000 0 0x1000>,
>> + <0 0x007c5000 0 0x1000>,
>> + <0 0x007c8000 0 0x8000>;
>> + reg-names = "hc", "cqhci", "ice";
>> +
>> + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "hc_irq", "pwr_irq";
>> +
>> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
>> + <&gcc GCC_SDCC1_APPS_CLK>,
>> + <&rpmhcc RPMH_CXO_CLK>,
>> + <&gcc GCC_SDCC1_ICE_CORE_CLK>,
>> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
>> + clock-names = "iface", "core", "xo", "ice", "bus";
>> +
>> + iommus = <&apps_smmu 0x140 0xf>;
>> +
>> + pinctrl-names = "default", "sleep";
>> + pinctrl-0 = <&sdc1_state_on>;
>> + pinctrl-1 = <&sdc1_state_off>;
>> + power-domains = <&rpmhpd SDM670_CX>;
>> +
>> + bus-width = <8>;
>> + non-removable;
>> +
>> + status = "disabled";
>> + };
>> +
>> + gpi_dma0: dma-controller@800000 {
>> + #dma-cells = <3>;
>> + compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
>> + reg = <0 0x00800000 0 0x60000>;
>> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
>> + dma-channels = <13>;
>> + dma-channel-mask = <0xfa>;
>> + iommus = <&apps_smmu 0x0016 0x0>;
>> + status = "disabled";
>> + };
>> +
>> + qupv3_id_0: geniqup@8c0000 {
>> + compatible = "qcom,geni-se-qup";
>> + reg = <0 0x008c0000 0 0x6000>;
>> + clock-names = "m-ahb", "s-ahb";
>> + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
>> + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
>> + iommus = <&apps_smmu 0x3 0x0>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
>> + interconnect-names = "qup-core";
>> + status = "disabled";
>> +
>> + i2c0: i2c@880000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x00880000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c0_default>;
>> + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SDM670_CX>;
>> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
>> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
>> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
>> + interconnect-names = "qup-core", "qup-config", "qup-memory";
>> + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
>> + <&gpi_dma0 1 0 QCOM_GPI_I2C>;
>> + dma-names = "tx", "rx";
>> + status = "disabled";
>> + };
>> +
>> + i2c1: i2c@884000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x00884000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c1_default>;
>> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SDM670_CX>;
>> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
>> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
>> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
>> + interconnect-names = "qup-core", "qup-config", "qup-memory";
>> + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
>> + <&gpi_dma0 1 1 QCOM_GPI_I2C>;
>> + dma-names = "tx", "rx";
>> + status = "disabled";
>> + };
>> +
>> + i2c2: i2c@888000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x00888000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c2_default>;
>> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SDM670_CX>;
>> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
>> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
>> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
>> + interconnect-names = "qup-core", "qup-config", "qup-memory";
>> + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
>> + <&gpi_dma0 1 2 QCOM_GPI_I2C>;
>> + dma-names = "tx", "rx";
>> + status = "disabled";
>> + };
>> +
>> + i2c3: i2c@88c000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x0088c000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c3_default>;
>> + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SDM670_CX>;
>> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
>> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
>> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
>> + interconnect-names = "qup-core", "qup-config", "qup-memory";
>> + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
>> + <&gpi_dma0 1 3 QCOM_GPI_I2C>;
>> + dma-names = "tx", "rx";
>> + status = "disabled";
>> + };
>> +
>> + i2c4: i2c@890000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x00890000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c4_default>;
>> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SDM670_CX>;
>> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
>> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
>> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
>> + interconnect-names = "qup-core", "qup-config", "qup-memory";
>> + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
>> + <&gpi_dma0 1 4 QCOM_GPI_I2C>;
>> + dma-names = "tx", "rx";
>> + status = "disabled";
>> + };
>> +
>> + i2c5: i2c@894000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x00894000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c5_default>;
>> + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SDM670_CX>;
>> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
>> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
>> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
>> + interconnect-names = "qup-core", "qup-config", "qup-memory";
>> + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
>> + <&gpi_dma0 1 5 QCOM_GPI_I2C>;
>> + dma-names = "tx", "rx";
>> + status = "disabled";
>> + };
>> +
>> + i2c6: i2c@898000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x00898000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c6_default>;
>> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SDM670_CX>;
>> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
>> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
>> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
>> + interconnect-names = "qup-core", "qup-config", "qup-memory";
>> + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
>> + <&gpi_dma0 1 6 QCOM_GPI_I2C>;
>> + dma-names = "tx", "rx";
>> + status = "disabled";
>> + };
>> +
>> + i2c7: i2c@89c000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x0089c000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c7_default>;
>> + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SDM670_CX>;
>> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
>> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
>> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
>> + interconnect-names = "qup-core", "qup-config", "qup-memory";
>> + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
>> + <&gpi_dma0 1 7 QCOM_GPI_I2C>;
>> + dma-names = "tx", "rx";
>> + status = "disabled";
>> + };
>> + };
>> +
>> + gpi_dma1: dma-controller@a00000 {
>> + #dma-cells = <3>;
>> + compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
>> + reg = <0 0x00a00000 0 0x60000>;
>> + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
>> + dma-channels = <13>;
>> + dma-channel-mask = <0xfa>;
>> + iommus = <&apps_smmu 0x06d6 0x0>;
>> + status = "disabled";
>> + };
>> +
>> + qupv3_id_1: geniqup@ac0000 {
>> + compatible = "qcom,geni-se-qup";
>> + reg = <0 0x00ac0000 0 0x6000>;
>> + clock-names = "m-ahb", "s-ahb";
>> + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
>> + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
>> + iommus = <&apps_smmu 0x6c3 0x0>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> + status = "disabled";
>> +
>> + i2c8: i2c@a80000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x00a80000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c8_default>;
>> + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SDM670_CX>;
>> + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
>> + <&gpi_dma1 1 0 QCOM_GPI_I2C>;
>> + dma-names = "tx", "rx";
>> + status = "disabled";
>> + };
>> +
>> + i2c9: i2c@a84000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x00a84000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c9_default>;
>> + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SDM670_CX>;
>> + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
>> + <&gpi_dma1 1 1 QCOM_GPI_I2C>;
>> + dma-names = "tx", "rx";
>> + status = "disabled";
>> + };
>> +
>> + i2c10: i2c@a88000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x00a88000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c10_default>;
>> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SDM670_CX>;
>> + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
>> + <&gpi_dma1 1 2 QCOM_GPI_I2C>;
>> + dma-names = "tx", "rx";
>> + status = "disabled";
>> + };
>> +
>> + i2c11: i2c@a8c000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x00a8c000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c11_default>;
>> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SDM670_CX>;
>> + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
>> + <&gpi_dma1 1 3 QCOM_GPI_I2C>;
>> + dma-names = "tx", "rx";
>> + status = "disabled";
>> + };
>> +
>> + i2c12: i2c@a90000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x00a90000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c12_default>;
>> + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SDM670_CX>;
>> + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
>> + <&gpi_dma1 1 4 QCOM_GPI_I2C>;
>> + dma-names = "tx", "rx";
>> + status = "disabled";
>> + };
>> +
>> + i2c13: i2c@a94000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x00a94000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c13_default>;
>> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SDM670_CX>;
>> + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
>> + <&gpi_dma1 1 5 QCOM_GPI_I2C>;
>> + dma-names = "tx", "rx";
>> + status = "disabled";
>> + };
>> +
>> + i2c14: i2c@a98000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x00a98000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c14_default>;
>> + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SDM670_CX>;
>> + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
>> + <&gpi_dma1 1 6 QCOM_GPI_I2C>;
>> + dma-names = "tx", "rx";
>> + status = "disabled";
>> + };
>> +
>> + i2c15: i2c@a9c000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x00a9c000 0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_i2c15_default>;
>> + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + power-domains = <&rpmhpd SDM670_CX>;
>> + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
>> + <&gpi_dma1 1 7 QCOM_GPI_I2C>;
>> + dma-names = "tx", "rx";
>> + status = "disabled";
>> + };
>> + };
>> +
>> + tlmm: pinctrl@3400000 {
>> + compatible = "qcom,sdm670-tlmm";
>> + reg = <0 0x03400000 0 0xc00000>;
>> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + gpio-ranges = <&tlmm 0 0 151>;
>> +
>> + qup_i2c0_default: qup-i2c0-default-state {
>> + pins = "gpio0", "gpio1";
>> + function = "qup0";
>> + };
>> +
>> + qup_i2c1_default: qup-i2c1-default-state {
>> + pins = "gpio17", "gpio18";
>> + function = "qup1";
>> + };
>> +
>> + qup_i2c2_default: qup-i2c2-default-state {
>> + pins = "gpio27", "gpio28";
>> + function = "qup2";
>> + };
>> +
>> + qup_i2c3_default: qup-i2c3-default-state {
>> + pins = "gpio41", "gpio42";
>> + function = "qup3";
>> + };
>> +
>> + qup_i2c4_default: qup-i2c4-default-state {
>> + pins = "gpio89", "gpio90";
>> + function = "qup4";
>> + };
>> +
>> + qup_i2c5_default: qup-i2c5-default-state {
>> + pins = "gpio85", "gpio86";
>> + function = "qup5";
>> + };
>> +
>> + qup_i2c6_default: qup-i2c6-default-state {
>> + pins = "gpio45", "gpio46";
>> + function = "qup6";
>> + };
>> +
>> + qup_i2c7_default: qup-i2c7-default-state {
>> + pins = "gpio93", "gpio94";
>> + function = "qup7";
>> + };
>> +
>> + qup_i2c8_default: qup-i2c8-default-state {
>> + pins = "gpio65", "gpio66";
>> + function = "qup8";
>> + };
>> +
>> + qup_i2c9_default: qup-i2c9-default-state {
>> + pins = "gpio6", "gpio7";
>> + function = "qup9";
>> + };
>> +
>> + qup_i2c10_default: qup-i2c10-default-state {
>> + pins = "gpio55", "gpio56";
>> + function = "qup10";
>> + };
>> +
>> + qup_i2c11_default: qup-i2c11-default-state {
>> + pins = "gpio31", "gpio32";
>> + function = "qup11";
>> + };
>> +
>> + qup_i2c12_default: qup-i2c12-default-state {
>> + pins = "gpio49", "gpio50";
>> + function = "qup12";
>> + };
>> +
>> + qup_i2c13_default: qup-i2c13-default-state {
>> + pins = "gpio105", "gpio106";
>> + function = "qup13";
>> + };
>> +
>> + qup_i2c14_default: qup-i2c14-default-state {
>> + pins = "gpio33", "gpio34";
>> + function = "qup14";
>> + };
>> +
>> + qup_i2c15_default: qup-i2c15-default-state {
>> + pins = "gpio81", "gpio82";
>> + function = "qup15";
>> + };
>> +
>> + sdc1_state_on: sdc1-on-state {
>> + clk-pins {
>> + pins = "sdc1_clk";
>> + bias-disable;
>> + drive-strength = <16>;
>> + };
>> +
>> + cmd-pins {
>> + pins = "sdc1_cmd";
>> + bias-pull-up;
>> + drive-strength = <10>;
>> + };
>> +
>> + data-pins {
>> + pins = "sdc1_data";
>> + bias-pull-up;
>> + drive-strength = <10>;
>> + };
>> +
>> + rclk-pins {
>> + pins = "sdc1_rclk";
>> + bias-pull-down;
>> + };
>> + };
>> +
>> + sdc1_state_off: sdc1-off-state {
>> + clk-pins {
>> + pins = "sdc1_clk";
>> + bias-disable;
>> + drive-strength = <2>;
>> + };
>> +
>> + cmd-pins {
>> + pins = "sdc1_cmd";
>> + bias-pull-up;
>> + drive-strength = <2>;
>> + };
>> +
>> + data-pins {
>> + pins = "sdc1_data";
>> + bias-pull-up;
>> + drive-strength = <2>;
>> + };
>> +
>> + rclk-pins {
>> + pins = "sdc1_rclk";
>> + bias-pull-down;
>> + };
>> + };
>> + };
>> +
>> + usb_1_hsphy: phy@88e2000 {
>> + compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy";
>> + reg = <0 0x088e2000 0 0x400>;
>> + status = "disabled";
>
> Status last, please.
Moved (also moved the prop in usb_1).
>
>
>> + #phy-cells = <0>;
>> +
>> + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
>> + <&rpmhcc RPMH_CXO_CLK>;
>> + clock-names = "cfg_ahb", "ref";
>> +
>> + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
>> + };
>> +
>> + usb_1: usb@a6f8800 {
>> + compatible = "qcom,sdm670-dwc3", "qcom,dwc3";
>> + reg = <0 0x0a6f8800 0 0x400>;
>> + status = "disabled";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> + dma-ranges;
>> +
>> + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
>> + <&gcc GCC_USB30_PRIM_MASTER_CLK>,
>> + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
>> + <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
>> + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
>> + clock-names = "cfg_noc",
>> + "core",
>> + "iface",
>> + "sleep",
>> + "mock_utmi";
>> +
>> + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
>> + <&gcc GCC_USB30_PRIM_MASTER_CLK>;
>> + assigned-clock-rates = <19200000>, <150000000>;
>> +
>> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "hs_phy_irq", "ss_phy_irq",
>> + "dm_hs_phy_irq", "dp_hs_phy_irq";
>> +
>> + power-domains = <&gcc USB30_PRIM_GDSC>;
>> +
>> + resets = <&gcc GCC_USB30_PRIM_BCR>;
>> +
>> + usb_1_dwc3: usb@a600000 {
>> + compatible = "snps,dwc3";
>> + reg = <0 0x0a600000 0 0xcd00>;
>> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
>> + iommus = <&apps_smmu 0x740 0>;
>> + snps,dis_u2_susphy_quirk;
>> + snps,dis_enblslpm_quirk;
>> + phys = <&usb_1_hsphy>;
>> + phy-names = "usb2-phy";
>> + };
>> + };
>> +
>> + spmi_bus: spmi@c440000 {
>> + compatible = "qcom,spmi-pmic-arb";
>> + reg = <0 0x0c440000 0 0x1100>,
>> + <0 0x0c600000 0 0x2000000>,
>> + <0 0x0e600000 0 0x100000>,
>> + <0 0x0e700000 0 0xa0000>,
>> + <0 0x0c40a000 0 0x26000>;
>> + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
>> + interrupt-names = "periph_irq";
>> + interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
>> + qcom,ee = <0>;
>> + qcom,channel = <0>;
>> + #address-cells = <2>;
>> + #size-cells = <0>;
>> + interrupt-controller;
>> + #interrupt-cells = <4>;
>> + };
>> +
>> + apps_smmu: iommu@15000000 {
>> + /*
>> + * The hardware tolerates the SDM845 reset quirk. The
>> + * iommu maintainers aren't responding to any patches
>> + * that would add support for new platforms. Set this
>> + * compatible so this dtsi is valid and functional.
>
> Not sure if this is the right approach. SDM670 is more or less a factory
> reject 845,
>
> but the software stack may be hiding some differences..
This compat string is why I don't want this applied just yet.
>
>
> Konrad
>
>> + */
>> + compatible = "qcom,sdm845-smmu-500", "qcom,smmu-500", "arm,mmu-500";
>> + reg = <0 0x15000000 0 0x80000>;
>> + #iommu-cells = <2>;
>> + #global-interrupts = <1>;
>> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + apps_rsc: rsc@179c0000 {
>> + label = "apps_rsc";
>> + compatible = "qcom,rpmh-rsc";
>> + reg = <0 0x179c0000 0 0x10000>,
>> + <0 0x179d0000 0 0x10000>,
>> + <0 0x179e0000 0 0x10000>;
>> + reg-names = "drv-0", "drv-1", "drv-2";
>> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
>> + qcom,tcs-offset = <0xd00>;
>> + qcom,drv-id = <2>;
>> + qcom,tcs-config = <ACTIVE_TCS 2>,
>> + <SLEEP_TCS 3>,
>> + <WAKE_TCS 3>,
>> + <CONTROL_TCS 1>;
>> +
>> + apps_bcm_voter: bcm-voter {
>> + compatible = "qcom,bcm-voter";
>> + };
>> +
>> + rpmhcc: clock-controller {
>> + compatible = "qcom,sdm670-rpmh-clk";
>> + #clock-cells = <1>;
>> + clock-names = "xo";
>> + clocks = <&xo_board>;
>> + };
>> +
>> + rpmhpd: power-controller {
>> + compatible = "qcom,sdm670-rpmhpd";
>> + #power-domain-cells = <1>;
>> + operating-points-v2 = <&rpmhpd_opp_table>;
>> +
>> + rpmhpd_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + rpmhpd_opp_ret: opp1 {
>> + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
>> + };
>> +
>> + rpmhpd_opp_min_svs: opp2 {
>> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
>> + };
>> +
>> + rpmhpd_opp_low_svs: opp3 {
>> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>> + };
>> +
>> + rpmhpd_opp_svs: opp4 {
>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
>> + };
>> +
>> + rpmhpd_opp_svs_l1: opp5 {
>> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
>> + };
>> +
>> + rpmhpd_opp_nom: opp6 {
>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
>> + };
>> +
>> + rpmhpd_opp_nom_l1: opp7 {
>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
>> + };
>> +
>> + rpmhpd_opp_nom_l2: opp8 {
>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
>> + };
>> +
>> + rpmhpd_opp_turbo: opp9 {
>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
>> + };
>> +
>> + rpmhpd_opp_turbo_l1: opp10 {
>> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + intc: interrupt-controller@17a00000 {
>> + compatible = "arm,gic-v3";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> + #interrupt-cells = <3>;
>> + interrupt-controller;
>> + reg = <0 0x17a00000 0 0x10000>, /* GICD */
>> + <0 0x17a60000 0 0x100000>; /* GICR * 8 */
>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> + };
>> +};
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 4/4] arm64: dts: qcom: add sdm670 and pixel 3a device trees
2022-11-01 23:57 ` [PATCH 4/4] arm64: dts: qcom: add sdm670 and pixel 3a device trees Richard Acayan
2022-11-02 2:19 ` Richard Acayan
2022-11-02 20:26 ` Konrad Dybcio
@ 2022-11-03 1:19 ` Richard Acayan
2022-11-03 20:34 ` kernel test robot
3 siblings, 0 replies; 16+ messages in thread
From: Richard Acayan @ 2022-11-03 1:19 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Robin Murphy, Chanho Park,
Thierry Reding, Stephan Gerhold, Lorenzo Pieralisi, Robert Marko,
Das Srinagesh, devicetree, linux-kernel, linux-arm-msm
Cc: ~postmarketos/upstreaming, phone-devel
On Tue, Nov 01, 2022 at 07:57:22PM -0400, Richard Acayan wrote:
> The Qualcomm Snapdragon 670 has been out for a while. Add a device tree
> for it and the Google Pixel 3a as the first device.
>
> The Pixel 3a has the same bootloader issue as the Pixel 3 and will not work
> on Android 10 bootloaders or later until it gets fixed for the Pixel 3.
>
> SoC Initial Features:
> - power management
> - clocks
> - pinctrl
> - eMMC
> - USB 2.0
> - GENI I2C
> - IOMMU
> - RPMh
> - interrupts
>
> Device-Specific Initial Features:
> - side buttons (keys)
> - regulators
> - touchscreen
>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> .../boot/dts/qcom/sdm670-google-sargo.dts | 519 +++++++
> arch/arm64/boot/dts/qcom/sdm670.dtsi | 1216 +++++++++++++++++
> 3 files changed, 1736 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
> create mode 100644 arch/arm64/boot/dts/qcom/sdm670.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index b0558d3389e5..4eb5d8829efb 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -124,6 +124,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm632-fairphone-fp3.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
> diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
> new file mode 100644
> index 000000000000..fa3dee78e442
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts
> @@ -0,0 +1,519 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device tree for Google Pixel 3a, adapted from google-blueline device tree,
> + * xiaomi-lavender device tree, and oneplus-common device tree.
> + *
> + * Copyright (c) 2022, Richard Acayan. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include "sdm670.dtsi"
> +#include "pm660.dtsi"
> +#include "pm660l.dtsi"
> +
> +/delete-node/ &mpss_region;
> +/delete-node/ &venus_mem;
> +/delete-node/ &wlan_msa_mem;
> +/delete-node/ &cdsp_mem;
> +/delete-node/ &mba_region;
> +/delete-node/ &adsp_mem;
> +/delete-node/ &ipa_fw_mem;
> +/delete-node/ &ipa_gsi_mem;
> +/delete-node/ &gpu_mem;
> +
> +/ {
> + model = "Google Pixel 3a";
> + compatible = "google,sargo", "qcom,sdm670";
> + qcom,board-id = <0x00041e05 0>;
> + qcom,msm-id = <321 0x20001>;
> +
> + aliases { };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + framebuffer@9c000000 {
> + compatible = "simple-framebuffer";
> + reg = <0x0 0x9c000000 0x0 (1080 * 2220 * 4)>;
> + width = <1080>;
> + height = <2220>;
> + stride = <(1080 * 4)>;
> + format = "a8r8g8b8";
> + };
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + mpss_region: mpss@8b000000 {
> + reg = <0 0x8b000000 0 0x9800000>;
> + no-map;
> + };
> +
> + venus_mem: venus@94800000 {
> + reg = <0 0x94800000 0 0x500000>;
> + no-map;
> + };
> +
> + wlan_msa_mem: wlan-msa@94d00000 {
> + reg = <0 0x94d00000 0 0x100000>;
> + no-map;
> + };
> +
> + cdsp_mem: cdsp@94e00000 {
> + reg = <0 0x94e00000 0 0x800000>;
> + no-map;
> + };
> +
> + mba_region: mba@95600000 {
> + reg = <0 0x95600000 0 0x200000>;
> + no-map;
> + };
> +
> + adsp_mem: adsp@95800000 {
> + reg = <0 0x95800000 0 0x2200000>;
> + no-map;
> + };
> +
> + ipa_fw_mem: ipa-fw@97a00000 {
> + reg = <0 0x97a00000 0 0x10000>;
> + no-map;
> + };
> +
> + ipa_gsi_mem: ipa-gsi@97a10000 {
> + reg = <0 0x97a10000 0 0x5000>;
> + no-map;
> + };
> +
> + gpu_mem: gpu@97a15000 {
> + reg = <0 0x97a15000 0 0x2000>;
> + no-map;
> + };
> +
> + framebuffer-region@9c000000 {
> + reg = <0 0x9c000000 0 0x2400000>;
> + no-map;
> + };
> +
> + /* Also includes ramoops regions */
> + debug_info_mem: debug-info@a1800000 {
> + reg = <0 0xa1800000 0 0x411000>;
> + no-map;
> + };
> + };
> +
> + /*
> + * Supply map from xiaomi-lavender specifies this as the supply for
> + * ldob1, ldob9, ldob10, ldoa2, and ldoa3, while downstream specifies
> + * this as a power domain. Set this as a fixed regulator with the same
> + * voltage as lavender until display is needed to avoid unneccessarily
> + * using a deprecated binding (regulator-fixed-domain).
> + */
> + vreg_s2b_1p05: vreg-s2b-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vreg_s2b";
> + regulator-min-microvolt = <1050000>;
> + regulator-max-microvolt = <1050000>;
> + };
> +
> + vph_pwr: vph-pwr-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vph_pwr";
> + regulator-min-microvolt = <3312000>;
> + regulator-max-microvolt = <3312000>;
> +
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + autorepeat;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&vol_up_pin>;
> +
> + key-vol-up {
> + label = "Volume Up";
> + linux,code = <KEY_VOLUMEUP>;
> + gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>;
> + };
> + };
> +
> + /*
> + * The touchscreen regulator seems to be controlled somehow by a gpio.
> + * Model it as a fixed regulator and keep it on. Without schematics we
> + * don't know how this is actually wired up...
> + */
> + ts_1p8_supply: ts-1p8-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "ts_1p8_supply";
> +
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> +
> + gpio = <&pm660_gpios 12 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +};
> +
> +&apps_rsc {
> + pm660l-regulators {
> + compatible = "qcom,pm660l-rpmh-regulators";
> + qcom,pmic-id = "b";
> +
> + vdd-s1-supply = <&vph_pwr>;
> + vdd-s2-supply = <&vph_pwr>;
> + vdd-s3-s4-supply = <&vph_pwr>;
> + vdd-s5-supply = <&vph_pwr>;
> +
> + vdd-l1-l9-l10-supply = <&vreg_s2b_1p05>;
> + vdd-l2-supply = <&vreg_bob>;
> + vdd-l3-l5-l7-l8-supply = <&vreg_bob>;
> + vdd-l4-l6-supply = <&vreg_bob>;
> + vdd-bob-supply = <&vph_pwr>;
> +
> + /* LDOs */
> + vreg_l1b_0p89: ldo1 {
> + regulator-min-microvolt = <880000>;
> + regulator-max-microvolt = <900000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l2b_2p38: ldo2 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <2960000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l3b_2p93: ldo3 {
> + regulator-min-microvolt = <2850000>;
> + regulator-max-microvolt = <3008000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l4b_2p96: ldo4 {
> + regulator-min-microvolt = <2960000>;
> + regulator-max-microvolt = <2960000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l5b_2p96: ldo5 {
> + regulator-min-microvolt = <2960000>;
> + regulator-max-microvolt = <2960000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l6b_3p15: ldo6 {
> + regulator-min-microvolt = <3008000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l7b_3p1: ldo7 {
> + regulator-min-microvolt = <3088000>;
> + regulator-max-microvolt = <3100000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l8b_3p3: ldo8 {
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3312000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + /*
> + * Downstream specifies a fixed voltage of 3.312 V, but the
> + * PMIC4 BOB ranges don't support that. Widen the range a
> + * little to avoid adding a new BOB regulator type.
> + */
> + vreg_bob: bob {
> + regulator-min-microvolt = <3296000>;
> + regulator-max-microvolt = <3328000>;
> + regulator-enable-ramp-delay = <500>;
> + };
> + };
> +
> + pm660-regulators {
> + compatible = "qcom,pm660-rpmh-regulators";
> + qcom,pmic-id = "a";
> +
> + vdd-s1-supply = <&vph_pwr>;
> + vdd-s2-supply = <&vph_pwr>;
> + vdd-s3-supply = <&vph_pwr>;
> + vdd-s4-supply = <&vph_pwr>;
> + vdd-s5-supply = <&vph_pwr>;
> + vdd-s6-supply = <&vph_pwr>;
> +
> + vdd-l1-l6-l7-supply = <&vreg_s6a_1p29>;
> + vdd-l2-l3-supply = <&vreg_s2b_1p05>;
> + vdd-l5-supply = <&vreg_s2b_1p05>;
> + vdd-l8-l9-l10-l11-l12-l13-l14-supply = <&vreg_s4a_1p92>;
> + vdd-l15-l16-l17-l18-l19-supply = <&vreg_bob>;
> +
> + /*
> + * S1A (FTAPC0), S2A (FTAPC1), S3A (HFAPC1) are managed
> + * by the Core Power Reduction hardened (CPRh) and the
> + * Operating State Manager (OSM) HW automatically.
> + */
> +
> + vreg_s4a_1p92: smps4 {
> + regulator-min-microvolt = <1808000>;
> + regulator-max-microvolt = <2040000>;
> + regulator-enable-ramp-delay = <200>;
> + };
> +
> + vreg_s6a_1p29: smps6 {
> + regulator-min-microvolt = <1224000>;
> + regulator-max-microvolt = <1352000>;
> + regulator-enable-ramp-delay = <150>;
> + };
> +
> + /* LDOs */
> + vreg_l1a_1p225: ldo1 {
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1250000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l2a_1p0: ldo2 {
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l3a_1p0: ldo3 {
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l5a_0p8: ldo5 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l6a_1p28: ldo6 {
> + regulator-min-microvolt = <1248000>;
> + regulator-max-microvolt = <1304000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l7a_1p2: ldo7 {
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l8a_1p8: ldo8 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l9a_1p8: ldo9 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l10a_1p8: ldo10 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l11a_1p8: ldo11 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l12a_1p8: ldo12 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l13a_1p8: ldo13 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l14a_1p8: ldo14 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l15a_2p38: ldo15 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <2950000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l16a_2p7: ldo16 {
> + regulator-min-microvolt = <2696000>;
> + regulator-max-microvolt = <2696000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l17a_2p38: ldo17 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <2950000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> +
> + vreg_l19a_3p3: ldo19 {
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3312000>;
> + regulator-enable-ramp-delay = <250>;
> + };
> + };
> +};
> +
> +&gpi_dma1 {
> + status = "okay";
> +};
> +
> +&qupv3_id_1 {
> + status = "okay";
> +};
> +
> +&i2c9 {
> + status = "okay";
> + clock-frequency = <100000>;
> +
> + synaptics-rmi4-i2c@20 {
> + compatible = "syna,rmi4-i2c";
> + reg = <0x20>;
> + #address-cells = <0x1>;
> + #size-cells = <0x0>;
> + interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&touchscreen_default>;
> +
> + /* VDD supply isn't specified, bind it to power */
> + vdd-supply = <&vph_pwr>;
> + vio-supply = <&ts_1p8_supply>;
> +
> + syna,reset-delay-ms = <200>;
> + syna,startup-delay-ms = <200>;
> +
> + rmi4-f01@1 {
> + reg = <0x01>;
> + syna,nosleep-mode = <1>;
> + };
> +
> + rmi4-f12@12 {
> + reg = <0x12>;
> + touchscreen-x-mm = <62>;
> + touchscreen-y-mm = <127>;
> + syna,sensor-type = <1>;
> + };
> + };
> +};
> +
> +&gcc {
> + protected-clocks = <GCC_QSPI_CORE_CLK>,
> + <GCC_QSPI_CORE_CLK_SRC>,
> + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>;
> +};
> +
> +&pm660l_gpios {
> + vol_up_pin: vol-up-state {
> + pins = "gpio7";
> + function = "normal";
> + qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
> + input-enable;
> + bias-pull-up;
> + };
> +};
> +
> +&pon_pwrkey {
> + status = "okay";
> +};
> +
> +&pon_resin {
> + status = "okay";
> + linux,code = <KEY_VOLUMEDOWN>;
> +};
> +
> +&sdhc_1 {
> + status = "okay";
> + supports-cqe;
> + mmc-hs200-1_8v;
> + mmc-hs400-1_8v;
> + mmc-ddr-1_8v;
> +
> + qcom,ddr-config = <0xc3040873>;
> +
> + vmmc-supply = <&vreg_l4b_2p96>;
> + vqmmc-supply = <&vreg_l8a_1p8>;
> +};
> +
> +&tlmm {
> + gpio-reserved-ranges = <0 4>, <81 4>;
> +
> + touchscreen_default: ts-default-state {
> + ts-reset-pins {
> + pins = "gpio99";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + output-high;
> + };
> +
> + ts-irq-pins {
> + pins = "gpio125";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + ts-switch-pins {
> + pins = "gpio135";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + output-low;
> + };
> + };
> +};
> +
> +&usb_1_hsphy {
> + status = "okay";
> +
> + vdd-supply = <&vreg_l1b_0p89>;
> + vdda-pll-supply = <&vreg_l10a_1p8>;
> + vdda-phy-dpdm-supply = <&vreg_l7b_3p1>;
> +};
> +
> +&usb_1 {
> + status = "okay";
> +
> + qcom,select-utmi-as-pipe-clk;
> +};
> +
> +&usb_1_dwc3 {
> + /* Only peripheral works for now */
> + dr_mode = "peripheral";
> +
> + /* Do not assume that sdm670.dtsi will never support USB 3.0 */
> + phys = <&usb_1_hsphy>;
> + phy-names = "usb2-phy";
> + maximum-speed = "high-speed";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
> new file mode 100644
> index 000000000000..4450ece839a0
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
> @@ -0,0 +1,1216 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SDM670 SoC device tree source, adapted from SDM845 SoC device tree
> + *
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2022, Richard Acayan. All rights reserved.
> + */
> +
> +#include <dt-bindings/clock/qcom,gcc-sdm845.h>
> +#include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/dma/qcom-gpi.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/phy/phy-qcom-qusb2.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases { };
> +
> + chosen { };
> +
> + memory@80000000 {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the size */
> + reg = <0 0x80000000 0 0>;
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + hyp_mem: hyp-mem@85700000 {
> + reg = <0 0x85700000 0 0x600000>;
> + no-map;
> + };
> +
> + xbl_mem: xbl-mem@85e00000 {
> + reg = <0 0x85e00000 0 0x100000>;
> + no-map;
> + };
> +
> + aop_mem: aop-mem@85fc0000 {
> + reg = <0 0x85fc0000 0 0x20000>;
> + no-map;
> + };
> +
> + aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
> + compatible = "qcom,cmd-db";
> + reg = <0x0 0x85fe0000 0 0x20000>;
> + no-map;
> + };
> +
> + camera_mem: camera-mem@8ab00000 {
> + reg = <0 0x8ab00000 0 0x500000>;
> + no-map;
> + };
> +
> + mpss_region: mpss@8b000000 {
> + reg = <0 0x8b000000 0 0x7e00000>;
> + no-map;
> + };
> +
> + venus_mem: venus@92e00000 {
> + reg = <0 0x92e00000 0 0x500000>;
> + no-map;
> + };
> +
> + wlan_msa_mem: wlan-msa@93300000 {
> + reg = <0 0x93300000 0 0x100000>;
> + no-map;
> + };
> +
> + cdsp_mem: cdsp@93400000 {
> + reg = <0 0x93400000 0 0x800000>;
> + no-map;
> + };
> +
> + mba_region: mba@93c00000 {
> + reg = <0 0x93c00000 0 0x200000>;
> + no-map;
> + };
> +
> + adsp_mem: adsp@93e00000 {
> + reg = <0 0x93e00000 0 0x1e00000>;
> + no-map;
> + };
> +
> + ipa_fw_mem: ipa-fw@95c00000 {
> + reg = <0 0x95c00000 0 0x10000>;
> + no-map;
> + };
> +
> + ipa_gsi_mem: ipa-gsi@95c10000 {
> + reg = <0 0x95c10000 0 0x5000>;
> + no-map;
> + };
> +
> + gpu_mem: gpu@95c15000 {
> + reg = <0 0x95c15000 0 0x2000>;
> + no-map;
> + };
> +
> + spss_mem: spss@97b00000 {
> + reg = <0 0x97b00000 0 0x100000>;
> + no-map;
> + };
> +
> + qseecom_mem: qseecom@9e400000 {
> + reg = <0 0x9e400000 0 0x1400000>;
> + no-map;
> + };
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD0>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_0>;
> + L2_0: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + L3_0: l3-cache {
> + compatible = "cache";
> + };
> + };
> + };
> +
> + CPU1: cpu@100 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD1>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_100>;
> + L2_100: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU2: cpu@200 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x200>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD2>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_200>;
> + L2_200: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU3: cpu@300 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x300>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD3>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_300>;
> + L2_300: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU4: cpu@400 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x400>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD4>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_400>;
> + L2_400: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU5: cpu@500 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x500>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD5>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_500>;
> + L2_500: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU6: cpu@600 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x600>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD6>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_600>;
> + L2_600: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU7: cpu@700 {
> + device_type = "cpu";
> + compatible = "qcom,kryo360";
> + reg = <0x0 0x700>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD7>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_700>;
> + L2_700: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&CPU0>;
> + };
> +
> + core1 {
> + cpu = <&CPU1>;
> + };
> +
> + core2 {
> + cpu = <&CPU2>;
> + };
> +
> + core3 {
> + cpu = <&CPU3>;
> + };
> +
> + core4 {
> + cpu = <&CPU4>;
> + };
> +
> + core5 {
> + cpu = <&CPU5>;
> + };
> +
> + core6 {
> + cpu = <&CPU6>;
> + };
> +
> + core7 {
> + cpu = <&CPU7>;
> + };
> + };
> + };
> +
> + idle-states {
> + entry-method = "psci";
> +
> + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
> + compatible = "arm,idle-state";
> + idle-state-name = "little-rail-power-collapse";
> + arm,psci-suspend-param = <0x40000004>;
> + entry-latency-us = <702>;
> + exit-latency-us = <915>;
> + min-residency-us = <1617>;
> + local-timer-stop;
> + };
> +
> + BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
> + compatible = "arm,idle-state";
> + idle-state-name = "big-rail-power-collapse";
> + arm,psci-suspend-param = <0x40000004>;
> + entry-latency-us = <526>;
> + exit-latency-us = <1854>;
> + min-residency-us = <2380>;
> + local-timer-stop;
> + };
> + };
> +
> + domain-idle-states {
> + CLUSTER_SLEEP_0: cluster-sleep-0 {
> + compatible = "domain-idle-state";
> + arm,psci-suspend-param = <0x4100c244>;
> + entry-latency-us = <3263>;
> + exit-latency-us = <6562>;
> + min-residency-us = <9825>;
> + };
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + clocks {
> + xo_board: xo-board {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <38400000>;
> + clock-output-names = "xo_board";
> + };
> +
> + sleep_clk: sleep-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32764>;
> + };
> + };
> +
> + firmware {
> + scm {
> + compatible = "qcom,scm-sdm670", "qcom,scm";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> +
> + CPU_PD0: power-domain-cpu0 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD1: power-domain-cpu1 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD2: power-domain-cpu2 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD3: power-domain-cpu3 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD4: power-domain-cpu4 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD5: power-domain-cpu5 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD6: power-domain-cpu6 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
> + };
> +
> + CPU_PD7: power-domain-cpu7 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&BIG_CPU_SLEEP_0>;
> + };
> +
> + CLUSTER_PD: power-domain-cluster {
> + #power-domain-cells = <0>;
> + domain-idle-states = <&CLUSTER_SLEEP_0>;
> + };
> + };
> +
> + soc: soc@0 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0 0 0 0 0x10 0>;
> + dma-ranges = <0 0 0 0 0x10 0>;
> + compatible = "simple-bus";
> +
> + gcc: clock-controller@100000 {
> + compatible = "qcom,gcc-sdm670";
> + reg = <0 0x00100000 0 0x1f0000>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&rpmhcc RPMH_CXO_CLK_A>,
> + <&sleep_clk>;
> + clock-names = "bi_tcxo",
> + "bi_tcxo_ao",
> + "sleep_clk";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> + sdhc_1: mmc@7c4000 {
> + compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0 0x007c4000 0 0x1000>,
> + <0 0x007c5000 0 0x1000>,
> + <0 0x007c8000 0 0x8000>;
> + reg-names = "hc", "cqhci", "ice";
> +
> + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> + <&gcc GCC_SDCC1_APPS_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_SDCC1_ICE_CORE_CLK>,
> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
> + clock-names = "iface", "core", "xo", "ice", "bus";
> +
> + iommus = <&apps_smmu 0x140 0xf>;
> +
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&sdc1_state_on>;
> + pinctrl-1 = <&sdc1_state_off>;
> + power-domains = <&rpmhpd SDM670_CX>;
> +
> + bus-width = <8>;
> + non-removable;
> +
> + status = "disabled";
> + };
> +
> + gpi_dma0: dma-controller@800000 {
> + #dma-cells = <3>;
> + compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
> + reg = <0 0x00800000 0 0x60000>;
> + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
> + dma-channels = <13>;
> + dma-channel-mask = <0xfa>;
> + iommus = <&apps_smmu 0x0016 0x0>;
> + status = "disabled";
> + };
> +
> + qupv3_id_0: geniqup@8c0000 {
> + compatible = "qcom,geni-se-qup";
> + reg = <0 0x008c0000 0 0x6000>;
> + clock-names = "m-ahb", "s-ahb";
> + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
> + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
> + iommus = <&apps_smmu 0x3 0x0>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
> + interconnect-names = "qup-core";
Another thing to fix: these interconnects are excluded in this series.
Will drop.
> + status = "disabled";
> +
> + i2c0: i2c@880000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00880000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c0_default>;
> + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 0 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c1: i2c@884000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00884000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c1_default>;
> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 1 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c2: i2c@888000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00888000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c2_default>;
> + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 2 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c3: i2c@88c000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x0088c000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c3_default>;
> + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 3 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c4: i2c@890000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00890000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c4_default>;
> + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 4 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c5: i2c@894000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00894000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c5_default>;
> + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 5 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c6: i2c@898000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00898000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c6_default>;
> + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 6 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c7: i2c@89c000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x0089c000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c7_default>;
> + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
> + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
> + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
> + <&gpi_dma0 1 7 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> + };
> +
> + gpi_dma1: dma-controller@a00000 {
> + #dma-cells = <3>;
> + compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
> + reg = <0 0x00a00000 0 0x60000>;
> + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
> + dma-channels = <13>;
> + dma-channel-mask = <0xfa>;
> + iommus = <&apps_smmu 0x06d6 0x0>;
> + status = "disabled";
> + };
> +
> + qupv3_id_1: geniqup@ac0000 {
> + compatible = "qcom,geni-se-qup";
> + reg = <0 0x00ac0000 0 0x6000>;
> + clock-names = "m-ahb", "s-ahb";
> + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
> + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> + iommus = <&apps_smmu 0x6c3 0x0>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + i2c8: i2c@a80000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a80000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c8_default>;
> + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 0 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c9: i2c@a84000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a84000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c9_default>;
> + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 1 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c10: i2c@a88000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a88000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c10_default>;
> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 2 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c11: i2c@a8c000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a8c000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c11_default>;
> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 3 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c12: i2c@a90000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a90000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c12_default>;
> + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 4 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c13: i2c@a94000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a94000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c13_default>;
> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 5 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c14: i2c@a98000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a98000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c14_default>;
> + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 6 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c15: i2c@a9c000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x00a9c000 0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c15_default>;
> + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + power-domains = <&rpmhpd SDM670_CX>;
> + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
> + <&gpi_dma1 1 7 QCOM_GPI_I2C>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> + };
> +
> + tlmm: pinctrl@3400000 {
> + compatible = "qcom,sdm670-tlmm";
> + reg = <0 0x03400000 0 0xc00000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-ranges = <&tlmm 0 0 151>;
> +
> + qup_i2c0_default: qup-i2c0-default-state {
> + pins = "gpio0", "gpio1";
> + function = "qup0";
> + };
> +
> + qup_i2c1_default: qup-i2c1-default-state {
> + pins = "gpio17", "gpio18";
> + function = "qup1";
> + };
> +
> + qup_i2c2_default: qup-i2c2-default-state {
> + pins = "gpio27", "gpio28";
> + function = "qup2";
> + };
> +
> + qup_i2c3_default: qup-i2c3-default-state {
> + pins = "gpio41", "gpio42";
> + function = "qup3";
> + };
> +
> + qup_i2c4_default: qup-i2c4-default-state {
> + pins = "gpio89", "gpio90";
> + function = "qup4";
> + };
> +
> + qup_i2c5_default: qup-i2c5-default-state {
> + pins = "gpio85", "gpio86";
> + function = "qup5";
> + };
> +
> + qup_i2c6_default: qup-i2c6-default-state {
> + pins = "gpio45", "gpio46";
> + function = "qup6";
> + };
> +
> + qup_i2c7_default: qup-i2c7-default-state {
> + pins = "gpio93", "gpio94";
> + function = "qup7";
> + };
> +
> + qup_i2c8_default: qup-i2c8-default-state {
> + pins = "gpio65", "gpio66";
> + function = "qup8";
> + };
> +
> + qup_i2c9_default: qup-i2c9-default-state {
> + pins = "gpio6", "gpio7";
> + function = "qup9";
> + };
> +
> + qup_i2c10_default: qup-i2c10-default-state {
> + pins = "gpio55", "gpio56";
> + function = "qup10";
> + };
> +
> + qup_i2c11_default: qup-i2c11-default-state {
> + pins = "gpio31", "gpio32";
> + function = "qup11";
> + };
> +
> + qup_i2c12_default: qup-i2c12-default-state {
> + pins = "gpio49", "gpio50";
> + function = "qup12";
> + };
> +
> + qup_i2c13_default: qup-i2c13-default-state {
> + pins = "gpio105", "gpio106";
> + function = "qup13";
> + };
> +
> + qup_i2c14_default: qup-i2c14-default-state {
> + pins = "gpio33", "gpio34";
> + function = "qup14";
> + };
> +
> + qup_i2c15_default: qup-i2c15-default-state {
> + pins = "gpio81", "gpio82";
> + function = "qup15";
> + };
> +
> + sdc1_state_on: sdc1-on-state {
> + clk-pins {
> + pins = "sdc1_clk";
> + bias-disable;
> + drive-strength = <16>;
> + };
> +
> + cmd-pins {
> + pins = "sdc1_cmd";
> + bias-pull-up;
> + drive-strength = <10>;
> + };
> +
> + data-pins {
> + pins = "sdc1_data";
> + bias-pull-up;
> + drive-strength = <10>;
> + };
> +
> + rclk-pins {
> + pins = "sdc1_rclk";
> + bias-pull-down;
> + };
> + };
> +
> + sdc1_state_off: sdc1-off-state {
> + clk-pins {
> + pins = "sdc1_clk";
> + bias-disable;
> + drive-strength = <2>;
> + };
> +
> + cmd-pins {
> + pins = "sdc1_cmd";
> + bias-pull-up;
> + drive-strength = <2>;
> + };
> +
> + data-pins {
> + pins = "sdc1_data";
> + bias-pull-up;
> + drive-strength = <2>;
> + };
> +
> + rclk-pins {
> + pins = "sdc1_rclk";
> + bias-pull-down;
> + };
> + };
> + };
> +
> + usb_1_hsphy: phy@88e2000 {
> + compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy";
> + reg = <0 0x088e2000 0 0x400>;
> + status = "disabled";
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "cfg_ahb", "ref";
> +
> + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> + };
> +
> + usb_1: usb@a6f8800 {
> + compatible = "qcom,sdm670-dwc3", "qcom,dwc3";
> + reg = <0 0x0a6f8800 0 0x400>;
> + status = "disabled";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + dma-ranges;
> +
> + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_MASTER_CLK>,
> + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
> + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
> + clock-names = "cfg_noc",
> + "core",
> + "iface",
> + "sleep",
> + "mock_utmi";
> +
> + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB30_PRIM_MASTER_CLK>;
> + assigned-clock-rates = <19200000>, <150000000>;
> +
> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hs_phy_irq", "ss_phy_irq",
> + "dm_hs_phy_irq", "dp_hs_phy_irq";
> +
> + power-domains = <&gcc USB30_PRIM_GDSC>;
> +
> + resets = <&gcc GCC_USB30_PRIM_BCR>;
> +
> + usb_1_dwc3: usb@a600000 {
> + compatible = "snps,dwc3";
> + reg = <0 0x0a600000 0 0xcd00>;
> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> + iommus = <&apps_smmu 0x740 0>;
> + snps,dis_u2_susphy_quirk;
> + snps,dis_enblslpm_quirk;
> + phys = <&usb_1_hsphy>;
> + phy-names = "usb2-phy";
> + };
> + };
> +
> + spmi_bus: spmi@c440000 {
> + compatible = "qcom,spmi-pmic-arb";
> + reg = <0 0x0c440000 0 0x1100>,
> + <0 0x0c600000 0 0x2000000>,
> + <0 0x0e600000 0 0x100000>,
> + <0 0x0e700000 0 0xa0000>,
> + <0 0x0c40a000 0 0x26000>;
> + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> + interrupt-names = "periph_irq";
> + interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
> + qcom,ee = <0>;
> + qcom,channel = <0>;
> + #address-cells = <2>;
> + #size-cells = <0>;
> + interrupt-controller;
> + #interrupt-cells = <4>;
> + };
> +
> + apps_smmu: iommu@15000000 {
> + /*
> + * The hardware tolerates the SDM845 reset quirk. The
> + * iommu maintainers aren't responding to any patches
> + * that would add support for new platforms. Set this
> + * compatible so this dtsi is valid and functional.
> + */
> + compatible = "qcom,sdm845-smmu-500", "qcom,smmu-500", "arm,mmu-500";
> + reg = <0 0x15000000 0 0x80000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <1>;
> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + apps_rsc: rsc@179c0000 {
> + label = "apps_rsc";
> + compatible = "qcom,rpmh-rsc";
> + reg = <0 0x179c0000 0 0x10000>,
> + <0 0x179d0000 0 0x10000>,
> + <0 0x179e0000 0 0x10000>;
> + reg-names = "drv-0", "drv-1", "drv-2";
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + qcom,tcs-offset = <0xd00>;
> + qcom,drv-id = <2>;
> + qcom,tcs-config = <ACTIVE_TCS 2>,
> + <SLEEP_TCS 3>,
> + <WAKE_TCS 3>,
> + <CONTROL_TCS 1>;
> +
> + apps_bcm_voter: bcm-voter {
> + compatible = "qcom,bcm-voter";
> + };
> +
> + rpmhcc: clock-controller {
> + compatible = "qcom,sdm670-rpmh-clk";
> + #clock-cells = <1>;
> + clock-names = "xo";
> + clocks = <&xo_board>;
> + };
> +
> + rpmhpd: power-controller {
> + compatible = "qcom,sdm670-rpmhpd";
> + #power-domain-cells = <1>;
> + operating-points-v2 = <&rpmhpd_opp_table>;
> +
> + rpmhpd_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + rpmhpd_opp_ret: opp1 {
> + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
> + };
> +
> + rpmhpd_opp_min_svs: opp2 {
> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> + };
> +
> + rpmhpd_opp_low_svs: opp3 {
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + };
> +
> + rpmhpd_opp_svs: opp4 {
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> + };
> +
> + rpmhpd_opp_svs_l1: opp5 {
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> + };
> +
> + rpmhpd_opp_nom: opp6 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> + };
> +
> + rpmhpd_opp_nom_l1: opp7 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> + };
> +
> + rpmhpd_opp_nom_l2: opp8 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
> + };
> +
> + rpmhpd_opp_turbo: opp9 {
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> + };
> +
> + rpmhpd_opp_turbo_l1: opp10 {
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> + };
> + };
> + };
> + };
> +
> + intc: interrupt-controller@17a00000 {
> + compatible = "arm,gic-v3";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0 0x17a00000 0 0x10000>, /* GICD */
> + <0 0x17a60000 0 0x100000>; /* GICR * 8 */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +};
> --
> 2.38.1
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 4/4] arm64: dts: qcom: add sdm670 and pixel 3a device trees
2022-11-01 23:57 ` [PATCH 4/4] arm64: dts: qcom: add sdm670 and pixel 3a device trees Richard Acayan
` (2 preceding siblings ...)
2022-11-03 1:19 ` Richard Acayan
@ 2022-11-03 20:34 ` kernel test robot
3 siblings, 0 replies; 16+ messages in thread
From: kernel test robot @ 2022-11-03 20:34 UTC (permalink / raw)
To: Richard Acayan, Rob Herring, Krzysztof Kozlowski, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Vinod Koul, Robin Murphy,
Chanho Park, Thierry Reding, Stephan Gerhold, Lorenzo Pieralisi,
Robert Marko, Das Srinagesh, devicetree, linux-kernel,
linux-arm-msm
Cc: oe-kbuild-all, ~postmarketos/upstreaming, phone-devel
[-- Attachment #1: Type: text/plain, Size: 1923 bytes --]
Hi Richard,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on krzk/for-next krzk-dt/for-next krzk-mem-ctrl/for-next linus/master v6.1-rc3 next-20221103]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Richard-Acayan/Initial-SDM670-and-Pixel-3a-support/20221102-080047
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20221101235722.53955-5-mailingradian%40gmail.com
patch subject: [PATCH 4/4] arm64: dts: qcom: add sdm670 and pixel 3a device trees
config: arm64-randconfig-c034-20221102
compiler: aarch64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/1704148fddd2c14f8a3ac028857cd79b1428a275
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Richard-Acayan/Initial-SDM670-and-Pixel-3a-support/20221102-080047
git checkout 1704148fddd2c14f8a3ac028857cd79b1428a275
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
Error: arch/arm64/boot/dts/qcom/sdm670.dtsi:442.29-30 syntax error
>> FATAL ERROR: Unable to parse input tree
--
0-DAY CI Kernel Test Service
https://01.org/lkp
[-- Attachment #2: config --]
[-- Type: text/plain, Size: 164335 bytes --]
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm64 6.1.0-rc1 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="aarch64-linux-gcc (GCC) 12.1.0"
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=120100
CONFIG_CLANG_VERSION=0
CONFIG_AS_IS_GNU=y
CONFIG_AS_VERSION=23800
CONFIG_LD_IS_BFD=y
CONFIG_LD_VERSION=23800
CONFIG_LLD_VERSION=0
CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
CONFIG_CC_HAS_ASM_INLINE=y
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
CONFIG_PAHOLE_VERSION=123
CONFIG_CONSTRUCTORS=y
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_TABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y
#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_COMPILE_TEST=y
# CONFIG_WERROR is not set
CONFIG_LOCALVERSION=""
CONFIG_BUILD_SALT=""
CONFIG_DEFAULT_INIT=""
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_COMPAT=y
CONFIG_WATCH_QUEUE=y
CONFIG_CROSS_MEMORY_ATTACH=y
CONFIG_USELIB=y
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_IRQ_INJECTION=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_SIM=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_GENERIC_IRQ_IPI=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_IRQ_MSI_IOMMU=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
CONFIG_GENERIC_IRQ_DEBUGFS=y
# end of IRQ subsystem
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
CONFIG_TIME_KUNIT_TEST=m
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ_COMMON=y
# CONFIG_HZ_PERIODIC is not set
# CONFIG_NO_HZ_IDLE is not set
CONFIG_NO_HZ_FULL=y
CONFIG_CONTEXT_TRACKING_USER=y
# CONFIG_CONTEXT_TRACKING_USER_FORCE is not set
CONFIG_NO_HZ=y
# CONFIG_HIGH_RES_TIMERS is not set
# end of Timers subsystem
CONFIG_HAVE_EBPF_JIT=y
CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y
#
# BPF subsystem
#
# CONFIG_BPF_SYSCALL is not set
# end of BPF subsystem
CONFIG_PREEMPT_BUILD=y
# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
CONFIG_PREEMPT_COUNT=y
CONFIG_PREEMPTION=y
CONFIG_PREEMPT_DYNAMIC=y
#
# CPU/Task time and stats accounting
#
CONFIG_VIRT_CPU_ACCOUNTING=y
CONFIG_VIRT_CPU_ACCOUNTING_GEN=y
# CONFIG_IRQ_TIME_ACCOUNTING is not set
CONFIG_HAVE_SCHED_AVG_IRQ=y
# CONFIG_PSI is not set
# end of CPU/Task time and stats accounting
CONFIG_CPU_ISOLATION=y
#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
CONFIG_PREEMPT_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
CONFIG_RCU_NOCB_CPU=y
CONFIG_RCU_NOCB_CPU_DEFAULT_ALL=y
# end of RCU Subsystem
CONFIG_IKCONFIG=y
CONFIG_IKHEADERS=m
CONFIG_GENERIC_SCHED_CLOCK=y
#
# Scheduler features
#
# end of Scheduler features
CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
CONFIG_CC_HAS_INT128=y
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
CONFIG_GCC12_NO_ARRAY_BOUNDS=y
CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_ARCH_SUPPORTS_INT128=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
# CONFIG_CGROUP_FAVOR_DYNMODS is not set
CONFIG_MEMCG=y
CONFIG_MEMCG_KMEM=y
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_CFS_BANDWIDTH=y
# CONFIG_RT_GROUP_SCHED is not set
CONFIG_CGROUP_PIDS=y
# CONFIG_CGROUP_RDMA is not set
# CONFIG_CGROUP_FREEZER is not set
CONFIG_CPUSETS=y
CONFIG_PROC_PID_CPUSET=y
CONFIG_CGROUP_DEVICE=y
# CONFIG_CGROUP_CPUACCT is not set
CONFIG_CGROUP_PERF=y
# CONFIG_CGROUP_MISC is not set
CONFIG_CGROUP_DEBUG=y
CONFIG_SCHED_AUTOGROUP=y
CONFIG_SYSFS_DEPRECATED=y
# CONFIG_SYSFS_DEPRECATED_V2 is not set
# CONFIG_RELAY is not set
# CONFIG_BLK_DEV_INITRD is not set
CONFIG_BOOT_CONFIG=y
CONFIG_BOOT_CONFIG_EMBED=y
CONFIG_BOOT_CONFIG_EMBED_FILE=""
# CONFIG_INITRAMFS_PRESERVE_MTIME is not set
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_LD_ORPHAN_WARN=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_EXPERT=y
# CONFIG_MULTIUSER is not set
CONFIG_SGETMASK_SYSCALL=y
# CONFIG_SYSFS_SYSCALL is not set
CONFIG_FHANDLE=y
# CONFIG_POSIX_TIMERS is not set
# CONFIG_PRINTK is not set
# CONFIG_BUG is not set
# CONFIG_BASE_FULL is not set
# CONFIG_FUTEX is not set
# CONFIG_EPOLL is not set
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
# CONFIG_AIO is not set
# CONFIG_IO_URING is not set
# CONFIG_ADVISE_SYSCALLS is not set
CONFIG_MEMBARRIER=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
CONFIG_KCMP=y
CONFIG_RSEQ=y
CONFIG_DEBUG_RSEQ=y
CONFIG_EMBEDDED=y
CONFIG_HAVE_PERF_EVENTS=y
# CONFIG_PC104 is not set
#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
# end of Kernel Performance Events And Counters
CONFIG_PROFILING=y
# end of General setup
CONFIG_ARM64=y
CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_64BIT=y
CONFIG_MMU=y
CONFIG_ARM64_PAGE_SHIFT=14
CONFIG_ARM64_CONT_PTE_SHIFT=7
CONFIG_ARM64_CONT_PMD_SHIFT=5
CONFIG_ARCH_MMAP_RND_BITS_MIN=16
CONFIG_ARCH_MMAP_RND_BITS_MAX=30
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=9
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_NO_IOPORT_MAP=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
CONFIG_SMP=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_KASAN_SHADOW_OFFSET=0xefffc00000000000
#
# Platform selection
#
CONFIG_ARCH_ACTIONS=y
# CONFIG_ARCH_SUNXI is not set
# CONFIG_ARCH_ALPINE is not set
CONFIG_ARCH_APPLE=y
# CONFIG_ARCH_BCM is not set
# CONFIG_ARCH_BERLIN is not set
# CONFIG_ARCH_BITMAIN is not set
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_SPARX5=y
CONFIG_ARCH_K3=y
CONFIG_ARCH_LG1K=y
CONFIG_ARCH_HISI=y
CONFIG_ARCH_KEEMBAY=y
# CONFIG_ARCH_MEDIATEK is not set
# CONFIG_ARCH_MESON is not set
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_NXP is not set
CONFIG_ARCH_NPCM=y
# CONFIG_ARCH_QCOM is not set
# CONFIG_ARCH_REALTEK is not set
CONFIG_ARCH_RENESAS=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_ARCH_SEATTLE=y
CONFIG_ARCH_INTEL_SOCFPGA=y
CONFIG_ARCH_SYNQUACER=y
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_TESLA_FSD is not set
# CONFIG_ARCH_SPRD is not set
# CONFIG_ARCH_THUNDER is not set
# CONFIG_ARCH_THUNDER2 is not set
CONFIG_ARCH_UNIPHIER=y
CONFIG_ARCH_VEXPRESS=y
# CONFIG_ARCH_VISCONTI is not set
CONFIG_ARCH_XGENE=y
CONFIG_ARCH_ZYNQMP=y
# end of Platform selection
#
# Kernel Features
#
#
# ARM errata workarounds via the alternatives framework
#
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
# CONFIG_ARM64_ERRATUM_826319 is not set
# CONFIG_ARM64_ERRATUM_827319 is not set
# CONFIG_ARM64_ERRATUM_824069 is not set
CONFIG_ARM64_ERRATUM_819472=y
# CONFIG_ARM64_ERRATUM_832075 is not set
CONFIG_ARM64_ERRATUM_1742098=y
CONFIG_ARM64_ERRATUM_845719=y
# CONFIG_ARM64_ERRATUM_843419 is not set
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
CONFIG_ARM64_ERRATUM_1024718=y
CONFIG_ARM64_ERRATUM_1418040=y
# CONFIG_ARM64_ERRATUM_1165522 is not set
# CONFIG_ARM64_ERRATUM_1319367 is not set
# CONFIG_ARM64_ERRATUM_1530923 is not set
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
CONFIG_ARM64_ERRATUM_2441007=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_1463225=y
CONFIG_ARM64_ERRATUM_1542419=y
CONFIG_ARM64_ERRATUM_1508412=y
CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE=y
# CONFIG_ARM64_ERRATUM_2051678 is not set
CONFIG_ARM64_ERRATUM_2077057=y
# CONFIG_ARM64_ERRATUM_2658417 is not set
CONFIG_ARM64_ERRATUM_2119858=y
CONFIG_ARM64_ERRATUM_2139208=y
CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
CONFIG_ARM64_ERRATUM_2054223=y
CONFIG_ARM64_ERRATUM_2067961=y
# CONFIG_ARM64_ERRATUM_2253138 is not set
# CONFIG_ARM64_ERRATUM_2224489 is not set
# CONFIG_ARM64_ERRATUM_2441009 is not set
CONFIG_ARM64_ERRATUM_2064142=y
# CONFIG_ARM64_ERRATUM_2038923 is not set
# CONFIG_ARM64_ERRATUM_1902691 is not set
# CONFIG_CAVIUM_ERRATUM_22375 is not set
# CONFIG_CAVIUM_ERRATUM_23154 is not set
# CONFIG_CAVIUM_ERRATUM_27456 is not set
CONFIG_CAVIUM_ERRATUM_30115=y
# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_HISILICON_ERRATUM_161600802=y
CONFIG_QCOM_FALKOR_ERRATUM_1003=y
# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set
# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set
CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set
# end of ARM errata workarounds via the alternatives framework
# CONFIG_ARM64_4K_PAGES is not set
CONFIG_ARM64_16K_PAGES=y
# CONFIG_ARM64_64K_PAGES is not set
# CONFIG_ARM64_VA_BITS_36 is not set
CONFIG_ARM64_VA_BITS_47=y
# CONFIG_ARM64_VA_BITS_48 is not set
CONFIG_ARM64_VA_BITS=47
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PA_BITS=48
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_CPU_LITTLE_ENDIAN=y
# CONFIG_SCHED_MC is not set
CONFIG_SCHED_CLUSTER=y
# CONFIG_SCHED_SMT is not set
CONFIG_NR_CPUS=256
CONFIG_HOTPLUG_CPU=y
# CONFIG_NUMA is not set
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=250
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_HW_PERF_EVENTS=y
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
CONFIG_PARAVIRT=y
CONFIG_PARAVIRT_TIME_ACCOUNTING=y
# CONFIG_KEXEC_FILE is not set
CONFIG_CRASH_DUMP=y
CONFIG_XEN_DOM0=y
CONFIG_XEN=y
CONFIG_ARCH_FORCE_MAX_ORDER=12
CONFIG_UNMAP_KERNEL_AT_EL0=y
# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
# CONFIG_ARM64_SW_TTBR0_PAN is not set
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_COMPAT=y
# CONFIG_KUSER_HELPERS is not set
CONFIG_COMPAT_ALIGNMENT_FIXUPS=y
#
# ARMv8.1 architectural features
#
CONFIG_ARM64_HW_AFDBM=y
# CONFIG_ARM64_PAN is not set
CONFIG_AS_HAS_LDAPR=y
CONFIG_AS_HAS_LSE_ATOMICS=y
# CONFIG_ARM64_USE_LSE_ATOMICS is not set
# end of ARMv8.1 architectural features
#
# ARMv8.2 architectural features
#
CONFIG_AS_HAS_ARMV8_2=y
CONFIG_AS_HAS_SHA3=y
# CONFIG_ARM64_PMEM is not set
CONFIG_ARM64_RAS_EXTN=y
CONFIG_ARM64_CNP=y
# end of ARMv8.2 architectural features
#
# ARMv8.3 architectural features
#
# CONFIG_ARM64_PTR_AUTH is not set
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y
CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y
CONFIG_AS_HAS_PAC=y
CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y
# end of ARMv8.3 architectural features
#
# ARMv8.4 architectural features
#
# CONFIG_ARM64_AMU_EXTN is not set
CONFIG_AS_HAS_ARMV8_4=y
# CONFIG_ARM64_TLB_RANGE is not set
# end of ARMv8.4 architectural features
#
# ARMv8.5 architectural features
#
CONFIG_AS_HAS_ARMV8_5=y
# CONFIG_ARM64_BTI is not set
CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y
CONFIG_ARM64_E0PD=y
CONFIG_ARM64_AS_HAS_MTE=y
# end of ARMv8.5 architectural features
#
# ARMv8.7 architectural features
#
# end of ARMv8.7 architectural features
CONFIG_ARM64_SVE=y
# CONFIG_ARM64_SME is not set
CONFIG_ARM64_MODULE_PLTS=y
# CONFIG_ARM64_PSEUDO_NMI is not set
CONFIG_RELOCATABLE=y
# CONFIG_RANDOMIZE_BASE is not set
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_STACKPROTECTOR_PER_TASK=y
CONFIG_ARCH_NR_GPIO=2048
# end of Kernel Features
#
# Boot options
#
CONFIG_CMDLINE=""
# CONFIG_EFI is not set
# end of Boot options
#
# Power management options
#
# CONFIG_SUSPEND is not set
CONFIG_PM=y
CONFIG_PM_DEBUG=y
CONFIG_PM_ADVANCED_DEBUG=y
CONFIG_PM_CLK=y
CONFIG_PM_GENERIC_DOMAINS=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_CPU_PM=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# end of Power management options
#
# CPU Power Management
#
#
# CPU Idle
#
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
# CONFIG_CPU_IDLE_GOV_TEO is not set
#
# ARM CPU Idle Drivers
#
# CONFIG_ARM_PSCI_CPUIDLE is not set
# CONFIG_ARM_CLPS711X_CPUIDLE is not set
# end of ARM CPU Idle Drivers
# end of CPU Idle
#
# CPU Frequency scaling
#
# CONFIG_CPU_FREQ is not set
# end of CPU Frequency scaling
# end of CPU Power Management
CONFIG_HAVE_KVM=y
# CONFIG_VIRTUALIZATION is not set
#
# General architecture-dependent options
#
# CONFIG_KPROBES is not set
CONFIG_JUMP_LABEL=y
CONFIG_STATIC_KEYS_SELFTEST=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
CONFIG_HAVE_NMI=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_KEEPINITRD=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
CONFIG_ARCH_WANTS_NO_INSTR=y
CONFIG_HAVE_ASM_MODVERSIONS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
CONFIG_MMU_GATHER_TABLE_FREE=y
CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_HAVE_ARCH_SECCOMP=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP=y
CONFIG_HAVE_ARCH_STACKLEAK=y
CONFIG_HAVE_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR=y
CONFIG_STACKPROTECTOR_STRONG=y
CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK=y
CONFIG_SHADOW_CALL_STACK=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
CONFIG_LTO_NONE=y
CONFIG_ARCH_SUPPORTS_CFI_CLANG=y
CONFIG_HAVE_CONTEXT_TRACKING_USER=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_MOVE_PUD=y
CONFIG_HAVE_MOVE_PMD=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_HAVE_ARCH_HUGE_VMALLOC=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_ARCH_MMAP_RND_BITS=16
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=9
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
CONFIG_ISA_BUS_API=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_COMPAT_OLD_SIGACTION=y
# CONFIG_COMPAT_32BIT_TIME is not set
CONFIG_HAVE_ARCH_VMAP_STACK=y
# CONFIG_VMAP_STACK is not set
CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
CONFIG_RANDOMIZE_KSTACK_OFFSET=y
# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_HAVE_ARCH_COMPILER_H=y
CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
# CONFIG_LOCK_EVENT_COUNTS is not set
CONFIG_ARCH_HAS_RELR=y
CONFIG_HAVE_PREEMPT_DYNAMIC=y
CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y
CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y
#
# GCOV-based kernel profiling
#
CONFIG_GCOV_KERNEL=y
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# end of GCOV-based kernel profiling
CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_GCC_PLUGINS=y
CONFIG_GCC_PLUGIN_LATENT_ENTROPY=y
# end of General architecture-dependent options
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=1
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
# CONFIG_MODULE_UNLOAD is not set
CONFIG_MODVERSIONS=y
CONFIG_ASM_MODVERSIONS=y
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
# CONFIG_MODULE_COMPRESS_NONE is not set
CONFIG_MODULE_COMPRESS_GZIP=y
# CONFIG_MODULE_COMPRESS_XZ is not set
# CONFIG_MODULE_COMPRESS_ZSTD is not set
# CONFIG_MODULE_DECOMPRESS is not set
# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
CONFIG_MODPROBE_PATH="/sbin/modprobe"
CONFIG_MODULES_TREE_LOOKUP=y
# CONFIG_BLOCK is not set
CONFIG_PADATA=y
CONFIG_ASN1=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
#
# Executable file formats
#
# CONFIG_BINFMT_ELF is not set
CONFIG_ARCH_BINFMT_ELF_STATE=y
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
CONFIG_ARCH_HAVE_ELF_PROT=y
CONFIG_ARCH_USE_GNU_PROPERTY=y
# CONFIG_BINFMT_SCRIPT is not set
# CONFIG_BINFMT_MISC is not set
# CONFIG_COREDUMP is not set
# end of Executable file formats
#
# Memory Management options
#
#
# SLAB allocator options
#
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
# CONFIG_SLAB_MERGE_DEFAULT is not set
CONFIG_SLAB_FREELIST_RANDOM=y
CONFIG_SLAB_FREELIST_HARDENED=y
CONFIG_SLUB_STATS=y
CONFIG_SLUB_CPU_PARTIAL=y
# end of SLAB allocator options
# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
CONFIG_COMPAT_BRK=y
CONFIG_SPARSEMEM=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_HAVE_FAST_GUP=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_MEMORY_ISOLATION=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
# CONFIG_MEMORY_HOTPLUG is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
CONFIG_MEMORY_BALLOON=y
CONFIG_BALLOON_COMPACTION=y
CONFIG_COMPACTION=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_PAGE_REPORTING=y
CONFIG_MIGRATION=y
CONFIG_ARCH_ENABLE_THP_MIGRATION=y
CONFIG_CONTIG_ALLOC=y
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_MMU_NOTIFIER=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
# CONFIG_MEMORY_FAILURE is not set
CONFIG_TRANSPARENT_HUGEPAGE=y
CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
CONFIG_READ_ONLY_THP_FOR_FS=y
CONFIG_CMA=y
CONFIG_CMA_DEBUG=y
# CONFIG_CMA_DEBUGFS is not set
CONFIG_CMA_SYSFS=y
CONFIG_CMA_AREAS=7
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_DEFERRED_STRUCT_PAGE_INIT=y
CONFIG_PAGE_IDLE_FLAG=y
CONFIG_IDLE_PAGE_TRACKING=y
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y
CONFIG_ARCH_HAS_PTE_DEVMAP=y
CONFIG_ARCH_HAS_ZONE_DMA_SET=y
# CONFIG_ZONE_DMA is not set
# CONFIG_ZONE_DMA32 is not set
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_PERCPU_STATS=y
CONFIG_GUP_TEST=y
CONFIG_ARCH_HAS_PTE_SPECIAL=y
CONFIG_USERFAULTFD=y
CONFIG_HAVE_ARCH_USERFAULTFD_MINOR=y
# CONFIG_LRU_GEN is not set
#
# Data Access Monitoring
#
CONFIG_DAMON=y
CONFIG_DAMON_VADDR=y
CONFIG_DAMON_PADDR=y
# CONFIG_DAMON_SYSFS is not set
# CONFIG_DAMON_DBGFS is not set
# CONFIG_DAMON_RECLAIM is not set
CONFIG_DAMON_LRU_SORT=y
# end of Data Access Monitoring
# end of Memory Management options
# CONFIG_NET is not set
#
# Device Drivers
#
CONFIG_ARM_AMBA=y
CONFIG_HAVE_PCI=y
# CONFIG_PCI is not set
CONFIG_PCCARD=y
# CONFIG_PCMCIA is not set
#
# PC-card bridges
#
#
# Generic Driver Options
#
CONFIG_AUXILIARY_BUS=y
CONFIG_UEVENT_HELPER=y
CONFIG_UEVENT_HELPER_PATH=""
# CONFIG_DEVTMPFS is not set
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
#
# Firmware loader
#
CONFIG_FW_LOADER=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_EXTRA_FIRMWARE=""
CONFIG_FW_LOADER_USER_HELPER=y
CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
CONFIG_FW_LOADER_COMPRESS=y
# CONFIG_FW_LOADER_COMPRESS_XZ is not set
# CONFIG_FW_LOADER_COMPRESS_ZSTD is not set
# CONFIG_FW_UPLOAD is not set
# end of Firmware loader
CONFIG_WANT_DEV_COREDUMP=y
CONFIG_ALLOW_DEV_COREDUMP=y
CONFIG_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_SOC_BUS=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_SPMI=y
CONFIG_REGMAP_W1=m
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_I3C=m
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
CONFIG_GENERIC_ARCH_TOPOLOGY=y
# end of Generic Driver Options
#
# Bus devices
#
CONFIG_ARM_CCI=y
# CONFIG_ARM_INTEGRATOR_LM is not set
# CONFIG_BRCMSTB_GISB_ARB is not set
# CONFIG_BT1_APB is not set
CONFIG_BT1_AXI=y
# CONFIG_HISILICON_LPC is not set
# CONFIG_INTEL_IXP4XX_EB is not set
CONFIG_QCOM_EBI2=y
CONFIG_UNIPHIER_SYSTEM_BUS=m
# CONFIG_VEXPRESS_CONFIG is not set
# CONFIG_FSL_MC_BUS is not set
# CONFIG_MHI_BUS is not set
CONFIG_MHI_BUS_EP=y
# end of Bus devices
#
# Firmware Drivers
#
#
# ARM System Control and Management Interface Protocol
#
CONFIG_ARM_SCMI_PROTOCOL=m
CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
CONFIG_ARM_SCMI_HAVE_SHMEM=y
CONFIG_ARM_SCMI_HAVE_MSG=y
CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
CONFIG_ARM_SCMI_TRANSPORT_SMC=y
# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
CONFIG_ARM_SCMI_TRANSPORT_VIRTIO=y
# CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_VERSION1_COMPLIANCE is not set
CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE=y
# CONFIG_ARM_SCMI_POWER_DOMAIN is not set
CONFIG_ARM_SCMI_POWER_CONTROL=y
# end of ARM System Control and Management Interface Protocol
CONFIG_ARM_SCPI_PROTOCOL=m
# CONFIG_ARM_SCPI_POWER_DOMAIN is not set
CONFIG_FIRMWARE_MEMMAP=y
CONFIG_INTEL_STRATIX10_SERVICE=m
# CONFIG_INTEL_STRATIX10_RSU is not set
CONFIG_MTK_ADSP_IPC=m
CONFIG_QCOM_SCM=m
CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT=y
CONFIG_TI_SCI_PROTOCOL=y
# CONFIG_TURRIS_MOX_RWTM is not set
# CONFIG_ARM_FFA_TRANSPORT is not set
CONFIG_BCM47XX_NVRAM=y
CONFIG_BCM47XX_SPROM=y
CONFIG_GOOGLE_FIRMWARE=y
CONFIG_GOOGLE_COREBOOT_TABLE=m
# CONFIG_GOOGLE_MEMCONSOLE_COREBOOT is not set
# CONFIG_GOOGLE_VPD is not set
CONFIG_IMX_DSP=m
CONFIG_IMX_SCU=y
CONFIG_IMX_SCU_PD=y
CONFIG_ARM_PSCI_FW=y
CONFIG_HAVE_ARM_SMCCC=y
CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
CONFIG_ARM_SMCCC_SOC_ID=y
#
# Tegra firmware driver
#
# end of Tegra firmware driver
#
# Zynq MPSoC Firmware Drivers
#
CONFIG_ZYNQMP_FIRMWARE=y
CONFIG_ZYNQMP_FIRMWARE_DEBUG=y
# end of Zynq MPSoC Firmware Drivers
# end of Firmware Drivers
# CONFIG_GNSS is not set
CONFIG_MTD=m
# CONFIG_MTD_TESTS is not set
#
# Partition parsers
#
CONFIG_MTD_AR7_PARTS=m
# CONFIG_MTD_BCM63XX_PARTS is not set
CONFIG_MTD_BRCM_U_BOOT=m
CONFIG_MTD_CMDLINE_PARTS=m
CONFIG_MTD_OF_PARTS=m
CONFIG_MTD_OF_PARTS_BCM4908=y
# CONFIG_MTD_OF_PARTS_LINKSYS_NS is not set
CONFIG_MTD_PARSER_IMAGETAG=m
# CONFIG_MTD_AFS_PARTS is not set
# CONFIG_MTD_PARSER_TRX is not set
# CONFIG_MTD_SHARPSL_PARTS is not set
# CONFIG_MTD_REDBOOT_PARTS is not set
# end of Partition parsers
#
# User Modules And Translation Layers
#
CONFIG_MTD_OOPS=m
CONFIG_MTD_PARTITIONED_MASTER=y
#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
CONFIG_MTD_JEDECPROBE=m
CONFIG_MTD_GEN_PROBE=m
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
CONFIG_MTD_CFI_INTELEXT=m
CONFIG_MTD_CFI_AMDSTD=m
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=m
CONFIG_MTD_RAM=m
CONFIG_MTD_ROM=m
CONFIG_MTD_ABSENT=m
# end of RAM/ROM/Flash chip drivers
#
# Mapping drivers for chip access
#
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=m
# CONFIG_MTD_PHYSMAP_COMPAT is not set
CONFIG_MTD_PHYSMAP_OF=y
# CONFIG_MTD_PHYSMAP_BT1_ROM is not set
# CONFIG_MTD_PHYSMAP_VERSATILE is not set
CONFIG_MTD_PHYSMAP_GEMINI=y
# CONFIG_MTD_PHYSMAP_GPIO_ADDR is not set
CONFIG_MTD_TS5500=m
# CONFIG_MTD_PLATRAM is not set
# end of Mapping drivers for chip access
#
# Self-contained MTD device drivers
#
CONFIG_MTD_SPEAR_SMI=m
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
#
# Disk-On-Chip Device Drivers
#
CONFIG_MTD_DOCG3=m
CONFIG_BCH_CONST_M=14
CONFIG_BCH_CONST_T=4
# end of Self-contained MTD device drivers
#
# NAND
#
CONFIG_MTD_NAND_CORE=m
CONFIG_MTD_ONENAND=m
# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
# CONFIG_MTD_ONENAND_GENERIC is not set
# CONFIG_MTD_ONENAND_SAMSUNG is not set
# CONFIG_MTD_ONENAND_OTP is not set
# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
CONFIG_MTD_RAW_NAND=m
#
# Raw/parallel NAND flash controllers
#
CONFIG_MTD_NAND_DENALI=m
CONFIG_MTD_NAND_DENALI_DT=m
CONFIG_MTD_NAND_AMS_DELTA=m
CONFIG_MTD_NAND_OMAP2=m
# CONFIG_MTD_NAND_OMAP_BCH is not set
# CONFIG_MTD_NAND_SHARPSL is not set
CONFIG_MTD_NAND_ATMEL=m
CONFIG_MTD_NAND_MARVELL=m
# CONFIG_MTD_NAND_SLC_LPC32XX is not set
CONFIG_MTD_NAND_MLC_LPC32XX=m
CONFIG_MTD_NAND_BRCMNAND=m
# CONFIG_MTD_NAND_BRCMNAND_BCM63XX is not set
CONFIG_MTD_NAND_BRCMNAND_BCMA=m
# CONFIG_MTD_NAND_BRCMNAND_BCMBCA is not set
# CONFIG_MTD_NAND_BRCMNAND_BRCMSTB is not set
CONFIG_MTD_NAND_BRCMNAND_IPROC=m
CONFIG_MTD_NAND_BCM47XXNFLASH=m
CONFIG_MTD_NAND_OXNAS=m
CONFIG_MTD_NAND_GPMI_NAND=m
CONFIG_MTD_NAND_FSL_IFC=m
CONFIG_MTD_NAND_VF610_NFC=m
# CONFIG_MTD_NAND_MXC is not set
# CONFIG_MTD_NAND_SH_FLCTL is not set
CONFIG_MTD_NAND_DAVINCI=m
# CONFIG_MTD_NAND_TXX9NDFMC is not set
CONFIG_MTD_NAND_JZ4780=m
CONFIG_MTD_NAND_INGENIC_ECC=y
CONFIG_MTD_NAND_JZ4740_ECC=m
CONFIG_MTD_NAND_JZ4725B_BCH=m
CONFIG_MTD_NAND_JZ4780_BCH=m
# CONFIG_MTD_NAND_FSMC is not set
CONFIG_MTD_NAND_SUNXI=m
CONFIG_MTD_NAND_HISI504=m
CONFIG_MTD_NAND_QCOM=m
CONFIG_MTD_NAND_MXIC=m
# CONFIG_MTD_NAND_TEGRA is not set
CONFIG_MTD_NAND_STM32_FMC2=m
CONFIG_MTD_NAND_MESON=m
# CONFIG_MTD_NAND_GPIO is not set
CONFIG_MTD_NAND_PLATFORM=m
CONFIG_MTD_NAND_CADENCE=m
CONFIG_MTD_NAND_ARASAN=m
# CONFIG_MTD_NAND_INTEL_LGM is not set
CONFIG_MTD_NAND_ROCKCHIP=m
# CONFIG_MTD_NAND_PL35X is not set
CONFIG_MTD_NAND_RENESAS=m
#
# Misc
#
CONFIG_MTD_NAND_NANDSIM=m
CONFIG_MTD_NAND_DISKONCHIP=m
# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set
CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0
# CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set
#
# ECC engine support
#
CONFIG_MTD_NAND_ECC=y
# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set
# CONFIG_MTD_NAND_ECC_SW_BCH is not set
# CONFIG_MTD_NAND_ECC_MXIC is not set
# CONFIG_MTD_NAND_ECC_MEDIATEK is not set
# end of ECC engine support
# end of NAND
#
# LPDDR & LPDDR2 PCM memory drivers
#
# CONFIG_MTD_LPDDR is not set
# end of LPDDR & LPDDR2 PCM memory drivers
CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
# CONFIG_MTD_UBI_FASTMAP is not set
CONFIG_MTD_UBI_GLUEBI=m
# CONFIG_MTD_HYPERBUS is not set
CONFIG_DTC=y
CONFIG_OF=y
CONFIG_OF_UNITTEST=y
CONFIG_OF_ALL_DTBS=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_KOBJ=y
CONFIG_OF_DYNAMIC=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_OF_OVERLAY=y
CONFIG_PARPORT=m
# CONFIG_PARPORT_AX88796 is not set
CONFIG_PARPORT_1284=y
CONFIG_PARPORT_NOT_PC=y
#
# NVME Support
#
# end of NVME Support
#
# Misc devices
#
CONFIG_SENSORS_LIS3LV02D=m
CONFIG_AD525X_DPOT=m
CONFIG_AD525X_DPOT_I2C=m
# CONFIG_DUMMY_IRQ is not set
CONFIG_ICS932S401=y
CONFIG_ATMEL_SSC=m
CONFIG_ENCLOSURE_SERVICES=m
CONFIG_HI6421V600_IRQ=y
CONFIG_QCOM_COINCELL=m
# CONFIG_QCOM_FASTRPC is not set
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
CONFIG_ISL29020=y
CONFIG_SENSORS_TSL2550=y
CONFIG_SENSORS_BH1770=m
CONFIG_SENSORS_APDS990X=m
CONFIG_HMC6352=y
CONFIG_DS1682=m
# CONFIG_SRAM is not set
CONFIG_XILINX_SDFEC=m
CONFIG_MISC_RTSX=m
CONFIG_HISI_HIKEY_USB=y
CONFIG_OPEN_DICE=m
CONFIG_VCPU_STALL_DETECTOR=m
CONFIG_C2PORT=m
#
# EEPROM support
#
CONFIG_EEPROM_AT24=m
CONFIG_EEPROM_LEGACY=m
# CONFIG_EEPROM_MAX6875 is not set
# CONFIG_EEPROM_93CX6 is not set
CONFIG_EEPROM_IDT_89HPESX=y
CONFIG_EEPROM_EE1004=y
# end of EEPROM support
#
# Texas Instruments shared transport line discipline
#
# end of Texas Instruments shared transport line discipline
CONFIG_SENSORS_LIS3_I2C=m
CONFIG_ALTERA_STAPL=m
# CONFIG_ECHO is not set
CONFIG_MISC_RTSX_USB=m
# CONFIG_UACCE is not set
CONFIG_PVPANIC=y
CONFIG_PVPANIC_MMIO=y
# end of Misc devices
#
# SCSI device support
#
# end of SCSI device support
#
# IEEE 1394 (FireWire) support
#
CONFIG_FIREWIRE=y
# end of IEEE 1394 (FireWire) support
#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_LEDS is not set
CONFIG_INPUT_FF_MEMLESS=y
CONFIG_INPUT_SPARSEKMAP=y
CONFIG_INPUT_MATRIXKMAP=y
CONFIG_INPUT_VIVALDIFMAP=y
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
CONFIG_INPUT_JOYDEV=m
CONFIG_INPUT_EVDEV=m
CONFIG_INPUT_EVBUG=m
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADC is not set
CONFIG_KEYBOARD_ADP5588=m
CONFIG_KEYBOARD_ADP5589=y
CONFIG_KEYBOARD_ATKBD=m
CONFIG_KEYBOARD_QT1050=m
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
CONFIG_KEYBOARD_CLPS711X=y
CONFIG_KEYBOARD_DLINK_DIR685=m
# CONFIG_KEYBOARD_LKKBD is not set
CONFIG_KEYBOARD_EP93XX=y
# CONFIG_KEYBOARD_GPIO is not set
CONFIG_KEYBOARD_GPIO_POLLED=m
CONFIG_KEYBOARD_TCA6416=m
CONFIG_KEYBOARD_TCA8418=y
CONFIG_KEYBOARD_MATRIX=y
CONFIG_KEYBOARD_LM8323=y
CONFIG_KEYBOARD_LM8333=m
CONFIG_KEYBOARD_MAX7359=m
# CONFIG_KEYBOARD_MCS is not set
CONFIG_KEYBOARD_MPR121=m
CONFIG_KEYBOARD_SNVS_PWRKEY=m
CONFIG_KEYBOARD_IMX=m
CONFIG_KEYBOARD_IMX_SC_KEY=m
# CONFIG_KEYBOARD_NEWTON is not set
CONFIG_KEYBOARD_OPENCORES=m
# CONFIG_KEYBOARD_PINEPHONE is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
CONFIG_KEYBOARD_GOLDFISH_EVENTS=m
CONFIG_KEYBOARD_STOWAWAY=y
CONFIG_KEYBOARD_ST_KEYSCAN=m
CONFIG_KEYBOARD_SUNKBD=m
CONFIG_KEYBOARD_SH_KEYSC=m
CONFIG_KEYBOARD_STMPE=m
CONFIG_KEYBOARD_IQS62X=m
CONFIG_KEYBOARD_OMAP4=y
CONFIG_KEYBOARD_TM2_TOUCHKEY=m
CONFIG_KEYBOARD_TWL4030=m
CONFIG_KEYBOARD_XTKBD=m
CONFIG_KEYBOARD_CAP11XX=m
CONFIG_KEYBOARD_BCM=m
CONFIG_KEYBOARD_MT6779=m
# CONFIG_KEYBOARD_MTK_PMIC is not set
CONFIG_KEYBOARD_CYPRESS_SF=m
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_BYD=y
# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
# CONFIG_MOUSE_PS2_SYNAPTICS is not set
# CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS is not set
# CONFIG_MOUSE_PS2_CYPRESS is not set
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_PS2_ELANTECH is not set
CONFIG_MOUSE_PS2_SENTELIC=y
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
CONFIG_MOUSE_PS2_FOCALTECH=y
CONFIG_MOUSE_SERIAL=y
# CONFIG_MOUSE_APPLETOUCH is not set
CONFIG_MOUSE_BCM5974=m
CONFIG_MOUSE_CYAPA=y
CONFIG_MOUSE_ELAN_I2C=y
CONFIG_MOUSE_ELAN_I2C_I2C=y
CONFIG_MOUSE_ELAN_I2C_SMBUS=y
CONFIG_MOUSE_VSXXXAA=m
# CONFIG_MOUSE_GPIO is not set
# CONFIG_MOUSE_SYNAPTICS_I2C is not set
# CONFIG_MOUSE_SYNAPTICS_USB is not set
CONFIG_INPUT_JOYSTICK=y
# CONFIG_JOYSTICK_ANALOG is not set
# CONFIG_JOYSTICK_A3D is not set
CONFIG_JOYSTICK_ADC=m
# CONFIG_JOYSTICK_ADI is not set
# CONFIG_JOYSTICK_COBRA is not set
# CONFIG_JOYSTICK_GF2K is not set
CONFIG_JOYSTICK_GRIP=y
# CONFIG_JOYSTICK_GRIP_MP is not set
CONFIG_JOYSTICK_GUILLEMOT=y
CONFIG_JOYSTICK_INTERACT=m
# CONFIG_JOYSTICK_SIDEWINDER is not set
CONFIG_JOYSTICK_TMDC=m
CONFIG_JOYSTICK_IFORCE=y
CONFIG_JOYSTICK_IFORCE_USB=m
# CONFIG_JOYSTICK_IFORCE_232 is not set
CONFIG_JOYSTICK_WARRIOR=m
CONFIG_JOYSTICK_MAGELLAN=m
# CONFIG_JOYSTICK_SPACEORB is not set
CONFIG_JOYSTICK_SPACEBALL=m
# CONFIG_JOYSTICK_STINGER is not set
CONFIG_JOYSTICK_TWIDJOY=m
CONFIG_JOYSTICK_ZHENHUA=m
# CONFIG_JOYSTICK_DB9 is not set
CONFIG_JOYSTICK_GAMECON=m
CONFIG_JOYSTICK_TURBOGRAFX=m
CONFIG_JOYSTICK_AS5011=m
CONFIG_JOYSTICK_JOYDUMP=m
CONFIG_JOYSTICK_XPAD=y
# CONFIG_JOYSTICK_XPAD_FF is not set
# CONFIG_JOYSTICK_XPAD_LEDS is not set
CONFIG_JOYSTICK_PXRC=m
CONFIG_JOYSTICK_QWIIC=y
# CONFIG_JOYSTICK_FSIA6B is not set
CONFIG_JOYSTICK_SENSEHAT=m
CONFIG_INPUT_TABLET=y
# CONFIG_TABLET_USB_ACECAD is not set
CONFIG_TABLET_USB_AIPTEK=m
# CONFIG_TABLET_USB_HANWANG is not set
CONFIG_TABLET_USB_KBTAB=y
# CONFIG_TABLET_USB_PEGASUS is not set
CONFIG_TABLET_SERIAL_WACOM4=y
# CONFIG_INPUT_TOUCHSCREEN is not set
CONFIG_INPUT_MISC=y
CONFIG_INPUT_88PM860X_ONKEY=m
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ATMEL_CAPTOUCH is not set
CONFIG_INPUT_BMA150=m
# CONFIG_INPUT_E3X0_BUTTON is not set
CONFIG_INPUT_MAX77650_ONKEY=m
# CONFIG_INPUT_MAX77693_HAPTIC is not set
CONFIG_INPUT_MC13783_PWRBUTTON=m
CONFIG_INPUT_MMA8450=m
# CONFIG_INPUT_GPIO_BEEPER is not set
CONFIG_INPUT_GPIO_DECODER=y
CONFIG_INPUT_GPIO_VIBRA=y
CONFIG_INPUT_ATI_REMOTE2=y
CONFIG_INPUT_KEYSPAN_REMOTE=y
CONFIG_INPUT_KXTJ9=m
CONFIG_INPUT_POWERMATE=m
# CONFIG_INPUT_YEALINK is not set
# CONFIG_INPUT_CM109 is not set
CONFIG_INPUT_REGULATOR_HAPTIC=m
CONFIG_INPUT_RETU_PWRBUTTON=m
# CONFIG_INPUT_TPS65218_PWRBUTTON is not set
CONFIG_INPUT_TWL4030_PWRBUTTON=y
# CONFIG_INPUT_TWL4030_VIBRA is not set
# CONFIG_INPUT_TWL6040_VIBRA is not set
# CONFIG_INPUT_UINPUT is not set
CONFIG_INPUT_PCF50633_PMU=m
CONFIG_INPUT_PCF8574=m
# CONFIG_INPUT_PWM_BEEPER is not set
CONFIG_INPUT_PWM_VIBRA=m
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
CONFIG_INPUT_DA7280_HAPTICS=y
# CONFIG_INPUT_DA9055_ONKEY is not set
CONFIG_INPUT_DA9063_ONKEY=m
# CONFIG_INPUT_ADXL34X is not set
CONFIG_INPUT_IBM_PANEL=y
CONFIG_INPUT_IMS_PCU=m
CONFIG_INPUT_IQS269A=y
CONFIG_INPUT_IQS626A=m
CONFIG_INPUT_IQS7222=m
CONFIG_INPUT_CMA3000=y
CONFIG_INPUT_CMA3000_I2C=y
CONFIG_INPUT_XEN_KBDDEV_FRONTEND=m
CONFIG_INPUT_DRV260X_HAPTICS=m
CONFIG_INPUT_DRV2665_HAPTICS=m
CONFIG_INPUT_DRV2667_HAPTICS=y
CONFIG_INPUT_HISI_POWERKEY=m
# CONFIG_INPUT_SC27XX_VIBRA is not set
# CONFIG_INPUT_RT5120_PWRKEY is not set
CONFIG_INPUT_STPMIC1_ONKEY=m
CONFIG_RMI4_CORE=y
# CONFIG_RMI4_I2C is not set
CONFIG_RMI4_SMB=y
CONFIG_RMI4_F03=y
CONFIG_RMI4_F03_SERIO=y
CONFIG_RMI4_2D_SENSOR=y
CONFIG_RMI4_F11=y
CONFIG_RMI4_F12=y
CONFIG_RMI4_F30=y
CONFIG_RMI4_F34=y
# CONFIG_RMI4_F3A is not set
CONFIG_RMI4_F55=y
#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=y
CONFIG_SERIO_PARKBD=m
CONFIG_SERIO_AMBAKMI=m
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
# CONFIG_SERIO_ALTERA_PS2 is not set
CONFIG_SERIO_PS2MULT=y
CONFIG_SERIO_ARC_PS2=y
CONFIG_SERIO_APBPS2=m
CONFIG_SERIO_OLPC_APSP=m
CONFIG_SERIO_SUN4I_PS2=y
# CONFIG_SERIO_GPIO_PS2 is not set
CONFIG_USERIO=y
CONFIG_GAMEPORT=y
# CONFIG_GAMEPORT_NS558 is not set
CONFIG_GAMEPORT_L4=m
# end of Hardware I/O ports
# end of Input device support
#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_LDISC_AUTOLOAD=y
#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
# CONFIG_SERIAL_AMBA_PL010 is not set
CONFIG_SERIAL_AMBA_PL011=y
# CONFIG_SERIAL_AMBA_PL011_CONSOLE is not set
# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set
# CONFIG_SERIAL_ATMEL is not set
# CONFIG_SERIAL_MESON is not set
CONFIG_SERIAL_CLPS711X=y
# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
CONFIG_SERIAL_SAMSUNG=y
CONFIG_SERIAL_SAMSUNG_UARTS_4=y
CONFIG_SERIAL_SAMSUNG_UARTS=4
# CONFIG_SERIAL_SAMSUNG_CONSOLE is not set
CONFIG_SERIAL_TEGRA=y
CONFIG_SERIAL_TEGRA_TCU=m
CONFIG_SERIAL_IMX=m
CONFIG_SERIAL_IMX_CONSOLE=m
CONFIG_SERIAL_IMX_EARLYCON=y
# CONFIG_SERIAL_UARTLITE is not set
# CONFIG_SERIAL_SH_SCI is not set
# CONFIG_SERIAL_HS_LPC32XX is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_SERIAL_MSM=y
# CONFIG_SERIAL_MSM_CONSOLE is not set
CONFIG_SERIAL_VT8500=y
CONFIG_SERIAL_VT8500_CONSOLE=y
# CONFIG_SERIAL_OMAP is not set
CONFIG_SERIAL_SIFIVE=y
# CONFIG_SERIAL_SIFIVE_CONSOLE is not set
# CONFIG_SERIAL_LANTIQ is not set
CONFIG_SERIAL_SCCNXP=m
CONFIG_SERIAL_SC16IS7XX_CORE=y
CONFIG_SERIAL_SC16IS7XX=y
CONFIG_SERIAL_SC16IS7XX_I2C=y
CONFIG_SERIAL_TIMBERDALE=y
CONFIG_SERIAL_BCM63XX=y
CONFIG_SERIAL_BCM63XX_CONSOLE=y
CONFIG_SERIAL_ALTERA_JTAGUART=y
CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE=y
CONFIG_SERIAL_ALTERA_JTAGUART_CONSOLE_BYPASS=y
CONFIG_SERIAL_ALTERA_UART=m
CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4
CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200
CONFIG_SERIAL_MXS_AUART=m
# CONFIG_SERIAL_XILINX_PS_UART is not set
# CONFIG_SERIAL_MPS2_UART is not set
# CONFIG_SERIAL_ARC is not set
CONFIG_SERIAL_FSL_LPUART=m
# CONFIG_SERIAL_FSL_LPUART_CONSOLE is not set
# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
CONFIG_SERIAL_ST_ASC=y
# CONFIG_SERIAL_ST_ASC_CONSOLE is not set
CONFIG_SERIAL_MEN_Z135=m
# CONFIG_SERIAL_SPRD is not set
# CONFIG_SERIAL_STM32 is not set
CONFIG_SERIAL_MVEBU_UART=y
# CONFIG_SERIAL_MVEBU_CONSOLE is not set
# CONFIG_SERIAL_OWL is not set
# CONFIG_SERIAL_RDA is not set
# CONFIG_SERIAL_MILBEAUT_USIO is not set
CONFIG_SERIAL_LITEUART=y
CONFIG_SERIAL_LITEUART_MAX_PORTS=1
CONFIG_SERIAL_LITEUART_CONSOLE=y
# CONFIG_SERIAL_SUNPLUS is not set
# end of Serial drivers
CONFIG_SERIAL_MCTRL_GPIO=y
# CONFIG_SERIAL_NONSTANDARD is not set
CONFIG_NULL_TTY=y
# CONFIG_HVC_XEN is not set
# CONFIG_HVC_DCC is not set
CONFIG_RPMSG_TTY=m
# CONFIG_SERIAL_DEV_BUS is not set
# CONFIG_TTY_PRINTK is not set
CONFIG_PRINTER=m
# CONFIG_LP_CONSOLE is not set
# CONFIG_PPDEV is not set
# CONFIG_VIRTIO_CONSOLE is not set
# CONFIG_IPMI_HANDLER is not set
CONFIG_IPMI_KCS_BMC=m
CONFIG_ASPEED_KCS_IPMI_BMC=m
CONFIG_NPCM7XX_KCS_IPMI_BMC=m
CONFIG_IPMI_KCS_BMC_CDEV_IPMI=m
CONFIG_IPMI_KCS_BMC_SERIO=m
# CONFIG_ASPEED_BT_IPMI_BMC is not set
CONFIG_IPMB_DEVICE_INTERFACE=y
CONFIG_HW_RANDOM=y
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
CONFIG_HW_RANDOM_ATMEL=y
CONFIG_HW_RANDOM_BA431=m
# CONFIG_HW_RANDOM_BCM2835 is not set
CONFIG_HW_RANDOM_IPROC_RNG200=m
CONFIG_HW_RANDOM_IXP4XX=y
# CONFIG_HW_RANDOM_OMAP is not set
# CONFIG_HW_RANDOM_OMAP3_ROM is not set
CONFIG_HW_RANDOM_VIRTIO=m
# CONFIG_HW_RANDOM_IMX_RNGC is not set
CONFIG_HW_RANDOM_NOMADIK=y
# CONFIG_HW_RANDOM_HISI is not set
# CONFIG_HW_RANDOM_XGENE is not set
# CONFIG_HW_RANDOM_STM32 is not set
CONFIG_HW_RANDOM_POLARFIRE_SOC=m
# CONFIG_HW_RANDOM_MESON is not set
# CONFIG_HW_RANDOM_MTK is not set
# CONFIG_HW_RANDOM_EXYNOS is not set
CONFIG_HW_RANDOM_NPCM=y
CONFIG_HW_RANDOM_KEYSTONE=m
# CONFIG_HW_RANDOM_CCTRNG is not set
CONFIG_HW_RANDOM_XIPHERA=y
CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y
CONFIG_DEVMEM=y
CONFIG_TCG_TPM=y
CONFIG_HW_RANDOM_TPM=y
CONFIG_TCG_TIS_CORE=m
CONFIG_TCG_TIS=m
# CONFIG_TCG_TIS_I2C is not set
# CONFIG_TCG_TIS_SYNQUACER is not set
CONFIG_TCG_TIS_I2C_CR50=m
CONFIG_TCG_TIS_I2C_ATMEL=y
CONFIG_TCG_TIS_I2C_INFINEON=y
CONFIG_TCG_TIS_I2C_NUVOTON=y
# CONFIG_TCG_XEN is not set
# CONFIG_TCG_VTPM_PROXY is not set
# CONFIG_TCG_TIS_ST33ZP24_I2C is not set
CONFIG_XILLYBUS_CLASS=y
CONFIG_XILLYBUS=y
# CONFIG_XILLYBUS_OF is not set
CONFIG_XILLYUSB=y
CONFIG_RANDOM_TRUST_CPU=y
CONFIG_RANDOM_TRUST_BOOTLOADER=y
# end of Character devices
#
# I2C support
#
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
# CONFIG_I2C_COMPAT is not set
# CONFIG_I2C_CHARDEV is not set
CONFIG_I2C_MUX=m
#
# Multiplexer I2C Chip support
#
CONFIG_I2C_ARB_GPIO_CHALLENGE=m
CONFIG_I2C_MUX_GPIO=m
# CONFIG_I2C_MUX_GPMUX is not set
CONFIG_I2C_MUX_LTC4306=m
CONFIG_I2C_MUX_PCA9541=m
CONFIG_I2C_MUX_PCA954x=m
CONFIG_I2C_MUX_PINCTRL=m
# CONFIG_I2C_MUX_REG is not set
# CONFIG_I2C_DEMUX_PINCTRL is not set
CONFIG_I2C_MUX_MLXCPLD=m
# end of Multiplexer I2C Chip support
# CONFIG_I2C_HELPER_AUTO is not set
CONFIG_I2C_SMBUS=y
#
# I2C Algorithms
#
CONFIG_I2C_ALGOBIT=y
CONFIG_I2C_ALGOPCF=y
CONFIG_I2C_ALGOPCA=y
# end of I2C Algorithms
#
# I2C Hardware Bus support
#
CONFIG_I2C_HIX5HD2=m
#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_ALTERA is not set
CONFIG_I2C_ASPEED=y
CONFIG_I2C_AT91=y
CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL=m
CONFIG_I2C_AXXIA=y
# CONFIG_I2C_BCM2835 is not set
CONFIG_I2C_BCM_IPROC=m
CONFIG_I2C_BCM_KONA=y
CONFIG_I2C_BRCMSTB=y
CONFIG_I2C_CADENCE=y
CONFIG_I2C_CBUS_GPIO=m
CONFIG_I2C_DAVINCI=m
# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
# CONFIG_I2C_DIGICOLOR is not set
# CONFIG_I2C_EMEV2 is not set
CONFIG_I2C_EXYNOS5=y
# CONFIG_I2C_GPIO is not set
CONFIG_I2C_HIGHLANDER=y
CONFIG_I2C_HISI=m
CONFIG_I2C_IMG=y
# CONFIG_I2C_IMX is not set
CONFIG_I2C_IMX_LPI2C=m
CONFIG_I2C_IOP3XX=m
CONFIG_I2C_JZ4780=y
# CONFIG_I2C_LPC2K is not set
# CONFIG_I2C_MESON is not set
# CONFIG_I2C_MICROCHIP_CORE is not set
# CONFIG_I2C_MT65XX is not set
CONFIG_I2C_MT7621=y
CONFIG_I2C_MV64XXX=y
CONFIG_I2C_MXS=m
CONFIG_I2C_NOMADIK=y
# CONFIG_I2C_NPCM is not set
CONFIG_I2C_OCORES=y
# CONFIG_I2C_OMAP is not set
# CONFIG_I2C_OWL is not set
# CONFIG_I2C_APPLE is not set
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_PNX is not set
CONFIG_I2C_PXA=y
# CONFIG_I2C_PXA_SLAVE is not set
# CONFIG_I2C_QCOM_CCI is not set
# CONFIG_I2C_QUP is not set
# CONFIG_I2C_RIIC is not set
CONFIG_I2C_RK3X=m
# CONFIG_I2C_RZV2M is not set
CONFIG_I2C_S3C2410=y
# CONFIG_I2C_SH_MOBILE is not set
CONFIG_I2C_SIMTEC=m
# CONFIG_I2C_SPRD is not set
CONFIG_I2C_ST=y
CONFIG_I2C_STM32F4=m
CONFIG_I2C_STM32F7=y
CONFIG_I2C_SUN6I_P2WI=m
CONFIG_I2C_SYNQUACER=y
CONFIG_I2C_TEGRA=y
CONFIG_I2C_TEGRA_BPMP=m
# CONFIG_I2C_UNIPHIER is not set
CONFIG_I2C_UNIPHIER_F=y
# CONFIG_I2C_VERSATILE is not set
# CONFIG_I2C_WMT is not set
CONFIG_I2C_XILINX=y
# CONFIG_I2C_XLP9XX is not set
CONFIG_I2C_RCAR=m
#
# External I2C/SMBus adapter drivers
#
CONFIG_I2C_DIOLAN_U2C=m
CONFIG_I2C_DLN2=m
CONFIG_I2C_CP2615=m
# CONFIG_I2C_PARPORT is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
CONFIG_I2C_TAOS_EVM=y
CONFIG_I2C_TINY_USB=m
# CONFIG_I2C_VIPERBOARD is not set
#
# Other I2C/SMBus bus drivers
#
CONFIG_I2C_MLXCPLD=y
CONFIG_I2C_XGENE_SLIMPRO=y
# CONFIG_I2C_VIRTIO is not set
# end of I2C Hardware Bus support
# CONFIG_I2C_STUB is not set
CONFIG_I2C_SLAVE=y
CONFIG_I2C_SLAVE_EEPROM=y
CONFIG_I2C_SLAVE_TESTUNIT=y
# CONFIG_I2C_DEBUG_CORE is not set
CONFIG_I2C_DEBUG_ALGO=y
CONFIG_I2C_DEBUG_BUS=y
# end of I2C support
CONFIG_I3C=y
# CONFIG_CDNS_I3C_MASTER is not set
CONFIG_DW_I3C_MASTER=y
CONFIG_SVC_I3C_MASTER=m
CONFIG_MIPI_I3C_HCI=m
# CONFIG_SPI is not set
CONFIG_SPMI=y
# CONFIG_SPMI_HISI3670 is not set
CONFIG_SPMI_MSM_PMIC_ARB=y
CONFIG_SPMI_MTK_PMIF=m
# CONFIG_HSI is not set
CONFIG_PPS=m
CONFIG_PPS_DEBUG=y
#
# PPS clients support
#
# CONFIG_PPS_CLIENT_KTIMER is not set
CONFIG_PPS_CLIENT_LDISC=m
# CONFIG_PPS_CLIENT_PARPORT is not set
# CONFIG_PPS_CLIENT_GPIO is not set
#
# PPS generators support
#
#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
# end of PTP clock support
CONFIG_PINCTRL=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_PINMUX=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_PINCONF=y
CONFIG_GENERIC_PINCONF=y
# CONFIG_DEBUG_PINCTRL is not set
CONFIG_PINCTRL_AMD=y
CONFIG_PINCTRL_APPLE_GPIO=y
CONFIG_PINCTRL_AT91PIO4=y
# CONFIG_PINCTRL_BM1880 is not set
CONFIG_PINCTRL_CY8C95X0=y
CONFIG_PINCTRL_DA850_PUPD=y
# CONFIG_PINCTRL_DA9062 is not set
# CONFIG_PINCTRL_EQUILIBRIUM is not set
# CONFIG_PINCTRL_INGENIC is not set
CONFIG_PINCTRL_KEEMBAY=y
# CONFIG_PINCTRL_LPC18XX is not set
CONFIG_PINCTRL_MAX77620=m
# CONFIG_PINCTRL_MCP23S08 is not set
CONFIG_PINCTRL_MICROCHIP_SGPIO=m
CONFIG_PINCTRL_OCELOT=y
CONFIG_PINCTRL_PISTACHIO=y
CONFIG_PINCTRL_ROCKCHIP=y
CONFIG_PINCTRL_SINGLE=m
# CONFIG_PINCTRL_STMFX is not set
CONFIG_PINCTRL_SX150X=y
CONFIG_PINCTRL_THUNDERBAY=y
CONFIG_PINCTRL_ZYNQMP=y
# CONFIG_PINCTRL_OWL is not set
CONFIG_PINCTRL_ASPEED=y
CONFIG_PINCTRL_ASPEED_G4=y
# CONFIG_PINCTRL_ASPEED_G5 is not set
# CONFIG_PINCTRL_ASPEED_G6 is not set
# CONFIG_PINCTRL_BCM281XX is not set
CONFIG_PINCTRL_BCM2835=y
CONFIG_PINCTRL_BCM4908=m
CONFIG_PINCTRL_BCM63XX=y
CONFIG_PINCTRL_BCM6318=y
CONFIG_PINCTRL_BCM6328=y
CONFIG_PINCTRL_BCM6358=y
CONFIG_PINCTRL_BCM6362=y
CONFIG_PINCTRL_BCM6368=y
CONFIG_PINCTRL_BCM63268=y
CONFIG_PINCTRL_IPROC_GPIO=y
# CONFIG_PINCTRL_CYGNUS_MUX is not set
CONFIG_PINCTRL_NS=y
CONFIG_PINCTRL_NSP_GPIO=y
# CONFIG_PINCTRL_NS2_MUX is not set
# CONFIG_PINCTRL_NSP_MUX is not set
CONFIG_PINCTRL_BERLIN=y
CONFIG_PINCTRL_AS370=y
# CONFIG_PINCTRL_BERLIN_BG4CT is not set
# CONFIG_PINCTRL_LOCHNAGAR is not set
CONFIG_PINCTRL_IMX=y
# CONFIG_PINCTRL_IMX8MM is not set
CONFIG_PINCTRL_IMX8MN=y
# CONFIG_PINCTRL_IMX8MP is not set
CONFIG_PINCTRL_IMX8MQ=m
#
# Intel pinctrl drivers
#
# end of Intel pinctrl drivers
#
# MediaTek pinctrl drivers
#
CONFIG_EINT_MTK=y
CONFIG_PINCTRL_MTK=y
CONFIG_PINCTRL_MTK_V2=y
CONFIG_PINCTRL_MTK_MOORE=y
CONFIG_PINCTRL_MTK_PARIS=y
# CONFIG_PINCTRL_MT2701 is not set
CONFIG_PINCTRL_MT7623=y
# CONFIG_PINCTRL_MT7629 is not set
CONFIG_PINCTRL_MT8135=y
# CONFIG_PINCTRL_MT8127 is not set
# CONFIG_PINCTRL_MT2712 is not set
CONFIG_PINCTRL_MT6765=m
CONFIG_PINCTRL_MT6779=y
CONFIG_PINCTRL_MT6795=y
# CONFIG_PINCTRL_MT6797 is not set
CONFIG_PINCTRL_MT7622=y
# CONFIG_PINCTRL_MT7986 is not set
# CONFIG_PINCTRL_MT8167 is not set
# CONFIG_PINCTRL_MT8173 is not set
# CONFIG_PINCTRL_MT8183 is not set
CONFIG_PINCTRL_MT8186=y
# CONFIG_PINCTRL_MT8188 is not set
CONFIG_PINCTRL_MT8192=y
# CONFIG_PINCTRL_MT8195 is not set
# CONFIG_PINCTRL_MT8365 is not set
CONFIG_PINCTRL_MT8516=y
# CONFIG_PINCTRL_MT6397 is not set
# end of MediaTek pinctrl drivers
CONFIG_PINCTRL_MESON=y
CONFIG_PINCTRL_MESON_GXBB=m
CONFIG_PINCTRL_MESON_GXL=y
CONFIG_PINCTRL_MESON8_PMX=y
# CONFIG_PINCTRL_MESON_AXG is not set
CONFIG_PINCTRL_MESON_AXG_PMX=y
CONFIG_PINCTRL_MESON_G12A=y
CONFIG_PINCTRL_MESON_A1=y
CONFIG_PINCTRL_MESON_S4=y
CONFIG_PINCTRL_WPCM450=y
CONFIG_PINCTRL_NPCM7XX=y
CONFIG_PINCTRL_PXA=y
CONFIG_PINCTRL_PXA25X=m
# CONFIG_PINCTRL_PXA27X is not set
# CONFIG_PINCTRL_MSM is not set
CONFIG_PINCTRL_QCOM_SPMI_PMIC=m
CONFIG_PINCTRL_QCOM_SSBI_PMIC=m
CONFIG_PINCTRL_SC7280_LPASS_LPI=y
CONFIG_PINCTRL_SM8250_LPASS_LPI=y
# CONFIG_PINCTRL_SM8450_LPASS_LPI is not set
CONFIG_PINCTRL_SC8280XP_LPASS_LPI=y
CONFIG_PINCTRL_LPASS_LPI=y
#
# Renesas pinctrl drivers
#
CONFIG_PINCTRL_RENESAS=y
CONFIG_PINCTRL_SH_PFC=y
CONFIG_PINCTRL_SH_PFC_GPIO=y
CONFIG_PINCTRL_SH_FUNC_GPIO=y
# CONFIG_PINCTRL_PFC_EMEV2 is not set
CONFIG_PINCTRL_PFC_R8A77995=y
# CONFIG_PINCTRL_PFC_R8A7794 is not set
CONFIG_PINCTRL_PFC_R8A77990=y
CONFIG_PINCTRL_PFC_R8A7779=y
# CONFIG_PINCTRL_PFC_R8A7790 is not set
CONFIG_PINCTRL_PFC_R8A77950=y
CONFIG_PINCTRL_PFC_R8A77951=y
CONFIG_PINCTRL_PFC_R8A7778=y
CONFIG_PINCTRL_PFC_R8A7793=y
# CONFIG_PINCTRL_PFC_R8A7791 is not set
# CONFIG_PINCTRL_PFC_R8A77965 is not set
CONFIG_PINCTRL_PFC_R8A77960=y
CONFIG_PINCTRL_PFC_R8A77961=y
# CONFIG_PINCTRL_PFC_R8A779F0 is not set
CONFIG_PINCTRL_PFC_R8A7792=y
CONFIG_PINCTRL_PFC_R8A77980=y
CONFIG_PINCTRL_PFC_R8A77970=y
CONFIG_PINCTRL_PFC_R8A779A0=y
# CONFIG_PINCTRL_PFC_R8A779G0 is not set
# CONFIG_PINCTRL_PFC_R8A7740 is not set
CONFIG_PINCTRL_PFC_R8A73A4=y
CONFIG_PINCTRL_RZA1=y
# CONFIG_PINCTRL_RZA2 is not set
CONFIG_PINCTRL_RZG2L=y
# CONFIG_PINCTRL_PFC_R8A77470 is not set
# CONFIG_PINCTRL_PFC_R8A7745 is not set
CONFIG_PINCTRL_PFC_R8A7742=y
# CONFIG_PINCTRL_PFC_R8A7743 is not set
# CONFIG_PINCTRL_PFC_R8A7744 is not set
# CONFIG_PINCTRL_PFC_R8A774C0 is not set
CONFIG_PINCTRL_PFC_R8A774E1=y
CONFIG_PINCTRL_PFC_R8A774A1=y
CONFIG_PINCTRL_PFC_R8A774B1=y
CONFIG_PINCTRL_RZN1=y
CONFIG_PINCTRL_RZV2M=y
# CONFIG_PINCTRL_PFC_SH7203 is not set
CONFIG_PINCTRL_PFC_SH7264=y
# CONFIG_PINCTRL_PFC_SH7269 is not set
# CONFIG_PINCTRL_PFC_SH7720 is not set
# CONFIG_PINCTRL_PFC_SH7722 is not set
CONFIG_PINCTRL_PFC_SH7734=y
CONFIG_PINCTRL_PFC_SH7757=y
# CONFIG_PINCTRL_PFC_SH7785 is not set
# CONFIG_PINCTRL_PFC_SH7786 is not set
CONFIG_PINCTRL_PFC_SH73A0=y
# CONFIG_PINCTRL_PFC_SH7723 is not set
# CONFIG_PINCTRL_PFC_SH7724 is not set
# CONFIG_PINCTRL_PFC_SHX3 is not set
# end of Renesas pinctrl drivers
CONFIG_PINCTRL_SAMSUNG=y
CONFIG_PINCTRL_EXYNOS=y
CONFIG_PINCTRL_EXYNOS_ARM=y
CONFIG_PINCTRL_EXYNOS_ARM64=y
CONFIG_PINCTRL_S3C24XX=y
CONFIG_PINCTRL_S3C64XX=y
# CONFIG_PINCTRL_SPRD_SC9860 is not set
CONFIG_PINCTRL_STARFIVE_JH7100=m
CONFIG_PINCTRL_STM32=y
CONFIG_PINCTRL_STM32F429=y
# CONFIG_PINCTRL_STM32F469 is not set
CONFIG_PINCTRL_STM32F746=y
CONFIG_PINCTRL_STM32F769=y
# CONFIG_PINCTRL_STM32H743 is not set
# CONFIG_PINCTRL_STM32MP135 is not set
# CONFIG_PINCTRL_STM32MP157 is not set
# CONFIG_PINCTRL_TI_IODELAY is not set
# CONFIG_PINCTRL_UNIPHIER is not set
CONFIG_PINCTRL_VISCONTI=y
CONFIG_PINCTRL_TMPV7700=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_FASTPATH_LIMIT=512
CONFIG_OF_GPIO=y
CONFIG_GPIOLIB_IRQCHIP=y
# CONFIG_DEBUG_GPIO is not set
# CONFIG_GPIO_SYSFS is not set
# CONFIG_GPIO_CDEV is not set
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_REGMAP=y
CONFIG_GPIO_MAX730X=m
#
# Memory mapped GPIO drivers
#
CONFIG_GPIO_74XX_MMIO=y
CONFIG_GPIO_ALTERA=y
CONFIG_GPIO_ASPEED=y
# CONFIG_GPIO_ASPEED_SGPIO is not set
# CONFIG_GPIO_ATH79 is not set
# CONFIG_GPIO_RASPBERRYPI_EXP is not set
CONFIG_GPIO_BCM_KONA=y
CONFIG_GPIO_BCM_XGS_IPROC=y
# CONFIG_GPIO_BRCMSTB is not set
CONFIG_GPIO_CADENCE=y
CONFIG_GPIO_CLPS711X=m
# CONFIG_GPIO_DAVINCI is not set
CONFIG_GPIO_DWAPB=m
# CONFIG_GPIO_EIC_SPRD is not set
CONFIG_GPIO_EM=y
CONFIG_GPIO_FTGPIO010=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_GPIO_GRGPIO=m
CONFIG_GPIO_HISI=y
# CONFIG_GPIO_HLWD is not set
CONFIG_GPIO_IMX_SCU=y
# CONFIG_GPIO_IOP is not set
CONFIG_GPIO_LOGICVC=m
CONFIG_GPIO_LPC18XX=m
CONFIG_GPIO_LPC32XX=y
CONFIG_GPIO_MB86S7X=y
CONFIG_GPIO_MENZ127=m
CONFIG_GPIO_MPC8XXX=y
# CONFIG_GPIO_MT7621 is not set
# CONFIG_GPIO_MXC is not set
# CONFIG_GPIO_MXS is not set
# CONFIG_GPIO_PL061 is not set
# CONFIG_GPIO_PMIC_EIC_SPRD is not set
CONFIG_GPIO_PXA=y
CONFIG_GPIO_RCAR=y
CONFIG_GPIO_RDA=y
CONFIG_GPIO_ROCKCHIP=m
# CONFIG_GPIO_SAMA5D2_PIOBU is not set
# CONFIG_GPIO_SIFIVE is not set
CONFIG_GPIO_SIOX=m
# CONFIG_GPIO_SNPS_CREG is not set
CONFIG_GPIO_SPRD=m
# CONFIG_GPIO_STP_XWAY is not set
# CONFIG_GPIO_SYSCON is not set
CONFIG_GPIO_TEGRA=y
CONFIG_GPIO_TEGRA186=y
# CONFIG_GPIO_TS4800 is not set
# CONFIG_GPIO_UNIPHIER is not set
CONFIG_GPIO_VISCONTI=m
CONFIG_GPIO_XGENE=y
CONFIG_GPIO_XGENE_SB=y
CONFIG_GPIO_XILINX=m
CONFIG_GPIO_XLP=m
CONFIG_GPIO_ZYNQ=m
# CONFIG_GPIO_ZYNQMP_MODEPIN is not set
CONFIG_GPIO_AMD_FCH=y
CONFIG_GPIO_IDT3243X=m
# end of Memory mapped GPIO drivers
#
# I2C GPIO expanders
#
# CONFIG_GPIO_ADNP is not set
CONFIG_GPIO_GW_PLD=y
CONFIG_GPIO_MAX7300=m
# CONFIG_GPIO_MAX732X is not set
CONFIG_GPIO_PCA953X=y
# CONFIG_GPIO_PCA953X_IRQ is not set
# CONFIG_GPIO_PCA9570 is not set
CONFIG_GPIO_PCF857X=y
CONFIG_GPIO_TPIC2810=y
CONFIG_GPIO_TS4900=y
# end of I2C GPIO expanders
#
# MFD GPIO expanders
#
CONFIG_GPIO_BD71815=m
CONFIG_GPIO_BD71828=m
# CONFIG_GPIO_BD9571MWV is not set
# CONFIG_GPIO_DA9055 is not set
CONFIG_GPIO_DLN2=m
CONFIG_GPIO_LP3943=m
# CONFIG_GPIO_LP873X is not set
# CONFIG_GPIO_LP87565 is not set
CONFIG_GPIO_MAX77620=y
# CONFIG_GPIO_MAX77650 is not set
# CONFIG_GPIO_RC5T583 is not set
CONFIG_GPIO_SL28CPLD=y
# CONFIG_GPIO_STMPE is not set
CONFIG_GPIO_TPS65086=y
CONFIG_GPIO_TPS65912=m
CONFIG_GPIO_TWL4030=y
CONFIG_GPIO_TWL6040=m
CONFIG_GPIO_WM8350=m
CONFIG_GPIO_WM8994=m
# end of MFD GPIO expanders
#
# USB GPIO expanders
#
CONFIG_GPIO_VIPERBOARD=m
# end of USB GPIO expanders
#
# Virtual GPIO drivers
#
CONFIG_GPIO_AGGREGATOR=y
# CONFIG_GPIO_MOCKUP is not set
# CONFIG_GPIO_VIRTIO is not set
CONFIG_GPIO_SIM=y
# end of Virtual GPIO drivers
CONFIG_W1=m
#
# 1-wire Bus Masters
#
CONFIG_W1_MASTER_DS2490=m
CONFIG_W1_MASTER_DS2482=m
# CONFIG_W1_MASTER_MXC is not set
# CONFIG_W1_MASTER_DS1WM is not set
# CONFIG_W1_MASTER_GPIO is not set
# CONFIG_W1_MASTER_SGI is not set
# end of 1-wire Bus Masters
#
# 1-wire Slaves
#
CONFIG_W1_SLAVE_THERM=m
CONFIG_W1_SLAVE_SMEM=m
CONFIG_W1_SLAVE_DS2405=m
# CONFIG_W1_SLAVE_DS2408 is not set
# CONFIG_W1_SLAVE_DS2413 is not set
# CONFIG_W1_SLAVE_DS2406 is not set
# CONFIG_W1_SLAVE_DS2423 is not set
# CONFIG_W1_SLAVE_DS2805 is not set
CONFIG_W1_SLAVE_DS2430=m
CONFIG_W1_SLAVE_DS2431=m
CONFIG_W1_SLAVE_DS2433=m
CONFIG_W1_SLAVE_DS2433_CRC=y
CONFIG_W1_SLAVE_DS2438=m
CONFIG_W1_SLAVE_DS250X=m
CONFIG_W1_SLAVE_DS2780=m
# CONFIG_W1_SLAVE_DS2781 is not set
# CONFIG_W1_SLAVE_DS28E04 is not set
CONFIG_W1_SLAVE_DS28E17=m
# end of 1-wire Slaves
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_BRCMKONA=y
# CONFIG_POWER_RESET_BRCMSTB is not set
# CONFIG_POWER_RESET_GEMINI_POWEROFF is not set
# CONFIG_POWER_RESET_GPIO is not set
# CONFIG_POWER_RESET_GPIO_RESTART is not set
CONFIG_POWER_RESET_HISI=y
CONFIG_POWER_RESET_OCELOT_RESET=y
# CONFIG_POWER_RESET_LTC2952 is not set
CONFIG_POWER_RESET_MT6323=y
# CONFIG_POWER_RESET_REGULATOR is not set
# CONFIG_POWER_RESET_RESTART is not set
# CONFIG_POWER_RESET_TPS65086 is not set
CONFIG_POWER_RESET_XGENE=y
CONFIG_POWER_RESET_KEYSTONE=y
CONFIG_POWER_RESET_SYSCON=y
# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set
# CONFIG_POWER_RESET_RMOBILE is not set
CONFIG_REBOOT_MODE=m
# CONFIG_SYSCON_REBOOT_MODE is not set
# CONFIG_POWER_RESET_SC27XX is not set
CONFIG_NVMEM_REBOOT_MODE=m
CONFIG_POWER_SUPPLY=y
CONFIG_POWER_SUPPLY_DEBUG=y
# CONFIG_PDA_POWER is not set
CONFIG_GENERIC_ADC_BATTERY=m
CONFIG_IP5XXX_POWER=y
CONFIG_WM8350_POWER=m
CONFIG_TEST_POWER=m
# CONFIG_BATTERY_88PM860X is not set
CONFIG_CHARGER_ADP5061=m
CONFIG_BATTERY_ACT8945A=m
CONFIG_BATTERY_CW2015=y
CONFIG_BATTERY_DS2760=m
CONFIG_BATTERY_DS2780=m
# CONFIG_BATTERY_DS2781 is not set
CONFIG_BATTERY_DS2782=m
CONFIG_BATTERY_LEGO_EV3=y
CONFIG_BATTERY_SAMSUNG_SDI=y
CONFIG_BATTERY_INGENIC=y
# CONFIG_BATTERY_SBS is not set
# CONFIG_CHARGER_SBS is not set
CONFIG_MANAGER_SBS=m
CONFIG_BATTERY_BQ27XXX=m
CONFIG_BATTERY_BQ27XXX_I2C=m
CONFIG_BATTERY_BQ27XXX_HDQ=m
# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set
CONFIG_BATTERY_DA9030=y
# CONFIG_BATTERY_MAX17040 is not set
# CONFIG_BATTERY_MAX17042 is not set
CONFIG_BATTERY_MAX1721X=m
CONFIG_BATTERY_TWL4030_MADC=m
# CONFIG_CHARGER_PCF50633 is not set
CONFIG_BATTERY_RX51=m
CONFIG_CHARGER_ISP1704=m
CONFIG_CHARGER_MAX8903=m
CONFIG_CHARGER_TWL4030=y
# CONFIG_CHARGER_LP8727 is not set
CONFIG_CHARGER_GPIO=y
CONFIG_CHARGER_MANAGER=y
CONFIG_CHARGER_LT3651=m
CONFIG_CHARGER_LTC4162L=y
# CONFIG_CHARGER_MAX14577 is not set
# CONFIG_CHARGER_DETECTOR_MAX14656 is not set
CONFIG_CHARGER_MAX77650=y
CONFIG_CHARGER_MAX77693=m
CONFIG_CHARGER_MAX77976=m
CONFIG_CHARGER_MP2629=m
CONFIG_CHARGER_MT6360=m
# CONFIG_CHARGER_MT6370 is not set
# CONFIG_CHARGER_QCOM_SMBB is not set
CONFIG_CHARGER_BQ2415X=m
CONFIG_CHARGER_BQ24190=y
# CONFIG_CHARGER_BQ24257 is not set
CONFIG_CHARGER_BQ24735=y
# CONFIG_CHARGER_BQ2515X is not set
CONFIG_CHARGER_BQ25890=m
CONFIG_CHARGER_BQ25980=y
CONFIG_CHARGER_BQ256XX=y
CONFIG_CHARGER_SMB347=m
# CONFIG_CHARGER_TPS65090 is not set
# CONFIG_CHARGER_TPS65217 is not set
CONFIG_BATTERY_GAUGE_LTC2941=y
CONFIG_BATTERY_GOLDFISH=y
CONFIG_BATTERY_RT5033=m
CONFIG_CHARGER_RT9455=m
CONFIG_CHARGER_SC2731=m
CONFIG_FUEL_GAUGE_SC27XX=m
CONFIG_CHARGER_UCS1002=m
# CONFIG_CHARGER_BD99954 is not set
CONFIG_BATTERY_UG3105=y
# CONFIG_HWMON is not set
# CONFIG_THERMAL is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=0
# CONFIG_WATCHDOG_SYSFS is not set
CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT=y
#
# Watchdog Pretimeout Governors
#
# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set
#
# Watchdog Device Drivers
#
CONFIG_SOFT_WATCHDOG=y
# CONFIG_DA9052_WATCHDOG is not set
# CONFIG_DA9055_WATCHDOG is not set
CONFIG_DA9063_WATCHDOG=y
CONFIG_DA9062_WATCHDOG=m
# CONFIG_GPIO_WATCHDOG is not set
CONFIG_MENF21BMC_WATCHDOG=m
CONFIG_MENZ069_WATCHDOG=m
CONFIG_WM8350_WATCHDOG=m
CONFIG_XILINX_WATCHDOG=y
CONFIG_ZIIRAVE_WATCHDOG=m
# CONFIG_SL28CPLD_WATCHDOG is not set
# CONFIG_ARM_SP805_WATCHDOG is not set
# CONFIG_ARM_SBSA_WATCHDOG is not set
# CONFIG_ARMADA_37XX_WATCHDOG is not set
CONFIG_ASM9260_WATCHDOG=m
CONFIG_AT91RM9200_WATCHDOG=m
CONFIG_AT91SAM9X_WATCHDOG=y
CONFIG_SAMA5D4_WATCHDOG=y
# CONFIG_CADENCE_WATCHDOG is not set
CONFIG_FTWDT010_WATCHDOG=y
CONFIG_S3C2410_WATCHDOG=m
CONFIG_DW_WATCHDOG=m
CONFIG_EP93XX_WATCHDOG=m
CONFIG_OMAP_WATCHDOG=y
# CONFIG_PNX4008_WATCHDOG is not set
CONFIG_DAVINCI_WATCHDOG=y
# CONFIG_K3_RTI_WATCHDOG is not set
# CONFIG_RN5T618_WATCHDOG is not set
CONFIG_SUNXI_WATCHDOG=m
CONFIG_NPCM7XX_WATCHDOG=y
CONFIG_TWL4030_WATCHDOG=m
CONFIG_STMP3XXX_RTC_WATCHDOG=y
# CONFIG_TS4800_WATCHDOG is not set
CONFIG_TS72XX_WATCHDOG=y
# CONFIG_MAX63XX_WATCHDOG is not set
# CONFIG_MAX77620_WATCHDOG is not set
# CONFIG_IMX2_WDT is not set
CONFIG_IMX_SC_WDT=y
CONFIG_IMX7ULP_WDT=y
CONFIG_RETU_WATCHDOG=m
CONFIG_MOXART_WDT=m
CONFIG_ST_LPC_WATCHDOG=y
# CONFIG_TEGRA_WATCHDOG is not set
CONFIG_QCOM_WDT=m
CONFIG_MESON_GXBB_WATCHDOG=m
# CONFIG_MESON_WATCHDOG is not set
CONFIG_MEDIATEK_WATCHDOG=y
# CONFIG_DIGICOLOR_WATCHDOG is not set
CONFIG_ARM_SMC_WATCHDOG=m
CONFIG_LPC18XX_WATCHDOG=y
CONFIG_RENESAS_WDT=y
CONFIG_RENESAS_RZAWDT=y
CONFIG_RENESAS_RZN1WDT=m
# CONFIG_RENESAS_RZG2LWDT is not set
# CONFIG_ASPEED_WATCHDOG is not set
CONFIG_STPMIC1_WATCHDOG=m
CONFIG_UNIPHIER_WATCHDOG=y
CONFIG_RTD119X_WATCHDOG=y
# CONFIG_REALTEK_OTTO_WDT is not set
CONFIG_SPRD_WATCHDOG=m
# CONFIG_VISCONTI_WATCHDOG is not set
CONFIG_MSC313E_WATCHDOG=m
# CONFIG_APPLE_WATCHDOG is not set
CONFIG_SUNPLUS_WATCHDOG=y
CONFIG_SC520_WDT=y
CONFIG_BCM47XX_WDT=m
CONFIG_BCM2835_WDT=m
CONFIG_BCM_KONA_WDT=m
# CONFIG_BCM_KONA_WDT_DEBUG is not set
CONFIG_BCM7038_WDT=m
CONFIG_IMGPDC_WDT=y
# CONFIG_MPC5200_WDT is not set
CONFIG_MEN_A21_WDT=y
CONFIG_XEN_WDT=y
CONFIG_UML_WATCHDOG=y
#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
CONFIG_KEEMBAY_WATCHDOG=m
CONFIG_SSB_POSSIBLE=y
CONFIG_SSB=y
CONFIG_SSB_SPROM=y
CONFIG_SSB_SDIOHOST_POSSIBLE=y
CONFIG_SSB_SDIOHOST=y
CONFIG_SSB_HOST_SOC=y
# CONFIG_SSB_DRIVER_GPIO is not set
CONFIG_BCMA_POSSIBLE=y
CONFIG_BCMA=m
CONFIG_BCMA_HOST_SOC=y
CONFIG_BCMA_DRIVER_MIPS=y
CONFIG_BCMA_PFLASH=y
CONFIG_BCMA_SFLASH=y
CONFIG_BCMA_NFLASH=y
# CONFIG_BCMA_DRIVER_GMAC_CMN is not set
CONFIG_BCMA_DRIVER_GPIO=y
# CONFIG_BCMA_DEBUG is not set
#
# Multifunction device drivers
#
CONFIG_MFD_CORE=y
CONFIG_MFD_ALTERA_SYSMGR=y
CONFIG_MFD_ACT8945A=y
# CONFIG_MFD_SUN4I_GPADC is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_MFD_AS3722 is not set
# CONFIG_PMIC_ADP5520 is not set
CONFIG_MFD_AAT2870_CORE=y
CONFIG_MFD_AT91_USART=m
CONFIG_MFD_ATMEL_FLEXCOM=y
CONFIG_MFD_ATMEL_HLCDC=y
CONFIG_MFD_ATMEL_SMC=y
# CONFIG_MFD_BCM590XX is not set
CONFIG_MFD_BD9571MWV=m
# CONFIG_MFD_AXP20X_I2C is not set
# CONFIG_MFD_MADERA is not set
CONFIG_MFD_ASIC3=y
CONFIG_PMIC_DA903X=y
# CONFIG_MFD_DA9052_I2C is not set
CONFIG_MFD_DA9055=y
CONFIG_MFD_DA9062=y
CONFIG_MFD_DA9063=m
# CONFIG_MFD_DA9150 is not set
CONFIG_MFD_DLN2=m
# CONFIG_MFD_ENE_KB3930 is not set
CONFIG_MFD_EXYNOS_LPASS=m
CONFIG_MFD_GATEWORKS_GSC=m
CONFIG_MFD_MC13XXX=m
CONFIG_MFD_MC13XXX_I2C=m
CONFIG_MFD_MP2629=y
CONFIG_MFD_MXS_LRADC=y
CONFIG_MFD_MX25_TSADC=y
CONFIG_MFD_HI6421_PMIC=y
# CONFIG_MFD_HI6421_SPMI is not set
CONFIG_MFD_HI655X_PMIC=m
CONFIG_HTC_PASIC3=m
# CONFIG_HTC_I2CPLD is not set
CONFIG_MFD_IQS62X=m
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
CONFIG_MFD_88PM860X=y
CONFIG_MFD_MAX14577=y
CONFIG_MFD_MAX77620=y
CONFIG_MFD_MAX77650=y
CONFIG_MFD_MAX77686=m
CONFIG_MFD_MAX77693=y
CONFIG_MFD_MAX77714=m
CONFIG_MFD_MAX77843=y
CONFIG_MFD_MAX8907=m
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
CONFIG_MFD_MT6360=m
CONFIG_MFD_MT6370=m
CONFIG_MFD_MT6397=y
CONFIG_MFD_MENF21BMC=y
CONFIG_MFD_VIPERBOARD=y
# CONFIG_MFD_NTXEC is not set
CONFIG_MFD_RETU=m
CONFIG_MFD_PCF50633=y
# CONFIG_PCF50633_ADC is not set
CONFIG_PCF50633_GPIO=m
# CONFIG_MFD_PM8XXX is not set
# CONFIG_MFD_SPMI_PMIC is not set
CONFIG_MFD_SY7636A=y
CONFIG_MFD_RT4831=m
CONFIG_MFD_RT5033=m
# CONFIG_MFD_RT5120 is not set
CONFIG_MFD_RC5T583=y
# CONFIG_MFD_RK808 is not set
# CONFIG_MFD_RN5T618 is not set
CONFIG_MFD_SEC_CORE=y
CONFIG_MFD_SI476X_CORE=m
CONFIG_MFD_SIMPLE_MFD_I2C=y
CONFIG_MFD_SL28CPLD=m
CONFIG_MFD_SM501=y
# CONFIG_MFD_SM501_GPIO is not set
CONFIG_MFD_SKY81452=m
CONFIG_ABX500_CORE=y
CONFIG_MFD_STMPE=y
#
# STMicroelectronics STMPE Interface Drivers
#
# CONFIG_STMPE_I2C is not set
# end of STMicroelectronics STMPE Interface Drivers
CONFIG_MFD_SUN6I_PRCM=y
CONFIG_MFD_SYSCON=y
CONFIG_MFD_TI_AM335X_TSCADC=y
CONFIG_MFD_LP3943=m
# CONFIG_MFD_LP8788 is not set
CONFIG_MFD_TI_LMU=m
# CONFIG_MFD_OMAP_USB_HOST is not set
# CONFIG_MFD_PALMAS is not set
CONFIG_TPS6105X=y
CONFIG_TPS65010=y
CONFIG_TPS6507X=y
CONFIG_MFD_TPS65086=y
CONFIG_MFD_TPS65090=y
CONFIG_MFD_TPS65217=m
CONFIG_MFD_TI_LP873X=m
CONFIG_MFD_TI_LP87565=y
# CONFIG_MFD_TPS65218 is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
CONFIG_MFD_TPS65912=m
CONFIG_MFD_TPS65912_I2C=m
CONFIG_TWL4030_CORE=y
CONFIG_MFD_TWL4030_AUDIO=y
CONFIG_TWL6040_CORE=y
CONFIG_MFD_WL1273_CORE=y
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TC3589X is not set
CONFIG_MFD_TQMX86=m
CONFIG_MFD_LOCHNAGAR=y
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
CONFIG_MFD_WM8350=y
CONFIG_MFD_WM8350_I2C=y
CONFIG_MFD_WM8994=y
CONFIG_MFD_STW481X=m
CONFIG_MFD_ROHM_BD718XX=y
CONFIG_MFD_ROHM_BD71828=m
# CONFIG_MFD_ROHM_BD957XMUF is not set
CONFIG_MFD_STM32_LPTIMER=y
CONFIG_MFD_STM32_TIMERS=m
CONFIG_MFD_STPMIC1=m
# CONFIG_MFD_STMFX is not set
# CONFIG_MFD_WCD934X is not set
# CONFIG_MFD_ATC260X_I2C is not set
# CONFIG_MFD_KHADAS_MCU is not set
# CONFIG_MFD_ACER_A500_EC is not set
CONFIG_MFD_QCOM_PM8008=y
# CONFIG_MFD_RSMU_I2C is not set
# end of Multifunction device drivers
CONFIG_REGULATOR=y
CONFIG_REGULATOR_DEBUG=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
CONFIG_REGULATOR_88PG86X=y
# CONFIG_REGULATOR_88PM8607 is not set
CONFIG_REGULATOR_ACT8865=y
# CONFIG_REGULATOR_ACT8945A is not set
CONFIG_REGULATOR_AD5398=m
CONFIG_REGULATOR_ANATOP=y
CONFIG_REGULATOR_AAT2870=m
CONFIG_REGULATOR_ARM_SCMI=m
CONFIG_REGULATOR_BD71815=m
# CONFIG_REGULATOR_BD71828 is not set
CONFIG_REGULATOR_BD718XX=m
CONFIG_REGULATOR_BD9571MWV=m
CONFIG_REGULATOR_DA903X=m
# CONFIG_REGULATOR_DA9055 is not set
CONFIG_REGULATOR_DA9062=y
CONFIG_REGULATOR_DA9063=m
CONFIG_REGULATOR_DA9121=m
CONFIG_REGULATOR_DA9210=y
CONFIG_REGULATOR_DA9211=y
# CONFIG_REGULATOR_FAN53555 is not set
CONFIG_REGULATOR_FAN53880=m
# CONFIG_REGULATOR_GPIO is not set
CONFIG_REGULATOR_HI6421=y
CONFIG_REGULATOR_HI6421V530=y
CONFIG_REGULATOR_HI655X=m
# CONFIG_REGULATOR_ISL9305 is not set
CONFIG_REGULATOR_ISL6271A=y
CONFIG_REGULATOR_LM363X=m
CONFIG_REGULATOR_LOCHNAGAR=y
CONFIG_REGULATOR_LP3971=y
CONFIG_REGULATOR_LP3972=m
# CONFIG_REGULATOR_LP872X is not set
# CONFIG_REGULATOR_LP873X is not set
CONFIG_REGULATOR_LP8755=m
CONFIG_REGULATOR_LP87565=m
# CONFIG_REGULATOR_LTC3589 is not set
CONFIG_REGULATOR_LTC3676=y
CONFIG_REGULATOR_MAX14577=y
CONFIG_REGULATOR_MAX1586=y
CONFIG_REGULATOR_MAX77620=y
CONFIG_REGULATOR_MAX77650=y
CONFIG_REGULATOR_MAX8649=m
CONFIG_REGULATOR_MAX8660=m
# CONFIG_REGULATOR_MAX8893 is not set
CONFIG_REGULATOR_MAX8907=m
CONFIG_REGULATOR_MAX8952=m
CONFIG_REGULATOR_MAX20086=y
CONFIG_REGULATOR_MAX77686=y
CONFIG_REGULATOR_MAX77693=y
# CONFIG_REGULATOR_MAX77802 is not set
CONFIG_REGULATOR_MAX77826=m
CONFIG_REGULATOR_MC13XXX_CORE=m
CONFIG_REGULATOR_MC13783=m
CONFIG_REGULATOR_MC13892=m
CONFIG_REGULATOR_MCP16502=m
# CONFIG_REGULATOR_MP5416 is not set
CONFIG_REGULATOR_MP8859=m
# CONFIG_REGULATOR_MP886X is not set
CONFIG_REGULATOR_MPQ7920=y
# CONFIG_REGULATOR_MT6311 is not set
CONFIG_REGULATOR_MT6315=m
# CONFIG_REGULATOR_MT6323 is not set
CONFIG_REGULATOR_MT6331=m
CONFIG_REGULATOR_MT6332=y
CONFIG_REGULATOR_MT6358=m
CONFIG_REGULATOR_MT6359=y
CONFIG_REGULATOR_MT6360=m
CONFIG_REGULATOR_MT6370=m
# CONFIG_REGULATOR_MT6380 is not set
CONFIG_REGULATOR_MT6397=y
CONFIG_REGULATOR_PBIAS=m
CONFIG_REGULATOR_PCA9450=m
CONFIG_REGULATOR_PCF50633=m
CONFIG_REGULATOR_PF8X00=y
CONFIG_REGULATOR_PFUZE100=m
CONFIG_REGULATOR_PV88060=y
# CONFIG_REGULATOR_PV88080 is not set
CONFIG_REGULATOR_PV88090=y
# CONFIG_REGULATOR_PWM is not set
CONFIG_REGULATOR_QCOM_RPMH=m
# CONFIG_REGULATOR_QCOM_SMD_RPM is not set
CONFIG_REGULATOR_QCOM_SPMI=m
CONFIG_REGULATOR_QCOM_USB_VBUS=m
CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
# CONFIG_REGULATOR_RC5T583 is not set
CONFIG_REGULATOR_ROHM=m
CONFIG_REGULATOR_RT4801=y
CONFIG_REGULATOR_RT4831=m
# CONFIG_REGULATOR_RT5033 is not set
CONFIG_REGULATOR_RT5190A=y
# CONFIG_REGULATOR_RT5759 is not set
# CONFIG_REGULATOR_RT6160 is not set
CONFIG_REGULATOR_RT6245=y
CONFIG_REGULATOR_RTQ2134=y
CONFIG_REGULATOR_RTMV20=m
CONFIG_REGULATOR_RTQ6752=y
CONFIG_REGULATOR_S2MPA01=y
CONFIG_REGULATOR_S2MPS11=y
CONFIG_REGULATOR_S5M8767=y
CONFIG_REGULATOR_SC2731=y
CONFIG_REGULATOR_SKY81452=m
# CONFIG_REGULATOR_SLG51000 is not set
# CONFIG_REGULATOR_STM32_BOOSTER is not set
CONFIG_REGULATOR_STM32_VREFBUF=y
CONFIG_REGULATOR_STM32_PWR=y
# CONFIG_REGULATOR_STPMIC1 is not set
# CONFIG_REGULATOR_TI_ABB is not set
# CONFIG_REGULATOR_STW481X_VMMC is not set
CONFIG_REGULATOR_SY7636A=m
CONFIG_REGULATOR_SY8106A=m
CONFIG_REGULATOR_SY8824X=y
CONFIG_REGULATOR_SY8827N=m
# CONFIG_REGULATOR_TPS51632 is not set
CONFIG_REGULATOR_TPS6105X=m
# CONFIG_REGULATOR_TPS62360 is not set
CONFIG_REGULATOR_TPS6286X=y
# CONFIG_REGULATOR_TPS65023 is not set
CONFIG_REGULATOR_TPS6507X=m
CONFIG_REGULATOR_TPS65086=y
# CONFIG_REGULATOR_TPS65090 is not set
CONFIG_REGULATOR_TPS65132=y
CONFIG_REGULATOR_TPS65217=m
CONFIG_REGULATOR_TPS65912=m
CONFIG_REGULATOR_TPS68470=y
CONFIG_REGULATOR_TWL4030=y
CONFIG_REGULATOR_UNIPHIER=m
# CONFIG_REGULATOR_VCTRL is not set
CONFIG_REGULATOR_WM8350=m
CONFIG_REGULATOR_WM8994=y
CONFIG_REGULATOR_QCOM_LABIBB=m
# CONFIG_RC_CORE is not set
CONFIG_CEC_CORE=m
CONFIG_CEC_NOTIFIER=y
#
# CEC support
#
# CONFIG_MEDIA_CEC_SUPPORT is not set
# end of CEC support
CONFIG_MEDIA_SUPPORT=m
# CONFIG_MEDIA_SUPPORT_FILTER is not set
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
#
# Media device types
#
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
CONFIG_MEDIA_RADIO_SUPPORT=y
CONFIG_MEDIA_SDR_SUPPORT=y
CONFIG_MEDIA_PLATFORM_SUPPORT=y
CONFIG_MEDIA_TEST_SUPPORT=y
# end of Media device types
#
# Media core support
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_MEDIA_CONTROLLER is not set
CONFIG_DVB_CORE=m
# end of Media core support
#
# Digital TV options
#
CONFIG_DVB_MAX_ADAPTERS=16
CONFIG_DVB_DYNAMIC_MINORS=y
CONFIG_DVB_DEMUX_SECTION_LOSS_LOG=y
# CONFIG_DVB_ULE_DEBUG is not set
# end of Digital TV options
#
# Media drivers
#
#
# Media drivers
#
# CONFIG_MEDIA_USB_SUPPORT is not set
CONFIG_MEDIA_PLATFORM_DRIVERS=y
# CONFIG_V4L_PLATFORM_DRIVERS is not set
# CONFIG_SDR_PLATFORM_DRIVERS is not set
# CONFIG_DVB_PLATFORM_DRIVERS is not set
#
# Allegro DVT media platform drivers
#
#
# Amlogic media platform drivers
#
#
# Amphion drivers
#
#
# Aspeed media platform drivers
#
#
# Atmel media platform drivers
#
#
# Cadence media platform drivers
#
#
# Chips&Media media platform drivers
#
#
# Intel media platform drivers
#
#
# Marvell media platform drivers
#
#
# Mediatek media platform drivers
#
#
# NVidia media platform drivers
#
#
# NXP media platform drivers
#
#
# Qualcomm media platform drivers
#
#
# Renesas media platform drivers
#
#
# Rockchip media platform drivers
#
#
# Samsung media platform drivers
#
#
# STMicroelectronics media platform drivers
#
#
# Sunxi media platform drivers
#
#
# Texas Instruments drivers
#
#
# Verisilicon media platform drivers
#
#
# VIA media platform drivers
#
#
# Xilinx media platform drivers
#
#
# MMC/SDIO DVB adapters
#
# CONFIG_SMS_SDIO_DRV is not set
CONFIG_DVB_TEST_DRIVERS=y
CONFIG_DVB_VIDTV=m
#
# FireWire (IEEE 1394) Adapters
#
CONFIG_DVB_FIREDTV=m
CONFIG_DVB_FIREDTV_INPUT=y
# end of Media drivers
#
# Media ancillary drivers
#
CONFIG_MEDIA_ATTACH=y
CONFIG_MEDIA_TUNER=m
#
# Customize TV tuners
#
CONFIG_MEDIA_TUNER_FC0011=m
CONFIG_MEDIA_TUNER_FC0012=m
# CONFIG_MEDIA_TUNER_FC0013 is not set
CONFIG_MEDIA_TUNER_IT913X=m
# CONFIG_MEDIA_TUNER_M88RS6000T is not set
CONFIG_MEDIA_TUNER_MAX2165=m
CONFIG_MEDIA_TUNER_MC44S803=m
# CONFIG_MEDIA_TUNER_MT2060 is not set
CONFIG_MEDIA_TUNER_MT2063=m
# CONFIG_MEDIA_TUNER_MT20XX is not set
CONFIG_MEDIA_TUNER_MT2131=m
CONFIG_MEDIA_TUNER_MT2266=m
CONFIG_MEDIA_TUNER_MXL301RF=m
CONFIG_MEDIA_TUNER_MXL5005S=m
CONFIG_MEDIA_TUNER_MXL5007T=m
CONFIG_MEDIA_TUNER_QM1D1B0004=m
CONFIG_MEDIA_TUNER_QM1D1C0042=m
CONFIG_MEDIA_TUNER_QT1010=m
CONFIG_MEDIA_TUNER_R820T=m
CONFIG_MEDIA_TUNER_SI2157=m
CONFIG_MEDIA_TUNER_SIMPLE=m
CONFIG_MEDIA_TUNER_TDA18212=m
# CONFIG_MEDIA_TUNER_TDA18218 is not set
CONFIG_MEDIA_TUNER_TDA18250=m
CONFIG_MEDIA_TUNER_TDA18271=m
CONFIG_MEDIA_TUNER_TDA827X=m
CONFIG_MEDIA_TUNER_TDA8290=m
CONFIG_MEDIA_TUNER_TDA9887=m
# CONFIG_MEDIA_TUNER_TEA5761 is not set
CONFIG_MEDIA_TUNER_TEA5767=m
CONFIG_MEDIA_TUNER_TUA9001=m
CONFIG_MEDIA_TUNER_XC2028=m
CONFIG_MEDIA_TUNER_XC4000=m
CONFIG_MEDIA_TUNER_XC5000=m
# end of Customize TV tuners
#
# Customise DVB Frontends
#
#
# Multistandard (satellite) frontends
#
CONFIG_DVB_M88DS3103=m
CONFIG_DVB_MXL5XX=m
CONFIG_DVB_STB0899=m
# CONFIG_DVB_STB6100 is not set
CONFIG_DVB_STV090x=m
CONFIG_DVB_STV0910=m
# CONFIG_DVB_STV6110x is not set
CONFIG_DVB_STV6111=m
#
# Multistandard (cable + terrestrial) frontends
#
CONFIG_DVB_DRXK=m
# CONFIG_DVB_MN88472 is not set
# CONFIG_DVB_MN88473 is not set
CONFIG_DVB_SI2165=m
CONFIG_DVB_TDA18271C2DD=m
#
# DVB-S (satellite) frontends
#
# CONFIG_DVB_CX24110 is not set
# CONFIG_DVB_CX24116 is not set
CONFIG_DVB_CX24117=m
CONFIG_DVB_CX24120=m
# CONFIG_DVB_CX24123 is not set
CONFIG_DVB_DS3000=m
CONFIG_DVB_MB86A16=m
CONFIG_DVB_MT312=m
CONFIG_DVB_S5H1420=m
# CONFIG_DVB_SI21XX is not set
# CONFIG_DVB_STB6000 is not set
CONFIG_DVB_STV0288=m
CONFIG_DVB_STV0299=m
# CONFIG_DVB_STV0900 is not set
CONFIG_DVB_STV6110=m
CONFIG_DVB_TDA10071=m
# CONFIG_DVB_TDA10086 is not set
CONFIG_DVB_TDA8083=m
CONFIG_DVB_TDA8261=m
# CONFIG_DVB_TDA826X is not set
CONFIG_DVB_TS2020=m
CONFIG_DVB_TUA6100=m
CONFIG_DVB_TUNER_CX24113=m
# CONFIG_DVB_TUNER_ITD1000 is not set
CONFIG_DVB_VES1X93=m
# CONFIG_DVB_ZL10036 is not set
CONFIG_DVB_ZL10039=m
#
# DVB-T (terrestrial) frontends
#
CONFIG_DVB_AF9013=m
# CONFIG_DVB_CX22700 is not set
CONFIG_DVB_CX22702=m
CONFIG_DVB_CXD2820R=m
# CONFIG_DVB_CXD2841ER is not set
CONFIG_DVB_DIB3000MB=m
CONFIG_DVB_DIB3000MC=m
CONFIG_DVB_DIB7000M=m
CONFIG_DVB_DIB7000P=m
CONFIG_DVB_DIB9000=m
CONFIG_DVB_DRXD=m
CONFIG_DVB_EC100=m
CONFIG_DVB_L64781=m
# CONFIG_DVB_MT352 is not set
CONFIG_DVB_NXT6000=m
# CONFIG_DVB_RTL2830 is not set
CONFIG_DVB_RTL2832=m
CONFIG_DVB_S5H1432=m
CONFIG_DVB_SI2168=m
# CONFIG_DVB_SP887X is not set
CONFIG_DVB_STV0367=m
CONFIG_DVB_TDA10048=m
CONFIG_DVB_TDA1004X=m
# CONFIG_DVB_ZD1301_DEMOD is not set
CONFIG_DVB_ZL10353=m
#
# DVB-C (cable) frontends
#
CONFIG_DVB_STV0297=m
# CONFIG_DVB_TDA10021 is not set
CONFIG_DVB_TDA10023=m
# CONFIG_DVB_VES1820 is not set
#
# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
#
CONFIG_DVB_AU8522=m
CONFIG_DVB_AU8522_DTV=m
CONFIG_DVB_BCM3510=m
# CONFIG_DVB_LG2160 is not set
CONFIG_DVB_LGDT3305=m
CONFIG_DVB_LGDT3306A=m
# CONFIG_DVB_LGDT330X is not set
CONFIG_DVB_MXL692=m
# CONFIG_DVB_NXT200X is not set
CONFIG_DVB_OR51132=m
CONFIG_DVB_OR51211=m
CONFIG_DVB_S5H1409=m
# CONFIG_DVB_S5H1411 is not set
#
# ISDB-T (terrestrial) frontends
#
CONFIG_DVB_DIB8000=m
CONFIG_DVB_MB86A20S=m
CONFIG_DVB_S921=m
#
# ISDB-S (satellite) & ISDB-T (terrestrial) frontends
#
CONFIG_DVB_MN88443X=m
# CONFIG_DVB_TC90522 is not set
#
# Digital terrestrial only tuners/PLL
#
# CONFIG_DVB_PLL is not set
# CONFIG_DVB_TUNER_DIB0070 is not set
# CONFIG_DVB_TUNER_DIB0090 is not set
#
# SEC control devices for DVB-S
#
# CONFIG_DVB_A8293 is not set
CONFIG_DVB_AF9033=m
CONFIG_DVB_ASCOT2E=m
# CONFIG_DVB_ATBM8830 is not set
CONFIG_DVB_HELENE=m
CONFIG_DVB_HORUS3A=m
CONFIG_DVB_ISL6405=m
CONFIG_DVB_ISL6421=m
CONFIG_DVB_ISL6423=m
# CONFIG_DVB_IX2505V is not set
CONFIG_DVB_LGS8GL5=m
# CONFIG_DVB_LGS8GXX is not set
CONFIG_DVB_LNBH25=m
CONFIG_DVB_LNBH29=m
CONFIG_DVB_LNBP21=m
# CONFIG_DVB_LNBP22 is not set
CONFIG_DVB_M88RS2000=m
# CONFIG_DVB_TDA665x is not set
CONFIG_DVB_DRX39XYJ=m
#
# Common Interface (EN50221) controller drivers
#
# CONFIG_DVB_CXD2099 is not set
# CONFIG_DVB_SP2 is not set
# end of Customise DVB Frontends
#
# Tools to develop new frontends
#
# CONFIG_DVB_DUMMY_FE is not set
# end of Media ancillary drivers
#
# Graphics support
#
CONFIG_APERTURE_HELPERS=y
# CONFIG_IMX_IPUV3_CORE is not set
CONFIG_DRM=m
CONFIG_DRM_MIPI_DSI=y
# CONFIG_DRM_KUNIT_TEST is not set
CONFIG_DRM_KMS_HELPER=m
CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS=y
# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
CONFIG_DRM_DP_AUX_BUS=m
CONFIG_DRM_DISPLAY_HELPER=m
CONFIG_DRM_DISPLAY_DP_HELPER=y
CONFIG_DRM_DISPLAY_HDCP_HELPER=y
CONFIG_DRM_DISPLAY_HDMI_HELPER=y
# CONFIG_DRM_DP_AUX_CHARDEV is not set
CONFIG_DRM_DP_CEC=y
CONFIG_DRM_GEM_DMA_HELPER=m
CONFIG_DRM_GEM_SHMEM_HELPER=m
CONFIG_DRM_SCHED=m
#
# I2C encoder or helper chips
#
CONFIG_DRM_I2C_CH7006=m
# CONFIG_DRM_I2C_SIL164 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
CONFIG_DRM_I2C_NXP_TDA9950=m
# end of I2C encoder or helper chips
#
# ARM devices
#
# CONFIG_DRM_HDLCD is not set
CONFIG_DRM_MALI_DISPLAY=m
CONFIG_DRM_KOMEDA=m
# end of ARM devices
# CONFIG_DRM_KMB_DISPLAY is not set
CONFIG_DRM_VGEM=m
# CONFIG_DRM_VKMS is not set
# CONFIG_DRM_EXYNOS is not set
CONFIG_DRM_ROCKCHIP=m
# CONFIG_ROCKCHIP_VOP is not set
CONFIG_ROCKCHIP_VOP2=y
# CONFIG_ROCKCHIP_CDN_DP is not set
# CONFIG_ROCKCHIP_DW_HDMI is not set
CONFIG_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_ROCKCHIP_INNO_HDMI=y
# CONFIG_ROCKCHIP_LVDS is not set
CONFIG_ROCKCHIP_RGB=y
CONFIG_ROCKCHIP_RK3066_HDMI=y
# CONFIG_DRM_UDL is not set
# CONFIG_DRM_RCAR_DU is not set
CONFIG_DRM_RCAR_DW_HDMI=m
# CONFIG_DRM_RCAR_USE_LVDS is not set
CONFIG_DRM_RCAR_MIPI_DSI=m
CONFIG_DRM_SUN4I=m
# CONFIG_DRM_SUN4I_HDMI is not set
# CONFIG_DRM_SUN4I_BACKEND is not set
CONFIG_DRM_SUN6I_DSI=m
CONFIG_DRM_SUN8I_DW_HDMI=m
CONFIG_DRM_SUN8I_MIXER=m
CONFIG_DRM_SUN8I_TCON_TOP=m
CONFIG_DRM_VIRTIO_GPU=m
CONFIG_DRM_MSM=m
CONFIG_DRM_MSM_GPU_STATE=y
# CONFIG_DRM_MSM_GPU_SUDO is not set
CONFIG_DRM_MSM_MDSS=y
# CONFIG_DRM_MSM_MDP4 is not set
CONFIG_DRM_MSM_MDP5=y
CONFIG_DRM_MSM_DPU=y
CONFIG_DRM_MSM_DP=y
# CONFIG_DRM_MSM_DSI is not set
CONFIG_DRM_MSM_HDMI=y
CONFIG_DRM_MSM_HDMI_HDCP=y
CONFIG_DRM_PANEL=y
#
# Display Panels
#
CONFIG_DRM_PANEL_ARM_VERSATILE=m
CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m
# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set
# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set
CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
CONFIG_DRM_PANEL_DSI_CM=m
# CONFIG_DRM_PANEL_LVDS is not set
# CONFIG_DRM_PANEL_SIMPLE is not set
# CONFIG_DRM_PANEL_EDP is not set
CONFIG_DRM_PANEL_EBBG_FT8719=m
CONFIG_DRM_PANEL_ELIDA_KD35T133=m
# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set
# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set
CONFIG_DRM_PANEL_ILITEK_ILI9881C=m
# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
CONFIG_DRM_PANEL_JDI_R63452=m
CONFIG_DRM_PANEL_KHADAS_TS050=m
# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set
CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m
# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set
CONFIG_DRM_PANEL_NOVATEK_NT35510=m
# CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set
CONFIG_DRM_PANEL_NOVATEK_NT35950=m
CONFIG_DRM_PANEL_NOVATEK_NT36672A=m
CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m
CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m
CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m
# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set
CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m
CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
CONFIG_DRM_PANEL_RONBO_RB070D30=m
CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set
CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=m
CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m
# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set
CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m
CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m
CONFIG_DRM_PANEL_SITRONIX_ST7701=m
CONFIG_DRM_PANEL_SITRONIX_ST7703=m
# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set
CONFIG_DRM_PANEL_TDO_TL070WSH30=m
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
CONFIG_DRM_PANEL_VISIONOX_RM69299=m
CONFIG_DRM_PANEL_XINPENG_XPP055C272=m
# end of Display Panels
CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y
#
# Display Interface Bridges
#
CONFIG_DRM_CDNS_DSI=m
# CONFIG_DRM_CHIPONE_ICN6211 is not set
CONFIG_DRM_CHRONTEL_CH7033=m
CONFIG_DRM_CROS_EC_ANX7688=m
# CONFIG_DRM_DISPLAY_CONNECTOR is not set
CONFIG_DRM_FSL_LDB=m
CONFIG_DRM_ITE_IT6505=m
CONFIG_DRM_LONTIUM_LT8912B=m
CONFIG_DRM_LONTIUM_LT9211=m
CONFIG_DRM_LONTIUM_LT9611=m
# CONFIG_DRM_LONTIUM_LT9611UXC is not set
CONFIG_DRM_ITE_IT66121=m
CONFIG_DRM_LVDS_CODEC=m
CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW=m
CONFIG_DRM_NWL_MIPI_DSI=m
CONFIG_DRM_NXP_PTN3460=m
# CONFIG_DRM_PARADE_PS8622 is not set
CONFIG_DRM_PARADE_PS8640=m
# CONFIG_DRM_SIL_SII8620 is not set
# CONFIG_DRM_SII902X is not set
CONFIG_DRM_SII9234=m
# CONFIG_DRM_SIMPLE_BRIDGE is not set
CONFIG_DRM_THINE_THC63LVD1024=m
# CONFIG_DRM_TOSHIBA_TC358762 is not set
CONFIG_DRM_TOSHIBA_TC358764=m
CONFIG_DRM_TOSHIBA_TC358767=m
CONFIG_DRM_TOSHIBA_TC358768=m
CONFIG_DRM_TOSHIBA_TC358775=m
# CONFIG_DRM_TI_DLPC3433 is not set
CONFIG_DRM_TI_TFP410=m
CONFIG_DRM_TI_SN65DSI83=m
CONFIG_DRM_TI_SN65DSI86=m
CONFIG_DRM_TI_TPD12S015=m
CONFIG_DRM_ANALOGIX_ANX6345=m
CONFIG_DRM_ANALOGIX_ANX78XX=m
CONFIG_DRM_ANALOGIX_DP=m
CONFIG_DRM_ANALOGIX_ANX7625=m
CONFIG_DRM_I2C_ADV7511=m
CONFIG_DRM_I2C_ADV7511_CEC=y
CONFIG_DRM_CDNS_MHDP8546=m
# CONFIG_DRM_CDNS_MHDP8546_J721E is not set
CONFIG_DRM_IMX8QM_LDB=m
CONFIG_DRM_IMX8QXP_LDB=m
CONFIG_DRM_IMX8QXP_PIXEL_COMBINER=m
CONFIG_DRM_IMX8QXP_PIXEL_LINK=m
# CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI is not set
CONFIG_DRM_DW_HDMI=m
CONFIG_DRM_DW_HDMI_CEC=m
CONFIG_DRM_DW_MIPI_DSI=m
# end of Display Interface Bridges
CONFIG_DRM_INGENIC=m
# CONFIG_DRM_INGENIC_IPU is not set
# CONFIG_DRM_V3D is not set
CONFIG_DRM_ETNAVIV=m
# CONFIG_DRM_ETNAVIV_THERMAL is not set
CONFIG_DRM_HISI_KIRIN=m
CONFIG_DRM_LOGICVC=m
CONFIG_DRM_MXS=y
CONFIG_DRM_MXSFB=m
CONFIG_DRM_IMX_LCDIF=m
# CONFIG_DRM_MESON is not set
CONFIG_DRM_ARCPGU=m
# CONFIG_DRM_GM12U320 is not set
CONFIG_DRM_SIMPLEDRM=m
# CONFIG_DRM_PL111 is not set
CONFIG_DRM_TVE200=m
# CONFIG_DRM_XEN_FRONTEND is not set
CONFIG_DRM_LIMA=m
CONFIG_DRM_PANFROST=m
CONFIG_DRM_ASPEED_GFX=m
CONFIG_DRM_MCDE=m
# CONFIG_DRM_TIDSS is not set
CONFIG_DRM_GUD=m
CONFIG_DRM_SSD130X=m
# CONFIG_DRM_SSD130X_I2C is not set
CONFIG_DRM_SPRD=m
# CONFIG_DRM_LEGACY is not set
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=m
CONFIG_DRM_NOMODESET=y
#
# Frame buffer Devices
#
CONFIG_FB_CMDLINE=y
CONFIG_FB_NOTIFY=y
CONFIG_FB=m
# CONFIG_FIRMWARE_EDID is not set
CONFIG_FB_CFB_FILLRECT=m
CONFIG_FB_CFB_COPYAREA=m
CONFIG_FB_CFB_IMAGEBLIT=m
CONFIG_FB_CFB_REV_PIXELS_IN_BYTE=y
CONFIG_FB_SYS_FILLRECT=m
CONFIG_FB_SYS_COPYAREA=m
CONFIG_FB_SYS_IMAGEBLIT=m
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=m
CONFIG_FB_DEFERRED_IO=y
CONFIG_FB_BACKLIGHT=m
CONFIG_FB_MODE_HELPERS=y
# CONFIG_FB_TILEBLITTING is not set
#
# Frame buffer hardware drivers
#
CONFIG_FB_ARMCLCD=m
# CONFIG_FB_CLPS711X is not set
CONFIG_FB_IMX=m
CONFIG_FB_ARC=m
# CONFIG_FB_PVR2 is not set
# CONFIG_FB_OPENCORES is not set
CONFIG_FB_S1D13XXX=m
CONFIG_FB_ATMEL=m
# CONFIG_FB_PXA168 is not set
# CONFIG_FB_W100 is not set
# CONFIG_FB_SH_MOBILE_LCDC is not set
CONFIG_FB_TMIO=m
CONFIG_FB_TMIO_ACCELL=y
# CONFIG_FB_S3C is not set
# CONFIG_FB_SM501 is not set
CONFIG_FB_SMSCUFX=m
CONFIG_FB_UDL=m
CONFIG_FB_IBM_GXT4500=m
CONFIG_FB_XILINX=m
CONFIG_FB_GOLDFISH=m
CONFIG_FB_DA8XX=m
CONFIG_FB_VIRTUAL=m
CONFIG_XEN_FBDEV_FRONTEND=m
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_BROADSHEET is not set
# CONFIG_FB_SIMPLE is not set
# CONFIG_FB_SSD1307 is not set
# CONFIG_FB_OMAP_LCD_H3 is not set
CONFIG_FB_OMAP2=m
CONFIG_FB_OMAP2_DEBUG_SUPPORT=y
CONFIG_FB_OMAP2_NUM_FBS=3
CONFIG_FB_OMAP2_DSS_INIT=y
CONFIG_FB_OMAP2_DSS=m
CONFIG_FB_OMAP2_DSS_DEBUG=y
CONFIG_FB_OMAP2_DSS_DEBUGFS=y
# CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS is not set
CONFIG_FB_OMAP2_DSS_DPI=y
CONFIG_FB_OMAP2_DSS_VENC=y
CONFIG_FB_OMAP2_DSS_HDMI_COMMON=y
CONFIG_FB_OMAP4_DSS_HDMI=y
CONFIG_FB_OMAP5_DSS_HDMI=y
CONFIG_FB_OMAP2_DSS_SDI=y
CONFIG_FB_OMAP2_DSS_DSI=y
CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK=0
# CONFIG_FB_OMAP2_DSS_SLEEP_AFTER_VENC_RESET is not set
#
# OMAPFB Panel and Encoder Drivers
#
CONFIG_FB_OMAP2_ENCODER_OPA362=m
CONFIG_FB_OMAP2_ENCODER_TFP410=m
CONFIG_FB_OMAP2_ENCODER_TPD12S015=m
CONFIG_FB_OMAP2_CONNECTOR_DVI=m
# CONFIG_FB_OMAP2_CONNECTOR_HDMI is not set
CONFIG_FB_OMAP2_CONNECTOR_ANALOG_TV=m
CONFIG_FB_OMAP2_PANEL_DPI=m
# end of OMAPFB Panel and Encoder Drivers
CONFIG_MMP_DISP=m
CONFIG_MMP_DISP_CONTROLLER=y
# CONFIG_MMP_FB is not set
# end of Frame buffer Devices
#
# Backlight & LCD device support
#
CONFIG_LCD_CLASS_DEVICE=m
# CONFIG_LCD_PLATFORM is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=m
CONFIG_BACKLIGHT_ATMEL_LCDC=y
CONFIG_BACKLIGHT_KTD253=m
# CONFIG_BACKLIGHT_OMAP1 is not set
CONFIG_BACKLIGHT_PWM=m
CONFIG_BACKLIGHT_DA903X=m
CONFIG_BACKLIGHT_MT6370=m
# CONFIG_BACKLIGHT_QCOM_WLED is not set
CONFIG_BACKLIGHT_RT4831=m
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
# CONFIG_BACKLIGHT_88PM860X is not set
CONFIG_BACKLIGHT_PCF50633=m
CONFIG_BACKLIGHT_AAT2870=m
CONFIG_BACKLIGHT_LM3630A=m
# CONFIG_BACKLIGHT_LM3639 is not set
CONFIG_BACKLIGHT_LP855X=m
CONFIG_BACKLIGHT_PANDORA=m
# CONFIG_BACKLIGHT_SKY81452 is not set
CONFIG_BACKLIGHT_TPS65217=m
CONFIG_BACKLIGHT_GPIO=m
# CONFIG_BACKLIGHT_LV5207LP is not set
CONFIG_BACKLIGHT_BD6107=m
CONFIG_BACKLIGHT_ARCXCNN=m
CONFIG_BACKLIGHT_LED=m
# end of Backlight & LCD device support
CONFIG_VIDEOMODE_HELPERS=y
CONFIG_HDMI=y
#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
# CONFIG_FRAMEBUFFER_CONSOLE is not set
# end of Console display driver support
# CONFIG_LOGO is not set
# end of Graphics support
# CONFIG_SOUND is not set
#
# HID support
#
CONFIG_HID=y
CONFIG_HID_BATTERY_STRENGTH=y
CONFIG_HIDRAW=y
# CONFIG_UHID is not set
CONFIG_HID_GENERIC=y
#
# Special HID drivers
#
# CONFIG_HID_A4TECH is not set
# CONFIG_HID_ACCUTOUCH is not set
CONFIG_HID_ACRUX=m
# CONFIG_HID_ACRUX_FF is not set
CONFIG_HID_APPLE=y
# CONFIG_HID_APPLEIR is not set
CONFIG_HID_ASUS=m
CONFIG_HID_AUREAL=m
# CONFIG_HID_BELKIN is not set
# CONFIG_HID_BETOP_FF is not set
CONFIG_HID_BIGBEN_FF=m
CONFIG_HID_CHERRY=y
CONFIG_HID_CHICONY=m
# CONFIG_HID_CORSAIR is not set
# CONFIG_HID_COUGAR is not set
CONFIG_HID_MACALLY=y
# CONFIG_HID_CMEDIA is not set
CONFIG_HID_CP2112=m
CONFIG_HID_CREATIVE_SB0540=m
CONFIG_HID_CYPRESS=m
CONFIG_HID_DRAGONRISE=y
CONFIG_DRAGONRISE_FF=y
CONFIG_HID_EMS_FF=m
CONFIG_HID_ELAN=m
# CONFIG_HID_ELECOM is not set
CONFIG_HID_ELO=m
# CONFIG_HID_EZKEY is not set
# CONFIG_HID_FT260 is not set
# CONFIG_HID_GEMBIRD is not set
# CONFIG_HID_GFRM is not set
CONFIG_HID_GLORIOUS=y
CONFIG_HID_HOLTEK=m
# CONFIG_HOLTEK_FF is not set
CONFIG_HID_VIVALDI_COMMON=y
CONFIG_HID_VIVALDI=y
CONFIG_HID_GT683R=m
CONFIG_HID_KEYTOUCH=m
# CONFIG_HID_KYE is not set
# CONFIG_HID_UCLOGIC is not set
CONFIG_HID_WALTOP=y
# CONFIG_HID_VIEWSONIC is not set
CONFIG_HID_VRC2=m
CONFIG_HID_XIAOMI=y
CONFIG_HID_GYRATION=y
# CONFIG_HID_ICADE is not set
# CONFIG_HID_ITE is not set
CONFIG_HID_JABRA=m
CONFIG_HID_TWINHAN=m
CONFIG_HID_KENSINGTON=y
CONFIG_HID_LCPOWER=y
CONFIG_HID_LED=y
CONFIG_HID_LENOVO=y
# CONFIG_HID_LETSKETCH is not set
# CONFIG_HID_LOGITECH is not set
CONFIG_HID_MAGICMOUSE=m
# CONFIG_HID_MALTRON is not set
# CONFIG_HID_MAYFLASH is not set
CONFIG_HID_MEGAWORLD_FF=m
CONFIG_HID_REDRAGON=m
CONFIG_HID_MICROSOFT=y
# CONFIG_HID_MONTEREY is not set
CONFIG_HID_MULTITOUCH=y
# CONFIG_HID_NINTENDO is not set
# CONFIG_HID_NTI is not set
CONFIG_HID_NTRIG=m
CONFIG_HID_ORTEK=y
CONFIG_HID_PANTHERLORD=y
# CONFIG_PANTHERLORD_FF is not set
CONFIG_HID_PENMOUNT=m
# CONFIG_HID_PETALYNX is not set
CONFIG_HID_PICOLCD=m
# CONFIG_HID_PICOLCD_FB is not set
CONFIG_HID_PICOLCD_BACKLIGHT=y
# CONFIG_HID_PICOLCD_LCD is not set
CONFIG_HID_PICOLCD_LEDS=y
# CONFIG_HID_PLANTRONICS is not set
CONFIG_HID_PXRC=m
CONFIG_HID_RAZER=y
CONFIG_HID_PRIMAX=y
# CONFIG_HID_RETRODE is not set
CONFIG_HID_ROCCAT=m
CONFIG_HID_SAITEK=m
# CONFIG_HID_SAMSUNG is not set
CONFIG_HID_SEMITEK=m
CONFIG_HID_SIGMAMICRO=m
# CONFIG_HID_SONY is not set
CONFIG_HID_SPEEDLINK=m
CONFIG_HID_STEAM=y
CONFIG_HID_STEELSERIES=m
CONFIG_HID_SUNPLUS=m
CONFIG_HID_RMI=y
# CONFIG_HID_GREENASIA is not set
CONFIG_HID_SMARTJOYPLUS=m
CONFIG_SMARTJOYPLUS_FF=y
CONFIG_HID_TIVO=m
CONFIG_HID_TOPSEED=y
CONFIG_HID_TOPRE=m
CONFIG_HID_THINGM=m
CONFIG_HID_THRUSTMASTER=m
# CONFIG_THRUSTMASTER_FF is not set
CONFIG_HID_UDRAW_PS3=y
# CONFIG_HID_U2FZERO is not set
CONFIG_HID_WACOM=m
CONFIG_HID_WIIMOTE=y
CONFIG_HID_XINMO=m
CONFIG_HID_ZEROPLUS=m
CONFIG_ZEROPLUS_FF=y
CONFIG_HID_ZYDACRON=m
CONFIG_HID_SENSOR_HUB=m
CONFIG_HID_SENSOR_CUSTOM_SENSOR=m
# CONFIG_HID_ALPS is not set
CONFIG_HID_MCP2221=m
# end of Special HID drivers
#
# USB HID support
#
CONFIG_USB_HID=m
# CONFIG_HID_PID is not set
CONFIG_USB_HIDDEV=y
#
# USB HID Boot Protocol drivers
#
CONFIG_USB_KBD=y
CONFIG_USB_MOUSE=y
# end of USB HID Boot Protocol drivers
# end of USB HID support
#
# I2C HID support
#
CONFIG_I2C_HID_OF=y
CONFIG_I2C_HID_OF_ELAN=y
CONFIG_I2C_HID_OF_GOODIX=m
# end of I2C HID support
CONFIG_I2C_HID_CORE=y
# end of HID support
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_LED_TRIG=y
# CONFIG_USB_ULPI_BUS is not set
CONFIG_USB_CONN_GPIO=m
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
#
# Miscellaneous USB options
#
# CONFIG_USB_DEFAULT_PERSIST is not set
CONFIG_USB_FEW_INIT_RETRIES=y
CONFIG_USB_DYNAMIC_MINORS=y
CONFIG_USB_OTG=y
# CONFIG_USB_OTG_PRODUCTLIST is not set
CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB=y
# CONFIG_USB_OTG_FSM is not set
CONFIG_USB_LEDS_TRIGGER_USBPORT=m
CONFIG_USB_AUTOSUSPEND_DELAY=2
CONFIG_USB_MON=m
#
# USB Host Controller Drivers
#
CONFIG_USB_C67X00_HCD=y
CONFIG_USB_XHCI_HCD=m
CONFIG_USB_XHCI_DBGCAP=y
# CONFIG_USB_XHCI_PCI_RENESAS is not set
CONFIG_USB_XHCI_PLATFORM=m
CONFIG_USB_XHCI_HISTB=m
CONFIG_USB_XHCI_MTK=m
# CONFIG_USB_XHCI_MVEBU is not set
CONFIG_USB_XHCI_RCAR=m
# CONFIG_USB_BRCMSTB is not set
CONFIG_USB_EHCI_HCD=m
CONFIG_USB_EHCI_ROOT_HUB_TT=y
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
CONFIG_USB_EHCI_FSL=m
# CONFIG_USB_EHCI_HCD_NPCM7XX is not set
CONFIG_USB_EHCI_HCD_ORION=m
# CONFIG_USB_EHCI_HCD_SPEAR is not set
CONFIG_USB_EHCI_HCD_STI=m
CONFIG_USB_EHCI_HCD_AT91=m
CONFIG_USB_EHCI_SH=y
CONFIG_USB_EHCI_EXYNOS=m
# CONFIG_USB_EHCI_MV is not set
CONFIG_USB_CNS3XXX_EHCI=y
CONFIG_USB_EHCI_HCD_PLATFORM=m
CONFIG_USB_OXU210HP_HCD=y
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_ISP1362_HCD is not set
# CONFIG_USB_FOTG210_HCD is not set
CONFIG_USB_OHCI_HCD=m
CONFIG_USB_OHCI_HCD_SPEAR=m
# CONFIG_USB_OHCI_HCD_STI is not set
CONFIG_USB_OHCI_HCD_S3C2410=m
CONFIG_USB_OHCI_HCD_AT91=m
CONFIG_USB_OHCI_HCD_OMAP3=m
CONFIG_USB_OHCI_HCD_DAVINCI=m
CONFIG_USB_OHCI_HCD_SSB=y
CONFIG_USB_OHCI_SH=y
# CONFIG_USB_OHCI_EXYNOS is not set
CONFIG_USB_CNS3XXX_OHCI=y
CONFIG_USB_OHCI_HCD_PLATFORM=m
CONFIG_USB_U132_HCD=m
# CONFIG_USB_SL811_HCD is not set
CONFIG_USB_R8A66597_HCD=y
# CONFIG_USB_HCD_BCMA is not set
CONFIG_USB_HCD_SSB=y
CONFIG_USB_HCD_TEST_MODE=y
CONFIG_USB_XEN_HCD=m
# CONFIG_USB_RENESAS_USBHS is not set
#
# USB Device Class drivers
#
CONFIG_USB_ACM=y
# CONFIG_USB_PRINTER is not set
CONFIG_USB_WDM=m
# CONFIG_USB_TMC is not set
#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#
#
# also be needed; see USB_STORAGE Help for more info
#
#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
CONFIG_USB_CDNS_SUPPORT=m
CONFIG_USB_CDNS_HOST=y
CONFIG_USB_CDNS3=m
CONFIG_USB_CDNS3_GADGET=y
CONFIG_USB_CDNS3_HOST=y
CONFIG_USB_CDNS3_TI=m
CONFIG_USB_CDNS3_IMX=m
# CONFIG_USB_MTU3 is not set
# CONFIG_USB_MUSB_HDRC is not set
CONFIG_USB_DWC3=m
# CONFIG_USB_DWC3_HOST is not set
CONFIG_USB_DWC3_GADGET=y
# CONFIG_USB_DWC3_DUAL_ROLE is not set
#
# Platform Glue Driver Support
#
CONFIG_USB_DWC3_OMAP=m
# CONFIG_USB_DWC3_EXYNOS is not set
CONFIG_USB_DWC3_KEYSTONE=m
CONFIG_USB_DWC3_MESON_G12A=m
CONFIG_USB_DWC3_OF_SIMPLE=m
CONFIG_USB_DWC3_ST=m
CONFIG_USB_DWC3_QCOM=m
# CONFIG_USB_DWC3_IMX8MP is not set
CONFIG_USB_DWC3_XILINX=m
CONFIG_USB_DWC3_AM62=m
CONFIG_USB_DWC2=y
CONFIG_USB_DWC2_HOST=y
#
# Gadget/Dual-role mode requires USB Gadget support to be enabled
#
# CONFIG_USB_DWC2_DEBUG is not set
CONFIG_USB_DWC2_TRACK_MISSED_SOFS=y
# CONFIG_USB_CHIPIDEA is not set
CONFIG_USB_ISP1760=m
CONFIG_USB_ISP1761_UDC=y
# CONFIG_USB_ISP1760_HOST_ROLE is not set
CONFIG_USB_ISP1760_GADGET_ROLE=y
# CONFIG_USB_ISP1760_DUAL_ROLE is not set
#
# USB port drivers
#
CONFIG_USB_USS720=m
# CONFIG_USB_SERIAL is not set
#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
CONFIG_USB_EMI26=y
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_SEVSEG is not set
CONFIG_USB_LEGOTOWER=y
CONFIG_USB_LCD=m
# CONFIG_USB_CYPRESS_CY7C63 is not set
CONFIG_USB_CYTHERM=y
# CONFIG_USB_IDMOUSE is not set
CONFIG_USB_FTDI_ELAN=y
CONFIG_USB_APPLEDISPLAY=m
CONFIG_USB_QCOM_EUD=y
CONFIG_APPLE_MFI_FASTCHARGE=m
# CONFIG_USB_SISUSBVGA is not set
# CONFIG_USB_LD is not set
CONFIG_USB_TRANCEVIBRATOR=y
# CONFIG_USB_IOWARRIOR is not set
CONFIG_USB_TEST=y
CONFIG_USB_EHSET_TEST_FIXTURE=m
CONFIG_USB_ISIGHTFW=m
# CONFIG_USB_YUREX is not set
CONFIG_USB_EZUSB_FX2=y
CONFIG_USB_HUB_USB251XB=y
CONFIG_USB_HSIC_USB3503=m
# CONFIG_USB_HSIC_USB4604 is not set
CONFIG_USB_LINK_LAYER_TEST=m
CONFIG_USB_CHAOSKEY=m
CONFIG_BRCM_USB_PINMAP=m
# CONFIG_USB_ONBOARD_HUB is not set
#
# USB Physical Layer drivers
#
CONFIG_USB_PHY=y
# CONFIG_NOP_USB_XCEIV is not set
CONFIG_USB_GPIO_VBUS=m
# CONFIG_TAHVO_USB is not set
# CONFIG_USB_ISP1301 is not set
# CONFIG_USB_TEGRA_PHY is not set
# CONFIG_USB_ULPI is not set
# CONFIG_JZ4770_PHY is not set
# end of USB Physical Layer drivers
CONFIG_USB_GADGET=m
CONFIG_USB_GADGET_DEBUG=y
CONFIG_USB_GADGET_VERBOSE=y
CONFIG_USB_GADGET_DEBUG_FS=y
CONFIG_USB_GADGET_VBUS_DRAW=2
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
# CONFIG_U_SERIAL_CONSOLE is not set
#
# USB Peripheral Controller
#
# CONFIG_USB_LPC32XX is not set
# CONFIG_USB_FOTG210_UDC is not set
CONFIG_USB_GR_UDC=m
CONFIG_USB_R8A66597=m
# CONFIG_USB_RENESAS_USB3 is not set
CONFIG_USB_PXA27X=m
CONFIG_USB_MV_UDC=m
CONFIG_USB_MV_U3D=m
# CONFIG_USB_SNP_UDC_PLAT is not set
CONFIG_USB_M66592=m
CONFIG_USB_BDC_UDC=m
# CONFIG_USB_NET2272 is not set
# CONFIG_USB_GADGET_XILINX is not set
# CONFIG_USB_ASPEED_UDC is not set
# CONFIG_USB_ASPEED_VHUB is not set
CONFIG_USB_DUMMY_HCD=m
# end of USB Peripheral Controller
CONFIG_USB_LIBCOMPOSITE=m
CONFIG_USB_F_SS_LB=m
CONFIG_USB_U_SERIAL=m
CONFIG_USB_F_PRINTER=m
# CONFIG_USB_CONFIGFS is not set
#
# USB Gadget precomposed configurations
#
CONFIG_USB_ZERO=m
# CONFIG_USB_ZERO_HNPTEST is not set
CONFIG_USB_GADGETFS=m
# CONFIG_USB_FUNCTIONFS is not set
# CONFIG_USB_G_SERIAL is not set
CONFIG_USB_G_PRINTER=m
# CONFIG_USB_G_HID is not set
CONFIG_USB_G_DBGP=m
# CONFIG_USB_G_DBGP_PRINTK is not set
CONFIG_USB_G_DBGP_SERIAL=y
CONFIG_USB_RAW_GADGET=m
# end of USB Gadget precomposed configurations
CONFIG_TYPEC=m
# CONFIG_TYPEC_TCPM is not set
# CONFIG_TYPEC_UCSI is not set
CONFIG_TYPEC_TPS6598X=m
# CONFIG_TYPEC_ANX7411 is not set
CONFIG_TYPEC_RT1719=m
CONFIG_TYPEC_HD3SS3220=m
# CONFIG_TYPEC_STUSB160X is not set
# CONFIG_TYPEC_QCOM_PMIC is not set
CONFIG_TYPEC_WUSB3801=m
#
# USB Type-C Multiplexer/DeMultiplexer Switch support
#
CONFIG_TYPEC_MUX_FSA4480=m
# CONFIG_TYPEC_MUX_PI3USB30532 is not set
# end of USB Type-C Multiplexer/DeMultiplexer Switch support
#
# USB Type-C Alternate Mode drivers
#
CONFIG_TYPEC_DP_ALTMODE=m
# CONFIG_TYPEC_NVIDIA_ALTMODE is not set
# end of USB Type-C Alternate Mode drivers
CONFIG_USB_ROLE_SWITCH=y
CONFIG_MMC=y
CONFIG_PWRSEQ_EMMC=m
CONFIG_PWRSEQ_SIMPLE=y
# CONFIG_SDIO_UART is not set
CONFIG_MMC_TEST=y
#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_ARMMMCI=y
CONFIG_MMC_STM32_SDMMC=y
# CONFIG_MMC_SDHCI is not set
CONFIG_MMC_MESON_GX=m
# CONFIG_MMC_MESON_MX_SDHC is not set
CONFIG_MMC_MESON_MX_SDIO=m
# CONFIG_MMC_MOXART is not set
CONFIG_MMC_OMAP_HS=y
# CONFIG_MMC_DAVINCI is not set
# CONFIG_MMC_S3C is not set
CONFIG_MMC_TMIO_CORE=y
CONFIG_MMC_TMIO=y
CONFIG_MMC_SDHI=m
# CONFIG_MMC_SDHI_SYS_DMAC is not set
CONFIG_MMC_SDHI_INTERNAL_DMAC=m
# CONFIG_MMC_UNIPHIER is not set
CONFIG_MMC_DW=y
CONFIG_MMC_DW_PLTFM=y
CONFIG_MMC_DW_BLUEFIELD=m
CONFIG_MMC_DW_EXYNOS=m
# CONFIG_MMC_DW_HI3798CV200 is not set
CONFIG_MMC_DW_K3=y
# CONFIG_MMC_DW_ROCKCHIP is not set
CONFIG_MMC_SH_MMCIF=y
CONFIG_MMC_VUB300=m
# CONFIG_MMC_USHC is not set
CONFIG_MMC_USDHI6ROL0=y
# CONFIG_MMC_REALTEK_USB is not set
CONFIG_MMC_SUNXI=m
CONFIG_MMC_CQHCI=y
CONFIG_MMC_HSQ=y
CONFIG_MMC_BCM2835=m
# CONFIG_MMC_MTK is not set
CONFIG_MMC_OWL=y
# CONFIG_MMC_LITEX is not set
CONFIG_MEMSTICK=y
CONFIG_MEMSTICK_DEBUG=y
#
# MemoryStick drivers
#
# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
#
# MemoryStick Host Controller Drivers
#
# CONFIG_MEMSTICK_REALTEK_USB is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=m
# CONFIG_LEDS_CLASS_MULTICOLOR is not set
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
#
# LED drivers
#
# CONFIG_LEDS_88PM860X is not set
# CONFIG_LEDS_AN30259A is not set
CONFIG_LEDS_ARIEL=y
CONFIG_LEDS_AW2013=m
# CONFIG_LEDS_BCM6328 is not set
# CONFIG_LEDS_BCM6358 is not set
# CONFIG_LEDS_LM3530 is not set
# CONFIG_LEDS_LM3532 is not set
CONFIG_LEDS_LM3642=y
# CONFIG_LEDS_LM3692X is not set
CONFIG_LEDS_MT6323=y
CONFIG_LEDS_S3C24XX=y
CONFIG_LEDS_COBALT_QUBE=y
# CONFIG_LEDS_COBALT_RAQ is not set
CONFIG_LEDS_PCA9532=y
# CONFIG_LEDS_PCA9532_GPIO is not set
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_LP3944=y
CONFIG_LEDS_LP3952=y
# CONFIG_LEDS_LP50XX is not set
CONFIG_LEDS_LP55XX_COMMON=m
CONFIG_LEDS_LP5521=m
CONFIG_LEDS_LP5523=m
# CONFIG_LEDS_LP5562 is not set
CONFIG_LEDS_LP8501=m
# CONFIG_LEDS_LP8860 is not set
CONFIG_LEDS_PCA955X=y
# CONFIG_LEDS_PCA955X_GPIO is not set
# CONFIG_LEDS_PCA963X is not set
CONFIG_LEDS_WM8350=m
# CONFIG_LEDS_DA903X is not set
CONFIG_LEDS_PWM=y
CONFIG_LEDS_REGULATOR=m
CONFIG_LEDS_BD2802=y
CONFIG_LEDS_LT3593=y
CONFIG_LEDS_MC13783=m
CONFIG_LEDS_NS2=y
# CONFIG_LEDS_NETXBIG is not set
# CONFIG_LEDS_ASIC3 is not set
CONFIG_LEDS_TCA6507=m
# CONFIG_LEDS_TLC591XX is not set
# CONFIG_LEDS_MAX77650 is not set
CONFIG_LEDS_LM355x=m
CONFIG_LEDS_OT200=y
CONFIG_LEDS_MENF21BMC=y
CONFIG_LEDS_IS31FL319X=m
# CONFIG_LEDS_IS31FL32XX is not set
#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
# CONFIG_LEDS_BLINKM is not set
# CONFIG_LEDS_SYSCON is not set
CONFIG_LEDS_MLXREG=y
CONFIG_LEDS_USER=m
CONFIG_LEDS_TI_LMU_COMMON=m
CONFIG_LEDS_LM3697=m
# CONFIG_LEDS_LM36274 is not set
CONFIG_LEDS_TPS6105X=m
CONFIG_LEDS_IP30=m
CONFIG_LEDS_BCM63138=y
CONFIG_LEDS_LGM=y
#
# Flash and Torch LED drivers
#
CONFIG_LEDS_AAT1290=m
CONFIG_LEDS_AS3645A=m
CONFIG_LEDS_KTD2692=m
CONFIG_LEDS_LM3601X=m
# CONFIG_LEDS_MAX77693 is not set
# CONFIG_LEDS_MT6360 is not set
CONFIG_LEDS_RT4505=m
CONFIG_LEDS_RT8515=m
# CONFIG_LEDS_SGM3140 is not set
#
# RGB LED drivers
#
#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
# CONFIG_LEDS_TRIGGER_ONESHOT is not set
CONFIG_LEDS_TRIGGER_MTD=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=m
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
# CONFIG_LEDS_TRIGGER_CPU is not set
CONFIG_LEDS_TRIGGER_ACTIVITY=y
CONFIG_LEDS_TRIGGER_GPIO=y
# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=y
CONFIG_LEDS_TRIGGER_CAMERA=m
CONFIG_LEDS_TRIGGER_PANIC=y
CONFIG_LEDS_TRIGGER_PATTERN=m
CONFIG_LEDS_TRIGGER_AUDIO=m
# CONFIG_LEDS_TRIGGER_TTY is not set
#
# Simple LED drivers
#
CONFIG_ACCESSIBILITY=y
# CONFIG_A11Y_BRAILLE_CONSOLE is not set
#
# Speakup console speech
#
CONFIG_SPEAKUP=y
CONFIG_SPEAKUP_SERIALIO=y
CONFIG_SPEAKUP_SYNTH_ACNTSA=y
# CONFIG_SPEAKUP_SYNTH_ACNTPC is not set
CONFIG_SPEAKUP_SYNTH_APOLLO=y
CONFIG_SPEAKUP_SYNTH_AUDPTR=m
CONFIG_SPEAKUP_SYNTH_BNS=m
CONFIG_SPEAKUP_SYNTH_DECTLK=m
CONFIG_SPEAKUP_SYNTH_DECEXT=y
CONFIG_SPEAKUP_SYNTH_DECPC=m
CONFIG_SPEAKUP_SYNTH_DTLK=m
CONFIG_SPEAKUP_SYNTH_KEYPC=y
CONFIG_SPEAKUP_SYNTH_LTLK=m
# CONFIG_SPEAKUP_SYNTH_SOFT is not set
CONFIG_SPEAKUP_SYNTH_SPKOUT=m
CONFIG_SPEAKUP_SYNTH_TXPRT=m
CONFIG_SPEAKUP_SYNTH_DUMMY=m
# end of Speakup console speech
CONFIG_EDAC_SUPPORT=y
CONFIG_EDAC=y
# CONFIG_EDAC_LEGACY_SYSFS is not set
CONFIG_EDAC_DEBUG=y
CONFIG_EDAC_AL_MC=m
# CONFIG_EDAC_ALTERA is not set
CONFIG_EDAC_SYNOPSYS=y
# CONFIG_EDAC_XGENE is not set
CONFIG_EDAC_BLUEFIELD=y
# CONFIG_EDAC_DMC520 is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_SYSTOHC is not set
# CONFIG_RTC_DEBUG is not set
CONFIG_RTC_LIB_KUNIT_TEST=m
CONFIG_RTC_NVMEM=y
#
# RTC interfaces
#
# CONFIG_RTC_INTF_SYSFS is not set
# CONFIG_RTC_INTF_DEV is not set
CONFIG_RTC_DRV_TEST=y
#
# I2C RTC drivers
#
CONFIG_RTC_DRV_88PM860X=y
CONFIG_RTC_DRV_ABB5ZES3=y
CONFIG_RTC_DRV_ABEOZ9=m
CONFIG_RTC_DRV_ABX80X=m
# CONFIG_RTC_DRV_BRCMSTB is not set
# CONFIG_RTC_DRV_DS1307 is not set
CONFIG_RTC_DRV_DS1374=y
# CONFIG_RTC_DRV_DS1374_WDT is not set
CONFIG_RTC_DRV_DS1672=m
CONFIG_RTC_DRV_HYM8563=y
CONFIG_RTC_DRV_MAX6900=m
CONFIG_RTC_DRV_MAX8907=m
# CONFIG_RTC_DRV_MAX77686 is not set
CONFIG_RTC_DRV_NCT3018Y=m
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
CONFIG_RTC_DRV_ISL12022=y
# CONFIG_RTC_DRV_ISL12026 is not set
CONFIG_RTC_DRV_X1205=m
CONFIG_RTC_DRV_PCF8523=m
CONFIG_RTC_DRV_PCF85063=y
CONFIG_RTC_DRV_PCF85363=y
CONFIG_RTC_DRV_PCF8563=y
CONFIG_RTC_DRV_PCF8583=y
CONFIG_RTC_DRV_M41T80=y
CONFIG_RTC_DRV_M41T80_WDT=y
# CONFIG_RTC_DRV_BD70528 is not set
CONFIG_RTC_DRV_BQ32K=m
CONFIG_RTC_DRV_TWL4030=y
# CONFIG_RTC_DRV_RC5T583 is not set
CONFIG_RTC_DRV_S35390A=m
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8010 is not set
CONFIG_RTC_DRV_RX8581=y
CONFIG_RTC_DRV_RX8025=y
# CONFIG_RTC_DRV_EM3027 is not set
# CONFIG_RTC_DRV_RV3028 is not set
CONFIG_RTC_DRV_RV3032=y
# CONFIG_RTC_DRV_RV8803 is not set
CONFIG_RTC_DRV_S5M=y
CONFIG_RTC_DRV_SD3078=m
#
# SPI RTC drivers
#
CONFIG_RTC_I2C_AND_SPI=y
#
# SPI and I2C RTC drivers
#
# CONFIG_RTC_DRV_DS3232 is not set
CONFIG_RTC_DRV_PCF2127=y
CONFIG_RTC_DRV_RV3029C2=y
CONFIG_RTC_DRV_RX6110=m
#
# Platform RTC drivers
#
CONFIG_RTC_DRV_DS1286=y
CONFIG_RTC_DRV_DS1511=m
CONFIG_RTC_DRV_DS1553=y
# CONFIG_RTC_DRV_DS1685_FAMILY is not set
CONFIG_RTC_DRV_DS1742=m
# CONFIG_RTC_DRV_DS2404 is not set
# CONFIG_RTC_DRV_DA9055 is not set
CONFIG_RTC_DRV_DA9063=y
CONFIG_RTC_DRV_STK17TA8=m
CONFIG_RTC_DRV_M48T86=y
CONFIG_RTC_DRV_M48T35=y
CONFIG_RTC_DRV_M48T59=m
# CONFIG_RTC_DRV_MSM6242 is not set
CONFIG_RTC_DRV_BQ4802=y
CONFIG_RTC_DRV_RP5C01=y
CONFIG_RTC_DRV_V3020=y
CONFIG_RTC_DRV_GAMECUBE=y
CONFIG_RTC_DRV_WM8350=y
CONFIG_RTC_DRV_SC27XX=y
# CONFIG_RTC_DRV_SPEAR is not set
CONFIG_RTC_DRV_PCF50633=m
CONFIG_RTC_DRV_ZYNQMP=m
#
# on-CPU RTC drivers
#
CONFIG_RTC_DRV_ASM9260=m
# CONFIG_RTC_DRV_DAVINCI is not set
CONFIG_RTC_DRV_DIGICOLOR=m
CONFIG_RTC_DRV_FSL_FTM_ALARM=m
CONFIG_RTC_DRV_MESON=y
# CONFIG_RTC_DRV_MESON_VRTC is not set
CONFIG_RTC_DRV_OMAP=m
CONFIG_RTC_DRV_S3C=m
CONFIG_RTC_DRV_EP93XX=m
CONFIG_RTC_DRV_SH=m
# CONFIG_RTC_DRV_PL030 is not set
CONFIG_RTC_DRV_PL031=m
# CONFIG_RTC_DRV_AT91RM9200 is not set
CONFIG_RTC_DRV_AT91SAM9=y
CONFIG_RTC_DRV_RZN1=m
CONFIG_RTC_DRV_GENERIC=y
CONFIG_RTC_DRV_VT8500=y
CONFIG_RTC_DRV_SUN6I=y
CONFIG_RTC_DRV_SUNXI=y
# CONFIG_RTC_DRV_MV is not set
CONFIG_RTC_DRV_ARMADA38X=m
CONFIG_RTC_DRV_CADENCE=m
CONFIG_RTC_DRV_FTRTC010=m
# CONFIG_RTC_DRV_STMP is not set
CONFIG_RTC_DRV_MC13XXX=m
CONFIG_RTC_DRV_JZ4740=y
# CONFIG_RTC_DRV_LPC24XX is not set
# CONFIG_RTC_DRV_LPC32XX is not set
CONFIG_RTC_DRV_PM8XXX=m
CONFIG_RTC_DRV_TEGRA=y
CONFIG_RTC_DRV_MXC=y
CONFIG_RTC_DRV_MXC_V2=m
CONFIG_RTC_DRV_SNVS=y
CONFIG_RTC_DRV_IMX_SC=m
CONFIG_RTC_DRV_MOXART=y
CONFIG_RTC_DRV_MT2712=m
CONFIG_RTC_DRV_MT6397=m
CONFIG_RTC_DRV_MT7622=m
CONFIG_RTC_DRV_XGENE=m
# CONFIG_RTC_DRV_R7301 is not set
CONFIG_RTC_DRV_STM32=m
CONFIG_RTC_DRV_RTD119X=y
# CONFIG_RTC_DRV_ASPEED is not set
CONFIG_RTC_DRV_TI_K3=m
#
# HID Sensor RTC drivers
#
CONFIG_RTC_DRV_HID_SENSOR_TIME=m
# CONFIG_RTC_DRV_GOLDFISH is not set
CONFIG_RTC_DRV_MSC313=m
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set
#
# DMA Devices
#
CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_OF=y
CONFIG_ALTERA_MSGDMA=y
CONFIG_AMBA_PL08X=y
# CONFIG_APPLE_ADMAC is not set
CONFIG_AXI_DMAC=m
CONFIG_DMA_JZ4780=y
CONFIG_DMA_SA11X0=m
CONFIG_DMA_SUN6I=m
# CONFIG_DW_AXI_DMAC is not set
# CONFIG_EP93XX_DMA is not set
CONFIG_FSL_EDMA=m
CONFIG_FSL_QDMA=y
CONFIG_IMG_MDC_DMA=y
CONFIG_INTEL_IDMA64=y
# CONFIG_INTEL_IOP_ADMA is not set
# CONFIG_K3_DMA is not set
# CONFIG_LPC18XX_DMAMUX is not set
# CONFIG_MCF_EDMA is not set
CONFIG_MILBEAUT_HDMAC=y
# CONFIG_MILBEAUT_XDMAC is not set
CONFIG_MMP_PDMA=m
CONFIG_MMP_TDMA=y
CONFIG_MV_XOR=y
CONFIG_MV_XOR_V2=y
CONFIG_MXS_DMA=y
CONFIG_NBPFAXI_DMA=m
CONFIG_OWL_DMA=y
CONFIG_PL330_DMA=m
CONFIG_STM32_DMA=y
# CONFIG_STM32_DMAMUX is not set
CONFIG_STM32_MDMA=y
CONFIG_SPRD_DMA=y
# CONFIG_S3C24XX_DMAC is not set
CONFIG_TEGRA186_GPC_DMA=y
# CONFIG_TEGRA20_APB_DMA is not set
CONFIG_TEGRA210_ADMA=y
CONFIG_TIMB_DMA=m
# CONFIG_UNIPHIER_MDMAC is not set
CONFIG_UNIPHIER_XDMAC=m
# CONFIG_XGENE_DMA is not set
CONFIG_XILINX_DMA=y
CONFIG_XILINX_ZYNQMP_DMA=m
CONFIG_XILINX_ZYNQMP_DPDMA=m
CONFIG_MTK_HSDMA=y
CONFIG_MTK_CQDMA=m
CONFIG_QCOM_HIDMA_MGMT=y
# CONFIG_QCOM_HIDMA is not set
CONFIG_DW_DMAC_CORE=y
CONFIG_DW_DMAC=y
CONFIG_RZN1_DMAMUX=m
# CONFIG_SF_PDMA is not set
CONFIG_RENESAS_DMA=y
# CONFIG_SH_DMAE_BASE is not set
# CONFIG_RCAR_DMAC is not set
CONFIG_RENESAS_USB_DMAC=m
# CONFIG_RZ_DMAC is not set
CONFIG_TI_EDMA=m
CONFIG_DMA_OMAP=m
# CONFIG_TI_K3_UDMA is not set
CONFIG_TI_DMA_CROSSBAR=y
CONFIG_INTEL_LDMA=y
#
# DMA Clients
#
CONFIG_ASYNC_TX_DMA=y
# CONFIG_DMATEST is not set
CONFIG_DMA_ENGINE_RAID=y
#
# DMABUF options
#
CONFIG_SYNC_FILE=y
CONFIG_SW_SYNC=y
# CONFIG_UDMABUF is not set
# CONFIG_DMABUF_MOVE_NOTIFY is not set
# CONFIG_DMABUF_DEBUG is not set
CONFIG_DMABUF_SELFTESTS=m
CONFIG_DMABUF_HEAPS=y
CONFIG_DMABUF_SYSFS_STATS=y
CONFIG_DMABUF_HEAPS_SYSTEM=y
CONFIG_DMABUF_HEAPS_CMA=y
# end of DMABUF options
CONFIG_AUXDISPLAY=y
CONFIG_CHARLCD=y
CONFIG_LINEDISP=m
CONFIG_HD44780_COMMON=y
CONFIG_HD44780=m
# CONFIG_IMG_ASCII_LCD is not set
CONFIG_HT16K33=m
CONFIG_LCD2S=y
CONFIG_PARPORT_PANEL=m
CONFIG_PANEL_PARPORT=0
CONFIG_PANEL_PROFILE=5
# CONFIG_PANEL_CHANGE_MESSAGE is not set
# CONFIG_CHARLCD_BL_OFF is not set
# CONFIG_CHARLCD_BL_ON is not set
CONFIG_CHARLCD_BL_FLASH=y
CONFIG_PANEL=m
CONFIG_UIO=m
CONFIG_UIO_PDRV_GENIRQ=m
# CONFIG_UIO_DMEM_GENIRQ is not set
CONFIG_UIO_PRUSS=m
CONFIG_VFIO=m
CONFIG_VFIO_IOMMU_TYPE1=m
CONFIG_VFIO_VIRQFD=m
# CONFIG_VFIO_NOIOMMU is not set
CONFIG_VFIO_PLATFORM=m
CONFIG_VFIO_AMBA=m
# CONFIG_VFIO_PLATFORM_CALXEDAXGMAC_RESET is not set
CONFIG_VFIO_PLATFORM_AMDXGBE_RESET=m
CONFIG_VFIO_PLATFORM_BCMFLEXRM_RESET=m
CONFIG_VFIO_MDEV=m
CONFIG_VIRT_DRIVERS=y
CONFIG_VIRTIO_ANCHOR=y
CONFIG_VIRTIO=m
CONFIG_VIRTIO_MENU=y
CONFIG_VIRTIO_BALLOON=m
CONFIG_VIRTIO_INPUT=m
CONFIG_VIRTIO_MMIO=m
CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
CONFIG_VIRTIO_DMA_SHARED_BUFFER=m
CONFIG_VHOST_MENU=y
CONFIG_VHOST_CROSS_ENDIAN_LEGACY=y
#
# Microsoft Hyper-V guest support
#
# end of Microsoft Hyper-V guest support
#
# Xen driver support
#
# CONFIG_XEN_BALLOON is not set
CONFIG_XEN_DEV_EVTCHN=y
CONFIG_XEN_BACKEND=y
# CONFIG_XENFS is not set
# CONFIG_XEN_SYS_HYPERVISOR is not set
CONFIG_XEN_XENBUS_FRONTEND=m
CONFIG_XEN_GNTDEV=y
CONFIG_XEN_GRANT_DEV_ALLOC=m
# CONFIG_XEN_GRANT_DMA_ALLOC is not set
CONFIG_SWIOTLB_XEN=y
CONFIG_XEN_PRIVCMD=m
CONFIG_XEN_AUTO_XLATE=y
# CONFIG_XEN_VIRTIO is not set
# end of Xen driver support
CONFIG_GREYBUS=m
CONFIG_GREYBUS_ES2=m
CONFIG_COMEDI=m
CONFIG_COMEDI_DEBUG=y
CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048
CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480
# CONFIG_COMEDI_MISC_DRIVERS is not set
# CONFIG_COMEDI_ISA_DRIVERS is not set
# CONFIG_COMEDI_USB_DRIVERS is not set
# CONFIG_COMEDI_8255_SA is not set
CONFIG_COMEDI_KCOMEDILIB=m
CONFIG_COMEDI_NI_ROUTING=m
CONFIG_COMEDI_TESTS=m
CONFIG_COMEDI_TESTS_EXAMPLE=m
CONFIG_COMEDI_TESTS_NI_ROUTES=m
# CONFIG_STAGING is not set
# CONFIG_GOLDFISH is not set
# CONFIG_CHROME_PLATFORMS is not set
# CONFIG_MELLANOX_PLATFORM is not set
# CONFIG_OLPC_XO175 is not set
# CONFIG_SURFACE_PLATFORMS is not set
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y
#
# Clock driver for ARM Reference designs
#
CONFIG_CLK_ICST=y
# CONFIG_CLK_SP810 is not set
# end of Clock driver for ARM Reference designs
# CONFIG_CLK_HSDK is not set
CONFIG_COMMON_CLK_APPLE_NCO=y
CONFIG_COMMON_CLK_MAX77686=y
CONFIG_COMMON_CLK_MAX9485=m
CONFIG_COMMON_CLK_HI655X=y
CONFIG_COMMON_CLK_SCMI=y
# CONFIG_COMMON_CLK_SCPI is not set
CONFIG_COMMON_CLK_SI5341=m
CONFIG_COMMON_CLK_SI5351=m
CONFIG_COMMON_CLK_SI514=m
CONFIG_COMMON_CLK_SI544=y
# CONFIG_COMMON_CLK_SI570 is not set
# CONFIG_COMMON_CLK_BM1880 is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_TPS68470 is not set
CONFIG_COMMON_CLK_CDCE925=m
# CONFIG_COMMON_CLK_CS2000_CP is not set
CONFIG_COMMON_CLK_EN7523=y
# CONFIG_COMMON_CLK_FSL_FLEXSPI is not set
# CONFIG_COMMON_CLK_FSL_SAI is not set
CONFIG_COMMON_CLK_GEMINI=y
CONFIG_COMMON_CLK_LAN966X=y
CONFIG_COMMON_CLK_ASPEED=y
# CONFIG_COMMON_CLK_S2MPS11 is not set
CONFIG_CLK_TWL6040=y
CONFIG_COMMON_CLK_AXI_CLKGEN=m
CONFIG_CLK_QORIQ=y
# CONFIG_CLK_LS1028A_PLLDIG is not set
CONFIG_COMMON_CLK_XGENE=y
# CONFIG_COMMON_CLK_LOCHNAGAR is not set
CONFIG_COMMON_CLK_PWM=m
# CONFIG_COMMON_CLK_OXNAS is not set
CONFIG_COMMON_CLK_RS9_PCIE=m
# CONFIG_COMMON_CLK_VC5 is not set
CONFIG_COMMON_CLK_VC7=y
# CONFIG_COMMON_CLK_MMP2_AUDIO is not set
CONFIG_COMMON_CLK_BD718XX=m
CONFIG_COMMON_CLK_FIXED_MMIO=y
CONFIG_CLK_ACTIONS=y
# CONFIG_CLK_OWL_S500 is not set
CONFIG_CLK_OWL_S700=y
CONFIG_CLK_OWL_S900=y
CONFIG_CLK_BAIKAL_T1=y
# CONFIG_CLK_BT1_CCU_PLL is not set
# CONFIG_CLK_BT1_CCU_DIV is not set
CONFIG_CLK_BT1_CCU_RST=y
CONFIG_CLK_BCM2711_DVP=y
# CONFIG_CLK_BCM2835 is not set
# CONFIG_CLK_BCM_63XX is not set
# CONFIG_CLK_BCM_63XX_GATE is not set
CONFIG_CLK_BCM_KONA=y
CONFIG_COMMON_CLK_IPROC=y
CONFIG_CLK_BCM_CYGNUS=y
CONFIG_CLK_BCM_HR2=y
# CONFIG_CLK_BCM_NSP is not set
# CONFIG_CLK_BCM_NS2 is not set
# CONFIG_CLK_BCM_SR is not set
CONFIG_CLK_RASPBERRYPI=y
# CONFIG_COMMON_CLK_HI3516CV300 is not set
CONFIG_COMMON_CLK_HI3519=y
CONFIG_COMMON_CLK_HI3559A=y
CONFIG_COMMON_CLK_HI3660=y
CONFIG_COMMON_CLK_HI3670=y
# CONFIG_COMMON_CLK_HI3798CV200 is not set
# CONFIG_COMMON_CLK_HI6220 is not set
CONFIG_RESET_HISI=y
CONFIG_STUB_CLK_HI6220=y
CONFIG_STUB_CLK_HI3660=y
# CONFIG_COMMON_CLK_BOSTON is not set
CONFIG_MXC_CLK=y
CONFIG_CLK_IMX8MM=m
CONFIG_CLK_IMX8MN=m
CONFIG_CLK_IMX8MP=m
# CONFIG_CLK_IMX8MQ is not set
# CONFIG_CLK_IMX8QXP is not set
# CONFIG_CLK_IMX8ULP is not set
CONFIG_CLK_IMX93=y
#
# Ingenic SoCs drivers
#
CONFIG_INGENIC_CGU_COMMON=y
CONFIG_INGENIC_CGU_JZ4740=y
CONFIG_INGENIC_CGU_JZ4725B=y
CONFIG_INGENIC_CGU_JZ4760=y
# CONFIG_INGENIC_CGU_JZ4770 is not set
# CONFIG_INGENIC_CGU_JZ4780 is not set
CONFIG_INGENIC_CGU_X1000=y
CONFIG_INGENIC_CGU_X1830=y
# CONFIG_INGENIC_TCU_CLK is not set
# end of Ingenic SoCs drivers
CONFIG_COMMON_CLK_KEYSTONE=m
CONFIG_TI_SCI_CLK=m
CONFIG_TI_SCI_CLK_PROBE_FROM_FW=y
# CONFIG_TI_SYSCON_CLK is not set
#
# Clock driver for MediaTek SoC
#
CONFIG_COMMON_CLK_MEDIATEK=y
CONFIG_COMMON_CLK_MT2701=y
CONFIG_COMMON_CLK_MT2701_MMSYS=y
# CONFIG_COMMON_CLK_MT2701_IMGSYS is not set
CONFIG_COMMON_CLK_MT2701_VDECSYS=y
# CONFIG_COMMON_CLK_MT2701_HIFSYS is not set
# CONFIG_COMMON_CLK_MT2701_ETHSYS is not set
# CONFIG_COMMON_CLK_MT2701_BDPSYS is not set
CONFIG_COMMON_CLK_MT2701_AUDSYS=y
CONFIG_COMMON_CLK_MT2701_G3DSYS=y
# CONFIG_COMMON_CLK_MT2712 is not set
CONFIG_COMMON_CLK_MT6765=y
CONFIG_COMMON_CLK_MT6765_AUDIOSYS=y
CONFIG_COMMON_CLK_MT6765_CAMSYS=y
# CONFIG_COMMON_CLK_MT6765_GCESYS is not set
CONFIG_COMMON_CLK_MT6765_MMSYS=y
# CONFIG_COMMON_CLK_MT6765_IMGSYS is not set
CONFIG_COMMON_CLK_MT6765_VCODECSYS=y
# CONFIG_COMMON_CLK_MT6765_MFGSYS is not set
CONFIG_COMMON_CLK_MT6765_MIPI0ASYS=y
# CONFIG_COMMON_CLK_MT6765_MIPI0BSYS is not set
# CONFIG_COMMON_CLK_MT6765_MIPI1ASYS is not set
# CONFIG_COMMON_CLK_MT6765_MIPI1BSYS is not set
# CONFIG_COMMON_CLK_MT6765_MIPI2ASYS is not set
CONFIG_COMMON_CLK_MT6765_MIPI2BSYS=y
CONFIG_COMMON_CLK_MT6779=m
# CONFIG_COMMON_CLK_MT6779_MMSYS is not set
# CONFIG_COMMON_CLK_MT6779_IMGSYS is not set
CONFIG_COMMON_CLK_MT6779_IPESYS=m
# CONFIG_COMMON_CLK_MT6779_CAMSYS is not set
# CONFIG_COMMON_CLK_MT6779_VDECSYS is not set
CONFIG_COMMON_CLK_MT6779_VENCSYS=m
# CONFIG_COMMON_CLK_MT6779_MFGCFG is not set
CONFIG_COMMON_CLK_MT6779_AUDSYS=m
# CONFIG_COMMON_CLK_MT6795 is not set
CONFIG_COMMON_CLK_MT6797=y
CONFIG_COMMON_CLK_MT6797_MMSYS=y
CONFIG_COMMON_CLK_MT6797_IMGSYS=y
CONFIG_COMMON_CLK_MT6797_VDECSYS=y
# CONFIG_COMMON_CLK_MT6797_VENCSYS is not set
CONFIG_COMMON_CLK_MT7622=y
# CONFIG_COMMON_CLK_MT7622_ETHSYS is not set
# CONFIG_COMMON_CLK_MT7622_HIFSYS is not set
CONFIG_COMMON_CLK_MT7622_AUDSYS=y
# CONFIG_COMMON_CLK_MT7629 is not set
# CONFIG_COMMON_CLK_MT7986 is not set
CONFIG_COMMON_CLK_MT8135=y
CONFIG_COMMON_CLK_MT8167=y
# CONFIG_COMMON_CLK_MT8167_AUDSYS is not set
CONFIG_COMMON_CLK_MT8167_IMGSYS=y
# CONFIG_COMMON_CLK_MT8167_MFGCFG is not set
CONFIG_COMMON_CLK_MT8167_MMSYS=y
# CONFIG_COMMON_CLK_MT8167_VDECSYS is not set
CONFIG_COMMON_CLK_MT8173=y
# CONFIG_COMMON_CLK_MT8173_MMSYS is not set
# CONFIG_COMMON_CLK_MT8183 is not set
# CONFIG_COMMON_CLK_MT8186 is not set
# CONFIG_COMMON_CLK_MT8192 is not set
# CONFIG_COMMON_CLK_MT8195 is not set
CONFIG_COMMON_CLK_MT8365=y
# CONFIG_COMMON_CLK_MT8365_APU is not set
CONFIG_COMMON_CLK_MT8365_CAM=y
CONFIG_COMMON_CLK_MT8365_MFG=m
CONFIG_COMMON_CLK_MT8365_MMSYS=m
CONFIG_COMMON_CLK_MT8365_VDEC=m
CONFIG_COMMON_CLK_MT8365_VENC=m
# CONFIG_COMMON_CLK_MT8516 is not set
# end of Clock driver for MediaTek SoC
#
# Clock support for Amlogic platforms
#
CONFIG_COMMON_CLK_MESON_REGMAP=y
CONFIG_COMMON_CLK_MESON_DUALDIV=y
CONFIG_COMMON_CLK_MESON_MPLL=y
CONFIG_COMMON_CLK_MESON_PHASE=y
CONFIG_COMMON_CLK_MESON_PLL=y
CONFIG_COMMON_CLK_MESON_SCLK_DIV=y
CONFIG_COMMON_CLK_MESON_VID_PLL_DIV=y
CONFIG_COMMON_CLK_MESON_AO_CLKC=y
CONFIG_COMMON_CLK_MESON_EE_CLKC=y
CONFIG_COMMON_CLK_MESON_CPU_DYNDIV=y
# CONFIG_COMMON_CLK_GXBB is not set
# CONFIG_COMMON_CLK_AXG is not set
CONFIG_COMMON_CLK_AXG_AUDIO=y
CONFIG_COMMON_CLK_G12A=y
# end of Clock support for Amlogic platforms
# CONFIG_MSTAR_MSC313_MPLL is not set
CONFIG_MCHP_CLK_MPFS=y
# CONFIG_COMMON_CLK_PISTACHIO is not set
# CONFIG_COMMON_CLK_QCOM is not set
CONFIG_CLK_MT7621=y
CONFIG_CLK_RENESAS=y
# CONFIG_CLK_EMEV2 is not set
# CONFIG_CLK_RZA1 is not set
CONFIG_CLK_R7S9210=y
CONFIG_CLK_R8A73A4=y
# CONFIG_CLK_R8A7740 is not set
CONFIG_CLK_R8A7742=y
# CONFIG_CLK_R8A7743 is not set
# CONFIG_CLK_R8A7745 is not set
# CONFIG_CLK_R8A77470 is not set
CONFIG_CLK_R8A774A1=y
CONFIG_CLK_R8A774B1=y
CONFIG_CLK_R8A774C0=y
CONFIG_CLK_R8A774E1=y
# CONFIG_CLK_R8A7778 is not set
# CONFIG_CLK_R8A7779 is not set
# CONFIG_CLK_R8A7790 is not set
# CONFIG_CLK_R8A7791 is not set
# CONFIG_CLK_R8A7792 is not set
# CONFIG_CLK_R8A7794 is not set
CONFIG_CLK_R8A7795=y
CONFIG_CLK_R8A77960=y
CONFIG_CLK_R8A77961=y
# CONFIG_CLK_R8A77965 is not set
CONFIG_CLK_R8A77970=y
CONFIG_CLK_R8A77980=y
CONFIG_CLK_R8A77990=y
CONFIG_CLK_R8A77995=y
CONFIG_CLK_R8A779A0=y
# CONFIG_CLK_R8A779F0 is not set
# CONFIG_CLK_R8A779G0 is not set
# CONFIG_CLK_R9A06G032 is not set
# CONFIG_CLK_R9A07G043 is not set
CONFIG_CLK_R9A07G044=y
# CONFIG_CLK_R9A07G054 is not set
CONFIG_CLK_R9A09G011=y
# CONFIG_CLK_SH73A0 is not set
CONFIG_CLK_RCAR_CPG_LIB=y
CONFIG_CLK_RCAR_GEN2_CPG=y
CONFIG_CLK_RCAR_GEN3_CPG=y
CONFIG_CLK_RCAR_GEN4_CPG=y
# CONFIG_CLK_RCAR_USB2_CLOCK_SEL is not set
CONFIG_CLK_RZG2L=y
CONFIG_CLK_RENESAS_CPG_MSSR=y
CONFIG_CLK_RENESAS_CPG_MSTP=y
CONFIG_CLK_RENESAS_DIV6=y
CONFIG_COMMON_CLK_ROCKCHIP=y
CONFIG_CLK_PX30=y
# CONFIG_CLK_RV110X is not set
# CONFIG_CLK_RV1126 is not set
CONFIG_CLK_RK3036=y
# CONFIG_CLK_RK312X is not set
# CONFIG_CLK_RK3188 is not set
# CONFIG_CLK_RK322X is not set
# CONFIG_CLK_RK3288 is not set
# CONFIG_CLK_RK3308 is not set
# CONFIG_CLK_RK3328 is not set
CONFIG_CLK_RK3368=y
CONFIG_CLK_RK3399=y
# CONFIG_CLK_RK3568 is not set
CONFIG_COMMON_CLK_SAMSUNG=y
# CONFIG_S3C64XX_COMMON_CLK is not set
# CONFIG_S5PV210_COMMON_CLK is not set
# CONFIG_EXYNOS_3250_COMMON_CLK is not set
# CONFIG_EXYNOS_4_COMMON_CLK is not set
# CONFIG_EXYNOS_5250_COMMON_CLK is not set
# CONFIG_EXYNOS_5260_COMMON_CLK is not set
# CONFIG_EXYNOS_5410_COMMON_CLK is not set
# CONFIG_EXYNOS_5420_COMMON_CLK is not set
CONFIG_EXYNOS_ARM64_COMMON_CLK=y
# CONFIG_EXYNOS_AUDSS_CLK_CON is not set
CONFIG_EXYNOS_CLKOUT=m
CONFIG_S3C2410_COMMON_CLK=y
# CONFIG_S3C2412_COMMON_CLK is not set
# CONFIG_S3C2443_COMMON_CLK is not set
# CONFIG_TESLA_FSD_COMMON_CLK is not set
# CONFIG_CLK_SIFIVE is not set
CONFIG_CLK_INTEL_SOCFPGA=y
CONFIG_CLK_INTEL_SOCFPGA32=y
CONFIG_CLK_INTEL_SOCFPGA64=y
CONFIG_SPRD_COMMON_CLK=y
CONFIG_SPRD_SC9860_CLK=m
CONFIG_SPRD_SC9863A_CLK=y
CONFIG_SPRD_UMS512_CLK=m
CONFIG_CLK_STARFIVE_JH7100=y
CONFIG_CLK_STARFIVE_JH7100_AUDIO=m
# CONFIG_CLK_SUNXI is not set
CONFIG_SUNXI_CCU=y
CONFIG_SUNIV_F1C100S_CCU=y
CONFIG_SUN20I_D1_CCU=m
# CONFIG_SUN20I_D1_R_CCU is not set
CONFIG_SUN50I_A64_CCU=y
CONFIG_SUN50I_A100_CCU=y
CONFIG_SUN50I_A100_R_CCU=m
# CONFIG_SUN50I_H6_CCU is not set
CONFIG_SUN50I_H616_CCU=m
# CONFIG_SUN50I_H6_R_CCU is not set
# CONFIG_SUN4I_A10_CCU is not set
# CONFIG_SUN5I_CCU is not set
CONFIG_SUN6I_A31_CCU=y
# CONFIG_SUN6I_RTC_CCU is not set
CONFIG_SUN8I_A23_CCU=y
# CONFIG_SUN8I_A33_CCU is not set
CONFIG_SUN8I_A83T_CCU=y
CONFIG_SUN8I_H3_CCU=m
# CONFIG_SUN8I_V3S_CCU is not set
# CONFIG_SUN8I_DE2_CCU is not set
# CONFIG_SUN8I_R40_CCU is not set
CONFIG_SUN9I_A80_CCU=m
CONFIG_SUN8I_R_CCU=m
CONFIG_COMMON_CLK_TI_ADPLL=y
CONFIG_CLK_UNIPHIER=y
# CONFIG_COMMON_CLK_VISCONTI is not set
# CONFIG_CLK_LGM_CGU is not set
CONFIG_XILINX_VCU=m
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
CONFIG_COMMON_CLK_ZYNQMP=y
CONFIG_CLK_KUNIT_TEST=m
CONFIG_CLK_GATE_KUNIT_TEST=m
# CONFIG_HWSPINLOCK is not set
#
# Clock Source drivers
#
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_CLKSRC_MMIO=y
CONFIG_BCM2835_TIMER=y
CONFIG_BCM_KONA_TIMER=y
# CONFIG_DAVINCI_TIMER is not set
# CONFIG_DIGICOLOR_TIMER is not set
CONFIG_OMAP_DM_TIMER=y
CONFIG_DW_APB_TIMER=y
CONFIG_DW_APB_TIMER_OF=y
# CONFIG_FTTMR010_TIMER is not set
# CONFIG_IXP4XX_TIMER is not set
CONFIG_ROCKCHIP_TIMER=y
# CONFIG_MESON6_TIMER is not set
CONFIG_OWL_TIMER=y
# CONFIG_RDA_TIMER is not set
CONFIG_SUN4I_TIMER=y
CONFIG_SUN5I_HSTIMER=y
CONFIG_TEGRA_TIMER=y
CONFIG_TEGRA186_TIMER=y
CONFIG_VT8500_TIMER=y
CONFIG_NPCM7XX_TIMER=y
# CONFIG_CADENCE_TTC_TIMER is not set
CONFIG_ASM9260_TIMER=y
CONFIG_CLKSRC_DBX500_PRCMU=y
# CONFIG_CLPS711X_TIMER is not set
# CONFIG_MXS_TIMER is not set
CONFIG_NSPIRE_TIMER=y
# CONFIG_KEYSTONE_TIMER is not set
CONFIG_INTEGRATOR_AP_TIMER=y
# CONFIG_CLKSRC_PISTACHIO is not set
# CONFIG_CLKSRC_TI_32K is not set
CONFIG_CLKSRC_STM32_LP=y
# CONFIG_CLKSRC_MPS2 is not set
# CONFIG_ARC_TIMERS is not set
CONFIG_ARM_ARCH_TIMER=y
# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
# CONFIG_FSL_ERRATUM_A008585 is not set
CONFIG_HISILICON_ERRATUM_161010101=y
CONFIG_ARM64_ERRATUM_858921=y
CONFIG_ARM_TIMER_SP804=y
CONFIG_ARMV7M_SYSTICK=y
CONFIG_ATMEL_PIT=y
CONFIG_ATMEL_ST=y
CONFIG_CLKSRC_EXYNOS_MCT=y
CONFIG_CLKSRC_SAMSUNG_PWM=y
CONFIG_FSL_FTM_TIMER=y
CONFIG_OXNAS_RPS_TIMER=y
CONFIG_SYS_SUPPORTS_SH_CMT=y
CONFIG_MTK_TIMER=y
CONFIG_SPRD_TIMER=y
CONFIG_SYS_SUPPORTS_SH_TMU=y
# CONFIG_CLKSRC_JCORE_PIT is not set
# CONFIG_SH_TIMER_CMT is not set
CONFIG_SH_TIMER_MTU2=y
# CONFIG_RENESAS_OSTM is not set
CONFIG_SH_TIMER_TMU=y
CONFIG_EM_TIMER_STI=y
# CONFIG_CLKSRC_VERSATILE is not set
CONFIG_CLKSRC_PXA=y
CONFIG_CLKSRC_IMX_GPT=y
# CONFIG_CLKSRC_IMX_TPM is not set
# CONFIG_TIMER_IMX_SYS_CTR is not set
# CONFIG_CLKSRC_ST_LPC is not set
# CONFIG_GXP_TIMER is not set
# CONFIG_MSC313E_TIMER is not set
CONFIG_INGENIC_TIMER=y
# CONFIG_INGENIC_SYSOST is not set
CONFIG_INGENIC_OST=y
# CONFIG_MICROCHIP_PIT64B is not set
# end of Clock Source drivers
CONFIG_MAILBOX=y
# CONFIG_APPLE_MAILBOX is not set
# CONFIG_ARM_MHU is not set
# CONFIG_ARM_MHU_V2 is not set
CONFIG_IMX_MBOX=y
# CONFIG_PLATFORM_MHU is not set
CONFIG_PL320_MBOX=y
CONFIG_ARMADA_37XX_RWTM_MBOX=y
CONFIG_OMAP2PLUS_MBOX=m
CONFIG_OMAP_MBOX_KFIFO_SIZE=256
# CONFIG_ROCKCHIP_MBOX is not set
CONFIG_ALTERA_MBOX=m
CONFIG_TI_MESSAGE_MANAGER=y
# CONFIG_HI3660_MBOX is not set
CONFIG_HI6220_MBOX=y
CONFIG_MAILBOX_TEST=m
CONFIG_POLARFIRE_SOC_MAILBOX=m
CONFIG_QCOM_APCS_IPC=y
# CONFIG_XGENE_SLIMPRO_MBOX is not set
CONFIG_BCM_PDC_MBOX=m
CONFIG_BCM_FLEXRM_MBOX=y
# CONFIG_STM32_IPCC is not set
CONFIG_MTK_ADSP_MBOX=m
CONFIG_MTK_CMDQ_MBOX=m
CONFIG_ZYNQMP_IPI_MBOX=y
CONFIG_SUN6I_MSGBOX=y
CONFIG_SPRD_MBOX=y
# CONFIG_QCOM_IPCC is not set
CONFIG_IOMMU_IOVA=y
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y
#
# Generic IOMMU Pagetable Support
#
CONFIG_IOMMU_IO_PGTABLE=y
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
CONFIG_IOMMU_IO_PGTABLE_DART=y
# end of Generic IOMMU Pagetable Support
# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
CONFIG_OF_IOMMU=y
CONFIG_IOMMU_DMA=y
CONFIG_OMAP_IOMMU=y
# CONFIG_OMAP_IOMMU_DEBUG is not set
CONFIG_ROCKCHIP_IOMMU=y
# CONFIG_SUN50I_IOMMU is not set
CONFIG_EXYNOS_IOMMU=y
# CONFIG_EXYNOS_IOMMU_DEBUG is not set
# CONFIG_IPMMU_VMSA is not set
CONFIG_APPLE_DART=y
CONFIG_ARM_SMMU=m
# CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT is not set
CONFIG_ARM_SMMU_V3=y
# CONFIG_ARM_SMMU_V3_SVA is not set
CONFIG_S390_CCW_IOMMU=y
# CONFIG_S390_AP_IOMMU is not set
# CONFIG_MTK_IOMMU is not set
# CONFIG_QCOM_IOMMU is not set
CONFIG_VIRTIO_IOMMU=m
# CONFIG_SPRD_IOMMU is not set
#
# Remoteproc drivers
#
# CONFIG_REMOTEPROC is not set
# end of Remoteproc drivers
#
# Rpmsg drivers
#
CONFIG_RPMSG=m
CONFIG_RPMSG_CTRL=m
CONFIG_RPMSG_NS=m
CONFIG_RPMSG_QCOM_GLINK=m
CONFIG_RPMSG_QCOM_GLINK_RPM=m
# CONFIG_RPMSG_VIRTIO is not set
# end of Rpmsg drivers
# CONFIG_SOUNDWIRE is not set
#
# SOC (System On Chip) specific Drivers
#
# CONFIG_OWL_PM_DOMAINS is not set
#
# Amlogic SoC drivers
#
CONFIG_MESON_CANVAS=y
# CONFIG_MESON_CLK_MEASURE is not set
CONFIG_MESON_GX_SOCINFO=y
CONFIG_MESON_GX_PM_DOMAINS=y
CONFIG_MESON_EE_PM_DOMAINS=m
CONFIG_MESON_MX_SOCINFO=y
# end of Amlogic SoC drivers
#
# Apple SoC drivers
#
CONFIG_APPLE_PMGR_PWRSTATE=y
CONFIG_APPLE_RTKIT=m
CONFIG_APPLE_SART=y
# end of Apple SoC drivers
#
# ASPEED SoC drivers
#
CONFIG_ASPEED_LPC_CTRL=y
CONFIG_ASPEED_LPC_SNOOP=y
# CONFIG_ASPEED_UART_ROUTING is not set
CONFIG_ASPEED_P2A_CTRL=m
CONFIG_ASPEED_SOCINFO=y
# end of ASPEED SoC drivers
CONFIG_AT91_SOC_ID=y
CONFIG_AT91_SOC_SFR=m
#
# Broadcom SoC drivers
#
CONFIG_BCM2835_POWER=y
# CONFIG_SOC_BCM63XX is not set
CONFIG_SOC_BRCMSTB=y
CONFIG_BCM_PMB=y
# end of Broadcom SoC drivers
#
# NXP/Freescale QorIQ SoC drivers
#
# CONFIG_QUICC_ENGINE is not set
# CONFIG_DPAA2_CONSOLE is not set
# end of NXP/Freescale QorIQ SoC drivers
#
# fujitsu SoC drivers
#
# end of fujitsu SoC drivers
#
# i.MX SoC drivers
#
# CONFIG_IMX_GPCV2_PM_DOMAINS is not set
CONFIG_SOC_IMX8M=y
CONFIG_SOC_IMX9=m
# end of i.MX SoC drivers
#
# IXP4xx SoC drivers
#
CONFIG_IXP4XX_QMGR=y
CONFIG_IXP4XX_NPE=y
# end of IXP4xx SoC drivers
#
# Enable LiteX SoC Builder specific drivers
#
CONFIG_LITEX=y
CONFIG_LITEX_SOC_CONTROLLER=y
# end of Enable LiteX SoC Builder specific drivers
#
# MediaTek SoC drivers
#
# CONFIG_MTK_CMDQ is not set
CONFIG_MTK_DEVAPC=m
CONFIG_MTK_INFRACFG=y
CONFIG_MTK_PMIC_WRAP=m
# CONFIG_MTK_SCPSYS is not set
CONFIG_MTK_SCPSYS_PM_DOMAINS=y
CONFIG_MTK_MMSYS=y
CONFIG_MTK_SVS=m
# end of MediaTek SoC drivers
CONFIG_POLARFIRE_SOC_SYS_CTRL=m
#
# Qualcomm SoC drivers
#
# CONFIG_QCOM_AOSS_QMP is not set
CONFIG_QCOM_COMMAND_DB=y
# CONFIG_QCOM_GENI_SE is not set
CONFIG_QCOM_GSBI=y
# CONFIG_QCOM_LLCC is not set
CONFIG_QCOM_RPMH=m
# CONFIG_QCOM_RPMHPD is not set
CONFIG_QCOM_RPMPD=m
CONFIG_QCOM_SMD_RPM=m
# CONFIG_QCOM_SPM is not set
CONFIG_QCOM_WCNSS_CTRL=m
# CONFIG_QCOM_ICC_BWMON is not set
# end of Qualcomm SoC drivers
CONFIG_SOC_RENESAS=y
CONFIG_ARCH_RCAR_GEN3=y
CONFIG_ARCH_RZG2L=y
CONFIG_ARCH_R8A77995=y
# CONFIG_ARCH_R8A77990 is not set
# CONFIG_ARCH_R8A77950 is not set
CONFIG_ARCH_R8A77951=y
# CONFIG_ARCH_R8A77965 is not set
CONFIG_ARCH_R8A77960=y
# CONFIG_ARCH_R8A77961 is not set
# CONFIG_ARCH_R8A779F0 is not set
# CONFIG_ARCH_R8A77980 is not set
CONFIG_ARCH_R8A77970=y
CONFIG_ARCH_R8A779A0=y
# CONFIG_ARCH_R8A779G0 is not set
# CONFIG_ARCH_R8A774C0 is not set
CONFIG_ARCH_R8A774E1=y
CONFIG_ARCH_R8A774A1=y
# CONFIG_ARCH_R8A774B1 is not set
# CONFIG_ARCH_R9A07G043 is not set
CONFIG_ARCH_R9A07G044=y
# CONFIG_ARCH_R9A07G054 is not set
CONFIG_ARCH_R9A09G011=y
CONFIG_RST_RCAR=y
CONFIG_SYSC_RCAR=y
CONFIG_SYSC_RCAR_GEN4=y
CONFIG_SYSC_R8A77995=y
CONFIG_SYSC_R8A7794=y
# CONFIG_SYSC_R8A77990 is not set
# CONFIG_SYSC_R8A7779 is not set
CONFIG_SYSC_R8A7790=y
CONFIG_SYSC_R8A7795=y
# CONFIG_SYSC_R8A7791 is not set
CONFIG_SYSC_R8A77965=y
CONFIG_SYSC_R8A77960=y
CONFIG_SYSC_R8A77961=y
# CONFIG_SYSC_R8A779F0 is not set
CONFIG_SYSC_R8A7792=y
# CONFIG_SYSC_R8A77980 is not set
CONFIG_SYSC_R8A77970=y
CONFIG_SYSC_R8A779A0=y
# CONFIG_SYSC_R8A779G0 is not set
CONFIG_SYSC_RMOBILE=y
CONFIG_SYSC_R8A77470=y
# CONFIG_SYSC_R8A7745 is not set
# CONFIG_SYSC_R8A7742 is not set
CONFIG_SYSC_R8A7743=y
CONFIG_SYSC_R8A774C0=y
CONFIG_SYSC_R8A774E1=y
CONFIG_SYSC_R8A774A1=y
CONFIG_SYSC_R8A774B1=y
# CONFIG_ROCKCHIP_GRF is not set
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_ROCKCHIP_PM_DOMAINS=y
CONFIG_SOC_SAMSUNG=y
# CONFIG_EXYNOS_CHIPID is not set
# CONFIG_EXYNOS_USI is not set
CONFIG_EXYNOS_PMU=y
CONFIG_EXYNOS_PMU_ARM_DRIVERS=y
CONFIG_EXYNOS_PM_DOMAINS=y
# CONFIG_EXYNOS_REGULATOR_COUPLER is not set
# CONFIG_SOC_TEGRA20_VOLTAGE_COUPLER is not set
CONFIG_SOC_TEGRA30_VOLTAGE_COUPLER=y
CONFIG_SOC_TI=y
# CONFIG_TI_SCI_PM_DOMAINS is not set
CONFIG_TI_K3_RINGACC=y
CONFIG_TI_K3_SOCINFO=y
CONFIG_TI_PRUSS=m
CONFIG_TI_SCI_INTA_MSI_DOMAIN=y
# CONFIG_UX500_SOC_ID is not set
#
# Xilinx SoC drivers
#
CONFIG_ZYNQMP_POWER=y
CONFIG_ZYNQMP_PM_DOMAINS=y
CONFIG_XLNX_EVENT_MANAGER=y
# end of Xilinx SoC drivers
# end of SOC (System On Chip) specific Drivers
CONFIG_PM_DEVFREQ=y
#
# DEVFREQ Governors
#
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
# CONFIG_DEVFREQ_GOV_USERSPACE is not set
CONFIG_DEVFREQ_GOV_PASSIVE=y
#
# DEVFREQ Drivers
#
CONFIG_ARM_EXYNOS_BUS_DEVFREQ=y
# CONFIG_ARM_IMX_BUS_DEVFREQ is not set
# CONFIG_ARM_IMX8M_DDRC_DEVFREQ is not set
CONFIG_ARM_TEGRA_DEVFREQ=y
CONFIG_ARM_MEDIATEK_CCI_DEVFREQ=m
CONFIG_ARM_RK3399_DMC_DEVFREQ=m
CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=y
CONFIG_PM_DEVFREQ_EVENT=y
# CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP is not set
CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU=y
CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=m
CONFIG_EXTCON=y
#
# Extcon Device Drivers
#
CONFIG_EXTCON_ADC_JACK=y
CONFIG_EXTCON_FSA9480=m
# CONFIG_EXTCON_GPIO is not set
CONFIG_EXTCON_MAX14577=y
CONFIG_EXTCON_MAX3355=y
# CONFIG_EXTCON_MAX77693 is not set
# CONFIG_EXTCON_MAX77843 is not set
CONFIG_EXTCON_PTN5150=m
# CONFIG_EXTCON_QCOM_SPMI_MISC is not set
# CONFIG_EXTCON_RT8973A is not set
CONFIG_EXTCON_SM5502=m
# CONFIG_EXTCON_USB_GPIO is not set
# CONFIG_EXTCON_USBC_TUSB320 is not set
CONFIG_MEMORY=y
CONFIG_DDR=y
# CONFIG_ARM_PL172_MPMC is not set
CONFIG_ATMEL_SDRAMC=y
CONFIG_ATMEL_EBI=y
# CONFIG_BRCMSTB_DPFE is not set
CONFIG_BRCMSTB_MEMC=y
# CONFIG_BT1_L2_CTL is not set
CONFIG_TI_AEMIF=y
CONFIG_TI_EMIF=m
CONFIG_OMAP_GPMC=y
CONFIG_OMAP_GPMC_DEBUG=y
CONFIG_MVEBU_DEVBUS=y
CONFIG_FSL_CORENET_CF=m
CONFIG_FSL_IFC=y
CONFIG_JZ4780_NEMC=y
CONFIG_MTK_SMI=y
CONFIG_DA8XX_DDRCTL=y
CONFIG_PL353_SMC=m
CONFIG_RENESAS_RPCIF=m
CONFIG_STM32_FMC2_EBI=y
# CONFIG_SAMSUNG_MC is not set
# CONFIG_TEGRA_MC is not set
CONFIG_IIO=y
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=m
CONFIG_IIO_BUFFER_DMA=y
CONFIG_IIO_BUFFER_DMAENGINE=y
CONFIG_IIO_BUFFER_HW_CONSUMER=y
CONFIG_IIO_KFIFO_BUF=y
CONFIG_IIO_TRIGGERED_BUFFER=y
CONFIG_IIO_CONFIGFS=y
CONFIG_IIO_TRIGGER=y
CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
# CONFIG_IIO_SW_DEVICE is not set
CONFIG_IIO_SW_TRIGGER=y
CONFIG_IIO_TRIGGERED_EVENT=m
#
# Accelerometers
#
# CONFIG_ADXL313_I2C is not set
CONFIG_ADXL345=m
CONFIG_ADXL345_I2C=m
CONFIG_ADXL355=m
CONFIG_ADXL355_I2C=m
# CONFIG_ADXL367_I2C is not set
CONFIG_ADXL372=y
CONFIG_ADXL372_I2C=y
# CONFIG_BMA400 is not set
CONFIG_BMC150_ACCEL=m
CONFIG_BMC150_ACCEL_I2C=m
CONFIG_DA280=y
# CONFIG_DA311 is not set
CONFIG_DMARD06=y
CONFIG_DMARD09=m
CONFIG_DMARD10=m
CONFIG_FXLS8962AF=y
CONFIG_FXLS8962AF_I2C=y
CONFIG_HID_SENSOR_ACCEL_3D=m
CONFIG_IIO_ST_ACCEL_3AXIS=m
CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
CONFIG_KXSD9=y
CONFIG_KXSD9_I2C=m
CONFIG_KXCJK1013=y
# CONFIG_MC3230 is not set
# CONFIG_MMA7455_I2C is not set
CONFIG_MMA7660=m
CONFIG_MMA8452=m
CONFIG_MMA9551_CORE=m
# CONFIG_MMA9551 is not set
CONFIG_MMA9553=m
CONFIG_MSA311=m
CONFIG_MXC4005=m
CONFIG_MXC6255=m
CONFIG_STK8312=m
# CONFIG_STK8BA50 is not set
# end of Accelerometers
#
# Analog to digital converters
#
# CONFIG_AD7091R5 is not set
CONFIG_AD7291=y
CONFIG_AD7606=m
CONFIG_AD7606_IFACE_PARALLEL=m
CONFIG_AD799X=m
CONFIG_ADI_AXI_ADC=y
# CONFIG_ASPEED_ADC is not set
CONFIG_AT91_ADC=y
CONFIG_AT91_SAMA5D2_ADC=m
CONFIG_BCM_IPROC_ADC=m
CONFIG_BERLIN2_ADC=y
CONFIG_CC10001_ADC=y
CONFIG_DLN2_ADC=m
# CONFIG_ENVELOPE_DETECTOR is not set
# CONFIG_EXYNOS_ADC is not set
CONFIG_MXS_LRADC_ADC=y
# CONFIG_FSL_MX25_ADC is not set
CONFIG_HX711=m
# CONFIG_INA2XX_ADC is not set
CONFIG_INGENIC_ADC=y
CONFIG_IMX7D_ADC=m
CONFIG_IMX8QXP_ADC=y
CONFIG_LPC18XX_ADC=y
# CONFIG_LPC32XX_ADC is not set
# CONFIG_LTC2471 is not set
CONFIG_LTC2485=y
CONFIG_LTC2497=m
CONFIG_MAX1363=m
# CONFIG_MAX9611 is not set
# CONFIG_MCP3422 is not set
CONFIG_MEDIATEK_MT6360_ADC=m
CONFIG_MEDIATEK_MT6577_AUXADC=y
CONFIG_MEN_Z188_ADC=m
CONFIG_MESON_SARADC=m
CONFIG_MP2629_ADC=y
CONFIG_NAU7802=m
CONFIG_NPCM_ADC=y
CONFIG_QCOM_SPMI_IADC=y
# CONFIG_QCOM_SPMI_VADC is not set
# CONFIG_QCOM_SPMI_ADC5 is not set
CONFIG_RCAR_GYRO_ADC=y
CONFIG_ROCKCHIP_SARADC=m
CONFIG_RICHTEK_RTQ6056=m
# CONFIG_RZG2L_ADC is not set
CONFIG_SC27XX_ADC=y
CONFIG_SPEAR_ADC=y
# CONFIG_SD_ADC_MODULATOR is not set
CONFIG_STM32_ADC_CORE=m
# CONFIG_STM32_ADC is not set
CONFIG_STM32_DFSDM_CORE=y
CONFIG_STM32_DFSDM_ADC=y
CONFIG_STMPE_ADC=m
CONFIG_TI_ADC081C=m
CONFIG_TI_ADS1015=m
CONFIG_TI_AM335X_ADC=m
CONFIG_TWL4030_MADC=m
CONFIG_TWL6030_GPADC=y
CONFIG_VF610_ADC=m
CONFIG_VIPERBOARD_ADC=m
CONFIG_XILINX_XADC=y
# CONFIG_XILINX_AMS is not set
# end of Analog to digital converters
#
# Analog to digital and digital to analog converters
#
# end of Analog to digital and digital to analog converters
#
# Analog Front Ends
#
CONFIG_IIO_RESCALE=y
# end of Analog Front Ends
#
# Amplifiers
#
# CONFIG_HMC425 is not set
# end of Amplifiers
#
# Capacitance to digital converters
#
# CONFIG_AD7150 is not set
# CONFIG_AD7746 is not set
# end of Capacitance to digital converters
#
# Chemical Sensors
#
# CONFIG_ATLAS_PH_SENSOR is not set
# CONFIG_ATLAS_EZO_SENSOR is not set
CONFIG_BME680=m
CONFIG_BME680_I2C=m
# CONFIG_CCS811 is not set
CONFIG_IAQCORE=m
CONFIG_SCD30_CORE=y
# CONFIG_SCD30_I2C is not set
# CONFIG_SCD4X is not set
CONFIG_SENSIRION_SGP30=m
# CONFIG_SENSIRION_SGP40 is not set
# CONFIG_SPS30_I2C is not set
CONFIG_SENSEAIR_SUNRISE_CO2=m
CONFIG_VZ89X=y
# end of Chemical Sensors
#
# Hid Sensor IIO Common
#
CONFIG_HID_SENSOR_IIO_COMMON=m
CONFIG_HID_SENSOR_IIO_TRIGGER=m
# end of Hid Sensor IIO Common
CONFIG_IIO_MS_SENSORS_I2C=m
#
# IIO SCMI Sensors
#
CONFIG_IIO_SCMI=m
# end of IIO SCMI Sensors
#
# SSP Sensor Common
#
# end of SSP Sensor Common
CONFIG_IIO_ST_SENSORS_I2C=y
CONFIG_IIO_ST_SENSORS_CORE=y
#
# Digital to analog converters
#
CONFIG_AD5064=y
# CONFIG_AD5380 is not set
CONFIG_AD5446=m
# CONFIG_AD5593R is not set
CONFIG_AD5686=m
CONFIG_AD5696_I2C=m
CONFIG_DPOT_DAC=m
# CONFIG_DS4424 is not set
CONFIG_LPC18XX_DAC=m
CONFIG_M62332=y
CONFIG_MAX517=m
# CONFIG_MAX5821 is not set
CONFIG_MCP4725=y
CONFIG_STM32_DAC=y
CONFIG_STM32_DAC_CORE=y
CONFIG_TI_DAC5571=y
CONFIG_VF610_DAC=y
# end of Digital to analog converters
#
# IIO dummy driver
#
# end of IIO dummy driver
#
# Filters
#
# end of Filters
#
# Frequency Synthesizers DDS/PLL
#
#
# Clock Generator/Distribution
#
# end of Clock Generator/Distribution
#
# Phase-Locked Loop (PLL) frequency synthesizers
#
# end of Phase-Locked Loop (PLL) frequency synthesizers
# end of Frequency Synthesizers DDS/PLL
#
# Digital gyroscope sensors
#
CONFIG_BMG160=m
CONFIG_BMG160_I2C=m
CONFIG_FXAS21002C=m
CONFIG_FXAS21002C_I2C=m
# CONFIG_HID_SENSOR_GYRO_3D is not set
# CONFIG_MPU3050_I2C is not set
CONFIG_IIO_ST_GYRO_3AXIS=y
CONFIG_IIO_ST_GYRO_I2C_3AXIS=y
CONFIG_ITG3200=m
# end of Digital gyroscope sensors
#
# Health Sensors
#
#
# Heart Rate Monitors
#
CONFIG_AFE4404=y
# CONFIG_MAX30100 is not set
# CONFIG_MAX30102 is not set
# end of Heart Rate Monitors
# end of Health Sensors
#
# Humidity sensors
#
CONFIG_AM2315=m
CONFIG_DHT11=m
CONFIG_HDC100X=m
# CONFIG_HDC2010 is not set
# CONFIG_HID_SENSOR_HUMIDITY is not set
CONFIG_HTS221=y
CONFIG_HTS221_I2C=y
# CONFIG_HTU21 is not set
# CONFIG_SI7005 is not set
# CONFIG_SI7020 is not set
# end of Humidity sensors
#
# Inertial measurement units
#
# CONFIG_BMI160_I2C is not set
CONFIG_BOSCH_BNO055=y
CONFIG_BOSCH_BNO055_I2C=y
CONFIG_FXOS8700=m
CONFIG_FXOS8700_I2C=m
CONFIG_KMX61=y
CONFIG_INV_ICM42600=y
CONFIG_INV_ICM42600_I2C=y
CONFIG_INV_MPU6050_IIO=m
CONFIG_INV_MPU6050_I2C=m
CONFIG_IIO_ST_LSM6DSX=m
CONFIG_IIO_ST_LSM6DSX_I2C=m
CONFIG_IIO_ST_LSM6DSX_I3C=m
CONFIG_IIO_ST_LSM9DS0=m
CONFIG_IIO_ST_LSM9DS0_I2C=m
# end of Inertial measurement units
#
# Light sensors
#
CONFIG_ADJD_S311=m
CONFIG_ADUX1020=y
CONFIG_AL3010=m
# CONFIG_AL3320A is not set
# CONFIG_APDS9300 is not set
CONFIG_APDS9960=m
CONFIG_AS73211=m
CONFIG_BH1750=m
CONFIG_BH1780=m
CONFIG_CM32181=y
# CONFIG_CM3232 is not set
CONFIG_CM3323=y
CONFIG_CM3605=y
CONFIG_CM36651=m
CONFIG_GP2AP002=m
CONFIG_GP2AP020A00F=m
# CONFIG_IQS621_ALS is not set
# CONFIG_SENSORS_ISL29018 is not set
CONFIG_SENSORS_ISL29028=m
CONFIG_ISL29125=m
# CONFIG_HID_SENSOR_ALS is not set
# CONFIG_HID_SENSOR_PROX is not set
CONFIG_JSA1212=m
CONFIG_RPR0521=y
# CONFIG_LTR501 is not set
CONFIG_LTRF216A=y
# CONFIG_LV0104CS is not set
CONFIG_MAX44000=m
CONFIG_MAX44009=y
# CONFIG_NOA1305 is not set
CONFIG_OPT3001=m
CONFIG_PA12203001=y
# CONFIG_SI1133 is not set
CONFIG_SI1145=m
CONFIG_STK3310=y
CONFIG_ST_UVIS25=y
CONFIG_ST_UVIS25_I2C=y
CONFIG_TCS3414=y
# CONFIG_TCS3472 is not set
CONFIG_SENSORS_TSL2563=y
CONFIG_TSL2583=m
CONFIG_TSL2591=m
CONFIG_TSL2772=y
CONFIG_TSL4531=y
CONFIG_US5182D=y
CONFIG_VCNL4000=m
# CONFIG_VCNL4035 is not set
CONFIG_VEML6030=m
CONFIG_VEML6070=m
# CONFIG_VL6180 is not set
CONFIG_ZOPT2201=m
# end of Light sensors
#
# Magnetometer sensors
#
CONFIG_AK8974=y
CONFIG_AK8975=m
CONFIG_AK09911=m
CONFIG_BMC150_MAGN=m
CONFIG_BMC150_MAGN_I2C=m
# CONFIG_MAG3110 is not set
CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
# CONFIG_MMC35240 is not set
CONFIG_IIO_ST_MAGN_3AXIS=y
CONFIG_IIO_ST_MAGN_I2C_3AXIS=y
CONFIG_SENSORS_HMC5843=m
CONFIG_SENSORS_HMC5843_I2C=m
CONFIG_SENSORS_RM3100=m
CONFIG_SENSORS_RM3100_I2C=m
CONFIG_YAMAHA_YAS530=y
# end of Magnetometer sensors
#
# Multiplexers
#
# CONFIG_IIO_MUX is not set
# end of Multiplexers
#
# Inclinometer sensors
#
CONFIG_HID_SENSOR_INCLINOMETER_3D=m
# CONFIG_HID_SENSOR_DEVICE_ROTATION is not set
# end of Inclinometer sensors
# CONFIG_IIO_RESCALE_KUNIT_TEST is not set
CONFIG_IIO_FORMAT_KUNIT_TEST=m
#
# Triggers - standalone
#
CONFIG_IIO_HRTIMER_TRIGGER=y
CONFIG_IIO_INTERRUPT_TRIGGER=m
CONFIG_IIO_STM32_LPTIMER_TRIGGER=y
CONFIG_IIO_STM32_TIMER_TRIGGER=y
# CONFIG_IIO_TIGHTLOOP_TRIGGER is not set
CONFIG_IIO_SYSFS_TRIGGER=m
# end of Triggers - standalone
#
# Linear and angular position sensors
#
CONFIG_IQS624_POS=m
CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m
# end of Linear and angular position sensors
#
# Digital potentiometers
#
# CONFIG_AD5110 is not set
# CONFIG_AD5272 is not set
CONFIG_DS1803=y
# CONFIG_MAX5432 is not set
CONFIG_MCP4018=y
# CONFIG_MCP4531 is not set
CONFIG_TPL0102=y
# end of Digital potentiometers
#
# Digital potentiostats
#
# CONFIG_LMP91000 is not set
# end of Digital potentiostats
#
# Pressure sensors
#
# CONFIG_ABP060MG is not set
CONFIG_BMP280=m
CONFIG_BMP280_I2C=m
# CONFIG_DLHL60D is not set
# CONFIG_DPS310 is not set
CONFIG_HID_SENSOR_PRESS=m
CONFIG_HP03=y
# CONFIG_ICP10100 is not set
CONFIG_MPL115=m
CONFIG_MPL115_I2C=m
CONFIG_MPL3115=m
# CONFIG_MS5611 is not set
# CONFIG_MS5637 is not set
CONFIG_IIO_ST_PRESS=m
CONFIG_IIO_ST_PRESS_I2C=m
# CONFIG_T5403 is not set
CONFIG_HP206C=y
CONFIG_ZPA2326=m
CONFIG_ZPA2326_I2C=m
# end of Pressure sensors
#
# Lightning sensors
#
# end of Lightning sensors
#
# Proximity and distance sensors
#
CONFIG_ISL29501=m
CONFIG_LIDAR_LITE_V2=y
CONFIG_MB1232=y
CONFIG_PING=m
# CONFIG_RFD77402 is not set
CONFIG_SRF04=m
CONFIG_SX_COMMON=m
# CONFIG_SX9310 is not set
CONFIG_SX9324=m
# CONFIG_SX9360 is not set
CONFIG_SX9500=m
CONFIG_SRF08=y
CONFIG_VCNL3020=m
# CONFIG_VL53L0X_I2C is not set
# end of Proximity and distance sensors
#
# Resolver to digital converters
#
# end of Resolver to digital converters
#
# Temperature sensors
#
# CONFIG_IQS620AT_TEMP is not set
CONFIG_HID_SENSOR_TEMP=m
CONFIG_MLX90614=m
CONFIG_MLX90632=m
# CONFIG_TMP006 is not set
# CONFIG_TMP007 is not set
CONFIG_TMP117=y
CONFIG_TSYS01=m
# CONFIG_TSYS02D is not set
# end of Temperature sensors
CONFIG_PWM=y
CONFIG_PWM_SYSFS=y
CONFIG_PWM_DEBUG=y
CONFIG_PWM_ATMEL=m
CONFIG_PWM_ATMEL_HLCDC_PWM=y
CONFIG_PWM_ATMEL_TCB=m
# CONFIG_PWM_BCM_IPROC is not set
CONFIG_PWM_BCM_KONA=y
CONFIG_PWM_BCM2835=m
# CONFIG_PWM_BERLIN is not set
CONFIG_PWM_BRCMSTB=m
# CONFIG_PWM_CLK is not set
# CONFIG_PWM_CLPS711X is not set
CONFIG_PWM_EP93XX=y
# CONFIG_PWM_FSL_FTM is not set
CONFIG_PWM_HIBVT=m
CONFIG_PWM_IMG=y
CONFIG_PWM_IMX1=y
CONFIG_PWM_IMX27=y
CONFIG_PWM_IMX_TPM=m
# CONFIG_PWM_INTEL_LGM is not set
# CONFIG_PWM_IQS620A is not set
# CONFIG_PWM_JZ4740 is not set
CONFIG_PWM_KEEMBAY=m
CONFIG_PWM_LP3943=m
# CONFIG_PWM_LPC18XX_SCT is not set
# CONFIG_PWM_LPC32XX is not set
# CONFIG_PWM_LPSS_PLATFORM is not set
CONFIG_PWM_MESON=y
CONFIG_PWM_MTK_DISP=y
CONFIG_PWM_MEDIATEK=y
CONFIG_PWM_MXS=y
CONFIG_PWM_OMAP_DMTIMER=m
CONFIG_PWM_PCA9685=m
CONFIG_PWM_PXA=m
# CONFIG_PWM_RASPBERRYPI_POE is not set
CONFIG_PWM_RCAR=y
CONFIG_PWM_RENESAS_TPU=m
# CONFIG_PWM_ROCKCHIP is not set
CONFIG_PWM_SAMSUNG=y
CONFIG_PWM_SIFIVE=y
CONFIG_PWM_SL28CPLD=m
CONFIG_PWM_SPEAR=y
CONFIG_PWM_SPRD=y
CONFIG_PWM_STI=m
# CONFIG_PWM_STM32 is not set
CONFIG_PWM_STM32_LP=m
# CONFIG_PWM_STMPE is not set
CONFIG_PWM_SUN4I=y
# CONFIG_PWM_SUNPLUS is not set
CONFIG_PWM_TEGRA=m
CONFIG_PWM_TIECAP=m
CONFIG_PWM_TIEHRPWM=m
CONFIG_PWM_TWL=m
CONFIG_PWM_TWL_LED=m
# CONFIG_PWM_VISCONTI is not set
CONFIG_PWM_VT8500=y
CONFIG_PWM_XILINX=m
#
# IRQ chip support
#
CONFIG_IRQCHIP=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_MAX_NR=1
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
# CONFIG_AL_FIC is not set
CONFIG_JCORE_AIC=y
# CONFIG_RENESAS_INTC_IRQPIN is not set
CONFIG_RENESAS_IRQC=y
CONFIG_RENESAS_RZA1_IRQC=y
CONFIG_RENESAS_RZG2L_IRQC=y
CONFIG_SL28CPLD_INTC=y
CONFIG_TS4800_IRQ=y
# CONFIG_XILINX_INTC is not set
CONFIG_INGENIC_TCU_IRQ=y
CONFIG_PARTITION_PERCPU=y
CONFIG_IRQ_UNIPHIER_AIDET=y
# CONFIG_MESON_IRQ_GPIO is not set
CONFIG_IMX_IRQSTEER=y
# CONFIG_IMX_INTMUX is not set
# CONFIG_IMX_MU_MSI is not set
CONFIG_TI_SCI_INTR_IRQCHIP=y
CONFIG_TI_SCI_INTA_IRQCHIP=y
CONFIG_TI_PRUSS_INTC=m
CONFIG_EXYNOS_IRQ_COMBINER=y
# CONFIG_MST_IRQ is not set
CONFIG_APPLE_AIC=y
# CONFIG_MCHP_EIC is not set
CONFIG_SUNPLUS_SP7021_INTC=y
# end of IRQ chip support
CONFIG_IPACK_BUS=y
CONFIG_SERIAL_IPOCTAL=y
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_RESET_CONTROLLER=y
# CONFIG_RESET_A10SR is not set
CONFIG_RESET_ATH79=y
CONFIG_RESET_AXS10X=y
CONFIG_RESET_BCM6345=y
CONFIG_RESET_BERLIN=y
CONFIG_RESET_BRCMSTB=m
CONFIG_RESET_BRCMSTB_RESCAL=m
CONFIG_RESET_HSDK=y
CONFIG_RESET_IMX7=y
# CONFIG_RESET_INTEL_GW is not set
CONFIG_RESET_K210=y
# CONFIG_RESET_LANTIQ is not set
# CONFIG_RESET_LPC18XX is not set
# CONFIG_RESET_MCHP_SPARX5 is not set
# CONFIG_RESET_MESON is not set
CONFIG_RESET_MESON_AUDIO_ARB=m
CONFIG_RESET_NPCM=y
# CONFIG_RESET_PISTACHIO is not set
CONFIG_RESET_POLARFIRE_SOC=y
CONFIG_RESET_QCOM_AOSS=m
CONFIG_RESET_QCOM_PDC=y
CONFIG_RESET_RASPBERRYPI=y
CONFIG_RESET_RZG2L_USBPHY_CTRL=y
CONFIG_RESET_SCMI=m
CONFIG_RESET_SIMPLE=y
CONFIG_RESET_SOCFPGA=y
CONFIG_RESET_STARFIVE_JH7100=y
CONFIG_RESET_SUNPLUS=y
# CONFIG_RESET_SUNXI is not set
CONFIG_RESET_TI_SCI=m
CONFIG_RESET_TI_SYSCON=m
# CONFIG_RESET_TI_TPS380X is not set
CONFIG_RESET_TN48M_CPLD=m
CONFIG_RESET_UNIPHIER=y
CONFIG_RESET_UNIPHIER_GLUE=y
# CONFIG_RESET_ZYNQ is not set
CONFIG_COMMON_RESET_HI3660=m
CONFIG_COMMON_RESET_HI6220=y
#
# PHY Subsystem
#
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PHY_MIPI_DPHY=y
CONFIG_PHY_LPC18XX_USB_OTG=y
# CONFIG_PHY_PISTACHIO_USB is not set
# CONFIG_PHY_XGENE is not set
CONFIG_USB_LGM_PHY=m
CONFIG_PHY_CAN_TRANSCEIVER=y
CONFIG_PHY_SUN4I_USB=m
CONFIG_PHY_SUN6I_MIPI_DPHY=m
CONFIG_PHY_SUN9I_USB=m
CONFIG_PHY_SUN50I_USB3=m
CONFIG_PHY_MESON8_HDMI_TX=y
CONFIG_PHY_MESON8B_USB2=y
# CONFIG_PHY_MESON_GXL_USB2 is not set
CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG=m
CONFIG_PHY_MESON_G12A_USB2=y
CONFIG_PHY_MESON_G12A_USB3_PCIE=y
# CONFIG_PHY_MESON_AXG_PCIE is not set
CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=m
# CONFIG_PHY_MESON_AXG_MIPI_DPHY is not set
#
# PHY drivers for Broadcom platforms
#
CONFIG_PHY_BCM63XX_USBH=m
CONFIG_PHY_CYGNUS_PCIE=m
CONFIG_PHY_BCM_SR_USB=m
CONFIG_BCM_KONA_USB2_PHY=y
# CONFIG_PHY_BCM_NS_USB2 is not set
CONFIG_PHY_NS2_USB_DRD=m
CONFIG_PHY_BRCM_SATA=m
# CONFIG_PHY_BRCM_USB is not set
# CONFIG_PHY_BCM_SR_PCIE is not set
# end of PHY drivers for Broadcom platforms
# CONFIG_PHY_CADENCE_TORRENT is not set
CONFIG_PHY_CADENCE_DPHY=m
# CONFIG_PHY_CADENCE_DPHY_RX is not set
CONFIG_PHY_CADENCE_SIERRA=m
CONFIG_PHY_CADENCE_SALVO=m
# CONFIG_PHY_FSL_IMX8MQ_USB is not set
CONFIG_PHY_MIXEL_LVDS_PHY=y
CONFIG_PHY_MIXEL_MIPI_DPHY=y
CONFIG_PHY_FSL_IMX8M_PCIE=y
# CONFIG_PHY_FSL_LYNX_28G is not set
# CONFIG_PHY_HI6220_USB is not set
CONFIG_PHY_HI3660_USB=m
CONFIG_PHY_HI3670_USB=m
# CONFIG_PHY_HI3670_PCIE is not set
# CONFIG_PHY_HISTB_COMBPHY is not set
CONFIG_PHY_HISI_INNO_USB2=y
CONFIG_PHY_INGENIC_USB=m
CONFIG_PHY_LANTIQ_VRX200_PCIE=m
CONFIG_PHY_LANTIQ_RCU_USB2=m
CONFIG_ARMADA375_USBCLUSTER_PHY=y
CONFIG_PHY_BERLIN_SATA=m
CONFIG_PHY_BERLIN_USB=y
CONFIG_PHY_MVEBU_A3700_COMPHY=m
# CONFIG_PHY_MVEBU_A3700_UTMI is not set
CONFIG_PHY_MVEBU_A38X_COMPHY=y
# CONFIG_PHY_MVEBU_CP110_COMPHY is not set
CONFIG_PHY_MVEBU_CP110_UTMI=y
CONFIG_PHY_PXA_28NM_HSIC=y
# CONFIG_PHY_PXA_28NM_USB2 is not set
CONFIG_PHY_PXA_USB=y
# CONFIG_PHY_MMP3_USB is not set
CONFIG_PHY_MMP3_HSIC=y
CONFIG_PHY_MTK_PCIE=m
CONFIG_PHY_MTK_TPHY=m
CONFIG_PHY_MTK_UFS=m
CONFIG_PHY_MTK_XSPHY=m
CONFIG_PHY_MTK_HDMI=y
CONFIG_PHY_MTK_MIPI_DSI=y
CONFIG_PHY_MTK_DP=y
CONFIG_PHY_SPARX5_SERDES=m
CONFIG_PHY_LAN966X_SERDES=y
# CONFIG_PHY_CPCAP_USB is not set
CONFIG_PHY_MAPPHONE_MDM6600=m
CONFIG_PHY_OCELOT_SERDES=y
# CONFIG_PHY_ATH79_USB is not set
CONFIG_PHY_QCOM_EDP=m
CONFIG_PHY_QCOM_IPQ4019_USB=y
CONFIG_PHY_QCOM_PCIE2=y
CONFIG_PHY_QCOM_QMP=y
CONFIG_PHY_QCOM_QUSB2=m
# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
# CONFIG_PHY_QCOM_USB_HS_28NM is not set
# CONFIG_PHY_QCOM_USB_SS is not set
CONFIG_PHY_QCOM_IPQ806X_USB=m
CONFIG_PHY_MT7621_PCI=y
CONFIG_PHY_RALINK_USB=y
CONFIG_PHY_RCAR_GEN2=m
CONFIG_PHY_RCAR_GEN3_PCIE=y
# CONFIG_PHY_RCAR_GEN3_USB2 is not set
# CONFIG_PHY_RCAR_GEN3_USB3 is not set
# CONFIG_PHY_ROCKCHIP_DP is not set
CONFIG_PHY_ROCKCHIP_DPHY_RX0=y
# CONFIG_PHY_ROCKCHIP_EMMC is not set
# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
# CONFIG_PHY_ROCKCHIP_INNO_USB2 is not set
# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=m
CONFIG_PHY_ROCKCHIP_PCIE=m
# CONFIG_PHY_ROCKCHIP_SNPS_PCIE3 is not set
# CONFIG_PHY_ROCKCHIP_TYPEC is not set
CONFIG_PHY_ROCKCHIP_USB=m
CONFIG_PHY_EXYNOS_DP_VIDEO=m
CONFIG_PHY_EXYNOS_MIPI_VIDEO=y
CONFIG_PHY_EXYNOS_PCIE=y
# CONFIG_PHY_SAMSUNG_UFS is not set
# CONFIG_PHY_SAMSUNG_USB2 is not set
CONFIG_PHY_UNIPHIER_USB2=m
# CONFIG_PHY_UNIPHIER_USB3 is not set
# CONFIG_PHY_UNIPHIER_PCIE is not set
# CONFIG_PHY_UNIPHIER_AHCI is not set
CONFIG_PHY_ST_SPEAR1310_MIPHY=m
# CONFIG_PHY_ST_SPEAR1340_MIPHY is not set
# CONFIG_PHY_STIH407_USB is not set
CONFIG_PHY_STM32_USBPHYC=y
CONFIG_PHY_SUNPLUS_USB=y
CONFIG_PHY_TEGRA194_P2U=y
CONFIG_PHY_DA8XX_USB=m
CONFIG_PHY_DM816X_USB=y
CONFIG_PHY_AM654_SERDES=m
CONFIG_PHY_J721E_WIZ=m
CONFIG_OMAP_CONTROL_PHY=y
# CONFIG_OMAP_USB2 is not set
# CONFIG_TI_PIPE3 is not set
CONFIG_PHY_INTEL_KEEMBAY_EMMC=y
CONFIG_PHY_INTEL_KEEMBAY_USB=y
# CONFIG_PHY_INTEL_LGM_COMBO is not set
# CONFIG_PHY_INTEL_LGM_EMMC is not set
CONFIG_PHY_INTEL_THUNDERBAY_EMMC=y
# CONFIG_PHY_XILINX_ZYNQMP is not set
# end of PHY Subsystem
# CONFIG_POWERCAP is not set
CONFIG_MCB=m
# CONFIG_MCB_LPC is not set
#
# Performance monitor support
#
CONFIG_ARM_CCI_PMU=y
# CONFIG_ARM_CCI400_PMU is not set
CONFIG_ARM_CCI5xx_PMU=y
CONFIG_ARM_CCN=m
# CONFIG_ARM_CMN is not set
CONFIG_ARM_PMU=y
# CONFIG_ARM_SMMU_V3_PMU is not set
CONFIG_ARM_DSU_PMU=m
CONFIG_FSL_IMX8_DDR_PMU=y
CONFIG_XGENE_PMU=y
CONFIG_ARM_SPE_PMU=y
CONFIG_ARM_DMC620_PMU=m
CONFIG_MARVELL_CN10K_TAD_PMU=m
# CONFIG_APPLE_M1_CPU_PMU is not set
# CONFIG_ALIBABA_UNCORE_DRW_PMU is not set
CONFIG_MARVELL_CN10K_DDR_PMU=y
# end of Performance monitor support
CONFIG_RAS=y
#
# Android
#
# CONFIG_ANDROID_BINDER_IPC is not set
# end of Android
CONFIG_DAX=y
# CONFIG_DEV_DAX is not set
CONFIG_NVMEM=y
CONFIG_NVMEM_SYSFS=y
CONFIG_NVMEM_APPLE_EFUSES=m
# CONFIG_NVMEM_BCM_OCOTP is not set
CONFIG_NVMEM_BRCM_NVRAM=y
CONFIG_NVMEM_IMX_IIM=y
CONFIG_NVMEM_IMX_OCOTP=m
CONFIG_NVMEM_IMX_OCOTP_SCU=y
CONFIG_NVMEM_JZ4780_EFUSE=y
CONFIG_NVMEM_LAN9662_OTPC=y
CONFIG_NVMEM_LAYERSCAPE_SFP=y
CONFIG_NVMEM_LPC18XX_EEPROM=m
CONFIG_NVMEM_LPC18XX_OTP=m
CONFIG_NVMEM_MESON_MX_EFUSE=m
CONFIG_NVMEM_MICROCHIP_OTPC=y
CONFIG_NVMEM_MTK_EFUSE=m
CONFIG_NVMEM_MXS_OCOTP=y
# CONFIG_NVMEM_NINTENDO_OTP is not set
CONFIG_NVMEM_QCOM_QFPROM=m
# CONFIG_NVMEM_RMEM is not set
CONFIG_NVMEM_ROCKCHIP_EFUSE=m
# CONFIG_NVMEM_ROCKCHIP_OTP is not set
CONFIG_NVMEM_SC27XX_EFUSE=m
# CONFIG_NVMEM_SNVS_LPGPR is not set
CONFIG_NVMEM_SPMI_SDAM=m
CONFIG_NVMEM_SPRD_EFUSE=y
CONFIG_NVMEM_STM32_ROMEM=m
CONFIG_NVMEM_SUNPLUS_OCOTP=y
CONFIG_NVMEM_U_BOOT_ENV=m
# CONFIG_NVMEM_UNIPHIER_EFUSE is not set
# CONFIG_NVMEM_VF610_OCOTP is not set
# CONFIG_NVMEM_ZYNQMP is not set
#
# HW tracing support
#
CONFIG_STM=m
CONFIG_STM_PROTO_BASIC=m
# CONFIG_STM_PROTO_SYS_T is not set
CONFIG_STM_DUMMY=m
CONFIG_STM_SOURCE_CONSOLE=m
CONFIG_STM_SOURCE_HEARTBEAT=m
CONFIG_INTEL_TH=m
# CONFIG_INTEL_TH_GTH is not set
CONFIG_INTEL_TH_STH=m
CONFIG_INTEL_TH_MSU=m
# CONFIG_INTEL_TH_PTI is not set
# CONFIG_INTEL_TH_DEBUG is not set
# end of HW tracing support
# CONFIG_FPGA is not set
# CONFIG_FSI is not set
# CONFIG_TEE is not set
CONFIG_MULTIPLEXER=y
#
# Multiplexer drivers
#
# CONFIG_MUX_ADG792A is not set
CONFIG_MUX_GPIO=m
CONFIG_MUX_MMIO=y
# end of Multiplexer drivers
CONFIG_PM_OPP=y
CONFIG_SIOX=y
CONFIG_SIOX_BUS_GPIO=m
CONFIG_SLIMBUS=y
CONFIG_SLIM_QCOM_CTRL=m
CONFIG_INTERCONNECT=y
CONFIG_INTERCONNECT_IMX=m
# CONFIG_INTERCONNECT_IMX8MM is not set
# CONFIG_INTERCONNECT_IMX8MN is not set
CONFIG_INTERCONNECT_IMX8MQ=m
# CONFIG_INTERCONNECT_IMX8MP is not set
CONFIG_INTERCONNECT_QCOM_OSM_L3=y
# CONFIG_INTERCONNECT_SAMSUNG is not set
CONFIG_COUNTER=y
CONFIG_104_QUAD_8=y
CONFIG_INTERRUPT_CNT=m
# CONFIG_STM32_TIMER_CNT is not set
# CONFIG_STM32_LPTIMER_CNT is not set
# CONFIG_TI_EQEP is not set
CONFIG_FTM_QUADDEC=m
# CONFIG_MICROCHIP_TCB_CAPTURE is not set
CONFIG_TI_ECAP_CAPTURE=m
CONFIG_MOST=m
CONFIG_MOST_USB_HDM=m
CONFIG_MOST_CDEV=m
CONFIG_PECI=m
# CONFIG_PECI_CPU is not set
CONFIG_PECI_ASPEED=m
CONFIG_HTE=y
# end of Device Drivers
#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_VALIDATE_FS_PARSER=y
CONFIG_EXPORTFS=y
CONFIG_EXPORTFS_BLOCK_OPS=y
# CONFIG_FILE_LOCKING is not set
CONFIG_FS_ENCRYPTION=y
# CONFIG_FS_VERITY is not set
CONFIG_FSNOTIFY=y
# CONFIG_DNOTIFY is not set
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
CONFIG_QUOTA=y
CONFIG_PRINT_QUOTA_WARNING=y
# CONFIG_QUOTA_DEBUG is not set
CONFIG_QUOTA_TREE=y
CONFIG_QFMT_V1=y
CONFIG_QFMT_V2=y
CONFIG_QUOTACTL=y
CONFIG_AUTOFS4_FS=m
CONFIG_AUTOFS_FS=y
# CONFIG_FUSE_FS is not set
CONFIG_OVERLAY_FS=m
CONFIG_OVERLAY_FS_REDIRECT_DIR=y
CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y
# CONFIG_OVERLAY_FS_INDEX is not set
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
CONFIG_OVERLAY_FS_METACOPY=y
#
# Caches
#
# CONFIG_FSCACHE is not set
# end of Caches
#
# Pseudo filesystems
#
# CONFIG_PROC_FS is not set
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
CONFIG_TMPFS_XATTR=y
# CONFIG_TMPFS_INODE64 is not set
CONFIG_ARCH_SUPPORTS_HUGETLBFS=y
# CONFIG_HUGETLBFS is not set
CONFIG_ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y
CONFIG_MEMFD_CREATE=y
CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
CONFIG_CONFIGFS_FS=y
# end of Pseudo filesystems
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=y
# CONFIG_NLS_CODEPAGE_775 is not set
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
CONFIG_NLS_CODEPAGE_861=y
CONFIG_NLS_CODEPAGE_862=y
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
CONFIG_NLS_CODEPAGE_869=y
# CONFIG_NLS_CODEPAGE_936 is not set
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=y
CONFIG_NLS_CODEPAGE_874=m
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=y
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=y
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=y
CONFIG_NLS_KOI8_R=y
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_MAC_ROMAN is not set
CONFIG_NLS_MAC_CELTIC=y
CONFIG_NLS_MAC_CENTEURO=m
CONFIG_NLS_MAC_CROATIAN=y
# CONFIG_NLS_MAC_CYRILLIC is not set
CONFIG_NLS_MAC_GAELIC=m
# CONFIG_NLS_MAC_GREEK is not set
CONFIG_NLS_MAC_ICELAND=m
CONFIG_NLS_MAC_INUIT=y
# CONFIG_NLS_MAC_ROMANIAN is not set
CONFIG_NLS_MAC_TURKISH=m
CONFIG_NLS_UTF8=m
CONFIG_UNICODE=y
# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set
# end of File systems
#
# Security options
#
CONFIG_KEYS=y
# CONFIG_KEYS_REQUEST_CACHE is not set
CONFIG_PERSISTENT_KEYRINGS=y
# CONFIG_TRUSTED_KEYS is not set
CONFIG_ENCRYPTED_KEYS=m
CONFIG_USER_DECRYPTED_DATA=y
# CONFIG_KEY_DH_OPERATIONS is not set
CONFIG_KEY_NOTIFICATIONS=y
CONFIG_SECURITY_DMESG_RESTRICT=y
CONFIG_SECURITYFS=y
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
# CONFIG_HARDENED_USERCOPY is not set
# CONFIG_FORTIFY_SOURCE is not set
# CONFIG_STATIC_USERMODEHELPER is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,bpf"
#
# Kernel hardening options
#
#
# Memory initialization
#
CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y
CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y
CONFIG_INIT_STACK_NONE=y
# CONFIG_INIT_STACK_ALL_PATTERN is not set
# CONFIG_INIT_STACK_ALL_ZERO is not set
CONFIG_GCC_PLUGIN_STACKLEAK=y
CONFIG_STACKLEAK_TRACK_MIN_SIZE=100
CONFIG_STACKLEAK_RUNTIME_DISABLE=y
CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y
# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
CONFIG_ZERO_CALL_USED_REGS=y
# end of Memory initialization
CONFIG_RANDSTRUCT_NONE=y
# CONFIG_RANDSTRUCT_FULL is not set
# CONFIG_RANDSTRUCT_PERFORMANCE is not set
# end of Kernel hardening options
# end of Security options
CONFIG_CRYPTO=y
#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_SKCIPHER=y
CONFIG_CRYPTO_SKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=m
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_PCRYPT=m
CONFIG_CRYPTO_CRYPTD=m
CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_TEST=y
CONFIG_CRYPTO_ENGINE=y
# end of Crypto core or helper
#
# Public-key cryptography
#
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=m
CONFIG_CRYPTO_DH_RFC7919_GROUPS=y
CONFIG_CRYPTO_ECC=m
CONFIG_CRYPTO_ECDH=m
CONFIG_CRYPTO_ECDSA=m
CONFIG_CRYPTO_ECRDSA=m
CONFIG_CRYPTO_SM2=y
# CONFIG_CRYPTO_CURVE25519 is not set
# end of Public-key cryptography
#
# Block ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_AES_TI=m
CONFIG_CRYPTO_ARIA=m
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_CAMELLIA is not set
CONFIG_CRYPTO_CAST_COMMON=m
CONFIG_CRYPTO_CAST5=m
# CONFIG_CRYPTO_CAST6 is not set
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_FCRYPT=y
CONFIG_CRYPTO_SERPENT=y
CONFIG_CRYPTO_SM4=y
CONFIG_CRYPTO_SM4_GENERIC=m
# CONFIG_CRYPTO_TWOFISH is not set
# end of Block ciphers
#
# Length-preserving ciphers and modes
#
CONFIG_CRYPTO_ADIANTUM=y
CONFIG_CRYPTO_CHACHA20=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CFB=m
CONFIG_CRYPTO_CTR=y
# CONFIG_CRYPTO_CTS is not set
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_HCTR2=y
CONFIG_CRYPTO_KEYWRAP=m
# CONFIG_CRYPTO_LRW is not set
CONFIG_CRYPTO_OFB=y
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_XCTR=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_NHPOLY1305=y
# end of Length-preserving ciphers and modes
#
# AEAD (authenticated encryption with associated data) ciphers
#
CONFIG_CRYPTO_AEGIS128=m
CONFIG_CRYPTO_AEGIS128_SIMD=y
CONFIG_CRYPTO_CHACHA20POLY1305=m
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_SEQIV=m
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_ESSIV=y
# end of AEAD (authenticated encryption with associated data) ciphers
#
# Hashes, digests, and MACs
#
CONFIG_CRYPTO_BLAKE2B=m
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=y
CONFIG_CRYPTO_POLYVAL=y
CONFIG_CRYPTO_POLY1305=m
CONFIG_CRYPTO_RMD160=m
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
# CONFIG_CRYPTO_SM3_GENERIC is not set
CONFIG_CRYPTO_STREEBOG=m
CONFIG_CRYPTO_VMAC=m
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_XCBC=y
CONFIG_CRYPTO_XXHASH=m
# end of Hashes, digests, and MACs
#
# CRCs (cyclic redundancy checks)
#
CONFIG_CRYPTO_CRC32C=y
# CONFIG_CRYPTO_CRC32 is not set
CONFIG_CRYPTO_CRCT10DIF=m
CONFIG_CRYPTO_CRC64_ROCKSOFT=m
# end of CRCs (cyclic redundancy checks)
#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=m
# CONFIG_CRYPTO_842 is not set
CONFIG_CRYPTO_LZ4=y
# CONFIG_CRYPTO_LZ4HC is not set
CONFIG_CRYPTO_ZSTD=y
# end of Compression
#
# Random number generation
#
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_HASH=y
CONFIG_CRYPTO_DRBG_CTR=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
# end of Random number generation
#
# Userspace interface
#
# end of Userspace interface
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_NHPOLY1305_NEON=y
# CONFIG_CRYPTO_CHACHA20_NEON is not set
#
# Accelerated Cryptographic Algorithms for CPU (arm64)
#
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_POLY1305_NEON=y
CONFIG_CRYPTO_SHA1_ARM64_CE=m
CONFIG_CRYPTO_SHA256_ARM64=y
CONFIG_CRYPTO_SHA2_ARM64_CE=m
CONFIG_CRYPTO_SHA512_ARM64=y
CONFIG_CRYPTO_SHA512_ARM64_CE=m
# CONFIG_CRYPTO_SHA3_ARM64 is not set
CONFIG_CRYPTO_SM3_ARM64_CE=m
CONFIG_CRYPTO_POLYVAL_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64=m
CONFIG_CRYPTO_AES_ARM64_CE=m
# CONFIG_CRYPTO_AES_ARM64_CE_BLK is not set
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
CONFIG_CRYPTO_AES_ARM64_BS=y
CONFIG_CRYPTO_SM4_ARM64_CE=m
CONFIG_CRYPTO_SM4_ARM64_CE_BLK=m
CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=m
CONFIG_CRYPTO_AES_ARM64_CE_CCM=m
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
# end of Accelerated Cryptographic Algorithms for CPU (arm64)
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_DEV_ALLWINNER=y
CONFIG_CRYPTO_DEV_SUN8I_CE=m
# CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG is not set
CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y
# CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG is not set
CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y
# CONFIG_CRYPTO_DEV_SUN8I_SS is not set
CONFIG_CRYPTO_DEV_SL3516=y
# CONFIG_CRYPTO_DEV_SL3516_DEBUG is not set
CONFIG_CRYPTO_DEV_EXYNOS_RNG=m
CONFIG_CRYPTO_DEV_S5P=y
# CONFIG_CRYPTO_DEV_ATMEL_AUTHENC is not set
CONFIG_CRYPTO_DEV_ATMEL_AES=y
# CONFIG_CRYPTO_DEV_ATMEL_TDES is not set
CONFIG_CRYPTO_DEV_ATMEL_SHA=m
CONFIG_CRYPTO_DEV_ATMEL_I2C=m
CONFIG_CRYPTO_DEV_ATMEL_ECC=m
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
CONFIG_CRYPTO_DEV_CCP=y
CONFIG_CRYPTO_DEV_CCP_DD=y
CONFIG_CRYPTO_DEV_SP_CCP=y
CONFIG_CRYPTO_DEV_CCP_CRYPTO=m
CONFIG_CRYPTO_DEV_CCP_DEBUGFS=y
# CONFIG_CRYPTO_DEV_QCE is not set
CONFIG_CRYPTO_DEV_QCOM_RNG=y
CONFIG_CRYPTO_DEV_IMGTEC_HASH=m
CONFIG_CRYPTO_DEV_ROCKCHIP=y
CONFIG_CRYPTO_DEV_ZYNQMP_AES=m
CONFIG_CRYPTO_DEV_ZYNQMP_SHA3=y
CONFIG_CRYPTO_DEV_VIRTIO=m
# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
CONFIG_CRYPTO_DEV_CCREE=y
CONFIG_CRYPTO_DEV_HISI_SEC=m
# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set
# CONFIG_CRYPTO_DEV_SA2UL is not set
# CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4 is not set
CONFIG_CRYPTO_DEV_KEEMBAY_OCS_ECC=m
CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU=m
# CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU_HMAC_SHA224 is not set
CONFIG_CRYPTO_DEV_ASPEED=m
# CONFIG_CRYPTO_DEV_ASPEED_DEBUG is not set
CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH=y
# CONFIG_CRYPTO_DEV_ASPEED_HACE_CRYPTO is not set
# CONFIG_ASYMMETRIC_KEY_TYPE is not set
#
# Certificates for signature checking
#
CONFIG_SYSTEM_BLACKLIST_KEYRING=y
CONFIG_SYSTEM_BLACKLIST_HASH_LIST=""
# end of Certificates for signature checking
#
# Library routines
#
CONFIG_LINEAR_RANGES=y
# CONFIG_PACKING is not set
CONFIG_BITREVERSE=y
CONFIG_HAVE_ARCH_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_CORDIC=m
CONFIG_PRIME_NUMBERS=y
CONFIG_RATIONAL=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_STMP_DEVICE=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
CONFIG_INDIRECT_PIO=y
#
# Crypto library routines
#
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LIB_AES=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
CONFIG_CRYPTO_LIB_CHACHA=y
CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m
CONFIG_CRYPTO_LIB_CURVE25519=m
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305=y
CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
# end of Crypto library routines
CONFIG_CRC_CCITT=m
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=m
CONFIG_CRC64_ROCKSOFT=m
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
# CONFIG_CRC32_SLICEBY8 is not set
CONFIG_CRC32_SLICEBY4=y
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
CONFIG_CRC64=m
CONFIG_CRC4=y
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
CONFIG_CRC8=m
CONFIG_XXHASH=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
# CONFIG_RANDOM32_SELFTEST is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=m
CONFIG_LZO_DECOMPRESS=m
CONFIG_LZ4_COMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_XZ_DEC=y
CONFIG_XZ_DEC_X86=y
CONFIG_XZ_DEC_POWERPC=y
CONFIG_XZ_DEC_IA64=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
# CONFIG_XZ_DEC_SPARC is not set
# CONFIG_XZ_DEC_MICROLZMA is not set
CONFIG_XZ_DEC_BCJ=y
# CONFIG_XZ_DEC_TEST is not set
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_REED_SOLOMON=m
CONFIG_REED_SOLOMON_DEC16=y
CONFIG_BCH=m
CONFIG_BCH_CONST_PARAMS=y
CONFIG_INTERVAL_TREE=y
CONFIG_XARRAY_MULTI=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_DMA=y
CONFIG_DMA_OPS=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_DMA_DECLARE_COHERENT=y
CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
CONFIG_SWIOTLB=y
CONFIG_DMA_RESTRICTED_POOL=y
CONFIG_DMA_NONCOHERENT_MMAP=y
CONFIG_DMA_COHERENT_POOL=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_CMA=y
CONFIG_DMA_PERNUMA_CMA=y
#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_MBYTES=16
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_ALIGNMENT=8
# CONFIG_DMA_API_DEBUG is not set
# CONFIG_DMA_MAP_BENCHMARK is not set
CONFIG_SGL_ALLOC=y
# CONFIG_CPUMASK_OFFSTACK is not set
CONFIG_FORCE_NR_CPUS=y
CONFIG_GLOB=y
CONFIG_GLOB_SELFTEST=m
CONFIG_CLZ_TAB=y
CONFIG_IRQ_POLL=y
CONFIG_MPILIB=y
CONFIG_LIBFDT=y
CONFIG_OID_REGISTRY=m
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_VDSO_TIME_NS=y
CONFIG_SG_SPLIT=y
CONFIG_ARCH_STACKWALK=y
CONFIG_STACKDEPOT=y
CONFIG_STACKDEPOT_ALWAYS_INIT=y
# CONFIG_PARMAN is not set
CONFIG_OBJAGG=y
# end of Library routines
CONFIG_GENERIC_IOREMAP=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
#
# Kernel hacking
#
#
# printk and dmesg options
#
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_CONSOLE_LOGLEVEL_QUIET=4
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
CONFIG_SYMBOLIC_ERRNAME=y
# end of printk and dmesg options
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MISC=y
#
# Compile-time checks and compiler options
#
CONFIG_DEBUG_INFO=y
CONFIG_AS_HAS_NON_CONST_LEB128=y
# CONFIG_DEBUG_INFO_NONE is not set
# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set
CONFIG_DEBUG_INFO_DWARF4=y
# CONFIG_DEBUG_INFO_DWARF5 is not set
CONFIG_DEBUG_INFO_REDUCED=y
# CONFIG_DEBUG_INFO_COMPRESSED is not set
CONFIG_DEBUG_INFO_SPLIT=y
CONFIG_PAHOLE_HAS_SPLIT_BTF=y
# CONFIG_GDB_SCRIPTS is not set
CONFIG_FRAME_WARN=8192
# CONFIG_STRIP_ASM_SYMS is not set
CONFIG_READABLE_ASM=y
CONFIG_HEADERS_INSTALL=y
CONFIG_DEBUG_SECTION_MISMATCH=y
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B=y
CONFIG_ARCH_WANT_FRAME_POINTERS=y
CONFIG_FRAME_POINTER=y
# CONFIG_VMLINUX_MAP is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# end of Compile-time checks and compiler options
#
# Generic Kernel Debugging Instruments
#
# CONFIG_MAGIC_SYSRQ is not set
CONFIG_DEBUG_FS=y
# CONFIG_DEBUG_FS_ALLOW_ALL is not set
CONFIG_DEBUG_FS_DISALLOW_MOUNT=y
# CONFIG_DEBUG_FS_ALLOW_NONE is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
# CONFIG_UBSAN is not set
CONFIG_HAVE_ARCH_KCSAN=y
CONFIG_HAVE_KCSAN_COMPILER=y
# end of Generic Kernel Debugging Instruments
#
# Networking Debugging
#
# end of Networking Debugging
#
# Memory Debugging
#
CONFIG_PAGE_EXTENSION=y
CONFIG_DEBUG_PAGEALLOC=y
# CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT is not set
CONFIG_SLUB_DEBUG=y
CONFIG_SLUB_DEBUG_ON=y
CONFIG_PAGE_OWNER=y
# CONFIG_PAGE_TABLE_CHECK is not set
CONFIG_PAGE_POISONING=y
# CONFIG_DEBUG_RODATA_TEST is not set
CONFIG_ARCH_HAS_DEBUG_WX=y
CONFIG_DEBUG_WX=y
CONFIG_GENERIC_PTDUMP=y
CONFIG_PTDUMP_CORE=y
CONFIG_PTDUMP_DEBUGFS=y
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SHRINKER_DEBUG is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_SCHED_STACK_END_CHECK is not set
CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
CONFIG_DEBUG_VM_IRQSOFF=y
CONFIG_DEBUG_VM=y
CONFIG_DEBUG_VM_MAPLE_TREE=y
# CONFIG_DEBUG_VM_RB is not set
CONFIG_DEBUG_VM_PGFLAGS=y
# CONFIG_DEBUG_VM_PGTABLE is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
CONFIG_DEBUG_VIRTUAL=y
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_DEBUG_PER_CPU_MAPS=y
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y
CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
CONFIG_CC_HAS_KASAN_GENERIC=y
CONFIG_CC_HAS_KASAN_SW_TAGS=y
CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
CONFIG_KASAN=y
# CONFIG_KASAN_GENERIC is not set
CONFIG_KASAN_SW_TAGS=y
# CONFIG_KASAN_OUTLINE is not set
CONFIG_KASAN_INLINE=y
CONFIG_KASAN_STACK=y
CONFIG_KASAN_VMALLOC=y
CONFIG_KASAN_KUNIT_TEST=m
# CONFIG_KASAN_MODULE_TEST is not set
CONFIG_HAVE_ARCH_KFENCE=y
CONFIG_KFENCE=y
CONFIG_KFENCE_SAMPLE_INTERVAL=100
CONFIG_KFENCE_NUM_OBJECTS=255
CONFIG_KFENCE_DEFERRABLE=y
CONFIG_KFENCE_STATIC_KEYS=y
CONFIG_KFENCE_STRESS_TEST_FAULTS=0
# end of Memory Debugging
# CONFIG_DEBUG_SHIRQ is not set
#
# Debug Oops, Lockups and Hangs
#
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
CONFIG_PANIC_TIMEOUT=0
# CONFIG_SOFTLOCKUP_DETECTOR is not set
# CONFIG_DETECT_HUNG_TASK is not set
CONFIG_WQ_WATCHDOG=y
CONFIG_TEST_LOCKUP=m
# end of Debug Oops, Lockups and Hangs
#
# Scheduler Debugging
#
# end of Scheduler Debugging
CONFIG_DEBUG_TIMEKEEPING=y
CONFIG_DEBUG_PREEMPT=y
#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_PROVE_LOCKING is not set
CONFIG_LOCK_STAT=y
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y
CONFIG_DEBUG_RWSEMS=y
CONFIG_DEBUG_LOCK_ALLOC=y
CONFIG_LOCKDEP=y
CONFIG_LOCKDEP_BITS=15
CONFIG_LOCKDEP_CHAINS_BITS=16
CONFIG_LOCKDEP_STACK_TRACE_BITS=19
CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14
CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12
# CONFIG_DEBUG_LOCKDEP is not set
# CONFIG_DEBUG_ATOMIC_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
CONFIG_LOCK_TORTURE_TEST=y
CONFIG_WW_MUTEX_SELFTEST=m
CONFIG_SCF_TORTURE_TEST=y
CONFIG_CSD_LOCK_WAIT_DEBUG=y
# end of Lock Debugging (spinlocks, mutexes, etc...)
CONFIG_DEBUG_IRQFLAGS=y
CONFIG_STACKTRACE=y
CONFIG_WARN_ALL_UNSEEDED_RANDOM=y
# CONFIG_DEBUG_KOBJECT is not set
#
# Debug kernel data structures
#
CONFIG_DEBUG_LIST=y
# CONFIG_DEBUG_PLIST is not set
# CONFIG_DEBUG_SG is not set
CONFIG_DEBUG_NOTIFIERS=y
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
CONFIG_DEBUG_MAPLE_TREE=y
# end of Debug kernel data structures
CONFIG_DEBUG_CREDENTIALS=y
#
# RCU Debugging
#
CONFIG_TORTURE_TEST=y
CONFIG_RCU_SCALE_TEST=m
CONFIG_RCU_TORTURE_TEST=y
CONFIG_RCU_REF_SCALE_TEST=m
CONFIG_RCU_CPU_STALL_TIMEOUT=21
CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0
# CONFIG_RCU_TRACE is not set
CONFIG_RCU_EQS_DEBUG=y
# end of RCU Debugging
# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_SAMPLES is not set
# CONFIG_STRICT_DEVMEM is not set
#
# arm64 Debugging
#
CONFIG_PID_IN_CONTEXTIDR=y
# CONFIG_ARM64_RELOC_TEST is not set
CONFIG_CORESIGHT=m
CONFIG_CORESIGHT_LINKS_AND_SINKS=m
CONFIG_CORESIGHT_LINK_AND_SINK_TMC=m
CONFIG_CORESIGHT_CATU=m
CONFIG_CORESIGHT_SINK_TPIU=m
CONFIG_CORESIGHT_SINK_ETBV10=m
CONFIG_CORESIGHT_SOURCE_ETM4X=m
CONFIG_ETM4X_IMPDEF_FEATURE=y
# CONFIG_CORESIGHT_STM is not set
# CONFIG_CORESIGHT_CPU_DEBUG is not set
# CONFIG_CORESIGHT_CTI is not set
CONFIG_CORESIGHT_TRBE=m
# end of arm64 Debugging
#
# Kernel Testing and Coverage
#
CONFIG_KUNIT=m
# CONFIG_KUNIT_DEBUGFS is not set
# CONFIG_KUNIT_TEST is not set
CONFIG_KUNIT_EXAMPLE_TEST=m
CONFIG_KUNIT_ALL_TESTS=m
# CONFIG_KUNIT_DEFAULT_ENABLED is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
CONFIG_FAULT_INJECTION=y
CONFIG_FAILSLAB=y
CONFIG_FAIL_PAGE_ALLOC=y
CONFIG_FAULT_INJECTION_USERCOPY=y
# CONFIG_FAULT_INJECTION_DEBUG_FS is not set
CONFIG_ARCH_HAS_KCOV=y
CONFIG_CC_HAS_SANCOV_TRACE_PC=y
CONFIG_KCOV=y
CONFIG_KCOV_ENABLE_COMPARISONS=y
# CONFIG_KCOV_INSTRUMENT_ALL is not set
CONFIG_KCOV_IRQ_AREA_SIZE=0x40000
# CONFIG_RUNTIME_TESTING_MENU is not set
CONFIG_ARCH_USE_MEMTEST=y
CONFIG_MEMTEST=y
# end of Kernel Testing and Coverage
#
# Rust hacking
#
# end of Rust hacking
# CONFIG_WARN_MISSING_DOCUMENTS is not set
# CONFIG_WARN_ABI_ERRORS is not set
# end of Kernel hacking
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2022-11-03 20:35 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-11-01 23:57 [PATCH 0/4] Initial SDM670 and Pixel 3a support Richard Acayan
2022-11-01 23:57 ` [PATCH 1/4] dt-bindings: arm: cpus: add qcom kryo 360 compatible Richard Acayan
2022-11-02 17:36 ` Rob Herring
2022-11-01 23:57 ` [PATCH 2/4] dt-bindings: arm: qcom: add sdm670 and pixel 3a compatible Richard Acayan
2022-11-02 17:37 ` Rob Herring
2022-11-01 23:57 ` [PATCH 3/4] dt-bindings: firmware: scm: add sdm670 compatible Richard Acayan
2022-11-02 17:37 ` Rob Herring
2022-11-02 17:51 ` Guru Das Srinagesh
2022-11-01 23:57 ` [PATCH 4/4] arm64: dts: qcom: add sdm670 and pixel 3a device trees Richard Acayan
2022-11-02 2:19 ` Richard Acayan
2022-11-02 20:26 ` Konrad Dybcio
2022-11-02 20:30 ` Krzysztof Kozlowski
2022-11-02 20:44 ` Konrad Dybcio
2022-11-03 0:53 ` Richard Acayan
2022-11-03 1:19 ` Richard Acayan
2022-11-03 20:34 ` kernel test robot
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