* [PATCH] cxl/pci: Add some type-safety to the AER trace points
@ 2022-12-06 4:28 Dan Williams
2022-12-06 6:41 ` Ira Weiny
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Dan Williams @ 2022-12-06 4:28 UTC (permalink / raw)
To: linux-cxl; +Cc: Jonathan Cameron, Dave Jiang, Steven Rostedt, dave.jiang
The first argument to the CXL AER trace points is the source device.
Pass a 'const struct device *' rather than a 'const char *' for more
type precision / safety.
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Dave Jiang <dave.jiang@intel.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
drivers/cxl/pci.c | 4 ++--
include/trace/events/cxl.h | 16 ++++++++--------
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 6cec9fa9326c..cced4a0df3d1 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -562,7 +562,7 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
}
header_log_copy(cxlds, hl);
- trace_cxl_aer_uncorrectable_error(dev_name(dev), status, fe, hl);
+ trace_cxl_aer_uncorrectable_error(dev, status, fe, hl);
writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr);
return true;
@@ -644,7 +644,7 @@ static void cxl_cor_error_detected(struct pci_dev *pdev)
status = le32_to_cpu(readl(addr));
if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {
writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);
- trace_cxl_aer_correctable_error(dev_name(dev), status);
+ trace_cxl_aer_correctable_error(dev, status);
}
}
diff --git a/include/trace/events/cxl.h b/include/trace/events/cxl.h
index 72c3e2870a9e..ad085a2534ef 100644
--- a/include/trace/events/cxl.h
+++ b/include/trace/events/cxl.h
@@ -45,16 +45,16 @@
)
TRACE_EVENT(cxl_aer_uncorrectable_error,
- TP_PROTO(const char *dev_name, u32 status, u32 fe, u32 *hl),
- TP_ARGS(dev_name, status, fe, hl),
+ TP_PROTO(const struct device *dev, u32 status, u32 fe, u32 *hl),
+ TP_ARGS(dev, status, fe, hl),
TP_STRUCT__entry(
- __string(dev_name, dev_name)
+ __string(dev_name, dev_name(dev))
__field(u32, status)
__field(u32, first_error)
__array(u32, header_log, CXL_HEADERLOG_SIZE_U32)
),
TP_fast_assign(
- __assign_str(dev_name, dev_name);
+ __assign_str(dev_name, dev_name(dev));
__entry->status = status;
__entry->first_error = fe;
/*
@@ -89,14 +89,14 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,
)
TRACE_EVENT(cxl_aer_correctable_error,
- TP_PROTO(const char *dev_name, u32 status),
- TP_ARGS(dev_name, status),
+ TP_PROTO(const struct device *dev, u32 status),
+ TP_ARGS(dev, status),
TP_STRUCT__entry(
- __string(dev_name, dev_name)
+ __string(dev_name, dev_name(dev))
__field(u32, status)
),
TP_fast_assign(
- __assign_str(dev_name, dev_name);
+ __assign_str(dev_name, dev_name(dev));
__entry->status = status;
),
TP_printk("%s: status: '%s'",
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] cxl/pci: Add some type-safety to the AER trace points
2022-12-06 4:28 [PATCH] cxl/pci: Add some type-safety to the AER trace points Dan Williams
@ 2022-12-06 6:41 ` Ira Weiny
2022-12-06 9:58 ` Jonathan Cameron
2022-12-06 17:06 ` Dave Jiang
2 siblings, 0 replies; 4+ messages in thread
From: Ira Weiny @ 2022-12-06 6:41 UTC (permalink / raw)
To: Dan Williams; +Cc: linux-cxl, Jonathan Cameron, Dave Jiang, Steven Rostedt
On Mon, Dec 05, 2022 at 08:28:34PM -0800, Dan Williams wrote:
> The first argument to the CXL AER trace points is the source device.
> Pass a 'const struct device *' rather than a 'const char *' for more
> type precision / safety.
>
> Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Cc: Dave Jiang <dave.jiang@intel.com>
> Cc: Steven Rostedt <rostedt@goodmis.org>
Sure.
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> ---
> drivers/cxl/pci.c | 4 ++--
> include/trace/events/cxl.h | 16 ++++++++--------
> 2 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 6cec9fa9326c..cced4a0df3d1 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -562,7 +562,7 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
> }
>
> header_log_copy(cxlds, hl);
> - trace_cxl_aer_uncorrectable_error(dev_name(dev), status, fe, hl);
> + trace_cxl_aer_uncorrectable_error(dev, status, fe, hl);
> writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr);
>
> return true;
> @@ -644,7 +644,7 @@ static void cxl_cor_error_detected(struct pci_dev *pdev)
> status = le32_to_cpu(readl(addr));
> if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {
> writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);
> - trace_cxl_aer_correctable_error(dev_name(dev), status);
> + trace_cxl_aer_correctable_error(dev, status);
> }
> }
>
> diff --git a/include/trace/events/cxl.h b/include/trace/events/cxl.h
> index 72c3e2870a9e..ad085a2534ef 100644
> --- a/include/trace/events/cxl.h
> +++ b/include/trace/events/cxl.h
> @@ -45,16 +45,16 @@
> )
>
> TRACE_EVENT(cxl_aer_uncorrectable_error,
> - TP_PROTO(const char *dev_name, u32 status, u32 fe, u32 *hl),
> - TP_ARGS(dev_name, status, fe, hl),
> + TP_PROTO(const struct device *dev, u32 status, u32 fe, u32 *hl),
> + TP_ARGS(dev, status, fe, hl),
> TP_STRUCT__entry(
> - __string(dev_name, dev_name)
> + __string(dev_name, dev_name(dev))
> __field(u32, status)
> __field(u32, first_error)
> __array(u32, header_log, CXL_HEADERLOG_SIZE_U32)
> ),
> TP_fast_assign(
> - __assign_str(dev_name, dev_name);
> + __assign_str(dev_name, dev_name(dev));
> __entry->status = status;
> __entry->first_error = fe;
> /*
> @@ -89,14 +89,14 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,
> )
>
> TRACE_EVENT(cxl_aer_correctable_error,
> - TP_PROTO(const char *dev_name, u32 status),
> - TP_ARGS(dev_name, status),
> + TP_PROTO(const struct device *dev, u32 status),
> + TP_ARGS(dev, status),
> TP_STRUCT__entry(
> - __string(dev_name, dev_name)
> + __string(dev_name, dev_name(dev))
> __field(u32, status)
> ),
> TP_fast_assign(
> - __assign_str(dev_name, dev_name);
> + __assign_str(dev_name, dev_name(dev));
> __entry->status = status;
> ),
> TP_printk("%s: status: '%s'",
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] cxl/pci: Add some type-safety to the AER trace points
2022-12-06 4:28 [PATCH] cxl/pci: Add some type-safety to the AER trace points Dan Williams
2022-12-06 6:41 ` Ira Weiny
@ 2022-12-06 9:58 ` Jonathan Cameron
2022-12-06 17:06 ` Dave Jiang
2 siblings, 0 replies; 4+ messages in thread
From: Jonathan Cameron @ 2022-12-06 9:58 UTC (permalink / raw)
To: Dan Williams; +Cc: linux-cxl, Dave Jiang, Steven Rostedt
On Mon, 05 Dec 2022 20:28:34 -0800
Dan Williams <dan.j.williams@intel.com> wrote:
> The first argument to the CXL AER trace points is the source device.
> Pass a 'const struct device *' rather than a 'const char *' for more
> type precision / safety.
>
> Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Cc: Dave Jiang <dave.jiang@intel.com>
> Cc: Steven Rostedt <rostedt@goodmis.org>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
I guess this is slightly nicer.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> drivers/cxl/pci.c | 4 ++--
> include/trace/events/cxl.h | 16 ++++++++--------
> 2 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 6cec9fa9326c..cced4a0df3d1 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -562,7 +562,7 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
> }
>
> header_log_copy(cxlds, hl);
> - trace_cxl_aer_uncorrectable_error(dev_name(dev), status, fe, hl);
> + trace_cxl_aer_uncorrectable_error(dev, status, fe, hl);
> writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr);
>
> return true;
> @@ -644,7 +644,7 @@ static void cxl_cor_error_detected(struct pci_dev *pdev)
> status = le32_to_cpu(readl(addr));
> if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {
> writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);
> - trace_cxl_aer_correctable_error(dev_name(dev), status);
> + trace_cxl_aer_correctable_error(dev, status);
> }
> }
>
> diff --git a/include/trace/events/cxl.h b/include/trace/events/cxl.h
> index 72c3e2870a9e..ad085a2534ef 100644
> --- a/include/trace/events/cxl.h
> +++ b/include/trace/events/cxl.h
> @@ -45,16 +45,16 @@
> )
>
> TRACE_EVENT(cxl_aer_uncorrectable_error,
> - TP_PROTO(const char *dev_name, u32 status, u32 fe, u32 *hl),
> - TP_ARGS(dev_name, status, fe, hl),
> + TP_PROTO(const struct device *dev, u32 status, u32 fe, u32 *hl),
> + TP_ARGS(dev, status, fe, hl),
> TP_STRUCT__entry(
> - __string(dev_name, dev_name)
> + __string(dev_name, dev_name(dev))
> __field(u32, status)
> __field(u32, first_error)
> __array(u32, header_log, CXL_HEADERLOG_SIZE_U32)
> ),
> TP_fast_assign(
> - __assign_str(dev_name, dev_name);
> + __assign_str(dev_name, dev_name(dev));
> __entry->status = status;
> __entry->first_error = fe;
> /*
> @@ -89,14 +89,14 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,
> )
>
> TRACE_EVENT(cxl_aer_correctable_error,
> - TP_PROTO(const char *dev_name, u32 status),
> - TP_ARGS(dev_name, status),
> + TP_PROTO(const struct device *dev, u32 status),
> + TP_ARGS(dev, status),
> TP_STRUCT__entry(
> - __string(dev_name, dev_name)
> + __string(dev_name, dev_name(dev))
> __field(u32, status)
> ),
> TP_fast_assign(
> - __assign_str(dev_name, dev_name);
> + __assign_str(dev_name, dev_name(dev));
> __entry->status = status;
> ),
> TP_printk("%s: status: '%s'",
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] cxl/pci: Add some type-safety to the AER trace points
2022-12-06 4:28 [PATCH] cxl/pci: Add some type-safety to the AER trace points Dan Williams
2022-12-06 6:41 ` Ira Weiny
2022-12-06 9:58 ` Jonathan Cameron
@ 2022-12-06 17:06 ` Dave Jiang
2 siblings, 0 replies; 4+ messages in thread
From: Dave Jiang @ 2022-12-06 17:06 UTC (permalink / raw)
To: Dan Williams, linux-cxl; +Cc: Jonathan Cameron, Steven Rostedt
On 12/5/2022 9:28 PM, Dan Williams wrote:
> The first argument to the CXL AER trace points is the source device.
> Pass a 'const struct device *' rather than a 'const char *' for more
> type precision / safety.
>
> Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Cc: Dave Jiang <dave.jiang@intel.com>
> Cc: Steven Rostedt <rostedt@goodmis.org>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> drivers/cxl/pci.c | 4 ++--
> include/trace/events/cxl.h | 16 ++++++++--------
> 2 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 6cec9fa9326c..cced4a0df3d1 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -562,7 +562,7 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
> }
>
> header_log_copy(cxlds, hl);
> - trace_cxl_aer_uncorrectable_error(dev_name(dev), status, fe, hl);
> + trace_cxl_aer_uncorrectable_error(dev, status, fe, hl);
> writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr);
>
> return true;
> @@ -644,7 +644,7 @@ static void cxl_cor_error_detected(struct pci_dev *pdev)
> status = le32_to_cpu(readl(addr));
> if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {
> writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);
> - trace_cxl_aer_correctable_error(dev_name(dev), status);
> + trace_cxl_aer_correctable_error(dev, status);
> }
> }
>
> diff --git a/include/trace/events/cxl.h b/include/trace/events/cxl.h
> index 72c3e2870a9e..ad085a2534ef 100644
> --- a/include/trace/events/cxl.h
> +++ b/include/trace/events/cxl.h
> @@ -45,16 +45,16 @@
> )
>
> TRACE_EVENT(cxl_aer_uncorrectable_error,
> - TP_PROTO(const char *dev_name, u32 status, u32 fe, u32 *hl),
> - TP_ARGS(dev_name, status, fe, hl),
> + TP_PROTO(const struct device *dev, u32 status, u32 fe, u32 *hl),
> + TP_ARGS(dev, status, fe, hl),
> TP_STRUCT__entry(
> - __string(dev_name, dev_name)
> + __string(dev_name, dev_name(dev))
> __field(u32, status)
> __field(u32, first_error)
> __array(u32, header_log, CXL_HEADERLOG_SIZE_U32)
> ),
> TP_fast_assign(
> - __assign_str(dev_name, dev_name);
> + __assign_str(dev_name, dev_name(dev));
> __entry->status = status;
> __entry->first_error = fe;
> /*
> @@ -89,14 +89,14 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,
> )
>
> TRACE_EVENT(cxl_aer_correctable_error,
> - TP_PROTO(const char *dev_name, u32 status),
> - TP_ARGS(dev_name, status),
> + TP_PROTO(const struct device *dev, u32 status),
> + TP_ARGS(dev, status),
> TP_STRUCT__entry(
> - __string(dev_name, dev_name)
> + __string(dev_name, dev_name(dev))
> __field(u32, status)
> ),
> TP_fast_assign(
> - __assign_str(dev_name, dev_name);
> + __assign_str(dev_name, dev_name(dev));
> __entry->status = status;
> ),
> TP_printk("%s: status: '%s'",
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-12-06 17:06 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-12-06 4:28 [PATCH] cxl/pci: Add some type-safety to the AER trace points Dan Williams
2022-12-06 6:41 ` Ira Weiny
2022-12-06 9:58 ` Jonathan Cameron
2022-12-06 17:06 ` Dave Jiang
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.