* [Intel-gfx] [PATCH v8 0/6] Enable YCbCr420 for VDSC
@ 2023-01-18 5:59 Suraj Kandpal
2023-01-18 5:59 ` [Intel-gfx] [PATCH v8 1/6] drm/dp_helper: Add helper to check if the sink supports given format with DSC Suraj Kandpal
` (13 more replies)
0 siblings, 14 replies; 16+ messages in thread
From: Suraj Kandpal @ 2023-01-18 5:59 UTC (permalink / raw)
To: intel-gfx
This patch series aims to enable the YCbCr420 format
for DSC. Changes are mostly compute params related for
hdmi,dp and dsi along with the addition of new rc_tables
for native_420 and corresponding changes to macros used to
fetch them.
---v2
-add fields missed for vdsc_cfg [Vandita]
-add corresponding registers and writing to the [Vandita]
---v3
-add 11 bit left shift missed in nsl_bpg_offset calculation
---v4
-add display version check before writing in new pps register
---v5
-add helper to check if sink supports given format with DSC
-add debugfs entry to enforce DSC with YCbCr420 format only
--v6
-add patch to check dsc slice design requirement [Vandita]
--v7
-fix function name to intel_slice_dimensions_valid [Jani]
-remove full bspec link just add the ref number [Jani]
-remove patches for debug fs will float them as a seprate series
-Add more description for YUV420 Enablement [Vandita]
--v8
-fix slice width and height 2's multiple check
-fix minimum pixel requirement in slice check
Ankit Nautiyal (2):
drm/dp_helper: Add helper to check if the sink supports given format
with DSC
drm/i915/dp: Check if DSC supports the given output_format
Suraj Kandpal (4):
drm/i915: Adding the new registers for DSC
drm/i915: Enable YCbCr420 for VDSC
drm/i915: Fill in native_420 field
drm/i915/vdsc: Check slice design requirement
drivers/gpu/drm/i915/display/icl_dsi.c | 2 -
drivers/gpu/drm/i915/display/intel_dp.c | 33 +++-
.../gpu/drm/i915/display/intel_qp_tables.c | 187 ++++++++++++++++--
.../gpu/drm/i915/display/intel_qp_tables.h | 4 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 106 +++++++++-
drivers/gpu/drm/i915/i915_reg.h | 28 +++
include/drm/display/drm_dp_helper.h | 7 +
7 files changed, 345 insertions(+), 22 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v8 1/6] drm/dp_helper: Add helper to check if the sink supports given format with DSC
2023-01-18 5:59 [Intel-gfx] [PATCH v8 0/6] Enable YCbCr420 for VDSC Suraj Kandpal
@ 2023-01-18 5:59 ` Suraj Kandpal
2023-01-18 5:59 ` [Intel-gfx] [PATCH v8 2/6] drm/i915/dp: Check if DSC supports the given output_format Suraj Kandpal
` (12 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Suraj Kandpal @ 2023-01-18 5:59 UTC (permalink / raw)
To: intel-gfx
From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Add helper function to check if the DP sink supports DSC with the given
output format.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
include/drm/display/drm_dp_helper.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index ab55453f2d2c..d529d0254b68 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -194,6 +194,13 @@ drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
DP_DSC_SLICE_WIDTH_MULTIPLIER;
}
+/* Check if sink supports DSC with given output format */
+static inline bool
+drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format)
+{
+ return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & output_format;
+}
+
/* Forward Error Correction Support on DP 1.4 */
static inline bool
drm_dp_sink_supports_fec(const u8 fec_capable)
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v8 2/6] drm/i915/dp: Check if DSC supports the given output_format
2023-01-18 5:59 [Intel-gfx] [PATCH v8 0/6] Enable YCbCr420 for VDSC Suraj Kandpal
2023-01-18 5:59 ` [Intel-gfx] [PATCH v8 1/6] drm/dp_helper: Add helper to check if the sink supports given format with DSC Suraj Kandpal
@ 2023-01-18 5:59 ` Suraj Kandpal
2023-01-18 5:59 ` [Intel-gfx] [PATCH v8 3/6] drm/i915: Adding the new registers for DSC Suraj Kandpal
` (11 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Suraj Kandpal @ 2023-01-18 5:59 UTC (permalink / raw)
To: intel-gfx
From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Go with DSC only if the given output_format is supported.
v2: Use drm helper to get DSC format support for sink.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 30 +++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 30c55f980014..6e531872ff38 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1483,6 +1483,31 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
return drm_dsc_compute_rc_parameters(vdsc_cfg);
}
+static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
+ enum intel_output_format output_format)
+{
+ u8 sink_dsc_format;
+
+ switch (output_format) {
+ case INTEL_OUTPUT_FORMAT_RGB:
+ sink_dsc_format = DP_DSC_RGB;
+ break;
+ case INTEL_OUTPUT_FORMAT_YCBCR444:
+ sink_dsc_format = DP_DSC_YCbCr444;
+ break;
+ case INTEL_OUTPUT_FORMAT_YCBCR420:
+ if (min(intel_dp_source_dsc_version_minor(intel_dp),
+ intel_dp_sink_dsc_version_minor(intel_dp)) < 2)
+ return false;
+ sink_dsc_format = DP_DSC_YCbCr420_Native;
+ break;
+ default:
+ return false;
+ }
+
+ return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
+}
+
int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -1503,11 +1528,16 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
+ if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
+ return -EINVAL;
+
if (compute_pipe_bpp)
pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
else
pipe_bpp = pipe_config->pipe_bpp;
+ pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
+
if (intel_dp->force_dsc_bpc) {
pipe_bpp = intel_dp->force_dsc_bpc * 3;
drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp);
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v8 3/6] drm/i915: Adding the new registers for DSC
2023-01-18 5:59 [Intel-gfx] [PATCH v8 0/6] Enable YCbCr420 for VDSC Suraj Kandpal
2023-01-18 5:59 ` [Intel-gfx] [PATCH v8 1/6] drm/dp_helper: Add helper to check if the sink supports given format with DSC Suraj Kandpal
2023-01-18 5:59 ` [Intel-gfx] [PATCH v8 2/6] drm/i915/dp: Check if DSC supports the given output_format Suraj Kandpal
@ 2023-01-18 5:59 ` Suraj Kandpal
2023-01-18 6:00 ` [Intel-gfx] [PATCH v8 4/6] drm/i915: Enable YCbCr420 for VDSC Suraj Kandpal
` (10 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Suraj Kandpal @ 2023-01-18 5:59 UTC (permalink / raw)
To: intel-gfx
Adding new DSC register which are introducted MTL onwards
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Vandita Kulkarni <Vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8b2cf980f323..69a645ce0fe8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7766,6 +7766,8 @@ enum skl_power_gate {
#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
+#define DSC_NATIVE_422_ENABLE BIT(23)
+#define DSC_NATIVE_420_ENABLE BIT(22)
#define DSC_ALT_ICH_SEL (1 << 20)
#define DSC_VBR_ENABLE (1 << 19)
#define DSC_422_ENABLE (1 << 18)
@@ -8010,6 +8012,32 @@ enum skl_power_gate {
#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
+/* MTL Display Stream Compression registers */
+#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB 0x782B4
+#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB 0x783B4
+#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC 0x784B4
+#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC 0x785B4
+#define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB, \
+ _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC)
+#define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \
+ _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC)
+#define DSC_SL_BPG_OFFSET(offset) ((offset) << 27)
+
+#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB 0x782B8
+#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB 0x783B8
+#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC 0x784B8
+#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC 0x785B8
+#define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB, \
+ _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC)
+#define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \
+ _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC)
+#define DSC_NSL_BPG_OFFSET(offset) ((offset) << 16)
+#define DSC_SL_OFFSET_ADJ(offset) ((offset) << 0)
+
/* Icelake Rate Control Buffer Threshold Registers */
#define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
#define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v8 4/6] drm/i915: Enable YCbCr420 for VDSC
2023-01-18 5:59 [Intel-gfx] [PATCH v8 0/6] Enable YCbCr420 for VDSC Suraj Kandpal
` (2 preceding siblings ...)
2023-01-18 5:59 ` [Intel-gfx] [PATCH v8 3/6] drm/i915: Adding the new registers for DSC Suraj Kandpal
@ 2023-01-18 6:00 ` Suraj Kandpal
2023-01-18 6:00 ` [Intel-gfx] [PATCH v8 5/6] drm/i915: Fill in native_420 field Suraj Kandpal
` (9 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Suraj Kandpal @ 2023-01-18 6:00 UTC (permalink / raw)
To: intel-gfx
Implementation of VDSC for YCbCr420.
Add QP tables for 8,10,12 BPC from rc_tables.h in intel_qp_tables.c
(Derived from C-Model, which is given along with DSC1.2a Spec from Vesa)
intel_lookup_range_min/max_qp functons need to take into account the
output format. Based on that appropriate qp table need to be chosen.
Other rc_parameters need to be set where currently values for 444 format
is hardcoded in calculate_rc_parameters( ).
vdsc_cfg struct needs to be filled with output format information, where
these are hardcoded for 444 format.
Bspec: 49259
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Vandita Kulkarni <Vandita.kulkarni@intel.com>
---
.../gpu/drm/i915/display/intel_qp_tables.c | 187 ++++++++++++++++--
.../gpu/drm/i915/display/intel_qp_tables.h | 4 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +-
3 files changed, 180 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c b/drivers/gpu/drm/i915/display/intel_qp_tables.c
index 6f8e4ec5c0fb..6e86c0971d24 100644
--- a/drivers/gpu/drm/i915/display/intel_qp_tables.c
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c
@@ -17,6 +17,15 @@
/* from BPP 6 to 36 in steps of 0.5 */
#define RC_RANGE_QP444_12BPC_MAX_NUM_BPP 61
+/* from BPP 6 to 24 in steps of 0.5 */
+#define RC_RANGE_QP420_8BPC_MAX_NUM_BPP 17
+
+/* from BPP 6 to 30 in steps of 0.5 */
+#define RC_RANGE_QP420_10BPC_MAX_NUM_BPP 23
+
+/* from BPP 6 to 36 in steps of 0.5 */
+#define RC_RANGE_QP420_12BPC_MAX_NUM_BPP 29
+
/*
* These qp tables are as per the C model
* and it has the rows pointing to bpps which increment
@@ -283,26 +292,182 @@ static const u8 rc_range_maxqp444_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_12BPC
11, 11, 10, 10, 10, 10, 10, 9, 9, 8, 8, 8, 8, 8, 7, 7, 6, 6, 6, 6, 5, 5, 4 }
};
-#define PARAM_TABLE(_minmax, _bpc, _row, _col) do { \
- if (bpc == (_bpc)) \
- return rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
+static const u8 rc_range_minqp420_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_8BPC_MAX_NUM_BPP] = {
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 },
+ { 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
+ { 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
+ { 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 0 },
+ { 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 0 },
+ { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1 },
+ { 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 1, 1 },
+ { 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 3, 2, 2, 1 },
+ { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 3, 3, 2, 1 },
+ { 9, 8, 8, 7, 7, 7, 7, 7, 7, 6, 5, 5, 4, 3, 3, 3, 2 },
+ { 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3 }
+};
+
+static const u8 rc_range_maxqp420_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_8BPC_MAX_NUM_BPP] = {
+ { 4, 4, 3, 3, 2, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 4, 4, 4, 4, 4, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+ { 5, 5, 5, 5, 5, 4, 3, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
+ { 6, 6, 6, 6, 6, 5, 4, 3, 2, 2, 2, 1, 1, 1, 1, 0, 0 },
+ { 7, 7, 7, 7, 7, 5, 4, 3, 2, 2, 2, 2, 2, 1, 1, 1, 0 },
+ { 7, 7, 7, 7, 7, 6, 5, 4, 3, 3, 3, 2, 2, 2, 1, 1, 0 },
+ { 7, 7, 7, 7, 7, 6, 5, 4, 3, 3, 3, 3, 2, 2, 2, 1, 1 },
+ { 8, 8, 8, 8, 8, 7, 6, 5, 4, 4, 4, 3, 3, 2, 2, 2, 1 },
+ { 9, 9, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1 },
+ { 10, 10, 9, 9, 9, 8, 7, 6, 5, 5, 5, 4, 4, 3, 3, 2, 2 },
+ { 10, 10, 10, 9, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3, 2, 2 },
+ { 11, 11, 10, 10, 9, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2 },
+ { 11, 11, 11, 10, 9, 9, 9, 8, 7, 7, 6, 5, 5, 4, 4, 3, 2 },
+ { 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 4, 4, 4, 3 },
+ { 14, 13, 13, 12, 11, 11, 10, 9, 9, 8, 7, 7, 6, 6, 5, 5, 4 }
+};
+
+static const u8 rc_range_minqp420_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_10BPC_MAX_NUM_BPP] = {
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 5, 5, 5, 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0 },
+ { 7, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 0, 0, 0, 0 },
+ { 7, 7, 7, 7, 7, 6, 5, 5, 5, 5, 5, 4, 3, 3, 2, 2, 1, 1, 1, 1, 1, 0, 0 },
+ { 7, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 3, 2, 2, 2, 2, 1, 1, 1, 0 },
+ { 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 5, 4, 4, 4, 3, 2, 2, 2, 1, 1, 1, 0 },
+ { 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 2, 1, 1 },
+ { 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1, 1 },
+ { 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1 },
+ { 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 7, 6, 6, 5, 4, 4, 3, 3, 2, 1 },
+ { 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3, 2, 1 },
+ { 13, 12, 12, 11, 11, 11, 11, 11, 11, 10, 9, 9, 8, 7, 7, 6, 5, 5, 4, 3, 3,
+ 2, 2 },
+ { 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10, 10, 9, 8, 8, 7, 6, 6, 5,
+ 5, 4, 4 }
+};
+
+static const u8 rc_range_maxqp420_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_10BPC_MAX_NUM_BPP] = {
+ { 8, 8, 7, 6, 4, 4, 3, 3, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 8, 8, 8, 7, 6, 5, 4, 4, 3, 3, 3, 3, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 },
+ { 9, 9, 9, 8, 8, 7, 6, 5, 4, 3, 3, 3, 3, 3, 2, 1, 1, 1, 0, 0, 0, 0, 0 },
+ { 10, 10, 10, 9, 9, 8, 7, 6, 5, 4, 4, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 0,
+ 0 },
+ { 11, 11, 11, 10, 10, 8, 7, 6, 5, 4, 4, 4, 4, 3, 3, 3, 2, 2, 2, 1, 1, 1,
+ 0 },
+ { 11, 11, 11, 10, 10, 9, 8, 7, 6, 6, 6, 5, 4, 4, 3, 3, 2, 2, 2, 2, 2, 1,
+ 1 },
+ { 11, 11, 11, 11, 11, 10, 9, 8, 7, 7, 7, 6, 5, 5, 4, 3, 3, 3, 3, 2, 2, 2,
+ 1 },
+ { 12, 12, 12, 12, 12, 11, 10, 9, 8, 8, 8, 7, 6, 5, 5, 4, 3, 3, 3, 2, 2,
+ 2, 1 },
+ { 13, 13, 13, 12, 12, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3, 3,
+ 2, 2 },
+ { 14, 14, 13, 13, 13, 12, 11, 10, 9, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3,
+ 2, 2 },
+ { 14, 14, 14, 13, 13, 12, 12, 11, 10, 10, 9, 9, 8, 8, 7, 6, 5, 5, 4, 4,
+ 3, 3, 2 },
+ { 15, 15, 14, 14, 13, 13, 12, 11, 11, 10, 10, 9, 9, 8, 7, 7, 6, 5, 5, 4,
+ 4, 3, 2 },
+ { 15, 15, 15, 14, 13, 13, 13, 12, 11, 11, 10, 9, 9, 8, 8, 7, 6, 5, 5, 4,
+ 4, 3, 2 },
+ { 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 4,
+ 4, 3, 3 },
+ { 18, 17, 17, 16, 15, 15, 14, 13, 13, 12, 11, 11, 11, 10, 9, 9, 8, 7, 7,
+ 6, 6, 5, 5 }
+};
+
+static const u8 rc_range_minqp420_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_12BPC_MAX_NUM_BPP] = {
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0 },
+ { 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0 },
+ { 9, 8, 8, 7, 7, 6, 5, 5, 4, 4, 4, 4, 3, 3, 3, 2, 2, 1, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0 },
+ { 10, 9, 9, 8, 8, 8, 7, 7, 6, 6, 6, 5, 5, 4, 4, 3, 2, 2, 1, 1, 1, 0, 0, 0,
+ 0, 0, 0, 0, 0 },
+ { 11, 10, 10, 10, 10, 9, 9, 8, 7, 6, 6, 6, 6, 5, 5, 4, 3, 3, 3, 2, 2, 1,
+ 0, 0, 0, 0, 0, 0, 0 },
+ { 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 9, 8, 7, 6, 5, 5, 4, 4, 3, 3, 3, 2,
+ 1, 1, 0, 0, 0, 0, 0 },
+ { 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 8, 8, 7, 6, 5, 5, 5, 5, 4, 3, 3,
+ 2, 1, 1, 1, 1, 1, 0 },
+ { 11, 11, 11, 11, 11, 11, 11, 10, 10, 10, 10, 9, 8, 8, 8, 7, 6, 6, 5, 4, 4,
+ 3, 2, 2, 1, 1, 1, 1, 1 },
+ { 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6, 5,
+ 5, 4, 4, 2, 2, 1, 1, 1, 1 },
+ { 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6,
+ 5, 4, 4, 3, 2, 2, 1, 1, 1 },
+ { 13, 13, 13, 13, 13, 13, 13, 12, 12, 12, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7,
+ 6, 5, 4, 3, 3, 2, 2, 1, 1 },
+ { 13, 13, 13, 13, 13, 13, 13, 13, 13, 12, 12, 12, 12, 11, 10, 10, 9, 8, 8,
+ 7, 7, 6, 5, 4, 3, 3, 2, 2, 1 },
+ { 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8,
+ 7, 7, 6, 5, 4, 4, 3, 2, 2, 1 },
+ { 15, 15, 15, 15, 15, 15, 15, 15, 15, 14, 13, 13, 12, 11, 11, 10, 9, 9, 8,
+ 8, 7, 6, 6, 5, 4, 4, 3, 3, 2 },
+ { 21, 20, 20, 19, 18, 18, 17, 16, 16, 15, 14, 14, 14, 13, 12, 12, 11, 10,
+ 10, 10, 9, 8, 8, 7, 6, 6, 5, 5, 4 }
+};
+
+static const u8 rc_range_maxqp420_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_12BPC_MAX_NUM_BPP] = {
+ { 11, 10, 9, 8, 6, 6, 5, 5, 4, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0,
+ 0, 0, 0, 0, 0, 0 },
+ { 12, 11, 11, 10, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1,
+ 1, 0, 0, 0, 0, 0, 0 },
+ { 13, 12, 12, 11, 11, 10, 9, 8, 7, 6, 6, 6, 5, 5, 4, 3, 3, 2, 1, 1, 1, 1,
+ 1, 0, 0, 0, 0, 0, 0 },
+ { 14, 13, 13, 12, 12, 11, 10, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2, 2, 2, 1,
+ 1, 1, 0, 0, 0, 0, 0 },
+ { 15, 14, 14, 13, 13, 11, 10, 9, 8, 7, 7, 7, 7, 6, 6, 5, 4, 4, 4, 3, 3, 2,
+ 1, 1, 1, 0, 0, 0, 0 },
+ { 15, 15, 15, 14, 14, 13, 12, 11, 10, 10, 10, 9, 8, 7, 6, 6, 5, 5, 4, 4,
+ 4, 3, 2, 2, 1, 1, 0, 0, 0 },
+ { 15, 15, 15, 15, 15, 14, 13, 12, 11, 11, 11, 10, 9, 8, 7, 6, 6, 6, 6, 5,
+ 4, 4, 3, 2, 2, 2, 1, 1, 0 },
+ { 16, 16, 16, 16, 16, 15, 14, 13, 12, 12, 12, 11, 10, 9, 9, 8, 7, 7, 6, 5,
+ 5, 4, 3, 3, 2, 2, 2, 1, 1 },
+ { 17, 17, 17, 16, 16, 15, 14, 14, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8, 7,
+ 6, 6, 5, 5, 3, 3, 2, 2, 1, 1 },
+ { 18, 18, 17, 17, 17, 16, 15, 14, 13, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8,
+ 7, 6, 5, 5, 4, 3, 3, 2, 2, 1 },
+ { 18, 18, 18, 17, 17, 16, 16, 15, 14, 14, 13, 13, 12, 12, 11, 10, 9, 9, 8,
+ 8, 7, 6, 5, 4, 4, 3, 3, 2, 2 },
+ { 19, 19, 18, 18, 17, 17, 16, 15, 15, 14, 14, 13, 13, 12, 11, 11, 10, 9,
+ 9, 8, 8, 7, 6, 5, 4, 4, 3, 3, 2 },
+ { 19, 19, 19, 18, 17, 17, 17, 16, 15, 15, 14, 13, 13, 12, 12, 11, 10, 9,
+ 9, 8, 8, 7, 6, 5, 5, 4, 3, 3, 2 },
+ { 21, 20, 20, 19, 18, 18, 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10,
+ 9, 9, 8, 7, 7, 6, 5, 5, 4, 4, 3 },
+ { 22, 21, 21, 20, 19, 19, 18, 17, 17, 16, 15, 15, 15, 14, 13, 13, 12, 11,
+ 11, 11, 10, 9, 9, 8, 7, 7, 6, 6, 5 }
+};
+
+#define PARAM_TABLE(_minmax, _bpc, _row, _col, _is_420) do { \
+ if (bpc == (_bpc)) { \
+ if (_is_420) \
+ return rc_range_##_minmax##qp420_##_bpc##bpc[_row][_col]; \
+ else \
+ return rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
+ } \
} while (0)
-u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i)
+u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i, bool is_420)
{
- PARAM_TABLE(min, 8, buf_i, bpp_i);
- PARAM_TABLE(min, 10, buf_i, bpp_i);
- PARAM_TABLE(min, 12, buf_i, bpp_i);
+ PARAM_TABLE(min, 8, buf_i, bpp_i, is_420);
+ PARAM_TABLE(min, 10, buf_i, bpp_i, is_420);
+ PARAM_TABLE(min, 12, buf_i, bpp_i, is_420);
MISSING_CASE(bpc);
return 0;
}
-u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i)
+u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i, bool is_420)
{
- PARAM_TABLE(max, 8, buf_i, bpp_i);
- PARAM_TABLE(max, 10, buf_i, bpp_i);
- PARAM_TABLE(max, 12, buf_i, bpp_i);
+ PARAM_TABLE(max, 8, buf_i, bpp_i, is_420);
+ PARAM_TABLE(max, 10, buf_i, bpp_i, is_420);
+ PARAM_TABLE(max, 12, buf_i, bpp_i, is_420);
MISSING_CASE(bpc);
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.h b/drivers/gpu/drm/i915/display/intel_qp_tables.h
index 9fb3c36bd7c6..a9ff9ca29938 100644
--- a/drivers/gpu/drm/i915/display/intel_qp_tables.h
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.h
@@ -8,7 +8,7 @@
#include <linux/types.h>
-u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i);
-u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i);
+u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i, bool is_420);
+u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i, bool is_420);
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 207b2a648d32..ed16f63d6355 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -422,9 +422,9 @@ calculate_rc_params(struct rc_parameters *rc,
for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
/* Read range_minqp and range_max_qp from qp tables */
rc->rc_range_params[buf_i].range_min_qp =
- intel_lookup_range_min_qp(bpc, buf_i, bpp_i);
+ intel_lookup_range_min_qp(bpc, buf_i, bpp_i, vdsc_cfg->native_420);
rc->rc_range_params[buf_i].range_max_qp =
- intel_lookup_range_max_qp(bpc, buf_i, bpp_i);
+ intel_lookup_range_max_qp(bpc, buf_i, bpp_i, vdsc_cfg->native_420);
/* Calculate range_bgp_offset */
if (bpp <= 6) {
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v8 5/6] drm/i915: Fill in native_420 field
2023-01-18 5:59 [Intel-gfx] [PATCH v8 0/6] Enable YCbCr420 for VDSC Suraj Kandpal
` (3 preceding siblings ...)
2023-01-18 6:00 ` [Intel-gfx] [PATCH v8 4/6] drm/i915: Enable YCbCr420 for VDSC Suraj Kandpal
@ 2023-01-18 6:00 ` Suraj Kandpal
2023-01-18 6:00 ` [Intel-gfx] [PATCH v8 6/6] drm/i915/vdsc: Check slice design requirement Suraj Kandpal
` (8 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Suraj Kandpal @ 2023-01-18 6:00 UTC (permalink / raw)
To: intel-gfx
Now that we have laid the groundwork for YUV420 Enablement
we fill up native_420 field in vdsc_cfg and add appropriate
checks wherever required.
---v2
-adding native_422 field as 0 [Vandita]
-filling in second_line_bpg_offset, second_line_offset_adj
and nsl_bpg_offset in vds_cfg when native_420 is true
---v3
-adding display version check to solve igt issue
--v7
-remove is_pipe_dsc check as its always true for D14 [Jani]
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 -
drivers/gpu/drm/i915/display/intel_dp.c | 3 -
drivers/gpu/drm/i915/display/intel_vdsc.c | 72 ++++++++++++++++++++++-
3 files changed, 69 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index ae14c794c4bc..ff9e15dd7595 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1626,8 +1626,6 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
if (crtc_state->dsc.slice_count > 1)
crtc_state->dsc.dsc_split = true;
- vdsc_cfg->convert_rgb = true;
-
/* FIXME: initialize from VBT */
vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6e531872ff38..2adac42e585d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1459,9 +1459,6 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
min(intel_dp_source_dsc_version_minor(intel_dp),
intel_dp_sink_dsc_version_minor(intel_dp));
- vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
- DP_DSC_RGB;
-
line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
if (!line_buf_depth) {
drm_dbg_kms(&i915->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index ed16f63d6355..13ad853e24eb 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -460,14 +460,47 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
pipe_config->dsc.slice_count);
-
- /* Gen 11 does not support YCbCr */
+ /*
+ * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
+ * else 1
+ */
+ vdsc_cfg->convert_rgb = !(pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
+ pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444);
+
+ if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ vdsc_cfg->native_420 = true;
+ /* We do not support YcBCr422 as of now */
+ vdsc_cfg->native_422 = false;
+ /* Gen 11 does not support YCbCr422 */
vdsc_cfg->simple_422 = false;
/* Gen 11 does not support VBR */
vdsc_cfg->vbr_enable = false;
/* Gen 11 only supports integral values of bpp */
vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
+ /*
+ * According to DSC 1.2 specs if native_420 is set:
+ * -We need to double the current bpp.
+ * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if slice
+ * height < 8.
+ * -second_line_offset_adj is 512 as shown by emperical values to yeild best chroma
+ * preservation in second line.
+ * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then rounded
+ * up to 16 fractional bits, we left shift second line offset by 11 to preserve 11
+ * fractional bits.
+ */
+ if (vdsc_cfg->native_420) {
+ vdsc_cfg->bits_per_pixel <<= 1;
+ if (vdsc_cfg->slice_height >= 8)
+ vdsc_cfg->second_line_bpg_offset = 12;
+ else
+ vdsc_cfg->second_line_bpg_offset =
+ 2 * (vdsc_cfg->slice_height - 1);
+ vdsc_cfg->second_line_offset_adj = 512;
+ vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11,
+ vdsc_cfg->slice_height - 1);
+ }
+
vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
@@ -594,8 +627,13 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
DSC_VER_MIN_SHIFT |
vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
- if (vdsc_cfg->dsc_version_minor == 2)
+ if (vdsc_cfg->dsc_version_minor == 2) {
pps_val |= DSC_ALT_ICH_SEL;
+ if (vdsc_cfg->native_420)
+ pps_val |= DSC_NATIVE_420_ENABLE;
+ if (vdsc_cfg->native_422)
+ pps_val |= DSC_NATIVE_422_ENABLE;
+ }
if (vdsc_cfg->block_pred_enable)
pps_val |= DSC_BLOCK_PREDICTION;
if (vdsc_cfg->convert_rgb)
@@ -906,6 +944,34 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
pps_val);
}
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ /* Populate PICTURE_PARAMETER_SET_17 registers */
+ pps_val = 0;
+ pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
+ drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
+ intel_de_write(dev_priv,
+ MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe),
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(dev_priv,
+ MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe),
+ pps_val);
+
+ /* Populate PICTURE_PARAMETER_SET_18 registers */
+ pps_val = 0;
+ pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
+ DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
+ drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
+ if (is_pipe_dsc(crtc, cpu_transcoder)) {
+ intel_de_write(dev_priv,
+ MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe),
+ pps_val);
+ if (crtc_state->dsc.dsc_split)
+ intel_de_write(dev_priv,
+ MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe),
+ pps_val);
+ }
+ }
/* Populate the RC_BUF_THRESH registers */
memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v8 6/6] drm/i915/vdsc: Check slice design requirement
2023-01-18 5:59 [Intel-gfx] [PATCH v8 0/6] Enable YCbCr420 for VDSC Suraj Kandpal
` (4 preceding siblings ...)
2023-01-18 6:00 ` [Intel-gfx] [PATCH v8 5/6] drm/i915: Fill in native_420 field Suraj Kandpal
@ 2023-01-18 6:00 ` Suraj Kandpal
2023-01-31 4:37 ` [Intel-gfx] [PATCH v9 " Suraj Kandpal
2023-01-18 6:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable YCbCr420 for VDSC Patchwork
` (7 subsequent siblings)
13 siblings, 1 reply; 16+ messages in thread
From: Suraj Kandpal @ 2023-01-18 6:00 UTC (permalink / raw)
To: intel-gfx
Add function to check if slice design requirements are being
met as defined in Bspec: 49259 in the section
Slice Design Requirement
--v7
-remove full bspec link [Jani]
-rename intel_dsc_check_slice_design_req to
intel_dsc_slice_dimensions_valid [Jani]
--v8
-fix condition to check if slice width and height are
of two
-fix minimum pixel in slice condition
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 32 +++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 13ad853e24eb..6ebefc195e83 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -447,6 +447,29 @@ calculate_rc_params(struct rc_parameters *rc,
}
}
+static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state *pipe_config,
+ struct drm_dsc_config *vdsc_cfg)
+{
+ if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB ||
+ pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
+ if (vdsc_cfg->slice_height > 4095)
+ return -EINVAL;
+ if (vdsc_cfg->slice_height * vdsc_cfg->slice_width >= 15000)
+ return -EINVAL;
+ } else if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
+ if (vdsc_cfg->slice_width % 2)
+ return -EINVAL;
+ if (vdsc_cfg->slice_height % 2)
+ return -EINVAL;
+ if (vdsc_cfg->slice_height > 4094)
+ return -EINVAL;
+ if (vdsc_cfg->slice_height * vdsc_cfg->slice_width >= 30000)
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
{
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
@@ -455,11 +478,20 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
const struct rc_parameters *rc_params;
struct rc_parameters *rc = NULL;
+ int err;
u8 i = 0;
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
pipe_config->dsc.slice_count);
+
+ err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg);
+
+ if (err) {
+ drm_dbg_kms(&dev_priv->drm, "Slice dimension requirements not met\n");
+ return err;
+ }
+
/*
* According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
* else 1
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable YCbCr420 for VDSC
2023-01-18 5:59 [Intel-gfx] [PATCH v8 0/6] Enable YCbCr420 for VDSC Suraj Kandpal
` (5 preceding siblings ...)
2023-01-18 6:00 ` [Intel-gfx] [PATCH v8 6/6] drm/i915/vdsc: Check slice design requirement Suraj Kandpal
@ 2023-01-18 6:19 ` Patchwork
2023-01-18 6:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (6 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2023-01-18 6:19 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
== Series Details ==
Series: Enable YCbCr420 for VDSC
URL : https://patchwork.freedesktop.org/series/112993/
State : warning
== Summary ==
Error: dim checkpatch failed
744170a1110d drm/dp_helper: Add helper to check if the sink supports given format with DSC
17cba7d62236 drm/i915/dp: Check if DSC supports the given output_format
98689fb69bc8 drm/i915: Adding the new registers for DSC
0d3a34008e55 drm/i915: Enable YCbCr420 for VDSC
-:199: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_row' - possible side-effects?
#199: FILE: drivers/gpu/drm/i915/display/intel_qp_tables.c:447:
+#define PARAM_TABLE(_minmax, _bpc, _row, _col, _is_420) do { \
+ if (bpc == (_bpc)) { \
+ if (_is_420) \
+ return rc_range_##_minmax##qp420_##_bpc##bpc[_row][_col]; \
+ else \
+ return rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
+ } \
} while (0)
-:199: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_col' - possible side-effects?
#199: FILE: drivers/gpu/drm/i915/display/intel_qp_tables.c:447:
+#define PARAM_TABLE(_minmax, _bpc, _row, _col, _is_420) do { \
+ if (bpc == (_bpc)) { \
+ if (_is_420) \
+ return rc_range_##_minmax##qp420_##_bpc##bpc[_row][_col]; \
+ else \
+ return rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
+ } \
} while (0)
total: 0 errors, 0 warnings, 2 checks, 228 lines checked
219616799a62 drm/i915: Fill in native_420 field
2fcd5e2628ea drm/i915/vdsc: Check slice design requirement
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Enable YCbCr420 for VDSC
2023-01-18 5:59 [Intel-gfx] [PATCH v8 0/6] Enable YCbCr420 for VDSC Suraj Kandpal
` (6 preceding siblings ...)
2023-01-18 6:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable YCbCr420 for VDSC Patchwork
@ 2023-01-18 6:34 ` Patchwork
2023-01-18 16:52 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
` (5 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2023-01-18 6:34 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5442 bytes --]
== Series Details ==
Series: Enable YCbCr420 for VDSC
URL : https://patchwork.freedesktop.org/series/112993/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12596 -> Patchwork_112993v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/index.html
Participating hosts (44 -> 43)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_112993v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3@smem:
- fi-rkl-11600: NOTRUN -> [INCOMPLETE][1] ([i915#7793])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/fi-rkl-11600/igt@gem_exec_suspend@basic-s3@smem.html
- fi-skl-6600u: [PASS][2] -> [FAIL][3] ([fdo#103375])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/fi-skl-6600u/igt@gem_exec_suspend@basic-s3@smem.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/fi-skl-6600u/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-skl-6600u: [PASS][4] -> [DMESG-FAIL][5] ([i915#5334])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/fi-skl-6600u/igt@i915_selftest@live@gt_heartbeat.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/fi-skl-6600u/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-n3050: [PASS][6] -> [FAIL][7] ([i915#6298])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html
#### Possible fixes ####
* igt@i915_selftest@live@gem:
- {bat-adln-1}: [DMESG-WARN][8] ([i915#2867]) -> [PASS][9] +9 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/bat-adln-1/igt@i915_selftest@live@gem.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/bat-adln-1/igt@i915_selftest@live@gem.html
* igt@i915_selftest@live@hangcheck:
- {bat-dg2-8}: [INCOMPLETE][10] ([i915#7834]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/bat-dg2-8/igt@i915_selftest@live@hangcheck.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/bat-dg2-8/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- {bat-rpls-2}: [INCOMPLETE][12] ([i915#6257]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/bat-rpls-2/igt@i915_selftest@live@requests.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/bat-rpls-2/igt@i915_selftest@live@requests.html
#### Warnings ####
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [INCOMPLETE][14] ([i915#4817]) -> [FAIL][15] ([fdo#103375])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7609]: https://gitlab.freedesktop.org/drm/intel/issues/7609
[i915#7793]: https://gitlab.freedesktop.org/drm/intel/issues/7793
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7834]: https://gitlab.freedesktop.org/drm/intel/issues/7834
Build changes
-------------
* Linux: CI_DRM_12596 -> Patchwork_112993v1
CI-20190529: 20190529
CI_DRM_12596: 0a0ee61784df01ac098a92bd43673ee30c629f13 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7121: aa16e81259f59734230d441905b9d0f605e4a4b5 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_112993v1: 0a0ee61784df01ac098a92bd43673ee30c629f13 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
d0975aa09876 drm/i915/vdsc: Check slice design requirement
575cb490568a drm/i915: Fill in native_420 field
2df628d9481c drm/i915: Enable YCbCr420 for VDSC
07d85aba5819 drm/i915: Adding the new registers for DSC
406102f3b3cc drm/i915/dp: Check if DSC supports the given output_format
448009727a7b drm/dp_helper: Add helper to check if the sink supports given format with DSC
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/index.html
[-- Attachment #2: Type: text/html, Size: 5928 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Enable YCbCr420 for VDSC
2023-01-18 5:59 [Intel-gfx] [PATCH v8 0/6] Enable YCbCr420 for VDSC Suraj Kandpal
` (7 preceding siblings ...)
2023-01-18 6:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-01-18 16:52 ` Patchwork
2023-01-31 4:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable YCbCr420 for VDSC (rev2) Patchwork
` (4 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2023-01-18 16:52 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 22524 bytes --]
== Series Details ==
Series: Enable YCbCr420 for VDSC
URL : https://patchwork.freedesktop.org/series/112993/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12596_full -> Patchwork_112993v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/index.html
Participating hosts (12 -> 9)
------------------------------
Missing (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005
Known issues
------------
Here are the changes found in Patchwork_112993v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_vblank@pipe-a-accuracy-idle:
- shard-glk: [PASS][1] -> [FAIL][2] ([i915#43])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-glk2/igt@kms_vblank@pipe-a-accuracy-idle.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-glk1/igt@kms_vblank@pipe-a-accuracy-idle.html
#### Possible fixes ####
* igt@api_intel_bb@object-reloc-keep-cache:
- {shard-rkl}: [SKIP][3] ([i915#3281]) -> [PASS][4] +6 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-rkl-2/igt@api_intel_bb@object-reloc-keep-cache.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-rkl-5/igt@api_intel_bb@object-reloc-keep-cache.html
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- {shard-rkl}: [FAIL][5] ([i915#7742]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-rkl-1/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-rkl-4/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@fbdev@unaligned-write:
- {shard-rkl}: [SKIP][7] ([i915#2582]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-rkl-5/igt@fbdev@unaligned-write.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-rkl-6/igt@fbdev@unaligned-write.html
* igt@gem_create@hog-create@smem0:
- {shard-rkl}: [FAIL][9] ([i915#7679]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-rkl-2/igt@gem_create@hog-create@smem0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-rkl-5/igt@gem_create@hog-create@smem0.html
* igt@gem_ctx_persistence@smoketest:
- {shard-rkl}: [FAIL][11] ([i915#5099]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-rkl-2/igt@gem_ctx_persistence@smoketest.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-rkl-3/igt@gem_ctx_persistence@smoketest.html
* igt@gem_exec_fair@basic-deadline:
- {shard-rkl}: [FAIL][13] ([i915#2846]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-rkl-2/igt@gem_exec_fair@basic-deadline.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-rkl-1/igt@gem_exec_fair@basic-deadline.html
- shard-glk: [FAIL][15] ([i915#2846]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-glk5/igt@gem_exec_fair@basic-deadline.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-glk4/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- {shard-rkl}: [FAIL][17] ([i915#2842]) -> [PASS][18] +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-rkl-2/igt@gem_exec_fair@basic-throttle@rcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-rkl-5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- {shard-rkl}: [SKIP][19] ([fdo#109313]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-rkl-6/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-rkl-5/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_reloc@basic-scanout@vcs0:
- {shard-tglu}: [SKIP][21] ([i915#3639]) -> [PASS][22] +4 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-tglu-6/igt@gem_exec_reloc@basic-scanout@vcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-tglu-1/igt@gem_exec_reloc@basic-scanout@vcs0.html
* igt@gem_pwrite@basic-self:
- {shard-rkl}: [SKIP][23] ([i915#3282]) -> [PASS][24] +3 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-rkl-2/igt@gem_pwrite@basic-self.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-rkl-5/igt@gem_pwrite@basic-self.html
* igt@gen9_exec_parse@bb-start-param:
- {shard-rkl}: [SKIP][25] ([i915#2527]) -> [PASS][26] +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-rkl-2/igt@gen9_exec_parse@bb-start-param.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-rkl-5/igt@gen9_exec_parse@bb-start-param.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- {shard-rkl}: [WARN][27] ([i915#2681]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-rkl-6/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
* igt@i915_pm_rpm@drm-resources-equal:
- {shard-tglu}: [SKIP][29] ([i915#3547]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-tglu-6/igt@i915_pm_rpm@drm-resources-equal.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-tglu-1/igt@i915_pm_rpm@drm-resources-equal.html
* igt@i915_suspend@basic-s3-without-i915:
- {shard-rkl}: [FAIL][31] ([fdo#103375]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-rkl-3/igt@i915_suspend@basic-s3-without-i915.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-rkl-1/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- {shard-tglu}: [SKIP][33] ([i915#1845] / [i915#7651]) -> [PASS][34] +5 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-tglu-6/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-tglu-1/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-180:
- {shard-tglu}: [SKIP][35] ([i915#7651]) -> [PASS][36] +20 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-tglu-6/igt@kms_big_fb@x-tiled-8bpp-rotate-180.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-tglu-1/igt@kms_big_fb@x-tiled-8bpp-rotate-180.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [FAIL][37] ([i915#72]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-glk9/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-glk: [FAIL][39] ([i915#2346]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
* igt@kms_flip@plain-flip-ts-check-interruptible@b-hdmi-a1:
- shard-glk: [FAIL][41] ([i915#2122]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-glk1/igt@kms_flip@plain-flip-ts-check-interruptible@b-hdmi-a1.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-glk8/igt@kms_flip@plain-flip-ts-check-interruptible@b-hdmi-a1.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt:
- {shard-tglu}: [SKIP][43] ([i915#1849]) -> [PASS][44] +3 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-tglu-6/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-tglu-3/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt:
- {shard-rkl}: [SKIP][45] ([i915#1849] / [i915#4098]) -> [PASS][46] +13 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
* igt@kms_plane@plane-panning-bottom-right@pipe-a-planes:
- {shard-rkl}: [SKIP][47] ([i915#1849]) -> [PASS][48] +2 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-rkl-1/igt@kms_plane@plane-panning-bottom-right@pipe-a-planes.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-rkl-6/igt@kms_plane@plane-panning-bottom-right@pipe-a-planes.html
* igt@kms_plane@plane-position-hole@pipe-b-planes:
- {shard-tglu}: [SKIP][49] ([i915#1849] / [i915#3558]) -> [PASS][50] +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-tglu-6/igt@kms_plane@plane-position-hole@pipe-b-planes.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-tglu-3/igt@kms_plane@plane-position-hole@pipe-b-planes.html
* igt@kms_psr@primary_blt:
- {shard-rkl}: [SKIP][51] ([i915#1072]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-rkl-1/igt@kms_psr@primary_blt.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-rkl-6/igt@kms_psr@primary_blt.html
* igt@kms_rotation_crc@exhaust-fences:
- {shard-rkl}: [SKIP][53] ([i915#1845] / [i915#4098]) -> [PASS][54] +24 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-rkl-5/igt@kms_rotation_crc@exhaust-fences.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-rkl-6/igt@kms_rotation_crc@exhaust-fences.html
* igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-b:
- {shard-rkl}: [SKIP][55] ([i915#4098]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-rkl-5/igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-b.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-rkl-6/igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-b.html
* igt@kms_universal_plane@universal-plane-pipe-a-functional:
- {shard-tglu}: [SKIP][57] ([fdo#109274]) -> [PASS][58] +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-tglu-6/igt@kms_universal_plane@universal-plane-pipe-a-functional.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-tglu-3/igt@kms_universal_plane@universal-plane-pipe-a-functional.html
* igt@perf@mi-rpc:
- {shard-rkl}: [SKIP][59] ([i915#2434]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-rkl-6/igt@perf@mi-rpc.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-rkl-5/igt@perf@mi-rpc.html
* igt@perf@polling-small-buf:
- {shard-rkl}: [FAIL][61] ([i915#1722]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-rkl-2/igt@perf@polling-small-buf.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-rkl-5/igt@perf@polling-small-buf.html
* igt@perf_pmu@idle@rcs0:
- {shard-dg1}: [FAIL][63] ([i915#4349]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-dg1-19/igt@perf_pmu@idle@rcs0.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-dg1-18/igt@perf_pmu@idle@rcs0.html
* igt@sysfs_timeslice_duration@timeout@rcs0:
- {shard-dg1}: [FAIL][65] ([i915#1755]) -> [PASS][66] +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12596/shard-dg1-15/igt@sysfs_timeslice_duration@timeout@rcs0.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/shard-dg1-15/igt@sysfs_timeslice_duration@timeout@rcs0.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3639]: https://gitlab.freedesktop.org/drm/intel/issues/3639
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#43]: https://gitlab.freedesktop.org/drm/intel/issues/43
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
[i915#5099]: https://gitlab.freedesktop.org/drm/intel/issues/5099
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
[i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
[i915#6403]: https://gitlab.freedesktop.org/drm/intel/issues/6403
[i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7679]: https://gitlab.freedesktop.org/drm/intel/issues/7679
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
Build changes
-------------
* Linux: CI_DRM_12596 -> Patchwork_112993v1
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_12596: 0a0ee61784df01ac098a92bd43673ee30c629f13 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7121: aa16e81259f59734230d441905b9d0f605e4a4b5 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_112993v1: 0a0ee61784df01ac098a92bd43673ee30c629f13 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v1/index.html
[-- Attachment #2: Type: text/html, Size: 17559 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v9 6/6] drm/i915/vdsc: Check slice design requirement
2023-01-18 6:00 ` [Intel-gfx] [PATCH v8 6/6] drm/i915/vdsc: Check slice design requirement Suraj Kandpal
@ 2023-01-31 4:37 ` Suraj Kandpal
0 siblings, 0 replies; 16+ messages in thread
From: Suraj Kandpal @ 2023-01-31 4:37 UTC (permalink / raw)
To: intel-gfx
Add function to check if slice design requirements are being
met as defined in Bspec: 49259 in the section
Slice Design Requirement
--v7
-remove full bspec link [Jani]
-rename intel_dsc_check_slice_design_req to
intel_dsc_slice_dimensions_valid [Jani]
--v8
-fix condition to check if slice width and height are
of two
-fix minimum pixel in slice condition
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 32 +++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 13ad853e24eb..6ebefc195e83 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -447,6 +447,29 @@ calculate_rc_params(struct rc_parameters *rc,
}
}
+static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state *pipe_config,
+ struct drm_dsc_config *vdsc_cfg)
+{
+ if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB ||
+ pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
+ if (vdsc_cfg->slice_height > 4095)
+ return -EINVAL;
+ if (vdsc_cfg->slice_height * vdsc_cfg->slice_width <= 15000)
+ return -EINVAL;
+ } else if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
+ if (vdsc_cfg->slice_width % 2)
+ return -EINVAL;
+ if (vdsc_cfg->slice_height % 2)
+ return -EINVAL;
+ if (vdsc_cfg->slice_height > 4094)
+ return -EINVAL;
+ if (vdsc_cfg->slice_height * vdsc_cfg->slice_width <= 30000)
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
{
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
@@ -455,11 +478,20 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
const struct rc_parameters *rc_params;
struct rc_parameters *rc = NULL;
+ int err;
u8 i = 0;
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
pipe_config->dsc.slice_count);
+
+ err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg);
+
+ if (err) {
+ drm_dbg_kms(&dev_priv->drm, "Slice dimension requirements not met\n");
+ return err;
+ }
+
/*
* According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
* else 1
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable YCbCr420 for VDSC (rev2)
2023-01-18 5:59 [Intel-gfx] [PATCH v8 0/6] Enable YCbCr420 for VDSC Suraj Kandpal
` (8 preceding siblings ...)
2023-01-18 16:52 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2023-01-31 4:55 ` Patchwork
2023-01-31 5:10 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (3 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2023-01-31 4:55 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
== Series Details ==
Series: Enable YCbCr420 for VDSC (rev2)
URL : https://patchwork.freedesktop.org/series/112993/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for Enable YCbCr420 for VDSC (rev2)
2023-01-18 5:59 [Intel-gfx] [PATCH v8 0/6] Enable YCbCr420 for VDSC Suraj Kandpal
` (9 preceding siblings ...)
2023-01-31 4:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable YCbCr420 for VDSC (rev2) Patchwork
@ 2023-01-31 5:10 ` Patchwork
2023-01-31 9:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable YCbCr420 for VDSC (rev3) Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2023-01-31 5:10 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 2711 bytes --]
== Series Details ==
Series: Enable YCbCr420 for VDSC (rev2)
URL : https://patchwork.freedesktop.org/series/112993/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12669 -> Patchwork_112993v2
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_112993v2 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_112993v2, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v2/index.html
Participating hosts (25 -> 24)
------------------------------
Missing (1): fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_112993v2:
### IGT changes ###
#### Possible regressions ####
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-1:
- fi-apl-guc: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12669/fi-apl-guc/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v2/fi-apl-guc/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-1.html
Known issues
------------
Here are the changes found in Patchwork_112993v2 that come from known issues:
### IGT changes ###
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
Build changes
-------------
* Linux: CI_DRM_12669 -> Patchwork_112993v2
CI-20190529: 20190529
CI_DRM_12669: 0ba44f2494c482325e1a25982c2e0754cbee2a48 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7143: c7b12dcc460fc2348e1fa7f4dcb791bb82e29e44 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_112993v2: 0ba44f2494c482325e1a25982c2e0754cbee2a48 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
b59922ae7675 drm/i915/vdsc: Check slice design requirement
370639404544 drm/i915: Fill in native_420 field
a1fb6aeb17ae drm/i915: Enable YCbCr420 for VDSC
6046c8096822 drm/i915: Adding the new registers for DSC
44972ac25002 drm/i915/dp: Check if DSC supports the given output_format
f5523b62eb21 drm/dp_helper: Add helper to check if the sink supports given format with DSC
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v2/index.html
[-- Attachment #2: Type: text/html, Size: 3225 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable YCbCr420 for VDSC (rev3)
2023-01-18 5:59 [Intel-gfx] [PATCH v8 0/6] Enable YCbCr420 for VDSC Suraj Kandpal
` (10 preceding siblings ...)
2023-01-31 5:10 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2023-01-31 9:01 ` Patchwork
2023-01-31 9:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-01-31 11:54 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
13 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2023-01-31 9:01 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
== Series Details ==
Series: Enable YCbCr420 for VDSC (rev3)
URL : https://patchwork.freedesktop.org/series/112993/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Enable YCbCr420 for VDSC (rev3)
2023-01-18 5:59 [Intel-gfx] [PATCH v8 0/6] Enable YCbCr420 for VDSC Suraj Kandpal
` (11 preceding siblings ...)
2023-01-31 9:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable YCbCr420 for VDSC (rev3) Patchwork
@ 2023-01-31 9:13 ` Patchwork
2023-01-31 11:54 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
13 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2023-01-31 9:13 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3188 bytes --]
== Series Details ==
Series: Enable YCbCr420 for VDSC (rev3)
URL : https://patchwork.freedesktop.org/series/112993/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12670 -> Patchwork_112993v3
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/index.html
Participating hosts (25 -> 24)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_112993v3 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][1] ([i915#5334]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@guc:
- {bat-rpls-2}: [DMESG-WARN][3] ([i915#7852]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/bat-rpls-2/igt@i915_selftest@live@guc.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/bat-rpls-2/igt@i915_selftest@live@guc.html
* igt@kms_pipe_crc_basic@read-crc@pipe-c-dp-1:
- {bat-adlp-9}: [FAIL][5] ([i915#4137]) -> [PASS][6] +3 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/bat-adlp-9/igt@kms_pipe_crc_basic@read-crc@pipe-c-dp-1.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/bat-adlp-9/igt@kms_pipe_crc_basic@read-crc@pipe-c-dp-1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#4137]: https://gitlab.freedesktop.org/drm/intel/issues/4137
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7852]: https://gitlab.freedesktop.org/drm/intel/issues/7852
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
Build changes
-------------
* Linux: CI_DRM_12670 -> Patchwork_112993v3
CI-20190529: 20190529
CI_DRM_12670: d98d1a109aa7df08b5398b29e2e90ba50b3f680a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7143: c7b12dcc460fc2348e1fa7f4dcb791bb82e29e44 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_112993v3: d98d1a109aa7df08b5398b29e2e90ba50b3f680a @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
7dc50fe6dbc6 drm/i915/vdsc: Check slice design requirement
fd08bb09137e drm/i915: Fill in native_420 field
b43572fc4165 drm/i915: Enable YCbCr420 for VDSC
689b8f01b3fd drm/i915: Adding the new registers for DSC
726ab66bbcd1 drm/i915/dp: Check if DSC supports the given output_format
2f3088c92334 drm/dp_helper: Add helper to check if the sink supports given format with DSC
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/index.html
[-- Attachment #2: Type: text/html, Size: 3686 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Enable YCbCr420 for VDSC (rev3)
2023-01-18 5:59 [Intel-gfx] [PATCH v8 0/6] Enable YCbCr420 for VDSC Suraj Kandpal
` (12 preceding siblings ...)
2023-01-31 9:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-01-31 11:54 ` Patchwork
13 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2023-01-31 11:54 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 20655 bytes --]
== Series Details ==
Series: Enable YCbCr420 for VDSC (rev3)
URL : https://patchwork.freedesktop.org/series/112993/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12670_full -> Patchwork_112993v3_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/index.html
Participating hosts (10 -> 11)
------------------------------
Additional (1): shard-rkl0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_112993v3_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_capture@pi@vcs1:
- {shard-tglu}: NOTRUN -> [ABORT][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-tglu-5/igt@gem_exec_capture@pi@vcs1.html
Known issues
------------
Here are the changes found in Patchwork_112993v3_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [PASS][2] -> [ABORT][3] ([i915#5566])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-glk2/igt@gen9_exec_parse@allowed-single.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-glk6/igt@gen9_exec_parse@allowed-single.html
* igt@kms_vblank@pipe-a-accuracy-idle:
- shard-glk: [PASS][4] -> [FAIL][5] ([i915#43])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-glk5/igt@kms_vblank@pipe-a-accuracy-idle.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-glk5/igt@kms_vblank@pipe-a-accuracy-idle.html
#### Possible fixes ####
* igt@drm_fdinfo@virtual-idle:
- {shard-rkl}: [FAIL][6] ([i915#7742]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-rkl-6/igt@drm_fdinfo@virtual-idle.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-rkl-1/igt@drm_fdinfo@virtual-idle.html
* igt@fbdev@unaligned-read:
- {shard-rkl}: [SKIP][8] ([i915#2582]) -> [PASS][9] +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-rkl-5/igt@fbdev@unaligned-read.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-rkl-6/igt@fbdev@unaligned-read.html
* igt@gem_bad_reloc@negative-reloc-lut:
- {shard-rkl}: [SKIP][10] ([i915#3281]) -> [PASS][11] +10 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-rkl-3/igt@gem_bad_reloc@negative-reloc-lut.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-rkl-5/igt@gem_bad_reloc@negative-reloc-lut.html
* igt@gem_ctx_persistence@engines-hang@bcs0:
- {shard-rkl}: [SKIP][12] ([i915#6252]) -> [PASS][13] +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-rkl-5/igt@gem_ctx_persistence@engines-hang@bcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-rkl-6/igt@gem_ctx_persistence@engines-hang@bcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- {shard-rkl}: [FAIL][14] ([i915#2842]) -> [PASS][15] +2 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-rkl-3/igt@gem_exec_fair@basic-none-vip@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-rkl-5/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- {shard-tglu-9}: [FAIL][16] ([i915#2842]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-tglu-9/igt@gem_exec_fair@basic-pace-share@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-tglu-9/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_pwrite@basic-self:
- {shard-rkl}: [SKIP][18] ([i915#3282]) -> [PASS][19] +3 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-rkl-2/igt@gem_pwrite@basic-self.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-rkl-5/igt@gem_pwrite@basic-self.html
* igt@gen9_exec_parse@valid-registers:
- {shard-rkl}: [SKIP][20] ([i915#2527]) -> [PASS][21] +3 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-rkl-1/igt@gen9_exec_parse@valid-registers.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-rkl-5/igt@gen9_exec_parse@valid-registers.html
* igt@i915_hangman@gt-engine-error@bcs0:
- {shard-rkl}: [SKIP][22] ([i915#6258]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-rkl-5/igt@i915_hangman@gt-engine-error@bcs0.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-rkl-4/igt@i915_hangman@gt-engine-error@bcs0.html
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- {shard-dg1}: [SKIP][24] ([i915#1397]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-dg1-14/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-dg1-15/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
* {igt@i915_power@sanity}:
- {shard-rkl}: [SKIP][26] ([i915#7984]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-rkl-3/igt@i915_power@sanity.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-rkl-5/igt@i915_power@sanity.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-glk: [FAIL][28] ([i915#2346]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@psr-suspend:
- {shard-rkl}: [SKIP][30] ([i915#3955]) -> [PASS][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-rkl-4/igt@kms_fbcon_fbt@psr-suspend.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-rkl-6/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@2x-plain-flip-fb-recreate@ac-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][32] ([i915#2122]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-glk4/igt@kms_flip@2x-plain-flip-fb-recreate@ac-hdmi-a1-hdmi-a2.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-glk8/igt@kms_flip@2x-plain-flip-fb-recreate@ac-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2:
- shard-glk: [FAIL][34] ([i915#79]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-glk3/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-glk2/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- {shard-rkl}: [SKIP][36] ([i915#1849] / [i915#4098]) -> [PASS][37] +16 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_plane@plane-position-covered@pipe-a-planes:
- {shard-rkl}: [SKIP][38] ([i915#1849]) -> [PASS][39] +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-rkl-5/igt@kms_plane@plane-position-covered@pipe-a-planes.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-rkl-6/igt@kms_plane@plane-position-covered@pipe-a-planes.html
* igt@kms_psr@primary_mmap_gtt:
- {shard-rkl}: [SKIP][40] ([i915#1072]) -> [PASS][41] +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-rkl-5/igt@kms_psr@primary_mmap_gtt.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-rkl-6/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- {shard-rkl}: [SKIP][42] ([i915#5461]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-rkl-1/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-rkl-6/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
- {shard-rkl}: [SKIP][44] ([i915#1845] / [i915#4098]) -> [PASS][45] +18 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-rkl-5/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-rkl-6/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
* igt@perf@polling-small-buf:
- {shard-rkl}: [FAIL][46] ([i915#1722]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-rkl-1/igt@perf@polling-small-buf.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-rkl-5/igt@perf@polling-small-buf.html
* igt@prime_vgem@basic-fence-read:
- {shard-rkl}: [SKIP][48] ([fdo#109295] / [i915#3291] / [i915#3708]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-rkl-2/igt@prime_vgem@basic-fence-read.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-rkl-5/igt@prime_vgem@basic-fence-read.html
* igt@testdisplay:
- {shard-rkl}: [SKIP][50] ([i915#4098]) -> [PASS][51] +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12670/shard-rkl-4/igt@testdisplay.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/shard-rkl-6/igt@testdisplay.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3639]: https://gitlab.freedesktop.org/drm/intel/issues/3639
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#43]: https://gitlab.freedesktop.org/drm/intel/issues/43
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
[i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
[i915#6355]: https://gitlab.freedesktop.org/drm/intel/issues/6355
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7949]: https://gitlab.freedesktop.org/drm/intel/issues/7949
[i915#7984]: https://gitlab.freedesktop.org/drm/intel/issues/7984
Build changes
-------------
* Linux: CI_DRM_12670 -> Patchwork_112993v3
CI-20190529: 20190529
CI_DRM_12670: d98d1a109aa7df08b5398b29e2e90ba50b3f680a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7143: c7b12dcc460fc2348e1fa7f4dcb791bb82e29e44 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_112993v3: d98d1a109aa7df08b5398b29e2e90ba50b3f680a @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112993v3/index.html
[-- Attachment #2: Type: text/html, Size: 14163 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2023-01-31 11:54 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-01-18 5:59 [Intel-gfx] [PATCH v8 0/6] Enable YCbCr420 for VDSC Suraj Kandpal
2023-01-18 5:59 ` [Intel-gfx] [PATCH v8 1/6] drm/dp_helper: Add helper to check if the sink supports given format with DSC Suraj Kandpal
2023-01-18 5:59 ` [Intel-gfx] [PATCH v8 2/6] drm/i915/dp: Check if DSC supports the given output_format Suraj Kandpal
2023-01-18 5:59 ` [Intel-gfx] [PATCH v8 3/6] drm/i915: Adding the new registers for DSC Suraj Kandpal
2023-01-18 6:00 ` [Intel-gfx] [PATCH v8 4/6] drm/i915: Enable YCbCr420 for VDSC Suraj Kandpal
2023-01-18 6:00 ` [Intel-gfx] [PATCH v8 5/6] drm/i915: Fill in native_420 field Suraj Kandpal
2023-01-18 6:00 ` [Intel-gfx] [PATCH v8 6/6] drm/i915/vdsc: Check slice design requirement Suraj Kandpal
2023-01-31 4:37 ` [Intel-gfx] [PATCH v9 " Suraj Kandpal
2023-01-18 6:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable YCbCr420 for VDSC Patchwork
2023-01-18 6:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-01-18 16:52 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-01-31 4:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable YCbCr420 for VDSC (rev2) Patchwork
2023-01-31 5:10 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-01-31 9:01 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable YCbCr420 for VDSC (rev3) Patchwork
2023-01-31 9:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-01-31 11:54 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.