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* [PATCH] irqchip/loongson-liointc: Save/restore int_edge/int_pol registers during S3/S4
@ 2022-12-07 14:06 Huacai Chen
  2023-01-19 12:44 ` Huacai Chen
  2023-02-05 11:29 ` [irqchip: irq/irqchip-next] " irqchip-bot for Huacai Chen
  0 siblings, 2 replies; 3+ messages in thread
From: Huacai Chen @ 2022-12-07 14:06 UTC (permalink / raw)
  To: Thomas Gleixner, Marc Zyngier
  Cc: loongarch, linux-kernel, Xuefeng Li, Huacai Chen, Jiaxun Yang,
	Huacai Chen, Yingkun Meng

If int_edge/int_pol registers are configured to not be the default values, we
should save/restore them during S3/S4.

Signed-off-by: Yingkun Meng <mengyingkun@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 drivers/irqchip/irq-loongson-liointc.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index c116f70929ae..4367ce9b558f 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -55,6 +55,8 @@ struct liointc_priv {
 	struct liointc_handler_data	handler[LIOINTC_NUM_PARENT];
 	void __iomem			*core_isr[LIOINTC_NUM_CORES];
 	u8				map_cache[LIOINTC_CHIP_IRQ];
+	u32				int_pol;
+	u32				int_edge;
 	bool				has_lpc_irq_errata;
 };
 
@@ -138,6 +140,14 @@ static int liointc_set_type(struct irq_data *data, unsigned int type)
 	return 0;
 }
 
+static void liointc_suspend(struct irq_chip_generic *gc)
+{
+	struct liointc_priv *priv = gc->private;
+
+	priv->int_pol = readl(gc->reg_base + LIOINTC_REG_INTC_POL);
+	priv->int_edge = readl(gc->reg_base + LIOINTC_REG_INTC_EDGE);
+}
+
 static void liointc_resume(struct irq_chip_generic *gc)
 {
 	struct liointc_priv *priv = gc->private;
@@ -150,6 +160,8 @@ static void liointc_resume(struct irq_chip_generic *gc)
 	/* Restore map cache */
 	for (i = 0; i < LIOINTC_CHIP_IRQ; i++)
 		writeb(priv->map_cache[i], gc->reg_base + i);
+	writel(priv->int_pol, gc->reg_base + LIOINTC_REG_INTC_POL);
+	writel(priv->int_edge, gc->reg_base + LIOINTC_REG_INTC_EDGE);
 	/* Restore mask cache */
 	writel(gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
 	irq_gc_unlock_irqrestore(gc, flags);
@@ -261,6 +273,7 @@ static int liointc_init(phys_addr_t addr, unsigned long size, int revision,
 	gc->private = priv;
 	gc->reg_base = base;
 	gc->domain = domain;
+	gc->suspend = liointc_suspend;
 	gc->resume = liointc_resume;
 
 	ct = gc->chip_types;
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 3+ messages in thread
* Re: [PATCH] irqchip/loongson-liointc: Save/restore int_edge/int_pol registers during S3/S4
  2022-12-07 14:06 [PATCH] irqchip/loongson-liointc: Save/restore int_edge/int_pol registers during S3/S4 Huacai Chen
@ 2023-01-19 12:44 ` Huacai Chen
  2023-02-05 11:29 ` [irqchip: irq/irqchip-next] " irqchip-bot for Huacai Chen
  1 sibling, 0 replies; 3+ messages in thread
From: Huacai Chen @ 2023-01-19 12:44 UTC (permalink / raw)
  To: Huacai Chen
  Cc: Thomas Gleixner, Marc Zyngier, loongarch, linux-kernel,
	Xuefeng Li, Jiaxun Yang, Yingkun Meng

Just a gentle ping.

This patch was sent for the 6.2 cycle but seems too late, now I think
ping it to be reviewed for 6.3 is better than resend it.

On Wed, Dec 7, 2022 at 10:06 PM Huacai Chen <chenhuacai@loongson.cn> wrote:
>
> If int_edge/int_pol registers are configured to not be the default values, we
> should save/restore them during S3/S4.
>
> Signed-off-by: Yingkun Meng <mengyingkun@loongson.cn>
> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
> ---
>  drivers/irqchip/irq-loongson-liointc.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>
> diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
> index c116f70929ae..4367ce9b558f 100644
> --- a/drivers/irqchip/irq-loongson-liointc.c
> +++ b/drivers/irqchip/irq-loongson-liointc.c
> @@ -55,6 +55,8 @@ struct liointc_priv {
>         struct liointc_handler_data     handler[LIOINTC_NUM_PARENT];
>         void __iomem                    *core_isr[LIOINTC_NUM_CORES];
>         u8                              map_cache[LIOINTC_CHIP_IRQ];
> +       u32                             int_pol;
> +       u32                             int_edge;
>         bool                            has_lpc_irq_errata;
>  };
>
> @@ -138,6 +140,14 @@ static int liointc_set_type(struct irq_data *data, unsigned int type)
>         return 0;
>  }
>
> +static void liointc_suspend(struct irq_chip_generic *gc)
> +{
> +       struct liointc_priv *priv = gc->private;
> +
> +       priv->int_pol = readl(gc->reg_base + LIOINTC_REG_INTC_POL);
> +       priv->int_edge = readl(gc->reg_base + LIOINTC_REG_INTC_EDGE);
> +}
> +
>  static void liointc_resume(struct irq_chip_generic *gc)
>  {
>         struct liointc_priv *priv = gc->private;
> @@ -150,6 +160,8 @@ static void liointc_resume(struct irq_chip_generic *gc)
>         /* Restore map cache */
>         for (i = 0; i < LIOINTC_CHIP_IRQ; i++)
>                 writeb(priv->map_cache[i], gc->reg_base + i);
> +       writel(priv->int_pol, gc->reg_base + LIOINTC_REG_INTC_POL);
> +       writel(priv->int_edge, gc->reg_base + LIOINTC_REG_INTC_EDGE);
>         /* Restore mask cache */
>         writel(gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
>         irq_gc_unlock_irqrestore(gc, flags);
> @@ -261,6 +273,7 @@ static int liointc_init(phys_addr_t addr, unsigned long size, int revision,
>         gc->private = priv;
>         gc->reg_base = base;
>         gc->domain = domain;
> +       gc->suspend = liointc_suspend;
>         gc->resume = liointc_resume;
>
>         ct = gc->chip_types;
> --
> 2.31.1
>

^ permalink raw reply	[flat|nested] 3+ messages in thread
* [irqchip: irq/irqchip-next] irqchip/loongson-liointc: Save/restore int_edge/int_pol registers during S3/S4
  2022-12-07 14:06 [PATCH] irqchip/loongson-liointc: Save/restore int_edge/int_pol registers during S3/S4 Huacai Chen
  2023-01-19 12:44 ` Huacai Chen
@ 2023-02-05 11:29 ` irqchip-bot for Huacai Chen
  1 sibling, 0 replies; 3+ messages in thread
From: irqchip-bot for Huacai Chen @ 2023-02-05 11:29 UTC (permalink / raw)
  To: linux-kernel; +Cc: Yingkun Meng, Huacai Chen, Marc Zyngier, tglx

The following commit has been merged into the irq/irqchip-next branch of irqchip:

Commit-ID:     fc98adb9a8435cdb4e8349138ac0b728df80ade9
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/fc98adb9a8435cdb4e8349138ac0b728df80ade9
Author:        Huacai Chen <chenhuacai@loongson.cn>
AuthorDate:    Wed, 07 Dec 2022 22:06:43 +08:00
Committer:     Marc Zyngier <maz@kernel.org>
CommitterDate: Sun, 05 Feb 2023 10:55:19 

irqchip/loongson-liointc: Save/restore int_edge/int_pol registers during S3/S4

If int_edge/int_pol registers are configured to not be the default values, we
should save/restore them during S3/S4.

Signed-off-by: Yingkun Meng <mengyingkun@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20221207140643.1600743-1-chenhuacai@loongson.cn
---
 drivers/irqchip/irq-loongson-liointc.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index 85b754f..8d00a9a 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -55,6 +55,8 @@ struct liointc_priv {
 	struct liointc_handler_data	handler[LIOINTC_NUM_PARENT];
 	void __iomem			*core_isr[LIOINTC_NUM_CORES];
 	u8				map_cache[LIOINTC_CHIP_IRQ];
+	u32				int_pol;
+	u32				int_edge;
 	bool				has_lpc_irq_errata;
 };
 
@@ -138,6 +140,14 @@ static int liointc_set_type(struct irq_data *data, unsigned int type)
 	return 0;
 }
 
+static void liointc_suspend(struct irq_chip_generic *gc)
+{
+	struct liointc_priv *priv = gc->private;
+
+	priv->int_pol = readl(gc->reg_base + LIOINTC_REG_INTC_POL);
+	priv->int_edge = readl(gc->reg_base + LIOINTC_REG_INTC_EDGE);
+}
+
 static void liointc_resume(struct irq_chip_generic *gc)
 {
 	struct liointc_priv *priv = gc->private;
@@ -150,6 +160,8 @@ static void liointc_resume(struct irq_chip_generic *gc)
 	/* Restore map cache */
 	for (i = 0; i < LIOINTC_CHIP_IRQ; i++)
 		writeb(priv->map_cache[i], gc->reg_base + i);
+	writel(priv->int_pol, gc->reg_base + LIOINTC_REG_INTC_POL);
+	writel(priv->int_edge, gc->reg_base + LIOINTC_REG_INTC_EDGE);
 	/* Restore mask cache */
 	writel(gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
 	irq_gc_unlock_irqrestore(gc, flags);
@@ -269,6 +281,7 @@ static int liointc_init(phys_addr_t addr, unsigned long size, int revision,
 	gc->private = priv;
 	gc->reg_base = base;
 	gc->domain = domain;
+	gc->suspend = liointc_suspend;
 	gc->resume = liointc_resume;
 
 	ct = gc->chip_types;

^ permalink raw reply related	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-02-05 11:30 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-12-07 14:06 [PATCH] irqchip/loongson-liointc: Save/restore int_edge/int_pol registers during S3/S4 Huacai Chen
2023-01-19 12:44 ` Huacai Chen
2023-02-05 11:29 ` [irqchip: irq/irqchip-next] " irqchip-bot for Huacai Chen

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