* [PATCH 00/10] drm/i915: move DSC RC tables to drm_dsc_helper.c
@ 2023-02-28 11:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
Other platforms (msm) will benefit from sharing the DSC config setup
functions. This series moves parts of static DSC config data from the
i915 driver to the common helpers to be used by other drivers.
Note: the RC parameters were cross-checked against config files found in
DSC model 2021062, 20161212 (and 20150914). The first patch modifies
tables according to those config files, while preserving parameter
values using the code. I have not changed one of the values in the
pre-SCR config file as it clearly looks like a typo in the config file,
considering the table E in DSC 1.1 and in the DSC 1.1 SCR.
Dmitry Baryshkov (10):
drm/i915/dsc: change DSC param tables to follow the DSC model
drm/i915/dsc: move rc_buf_thresh values to common helper
drm/i915/dsc: move DSC tables to DRM DSC helper
drm/i915/dsc: stop using interim structure for calculated params
drm/display/dsc: use flat array for rc_parameters lookup
drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
drm/display/dsc: include the rest of pre-SCR parameters
drm/display/dsc: add YCbCr 4:2:2 and 4:2:0 RC parameters
drm/display/dsc: add helper to set semi-const parameters
drm/msm/dsi: use new helpers for DSC setup
drivers/gpu/drm/display/drm_dsc_helper.c | 1001 +++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.c | 432 +--------
drivers/gpu/drm/msm/dsi/dsi_host.c | 61 +-
include/drm/display/drm_dsc_helper.h | 10 +
4 files changed, 1058 insertions(+), 446 deletions(-)
--
2.39.2
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 00/10] drm/i915: move DSC RC tables to drm_dsc_helper.c
@ 2023-02-28 11:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
Other platforms (msm) will benefit from sharing the DSC config setup
functions. This series moves parts of static DSC config data from the
i915 driver to the common helpers to be used by other drivers.
Note: the RC parameters were cross-checked against config files found in
DSC model 2021062, 20161212 (and 20150914). The first patch modifies
tables according to those config files, while preserving parameter
values using the code. I have not changed one of the values in the
pre-SCR config file as it clearly looks like a typo in the config file,
considering the table E in DSC 1.1 and in the DSC 1.1 SCR.
Dmitry Baryshkov (10):
drm/i915/dsc: change DSC param tables to follow the DSC model
drm/i915/dsc: move rc_buf_thresh values to common helper
drm/i915/dsc: move DSC tables to DRM DSC helper
drm/i915/dsc: stop using interim structure for calculated params
drm/display/dsc: use flat array for rc_parameters lookup
drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
drm/display/dsc: include the rest of pre-SCR parameters
drm/display/dsc: add YCbCr 4:2:2 and 4:2:0 RC parameters
drm/display/dsc: add helper to set semi-const parameters
drm/msm/dsi: use new helpers for DSC setup
drivers/gpu/drm/display/drm_dsc_helper.c | 1001 +++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.c | 432 +--------
drivers/gpu/drm/msm/dsi/dsi_host.c | 61 +-
include/drm/display/drm_dsc_helper.h | 10 +
4 files changed, 1058 insertions(+), 446 deletions(-)
--
2.39.2
^ permalink raw reply [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH 00/10] drm/i915: move DSC RC tables to drm_dsc_helper.c
@ 2023-02-28 11:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
Other platforms (msm) will benefit from sharing the DSC config setup
functions. This series moves parts of static DSC config data from the
i915 driver to the common helpers to be used by other drivers.
Note: the RC parameters were cross-checked against config files found in
DSC model 2021062, 20161212 (and 20150914). The first patch modifies
tables according to those config files, while preserving parameter
values using the code. I have not changed one of the values in the
pre-SCR config file as it clearly looks like a typo in the config file,
considering the table E in DSC 1.1 and in the DSC 1.1 SCR.
Dmitry Baryshkov (10):
drm/i915/dsc: change DSC param tables to follow the DSC model
drm/i915/dsc: move rc_buf_thresh values to common helper
drm/i915/dsc: move DSC tables to DRM DSC helper
drm/i915/dsc: stop using interim structure for calculated params
drm/display/dsc: use flat array for rc_parameters lookup
drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
drm/display/dsc: include the rest of pre-SCR parameters
drm/display/dsc: add YCbCr 4:2:2 and 4:2:0 RC parameters
drm/display/dsc: add helper to set semi-const parameters
drm/msm/dsi: use new helpers for DSC setup
drivers/gpu/drm/display/drm_dsc_helper.c | 1001 +++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.c | 432 +--------
drivers/gpu/drm/msm/dsi/dsi_host.c | 61 +-
include/drm/display/drm_dsc_helper.h | 10 +
4 files changed, 1058 insertions(+), 446 deletions(-)
--
2.39.2
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 01/10] drm/i915/dsc: change DSC param tables to follow the DSC model
2023-02-28 11:33 ` Dmitry Baryshkov
(?)
@ 2023-02-28 11:33 ` Dmitry Baryshkov
-1 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
After cross-checking DSC models (20150914, 20161212, 20210623) change
values in rc_parameters tables to follow config files present inside
the DSC model. Handle two places, where i915 tables diverged from the
model, by patching the rc values in the code.
Note: I left one case uncorrected, 8bpp/10bpc/range_max_qp[0], because
the table in the VESA DSC 1.1 sets it to 4.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 207b2a648d32..d080741fd0b3 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -86,7 +86,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
}
},
/* 6BPP/14BPC */
- { 768, 15, 6144, 15, 25, 23, 27, {
+ { 768, 15, 6144, 15, 25, 23, 23, {
{ 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
{ 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
{ 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
@@ -115,6 +115,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
},
/* 8BPP/10BPC */
{ 512, 12, 6144, 7, 16, 15, 15, {
+ /*
+ * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
+ * VESA DSC 1.1 Table E-5 sets it to 4.
+ */
{ 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
@@ -132,7 +136,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
},
/* 8BPP/14BPC */
{ 512, 12, 6144, 15, 24, 23, 23, {
- { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
{ 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
{ 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
@@ -529,6 +533,16 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
DSC_RANGE_BPG_OFFSET_MASK;
}
+ if (DISPLAY_VER(dev_priv) < 13) {
+ if (compressed_bpp == 6 &&
+ vdsc_cfg->bits_per_component == 8)
+ vdsc_cfg->rc_quant_incr_limit1 = 23;
+
+ if (compressed_bpp == 8 &&
+ vdsc_cfg->bits_per_component == 14)
+ vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
+ }
+
/*
* BitsPerComponent value determines mux_word_size:
* When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 01/10] drm/i915/dsc: change DSC param tables to follow the DSC model
@ 2023-02-28 11:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
After cross-checking DSC models (20150914, 20161212, 20210623) change
values in rc_parameters tables to follow config files present inside
the DSC model. Handle two places, where i915 tables diverged from the
model, by patching the rc values in the code.
Note: I left one case uncorrected, 8bpp/10bpc/range_max_qp[0], because
the table in the VESA DSC 1.1 sets it to 4.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 207b2a648d32..d080741fd0b3 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -86,7 +86,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
}
},
/* 6BPP/14BPC */
- { 768, 15, 6144, 15, 25, 23, 27, {
+ { 768, 15, 6144, 15, 25, 23, 23, {
{ 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
{ 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
{ 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
@@ -115,6 +115,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
},
/* 8BPP/10BPC */
{ 512, 12, 6144, 7, 16, 15, 15, {
+ /*
+ * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
+ * VESA DSC 1.1 Table E-5 sets it to 4.
+ */
{ 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
@@ -132,7 +136,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
},
/* 8BPP/14BPC */
{ 512, 12, 6144, 15, 24, 23, 23, {
- { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
{ 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
{ 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
@@ -529,6 +533,16 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
DSC_RANGE_BPG_OFFSET_MASK;
}
+ if (DISPLAY_VER(dev_priv) < 13) {
+ if (compressed_bpp == 6 &&
+ vdsc_cfg->bits_per_component == 8)
+ vdsc_cfg->rc_quant_incr_limit1 = 23;
+
+ if (compressed_bpp == 8 &&
+ vdsc_cfg->bits_per_component == 14)
+ vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
+ }
+
/*
* BitsPerComponent value determines mux_word_size:
* When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH 01/10] drm/i915/dsc: change DSC param tables to follow the DSC model
@ 2023-02-28 11:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
After cross-checking DSC models (20150914, 20161212, 20210623) change
values in rc_parameters tables to follow config files present inside
the DSC model. Handle two places, where i915 tables diverged from the
model, by patching the rc values in the code.
Note: I left one case uncorrected, 8bpp/10bpc/range_max_qp[0], because
the table in the VESA DSC 1.1 sets it to 4.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 207b2a648d32..d080741fd0b3 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -86,7 +86,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
}
},
/* 6BPP/14BPC */
- { 768, 15, 6144, 15, 25, 23, 27, {
+ { 768, 15, 6144, 15, 25, 23, 23, {
{ 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
{ 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
{ 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
@@ -115,6 +115,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
},
/* 8BPP/10BPC */
{ 512, 12, 6144, 7, 16, 15, 15, {
+ /*
+ * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
+ * VESA DSC 1.1 Table E-5 sets it to 4.
+ */
{ 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
@@ -132,7 +136,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
},
/* 8BPP/14BPC */
{ 512, 12, 6144, 15, 24, 23, 23, {
- { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
{ 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
{ 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
@@ -529,6 +533,16 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
DSC_RANGE_BPG_OFFSET_MASK;
}
+ if (DISPLAY_VER(dev_priv) < 13) {
+ if (compressed_bpp == 6 &&
+ vdsc_cfg->bits_per_component == 8)
+ vdsc_cfg->rc_quant_incr_limit1 = 23;
+
+ if (compressed_bpp == 8 &&
+ vdsc_cfg->bits_per_component == 14)
+ vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
+ }
+
/*
* BitsPerComponent value determines mux_word_size:
* When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 02/10] drm/i915/dsc: move rc_buf_thresh values to common helper
2023-02-28 11:33 ` Dmitry Baryshkov
(?)
@ 2023-02-28 11:33 ` Dmitry Baryshkov
-1 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
The rc_buf_thresh values are common to all DSC implementations. Move
them to the common helper together with the code to propagage them to
the drm_dsc_config.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 37 +++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +--------------
include/drm/display/drm_dsc_helper.h | 1 +
3 files changed, 39 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index c869c6e51e2b..ab8679c158b5 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -270,6 +270,43 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
}
EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
+/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
+const u16 drm_dsc_rc_buf_thresh[] = {
+ 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
+ 7744, 7872, 8000, 8064
+};
+EXPORT_SYMBOL(drm_dsc_rc_buf_thresh);
+
+/**
+ * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
+ * in accordance with the DSC 1.2 specification.
+ *
+ * @vdsc_cfg: DSC Configuration data partially filled by driver
+ */
+void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
+{
+ int i = 0;
+
+ for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
+ /*
+ * six 0s are appended to the lsb of each threshold value
+ * internally in h/w.
+ * Only 8 bits are allowed for programming RcBufThreshold
+ */
+ vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
+ }
+
+ /*
+ * For 6bpp, RC Buffer threshold 12 and 13 need a different value
+ * as per C Model
+ */
+ if (vdsc_cfg->bits_per_pixel == 6 << 4) {
+ vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
+ vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
+ }
+}
+EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
+
/**
* drm_dsc_compute_rc_parameters() - Write rate control
* parameters to the dsc configuration defined in
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index d080741fd0b3..b4faab4c8fb3 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -36,12 +36,6 @@ enum COLUMN_INDEX_BPC {
MAX_COLUMN_INDEX
};
-/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
-static const u16 rc_buf_thresh[] = {
- 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
- 7744, 7872, 8000, 8064
-};
-
struct rc_parameters {
u16 initial_xmit_delay;
u8 first_line_bpg_offset;
@@ -474,23 +468,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
- for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
- /*
- * six 0s are appended to the lsb of each threshold value
- * internally in h/w.
- * Only 8 bits are allowed for programming RcBufThreshold
- */
- vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
- }
-
- /*
- * For 6bpp, RC Buffer threshold 12 and 13 need a different value
- * as per C Model
- */
- if (compressed_bpp == 6) {
- vdsc_cfg->rc_buf_thresh[12] = 0x7C;
- vdsc_cfg->rc_buf_thresh[13] = 0x7D;
- }
+ drm_dsc_set_rc_buf_thresh(vdsc_cfg);
/*
* From XE_LPD onwards we supports compression bpps in steps of 1
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 8b41edbbabab..706ba1d34742 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
+void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
#endif /* _DRM_DSC_HELPER_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 02/10] drm/i915/dsc: move rc_buf_thresh values to common helper
@ 2023-02-28 11:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
The rc_buf_thresh values are common to all DSC implementations. Move
them to the common helper together with the code to propagage them to
the drm_dsc_config.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 37 +++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +--------------
include/drm/display/drm_dsc_helper.h | 1 +
3 files changed, 39 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index c869c6e51e2b..ab8679c158b5 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -270,6 +270,43 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
}
EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
+/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
+const u16 drm_dsc_rc_buf_thresh[] = {
+ 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
+ 7744, 7872, 8000, 8064
+};
+EXPORT_SYMBOL(drm_dsc_rc_buf_thresh);
+
+/**
+ * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
+ * in accordance with the DSC 1.2 specification.
+ *
+ * @vdsc_cfg: DSC Configuration data partially filled by driver
+ */
+void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
+{
+ int i = 0;
+
+ for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
+ /*
+ * six 0s are appended to the lsb of each threshold value
+ * internally in h/w.
+ * Only 8 bits are allowed for programming RcBufThreshold
+ */
+ vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
+ }
+
+ /*
+ * For 6bpp, RC Buffer threshold 12 and 13 need a different value
+ * as per C Model
+ */
+ if (vdsc_cfg->bits_per_pixel == 6 << 4) {
+ vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
+ vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
+ }
+}
+EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
+
/**
* drm_dsc_compute_rc_parameters() - Write rate control
* parameters to the dsc configuration defined in
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index d080741fd0b3..b4faab4c8fb3 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -36,12 +36,6 @@ enum COLUMN_INDEX_BPC {
MAX_COLUMN_INDEX
};
-/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
-static const u16 rc_buf_thresh[] = {
- 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
- 7744, 7872, 8000, 8064
-};
-
struct rc_parameters {
u16 initial_xmit_delay;
u8 first_line_bpg_offset;
@@ -474,23 +468,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
- for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
- /*
- * six 0s are appended to the lsb of each threshold value
- * internally in h/w.
- * Only 8 bits are allowed for programming RcBufThreshold
- */
- vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
- }
-
- /*
- * For 6bpp, RC Buffer threshold 12 and 13 need a different value
- * as per C Model
- */
- if (compressed_bpp == 6) {
- vdsc_cfg->rc_buf_thresh[12] = 0x7C;
- vdsc_cfg->rc_buf_thresh[13] = 0x7D;
- }
+ drm_dsc_set_rc_buf_thresh(vdsc_cfg);
/*
* From XE_LPD onwards we supports compression bpps in steps of 1
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 8b41edbbabab..706ba1d34742 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
+void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
#endif /* _DRM_DSC_HELPER_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH 02/10] drm/i915/dsc: move rc_buf_thresh values to common helper
@ 2023-02-28 11:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
The rc_buf_thresh values are common to all DSC implementations. Move
them to the common helper together with the code to propagage them to
the drm_dsc_config.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 37 +++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +--------------
include/drm/display/drm_dsc_helper.h | 1 +
3 files changed, 39 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index c869c6e51e2b..ab8679c158b5 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -270,6 +270,43 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
}
EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
+/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
+const u16 drm_dsc_rc_buf_thresh[] = {
+ 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
+ 7744, 7872, 8000, 8064
+};
+EXPORT_SYMBOL(drm_dsc_rc_buf_thresh);
+
+/**
+ * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
+ * in accordance with the DSC 1.2 specification.
+ *
+ * @vdsc_cfg: DSC Configuration data partially filled by driver
+ */
+void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
+{
+ int i = 0;
+
+ for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
+ /*
+ * six 0s are appended to the lsb of each threshold value
+ * internally in h/w.
+ * Only 8 bits are allowed for programming RcBufThreshold
+ */
+ vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
+ }
+
+ /*
+ * For 6bpp, RC Buffer threshold 12 and 13 need a different value
+ * as per C Model
+ */
+ if (vdsc_cfg->bits_per_pixel == 6 << 4) {
+ vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
+ vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
+ }
+}
+EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
+
/**
* drm_dsc_compute_rc_parameters() - Write rate control
* parameters to the dsc configuration defined in
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index d080741fd0b3..b4faab4c8fb3 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -36,12 +36,6 @@ enum COLUMN_INDEX_BPC {
MAX_COLUMN_INDEX
};
-/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
-static const u16 rc_buf_thresh[] = {
- 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
- 7744, 7872, 8000, 8064
-};
-
struct rc_parameters {
u16 initial_xmit_delay;
u8 first_line_bpg_offset;
@@ -474,23 +468,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
- for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
- /*
- * six 0s are appended to the lsb of each threshold value
- * internally in h/w.
- * Only 8 bits are allowed for programming RcBufThreshold
- */
- vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
- }
-
- /*
- * For 6bpp, RC Buffer threshold 12 and 13 need a different value
- * as per C Model
- */
- if (compressed_bpp == 6) {
- vdsc_cfg->rc_buf_thresh[12] = 0x7C;
- vdsc_cfg->rc_buf_thresh[13] = 0x7D;
- }
+ drm_dsc_set_rc_buf_thresh(vdsc_cfg);
/*
* From XE_LPD onwards we supports compression bpps in steps of 1
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 8b41edbbabab..706ba1d34742 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
+void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
#endif /* _DRM_DSC_HELPER_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper
2023-02-28 11:33 ` Dmitry Baryshkov
(?)
@ 2023-02-28 11:33 ` Dmitry Baryshkov
-1 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
This moves DSC RC tables to DRM DSC helper. No additional code changes
and/or cleanups are a part of this commit, it will be cleaned up in the
followup commits.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 364 ++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.c | 319 +------------------
include/drm/display/drm_dsc_helper.h | 1 +
3 files changed, 372 insertions(+), 312 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index ab8679c158b5..deaa84722bd4 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -307,6 +307,370 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
}
EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
+enum ROW_INDEX_BPP {
+ ROW_INDEX_6BPP = 0,
+ ROW_INDEX_8BPP,
+ ROW_INDEX_10BPP,
+ ROW_INDEX_12BPP,
+ ROW_INDEX_15BPP,
+ MAX_ROW_INDEX
+};
+
+enum COLUMN_INDEX_BPC {
+ COLUMN_INDEX_8BPC = 0,
+ COLUMN_INDEX_10BPC,
+ COLUMN_INDEX_12BPC,
+ COLUMN_INDEX_14BPC,
+ COLUMN_INDEX_16BPC,
+ MAX_COLUMN_INDEX
+};
+
+struct rc_parameters {
+ u16 initial_xmit_delay;
+ u8 first_line_bpg_offset;
+ u16 initial_offset;
+ u8 flatness_min_qp;
+ u8 flatness_max_qp;
+ u8 rc_quant_incr_limit0;
+ u8 rc_quant_incr_limit1;
+ struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+};
+
+/*
+ * Selected Rate Control Related Parameter Recommended Values
+ * from DSC_v1.11 spec & C Model release: DSC_model_20161212
+ */
+static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
+{
+ /* 6BPP/8BPC */
+ { 768, 15, 6144, 3, 13, 11, 11, {
+ { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
+ { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
+ { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
+ { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
+ }
+ },
+ /* 6BPP/10BPC */
+ { 768, 15, 6144, 7, 17, 15, 15, {
+ { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
+ { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
+ { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
+ { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
+ { 17, 18, -12 }
+ }
+ },
+ /* 6BPP/12BPC */
+ { 768, 15, 6144, 11, 21, 19, 19, {
+ { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
+ { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
+ { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
+ { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
+ { 21, 22, -12 }
+ }
+ },
+ /* 6BPP/14BPC */
+ { 768, 15, 6144, 15, 25, 23, 23, {
+ { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
+ { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
+ { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
+ { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
+ { 25, 26, -12 }
+ }
+ },
+ /* 6BPP/16BPC */
+ { 768, 15, 6144, 19, 29, 27, 27, {
+ { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
+ { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
+ { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
+ { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
+ { 29, 30, -12 }
+ }
+ },
+},
+{
+ /* 8BPP/8BPC */
+ { 512, 12, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
+ { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ },
+ /* 8BPP/10BPC */
+ { 512, 12, 6144, 7, 16, 15, 15, {
+ /*
+ * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
+ * VESA DSC 1.1 Table E-5 sets it to 4.
+ */
+ { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ },
+ /* 8BPP/12BPC */
+ { 512, 12, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ },
+ /* 8BPP/14BPC */
+ { 512, 12, 6144, 15, 24, 23, 23, {
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
+ { 24, 25, -12 }
+ }
+ },
+ /* 8BPP/16BPC */
+ { 512, 12, 6144, 19, 28, 27, 27, {
+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
+ { 28, 29, -12 }
+ }
+ },
+},
+{
+ /* 10BPP/8BPC */
+ { 410, 15, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
+ }
+ },
+ /* 10BPP/10BPC */
+ { 410, 15, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
+ }
+ },
+ /* 10BPP/12BPC */
+ { 410, 15, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
+ { 19, 20, -12 }
+ }
+ },
+ /* 10BPP/14BPC */
+ { 410, 15, 5632, 15, 24, 23, 23, {
+ { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
+ { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
+ { 23, 24, -12 }
+ }
+ },
+ /* 10BPP/16BPC */
+ { 410, 15, 5632, 19, 28, 27, 27, {
+ { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
+ { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
+ { 27, 28, -12 }
+ }
+ },
+},
+{
+ /* 12BPP/8BPC */
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
+ { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ },
+ /* 12BPP/10BPC */
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ },
+ /* 12BPP/12BPC */
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ },
+ /* 12BPP/14BPC */
+ { 341, 15, 2048, 15, 24, 23, 23, {
+ { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
+ { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
+ { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
+ { 22, 23, -12 }
+ }
+ },
+ /* 12BPP/16BPC */
+ { 341, 15, 2048, 19, 28, 27, 27, {
+ { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
+ { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
+ { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
+ { 26, 27, -12 }
+ }
+ },
+},
+{
+ /* 15BPP/8BPC */
+ { 273, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
+ { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
+ { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
+ }
+ },
+ /* 15BPP/10BPC */
+ { 273, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
+ { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
+ { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
+ }
+ },
+ /* 15BPP/12BPC */
+ { 273, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
+ { 16, 17, -12 }
+ }
+ },
+ /* 15BPP/14BPC */
+ { 273, 15, 2048, 15, 24, 23, 23, {
+ { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
+ { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
+ { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
+ { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
+ { 20, 21, -12 }
+ }
+ },
+ /* 15BPP/16BPC */
+ { 273, 15, 2048, 19, 28, 27, 27, {
+ { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
+ { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
+ { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
+ { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+}
+};
+
+static int get_row_index_for_rc_params(u16 compressed_bpp)
+{
+ switch (compressed_bpp) {
+ case 6:
+ return ROW_INDEX_6BPP;
+ case 8:
+ return ROW_INDEX_8BPP;
+ case 10:
+ return ROW_INDEX_10BPP;
+ case 12:
+ return ROW_INDEX_12BPP;
+ case 15:
+ return ROW_INDEX_15BPP;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int get_column_index_for_rc_params(u8 bits_per_component)
+{
+ switch (bits_per_component) {
+ case 8:
+ return COLUMN_INDEX_8BPC;
+ case 10:
+ return COLUMN_INDEX_10BPC;
+ case 12:
+ return COLUMN_INDEX_12BPC;
+ case 14:
+ return COLUMN_INDEX_14BPC;
+ case 16:
+ return COLUMN_INDEX_16BPC;
+ default:
+ return -EINVAL;
+ }
+}
+
+static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
+ u8 bits_per_component)
+{
+ int row_index, column_index;
+
+ row_index = get_row_index_for_rc_params(compressed_bpp);
+ if (row_index < 0)
+ return NULL;
+
+ column_index = get_column_index_for_rc_params(bits_per_component);
+ if (column_index < 0)
+ return NULL;
+
+ return &rc_parameters[row_index][column_index];
+}
+
+/**
+ * drm_dsc_compute_rc_parameters() - Set parameters and limits for RC model in
+ * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
+ *
+ * @vdsc_cfg: DSC Configuration data partially filled by driver
+ */
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
+{
+ const struct rc_parameters *rc_params;
+ int i;
+
+ /* fractional BPP is not supported */
+ if (vdsc_cfg->bits_per_pixel & 0xf)
+ return -EINVAL;
+
+ rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
+ vdsc_cfg->bits_per_component);
+ if (!rc_params)
+ return -EINVAL;
+
+ vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
+ vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
+ vdsc_cfg->initial_offset = rc_params->initial_offset;
+ vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
+ vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
+ vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
+ vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
+
+ for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
+ vdsc_cfg->rc_range_params[i].range_min_qp =
+ rc_params->rc_range_params[i].range_min_qp;
+ vdsc_cfg->rc_range_params[i].range_max_qp =
+ rc_params->rc_range_params[i].range_max_qp;
+ /*
+ * Range BPG Offset uses 2's complement and is only a 6 bits. So
+ * mask it to get only 6 bits.
+ */
+ vdsc_cfg->rc_range_params[i].range_bpg_offset =
+ rc_params->rc_range_params[i].range_bpg_offset &
+ DSC_RANGE_BPG_OFFSET_MASK;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dsc_setup_rc_params);
+
/**
* drm_dsc_compute_rc_parameters() - Write rate control
* parameters to the dsc configuration defined in
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index b4faab4c8fb3..d5a7e9494b23 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -18,24 +18,6 @@
#include "intel_qp_tables.h"
#include "intel_vdsc.h"
-enum ROW_INDEX_BPP {
- ROW_INDEX_6BPP = 0,
- ROW_INDEX_8BPP,
- ROW_INDEX_10BPP,
- ROW_INDEX_12BPP,
- ROW_INDEX_15BPP,
- MAX_ROW_INDEX
-};
-
-enum COLUMN_INDEX_BPC {
- COLUMN_INDEX_8BPC = 0,
- COLUMN_INDEX_10BPC,
- COLUMN_INDEX_12BPC,
- COLUMN_INDEX_14BPC,
- COLUMN_INDEX_16BPC,
- MAX_COLUMN_INDEX
-};
-
struct rc_parameters {
u16 initial_xmit_delay;
u8 first_line_bpg_offset;
@@ -47,296 +29,6 @@ struct rc_parameters {
struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
};
-/*
- * Selected Rate Control Related Parameter Recommended Values
- * from DSC_v1.11 spec & C Model release: DSC_model_20161212
- */
-static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
-{
- /* 6BPP/8BPC */
- { 768, 15, 6144, 3, 13, 11, 11, {
- { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
- { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
- { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
- { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
- }
- },
- /* 6BPP/10BPC */
- { 768, 15, 6144, 7, 17, 15, 15, {
- { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
- { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
- { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
- { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
- { 17, 18, -12 }
- }
- },
- /* 6BPP/12BPC */
- { 768, 15, 6144, 11, 21, 19, 19, {
- { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
- { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
- { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
- { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
- { 21, 22, -12 }
- }
- },
- /* 6BPP/14BPC */
- { 768, 15, 6144, 15, 25, 23, 23, {
- { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
- { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
- { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
- { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
- { 25, 26, -12 }
- }
- },
- /* 6BPP/16BPC */
- { 768, 15, 6144, 19, 29, 27, 27, {
- { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
- { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
- { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
- { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
- { 29, 30, -12 }
- }
- },
-},
-{
- /* 8BPP/8BPC */
- { 512, 12, 6144, 3, 12, 11, 11, {
- { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
- { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
- { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
- }
- },
- /* 8BPP/10BPC */
- { 512, 12, 6144, 7, 16, 15, 15, {
- /*
- * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
- * VESA DSC 1.1 Table E-5 sets it to 4.
- */
- { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
- { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
- }
- },
- /* 8BPP/12BPC */
- { 512, 12, 6144, 11, 20, 19, 19, {
- { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
- { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
- }
- },
- /* 8BPP/14BPC */
- { 512, 12, 6144, 15, 24, 23, 23, {
- { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
- { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
- { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
- { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
- { 24, 25, -12 }
- }
- },
- /* 8BPP/16BPC */
- { 512, 12, 6144, 19, 28, 27, 27, {
- { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
- { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
- { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
- { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
- { 28, 29, -12 }
- }
- },
-},
-{
- /* 10BPP/8BPC */
- { 410, 15, 5632, 3, 12, 11, 11, {
- { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
- { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
- { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
- }
- },
- /* 10BPP/10BPC */
- { 410, 15, 5632, 7, 16, 15, 15, {
- { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
- { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
- { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
- }
- },
- /* 10BPP/12BPC */
- { 410, 15, 5632, 11, 20, 19, 19, {
- { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
- { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
- { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
- { 19, 20, -12 }
- }
- },
- /* 10BPP/14BPC */
- { 410, 15, 5632, 15, 24, 23, 23, {
- { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
- { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
- { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
- { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
- { 23, 24, -12 }
- }
- },
- /* 10BPP/16BPC */
- { 410, 15, 5632, 19, 28, 27, 27, {
- { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
- { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
- { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
- { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
- { 27, 28, -12 }
- }
- },
-},
-{
- /* 12BPP/8BPC */
- { 341, 15, 2048, 3, 12, 11, 11, {
- { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
- { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
- { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
- }
- },
- /* 12BPP/10BPC */
- { 341, 15, 2048, 7, 16, 15, 15, {
- { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
- { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
- }
- },
- /* 12BPP/12BPC */
- { 341, 15, 2048, 11, 20, 19, 19, {
- { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
- { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
- }
- },
- /* 12BPP/14BPC */
- { 341, 15, 2048, 15, 24, 23, 23, {
- { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
- { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
- { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
- { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
- { 22, 23, -12 }
- }
- },
- /* 12BPP/16BPC */
- { 341, 15, 2048, 19, 28, 27, 27, {
- { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
- { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
- { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
- { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
- { 26, 27, -12 }
- }
- },
-},
-{
- /* 15BPP/8BPC */
- { 273, 15, 2048, 3, 12, 11, 11, {
- { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
- { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
- { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
- { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
- }
- },
- /* 15BPP/10BPC */
- { 273, 15, 2048, 7, 16, 15, 15, {
- { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
- { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
- { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
- { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
- }
- },
- /* 15BPP/12BPC */
- { 273, 15, 2048, 11, 20, 19, 19, {
- { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
- { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
- { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
- { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
- { 16, 17, -12 }
- }
- },
- /* 15BPP/14BPC */
- { 273, 15, 2048, 15, 24, 23, 23, {
- { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
- { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
- { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
- { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
- { 20, 21, -12 }
- }
- },
- /* 15BPP/16BPC */
- { 273, 15, 2048, 19, 28, 27, 27, {
- { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
- { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
- { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
- { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
- { 24, 25, -12 }
- }
- }
-}
-
-};
-
-static int get_row_index_for_rc_params(u16 compressed_bpp)
-{
- switch (compressed_bpp) {
- case 6:
- return ROW_INDEX_6BPP;
- case 8:
- return ROW_INDEX_8BPP;
- case 10:
- return ROW_INDEX_10BPP;
- case 12:
- return ROW_INDEX_12BPP;
- case 15:
- return ROW_INDEX_15BPP;
- default:
- return -EINVAL;
- }
-}
-
-static int get_column_index_for_rc_params(u8 bits_per_component)
-{
- switch (bits_per_component) {
- case 8:
- return COLUMN_INDEX_8BPC;
- case 10:
- return COLUMN_INDEX_10BPC;
- case 12:
- return COLUMN_INDEX_12BPC;
- case 14:
- return COLUMN_INDEX_14BPC;
- case 16:
- return COLUMN_INDEX_16BPC;
- default:
- return -EINVAL;
- }
-}
-
-static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
- u8 bits_per_component)
-{
- int row_index, column_index;
-
- row_index = get_row_index_for_rc_params(compressed_bpp);
- if (row_index < 0)
- return NULL;
-
- column_index = get_column_index_for_rc_params(bits_per_component);
- if (column_index < 0)
- return NULL;
-
- return &rc_parameters[row_index][column_index];
-}
-
bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
{
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -454,6 +146,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
const struct rc_parameters *rc_params;
struct rc_parameters *rc = NULL;
u8 i = 0;
+ int ret;
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
@@ -483,10 +176,11 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
calculate_rc_params(rc, vdsc_cfg);
rc_params = rc;
} else {
- rc_params = get_rc_params(compressed_bpp,
- vdsc_cfg->bits_per_component);
- if (!rc_params)
- return -EINVAL;
+ ret = drm_dsc_setup_rc_params(vdsc_cfg);
+ if (ret)
+ return ret;
+
+ goto out;
}
vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
@@ -521,6 +215,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
}
+out:
/*
* BitsPerComponent value determines mux_word_size:
* When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 706ba1d34742..1681791f65a5 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -15,6 +15,7 @@ int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
#endif /* _DRM_DSC_HELPER_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper
@ 2023-02-28 11:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
This moves DSC RC tables to DRM DSC helper. No additional code changes
and/or cleanups are a part of this commit, it will be cleaned up in the
followup commits.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 364 ++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.c | 319 +------------------
include/drm/display/drm_dsc_helper.h | 1 +
3 files changed, 372 insertions(+), 312 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index ab8679c158b5..deaa84722bd4 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -307,6 +307,370 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
}
EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
+enum ROW_INDEX_BPP {
+ ROW_INDEX_6BPP = 0,
+ ROW_INDEX_8BPP,
+ ROW_INDEX_10BPP,
+ ROW_INDEX_12BPP,
+ ROW_INDEX_15BPP,
+ MAX_ROW_INDEX
+};
+
+enum COLUMN_INDEX_BPC {
+ COLUMN_INDEX_8BPC = 0,
+ COLUMN_INDEX_10BPC,
+ COLUMN_INDEX_12BPC,
+ COLUMN_INDEX_14BPC,
+ COLUMN_INDEX_16BPC,
+ MAX_COLUMN_INDEX
+};
+
+struct rc_parameters {
+ u16 initial_xmit_delay;
+ u8 first_line_bpg_offset;
+ u16 initial_offset;
+ u8 flatness_min_qp;
+ u8 flatness_max_qp;
+ u8 rc_quant_incr_limit0;
+ u8 rc_quant_incr_limit1;
+ struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+};
+
+/*
+ * Selected Rate Control Related Parameter Recommended Values
+ * from DSC_v1.11 spec & C Model release: DSC_model_20161212
+ */
+static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
+{
+ /* 6BPP/8BPC */
+ { 768, 15, 6144, 3, 13, 11, 11, {
+ { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
+ { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
+ { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
+ { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
+ }
+ },
+ /* 6BPP/10BPC */
+ { 768, 15, 6144, 7, 17, 15, 15, {
+ { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
+ { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
+ { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
+ { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
+ { 17, 18, -12 }
+ }
+ },
+ /* 6BPP/12BPC */
+ { 768, 15, 6144, 11, 21, 19, 19, {
+ { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
+ { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
+ { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
+ { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
+ { 21, 22, -12 }
+ }
+ },
+ /* 6BPP/14BPC */
+ { 768, 15, 6144, 15, 25, 23, 23, {
+ { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
+ { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
+ { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
+ { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
+ { 25, 26, -12 }
+ }
+ },
+ /* 6BPP/16BPC */
+ { 768, 15, 6144, 19, 29, 27, 27, {
+ { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
+ { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
+ { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
+ { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
+ { 29, 30, -12 }
+ }
+ },
+},
+{
+ /* 8BPP/8BPC */
+ { 512, 12, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
+ { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ },
+ /* 8BPP/10BPC */
+ { 512, 12, 6144, 7, 16, 15, 15, {
+ /*
+ * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
+ * VESA DSC 1.1 Table E-5 sets it to 4.
+ */
+ { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ },
+ /* 8BPP/12BPC */
+ { 512, 12, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ },
+ /* 8BPP/14BPC */
+ { 512, 12, 6144, 15, 24, 23, 23, {
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
+ { 24, 25, -12 }
+ }
+ },
+ /* 8BPP/16BPC */
+ { 512, 12, 6144, 19, 28, 27, 27, {
+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
+ { 28, 29, -12 }
+ }
+ },
+},
+{
+ /* 10BPP/8BPC */
+ { 410, 15, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
+ }
+ },
+ /* 10BPP/10BPC */
+ { 410, 15, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
+ }
+ },
+ /* 10BPP/12BPC */
+ { 410, 15, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
+ { 19, 20, -12 }
+ }
+ },
+ /* 10BPP/14BPC */
+ { 410, 15, 5632, 15, 24, 23, 23, {
+ { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
+ { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
+ { 23, 24, -12 }
+ }
+ },
+ /* 10BPP/16BPC */
+ { 410, 15, 5632, 19, 28, 27, 27, {
+ { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
+ { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
+ { 27, 28, -12 }
+ }
+ },
+},
+{
+ /* 12BPP/8BPC */
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
+ { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ },
+ /* 12BPP/10BPC */
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ },
+ /* 12BPP/12BPC */
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ },
+ /* 12BPP/14BPC */
+ { 341, 15, 2048, 15, 24, 23, 23, {
+ { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
+ { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
+ { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
+ { 22, 23, -12 }
+ }
+ },
+ /* 12BPP/16BPC */
+ { 341, 15, 2048, 19, 28, 27, 27, {
+ { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
+ { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
+ { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
+ { 26, 27, -12 }
+ }
+ },
+},
+{
+ /* 15BPP/8BPC */
+ { 273, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
+ { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
+ { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
+ }
+ },
+ /* 15BPP/10BPC */
+ { 273, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
+ { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
+ { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
+ }
+ },
+ /* 15BPP/12BPC */
+ { 273, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
+ { 16, 17, -12 }
+ }
+ },
+ /* 15BPP/14BPC */
+ { 273, 15, 2048, 15, 24, 23, 23, {
+ { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
+ { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
+ { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
+ { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
+ { 20, 21, -12 }
+ }
+ },
+ /* 15BPP/16BPC */
+ { 273, 15, 2048, 19, 28, 27, 27, {
+ { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
+ { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
+ { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
+ { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+}
+};
+
+static int get_row_index_for_rc_params(u16 compressed_bpp)
+{
+ switch (compressed_bpp) {
+ case 6:
+ return ROW_INDEX_6BPP;
+ case 8:
+ return ROW_INDEX_8BPP;
+ case 10:
+ return ROW_INDEX_10BPP;
+ case 12:
+ return ROW_INDEX_12BPP;
+ case 15:
+ return ROW_INDEX_15BPP;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int get_column_index_for_rc_params(u8 bits_per_component)
+{
+ switch (bits_per_component) {
+ case 8:
+ return COLUMN_INDEX_8BPC;
+ case 10:
+ return COLUMN_INDEX_10BPC;
+ case 12:
+ return COLUMN_INDEX_12BPC;
+ case 14:
+ return COLUMN_INDEX_14BPC;
+ case 16:
+ return COLUMN_INDEX_16BPC;
+ default:
+ return -EINVAL;
+ }
+}
+
+static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
+ u8 bits_per_component)
+{
+ int row_index, column_index;
+
+ row_index = get_row_index_for_rc_params(compressed_bpp);
+ if (row_index < 0)
+ return NULL;
+
+ column_index = get_column_index_for_rc_params(bits_per_component);
+ if (column_index < 0)
+ return NULL;
+
+ return &rc_parameters[row_index][column_index];
+}
+
+/**
+ * drm_dsc_compute_rc_parameters() - Set parameters and limits for RC model in
+ * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
+ *
+ * @vdsc_cfg: DSC Configuration data partially filled by driver
+ */
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
+{
+ const struct rc_parameters *rc_params;
+ int i;
+
+ /* fractional BPP is not supported */
+ if (vdsc_cfg->bits_per_pixel & 0xf)
+ return -EINVAL;
+
+ rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
+ vdsc_cfg->bits_per_component);
+ if (!rc_params)
+ return -EINVAL;
+
+ vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
+ vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
+ vdsc_cfg->initial_offset = rc_params->initial_offset;
+ vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
+ vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
+ vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
+ vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
+
+ for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
+ vdsc_cfg->rc_range_params[i].range_min_qp =
+ rc_params->rc_range_params[i].range_min_qp;
+ vdsc_cfg->rc_range_params[i].range_max_qp =
+ rc_params->rc_range_params[i].range_max_qp;
+ /*
+ * Range BPG Offset uses 2's complement and is only a 6 bits. So
+ * mask it to get only 6 bits.
+ */
+ vdsc_cfg->rc_range_params[i].range_bpg_offset =
+ rc_params->rc_range_params[i].range_bpg_offset &
+ DSC_RANGE_BPG_OFFSET_MASK;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dsc_setup_rc_params);
+
/**
* drm_dsc_compute_rc_parameters() - Write rate control
* parameters to the dsc configuration defined in
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index b4faab4c8fb3..d5a7e9494b23 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -18,24 +18,6 @@
#include "intel_qp_tables.h"
#include "intel_vdsc.h"
-enum ROW_INDEX_BPP {
- ROW_INDEX_6BPP = 0,
- ROW_INDEX_8BPP,
- ROW_INDEX_10BPP,
- ROW_INDEX_12BPP,
- ROW_INDEX_15BPP,
- MAX_ROW_INDEX
-};
-
-enum COLUMN_INDEX_BPC {
- COLUMN_INDEX_8BPC = 0,
- COLUMN_INDEX_10BPC,
- COLUMN_INDEX_12BPC,
- COLUMN_INDEX_14BPC,
- COLUMN_INDEX_16BPC,
- MAX_COLUMN_INDEX
-};
-
struct rc_parameters {
u16 initial_xmit_delay;
u8 first_line_bpg_offset;
@@ -47,296 +29,6 @@ struct rc_parameters {
struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
};
-/*
- * Selected Rate Control Related Parameter Recommended Values
- * from DSC_v1.11 spec & C Model release: DSC_model_20161212
- */
-static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
-{
- /* 6BPP/8BPC */
- { 768, 15, 6144, 3, 13, 11, 11, {
- { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
- { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
- { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
- { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
- }
- },
- /* 6BPP/10BPC */
- { 768, 15, 6144, 7, 17, 15, 15, {
- { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
- { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
- { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
- { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
- { 17, 18, -12 }
- }
- },
- /* 6BPP/12BPC */
- { 768, 15, 6144, 11, 21, 19, 19, {
- { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
- { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
- { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
- { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
- { 21, 22, -12 }
- }
- },
- /* 6BPP/14BPC */
- { 768, 15, 6144, 15, 25, 23, 23, {
- { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
- { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
- { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
- { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
- { 25, 26, -12 }
- }
- },
- /* 6BPP/16BPC */
- { 768, 15, 6144, 19, 29, 27, 27, {
- { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
- { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
- { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
- { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
- { 29, 30, -12 }
- }
- },
-},
-{
- /* 8BPP/8BPC */
- { 512, 12, 6144, 3, 12, 11, 11, {
- { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
- { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
- { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
- }
- },
- /* 8BPP/10BPC */
- { 512, 12, 6144, 7, 16, 15, 15, {
- /*
- * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
- * VESA DSC 1.1 Table E-5 sets it to 4.
- */
- { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
- { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
- }
- },
- /* 8BPP/12BPC */
- { 512, 12, 6144, 11, 20, 19, 19, {
- { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
- { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
- }
- },
- /* 8BPP/14BPC */
- { 512, 12, 6144, 15, 24, 23, 23, {
- { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
- { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
- { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
- { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
- { 24, 25, -12 }
- }
- },
- /* 8BPP/16BPC */
- { 512, 12, 6144, 19, 28, 27, 27, {
- { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
- { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
- { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
- { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
- { 28, 29, -12 }
- }
- },
-},
-{
- /* 10BPP/8BPC */
- { 410, 15, 5632, 3, 12, 11, 11, {
- { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
- { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
- { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
- }
- },
- /* 10BPP/10BPC */
- { 410, 15, 5632, 7, 16, 15, 15, {
- { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
- { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
- { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
- }
- },
- /* 10BPP/12BPC */
- { 410, 15, 5632, 11, 20, 19, 19, {
- { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
- { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
- { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
- { 19, 20, -12 }
- }
- },
- /* 10BPP/14BPC */
- { 410, 15, 5632, 15, 24, 23, 23, {
- { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
- { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
- { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
- { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
- { 23, 24, -12 }
- }
- },
- /* 10BPP/16BPC */
- { 410, 15, 5632, 19, 28, 27, 27, {
- { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
- { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
- { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
- { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
- { 27, 28, -12 }
- }
- },
-},
-{
- /* 12BPP/8BPC */
- { 341, 15, 2048, 3, 12, 11, 11, {
- { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
- { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
- { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
- }
- },
- /* 12BPP/10BPC */
- { 341, 15, 2048, 7, 16, 15, 15, {
- { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
- { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
- }
- },
- /* 12BPP/12BPC */
- { 341, 15, 2048, 11, 20, 19, 19, {
- { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
- { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
- }
- },
- /* 12BPP/14BPC */
- { 341, 15, 2048, 15, 24, 23, 23, {
- { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
- { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
- { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
- { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
- { 22, 23, -12 }
- }
- },
- /* 12BPP/16BPC */
- { 341, 15, 2048, 19, 28, 27, 27, {
- { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
- { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
- { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
- { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
- { 26, 27, -12 }
- }
- },
-},
-{
- /* 15BPP/8BPC */
- { 273, 15, 2048, 3, 12, 11, 11, {
- { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
- { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
- { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
- { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
- }
- },
- /* 15BPP/10BPC */
- { 273, 15, 2048, 7, 16, 15, 15, {
- { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
- { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
- { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
- { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
- }
- },
- /* 15BPP/12BPC */
- { 273, 15, 2048, 11, 20, 19, 19, {
- { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
- { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
- { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
- { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
- { 16, 17, -12 }
- }
- },
- /* 15BPP/14BPC */
- { 273, 15, 2048, 15, 24, 23, 23, {
- { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
- { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
- { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
- { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
- { 20, 21, -12 }
- }
- },
- /* 15BPP/16BPC */
- { 273, 15, 2048, 19, 28, 27, 27, {
- { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
- { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
- { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
- { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
- { 24, 25, -12 }
- }
- }
-}
-
-};
-
-static int get_row_index_for_rc_params(u16 compressed_bpp)
-{
- switch (compressed_bpp) {
- case 6:
- return ROW_INDEX_6BPP;
- case 8:
- return ROW_INDEX_8BPP;
- case 10:
- return ROW_INDEX_10BPP;
- case 12:
- return ROW_INDEX_12BPP;
- case 15:
- return ROW_INDEX_15BPP;
- default:
- return -EINVAL;
- }
-}
-
-static int get_column_index_for_rc_params(u8 bits_per_component)
-{
- switch (bits_per_component) {
- case 8:
- return COLUMN_INDEX_8BPC;
- case 10:
- return COLUMN_INDEX_10BPC;
- case 12:
- return COLUMN_INDEX_12BPC;
- case 14:
- return COLUMN_INDEX_14BPC;
- case 16:
- return COLUMN_INDEX_16BPC;
- default:
- return -EINVAL;
- }
-}
-
-static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
- u8 bits_per_component)
-{
- int row_index, column_index;
-
- row_index = get_row_index_for_rc_params(compressed_bpp);
- if (row_index < 0)
- return NULL;
-
- column_index = get_column_index_for_rc_params(bits_per_component);
- if (column_index < 0)
- return NULL;
-
- return &rc_parameters[row_index][column_index];
-}
-
bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
{
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -454,6 +146,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
const struct rc_parameters *rc_params;
struct rc_parameters *rc = NULL;
u8 i = 0;
+ int ret;
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
@@ -483,10 +176,11 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
calculate_rc_params(rc, vdsc_cfg);
rc_params = rc;
} else {
- rc_params = get_rc_params(compressed_bpp,
- vdsc_cfg->bits_per_component);
- if (!rc_params)
- return -EINVAL;
+ ret = drm_dsc_setup_rc_params(vdsc_cfg);
+ if (ret)
+ return ret;
+
+ goto out;
}
vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
@@ -521,6 +215,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
}
+out:
/*
* BitsPerComponent value determines mux_word_size:
* When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 706ba1d34742..1681791f65a5 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -15,6 +15,7 @@ int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
#endif /* _DRM_DSC_HELPER_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper
@ 2023-02-28 11:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
This moves DSC RC tables to DRM DSC helper. No additional code changes
and/or cleanups are a part of this commit, it will be cleaned up in the
followup commits.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 364 ++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.c | 319 +------------------
include/drm/display/drm_dsc_helper.h | 1 +
3 files changed, 372 insertions(+), 312 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index ab8679c158b5..deaa84722bd4 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -307,6 +307,370 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
}
EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
+enum ROW_INDEX_BPP {
+ ROW_INDEX_6BPP = 0,
+ ROW_INDEX_8BPP,
+ ROW_INDEX_10BPP,
+ ROW_INDEX_12BPP,
+ ROW_INDEX_15BPP,
+ MAX_ROW_INDEX
+};
+
+enum COLUMN_INDEX_BPC {
+ COLUMN_INDEX_8BPC = 0,
+ COLUMN_INDEX_10BPC,
+ COLUMN_INDEX_12BPC,
+ COLUMN_INDEX_14BPC,
+ COLUMN_INDEX_16BPC,
+ MAX_COLUMN_INDEX
+};
+
+struct rc_parameters {
+ u16 initial_xmit_delay;
+ u8 first_line_bpg_offset;
+ u16 initial_offset;
+ u8 flatness_min_qp;
+ u8 flatness_max_qp;
+ u8 rc_quant_incr_limit0;
+ u8 rc_quant_incr_limit1;
+ struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+};
+
+/*
+ * Selected Rate Control Related Parameter Recommended Values
+ * from DSC_v1.11 spec & C Model release: DSC_model_20161212
+ */
+static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
+{
+ /* 6BPP/8BPC */
+ { 768, 15, 6144, 3, 13, 11, 11, {
+ { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
+ { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
+ { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
+ { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
+ }
+ },
+ /* 6BPP/10BPC */
+ { 768, 15, 6144, 7, 17, 15, 15, {
+ { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
+ { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
+ { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
+ { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
+ { 17, 18, -12 }
+ }
+ },
+ /* 6BPP/12BPC */
+ { 768, 15, 6144, 11, 21, 19, 19, {
+ { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
+ { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
+ { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
+ { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
+ { 21, 22, -12 }
+ }
+ },
+ /* 6BPP/14BPC */
+ { 768, 15, 6144, 15, 25, 23, 23, {
+ { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
+ { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
+ { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
+ { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
+ { 25, 26, -12 }
+ }
+ },
+ /* 6BPP/16BPC */
+ { 768, 15, 6144, 19, 29, 27, 27, {
+ { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
+ { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
+ { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
+ { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
+ { 29, 30, -12 }
+ }
+ },
+},
+{
+ /* 8BPP/8BPC */
+ { 512, 12, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
+ { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ },
+ /* 8BPP/10BPC */
+ { 512, 12, 6144, 7, 16, 15, 15, {
+ /*
+ * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
+ * VESA DSC 1.1 Table E-5 sets it to 4.
+ */
+ { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ },
+ /* 8BPP/12BPC */
+ { 512, 12, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ },
+ /* 8BPP/14BPC */
+ { 512, 12, 6144, 15, 24, 23, 23, {
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
+ { 24, 25, -12 }
+ }
+ },
+ /* 8BPP/16BPC */
+ { 512, 12, 6144, 19, 28, 27, 27, {
+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
+ { 28, 29, -12 }
+ }
+ },
+},
+{
+ /* 10BPP/8BPC */
+ { 410, 15, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
+ }
+ },
+ /* 10BPP/10BPC */
+ { 410, 15, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
+ }
+ },
+ /* 10BPP/12BPC */
+ { 410, 15, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
+ { 19, 20, -12 }
+ }
+ },
+ /* 10BPP/14BPC */
+ { 410, 15, 5632, 15, 24, 23, 23, {
+ { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
+ { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
+ { 23, 24, -12 }
+ }
+ },
+ /* 10BPP/16BPC */
+ { 410, 15, 5632, 19, 28, 27, 27, {
+ { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
+ { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
+ { 27, 28, -12 }
+ }
+ },
+},
+{
+ /* 12BPP/8BPC */
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
+ { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ },
+ /* 12BPP/10BPC */
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ },
+ /* 12BPP/12BPC */
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ },
+ /* 12BPP/14BPC */
+ { 341, 15, 2048, 15, 24, 23, 23, {
+ { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
+ { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
+ { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
+ { 22, 23, -12 }
+ }
+ },
+ /* 12BPP/16BPC */
+ { 341, 15, 2048, 19, 28, 27, 27, {
+ { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
+ { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
+ { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
+ { 26, 27, -12 }
+ }
+ },
+},
+{
+ /* 15BPP/8BPC */
+ { 273, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
+ { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
+ { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
+ }
+ },
+ /* 15BPP/10BPC */
+ { 273, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
+ { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
+ { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
+ }
+ },
+ /* 15BPP/12BPC */
+ { 273, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
+ { 16, 17, -12 }
+ }
+ },
+ /* 15BPP/14BPC */
+ { 273, 15, 2048, 15, 24, 23, 23, {
+ { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
+ { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
+ { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
+ { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
+ { 20, 21, -12 }
+ }
+ },
+ /* 15BPP/16BPC */
+ { 273, 15, 2048, 19, 28, 27, 27, {
+ { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
+ { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
+ { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
+ { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+}
+};
+
+static int get_row_index_for_rc_params(u16 compressed_bpp)
+{
+ switch (compressed_bpp) {
+ case 6:
+ return ROW_INDEX_6BPP;
+ case 8:
+ return ROW_INDEX_8BPP;
+ case 10:
+ return ROW_INDEX_10BPP;
+ case 12:
+ return ROW_INDEX_12BPP;
+ case 15:
+ return ROW_INDEX_15BPP;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int get_column_index_for_rc_params(u8 bits_per_component)
+{
+ switch (bits_per_component) {
+ case 8:
+ return COLUMN_INDEX_8BPC;
+ case 10:
+ return COLUMN_INDEX_10BPC;
+ case 12:
+ return COLUMN_INDEX_12BPC;
+ case 14:
+ return COLUMN_INDEX_14BPC;
+ case 16:
+ return COLUMN_INDEX_16BPC;
+ default:
+ return -EINVAL;
+ }
+}
+
+static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
+ u8 bits_per_component)
+{
+ int row_index, column_index;
+
+ row_index = get_row_index_for_rc_params(compressed_bpp);
+ if (row_index < 0)
+ return NULL;
+
+ column_index = get_column_index_for_rc_params(bits_per_component);
+ if (column_index < 0)
+ return NULL;
+
+ return &rc_parameters[row_index][column_index];
+}
+
+/**
+ * drm_dsc_compute_rc_parameters() - Set parameters and limits for RC model in
+ * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
+ *
+ * @vdsc_cfg: DSC Configuration data partially filled by driver
+ */
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
+{
+ const struct rc_parameters *rc_params;
+ int i;
+
+ /* fractional BPP is not supported */
+ if (vdsc_cfg->bits_per_pixel & 0xf)
+ return -EINVAL;
+
+ rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
+ vdsc_cfg->bits_per_component);
+ if (!rc_params)
+ return -EINVAL;
+
+ vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
+ vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
+ vdsc_cfg->initial_offset = rc_params->initial_offset;
+ vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
+ vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
+ vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
+ vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
+
+ for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
+ vdsc_cfg->rc_range_params[i].range_min_qp =
+ rc_params->rc_range_params[i].range_min_qp;
+ vdsc_cfg->rc_range_params[i].range_max_qp =
+ rc_params->rc_range_params[i].range_max_qp;
+ /*
+ * Range BPG Offset uses 2's complement and is only a 6 bits. So
+ * mask it to get only 6 bits.
+ */
+ vdsc_cfg->rc_range_params[i].range_bpg_offset =
+ rc_params->rc_range_params[i].range_bpg_offset &
+ DSC_RANGE_BPG_OFFSET_MASK;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dsc_setup_rc_params);
+
/**
* drm_dsc_compute_rc_parameters() - Write rate control
* parameters to the dsc configuration defined in
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index b4faab4c8fb3..d5a7e9494b23 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -18,24 +18,6 @@
#include "intel_qp_tables.h"
#include "intel_vdsc.h"
-enum ROW_INDEX_BPP {
- ROW_INDEX_6BPP = 0,
- ROW_INDEX_8BPP,
- ROW_INDEX_10BPP,
- ROW_INDEX_12BPP,
- ROW_INDEX_15BPP,
- MAX_ROW_INDEX
-};
-
-enum COLUMN_INDEX_BPC {
- COLUMN_INDEX_8BPC = 0,
- COLUMN_INDEX_10BPC,
- COLUMN_INDEX_12BPC,
- COLUMN_INDEX_14BPC,
- COLUMN_INDEX_16BPC,
- MAX_COLUMN_INDEX
-};
-
struct rc_parameters {
u16 initial_xmit_delay;
u8 first_line_bpg_offset;
@@ -47,296 +29,6 @@ struct rc_parameters {
struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
};
-/*
- * Selected Rate Control Related Parameter Recommended Values
- * from DSC_v1.11 spec & C Model release: DSC_model_20161212
- */
-static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
-{
- /* 6BPP/8BPC */
- { 768, 15, 6144, 3, 13, 11, 11, {
- { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
- { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
- { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
- { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
- }
- },
- /* 6BPP/10BPC */
- { 768, 15, 6144, 7, 17, 15, 15, {
- { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
- { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
- { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
- { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
- { 17, 18, -12 }
- }
- },
- /* 6BPP/12BPC */
- { 768, 15, 6144, 11, 21, 19, 19, {
- { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
- { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
- { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
- { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
- { 21, 22, -12 }
- }
- },
- /* 6BPP/14BPC */
- { 768, 15, 6144, 15, 25, 23, 23, {
- { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
- { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
- { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
- { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
- { 25, 26, -12 }
- }
- },
- /* 6BPP/16BPC */
- { 768, 15, 6144, 19, 29, 27, 27, {
- { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
- { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
- { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
- { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
- { 29, 30, -12 }
- }
- },
-},
-{
- /* 8BPP/8BPC */
- { 512, 12, 6144, 3, 12, 11, 11, {
- { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
- { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
- { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
- }
- },
- /* 8BPP/10BPC */
- { 512, 12, 6144, 7, 16, 15, 15, {
- /*
- * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
- * VESA DSC 1.1 Table E-5 sets it to 4.
- */
- { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
- { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
- }
- },
- /* 8BPP/12BPC */
- { 512, 12, 6144, 11, 20, 19, 19, {
- { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
- { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
- }
- },
- /* 8BPP/14BPC */
- { 512, 12, 6144, 15, 24, 23, 23, {
- { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
- { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
- { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
- { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
- { 24, 25, -12 }
- }
- },
- /* 8BPP/16BPC */
- { 512, 12, 6144, 19, 28, 27, 27, {
- { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
- { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
- { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
- { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
- { 28, 29, -12 }
- }
- },
-},
-{
- /* 10BPP/8BPC */
- { 410, 15, 5632, 3, 12, 11, 11, {
- { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
- { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
- { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
- }
- },
- /* 10BPP/10BPC */
- { 410, 15, 5632, 7, 16, 15, 15, {
- { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
- { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
- { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
- }
- },
- /* 10BPP/12BPC */
- { 410, 15, 5632, 11, 20, 19, 19, {
- { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
- { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
- { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
- { 19, 20, -12 }
- }
- },
- /* 10BPP/14BPC */
- { 410, 15, 5632, 15, 24, 23, 23, {
- { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
- { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
- { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
- { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
- { 23, 24, -12 }
- }
- },
- /* 10BPP/16BPC */
- { 410, 15, 5632, 19, 28, 27, 27, {
- { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
- { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
- { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
- { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
- { 27, 28, -12 }
- }
- },
-},
-{
- /* 12BPP/8BPC */
- { 341, 15, 2048, 3, 12, 11, 11, {
- { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
- { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
- { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
- }
- },
- /* 12BPP/10BPC */
- { 341, 15, 2048, 7, 16, 15, 15, {
- { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
- { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
- }
- },
- /* 12BPP/12BPC */
- { 341, 15, 2048, 11, 20, 19, 19, {
- { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
- { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
- }
- },
- /* 12BPP/14BPC */
- { 341, 15, 2048, 15, 24, 23, 23, {
- { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
- { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
- { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
- { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
- { 22, 23, -12 }
- }
- },
- /* 12BPP/16BPC */
- { 341, 15, 2048, 19, 28, 27, 27, {
- { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
- { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
- { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
- { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
- { 26, 27, -12 }
- }
- },
-},
-{
- /* 15BPP/8BPC */
- { 273, 15, 2048, 3, 12, 11, 11, {
- { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
- { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
- { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
- { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
- }
- },
- /* 15BPP/10BPC */
- { 273, 15, 2048, 7, 16, 15, 15, {
- { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
- { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
- { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
- { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
- }
- },
- /* 15BPP/12BPC */
- { 273, 15, 2048, 11, 20, 19, 19, {
- { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
- { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
- { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
- { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
- { 16, 17, -12 }
- }
- },
- /* 15BPP/14BPC */
- { 273, 15, 2048, 15, 24, 23, 23, {
- { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
- { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
- { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
- { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
- { 20, 21, -12 }
- }
- },
- /* 15BPP/16BPC */
- { 273, 15, 2048, 19, 28, 27, 27, {
- { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
- { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
- { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
- { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
- { 24, 25, -12 }
- }
- }
-}
-
-};
-
-static int get_row_index_for_rc_params(u16 compressed_bpp)
-{
- switch (compressed_bpp) {
- case 6:
- return ROW_INDEX_6BPP;
- case 8:
- return ROW_INDEX_8BPP;
- case 10:
- return ROW_INDEX_10BPP;
- case 12:
- return ROW_INDEX_12BPP;
- case 15:
- return ROW_INDEX_15BPP;
- default:
- return -EINVAL;
- }
-}
-
-static int get_column_index_for_rc_params(u8 bits_per_component)
-{
- switch (bits_per_component) {
- case 8:
- return COLUMN_INDEX_8BPC;
- case 10:
- return COLUMN_INDEX_10BPC;
- case 12:
- return COLUMN_INDEX_12BPC;
- case 14:
- return COLUMN_INDEX_14BPC;
- case 16:
- return COLUMN_INDEX_16BPC;
- default:
- return -EINVAL;
- }
-}
-
-static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
- u8 bits_per_component)
-{
- int row_index, column_index;
-
- row_index = get_row_index_for_rc_params(compressed_bpp);
- if (row_index < 0)
- return NULL;
-
- column_index = get_column_index_for_rc_params(bits_per_component);
- if (column_index < 0)
- return NULL;
-
- return &rc_parameters[row_index][column_index];
-}
-
bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
{
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -454,6 +146,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
const struct rc_parameters *rc_params;
struct rc_parameters *rc = NULL;
u8 i = 0;
+ int ret;
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
@@ -483,10 +176,11 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
calculate_rc_params(rc, vdsc_cfg);
rc_params = rc;
} else {
- rc_params = get_rc_params(compressed_bpp,
- vdsc_cfg->bits_per_component);
- if (!rc_params)
- return -EINVAL;
+ ret = drm_dsc_setup_rc_params(vdsc_cfg);
+ if (ret)
+ return ret;
+
+ goto out;
}
vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
@@ -521,6 +215,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
}
+out:
/*
* BitsPerComponent value determines mux_word_size:
* When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 706ba1d34742..1681791f65a5 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -15,6 +15,7 @@ int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
#endif /* _DRM_DSC_HELPER_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 04/10] drm/i915/dsc: stop using interim structure for calculated params
2023-02-28 11:33 ` Dmitry Baryshkov
(?)
@ 2023-02-28 11:33 ` Dmitry Baryshkov
-1 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
Stop using an interim structure rc_parameters for storing calculated
params and then setting drm_dsc_config using that structure. Instead put
calculated params into the struct drm_dsc_config directly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 89 +++++------------------
1 file changed, 20 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index d5a7e9494b23..1ee8d13c9d64 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -18,17 +18,6 @@
#include "intel_qp_tables.h"
#include "intel_vdsc.h"
-struct rc_parameters {
- u16 initial_xmit_delay;
- u8 first_line_bpg_offset;
- u16 initial_offset;
- u8 flatness_min_qp;
- u8 flatness_max_qp;
- u8 rc_quant_incr_limit0;
- u8 rc_quant_incr_limit1;
- struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
-};
-
bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
{
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -63,8 +52,7 @@ static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
}
static void
-calculate_rc_params(struct rc_parameters *rc,
- struct drm_dsc_config *vdsc_cfg)
+calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
{
int bpc = vdsc_cfg->bits_per_component;
int bpp = vdsc_cfg->bits_per_pixel >> 4;
@@ -84,54 +72,54 @@ calculate_rc_params(struct rc_parameters *rc,
u32 res, buf_i, bpp_i;
if (vdsc_cfg->slice_height >= 8)
- rc->first_line_bpg_offset =
+ vdsc_cfg->first_line_bpg_offset =
12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);
else
- rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
+ vdsc_cfg->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
/* Our hw supports only 444 modes as of today */
if (bpp >= 12)
- rc->initial_offset = 2048;
+ vdsc_cfg->initial_offset = 2048;
else if (bpp >= 10)
- rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
+ vdsc_cfg->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
else if (bpp >= 8)
- rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
+ vdsc_cfg->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
else
- rc->initial_offset = 6144;
+ vdsc_cfg->initial_offset = 6144;
/* initial_xmit_delay = rc_model_size/2/compression_bpp */
- rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
+ vdsc_cfg->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
- rc->flatness_min_qp = 3 + qp_bpc_modifier;
- rc->flatness_max_qp = 12 + qp_bpc_modifier;
+ vdsc_cfg->flatness_min_qp = 3 + qp_bpc_modifier;
+ vdsc_cfg->flatness_max_qp = 12 + qp_bpc_modifier;
- rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
- rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
+ vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
+ vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
bpp_i = (2 * (bpp - 6));
for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
/* Read range_minqp and range_max_qp from qp tables */
- rc->rc_range_params[buf_i].range_min_qp =
+ vdsc_cfg->rc_range_params[buf_i].range_min_qp =
intel_lookup_range_min_qp(bpc, buf_i, bpp_i);
- rc->rc_range_params[buf_i].range_max_qp =
+ vdsc_cfg->rc_range_params[buf_i].range_max_qp =
intel_lookup_range_max_qp(bpc, buf_i, bpp_i);
/* Calculate range_bgp_offset */
if (bpp <= 6) {
- rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
+ vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
} else if (bpp <= 8) {
res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
- rc->rc_range_params[buf_i].range_bpg_offset =
+ vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
ofs_und6[buf_i] + res;
} else if (bpp <= 12) {
- rc->rc_range_params[buf_i].range_bpg_offset =
+ vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
ofs_und8[buf_i];
} else if (bpp <= 15) {
res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
- rc->rc_range_params[buf_i].range_bpg_offset =
+ vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
ofs_und12[buf_i] + res;
} else {
- rc->rc_range_params[buf_i].range_bpg_offset =
+ vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
ofs_und15[buf_i];
}
}
@@ -143,9 +131,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
- const struct rc_parameters *rc_params;
- struct rc_parameters *rc = NULL;
- u8 i = 0;
int ret;
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
@@ -169,43 +154,12 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
* parameters
*/
if (DISPLAY_VER(dev_priv) >= 13) {
- rc = kmalloc(sizeof(*rc), GFP_KERNEL);
- if (!rc)
- return -ENOMEM;
-
- calculate_rc_params(rc, vdsc_cfg);
- rc_params = rc;
+ calculate_rc_params(vdsc_cfg);
} else {
ret = drm_dsc_setup_rc_params(vdsc_cfg);
if (ret)
return ret;
- goto out;
- }
-
- vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
- vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
- vdsc_cfg->initial_offset = rc_params->initial_offset;
- vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
- vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
- vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
- vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
-
- for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
- vdsc_cfg->rc_range_params[i].range_min_qp =
- rc_params->rc_range_params[i].range_min_qp;
- vdsc_cfg->rc_range_params[i].range_max_qp =
- rc_params->rc_range_params[i].range_max_qp;
- /*
- * Range BPG Offset uses 2's complement and is only a 6 bits. So
- * mask it to get only 6 bits.
- */
- vdsc_cfg->rc_range_params[i].range_bpg_offset =
- rc_params->rc_range_params[i].range_bpg_offset &
- DSC_RANGE_BPG_OFFSET_MASK;
- }
-
- if (DISPLAY_VER(dev_priv) < 13) {
if (compressed_bpp == 6 &&
vdsc_cfg->bits_per_component == 8)
vdsc_cfg->rc_quant_incr_limit1 = 23;
@@ -215,7 +169,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
}
-out:
/*
* BitsPerComponent value determines mux_word_size:
* When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
@@ -230,8 +183,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
- kfree(rc);
-
return 0;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 04/10] drm/i915/dsc: stop using interim structure for calculated params
@ 2023-02-28 11:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
Stop using an interim structure rc_parameters for storing calculated
params and then setting drm_dsc_config using that structure. Instead put
calculated params into the struct drm_dsc_config directly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 89 +++++------------------
1 file changed, 20 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index d5a7e9494b23..1ee8d13c9d64 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -18,17 +18,6 @@
#include "intel_qp_tables.h"
#include "intel_vdsc.h"
-struct rc_parameters {
- u16 initial_xmit_delay;
- u8 first_line_bpg_offset;
- u16 initial_offset;
- u8 flatness_min_qp;
- u8 flatness_max_qp;
- u8 rc_quant_incr_limit0;
- u8 rc_quant_incr_limit1;
- struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
-};
-
bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
{
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -63,8 +52,7 @@ static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
}
static void
-calculate_rc_params(struct rc_parameters *rc,
- struct drm_dsc_config *vdsc_cfg)
+calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
{
int bpc = vdsc_cfg->bits_per_component;
int bpp = vdsc_cfg->bits_per_pixel >> 4;
@@ -84,54 +72,54 @@ calculate_rc_params(struct rc_parameters *rc,
u32 res, buf_i, bpp_i;
if (vdsc_cfg->slice_height >= 8)
- rc->first_line_bpg_offset =
+ vdsc_cfg->first_line_bpg_offset =
12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);
else
- rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
+ vdsc_cfg->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
/* Our hw supports only 444 modes as of today */
if (bpp >= 12)
- rc->initial_offset = 2048;
+ vdsc_cfg->initial_offset = 2048;
else if (bpp >= 10)
- rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
+ vdsc_cfg->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
else if (bpp >= 8)
- rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
+ vdsc_cfg->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
else
- rc->initial_offset = 6144;
+ vdsc_cfg->initial_offset = 6144;
/* initial_xmit_delay = rc_model_size/2/compression_bpp */
- rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
+ vdsc_cfg->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
- rc->flatness_min_qp = 3 + qp_bpc_modifier;
- rc->flatness_max_qp = 12 + qp_bpc_modifier;
+ vdsc_cfg->flatness_min_qp = 3 + qp_bpc_modifier;
+ vdsc_cfg->flatness_max_qp = 12 + qp_bpc_modifier;
- rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
- rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
+ vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
+ vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
bpp_i = (2 * (bpp - 6));
for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
/* Read range_minqp and range_max_qp from qp tables */
- rc->rc_range_params[buf_i].range_min_qp =
+ vdsc_cfg->rc_range_params[buf_i].range_min_qp =
intel_lookup_range_min_qp(bpc, buf_i, bpp_i);
- rc->rc_range_params[buf_i].range_max_qp =
+ vdsc_cfg->rc_range_params[buf_i].range_max_qp =
intel_lookup_range_max_qp(bpc, buf_i, bpp_i);
/* Calculate range_bgp_offset */
if (bpp <= 6) {
- rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
+ vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
} else if (bpp <= 8) {
res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
- rc->rc_range_params[buf_i].range_bpg_offset =
+ vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
ofs_und6[buf_i] + res;
} else if (bpp <= 12) {
- rc->rc_range_params[buf_i].range_bpg_offset =
+ vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
ofs_und8[buf_i];
} else if (bpp <= 15) {
res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
- rc->rc_range_params[buf_i].range_bpg_offset =
+ vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
ofs_und12[buf_i] + res;
} else {
- rc->rc_range_params[buf_i].range_bpg_offset =
+ vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
ofs_und15[buf_i];
}
}
@@ -143,9 +131,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
- const struct rc_parameters *rc_params;
- struct rc_parameters *rc = NULL;
- u8 i = 0;
int ret;
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
@@ -169,43 +154,12 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
* parameters
*/
if (DISPLAY_VER(dev_priv) >= 13) {
- rc = kmalloc(sizeof(*rc), GFP_KERNEL);
- if (!rc)
- return -ENOMEM;
-
- calculate_rc_params(rc, vdsc_cfg);
- rc_params = rc;
+ calculate_rc_params(vdsc_cfg);
} else {
ret = drm_dsc_setup_rc_params(vdsc_cfg);
if (ret)
return ret;
- goto out;
- }
-
- vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
- vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
- vdsc_cfg->initial_offset = rc_params->initial_offset;
- vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
- vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
- vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
- vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
-
- for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
- vdsc_cfg->rc_range_params[i].range_min_qp =
- rc_params->rc_range_params[i].range_min_qp;
- vdsc_cfg->rc_range_params[i].range_max_qp =
- rc_params->rc_range_params[i].range_max_qp;
- /*
- * Range BPG Offset uses 2's complement and is only a 6 bits. So
- * mask it to get only 6 bits.
- */
- vdsc_cfg->rc_range_params[i].range_bpg_offset =
- rc_params->rc_range_params[i].range_bpg_offset &
- DSC_RANGE_BPG_OFFSET_MASK;
- }
-
- if (DISPLAY_VER(dev_priv) < 13) {
if (compressed_bpp == 6 &&
vdsc_cfg->bits_per_component == 8)
vdsc_cfg->rc_quant_incr_limit1 = 23;
@@ -215,7 +169,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
}
-out:
/*
* BitsPerComponent value determines mux_word_size:
* When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
@@ -230,8 +183,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
- kfree(rc);
-
return 0;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH 04/10] drm/i915/dsc: stop using interim structure for calculated params
@ 2023-02-28 11:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
Stop using an interim structure rc_parameters for storing calculated
params and then setting drm_dsc_config using that structure. Instead put
calculated params into the struct drm_dsc_config directly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 89 +++++------------------
1 file changed, 20 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index d5a7e9494b23..1ee8d13c9d64 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -18,17 +18,6 @@
#include "intel_qp_tables.h"
#include "intel_vdsc.h"
-struct rc_parameters {
- u16 initial_xmit_delay;
- u8 first_line_bpg_offset;
- u16 initial_offset;
- u8 flatness_min_qp;
- u8 flatness_max_qp;
- u8 rc_quant_incr_limit0;
- u8 rc_quant_incr_limit1;
- struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
-};
-
bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
{
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -63,8 +52,7 @@ static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
}
static void
-calculate_rc_params(struct rc_parameters *rc,
- struct drm_dsc_config *vdsc_cfg)
+calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
{
int bpc = vdsc_cfg->bits_per_component;
int bpp = vdsc_cfg->bits_per_pixel >> 4;
@@ -84,54 +72,54 @@ calculate_rc_params(struct rc_parameters *rc,
u32 res, buf_i, bpp_i;
if (vdsc_cfg->slice_height >= 8)
- rc->first_line_bpg_offset =
+ vdsc_cfg->first_line_bpg_offset =
12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);
else
- rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
+ vdsc_cfg->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
/* Our hw supports only 444 modes as of today */
if (bpp >= 12)
- rc->initial_offset = 2048;
+ vdsc_cfg->initial_offset = 2048;
else if (bpp >= 10)
- rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
+ vdsc_cfg->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
else if (bpp >= 8)
- rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
+ vdsc_cfg->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
else
- rc->initial_offset = 6144;
+ vdsc_cfg->initial_offset = 6144;
/* initial_xmit_delay = rc_model_size/2/compression_bpp */
- rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
+ vdsc_cfg->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
- rc->flatness_min_qp = 3 + qp_bpc_modifier;
- rc->flatness_max_qp = 12 + qp_bpc_modifier;
+ vdsc_cfg->flatness_min_qp = 3 + qp_bpc_modifier;
+ vdsc_cfg->flatness_max_qp = 12 + qp_bpc_modifier;
- rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
- rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
+ vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
+ vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
bpp_i = (2 * (bpp - 6));
for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
/* Read range_minqp and range_max_qp from qp tables */
- rc->rc_range_params[buf_i].range_min_qp =
+ vdsc_cfg->rc_range_params[buf_i].range_min_qp =
intel_lookup_range_min_qp(bpc, buf_i, bpp_i);
- rc->rc_range_params[buf_i].range_max_qp =
+ vdsc_cfg->rc_range_params[buf_i].range_max_qp =
intel_lookup_range_max_qp(bpc, buf_i, bpp_i);
/* Calculate range_bgp_offset */
if (bpp <= 6) {
- rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
+ vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
} else if (bpp <= 8) {
res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
- rc->rc_range_params[buf_i].range_bpg_offset =
+ vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
ofs_und6[buf_i] + res;
} else if (bpp <= 12) {
- rc->rc_range_params[buf_i].range_bpg_offset =
+ vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
ofs_und8[buf_i];
} else if (bpp <= 15) {
res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
- rc->rc_range_params[buf_i].range_bpg_offset =
+ vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
ofs_und12[buf_i] + res;
} else {
- rc->rc_range_params[buf_i].range_bpg_offset =
+ vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
ofs_und15[buf_i];
}
}
@@ -143,9 +131,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
- const struct rc_parameters *rc_params;
- struct rc_parameters *rc = NULL;
- u8 i = 0;
int ret;
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
@@ -169,43 +154,12 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
* parameters
*/
if (DISPLAY_VER(dev_priv) >= 13) {
- rc = kmalloc(sizeof(*rc), GFP_KERNEL);
- if (!rc)
- return -ENOMEM;
-
- calculate_rc_params(rc, vdsc_cfg);
- rc_params = rc;
+ calculate_rc_params(vdsc_cfg);
} else {
ret = drm_dsc_setup_rc_params(vdsc_cfg);
if (ret)
return ret;
- goto out;
- }
-
- vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
- vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
- vdsc_cfg->initial_offset = rc_params->initial_offset;
- vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
- vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
- vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
- vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
-
- for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
- vdsc_cfg->rc_range_params[i].range_min_qp =
- rc_params->rc_range_params[i].range_min_qp;
- vdsc_cfg->rc_range_params[i].range_max_qp =
- rc_params->rc_range_params[i].range_max_qp;
- /*
- * Range BPG Offset uses 2's complement and is only a 6 bits. So
- * mask it to get only 6 bits.
- */
- vdsc_cfg->rc_range_params[i].range_bpg_offset =
- rc_params->rc_range_params[i].range_bpg_offset &
- DSC_RANGE_BPG_OFFSET_MASK;
- }
-
- if (DISPLAY_VER(dev_priv) < 13) {
if (compressed_bpp == 6 &&
vdsc_cfg->bits_per_component == 8)
vdsc_cfg->rc_quant_incr_limit1 = 23;
@@ -215,7 +169,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
}
-out:
/*
* BitsPerComponent value determines mux_word_size:
* When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
@@ -230,8 +183,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
- kfree(rc);
-
return 0;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 05/10] drm/display/dsc: use flat array for rc_parameters lookup
2023-02-28 11:33 ` Dmitry Baryshkov
(?)
@ 2023-02-28 11:33 ` Dmitry Baryshkov
-1 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
Next commits are going to add support for additional RC parameter lookup
tables. These tables are going to use different bpp/bpc combinations,
thus it makes little sense to keep the 2d array for RC parameters.
Switch to using the flat array.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 188 +++++++++++------------
1 file changed, 88 insertions(+), 100 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index deaa84722bd4..a6d11f474656 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -307,24 +307,6 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
}
EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
-enum ROW_INDEX_BPP {
- ROW_INDEX_6BPP = 0,
- ROW_INDEX_8BPP,
- ROW_INDEX_10BPP,
- ROW_INDEX_12BPP,
- ROW_INDEX_15BPP,
- MAX_ROW_INDEX
-};
-
-enum COLUMN_INDEX_BPC {
- COLUMN_INDEX_8BPC = 0,
- COLUMN_INDEX_10BPC,
- COLUMN_INDEX_12BPC,
- COLUMN_INDEX_14BPC,
- COLUMN_INDEX_16BPC,
- MAX_COLUMN_INDEX
-};
-
struct rc_parameters {
u16 initial_xmit_delay;
u8 first_line_bpg_offset;
@@ -336,12 +318,20 @@ struct rc_parameters {
struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
};
+struct rc_parameters_data {
+ u8 bpp;
+ u8 bpc;
+ struct rc_parameters params;
+};
+
+#define DSC_BPP(bpp) ((bpp) << 4)
+
/*
* Selected Rate Control Related Parameter Recommended Values
* from DSC_v1.11 spec & C Model release: DSC_model_20161212
*/
-static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
-{
+static const struct rc_parameters_data rc_parameters[] = {
+{ DSC_BPP(6), 8,
/* 6BPP/8BPC */
{ 768, 15, 6144, 3, 13, 11, 11, {
{ 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
@@ -349,7 +339,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
{ 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
}
- },
+ }
+},
+{ DSC_BPP(6), 10,
/* 6BPP/10BPC */
{ 768, 15, 6144, 7, 17, 15, 15, {
{ 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
@@ -358,7 +350,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
{ 17, 18, -12 }
}
- },
+ }
+},
+{ DSC_BPP(6), 12,
/* 6BPP/12BPC */
{ 768, 15, 6144, 11, 21, 19, 19, {
{ 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
@@ -367,7 +361,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
{ 21, 22, -12 }
}
- },
+ }
+},
+{ DSC_BPP(6), 14,
/* 6BPP/14BPC */
{ 768, 15, 6144, 15, 25, 23, 23, {
{ 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
@@ -376,7 +372,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
{ 25, 26, -12 }
}
- },
+ }
+},
+{ DSC_BPP(6), 16,
/* 6BPP/16BPC */
{ 768, 15, 6144, 19, 29, 27, 27, {
{ 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
@@ -385,9 +383,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
{ 29, 30, -12 }
}
- },
+ }
},
-{
+{ DSC_BPP(8), 8,
/* 8BPP/8BPC */
{ 512, 12, 6144, 3, 12, 11, 11, {
{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
@@ -395,7 +393,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
{ 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
}
- },
+ }
+},
+{ DSC_BPP(8), 10,
/* 8BPP/10BPC */
{ 512, 12, 6144, 7, 16, 15, 15, {
/*
@@ -407,7 +407,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
}
- },
+ }
+},
+{ DSC_BPP(8), 12,
/* 8BPP/12BPC */
{ 512, 12, 6144, 11, 20, 19, 19, {
{ 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
@@ -416,7 +418,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
{ 21, 23, -12 }
}
- },
+ }
+},
+{ DSC_BPP(8), 14,
/* 8BPP/14BPC */
{ 512, 12, 6144, 15, 24, 23, 23, {
{ 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
@@ -425,7 +429,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
{ 24, 25, -12 }
}
- },
+ }
+},
+{ DSC_BPP(8), 16,
/* 8BPP/16BPC */
{ 512, 12, 6144, 19, 28, 27, 27, {
{ 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
@@ -434,9 +440,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
{ 28, 29, -12 }
}
- },
+ }
},
-{
+{ DSC_BPP(10), 8,
/* 10BPP/8BPC */
{ 410, 15, 5632, 3, 12, 11, 11, {
{ 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
@@ -444,7 +450,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
{ 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
}
- },
+ }
+},
+{ DSC_BPP(10), 10,
/* 10BPP/10BPC */
{ 410, 15, 5632, 7, 16, 15, 15, {
{ 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
@@ -452,7 +460,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
{ 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
}
- },
+ }
+},
+{ DSC_BPP(10), 12,
/* 10BPP/12BPC */
{ 410, 15, 5632, 11, 20, 19, 19, {
{ 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
@@ -461,7 +471,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
{ 19, 20, -12 }
}
- },
+ }
+},
+{ DSC_BPP(10), 14,
/* 10BPP/14BPC */
{ 410, 15, 5632, 15, 24, 23, 23, {
{ 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
@@ -470,7 +482,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
{ 23, 24, -12 }
}
- },
+ }
+},
+{ DSC_BPP(10), 16,
/* 10BPP/16BPC */
{ 410, 15, 5632, 19, 28, 27, 27, {
{ 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
@@ -479,9 +493,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
{ 27, 28, -12 }
}
- },
+ }
},
-{
+{ DSC_BPP(12), 8,
/* 12BPP/8BPC */
{ 341, 15, 2048, 3, 12, 11, 11, {
{ 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
@@ -489,7 +503,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
{ 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
}
- },
+ }
+},
+{ DSC_BPP(12), 10,
/* 12BPP/10BPC */
{ 341, 15, 2048, 7, 16, 15, 15, {
{ 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
@@ -497,7 +513,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
}
- },
+ }
+},
+{ DSC_BPP(12), 12,
/* 12BPP/12BPC */
{ 341, 15, 2048, 11, 20, 19, 19, {
{ 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
@@ -506,7 +524,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
{ 21, 23, -12 }
}
- },
+ }
+},
+{ DSC_BPP(12), 14,
/* 12BPP/14BPC */
{ 341, 15, 2048, 15, 24, 23, 23, {
{ 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
@@ -515,7 +535,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
{ 22, 23, -12 }
}
- },
+ }
+},
+{ DSC_BPP(12), 16,
/* 12BPP/16BPC */
{ 341, 15, 2048, 19, 28, 27, 27, {
{ 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
@@ -524,9 +546,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
{ 26, 27, -12 }
}
- },
+ }
},
-{
+{ DSC_BPP(15), 8,
/* 15BPP/8BPC */
{ 273, 15, 2048, 3, 12, 11, 11, {
{ 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
@@ -534,7 +556,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
{ 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
}
- },
+ }
+},
+{ DSC_BPP(15), 10,
/* 15BPP/10BPC */
{ 273, 15, 2048, 7, 16, 15, 15, {
{ 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
@@ -542,7 +566,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
{ 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
}
- },
+ }
+},
+{ DSC_BPP(15), 12,
/* 15BPP/12BPC */
{ 273, 15, 2048, 11, 20, 19, 19, {
{ 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
@@ -551,7 +577,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
{ 16, 17, -12 }
}
- },
+ }
+},
+{ DSC_BPP(15), 14,
/* 15BPP/14BPC */
{ 273, 15, 2048, 15, 24, 23, 23, {
{ 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
@@ -560,7 +588,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
{ 20, 21, -12 }
}
- },
+ }
+},
+{ DSC_BPP(15), 16,
/* 15BPP/16BPC */
{ 273, 15, 2048, 19, 28, 27, 27, {
{ 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
@@ -570,59 +600,21 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 24, 25, -12 }
}
}
-}
+},
+{ /* sentinel */ }
};
-static int get_row_index_for_rc_params(u16 compressed_bpp)
-{
- switch (compressed_bpp) {
- case 6:
- return ROW_INDEX_6BPP;
- case 8:
- return ROW_INDEX_8BPP;
- case 10:
- return ROW_INDEX_10BPP;
- case 12:
- return ROW_INDEX_12BPP;
- case 15:
- return ROW_INDEX_15BPP;
- default:
- return -EINVAL;
- }
-}
-
-static int get_column_index_for_rc_params(u8 bits_per_component)
-{
- switch (bits_per_component) {
- case 8:
- return COLUMN_INDEX_8BPC;
- case 10:
- return COLUMN_INDEX_10BPC;
- case 12:
- return COLUMN_INDEX_12BPC;
- case 14:
- return COLUMN_INDEX_14BPC;
- case 16:
- return COLUMN_INDEX_16BPC;
- default:
- return -EINVAL;
- }
-}
-
-static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
+static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
u8 bits_per_component)
{
- int row_index, column_index;
-
- row_index = get_row_index_for_rc_params(compressed_bpp);
- if (row_index < 0)
- return NULL;
+ int i;
- column_index = get_column_index_for_rc_params(bits_per_component);
- if (column_index < 0)
- return NULL;
+ for (i = 0; rc_parameters[i].bpp; i++)
+ if (rc_parameters[i].bpp == dsc_bpp &&
+ rc_parameters[i].bpc == bits_per_component)
+ return &rc_parameters[i].params;
- return &rc_parameters[row_index][column_index];
+ return NULL;
}
/**
@@ -636,11 +628,7 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
const struct rc_parameters *rc_params;
int i;
- /* fractional BPP is not supported */
- if (vdsc_cfg->bits_per_pixel & 0xf)
- return -EINVAL;
-
- rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
+ rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
vdsc_cfg->bits_per_component);
if (!rc_params)
return -EINVAL;
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 05/10] drm/display/dsc: use flat array for rc_parameters lookup
@ 2023-02-28 11:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
Next commits are going to add support for additional RC parameter lookup
tables. These tables are going to use different bpp/bpc combinations,
thus it makes little sense to keep the 2d array for RC parameters.
Switch to using the flat array.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 188 +++++++++++------------
1 file changed, 88 insertions(+), 100 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index deaa84722bd4..a6d11f474656 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -307,24 +307,6 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
}
EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
-enum ROW_INDEX_BPP {
- ROW_INDEX_6BPP = 0,
- ROW_INDEX_8BPP,
- ROW_INDEX_10BPP,
- ROW_INDEX_12BPP,
- ROW_INDEX_15BPP,
- MAX_ROW_INDEX
-};
-
-enum COLUMN_INDEX_BPC {
- COLUMN_INDEX_8BPC = 0,
- COLUMN_INDEX_10BPC,
- COLUMN_INDEX_12BPC,
- COLUMN_INDEX_14BPC,
- COLUMN_INDEX_16BPC,
- MAX_COLUMN_INDEX
-};
-
struct rc_parameters {
u16 initial_xmit_delay;
u8 first_line_bpg_offset;
@@ -336,12 +318,20 @@ struct rc_parameters {
struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
};
+struct rc_parameters_data {
+ u8 bpp;
+ u8 bpc;
+ struct rc_parameters params;
+};
+
+#define DSC_BPP(bpp) ((bpp) << 4)
+
/*
* Selected Rate Control Related Parameter Recommended Values
* from DSC_v1.11 spec & C Model release: DSC_model_20161212
*/
-static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
-{
+static const struct rc_parameters_data rc_parameters[] = {
+{ DSC_BPP(6), 8,
/* 6BPP/8BPC */
{ 768, 15, 6144, 3, 13, 11, 11, {
{ 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
@@ -349,7 +339,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
{ 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
}
- },
+ }
+},
+{ DSC_BPP(6), 10,
/* 6BPP/10BPC */
{ 768, 15, 6144, 7, 17, 15, 15, {
{ 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
@@ -358,7 +350,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
{ 17, 18, -12 }
}
- },
+ }
+},
+{ DSC_BPP(6), 12,
/* 6BPP/12BPC */
{ 768, 15, 6144, 11, 21, 19, 19, {
{ 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
@@ -367,7 +361,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
{ 21, 22, -12 }
}
- },
+ }
+},
+{ DSC_BPP(6), 14,
/* 6BPP/14BPC */
{ 768, 15, 6144, 15, 25, 23, 23, {
{ 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
@@ -376,7 +372,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
{ 25, 26, -12 }
}
- },
+ }
+},
+{ DSC_BPP(6), 16,
/* 6BPP/16BPC */
{ 768, 15, 6144, 19, 29, 27, 27, {
{ 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
@@ -385,9 +383,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
{ 29, 30, -12 }
}
- },
+ }
},
-{
+{ DSC_BPP(8), 8,
/* 8BPP/8BPC */
{ 512, 12, 6144, 3, 12, 11, 11, {
{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
@@ -395,7 +393,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
{ 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
}
- },
+ }
+},
+{ DSC_BPP(8), 10,
/* 8BPP/10BPC */
{ 512, 12, 6144, 7, 16, 15, 15, {
/*
@@ -407,7 +407,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
}
- },
+ }
+},
+{ DSC_BPP(8), 12,
/* 8BPP/12BPC */
{ 512, 12, 6144, 11, 20, 19, 19, {
{ 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
@@ -416,7 +418,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
{ 21, 23, -12 }
}
- },
+ }
+},
+{ DSC_BPP(8), 14,
/* 8BPP/14BPC */
{ 512, 12, 6144, 15, 24, 23, 23, {
{ 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
@@ -425,7 +429,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
{ 24, 25, -12 }
}
- },
+ }
+},
+{ DSC_BPP(8), 16,
/* 8BPP/16BPC */
{ 512, 12, 6144, 19, 28, 27, 27, {
{ 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
@@ -434,9 +440,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
{ 28, 29, -12 }
}
- },
+ }
},
-{
+{ DSC_BPP(10), 8,
/* 10BPP/8BPC */
{ 410, 15, 5632, 3, 12, 11, 11, {
{ 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
@@ -444,7 +450,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
{ 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
}
- },
+ }
+},
+{ DSC_BPP(10), 10,
/* 10BPP/10BPC */
{ 410, 15, 5632, 7, 16, 15, 15, {
{ 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
@@ -452,7 +460,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
{ 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
}
- },
+ }
+},
+{ DSC_BPP(10), 12,
/* 10BPP/12BPC */
{ 410, 15, 5632, 11, 20, 19, 19, {
{ 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
@@ -461,7 +471,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
{ 19, 20, -12 }
}
- },
+ }
+},
+{ DSC_BPP(10), 14,
/* 10BPP/14BPC */
{ 410, 15, 5632, 15, 24, 23, 23, {
{ 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
@@ -470,7 +482,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
{ 23, 24, -12 }
}
- },
+ }
+},
+{ DSC_BPP(10), 16,
/* 10BPP/16BPC */
{ 410, 15, 5632, 19, 28, 27, 27, {
{ 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
@@ -479,9 +493,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
{ 27, 28, -12 }
}
- },
+ }
},
-{
+{ DSC_BPP(12), 8,
/* 12BPP/8BPC */
{ 341, 15, 2048, 3, 12, 11, 11, {
{ 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
@@ -489,7 +503,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
{ 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
}
- },
+ }
+},
+{ DSC_BPP(12), 10,
/* 12BPP/10BPC */
{ 341, 15, 2048, 7, 16, 15, 15, {
{ 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
@@ -497,7 +513,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
}
- },
+ }
+},
+{ DSC_BPP(12), 12,
/* 12BPP/12BPC */
{ 341, 15, 2048, 11, 20, 19, 19, {
{ 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
@@ -506,7 +524,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
{ 21, 23, -12 }
}
- },
+ }
+},
+{ DSC_BPP(12), 14,
/* 12BPP/14BPC */
{ 341, 15, 2048, 15, 24, 23, 23, {
{ 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
@@ -515,7 +535,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
{ 22, 23, -12 }
}
- },
+ }
+},
+{ DSC_BPP(12), 16,
/* 12BPP/16BPC */
{ 341, 15, 2048, 19, 28, 27, 27, {
{ 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
@@ -524,9 +546,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
{ 26, 27, -12 }
}
- },
+ }
},
-{
+{ DSC_BPP(15), 8,
/* 15BPP/8BPC */
{ 273, 15, 2048, 3, 12, 11, 11, {
{ 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
@@ -534,7 +556,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
{ 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
}
- },
+ }
+},
+{ DSC_BPP(15), 10,
/* 15BPP/10BPC */
{ 273, 15, 2048, 7, 16, 15, 15, {
{ 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
@@ -542,7 +566,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
{ 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
}
- },
+ }
+},
+{ DSC_BPP(15), 12,
/* 15BPP/12BPC */
{ 273, 15, 2048, 11, 20, 19, 19, {
{ 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
@@ -551,7 +577,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
{ 16, 17, -12 }
}
- },
+ }
+},
+{ DSC_BPP(15), 14,
/* 15BPP/14BPC */
{ 273, 15, 2048, 15, 24, 23, 23, {
{ 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
@@ -560,7 +588,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
{ 20, 21, -12 }
}
- },
+ }
+},
+{ DSC_BPP(15), 16,
/* 15BPP/16BPC */
{ 273, 15, 2048, 19, 28, 27, 27, {
{ 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
@@ -570,59 +600,21 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 24, 25, -12 }
}
}
-}
+},
+{ /* sentinel */ }
};
-static int get_row_index_for_rc_params(u16 compressed_bpp)
-{
- switch (compressed_bpp) {
- case 6:
- return ROW_INDEX_6BPP;
- case 8:
- return ROW_INDEX_8BPP;
- case 10:
- return ROW_INDEX_10BPP;
- case 12:
- return ROW_INDEX_12BPP;
- case 15:
- return ROW_INDEX_15BPP;
- default:
- return -EINVAL;
- }
-}
-
-static int get_column_index_for_rc_params(u8 bits_per_component)
-{
- switch (bits_per_component) {
- case 8:
- return COLUMN_INDEX_8BPC;
- case 10:
- return COLUMN_INDEX_10BPC;
- case 12:
- return COLUMN_INDEX_12BPC;
- case 14:
- return COLUMN_INDEX_14BPC;
- case 16:
- return COLUMN_INDEX_16BPC;
- default:
- return -EINVAL;
- }
-}
-
-static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
+static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
u8 bits_per_component)
{
- int row_index, column_index;
-
- row_index = get_row_index_for_rc_params(compressed_bpp);
- if (row_index < 0)
- return NULL;
+ int i;
- column_index = get_column_index_for_rc_params(bits_per_component);
- if (column_index < 0)
- return NULL;
+ for (i = 0; rc_parameters[i].bpp; i++)
+ if (rc_parameters[i].bpp == dsc_bpp &&
+ rc_parameters[i].bpc == bits_per_component)
+ return &rc_parameters[i].params;
- return &rc_parameters[row_index][column_index];
+ return NULL;
}
/**
@@ -636,11 +628,7 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
const struct rc_parameters *rc_params;
int i;
- /* fractional BPP is not supported */
- if (vdsc_cfg->bits_per_pixel & 0xf)
- return -EINVAL;
-
- rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
+ rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
vdsc_cfg->bits_per_component);
if (!rc_params)
return -EINVAL;
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH 05/10] drm/display/dsc: use flat array for rc_parameters lookup
@ 2023-02-28 11:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
Next commits are going to add support for additional RC parameter lookup
tables. These tables are going to use different bpp/bpc combinations,
thus it makes little sense to keep the 2d array for RC parameters.
Switch to using the flat array.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 188 +++++++++++------------
1 file changed, 88 insertions(+), 100 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index deaa84722bd4..a6d11f474656 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -307,24 +307,6 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
}
EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
-enum ROW_INDEX_BPP {
- ROW_INDEX_6BPP = 0,
- ROW_INDEX_8BPP,
- ROW_INDEX_10BPP,
- ROW_INDEX_12BPP,
- ROW_INDEX_15BPP,
- MAX_ROW_INDEX
-};
-
-enum COLUMN_INDEX_BPC {
- COLUMN_INDEX_8BPC = 0,
- COLUMN_INDEX_10BPC,
- COLUMN_INDEX_12BPC,
- COLUMN_INDEX_14BPC,
- COLUMN_INDEX_16BPC,
- MAX_COLUMN_INDEX
-};
-
struct rc_parameters {
u16 initial_xmit_delay;
u8 first_line_bpg_offset;
@@ -336,12 +318,20 @@ struct rc_parameters {
struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
};
+struct rc_parameters_data {
+ u8 bpp;
+ u8 bpc;
+ struct rc_parameters params;
+};
+
+#define DSC_BPP(bpp) ((bpp) << 4)
+
/*
* Selected Rate Control Related Parameter Recommended Values
* from DSC_v1.11 spec & C Model release: DSC_model_20161212
*/
-static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
-{
+static const struct rc_parameters_data rc_parameters[] = {
+{ DSC_BPP(6), 8,
/* 6BPP/8BPC */
{ 768, 15, 6144, 3, 13, 11, 11, {
{ 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
@@ -349,7 +339,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
{ 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
}
- },
+ }
+},
+{ DSC_BPP(6), 10,
/* 6BPP/10BPC */
{ 768, 15, 6144, 7, 17, 15, 15, {
{ 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
@@ -358,7 +350,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
{ 17, 18, -12 }
}
- },
+ }
+},
+{ DSC_BPP(6), 12,
/* 6BPP/12BPC */
{ 768, 15, 6144, 11, 21, 19, 19, {
{ 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
@@ -367,7 +361,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
{ 21, 22, -12 }
}
- },
+ }
+},
+{ DSC_BPP(6), 14,
/* 6BPP/14BPC */
{ 768, 15, 6144, 15, 25, 23, 23, {
{ 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
@@ -376,7 +372,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
{ 25, 26, -12 }
}
- },
+ }
+},
+{ DSC_BPP(6), 16,
/* 6BPP/16BPC */
{ 768, 15, 6144, 19, 29, 27, 27, {
{ 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
@@ -385,9 +383,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
{ 29, 30, -12 }
}
- },
+ }
},
-{
+{ DSC_BPP(8), 8,
/* 8BPP/8BPC */
{ 512, 12, 6144, 3, 12, 11, 11, {
{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
@@ -395,7 +393,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
{ 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
}
- },
+ }
+},
+{ DSC_BPP(8), 10,
/* 8BPP/10BPC */
{ 512, 12, 6144, 7, 16, 15, 15, {
/*
@@ -407,7 +407,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
}
- },
+ }
+},
+{ DSC_BPP(8), 12,
/* 8BPP/12BPC */
{ 512, 12, 6144, 11, 20, 19, 19, {
{ 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
@@ -416,7 +418,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
{ 21, 23, -12 }
}
- },
+ }
+},
+{ DSC_BPP(8), 14,
/* 8BPP/14BPC */
{ 512, 12, 6144, 15, 24, 23, 23, {
{ 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
@@ -425,7 +429,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
{ 24, 25, -12 }
}
- },
+ }
+},
+{ DSC_BPP(8), 16,
/* 8BPP/16BPC */
{ 512, 12, 6144, 19, 28, 27, 27, {
{ 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
@@ -434,9 +440,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
{ 28, 29, -12 }
}
- },
+ }
},
-{
+{ DSC_BPP(10), 8,
/* 10BPP/8BPC */
{ 410, 15, 5632, 3, 12, 11, 11, {
{ 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
@@ -444,7 +450,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
{ 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
}
- },
+ }
+},
+{ DSC_BPP(10), 10,
/* 10BPP/10BPC */
{ 410, 15, 5632, 7, 16, 15, 15, {
{ 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
@@ -452,7 +460,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
{ 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
}
- },
+ }
+},
+{ DSC_BPP(10), 12,
/* 10BPP/12BPC */
{ 410, 15, 5632, 11, 20, 19, 19, {
{ 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
@@ -461,7 +471,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
{ 19, 20, -12 }
}
- },
+ }
+},
+{ DSC_BPP(10), 14,
/* 10BPP/14BPC */
{ 410, 15, 5632, 15, 24, 23, 23, {
{ 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
@@ -470,7 +482,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
{ 23, 24, -12 }
}
- },
+ }
+},
+{ DSC_BPP(10), 16,
/* 10BPP/16BPC */
{ 410, 15, 5632, 19, 28, 27, 27, {
{ 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
@@ -479,9 +493,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
{ 27, 28, -12 }
}
- },
+ }
},
-{
+{ DSC_BPP(12), 8,
/* 12BPP/8BPC */
{ 341, 15, 2048, 3, 12, 11, 11, {
{ 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
@@ -489,7 +503,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
{ 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
}
- },
+ }
+},
+{ DSC_BPP(12), 10,
/* 12BPP/10BPC */
{ 341, 15, 2048, 7, 16, 15, 15, {
{ 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
@@ -497,7 +513,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
}
- },
+ }
+},
+{ DSC_BPP(12), 12,
/* 12BPP/12BPC */
{ 341, 15, 2048, 11, 20, 19, 19, {
{ 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
@@ -506,7 +524,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
{ 21, 23, -12 }
}
- },
+ }
+},
+{ DSC_BPP(12), 14,
/* 12BPP/14BPC */
{ 341, 15, 2048, 15, 24, 23, 23, {
{ 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
@@ -515,7 +535,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
{ 22, 23, -12 }
}
- },
+ }
+},
+{ DSC_BPP(12), 16,
/* 12BPP/16BPC */
{ 341, 15, 2048, 19, 28, 27, 27, {
{ 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
@@ -524,9 +546,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
{ 26, 27, -12 }
}
- },
+ }
},
-{
+{ DSC_BPP(15), 8,
/* 15BPP/8BPC */
{ 273, 15, 2048, 3, 12, 11, 11, {
{ 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
@@ -534,7 +556,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
{ 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
}
- },
+ }
+},
+{ DSC_BPP(15), 10,
/* 15BPP/10BPC */
{ 273, 15, 2048, 7, 16, 15, 15, {
{ 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
@@ -542,7 +566,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
{ 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
}
- },
+ }
+},
+{ DSC_BPP(15), 12,
/* 15BPP/12BPC */
{ 273, 15, 2048, 11, 20, 19, 19, {
{ 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
@@ -551,7 +577,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
{ 16, 17, -12 }
}
- },
+ }
+},
+{ DSC_BPP(15), 14,
/* 15BPP/14BPC */
{ 273, 15, 2048, 15, 24, 23, 23, {
{ 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
@@ -560,7 +588,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
{ 20, 21, -12 }
}
- },
+ }
+},
+{ DSC_BPP(15), 16,
/* 15BPP/16BPC */
{ 273, 15, 2048, 19, 28, 27, 27, {
{ 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
@@ -570,59 +600,21 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 24, 25, -12 }
}
}
-}
+},
+{ /* sentinel */ }
};
-static int get_row_index_for_rc_params(u16 compressed_bpp)
-{
- switch (compressed_bpp) {
- case 6:
- return ROW_INDEX_6BPP;
- case 8:
- return ROW_INDEX_8BPP;
- case 10:
- return ROW_INDEX_10BPP;
- case 12:
- return ROW_INDEX_12BPP;
- case 15:
- return ROW_INDEX_15BPP;
- default:
- return -EINVAL;
- }
-}
-
-static int get_column_index_for_rc_params(u8 bits_per_component)
-{
- switch (bits_per_component) {
- case 8:
- return COLUMN_INDEX_8BPC;
- case 10:
- return COLUMN_INDEX_10BPC;
- case 12:
- return COLUMN_INDEX_12BPC;
- case 14:
- return COLUMN_INDEX_14BPC;
- case 16:
- return COLUMN_INDEX_16BPC;
- default:
- return -EINVAL;
- }
-}
-
-static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
+static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
u8 bits_per_component)
{
- int row_index, column_index;
-
- row_index = get_row_index_for_rc_params(compressed_bpp);
- if (row_index < 0)
- return NULL;
+ int i;
- column_index = get_column_index_for_rc_params(bits_per_component);
- if (column_index < 0)
- return NULL;
+ for (i = 0; rc_parameters[i].bpp; i++)
+ if (rc_parameters[i].bpp == dsc_bpp &&
+ rc_parameters[i].bpc == bits_per_component)
+ return &rc_parameters[i].params;
- return &rc_parameters[row_index][column_index];
+ return NULL;
}
/**
@@ -636,11 +628,7 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
const struct rc_parameters *rc_params;
int i;
- /* fractional BPP is not supported */
- if (vdsc_cfg->bits_per_pixel & 0xf)
- return -EINVAL;
-
- rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
+ rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
vdsc_cfg->bits_per_component);
if (!rc_params)
return -EINVAL;
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 06/10] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
2023-02-28 11:33 ` Dmitry Baryshkov
(?)
@ 2023-02-28 11:33 ` Dmitry Baryshkov
-1 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
The array of rc_parameters contains a mixture of parameters from DSC 1.1
and DSC 1.2 standards. Split these tow configuration arrays in
preparation to adding more configuration data.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 127 ++++++++++++++++++----
drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
include/drm/display/drm_dsc_helper.h | 7 +-
3 files changed, 119 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index a6d11f474656..51794b40526a 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -326,11 +326,81 @@ struct rc_parameters_data {
#define DSC_BPP(bpp) ((bpp) << 4)
+static const struct rc_parameters_data rc_parameters_pre_scr[] = {
+{ DSC_BPP(8), 8,
+ /* 8BPP/8BPC */
+ { 512, 12, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
+ { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 10,
+ /* 8BPP/10BPC */
+ { 512, 12, 6144, 7, 16, 15, 15, {
+ /*
+ * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
+ * VESA DSC 1.1 Table E-5 sets it to 4.
+ */
+ { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 12,
+ /* 8BPP/12BPC */
+ { 512, 12, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+},
+{ DSC_BPP(12), 8,
+ /* 12BPP/8BPC */
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
+ { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+},
+{ DSC_BPP(12), 10,
+ /* 12BPP/10BPC */
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+},
+{ DSC_BPP(12), 12,
+ /* 12BPP/12BPC */
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+},
+{ /* sentinel */ }
+};
+
/*
* Selected Rate Control Related Parameter Recommended Values
* from DSC_v1.11 spec & C Model release: DSC_model_20161212
*/
-static const struct rc_parameters_data rc_parameters[] = {
+static const struct rc_parameters_data rc_parameters_1_2_444[] = {
{ DSC_BPP(6), 8,
/* 6BPP/8BPC */
{ 768, 15, 6144, 3, 13, 11, 11, {
@@ -390,22 +460,18 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 512, 12, 6144, 3, 12, 11, 11, {
{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
- { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
+ { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
}
}
},
{ DSC_BPP(8), 10,
/* 8BPP/10BPC */
{ 512, 12, 6144, 7, 16, 15, 15, {
- /*
- * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
- * VESA DSC 1.1 Table E-5 sets it to 4.
- */
- { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
+ { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
}
}
},
@@ -414,9 +480,9 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 512, 12, 6144, 11, 20, 19, 19, {
{ 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
+ { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
+ { 20, 21, -12 }
}
}
},
@@ -500,8 +566,8 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 341, 15, 2048, 3, 12, 11, 11, {
{ 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
- { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
+ { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
}
}
},
@@ -510,8 +576,8 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 341, 15, 2048, 7, 16, 15, 15, {
{ 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
{ 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
+ { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
}
}
},
@@ -520,9 +586,9 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 341, 15, 2048, 11, 20, 19, 19, {
{ 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
{ 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
+ { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
+ { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
+ { 18, 19, -12 }
}
}
},
@@ -604,7 +670,8 @@ static const struct rc_parameters_data rc_parameters[] = {
{ /* sentinel */ }
};
-static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
+static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
+ u16 dsc_bpp,
u8 bits_per_component)
{
int i;
@@ -622,13 +689,27 @@ static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
* accordance with the DSC 1.1 or 1.2 specification and DSC C Model
*
* @vdsc_cfg: DSC Configuration data partially filled by driver
+ * @kind: operating mode and standard to follow
*/
-int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind)
{
+ const struct rc_parameters_data *data;
const struct rc_parameters *rc_params;
int i;
- rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
+ switch (kind) {
+ case DRM_DSC_1_2_444:
+ data = rc_parameters_1_2_444;
+ break;
+ case DRM_DSC_1_1_PRE_SCR:
+ data = rc_parameters_pre_scr;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ rc_params = get_rc_params(data,
+ vdsc_cfg->bits_per_pixel,
vdsc_cfg->bits_per_component);
if (!rc_params)
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 1ee8d13c9d64..4d220d24fa73 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -156,7 +156,15 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
if (DISPLAY_VER(dev_priv) >= 13) {
calculate_rc_params(vdsc_cfg);
} else {
- ret = drm_dsc_setup_rc_params(vdsc_cfg);
+ if ((compressed_bpp == 8 ||
+ compressed_bpp == 12) &&
+ (vdsc_cfg->bits_per_pixel == 8 ||
+ vdsc_cfg->bits_per_pixel == 10 ||
+ vdsc_cfg->bits_per_pixel == 12))
+ ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
+ else
+ ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
+
if (ret)
return ret;
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 1681791f65a5..c634bb2935d3 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -10,12 +10,17 @@
#include <drm/display/drm_dsc.h>
+enum drm_dsc_params_kind {
+ DRM_DSC_1_2_444,
+ DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
+};
+
void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
-int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
#endif /* _DRM_DSC_HELPER_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 06/10] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
@ 2023-02-28 11:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
The array of rc_parameters contains a mixture of parameters from DSC 1.1
and DSC 1.2 standards. Split these tow configuration arrays in
preparation to adding more configuration data.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 127 ++++++++++++++++++----
drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
include/drm/display/drm_dsc_helper.h | 7 +-
3 files changed, 119 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index a6d11f474656..51794b40526a 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -326,11 +326,81 @@ struct rc_parameters_data {
#define DSC_BPP(bpp) ((bpp) << 4)
+static const struct rc_parameters_data rc_parameters_pre_scr[] = {
+{ DSC_BPP(8), 8,
+ /* 8BPP/8BPC */
+ { 512, 12, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
+ { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 10,
+ /* 8BPP/10BPC */
+ { 512, 12, 6144, 7, 16, 15, 15, {
+ /*
+ * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
+ * VESA DSC 1.1 Table E-5 sets it to 4.
+ */
+ { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 12,
+ /* 8BPP/12BPC */
+ { 512, 12, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+},
+{ DSC_BPP(12), 8,
+ /* 12BPP/8BPC */
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
+ { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+},
+{ DSC_BPP(12), 10,
+ /* 12BPP/10BPC */
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+},
+{ DSC_BPP(12), 12,
+ /* 12BPP/12BPC */
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+},
+{ /* sentinel */ }
+};
+
/*
* Selected Rate Control Related Parameter Recommended Values
* from DSC_v1.11 spec & C Model release: DSC_model_20161212
*/
-static const struct rc_parameters_data rc_parameters[] = {
+static const struct rc_parameters_data rc_parameters_1_2_444[] = {
{ DSC_BPP(6), 8,
/* 6BPP/8BPC */
{ 768, 15, 6144, 3, 13, 11, 11, {
@@ -390,22 +460,18 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 512, 12, 6144, 3, 12, 11, 11, {
{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
- { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
+ { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
}
}
},
{ DSC_BPP(8), 10,
/* 8BPP/10BPC */
{ 512, 12, 6144, 7, 16, 15, 15, {
- /*
- * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
- * VESA DSC 1.1 Table E-5 sets it to 4.
- */
- { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
+ { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
}
}
},
@@ -414,9 +480,9 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 512, 12, 6144, 11, 20, 19, 19, {
{ 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
+ { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
+ { 20, 21, -12 }
}
}
},
@@ -500,8 +566,8 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 341, 15, 2048, 3, 12, 11, 11, {
{ 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
- { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
+ { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
}
}
},
@@ -510,8 +576,8 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 341, 15, 2048, 7, 16, 15, 15, {
{ 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
{ 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
+ { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
}
}
},
@@ -520,9 +586,9 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 341, 15, 2048, 11, 20, 19, 19, {
{ 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
{ 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
+ { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
+ { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
+ { 18, 19, -12 }
}
}
},
@@ -604,7 +670,8 @@ static const struct rc_parameters_data rc_parameters[] = {
{ /* sentinel */ }
};
-static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
+static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
+ u16 dsc_bpp,
u8 bits_per_component)
{
int i;
@@ -622,13 +689,27 @@ static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
* accordance with the DSC 1.1 or 1.2 specification and DSC C Model
*
* @vdsc_cfg: DSC Configuration data partially filled by driver
+ * @kind: operating mode and standard to follow
*/
-int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind)
{
+ const struct rc_parameters_data *data;
const struct rc_parameters *rc_params;
int i;
- rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
+ switch (kind) {
+ case DRM_DSC_1_2_444:
+ data = rc_parameters_1_2_444;
+ break;
+ case DRM_DSC_1_1_PRE_SCR:
+ data = rc_parameters_pre_scr;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ rc_params = get_rc_params(data,
+ vdsc_cfg->bits_per_pixel,
vdsc_cfg->bits_per_component);
if (!rc_params)
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 1ee8d13c9d64..4d220d24fa73 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -156,7 +156,15 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
if (DISPLAY_VER(dev_priv) >= 13) {
calculate_rc_params(vdsc_cfg);
} else {
- ret = drm_dsc_setup_rc_params(vdsc_cfg);
+ if ((compressed_bpp == 8 ||
+ compressed_bpp == 12) &&
+ (vdsc_cfg->bits_per_pixel == 8 ||
+ vdsc_cfg->bits_per_pixel == 10 ||
+ vdsc_cfg->bits_per_pixel == 12))
+ ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
+ else
+ ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
+
if (ret)
return ret;
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 1681791f65a5..c634bb2935d3 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -10,12 +10,17 @@
#include <drm/display/drm_dsc.h>
+enum drm_dsc_params_kind {
+ DRM_DSC_1_2_444,
+ DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
+};
+
void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
-int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
#endif /* _DRM_DSC_HELPER_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH 06/10] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
@ 2023-02-28 11:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
The array of rc_parameters contains a mixture of parameters from DSC 1.1
and DSC 1.2 standards. Split these tow configuration arrays in
preparation to adding more configuration data.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 127 ++++++++++++++++++----
drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
include/drm/display/drm_dsc_helper.h | 7 +-
3 files changed, 119 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index a6d11f474656..51794b40526a 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -326,11 +326,81 @@ struct rc_parameters_data {
#define DSC_BPP(bpp) ((bpp) << 4)
+static const struct rc_parameters_data rc_parameters_pre_scr[] = {
+{ DSC_BPP(8), 8,
+ /* 8BPP/8BPC */
+ { 512, 12, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
+ { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 10,
+ /* 8BPP/10BPC */
+ { 512, 12, 6144, 7, 16, 15, 15, {
+ /*
+ * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
+ * VESA DSC 1.1 Table E-5 sets it to 4.
+ */
+ { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 12,
+ /* 8BPP/12BPC */
+ { 512, 12, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+},
+{ DSC_BPP(12), 8,
+ /* 12BPP/8BPC */
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
+ { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+},
+{ DSC_BPP(12), 10,
+ /* 12BPP/10BPC */
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+},
+{ DSC_BPP(12), 12,
+ /* 12BPP/12BPC */
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+},
+{ /* sentinel */ }
+};
+
/*
* Selected Rate Control Related Parameter Recommended Values
* from DSC_v1.11 spec & C Model release: DSC_model_20161212
*/
-static const struct rc_parameters_data rc_parameters[] = {
+static const struct rc_parameters_data rc_parameters_1_2_444[] = {
{ DSC_BPP(6), 8,
/* 6BPP/8BPC */
{ 768, 15, 6144, 3, 13, 11, 11, {
@@ -390,22 +460,18 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 512, 12, 6144, 3, 12, 11, 11, {
{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
- { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
+ { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
}
}
},
{ DSC_BPP(8), 10,
/* 8BPP/10BPC */
{ 512, 12, 6144, 7, 16, 15, 15, {
- /*
- * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
- * VESA DSC 1.1 Table E-5 sets it to 4.
- */
- { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
+ { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
}
}
},
@@ -414,9 +480,9 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 512, 12, 6144, 11, 20, 19, 19, {
{ 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
+ { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
+ { 20, 21, -12 }
}
}
},
@@ -500,8 +566,8 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 341, 15, 2048, 3, 12, 11, 11, {
{ 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
- { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
+ { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
}
}
},
@@ -510,8 +576,8 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 341, 15, 2048, 7, 16, 15, 15, {
{ 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
{ 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
+ { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
}
}
},
@@ -520,9 +586,9 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 341, 15, 2048, 11, 20, 19, 19, {
{ 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
{ 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
+ { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
+ { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
+ { 18, 19, -12 }
}
}
},
@@ -604,7 +670,8 @@ static const struct rc_parameters_data rc_parameters[] = {
{ /* sentinel */ }
};
-static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
+static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
+ u16 dsc_bpp,
u8 bits_per_component)
{
int i;
@@ -622,13 +689,27 @@ static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
* accordance with the DSC 1.1 or 1.2 specification and DSC C Model
*
* @vdsc_cfg: DSC Configuration data partially filled by driver
+ * @kind: operating mode and standard to follow
*/
-int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind)
{
+ const struct rc_parameters_data *data;
const struct rc_parameters *rc_params;
int i;
- rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
+ switch (kind) {
+ case DRM_DSC_1_2_444:
+ data = rc_parameters_1_2_444;
+ break;
+ case DRM_DSC_1_1_PRE_SCR:
+ data = rc_parameters_pre_scr;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ rc_params = get_rc_params(data,
+ vdsc_cfg->bits_per_pixel,
vdsc_cfg->bits_per_component);
if (!rc_params)
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 1ee8d13c9d64..4d220d24fa73 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -156,7 +156,15 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
if (DISPLAY_VER(dev_priv) >= 13) {
calculate_rc_params(vdsc_cfg);
} else {
- ret = drm_dsc_setup_rc_params(vdsc_cfg);
+ if ((compressed_bpp == 8 ||
+ compressed_bpp == 12) &&
+ (vdsc_cfg->bits_per_pixel == 8 ||
+ vdsc_cfg->bits_per_pixel == 10 ||
+ vdsc_cfg->bits_per_pixel == 12))
+ ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
+ else
+ ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
+
if (ret)
return ret;
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 1681791f65a5..c634bb2935d3 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -10,12 +10,17 @@
#include <drm/display/drm_dsc.h>
+enum drm_dsc_params_kind {
+ DRM_DSC_1_2_444,
+ DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
+};
+
void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
-int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
#endif /* _DRM_DSC_HELPER_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 07/10] drm/display/dsc: include the rest of pre-SCR parameters
2023-02-28 11:33 ` Dmitry Baryshkov
(?)
@ 2023-02-28 11:33 ` Dmitry Baryshkov
-1 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
DSC model contains pre-SCR RC parameters for other bpp/bpc combinations,
include them here for completeness.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 72 ++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index 51794b40526a..1612536014ea 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -327,6 +327,16 @@ struct rc_parameters_data {
#define DSC_BPP(bpp) ((bpp) << 4)
static const struct rc_parameters_data rc_parameters_pre_scr[] = {
+{ DSC_BPP(6), 8,
+ /* 6BPP/8BPC */
+ { 683, 15, 6144, 3, 13, 11, 11, {
+ { 0, 2, 0 }, { 1, 4, -2 }, { 3, 6, -2 }, { 4, 6, -4 },
+ { 5, 7, -6 }, { 5, 7, -6 }, { 6, 7, -6 }, { 6, 8, -8 },
+ { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 }, { 10, 12, -12 },
+ { 10, 13, -12 }, { 12, 14, -12 }, { 15, 15, -12 }
+ }
+ }
+},
{ DSC_BPP(8), 8,
/* 8BPP/8BPC */
{ 512, 12, 6144, 3, 12, 11, 11, {
@@ -362,6 +372,37 @@ static const struct rc_parameters_data rc_parameters_pre_scr[] = {
}
}
},
+{ DSC_BPP(10), 8,
+ /* 10BPP/8BPC */
+ { 410, 12, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 11, -10 },
+ { 5, 12, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+},
+{ DSC_BPP(10), 10,
+ /* 10BPP/10BPC */
+ { 410, 12, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 15, -10 },
+ { 9, 16, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+},
+{ DSC_BPP(10), 12,
+ /* 10BPP/12BPC */
+ { 410, 12, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 19, -10 }, { 13, 20, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+},
{ DSC_BPP(12), 8,
/* 12BPP/8BPC */
{ 341, 15, 2048, 3, 12, 11, 11, {
@@ -393,6 +434,37 @@ static const struct rc_parameters_data rc_parameters_pre_scr[] = {
}
}
},
+{ DSC_BPP(15), 8,
+ /* 15BPP/8BPC */
+ { 273, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 4, -2 }, { 2, 4, -4 },
+ { 3, 4, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 5, 7, -10 },
+ { 5, 8, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+},
+{ DSC_BPP(15), 10,
+ /* 15BPP/10BPC */
+ { 273, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 8, -2 }, { 6, 8, -4 },
+ { 7, 8, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 },
+ { 9, 12, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+},
+{ DSC_BPP(15), 12,
+ /* 15BPP/12BPC */
+ { 273, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 12, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 16, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+},
{ /* sentinel */ }
};
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 07/10] drm/display/dsc: include the rest of pre-SCR parameters
@ 2023-02-28 11:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
DSC model contains pre-SCR RC parameters for other bpp/bpc combinations,
include them here for completeness.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 72 ++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index 51794b40526a..1612536014ea 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -327,6 +327,16 @@ struct rc_parameters_data {
#define DSC_BPP(bpp) ((bpp) << 4)
static const struct rc_parameters_data rc_parameters_pre_scr[] = {
+{ DSC_BPP(6), 8,
+ /* 6BPP/8BPC */
+ { 683, 15, 6144, 3, 13, 11, 11, {
+ { 0, 2, 0 }, { 1, 4, -2 }, { 3, 6, -2 }, { 4, 6, -4 },
+ { 5, 7, -6 }, { 5, 7, -6 }, { 6, 7, -6 }, { 6, 8, -8 },
+ { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 }, { 10, 12, -12 },
+ { 10, 13, -12 }, { 12, 14, -12 }, { 15, 15, -12 }
+ }
+ }
+},
{ DSC_BPP(8), 8,
/* 8BPP/8BPC */
{ 512, 12, 6144, 3, 12, 11, 11, {
@@ -362,6 +372,37 @@ static const struct rc_parameters_data rc_parameters_pre_scr[] = {
}
}
},
+{ DSC_BPP(10), 8,
+ /* 10BPP/8BPC */
+ { 410, 12, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 11, -10 },
+ { 5, 12, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+},
+{ DSC_BPP(10), 10,
+ /* 10BPP/10BPC */
+ { 410, 12, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 15, -10 },
+ { 9, 16, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+},
+{ DSC_BPP(10), 12,
+ /* 10BPP/12BPC */
+ { 410, 12, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 19, -10 }, { 13, 20, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+},
{ DSC_BPP(12), 8,
/* 12BPP/8BPC */
{ 341, 15, 2048, 3, 12, 11, 11, {
@@ -393,6 +434,37 @@ static const struct rc_parameters_data rc_parameters_pre_scr[] = {
}
}
},
+{ DSC_BPP(15), 8,
+ /* 15BPP/8BPC */
+ { 273, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 4, -2 }, { 2, 4, -4 },
+ { 3, 4, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 5, 7, -10 },
+ { 5, 8, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+},
+{ DSC_BPP(15), 10,
+ /* 15BPP/10BPC */
+ { 273, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 8, -2 }, { 6, 8, -4 },
+ { 7, 8, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 },
+ { 9, 12, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+},
+{ DSC_BPP(15), 12,
+ /* 15BPP/12BPC */
+ { 273, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 12, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 16, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+},
{ /* sentinel */ }
};
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH 07/10] drm/display/dsc: include the rest of pre-SCR parameters
@ 2023-02-28 11:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
DSC model contains pre-SCR RC parameters for other bpp/bpc combinations,
include them here for completeness.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 72 ++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index 51794b40526a..1612536014ea 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -327,6 +327,16 @@ struct rc_parameters_data {
#define DSC_BPP(bpp) ((bpp) << 4)
static const struct rc_parameters_data rc_parameters_pre_scr[] = {
+{ DSC_BPP(6), 8,
+ /* 6BPP/8BPC */
+ { 683, 15, 6144, 3, 13, 11, 11, {
+ { 0, 2, 0 }, { 1, 4, -2 }, { 3, 6, -2 }, { 4, 6, -4 },
+ { 5, 7, -6 }, { 5, 7, -6 }, { 6, 7, -6 }, { 6, 8, -8 },
+ { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 }, { 10, 12, -12 },
+ { 10, 13, -12 }, { 12, 14, -12 }, { 15, 15, -12 }
+ }
+ }
+},
{ DSC_BPP(8), 8,
/* 8BPP/8BPC */
{ 512, 12, 6144, 3, 12, 11, 11, {
@@ -362,6 +372,37 @@ static const struct rc_parameters_data rc_parameters_pre_scr[] = {
}
}
},
+{ DSC_BPP(10), 8,
+ /* 10BPP/8BPC */
+ { 410, 12, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 11, -10 },
+ { 5, 12, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+},
+{ DSC_BPP(10), 10,
+ /* 10BPP/10BPC */
+ { 410, 12, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 15, -10 },
+ { 9, 16, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+},
+{ DSC_BPP(10), 12,
+ /* 10BPP/12BPC */
+ { 410, 12, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 19, -10 }, { 13, 20, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+},
{ DSC_BPP(12), 8,
/* 12BPP/8BPC */
{ 341, 15, 2048, 3, 12, 11, 11, {
@@ -393,6 +434,37 @@ static const struct rc_parameters_data rc_parameters_pre_scr[] = {
}
}
},
+{ DSC_BPP(15), 8,
+ /* 15BPP/8BPC */
+ { 273, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 4, -2 }, { 2, 4, -4 },
+ { 3, 4, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 5, 7, -10 },
+ { 5, 8, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+},
+{ DSC_BPP(15), 10,
+ /* 15BPP/10BPC */
+ { 273, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 8, -2 }, { 6, 8, -4 },
+ { 7, 8, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 },
+ { 9, 12, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+},
+{ DSC_BPP(15), 12,
+ /* 15BPP/12BPC */
+ { 273, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 12, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 16, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+},
{ /* sentinel */ }
};
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 08/10] drm/display/dsc: add YCbCr 4:2:2 and 4:2:0 RC parameters
2023-02-28 11:33 ` Dmitry Baryshkov
(?)
@ 2023-02-28 11:33 ` Dmitry Baryshkov
-1 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
Include RC parameters for YCbCr 4:2:2 and 4:2:0 configurations.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 438 +++++++++++++++++++++++
include/drm/display/drm_dsc_helper.h | 2 +
2 files changed, 440 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index 1612536014ea..d11ee8f1efa7 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -742,6 +742,438 @@ static const struct rc_parameters_data rc_parameters_1_2_444[] = {
{ /* sentinel */ }
};
+static const struct rc_parameters_data rc_parameters_1_2_422[] = {
+{ DSC_BPP(6), 8,
+ /* 12BPP/8BPC */
+ { 512, 15, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
+ { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 10,
+ /* 12BPP/10BPC */
+ { 512, 15, 6144, 7, 16, 15, 15, {
+ { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
+ { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 12,
+ /* 12BPP/12BPC */
+ { 512, 15, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
+ { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 14,
+ /* 12BPP/14BPC */
+ { 512, 15, 6144, 15, 24, 23, 23, {
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 16,
+ /* 12BPP/16BPC */
+ { 512, 15, 6144, 19, 28, 27, 27, {
+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
+ { 28, 29, -12 }
+ }
+ }
+},
+{ DSC_BPP(7), 8,
+ /* 14BPP/8BPC */
+ { 410, 15, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
+ }
+ }
+},
+{ DSC_BPP(7), 10,
+ /* 14BPP/10BPC */
+ { 410, 15, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
+ }
+ }
+},
+{ DSC_BPP(7), 12,
+ /* 14BPP/12BPC */
+ { 410, 15, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
+ { 19, 20, -12 }
+ }
+ }
+},
+{ DSC_BPP(7), 14,
+ /* 14BPP/14BPC */
+ { 410, 15, 5632, 15, 24, 23, 23, {
+ { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
+ { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
+ { 23, 24, -12 }
+ }
+ }
+},
+{ DSC_BPP(7), 16,
+ /* 14BPP/16BPC */
+ { 410, 15, 5632, 19, 28, 27, 27, {
+ { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
+ { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
+ { 27, 28, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 8,
+ /* 16BPP/8BPC */
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
+ { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 10,
+ /* 16BPP/10BPC */
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
+ { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 12,
+ /* 16BPP/12BPC */
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
+ { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
+ { 18, 19, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 14,
+ /* 16BPP/14BPC */
+ { 341, 15, 2048, 15, 24, 23, 23, {
+ { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
+ { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
+ { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
+ { 22, 23, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 16,
+ /* 16BPP/16BPC */
+ { 341, 15, 2048, 19, 28, 27, 27, {
+ { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
+ { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
+ { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
+ { 26, 27, -12 }
+ }
+ }
+},
+{ DSC_BPP(10), 8,
+ /* 20BPP/8BPC */
+ { 273, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
+ { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
+ { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
+ }
+ }
+},
+{ DSC_BPP(10), 10,
+ /* 20BPP/10BPC */
+ { 273, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
+ { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
+ { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+},
+{ DSC_BPP(10), 12,
+ /* 20BPP/12BPC */
+ { 273, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
+ { 16, 17, -12 }
+ }
+ }
+},
+{ DSC_BPP(10), 14,
+ /* 20BPP/14BPC */
+ { 273, 15, 2048, 15, 24, 23, 23, {
+ { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
+ { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
+ { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
+ { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+},
+{ DSC_BPP(10), 16,
+ /* 20BPP/16BPC */
+ { 273, 15, 2048, 19, 28, 27, 27, {
+ { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
+ { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
+ { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
+ { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+},
+{ /* sentinel */ }
+};
+
+static const struct rc_parameters_data rc_parameters_1_2_420[] = {
+{ DSC_BPP(4), 8,
+ /* 8BPP/8BPC */
+ { 512, 12, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
+ { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+},
+{ DSC_BPP(4), 10,
+ /* 8BPP/10BPC */
+ { 512, 12, 6144, 7, 16, 15, 15, {
+ { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
+ { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
+ }
+ }
+},
+{ DSC_BPP(4), 12,
+ /* 8BPP/12BPC */
+ { 512, 12, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
+ { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+},
+{ DSC_BPP(4), 14,
+ /* 8BPP/14BPC */
+ { 512, 12, 6144, 15, 24, 23, 23, {
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+},
+{ DSC_BPP(4), 16,
+ /* 8BPP/16BPC */
+ { 512, 12, 6144, 19, 28, 27, 27, {
+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
+ { 28, 29, -12 }
+ }
+ }
+},
+{ DSC_BPP(5), 8,
+ /* 10BPP/8BPC */
+ { 410, 15, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
+ }
+ }
+},
+{ DSC_BPP(5), 10,
+ /* 10BPP/10BPC */
+ { 410, 15, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
+ }
+ }
+},
+{ DSC_BPP(5), 12,
+ /* 10BPP/12BPC */
+ { 410, 15, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
+ { 19, 20, -12 }
+ }
+ }
+},
+{ DSC_BPP(5), 14,
+ /* 10BPP/14BPC */
+ { 410, 15, 5632, 15, 24, 23, 23, {
+ { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
+ { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
+ { 23, 24, -12 }
+ }
+ }
+},
+{ DSC_BPP(5), 16,
+ /* 10BPP/16BPC */
+ { 410, 15, 5632, 19, 28, 27, 27, {
+ { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
+ { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
+ { 27, 28, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 8,
+ /* 12BPP/8BPC */
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
+ { 5, 9, -12 }, { 7, 10, -12 }, { 10, 12, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 10,
+ /* 12BPP/10BPC */
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
+ { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 12,
+ /* 12BPP/12BPC */
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
+ { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
+ { 18, 19, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 14,
+ /* 12BPP/14BPC */
+ { 341, 15, 2048, 15, 24, 23, 23, {
+ { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
+ { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
+ { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
+ { 22, 23, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 16,
+ /* 12BPP/16BPC */
+ { 341, 15, 2048, 19, 28, 27, 27, {
+ { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
+ { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
+ { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
+ { 26, 27, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 8,
+ /* 16BPP/8BPC */
+ { 256, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
+ { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
+ { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 10,
+ /* 16BPP/10BPC */
+ { 256, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
+ { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
+ { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 12,
+ /* 16BPP/12BPC */
+ { 256, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
+ { 16, 17, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 14,
+ /* 16BPP/14BPC */
+ { 256, 15, 2048, 15, 24, 23, 23, {
+ { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
+ { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
+ { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
+ { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 16,
+ /* 16BPP/16BPC */
+ { 256, 15, 2048, 19, 28, 27, 27, {
+ { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
+ { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
+ { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
+ { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+},
+{ /* sentinel */ }
+};
+
static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
u16 dsc_bpp,
u8 bits_per_component)
@@ -776,6 +1208,12 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params
case DRM_DSC_1_1_PRE_SCR:
data = rc_parameters_pre_scr;
break;
+ case DRM_DSC_1_2_422:
+ data = rc_parameters_1_2_422;
+ break;
+ case DRM_DSC_1_2_420:
+ data = rc_parameters_1_2_420;
+ break;
default:
return -EINVAL;
}
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index c634bb2935d3..0bb0c3afd740 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -13,6 +13,8 @@
enum drm_dsc_params_kind {
DRM_DSC_1_2_444,
DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
+ DRM_DSC_1_2_422,
+ DRM_DSC_1_2_420,
};
void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 08/10] drm/display/dsc: add YCbCr 4:2:2 and 4:2:0 RC parameters
@ 2023-02-28 11:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
Include RC parameters for YCbCr 4:2:2 and 4:2:0 configurations.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 438 +++++++++++++++++++++++
include/drm/display/drm_dsc_helper.h | 2 +
2 files changed, 440 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index 1612536014ea..d11ee8f1efa7 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -742,6 +742,438 @@ static const struct rc_parameters_data rc_parameters_1_2_444[] = {
{ /* sentinel */ }
};
+static const struct rc_parameters_data rc_parameters_1_2_422[] = {
+{ DSC_BPP(6), 8,
+ /* 12BPP/8BPC */
+ { 512, 15, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
+ { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 10,
+ /* 12BPP/10BPC */
+ { 512, 15, 6144, 7, 16, 15, 15, {
+ { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
+ { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 12,
+ /* 12BPP/12BPC */
+ { 512, 15, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
+ { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 14,
+ /* 12BPP/14BPC */
+ { 512, 15, 6144, 15, 24, 23, 23, {
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 16,
+ /* 12BPP/16BPC */
+ { 512, 15, 6144, 19, 28, 27, 27, {
+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
+ { 28, 29, -12 }
+ }
+ }
+},
+{ DSC_BPP(7), 8,
+ /* 14BPP/8BPC */
+ { 410, 15, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
+ }
+ }
+},
+{ DSC_BPP(7), 10,
+ /* 14BPP/10BPC */
+ { 410, 15, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
+ }
+ }
+},
+{ DSC_BPP(7), 12,
+ /* 14BPP/12BPC */
+ { 410, 15, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
+ { 19, 20, -12 }
+ }
+ }
+},
+{ DSC_BPP(7), 14,
+ /* 14BPP/14BPC */
+ { 410, 15, 5632, 15, 24, 23, 23, {
+ { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
+ { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
+ { 23, 24, -12 }
+ }
+ }
+},
+{ DSC_BPP(7), 16,
+ /* 14BPP/16BPC */
+ { 410, 15, 5632, 19, 28, 27, 27, {
+ { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
+ { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
+ { 27, 28, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 8,
+ /* 16BPP/8BPC */
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
+ { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 10,
+ /* 16BPP/10BPC */
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
+ { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 12,
+ /* 16BPP/12BPC */
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
+ { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
+ { 18, 19, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 14,
+ /* 16BPP/14BPC */
+ { 341, 15, 2048, 15, 24, 23, 23, {
+ { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
+ { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
+ { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
+ { 22, 23, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 16,
+ /* 16BPP/16BPC */
+ { 341, 15, 2048, 19, 28, 27, 27, {
+ { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
+ { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
+ { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
+ { 26, 27, -12 }
+ }
+ }
+},
+{ DSC_BPP(10), 8,
+ /* 20BPP/8BPC */
+ { 273, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
+ { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
+ { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
+ }
+ }
+},
+{ DSC_BPP(10), 10,
+ /* 20BPP/10BPC */
+ { 273, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
+ { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
+ { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+},
+{ DSC_BPP(10), 12,
+ /* 20BPP/12BPC */
+ { 273, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
+ { 16, 17, -12 }
+ }
+ }
+},
+{ DSC_BPP(10), 14,
+ /* 20BPP/14BPC */
+ { 273, 15, 2048, 15, 24, 23, 23, {
+ { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
+ { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
+ { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
+ { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+},
+{ DSC_BPP(10), 16,
+ /* 20BPP/16BPC */
+ { 273, 15, 2048, 19, 28, 27, 27, {
+ { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
+ { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
+ { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
+ { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+},
+{ /* sentinel */ }
+};
+
+static const struct rc_parameters_data rc_parameters_1_2_420[] = {
+{ DSC_BPP(4), 8,
+ /* 8BPP/8BPC */
+ { 512, 12, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
+ { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+},
+{ DSC_BPP(4), 10,
+ /* 8BPP/10BPC */
+ { 512, 12, 6144, 7, 16, 15, 15, {
+ { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
+ { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
+ }
+ }
+},
+{ DSC_BPP(4), 12,
+ /* 8BPP/12BPC */
+ { 512, 12, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
+ { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+},
+{ DSC_BPP(4), 14,
+ /* 8BPP/14BPC */
+ { 512, 12, 6144, 15, 24, 23, 23, {
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+},
+{ DSC_BPP(4), 16,
+ /* 8BPP/16BPC */
+ { 512, 12, 6144, 19, 28, 27, 27, {
+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
+ { 28, 29, -12 }
+ }
+ }
+},
+{ DSC_BPP(5), 8,
+ /* 10BPP/8BPC */
+ { 410, 15, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
+ }
+ }
+},
+{ DSC_BPP(5), 10,
+ /* 10BPP/10BPC */
+ { 410, 15, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
+ }
+ }
+},
+{ DSC_BPP(5), 12,
+ /* 10BPP/12BPC */
+ { 410, 15, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
+ { 19, 20, -12 }
+ }
+ }
+},
+{ DSC_BPP(5), 14,
+ /* 10BPP/14BPC */
+ { 410, 15, 5632, 15, 24, 23, 23, {
+ { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
+ { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
+ { 23, 24, -12 }
+ }
+ }
+},
+{ DSC_BPP(5), 16,
+ /* 10BPP/16BPC */
+ { 410, 15, 5632, 19, 28, 27, 27, {
+ { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
+ { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
+ { 27, 28, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 8,
+ /* 12BPP/8BPC */
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
+ { 5, 9, -12 }, { 7, 10, -12 }, { 10, 12, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 10,
+ /* 12BPP/10BPC */
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
+ { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 12,
+ /* 12BPP/12BPC */
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
+ { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
+ { 18, 19, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 14,
+ /* 12BPP/14BPC */
+ { 341, 15, 2048, 15, 24, 23, 23, {
+ { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
+ { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
+ { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
+ { 22, 23, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 16,
+ /* 12BPP/16BPC */
+ { 341, 15, 2048, 19, 28, 27, 27, {
+ { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
+ { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
+ { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
+ { 26, 27, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 8,
+ /* 16BPP/8BPC */
+ { 256, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
+ { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
+ { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 10,
+ /* 16BPP/10BPC */
+ { 256, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
+ { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
+ { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 12,
+ /* 16BPP/12BPC */
+ { 256, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
+ { 16, 17, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 14,
+ /* 16BPP/14BPC */
+ { 256, 15, 2048, 15, 24, 23, 23, {
+ { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
+ { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
+ { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
+ { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 16,
+ /* 16BPP/16BPC */
+ { 256, 15, 2048, 19, 28, 27, 27, {
+ { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
+ { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
+ { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
+ { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+},
+{ /* sentinel */ }
+};
+
static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
u16 dsc_bpp,
u8 bits_per_component)
@@ -776,6 +1208,12 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params
case DRM_DSC_1_1_PRE_SCR:
data = rc_parameters_pre_scr;
break;
+ case DRM_DSC_1_2_422:
+ data = rc_parameters_1_2_422;
+ break;
+ case DRM_DSC_1_2_420:
+ data = rc_parameters_1_2_420;
+ break;
default:
return -EINVAL;
}
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index c634bb2935d3..0bb0c3afd740 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -13,6 +13,8 @@
enum drm_dsc_params_kind {
DRM_DSC_1_2_444,
DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
+ DRM_DSC_1_2_422,
+ DRM_DSC_1_2_420,
};
void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH 08/10] drm/display/dsc: add YCbCr 4:2:2 and 4:2:0 RC parameters
@ 2023-02-28 11:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
Include RC parameters for YCbCr 4:2:2 and 4:2:0 configurations.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 438 +++++++++++++++++++++++
include/drm/display/drm_dsc_helper.h | 2 +
2 files changed, 440 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index 1612536014ea..d11ee8f1efa7 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -742,6 +742,438 @@ static const struct rc_parameters_data rc_parameters_1_2_444[] = {
{ /* sentinel */ }
};
+static const struct rc_parameters_data rc_parameters_1_2_422[] = {
+{ DSC_BPP(6), 8,
+ /* 12BPP/8BPC */
+ { 512, 15, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
+ { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 10,
+ /* 12BPP/10BPC */
+ { 512, 15, 6144, 7, 16, 15, 15, {
+ { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
+ { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 12,
+ /* 12BPP/12BPC */
+ { 512, 15, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
+ { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 14,
+ /* 12BPP/14BPC */
+ { 512, 15, 6144, 15, 24, 23, 23, {
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 16,
+ /* 12BPP/16BPC */
+ { 512, 15, 6144, 19, 28, 27, 27, {
+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
+ { 28, 29, -12 }
+ }
+ }
+},
+{ DSC_BPP(7), 8,
+ /* 14BPP/8BPC */
+ { 410, 15, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
+ }
+ }
+},
+{ DSC_BPP(7), 10,
+ /* 14BPP/10BPC */
+ { 410, 15, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
+ }
+ }
+},
+{ DSC_BPP(7), 12,
+ /* 14BPP/12BPC */
+ { 410, 15, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
+ { 19, 20, -12 }
+ }
+ }
+},
+{ DSC_BPP(7), 14,
+ /* 14BPP/14BPC */
+ { 410, 15, 5632, 15, 24, 23, 23, {
+ { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
+ { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
+ { 23, 24, -12 }
+ }
+ }
+},
+{ DSC_BPP(7), 16,
+ /* 14BPP/16BPC */
+ { 410, 15, 5632, 19, 28, 27, 27, {
+ { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
+ { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
+ { 27, 28, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 8,
+ /* 16BPP/8BPC */
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
+ { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 10,
+ /* 16BPP/10BPC */
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
+ { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 12,
+ /* 16BPP/12BPC */
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
+ { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
+ { 18, 19, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 14,
+ /* 16BPP/14BPC */
+ { 341, 15, 2048, 15, 24, 23, 23, {
+ { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
+ { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
+ { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
+ { 22, 23, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 16,
+ /* 16BPP/16BPC */
+ { 341, 15, 2048, 19, 28, 27, 27, {
+ { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
+ { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
+ { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
+ { 26, 27, -12 }
+ }
+ }
+},
+{ DSC_BPP(10), 8,
+ /* 20BPP/8BPC */
+ { 273, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
+ { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
+ { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
+ }
+ }
+},
+{ DSC_BPP(10), 10,
+ /* 20BPP/10BPC */
+ { 273, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
+ { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
+ { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+},
+{ DSC_BPP(10), 12,
+ /* 20BPP/12BPC */
+ { 273, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
+ { 16, 17, -12 }
+ }
+ }
+},
+{ DSC_BPP(10), 14,
+ /* 20BPP/14BPC */
+ { 273, 15, 2048, 15, 24, 23, 23, {
+ { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
+ { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
+ { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
+ { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+},
+{ DSC_BPP(10), 16,
+ /* 20BPP/16BPC */
+ { 273, 15, 2048, 19, 28, 27, 27, {
+ { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
+ { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
+ { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
+ { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+},
+{ /* sentinel */ }
+};
+
+static const struct rc_parameters_data rc_parameters_1_2_420[] = {
+{ DSC_BPP(4), 8,
+ /* 8BPP/8BPC */
+ { 512, 12, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
+ { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+},
+{ DSC_BPP(4), 10,
+ /* 8BPP/10BPC */
+ { 512, 12, 6144, 7, 16, 15, 15, {
+ { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
+ { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
+ }
+ }
+},
+{ DSC_BPP(4), 12,
+ /* 8BPP/12BPC */
+ { 512, 12, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
+ { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+},
+{ DSC_BPP(4), 14,
+ /* 8BPP/14BPC */
+ { 512, 12, 6144, 15, 24, 23, 23, {
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+},
+{ DSC_BPP(4), 16,
+ /* 8BPP/16BPC */
+ { 512, 12, 6144, 19, 28, 27, 27, {
+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
+ { 28, 29, -12 }
+ }
+ }
+},
+{ DSC_BPP(5), 8,
+ /* 10BPP/8BPC */
+ { 410, 15, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
+ }
+ }
+},
+{ DSC_BPP(5), 10,
+ /* 10BPP/10BPC */
+ { 410, 15, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
+ }
+ }
+},
+{ DSC_BPP(5), 12,
+ /* 10BPP/12BPC */
+ { 410, 15, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
+ { 19, 20, -12 }
+ }
+ }
+},
+{ DSC_BPP(5), 14,
+ /* 10BPP/14BPC */
+ { 410, 15, 5632, 15, 24, 23, 23, {
+ { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
+ { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
+ { 23, 24, -12 }
+ }
+ }
+},
+{ DSC_BPP(5), 16,
+ /* 10BPP/16BPC */
+ { 410, 15, 5632, 19, 28, 27, 27, {
+ { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
+ { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
+ { 27, 28, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 8,
+ /* 12BPP/8BPC */
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
+ { 5, 9, -12 }, { 7, 10, -12 }, { 10, 12, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 10,
+ /* 12BPP/10BPC */
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
+ { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 12,
+ /* 12BPP/12BPC */
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
+ { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
+ { 18, 19, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 14,
+ /* 12BPP/14BPC */
+ { 341, 15, 2048, 15, 24, 23, 23, {
+ { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
+ { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
+ { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
+ { 22, 23, -12 }
+ }
+ }
+},
+{ DSC_BPP(6), 16,
+ /* 12BPP/16BPC */
+ { 341, 15, 2048, 19, 28, 27, 27, {
+ { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
+ { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
+ { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
+ { 26, 27, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 8,
+ /* 16BPP/8BPC */
+ { 256, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
+ { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
+ { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 10,
+ /* 16BPP/10BPC */
+ { 256, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
+ { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
+ { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 12,
+ /* 16BPP/12BPC */
+ { 256, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
+ { 16, 17, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 14,
+ /* 16BPP/14BPC */
+ { 256, 15, 2048, 15, 24, 23, 23, {
+ { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
+ { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
+ { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
+ { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+},
+{ DSC_BPP(8), 16,
+ /* 16BPP/16BPC */
+ { 256, 15, 2048, 19, 28, 27, 27, {
+ { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
+ { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
+ { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
+ { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+},
+{ /* sentinel */ }
+};
+
static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
u16 dsc_bpp,
u8 bits_per_component)
@@ -776,6 +1208,12 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params
case DRM_DSC_1_1_PRE_SCR:
data = rc_parameters_pre_scr;
break;
+ case DRM_DSC_1_2_422:
+ data = rc_parameters_1_2_422;
+ break;
+ case DRM_DSC_1_2_420:
+ data = rc_parameters_1_2_420;
+ break;
default:
return -EINVAL;
}
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index c634bb2935d3..0bb0c3afd740 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -13,6 +13,8 @@
enum drm_dsc_params_kind {
DRM_DSC_1_2_444,
DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
+ DRM_DSC_1_2_422,
+ DRM_DSC_1_2_420,
};
void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 09/10] drm/display/dsc: add helper to set semi-const parameters
2023-02-28 11:33 ` Dmitry Baryshkov
(?)
@ 2023-02-28 11:33 ` Dmitry Baryshkov
-1 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
Add a helper setting config values which are typically constant across
operating modes (table E-4 of the standard) and mux_word_size (which is
a const according to 3.5.2).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 21 +++++++++++++++++++++
include/drm/display/drm_dsc_helper.h | 1 +
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index d11ee8f1efa7..7de1d84f5bc7 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -270,6 +270,27 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
}
EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
+/**
+ * drm_dsc_set_const_params() - Set DSC parameters considered typically
+ * constant across operation modes
+ *
+ * @vdsc_cfg:
+ * DSC Configuration data partially filled by driver
+ */
+void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg)
+{
+ vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
+ vdsc_cfg->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
+ vdsc_cfg->rc_tgt_offset_high = DSC_RC_TGT_OFFSET_HI_CONST;
+ vdsc_cfg->rc_tgt_offset_low = DSC_RC_TGT_OFFSET_LO_CONST;
+
+ if (vdsc_cfg->bits_per_component <= 10)
+ vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
+ else
+ vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
+}
+EXPORT_SYMBOL(drm_dsc_set_const_params);
+
/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
const u16 drm_dsc_rc_buf_thresh[] = {
896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 0bb0c3afd740..4448c482b092 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -21,6 +21,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
+void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg);
void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 09/10] drm/display/dsc: add helper to set semi-const parameters
@ 2023-02-28 11:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
Add a helper setting config values which are typically constant across
operating modes (table E-4 of the standard) and mux_word_size (which is
a const according to 3.5.2).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 21 +++++++++++++++++++++
include/drm/display/drm_dsc_helper.h | 1 +
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index d11ee8f1efa7..7de1d84f5bc7 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -270,6 +270,27 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
}
EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
+/**
+ * drm_dsc_set_const_params() - Set DSC parameters considered typically
+ * constant across operation modes
+ *
+ * @vdsc_cfg:
+ * DSC Configuration data partially filled by driver
+ */
+void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg)
+{
+ vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
+ vdsc_cfg->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
+ vdsc_cfg->rc_tgt_offset_high = DSC_RC_TGT_OFFSET_HI_CONST;
+ vdsc_cfg->rc_tgt_offset_low = DSC_RC_TGT_OFFSET_LO_CONST;
+
+ if (vdsc_cfg->bits_per_component <= 10)
+ vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
+ else
+ vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
+}
+EXPORT_SYMBOL(drm_dsc_set_const_params);
+
/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
const u16 drm_dsc_rc_buf_thresh[] = {
896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 0bb0c3afd740..4448c482b092 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -21,6 +21,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
+void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg);
void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH 09/10] drm/display/dsc: add helper to set semi-const parameters
@ 2023-02-28 11:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
Add a helper setting config values which are typically constant across
operating modes (table E-4 of the standard) and mux_word_size (which is
a const according to 3.5.2).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 21 +++++++++++++++++++++
include/drm/display/drm_dsc_helper.h | 1 +
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index d11ee8f1efa7..7de1d84f5bc7 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -270,6 +270,27 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
}
EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
+/**
+ * drm_dsc_set_const_params() - Set DSC parameters considered typically
+ * constant across operation modes
+ *
+ * @vdsc_cfg:
+ * DSC Configuration data partially filled by driver
+ */
+void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg)
+{
+ vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
+ vdsc_cfg->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
+ vdsc_cfg->rc_tgt_offset_high = DSC_RC_TGT_OFFSET_HI_CONST;
+ vdsc_cfg->rc_tgt_offset_low = DSC_RC_TGT_OFFSET_LO_CONST;
+
+ if (vdsc_cfg->bits_per_component <= 10)
+ vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
+ else
+ vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
+}
+EXPORT_SYMBOL(drm_dsc_set_const_params);
+
/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
const u16 drm_dsc_rc_buf_thresh[] = {
896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 0bb0c3afd740..4448c482b092 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -21,6 +21,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
+void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg);
void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 10/10] drm/msm/dsi: use new helpers for DSC setup
2023-02-28 11:33 ` Dmitry Baryshkov
(?)
@ 2023-02-28 11:33 ` Dmitry Baryshkov
-1 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
Use new DRM DSC helpers to setup DSI DSC configuration. The
initial_scale_value needs to be adjusted according to the standard, but
this is a separate change.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 61 ++++--------------------------
1 file changed, 8 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 18fa30e1e858..dda989727921 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -1735,28 +1735,9 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
return -EINVAL;
}
-static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = {
- 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62,
- 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e
-};
-
-/* only 8bpc, 8bpp added */
-static char min_qp[DSC_NUM_BUF_RANGES] = {
- 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13
-};
-
-static char max_qp[DSC_NUM_BUF_RANGES] = {
- 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15
-};
-
-static char bpg_offset[DSC_NUM_BUF_RANGES] = {
- 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
-};
-
static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc)
{
- int i;
- u16 bpp = dsc->bits_per_pixel >> 4;
+ int ret;
if (dsc->bits_per_pixel & 0xf) {
DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n");
@@ -1768,49 +1749,23 @@ static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc
return -EOPNOTSUPP;
}
- dsc->rc_model_size = 8192;
- dsc->first_line_bpg_offset = 12;
- dsc->rc_edge_factor = 6;
- dsc->rc_tgt_offset_high = 3;
- dsc->rc_tgt_offset_low = 3;
dsc->simple_422 = 0;
dsc->convert_rgb = 1;
dsc->vbr_enable = 0;
- /* handle only bpp = bpc = 8 */
- for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++)
- dsc->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i];
+ drm_dsc_set_const_params(dsc);
+ drm_dsc_set_rc_buf_thresh(dsc);
- for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
- dsc->rc_range_params[i].range_min_qp = min_qp[i];
- dsc->rc_range_params[i].range_max_qp = max_qp[i];
- /*
- * Range BPG Offset contains two's-complement signed values that fill
- * 8 bits, yet the registers and DCS PPS field are only 6 bits wide.
- */
- dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i] & DSC_RANGE_BPG_OFFSET_MASK;
+ /* handle only bpp = bpc = 8, pre-SCR panels */
+ ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR);
+ if (ret) {
+ DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n");
+ return ret;
}
- dsc->initial_offset = 6144; /* Not bpp 12 */
- if (bpp != 8)
- dsc->initial_offset = 2048; /* bpp = 12 */
-
- if (dsc->bits_per_component <= 10)
- dsc->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
- else
- dsc->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
-
- dsc->initial_xmit_delay = 512;
dsc->initial_scale_value = 32;
- dsc->first_line_bpg_offset = 12;
dsc->line_buf_depth = dsc->bits_per_component + 1;
- /* bpc 8 */
- dsc->flatness_min_qp = 3;
- dsc->flatness_max_qp = 12;
- dsc->rc_quant_incr_limit0 = 11;
- dsc->rc_quant_incr_limit1 = 11;
-
return drm_dsc_compute_rc_parameters(dsc);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH 10/10] drm/msm/dsi: use new helpers for DSC setup
@ 2023-02-28 11:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
Use new DRM DSC helpers to setup DSI DSC configuration. The
initial_scale_value needs to be adjusted according to the standard, but
this is a separate change.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 61 ++++--------------------------
1 file changed, 8 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 18fa30e1e858..dda989727921 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -1735,28 +1735,9 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
return -EINVAL;
}
-static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = {
- 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62,
- 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e
-};
-
-/* only 8bpc, 8bpp added */
-static char min_qp[DSC_NUM_BUF_RANGES] = {
- 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13
-};
-
-static char max_qp[DSC_NUM_BUF_RANGES] = {
- 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15
-};
-
-static char bpg_offset[DSC_NUM_BUF_RANGES] = {
- 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
-};
-
static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc)
{
- int i;
- u16 bpp = dsc->bits_per_pixel >> 4;
+ int ret;
if (dsc->bits_per_pixel & 0xf) {
DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n");
@@ -1768,49 +1749,23 @@ static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc
return -EOPNOTSUPP;
}
- dsc->rc_model_size = 8192;
- dsc->first_line_bpg_offset = 12;
- dsc->rc_edge_factor = 6;
- dsc->rc_tgt_offset_high = 3;
- dsc->rc_tgt_offset_low = 3;
dsc->simple_422 = 0;
dsc->convert_rgb = 1;
dsc->vbr_enable = 0;
- /* handle only bpp = bpc = 8 */
- for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++)
- dsc->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i];
+ drm_dsc_set_const_params(dsc);
+ drm_dsc_set_rc_buf_thresh(dsc);
- for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
- dsc->rc_range_params[i].range_min_qp = min_qp[i];
- dsc->rc_range_params[i].range_max_qp = max_qp[i];
- /*
- * Range BPG Offset contains two's-complement signed values that fill
- * 8 bits, yet the registers and DCS PPS field are only 6 bits wide.
- */
- dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i] & DSC_RANGE_BPG_OFFSET_MASK;
+ /* handle only bpp = bpc = 8, pre-SCR panels */
+ ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR);
+ if (ret) {
+ DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n");
+ return ret;
}
- dsc->initial_offset = 6144; /* Not bpp 12 */
- if (bpp != 8)
- dsc->initial_offset = 2048; /* bpp = 12 */
-
- if (dsc->bits_per_component <= 10)
- dsc->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
- else
- dsc->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
-
- dsc->initial_xmit_delay = 512;
dsc->initial_scale_value = 32;
- dsc->first_line_bpg_offset = 12;
dsc->line_buf_depth = dsc->bits_per_component + 1;
- /* bpc 8 */
- dsc->flatness_min_qp = 3;
- dsc->flatness_max_qp = 12;
- dsc->rc_quant_incr_limit0 = 11;
- dsc->rc_quant_incr_limit1 = 11;
-
return drm_dsc_compute_rc_parameters(dsc);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH 10/10] drm/msm/dsi: use new helpers for DSC setup
@ 2023-02-28 11:33 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 11:33 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
Use new DRM DSC helpers to setup DSI DSC configuration. The
initial_scale_value needs to be adjusted according to the standard, but
this is a separate change.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 61 ++++--------------------------
1 file changed, 8 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 18fa30e1e858..dda989727921 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -1735,28 +1735,9 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
return -EINVAL;
}
-static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = {
- 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62,
- 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e
-};
-
-/* only 8bpc, 8bpp added */
-static char min_qp[DSC_NUM_BUF_RANGES] = {
- 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13
-};
-
-static char max_qp[DSC_NUM_BUF_RANGES] = {
- 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15
-};
-
-static char bpg_offset[DSC_NUM_BUF_RANGES] = {
- 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
-};
-
static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc)
{
- int i;
- u16 bpp = dsc->bits_per_pixel >> 4;
+ int ret;
if (dsc->bits_per_pixel & 0xf) {
DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n");
@@ -1768,49 +1749,23 @@ static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc
return -EOPNOTSUPP;
}
- dsc->rc_model_size = 8192;
- dsc->first_line_bpg_offset = 12;
- dsc->rc_edge_factor = 6;
- dsc->rc_tgt_offset_high = 3;
- dsc->rc_tgt_offset_low = 3;
dsc->simple_422 = 0;
dsc->convert_rgb = 1;
dsc->vbr_enable = 0;
- /* handle only bpp = bpc = 8 */
- for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++)
- dsc->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i];
+ drm_dsc_set_const_params(dsc);
+ drm_dsc_set_rc_buf_thresh(dsc);
- for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
- dsc->rc_range_params[i].range_min_qp = min_qp[i];
- dsc->rc_range_params[i].range_max_qp = max_qp[i];
- /*
- * Range BPG Offset contains two's-complement signed values that fill
- * 8 bits, yet the registers and DCS PPS field are only 6 bits wide.
- */
- dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i] & DSC_RANGE_BPG_OFFSET_MASK;
+ /* handle only bpp = bpc = 8, pre-SCR panels */
+ ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR);
+ if (ret) {
+ DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n");
+ return ret;
}
- dsc->initial_offset = 6144; /* Not bpp 12 */
- if (bpp != 8)
- dsc->initial_offset = 2048; /* bpp = 12 */
-
- if (dsc->bits_per_component <= 10)
- dsc->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
- else
- dsc->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
-
- dsc->initial_xmit_delay = 512;
dsc->initial_scale_value = 32;
- dsc->first_line_bpg_offset = 12;
dsc->line_buf_depth = dsc->bits_per_component + 1;
- /* bpc 8 */
- dsc->flatness_min_qp = 3;
- dsc->flatness_max_qp = 12;
- dsc->rc_quant_incr_limit0 = 11;
- dsc->rc_quant_incr_limit1 = 11;
-
return drm_dsc_compute_rc_parameters(dsc);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: move DSC RC tables to drm_dsc_helper.c
2023-02-28 11:33 ` Dmitry Baryshkov
` (11 preceding siblings ...)
(?)
@ 2023-02-28 12:03 ` Patchwork
-1 siblings, 0 replies; 80+ messages in thread
From: Patchwork @ 2023-02-28 12:03 UTC (permalink / raw)
To: Dmitry Baryshkov; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 15290 bytes --]
== Series Details ==
Series: drm/i915: move DSC RC tables to drm_dsc_helper.c
URL : https://patchwork.freedesktop.org/series/114473/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12790 -> Patchwork_114473v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/index.html
Participating hosts (2 -> 36)
------------------------------
Additional (35): fi-rkl-11600 bat-dg1-6 bat-dg1-5 bat-adlp-6 fi-apl-guc fi-pnv-d510 bat-rpls-1 fi-blb-e6850 bat-rpls-2 fi-skl-6600u fi-bsw-n3050 bat-dg2-8 bat-adlm-1 bat-dg2-9 fi-ilk-650 fi-hsw-4770 bat-adln-1 fi-ivb-3770 bat-jsl-3 bat-rplp-1 fi-elk-e7500 bat-dg2-11 fi-bsw-nick fi-kbl-7567u bat-dg1-7 bat-adlp-9 fi-skl-guc fi-cfl-8700k fi-glk-j4005 bat-jsl-1 fi-tgl-1115g4 fi-cfl-guc fi-kbl-guc fi-kbl-x1275 fi-cfl-8109u
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_114473v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- fi-skl-guc: NOTRUN -> [SKIP][1] ([fdo#109271])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-skl-guc/igt@debugfs_test@basic-hwmon.html
- bat-rpls-2: NOTRUN -> [SKIP][2] ([i915#7456])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-rpls-2/igt@debugfs_test@basic-hwmon.html
- fi-glk-j4005: NOTRUN -> [SKIP][3] ([fdo#109271])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-glk-j4005/igt@debugfs_test@basic-hwmon.html
- fi-hsw-4770: NOTRUN -> [SKIP][4] ([fdo#109271])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-hsw-4770/igt@debugfs_test@basic-hwmon.html
- fi-cfl-8109u: NOTRUN -> [SKIP][5] ([fdo#109271])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-cfl-8109u/igt@debugfs_test@basic-hwmon.html
- bat-adlp-9: NOTRUN -> [SKIP][6] ([i915#7456])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-adlp-9/igt@debugfs_test@basic-hwmon.html
- fi-kbl-7567u: NOTRUN -> [SKIP][7] ([fdo#109271])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-kbl-7567u/igt@debugfs_test@basic-hwmon.html
- bat-adln-1: NOTRUN -> [SKIP][8] ([i915#7456])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-adln-1/igt@debugfs_test@basic-hwmon.html
- fi-ivb-3770: NOTRUN -> [SKIP][9] ([fdo#109271])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-ivb-3770/igt@debugfs_test@basic-hwmon.html
- fi-elk-e7500: NOTRUN -> [SKIP][10] ([fdo#109271])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-elk-e7500/igt@debugfs_test@basic-hwmon.html
- fi-cfl-8700k: NOTRUN -> [SKIP][11] ([fdo#109271])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-cfl-8700k/igt@debugfs_test@basic-hwmon.html
- bat-adlm-1: NOTRUN -> [SKIP][12] ([i915#7456])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-adlm-1/igt@debugfs_test@basic-hwmon.html
- fi-ilk-650: NOTRUN -> [SKIP][13] ([fdo#109271])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-ilk-650/igt@debugfs_test@basic-hwmon.html
- bat-jsl-1: NOTRUN -> [SKIP][14] ([i915#7456])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-jsl-1/igt@debugfs_test@basic-hwmon.html
- fi-tgl-1115g4: NOTRUN -> [SKIP][15] ([i915#7456])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-tgl-1115g4/igt@debugfs_test@basic-hwmon.html
- bat-adlp-6: NOTRUN -> [SKIP][16] ([i915#7456])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-adlp-6/igt@debugfs_test@basic-hwmon.html
- bat-rplp-1: NOTRUN -> [SKIP][17] ([i915#7456])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-rplp-1/igt@debugfs_test@basic-hwmon.html
- fi-rkl-11600: NOTRUN -> [SKIP][18] ([i915#7456])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-rkl-11600/igt@debugfs_test@basic-hwmon.html
- fi-bsw-n3050: NOTRUN -> [SKIP][19] ([fdo#109271])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-bsw-n3050/igt@debugfs_test@basic-hwmon.html
- bat-rpls-1: NOTRUN -> [SKIP][20] ([i915#7456])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-rpls-1/igt@debugfs_test@basic-hwmon.html
- fi-apl-guc: NOTRUN -> [SKIP][21] ([fdo#109271])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-apl-guc/igt@debugfs_test@basic-hwmon.html
- fi-cfl-guc: NOTRUN -> [SKIP][22] ([fdo#109271])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-cfl-guc/igt@debugfs_test@basic-hwmon.html
- fi-skl-6600u: NOTRUN -> [SKIP][23] ([fdo#109271])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-skl-6600u/igt@debugfs_test@basic-hwmon.html
- bat-jsl-3: NOTRUN -> [SKIP][24] ([i915#7456])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-jsl-3/igt@debugfs_test@basic-hwmon.html
* igt@fbdev@eof:
- fi-kbl-guc: NOTRUN -> [SKIP][25] ([fdo#109271]) +5 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-kbl-guc/igt@fbdev@eof.html
- bat-adlm-1: NOTRUN -> [SKIP][26] ([i915#2582]) +4 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-adlm-1/igt@fbdev@eof.html
- fi-bsw-nick: NOTRUN -> [SKIP][27] ([fdo#109271]) +5 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-bsw-nick/igt@fbdev@eof.html
* igt@fbdev@info:
- bat-dg1-7: NOTRUN -> [SKIP][28] ([i915#2582]) +4 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-dg1-7/igt@fbdev@info.html
* igt@fbdev@nullptr:
- bat-rpls-1: NOTRUN -> [SKIP][29] ([i915#2582]) +4 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-rpls-1/igt@fbdev@nullptr.html
* igt@fbdev@read:
- bat-rpls-2: NOTRUN -> [SKIP][30] ([i915#2582]) +4 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-rpls-2/igt@fbdev@read.html
- fi-kbl-x1275: NOTRUN -> [SKIP][31] ([fdo#109271]) +5 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-kbl-x1275/igt@fbdev@read.html
* igt@gem_ctx_create@basic:
- fi-blb-e6850: NOTRUN -> [SKIP][32] ([fdo#109271]) +3 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-blb-e6850/igt@gem_ctx_create@basic.html
* igt@gem_ctx_create@basic-files:
- fi-pnv-d510: NOTRUN -> [SKIP][33] ([fdo#109271]) +3 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-pnv-d510/igt@gem_ctx_create@basic-files.html
* igt@gem_exec_fence@basic-busy@ccs0:
- bat-dg2-11: NOTRUN -> [ABORT][34] ([i915#8233])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-dg2-11/igt@gem_exec_fence@basic-busy@ccs0.html
* igt@gem_exec_fence@basic-busy@ccs3:
- bat-dg2-9: NOTRUN -> [ABORT][35] ([i915#8233])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-dg2-9/igt@gem_exec_fence@basic-busy@ccs3.html
- bat-dg2-8: NOTRUN -> [ABORT][36] ([i915#8233])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-dg2-8/igt@gem_exec_fence@basic-busy@ccs3.html
* igt@gem_exec_fence@basic-busy@rcs0:
- fi-blb-e6850: NOTRUN -> [ABORT][37] ([i915#8233])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-blb-e6850/igt@gem_exec_fence@basic-busy@rcs0.html
- fi-pnv-d510: NOTRUN -> [ABORT][38] ([i915#8233])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-pnv-d510/igt@gem_exec_fence@basic-busy@rcs0.html
* igt@gem_exec_fence@basic-busy@vcs0:
- fi-ivb-3770: NOTRUN -> [ABORT][39] ([i915#8233])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-ivb-3770/igt@gem_exec_fence@basic-busy@vcs0.html
- fi-elk-e7500: NOTRUN -> [ABORT][40] ([i915#8233])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-elk-e7500/igt@gem_exec_fence@basic-busy@vcs0.html
- fi-ilk-650: NOTRUN -> [ABORT][41] ([i915#8233])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-ilk-650/igt@gem_exec_fence@basic-busy@vcs0.html
* igt@gem_exec_fence@basic-busy@vecs0:
- bat-adlp-9: NOTRUN -> [ABORT][42] ([i915#8233])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-adlp-9/igt@gem_exec_fence@basic-busy@vecs0.html
- fi-skl-guc: NOTRUN -> [ABORT][43] ([i915#8233])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-skl-guc/igt@gem_exec_fence@basic-busy@vecs0.html
- bat-rpls-2: NOTRUN -> [ABORT][44] ([i915#8233])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-rpls-2/igt@gem_exec_fence@basic-busy@vecs0.html
- bat-dg1-6: NOTRUN -> [ABORT][45] ([i915#8233])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-dg1-6/igt@gem_exec_fence@basic-busy@vecs0.html
- fi-cfl-8109u: NOTRUN -> [ABORT][46] ([i915#8233])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-cfl-8109u/igt@gem_exec_fence@basic-busy@vecs0.html
- fi-kbl-7567u: NOTRUN -> [ABORT][47] ([i915#8233])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-kbl-7567u/igt@gem_exec_fence@basic-busy@vecs0.html
- bat-adln-1: NOTRUN -> [ABORT][48] ([i915#8233])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-adln-1/igt@gem_exec_fence@basic-busy@vecs0.html
- bat-jsl-1: NOTRUN -> [ABORT][49] ([i915#8233])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-jsl-1/igt@gem_exec_fence@basic-busy@vecs0.html
- fi-bsw-nick: NOTRUN -> [ABORT][50] ([i915#8233])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-bsw-nick/igt@gem_exec_fence@basic-busy@vecs0.html
- fi-kbl-guc: NOTRUN -> [ABORT][51] ([i915#8233])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-kbl-guc/igt@gem_exec_fence@basic-busy@vecs0.html
- fi-cfl-8700k: NOTRUN -> [ABORT][52] ([i915#8233])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-cfl-8700k/igt@gem_exec_fence@basic-busy@vecs0.html
- bat-adlm-1: NOTRUN -> [ABORT][53] ([i915#8233])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-adlm-1/igt@gem_exec_fence@basic-busy@vecs0.html
- bat-rplp-1: NOTRUN -> [ABORT][54] ([i915#8233])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-rplp-1/igt@gem_exec_fence@basic-busy@vecs0.html
- bat-rpls-1: NOTRUN -> [ABORT][55] ([i915#8233])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-rpls-1/igt@gem_exec_fence@basic-busy@vecs0.html
- fi-tgl-1115g4: NOTRUN -> [ABORT][56] ([i915#8233])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-tgl-1115g4/igt@gem_exec_fence@basic-busy@vecs0.html
- bat-adlp-6: NOTRUN -> [ABORT][57] ([i915#8233])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-adlp-6/igt@gem_exec_fence@basic-busy@vecs0.html
- fi-rkl-11600: NOTRUN -> [ABORT][58] ([i915#8233])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-rkl-11600/igt@gem_exec_fence@basic-busy@vecs0.html
- fi-skl-6600u: NOTRUN -> [ABORT][59] ([i915#8233])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-skl-6600u/igt@gem_exec_fence@basic-busy@vecs0.html
- fi-bsw-n3050: NOTRUN -> [ABORT][60] ([i915#8233])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-bsw-n3050/igt@gem_exec_fence@basic-busy@vecs0.html
- fi-apl-guc: NOTRUN -> [ABORT][61] ([i915#8233])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-apl-guc/igt@gem_exec_fence@basic-busy@vecs0.html
- bat-dg1-5: NOTRUN -> [ABORT][62] ([i915#8233])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-dg1-5/igt@gem_exec_fence@basic-busy@vecs0.html
- fi-cfl-guc: NOTRUN -> [ABORT][63] ([i915#8233])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-cfl-guc/igt@gem_exec_fence@basic-busy@vecs0.html
- bat-dg1-7: NOTRUN -> [ABORT][64] ([i915#8233])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-dg1-7/igt@gem_exec_fence@basic-busy@vecs0.html
- fi-kbl-x1275: NOTRUN -> [ABORT][65] ([i915#8233])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-kbl-x1275/igt@gem_exec_fence@basic-busy@vecs0.html
- bat-jsl-3: NOTRUN -> [ABORT][66] ([i915#8233])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/bat-jsl-3/igt@gem_exec_fence@basic-busy@vecs0.html
- fi-glk-j4005: NOTRUN -> [ABORT][67] ([i915#8233])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-glk-j4005/igt@gem_exec_fence@basic-busy@vecs0.html
- fi-hsw-4770: NOTRUN -> [ABORT][68] ([i915#8233])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/fi-hsw-4770/igt@gem_exec_fence@basic-busy@vecs0.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#8233]: https://gitlab.freedesktop.org/drm/intel/issues/8233
Build changes
-------------
* Linux: CI_DRM_12790 -> Patchwork_114473v1
CI-20190529: 20190529
CI_DRM_12790: 92b7ba2b502495a393b6db904061b6938a09db17 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7175: e825eb183729902489365e56bd99f15af2aa3316 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_114473v1: 92b7ba2b502495a393b6db904061b6938a09db17 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
f6cbddae2db3 drm/msm/dsi: use new helpers for DSC setup
c520830814e8 drm/display/dsc: add helper to set semi-const parameters
89e01861d200 drm/display/dsc: add YCbCr 4:2:2 and 4:2:0 RC parameters
6ecab7475701 drm/display/dsc: include the rest of pre-SCR parameters
284545f6155d drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
0079d6f2ccc1 drm/display/dsc: use flat array for rc_parameters lookup
a13494a70f9e drm/i915/dsc: stop using interim structure for calculated params
ae962c600c57 drm/i915/dsc: move DSC tables to DRM DSC helper
db78e2293650 drm/i915/dsc: move rc_buf_thresh values to common helper
03c0ac635674 drm/i915/dsc: change DSC param tables to follow the DSC model
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/index.html
[-- Attachment #2: Type: text/html, Size: 21268 bytes --]
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 02/10] drm/i915/dsc: move rc_buf_thresh values to common helper
2023-02-28 11:33 ` Dmitry Baryshkov
(?)
@ 2023-02-28 12:24 ` Jani Nikula
-1 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 12:24 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> The rc_buf_thresh values are common to all DSC implementations. Move
> them to the common helper together with the code to propagage them to
> the drm_dsc_config.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 37 +++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +--------------
> include/drm/display/drm_dsc_helper.h | 1 +
> 3 files changed, 39 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> index c869c6e51e2b..ab8679c158b5 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -270,6 +270,43 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
> }
> EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
>
> +/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
> +const u16 drm_dsc_rc_buf_thresh[] = {
> + 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
> + 7744, 7872, 8000, 8064
> +};
> +EXPORT_SYMBOL(drm_dsc_rc_buf_thresh);
This needs to be static, without exports.
> +
> +/**
> + * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
> + * in accordance with the DSC 1.2 specification.
> + *
> + * @vdsc_cfg: DSC Configuration data partially filled by driver
> + */
> +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
> +{
> + int i = 0;
Unnecessary initialization.
> +
> + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
Please use ARRAY_SIZE(). Maybe add BUILD_BUG_ON() for DSC_NUM_BUF_RANGES
vs. ARRAY_SIZE(). (Yes, we should've used ARRAY_SIZE() in i915.)
> + /*
> + * six 0s are appended to the lsb of each threshold value
> + * internally in h/w.
> + * Only 8 bits are allowed for programming RcBufThreshold
> + */
> + vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
> + }
> +
> + /*
> + * For 6bpp, RC Buffer threshold 12 and 13 need a different value
> + * as per C Model
> + */
> + if (vdsc_cfg->bits_per_pixel == 6 << 4) {
> + vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
> + vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
> + }
> +}
> +EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
> +
> /**
> * drm_dsc_compute_rc_parameters() - Write rate control
> * parameters to the dsc configuration defined in
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index d080741fd0b3..b4faab4c8fb3 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -36,12 +36,6 @@ enum COLUMN_INDEX_BPC {
> MAX_COLUMN_INDEX
> };
>
> -/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
> -static const u16 rc_buf_thresh[] = {
> - 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
> - 7744, 7872, 8000, 8064
> -};
> -
> struct rc_parameters {
> u16 initial_xmit_delay;
> u8 first_line_bpg_offset;
> @@ -474,23 +468,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
> vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
>
> - for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
> - /*
> - * six 0s are appended to the lsb of each threshold value
> - * internally in h/w.
> - * Only 8 bits are allowed for programming RcBufThreshold
> - */
> - vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
> - }
> -
> - /*
> - * For 6bpp, RC Buffer threshold 12 and 13 need a different value
> - * as per C Model
> - */
> - if (compressed_bpp == 6) {
> - vdsc_cfg->rc_buf_thresh[12] = 0x7C;
> - vdsc_cfg->rc_buf_thresh[13] = 0x7D;
> - }
> + drm_dsc_set_rc_buf_thresh(vdsc_cfg);
>
> /*
> * From XE_LPD onwards we supports compression bpps in steps of 1
> diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> index 8b41edbbabab..706ba1d34742 100644
> --- a/include/drm/display/drm_dsc_helper.h
> +++ b/include/drm/display/drm_dsc_helper.h
> @@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
> int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> const struct drm_dsc_config *dsc_cfg);
> +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>
> #endif /* _DRM_DSC_HELPER_H_ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 02/10] drm/i915/dsc: move rc_buf_thresh values to common helper
@ 2023-02-28 12:24 ` Jani Nikula
0 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 12:24 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> The rc_buf_thresh values are common to all DSC implementations. Move
> them to the common helper together with the code to propagage them to
> the drm_dsc_config.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 37 +++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +--------------
> include/drm/display/drm_dsc_helper.h | 1 +
> 3 files changed, 39 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> index c869c6e51e2b..ab8679c158b5 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -270,6 +270,43 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
> }
> EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
>
> +/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
> +const u16 drm_dsc_rc_buf_thresh[] = {
> + 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
> + 7744, 7872, 8000, 8064
> +};
> +EXPORT_SYMBOL(drm_dsc_rc_buf_thresh);
This needs to be static, without exports.
> +
> +/**
> + * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
> + * in accordance with the DSC 1.2 specification.
> + *
> + * @vdsc_cfg: DSC Configuration data partially filled by driver
> + */
> +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
> +{
> + int i = 0;
Unnecessary initialization.
> +
> + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
Please use ARRAY_SIZE(). Maybe add BUILD_BUG_ON() for DSC_NUM_BUF_RANGES
vs. ARRAY_SIZE(). (Yes, we should've used ARRAY_SIZE() in i915.)
> + /*
> + * six 0s are appended to the lsb of each threshold value
> + * internally in h/w.
> + * Only 8 bits are allowed for programming RcBufThreshold
> + */
> + vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
> + }
> +
> + /*
> + * For 6bpp, RC Buffer threshold 12 and 13 need a different value
> + * as per C Model
> + */
> + if (vdsc_cfg->bits_per_pixel == 6 << 4) {
> + vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
> + vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
> + }
> +}
> +EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
> +
> /**
> * drm_dsc_compute_rc_parameters() - Write rate control
> * parameters to the dsc configuration defined in
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index d080741fd0b3..b4faab4c8fb3 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -36,12 +36,6 @@ enum COLUMN_INDEX_BPC {
> MAX_COLUMN_INDEX
> };
>
> -/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
> -static const u16 rc_buf_thresh[] = {
> - 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
> - 7744, 7872, 8000, 8064
> -};
> -
> struct rc_parameters {
> u16 initial_xmit_delay;
> u8 first_line_bpg_offset;
> @@ -474,23 +468,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
> vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
>
> - for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
> - /*
> - * six 0s are appended to the lsb of each threshold value
> - * internally in h/w.
> - * Only 8 bits are allowed for programming RcBufThreshold
> - */
> - vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
> - }
> -
> - /*
> - * For 6bpp, RC Buffer threshold 12 and 13 need a different value
> - * as per C Model
> - */
> - if (compressed_bpp == 6) {
> - vdsc_cfg->rc_buf_thresh[12] = 0x7C;
> - vdsc_cfg->rc_buf_thresh[13] = 0x7D;
> - }
> + drm_dsc_set_rc_buf_thresh(vdsc_cfg);
>
> /*
> * From XE_LPD onwards we supports compression bpps in steps of 1
> diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> index 8b41edbbabab..706ba1d34742 100644
> --- a/include/drm/display/drm_dsc_helper.h
> +++ b/include/drm/display/drm_dsc_helper.h
> @@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
> int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> const struct drm_dsc_config *dsc_cfg);
> +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>
> #endif /* _DRM_DSC_HELPER_H_ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH 02/10] drm/i915/dsc: move rc_buf_thresh values to common helper
@ 2023-02-28 12:24 ` Jani Nikula
0 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 12:24 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> The rc_buf_thresh values are common to all DSC implementations. Move
> them to the common helper together with the code to propagage them to
> the drm_dsc_config.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 37 +++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +--------------
> include/drm/display/drm_dsc_helper.h | 1 +
> 3 files changed, 39 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> index c869c6e51e2b..ab8679c158b5 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -270,6 +270,43 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
> }
> EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
>
> +/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
> +const u16 drm_dsc_rc_buf_thresh[] = {
> + 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
> + 7744, 7872, 8000, 8064
> +};
> +EXPORT_SYMBOL(drm_dsc_rc_buf_thresh);
This needs to be static, without exports.
> +
> +/**
> + * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
> + * in accordance with the DSC 1.2 specification.
> + *
> + * @vdsc_cfg: DSC Configuration data partially filled by driver
> + */
> +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
> +{
> + int i = 0;
Unnecessary initialization.
> +
> + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
Please use ARRAY_SIZE(). Maybe add BUILD_BUG_ON() for DSC_NUM_BUF_RANGES
vs. ARRAY_SIZE(). (Yes, we should've used ARRAY_SIZE() in i915.)
> + /*
> + * six 0s are appended to the lsb of each threshold value
> + * internally in h/w.
> + * Only 8 bits are allowed for programming RcBufThreshold
> + */
> + vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
> + }
> +
> + /*
> + * For 6bpp, RC Buffer threshold 12 and 13 need a different value
> + * as per C Model
> + */
> + if (vdsc_cfg->bits_per_pixel == 6 << 4) {
> + vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
> + vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
> + }
> +}
> +EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
> +
> /**
> * drm_dsc_compute_rc_parameters() - Write rate control
> * parameters to the dsc configuration defined in
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index d080741fd0b3..b4faab4c8fb3 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -36,12 +36,6 @@ enum COLUMN_INDEX_BPC {
> MAX_COLUMN_INDEX
> };
>
> -/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
> -static const u16 rc_buf_thresh[] = {
> - 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
> - 7744, 7872, 8000, 8064
> -};
> -
> struct rc_parameters {
> u16 initial_xmit_delay;
> u8 first_line_bpg_offset;
> @@ -474,23 +468,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
> vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
>
> - for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
> - /*
> - * six 0s are appended to the lsb of each threshold value
> - * internally in h/w.
> - * Only 8 bits are allowed for programming RcBufThreshold
> - */
> - vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
> - }
> -
> - /*
> - * For 6bpp, RC Buffer threshold 12 and 13 need a different value
> - * as per C Model
> - */
> - if (compressed_bpp == 6) {
> - vdsc_cfg->rc_buf_thresh[12] = 0x7C;
> - vdsc_cfg->rc_buf_thresh[13] = 0x7D;
> - }
> + drm_dsc_set_rc_buf_thresh(vdsc_cfg);
>
> /*
> * From XE_LPD onwards we supports compression bpps in steps of 1
> diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> index 8b41edbbabab..706ba1d34742 100644
> --- a/include/drm/display/drm_dsc_helper.h
> +++ b/include/drm/display/drm_dsc_helper.h
> @@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
> int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> const struct drm_dsc_config *dsc_cfg);
> +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>
> #endif /* _DRM_DSC_HELPER_H_ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 02/10] drm/i915/dsc: move rc_buf_thresh values to common helper
2023-02-28 12:24 ` Jani Nikula
(?)
@ 2023-02-28 12:35 ` Dmitry Baryshkov
-1 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 12:35 UTC (permalink / raw)
To: Jani Nikula
Cc: David Airlie, Daniel Vetter, Joonas Lahtinen, Rodrigo Vivi,
Tvrtko Ursulin, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, Ville Syrjälä,
dri-devel, intel-gfx, linux-arm-msm, freedreno
On Tue, 28 Feb 2023 at 14:25, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>
> On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> > The rc_buf_thresh values are common to all DSC implementations. Move
> > them to the common helper together with the code to propagage them to
> > the drm_dsc_config.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > drivers/gpu/drm/display/drm_dsc_helper.c | 37 +++++++++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +--------------
> > include/drm/display/drm_dsc_helper.h | 1 +
> > 3 files changed, 39 insertions(+), 23 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> > index c869c6e51e2b..ab8679c158b5 100644
> > --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> > +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> > @@ -270,6 +270,43 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
> > }
> > EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
> >
> > +/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
> > +const u16 drm_dsc_rc_buf_thresh[] = {
> > + 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
> > + 7744, 7872, 8000, 8064
> > +};
> > +EXPORT_SYMBOL(drm_dsc_rc_buf_thresh);
>
> This needs to be static, without exports.
Exported this to let other drivers use it, while skipping the
drm_dsc_set_rc_buf_thresh(). For example amdgpu driver sets buffer
thresholds on the interim structure, so the helper is not directly
applicable. See _do_calc_rc_params().
>
> > +
> > +/**
> > + * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
> > + * in accordance with the DSC 1.2 specification.
> > + *
> > + * @vdsc_cfg: DSC Configuration data partially filled by driver
> > + */
> > +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
> > +{
> > + int i = 0;
>
> Unnecessary initialization.
My bad.
>
> > +
> > + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
>
> Please use ARRAY_SIZE(). Maybe add BUILD_BUG_ON() for DSC_NUM_BUF_RANGES
> vs. ARRAY_SIZE(). (Yes, we should've used ARRAY_SIZE() in i915.)
Ack
>
> > + /*
> > + * six 0s are appended to the lsb of each threshold value
> > + * internally in h/w.
> > + * Only 8 bits are allowed for programming RcBufThreshold
> > + */
> > + vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
> > + }
> > +
> > + /*
> > + * For 6bpp, RC Buffer threshold 12 and 13 need a different value
> > + * as per C Model
> > + */
> > + if (vdsc_cfg->bits_per_pixel == 6 << 4) {
> > + vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
> > + vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
> > + }
> > +}
> > +EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
> > +
> > /**
> > * drm_dsc_compute_rc_parameters() - Write rate control
> > * parameters to the dsc configuration defined in
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index d080741fd0b3..b4faab4c8fb3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -36,12 +36,6 @@ enum COLUMN_INDEX_BPC {
> > MAX_COLUMN_INDEX
> > };
> >
> > -/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
> > -static const u16 rc_buf_thresh[] = {
> > - 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
> > - 7744, 7872, 8000, 8064
> > -};
> > -
> > struct rc_parameters {
> > u16 initial_xmit_delay;
> > u8 first_line_bpg_offset;
> > @@ -474,23 +468,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> > vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
> > vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
> >
> > - for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
> > - /*
> > - * six 0s are appended to the lsb of each threshold value
> > - * internally in h/w.
> > - * Only 8 bits are allowed for programming RcBufThreshold
> > - */
> > - vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
> > - }
> > -
> > - /*
> > - * For 6bpp, RC Buffer threshold 12 and 13 need a different value
> > - * as per C Model
> > - */
> > - if (compressed_bpp == 6) {
> > - vdsc_cfg->rc_buf_thresh[12] = 0x7C;
> > - vdsc_cfg->rc_buf_thresh[13] = 0x7D;
> > - }
> > + drm_dsc_set_rc_buf_thresh(vdsc_cfg);
> >
> > /*
> > * From XE_LPD onwards we supports compression bpps in steps of 1
> > diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> > index 8b41edbbabab..706ba1d34742 100644
> > --- a/include/drm/display/drm_dsc_helper.h
> > +++ b/include/drm/display/drm_dsc_helper.h
> > @@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
> > int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> > void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> > const struct drm_dsc_config *dsc_cfg);
> > +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> > int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
> >
> > #endif /* _DRM_DSC_HELPER_H_ */
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 02/10] drm/i915/dsc: move rc_buf_thresh values to common helper
@ 2023-02-28 12:35 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 12:35 UTC (permalink / raw)
To: Jani Nikula
Cc: linux-arm-msm, Tvrtko Ursulin, Sean Paul, intel-gfx,
Abhinav Kumar, dri-devel, Rodrigo Vivi, Marijn Suijten,
freedreno
On Tue, 28 Feb 2023 at 14:25, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>
> On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> > The rc_buf_thresh values are common to all DSC implementations. Move
> > them to the common helper together with the code to propagage them to
> > the drm_dsc_config.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > drivers/gpu/drm/display/drm_dsc_helper.c | 37 +++++++++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +--------------
> > include/drm/display/drm_dsc_helper.h | 1 +
> > 3 files changed, 39 insertions(+), 23 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> > index c869c6e51e2b..ab8679c158b5 100644
> > --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> > +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> > @@ -270,6 +270,43 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
> > }
> > EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
> >
> > +/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
> > +const u16 drm_dsc_rc_buf_thresh[] = {
> > + 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
> > + 7744, 7872, 8000, 8064
> > +};
> > +EXPORT_SYMBOL(drm_dsc_rc_buf_thresh);
>
> This needs to be static, without exports.
Exported this to let other drivers use it, while skipping the
drm_dsc_set_rc_buf_thresh(). For example amdgpu driver sets buffer
thresholds on the interim structure, so the helper is not directly
applicable. See _do_calc_rc_params().
>
> > +
> > +/**
> > + * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
> > + * in accordance with the DSC 1.2 specification.
> > + *
> > + * @vdsc_cfg: DSC Configuration data partially filled by driver
> > + */
> > +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
> > +{
> > + int i = 0;
>
> Unnecessary initialization.
My bad.
>
> > +
> > + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
>
> Please use ARRAY_SIZE(). Maybe add BUILD_BUG_ON() for DSC_NUM_BUF_RANGES
> vs. ARRAY_SIZE(). (Yes, we should've used ARRAY_SIZE() in i915.)
Ack
>
> > + /*
> > + * six 0s are appended to the lsb of each threshold value
> > + * internally in h/w.
> > + * Only 8 bits are allowed for programming RcBufThreshold
> > + */
> > + vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
> > + }
> > +
> > + /*
> > + * For 6bpp, RC Buffer threshold 12 and 13 need a different value
> > + * as per C Model
> > + */
> > + if (vdsc_cfg->bits_per_pixel == 6 << 4) {
> > + vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
> > + vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
> > + }
> > +}
> > +EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
> > +
> > /**
> > * drm_dsc_compute_rc_parameters() - Write rate control
> > * parameters to the dsc configuration defined in
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index d080741fd0b3..b4faab4c8fb3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -36,12 +36,6 @@ enum COLUMN_INDEX_BPC {
> > MAX_COLUMN_INDEX
> > };
> >
> > -/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
> > -static const u16 rc_buf_thresh[] = {
> > - 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
> > - 7744, 7872, 8000, 8064
> > -};
> > -
> > struct rc_parameters {
> > u16 initial_xmit_delay;
> > u8 first_line_bpg_offset;
> > @@ -474,23 +468,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> > vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
> > vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
> >
> > - for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
> > - /*
> > - * six 0s are appended to the lsb of each threshold value
> > - * internally in h/w.
> > - * Only 8 bits are allowed for programming RcBufThreshold
> > - */
> > - vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
> > - }
> > -
> > - /*
> > - * For 6bpp, RC Buffer threshold 12 and 13 need a different value
> > - * as per C Model
> > - */
> > - if (compressed_bpp == 6) {
> > - vdsc_cfg->rc_buf_thresh[12] = 0x7C;
> > - vdsc_cfg->rc_buf_thresh[13] = 0x7D;
> > - }
> > + drm_dsc_set_rc_buf_thresh(vdsc_cfg);
> >
> > /*
> > * From XE_LPD onwards we supports compression bpps in steps of 1
> > diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> > index 8b41edbbabab..706ba1d34742 100644
> > --- a/include/drm/display/drm_dsc_helper.h
> > +++ b/include/drm/display/drm_dsc_helper.h
> > @@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
> > int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> > void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> > const struct drm_dsc_config *dsc_cfg);
> > +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> > int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
> >
> > #endif /* _DRM_DSC_HELPER_H_ */
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH 02/10] drm/i915/dsc: move rc_buf_thresh values to common helper
@ 2023-02-28 12:35 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 12:35 UTC (permalink / raw)
To: Jani Nikula
Cc: linux-arm-msm, intel-gfx, Abhinav Kumar, dri-devel,
Daniel Vetter, Rodrigo Vivi, Marijn Suijten, freedreno,
David Airlie
On Tue, 28 Feb 2023 at 14:25, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>
> On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> > The rc_buf_thresh values are common to all DSC implementations. Move
> > them to the common helper together with the code to propagage them to
> > the drm_dsc_config.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > drivers/gpu/drm/display/drm_dsc_helper.c | 37 +++++++++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +--------------
> > include/drm/display/drm_dsc_helper.h | 1 +
> > 3 files changed, 39 insertions(+), 23 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> > index c869c6e51e2b..ab8679c158b5 100644
> > --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> > +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> > @@ -270,6 +270,43 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
> > }
> > EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
> >
> > +/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
> > +const u16 drm_dsc_rc_buf_thresh[] = {
> > + 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
> > + 7744, 7872, 8000, 8064
> > +};
> > +EXPORT_SYMBOL(drm_dsc_rc_buf_thresh);
>
> This needs to be static, without exports.
Exported this to let other drivers use it, while skipping the
drm_dsc_set_rc_buf_thresh(). For example amdgpu driver sets buffer
thresholds on the interim structure, so the helper is not directly
applicable. See _do_calc_rc_params().
>
> > +
> > +/**
> > + * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
> > + * in accordance with the DSC 1.2 specification.
> > + *
> > + * @vdsc_cfg: DSC Configuration data partially filled by driver
> > + */
> > +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
> > +{
> > + int i = 0;
>
> Unnecessary initialization.
My bad.
>
> > +
> > + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
>
> Please use ARRAY_SIZE(). Maybe add BUILD_BUG_ON() for DSC_NUM_BUF_RANGES
> vs. ARRAY_SIZE(). (Yes, we should've used ARRAY_SIZE() in i915.)
Ack
>
> > + /*
> > + * six 0s are appended to the lsb of each threshold value
> > + * internally in h/w.
> > + * Only 8 bits are allowed for programming RcBufThreshold
> > + */
> > + vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
> > + }
> > +
> > + /*
> > + * For 6bpp, RC Buffer threshold 12 and 13 need a different value
> > + * as per C Model
> > + */
> > + if (vdsc_cfg->bits_per_pixel == 6 << 4) {
> > + vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
> > + vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
> > + }
> > +}
> > +EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
> > +
> > /**
> > * drm_dsc_compute_rc_parameters() - Write rate control
> > * parameters to the dsc configuration defined in
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index d080741fd0b3..b4faab4c8fb3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -36,12 +36,6 @@ enum COLUMN_INDEX_BPC {
> > MAX_COLUMN_INDEX
> > };
> >
> > -/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
> > -static const u16 rc_buf_thresh[] = {
> > - 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
> > - 7744, 7872, 8000, 8064
> > -};
> > -
> > struct rc_parameters {
> > u16 initial_xmit_delay;
> > u8 first_line_bpg_offset;
> > @@ -474,23 +468,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> > vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
> > vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
> >
> > - for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
> > - /*
> > - * six 0s are appended to the lsb of each threshold value
> > - * internally in h/w.
> > - * Only 8 bits are allowed for programming RcBufThreshold
> > - */
> > - vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
> > - }
> > -
> > - /*
> > - * For 6bpp, RC Buffer threshold 12 and 13 need a different value
> > - * as per C Model
> > - */
> > - if (compressed_bpp == 6) {
> > - vdsc_cfg->rc_buf_thresh[12] = 0x7C;
> > - vdsc_cfg->rc_buf_thresh[13] = 0x7D;
> > - }
> > + drm_dsc_set_rc_buf_thresh(vdsc_cfg);
> >
> > /*
> > * From XE_LPD onwards we supports compression bpps in steps of 1
> > diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> > index 8b41edbbabab..706ba1d34742 100644
> > --- a/include/drm/display/drm_dsc_helper.h
> > +++ b/include/drm/display/drm_dsc_helper.h
> > @@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
> > int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> > void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> > const struct drm_dsc_config *dsc_cfg);
> > +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> > int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
> >
> > #endif /* _DRM_DSC_HELPER_H_ */
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 02/10] drm/i915/dsc: move rc_buf_thresh values to common helper
2023-02-28 12:35 ` Dmitry Baryshkov
(?)
@ 2023-02-28 12:49 ` Jani Nikula
-1 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 12:49 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: David Airlie, Daniel Vetter, Joonas Lahtinen, Rodrigo Vivi,
Tvrtko Ursulin, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, Ville Syrjälä,
dri-devel, intel-gfx, linux-arm-msm, freedreno
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> On Tue, 28 Feb 2023 at 14:25, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>
>> On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
>> > The rc_buf_thresh values are common to all DSC implementations. Move
>> > them to the common helper together with the code to propagage them to
>> > the drm_dsc_config.
>> >
>> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> > ---
>> > drivers/gpu/drm/display/drm_dsc_helper.c | 37 +++++++++++++++++++++++
>> > drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +--------------
>> > include/drm/display/drm_dsc_helper.h | 1 +
>> > 3 files changed, 39 insertions(+), 23 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
>> > index c869c6e51e2b..ab8679c158b5 100644
>> > --- a/drivers/gpu/drm/display/drm_dsc_helper.c
>> > +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
>> > @@ -270,6 +270,43 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
>> > }
>> > EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
>> >
>> > +/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
>> > +const u16 drm_dsc_rc_buf_thresh[] = {
>> > + 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
>> > + 7744, 7872, 8000, 8064
>> > +};
>> > +EXPORT_SYMBOL(drm_dsc_rc_buf_thresh);
>>
>> This needs to be static, without exports.
>
> Exported this to let other drivers use it, while skipping the
> drm_dsc_set_rc_buf_thresh(). For example amdgpu driver sets buffer
> thresholds on the interim structure, so the helper is not directly
> applicable. See _do_calc_rc_params().
Regardless, I'm still saying don't do that.
Data is not an interface.
If you make it easy to just use the data, nobody will ever fix their
drivers to use proper interfaces, and you'll lock yourself to a
particular representation of the data even though it's supposed to be a
hidden implementation detail.
BR,
Jani.
>
>>
>> > +
>> > +/**
>> > + * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
>> > + * in accordance with the DSC 1.2 specification.
>> > + *
>> > + * @vdsc_cfg: DSC Configuration data partially filled by driver
>> > + */
>> > +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
>> > +{
>> > + int i = 0;
>>
>> Unnecessary initialization.
>
> My bad.
>
>>
>> > +
>> > + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
>>
>> Please use ARRAY_SIZE(). Maybe add BUILD_BUG_ON() for DSC_NUM_BUF_RANGES
>> vs. ARRAY_SIZE(). (Yes, we should've used ARRAY_SIZE() in i915.)
>
> Ack
>
>>
>> > + /*
>> > + * six 0s are appended to the lsb of each threshold value
>> > + * internally in h/w.
>> > + * Only 8 bits are allowed for programming RcBufThreshold
>> > + */
>> > + vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
>> > + }
>> > +
>> > + /*
>> > + * For 6bpp, RC Buffer threshold 12 and 13 need a different value
>> > + * as per C Model
>> > + */
>> > + if (vdsc_cfg->bits_per_pixel == 6 << 4) {
>> > + vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
>> > + vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
>> > + }
>> > +}
>> > +EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
>> > +
>> > /**
>> > * drm_dsc_compute_rc_parameters() - Write rate control
>> > * parameters to the dsc configuration defined in
>> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > index d080741fd0b3..b4faab4c8fb3 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > @@ -36,12 +36,6 @@ enum COLUMN_INDEX_BPC {
>> > MAX_COLUMN_INDEX
>> > };
>> >
>> > -/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
>> > -static const u16 rc_buf_thresh[] = {
>> > - 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
>> > - 7744, 7872, 8000, 8064
>> > -};
>> > -
>> > struct rc_parameters {
>> > u16 initial_xmit_delay;
>> > u8 first_line_bpg_offset;
>> > @@ -474,23 +468,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
>> > vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
>> > vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
>> >
>> > - for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
>> > - /*
>> > - * six 0s are appended to the lsb of each threshold value
>> > - * internally in h/w.
>> > - * Only 8 bits are allowed for programming RcBufThreshold
>> > - */
>> > - vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
>> > - }
>> > -
>> > - /*
>> > - * For 6bpp, RC Buffer threshold 12 and 13 need a different value
>> > - * as per C Model
>> > - */
>> > - if (compressed_bpp == 6) {
>> > - vdsc_cfg->rc_buf_thresh[12] = 0x7C;
>> > - vdsc_cfg->rc_buf_thresh[13] = 0x7D;
>> > - }
>> > + drm_dsc_set_rc_buf_thresh(vdsc_cfg);
>> >
>> > /*
>> > * From XE_LPD onwards we supports compression bpps in steps of 1
>> > diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
>> > index 8b41edbbabab..706ba1d34742 100644
>> > --- a/include/drm/display/drm_dsc_helper.h
>> > +++ b/include/drm/display/drm_dsc_helper.h
>> > @@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
>> > int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
>> > void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
>> > const struct drm_dsc_config *dsc_cfg);
>> > +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
>> > int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>> >
>> > #endif /* _DRM_DSC_HELPER_H_ */
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 02/10] drm/i915/dsc: move rc_buf_thresh values to common helper
@ 2023-02-28 12:49 ` Jani Nikula
0 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 12:49 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: linux-arm-msm, Tvrtko Ursulin, Sean Paul, intel-gfx,
Abhinav Kumar, dri-devel, Rodrigo Vivi, Marijn Suijten,
freedreno
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> On Tue, 28 Feb 2023 at 14:25, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>
>> On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
>> > The rc_buf_thresh values are common to all DSC implementations. Move
>> > them to the common helper together with the code to propagage them to
>> > the drm_dsc_config.
>> >
>> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> > ---
>> > drivers/gpu/drm/display/drm_dsc_helper.c | 37 +++++++++++++++++++++++
>> > drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +--------------
>> > include/drm/display/drm_dsc_helper.h | 1 +
>> > 3 files changed, 39 insertions(+), 23 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
>> > index c869c6e51e2b..ab8679c158b5 100644
>> > --- a/drivers/gpu/drm/display/drm_dsc_helper.c
>> > +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
>> > @@ -270,6 +270,43 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
>> > }
>> > EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
>> >
>> > +/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
>> > +const u16 drm_dsc_rc_buf_thresh[] = {
>> > + 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
>> > + 7744, 7872, 8000, 8064
>> > +};
>> > +EXPORT_SYMBOL(drm_dsc_rc_buf_thresh);
>>
>> This needs to be static, without exports.
>
> Exported this to let other drivers use it, while skipping the
> drm_dsc_set_rc_buf_thresh(). For example amdgpu driver sets buffer
> thresholds on the interim structure, so the helper is not directly
> applicable. See _do_calc_rc_params().
Regardless, I'm still saying don't do that.
Data is not an interface.
If you make it easy to just use the data, nobody will ever fix their
drivers to use proper interfaces, and you'll lock yourself to a
particular representation of the data even though it's supposed to be a
hidden implementation detail.
BR,
Jani.
>
>>
>> > +
>> > +/**
>> > + * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
>> > + * in accordance with the DSC 1.2 specification.
>> > + *
>> > + * @vdsc_cfg: DSC Configuration data partially filled by driver
>> > + */
>> > +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
>> > +{
>> > + int i = 0;
>>
>> Unnecessary initialization.
>
> My bad.
>
>>
>> > +
>> > + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
>>
>> Please use ARRAY_SIZE(). Maybe add BUILD_BUG_ON() for DSC_NUM_BUF_RANGES
>> vs. ARRAY_SIZE(). (Yes, we should've used ARRAY_SIZE() in i915.)
>
> Ack
>
>>
>> > + /*
>> > + * six 0s are appended to the lsb of each threshold value
>> > + * internally in h/w.
>> > + * Only 8 bits are allowed for programming RcBufThreshold
>> > + */
>> > + vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
>> > + }
>> > +
>> > + /*
>> > + * For 6bpp, RC Buffer threshold 12 and 13 need a different value
>> > + * as per C Model
>> > + */
>> > + if (vdsc_cfg->bits_per_pixel == 6 << 4) {
>> > + vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
>> > + vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
>> > + }
>> > +}
>> > +EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
>> > +
>> > /**
>> > * drm_dsc_compute_rc_parameters() - Write rate control
>> > * parameters to the dsc configuration defined in
>> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > index d080741fd0b3..b4faab4c8fb3 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > @@ -36,12 +36,6 @@ enum COLUMN_INDEX_BPC {
>> > MAX_COLUMN_INDEX
>> > };
>> >
>> > -/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
>> > -static const u16 rc_buf_thresh[] = {
>> > - 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
>> > - 7744, 7872, 8000, 8064
>> > -};
>> > -
>> > struct rc_parameters {
>> > u16 initial_xmit_delay;
>> > u8 first_line_bpg_offset;
>> > @@ -474,23 +468,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
>> > vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
>> > vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
>> >
>> > - for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
>> > - /*
>> > - * six 0s are appended to the lsb of each threshold value
>> > - * internally in h/w.
>> > - * Only 8 bits are allowed for programming RcBufThreshold
>> > - */
>> > - vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
>> > - }
>> > -
>> > - /*
>> > - * For 6bpp, RC Buffer threshold 12 and 13 need a different value
>> > - * as per C Model
>> > - */
>> > - if (compressed_bpp == 6) {
>> > - vdsc_cfg->rc_buf_thresh[12] = 0x7C;
>> > - vdsc_cfg->rc_buf_thresh[13] = 0x7D;
>> > - }
>> > + drm_dsc_set_rc_buf_thresh(vdsc_cfg);
>> >
>> > /*
>> > * From XE_LPD onwards we supports compression bpps in steps of 1
>> > diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
>> > index 8b41edbbabab..706ba1d34742 100644
>> > --- a/include/drm/display/drm_dsc_helper.h
>> > +++ b/include/drm/display/drm_dsc_helper.h
>> > @@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
>> > int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
>> > void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
>> > const struct drm_dsc_config *dsc_cfg);
>> > +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
>> > int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>> >
>> > #endif /* _DRM_DSC_HELPER_H_ */
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH 02/10] drm/i915/dsc: move rc_buf_thresh values to common helper
@ 2023-02-28 12:49 ` Jani Nikula
0 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 12:49 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: linux-arm-msm, intel-gfx, Abhinav Kumar, dri-devel,
Daniel Vetter, Rodrigo Vivi, Marijn Suijten, freedreno,
David Airlie
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> On Tue, 28 Feb 2023 at 14:25, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>
>> On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
>> > The rc_buf_thresh values are common to all DSC implementations. Move
>> > them to the common helper together with the code to propagage them to
>> > the drm_dsc_config.
>> >
>> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> > ---
>> > drivers/gpu/drm/display/drm_dsc_helper.c | 37 +++++++++++++++++++++++
>> > drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +--------------
>> > include/drm/display/drm_dsc_helper.h | 1 +
>> > 3 files changed, 39 insertions(+), 23 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
>> > index c869c6e51e2b..ab8679c158b5 100644
>> > --- a/drivers/gpu/drm/display/drm_dsc_helper.c
>> > +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
>> > @@ -270,6 +270,43 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
>> > }
>> > EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
>> >
>> > +/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
>> > +const u16 drm_dsc_rc_buf_thresh[] = {
>> > + 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
>> > + 7744, 7872, 8000, 8064
>> > +};
>> > +EXPORT_SYMBOL(drm_dsc_rc_buf_thresh);
>>
>> This needs to be static, without exports.
>
> Exported this to let other drivers use it, while skipping the
> drm_dsc_set_rc_buf_thresh(). For example amdgpu driver sets buffer
> thresholds on the interim structure, so the helper is not directly
> applicable. See _do_calc_rc_params().
Regardless, I'm still saying don't do that.
Data is not an interface.
If you make it easy to just use the data, nobody will ever fix their
drivers to use proper interfaces, and you'll lock yourself to a
particular representation of the data even though it's supposed to be a
hidden implementation detail.
BR,
Jani.
>
>>
>> > +
>> > +/**
>> > + * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
>> > + * in accordance with the DSC 1.2 specification.
>> > + *
>> > + * @vdsc_cfg: DSC Configuration data partially filled by driver
>> > + */
>> > +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
>> > +{
>> > + int i = 0;
>>
>> Unnecessary initialization.
>
> My bad.
>
>>
>> > +
>> > + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
>>
>> Please use ARRAY_SIZE(). Maybe add BUILD_BUG_ON() for DSC_NUM_BUF_RANGES
>> vs. ARRAY_SIZE(). (Yes, we should've used ARRAY_SIZE() in i915.)
>
> Ack
>
>>
>> > + /*
>> > + * six 0s are appended to the lsb of each threshold value
>> > + * internally in h/w.
>> > + * Only 8 bits are allowed for programming RcBufThreshold
>> > + */
>> > + vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
>> > + }
>> > +
>> > + /*
>> > + * For 6bpp, RC Buffer threshold 12 and 13 need a different value
>> > + * as per C Model
>> > + */
>> > + if (vdsc_cfg->bits_per_pixel == 6 << 4) {
>> > + vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
>> > + vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
>> > + }
>> > +}
>> > +EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
>> > +
>> > /**
>> > * drm_dsc_compute_rc_parameters() - Write rate control
>> > * parameters to the dsc configuration defined in
>> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > index d080741fd0b3..b4faab4c8fb3 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > @@ -36,12 +36,6 @@ enum COLUMN_INDEX_BPC {
>> > MAX_COLUMN_INDEX
>> > };
>> >
>> > -/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
>> > -static const u16 rc_buf_thresh[] = {
>> > - 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
>> > - 7744, 7872, 8000, 8064
>> > -};
>> > -
>> > struct rc_parameters {
>> > u16 initial_xmit_delay;
>> > u8 first_line_bpg_offset;
>> > @@ -474,23 +468,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
>> > vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
>> > vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
>> >
>> > - for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
>> > - /*
>> > - * six 0s are appended to the lsb of each threshold value
>> > - * internally in h/w.
>> > - * Only 8 bits are allowed for programming RcBufThreshold
>> > - */
>> > - vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
>> > - }
>> > -
>> > - /*
>> > - * For 6bpp, RC Buffer threshold 12 and 13 need a different value
>> > - * as per C Model
>> > - */
>> > - if (compressed_bpp == 6) {
>> > - vdsc_cfg->rc_buf_thresh[12] = 0x7C;
>> > - vdsc_cfg->rc_buf_thresh[13] = 0x7D;
>> > - }
>> > + drm_dsc_set_rc_buf_thresh(vdsc_cfg);
>> >
>> > /*
>> > * From XE_LPD onwards we supports compression bpps in steps of 1
>> > diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
>> > index 8b41edbbabab..706ba1d34742 100644
>> > --- a/include/drm/display/drm_dsc_helper.h
>> > +++ b/include/drm/display/drm_dsc_helper.h
>> > @@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
>> > int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
>> > void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
>> > const struct drm_dsc_config *dsc_cfg);
>> > +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
>> > int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>> >
>> > #endif /* _DRM_DSC_HELPER_H_ */
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: move DSC RC tables to drm_dsc_helper.c
2023-02-28 11:33 ` Dmitry Baryshkov
` (12 preceding siblings ...)
(?)
@ 2023-02-28 12:57 ` Patchwork
-1 siblings, 0 replies; 80+ messages in thread
From: Patchwork @ 2023-02-28 12:57 UTC (permalink / raw)
To: Dmitry Baryshkov; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8638 bytes --]
== Series Details ==
Series: drm/i915: move DSC RC tables to drm_dsc_helper.c
URL : https://patchwork.freedesktop.org/series/114473/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12790_full -> Patchwork_114473v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/index.html
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_114473v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_close_race@multigpu-basic-threads:
- shard-tglu-9: NOTRUN -> [SKIP][1] ([i915#7697])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/shard-tglu-9/igt@gem_close_race@multigpu-basic-threads.html
* igt@gem_eio@in-flight-1us:
- shard-tglu-9: NOTRUN -> [ABORT][2] ([i915#8233]) +1 similar issue
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/shard-tglu-9/igt@gem_eio@in-flight-1us.html
* igt@gem_huc_copy@huc-copy:
- shard-tglu-9: NOTRUN -> [SKIP][3] ([i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/shard-tglu-9/igt@gem_huc_copy@huc-copy.html
* igt@gem_userptr_blits@vma-merge:
- shard-tglu-9: NOTRUN -> [FAIL][4] ([i915#3318])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/shard-tglu-9/igt@gem_userptr_blits@vma-merge.html
* igt@kms_async_flips@crc:
- shard-tglu-9: NOTRUN -> [SKIP][5] ([i915#1845]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/shard-tglu-9/igt@kms_async_flips@crc.html
* igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-tglu-9: NOTRUN -> [SKIP][6] ([i915#1845] / [i915#7651]) +8 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/shard-tglu-9/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_cdclk@plane-scaling:
- shard-tglu-9: NOTRUN -> [SKIP][7] ([i915#3742])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/shard-tglu-9/igt@kms_cdclk@plane-scaling.html
* igt@kms_chamelium_color@ctm-max:
- shard-tglu-9: NOTRUN -> [SKIP][8] ([fdo#111827])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/shard-tglu-9/igt@kms_chamelium_color@ctm-max.html
* igt@kms_chamelium_hpd@dp-hpd-after-suspend:
- shard-tglu-9: NOTRUN -> [SKIP][9] ([i915#7828]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/shard-tglu-9/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-tglu-9: NOTRUN -> [SKIP][10] ([fdo#109274] / [i915#3637])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/shard-tglu-9/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_flip@blocking-wf_vblank:
- shard-tglu-9: NOTRUN -> [SKIP][11] ([i915#3637])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/shard-tglu-9/igt@kms_flip@blocking-wf_vblank.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
- shard-tglu-9: NOTRUN -> [SKIP][12] ([i915#3555])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/shard-tglu-9/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt:
- shard-tglu-9: NOTRUN -> [SKIP][13] ([i915#1849]) +10 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/shard-tglu-9/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_plane_alpha_blend@alpha-transparent-fb:
- shard-tglu-9: NOTRUN -> [SKIP][14] ([i915#7128] / [i915#7294])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/shard-tglu-9/igt@kms_plane_alpha_blend@alpha-transparent-fb.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25:
- shard-tglu-9: NOTRUN -> [SKIP][15] ([i915#6953] / [i915#8152])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/shard-tglu-9/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-tglu-9: NOTRUN -> [SKIP][16] ([fdo#110189])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/shard-tglu-9/igt@kms_psr@psr2_cursor_plane_move.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
[i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#8152]: https://gitlab.freedesktop.org/drm/intel/issues/8152
[i915#8233]: https://gitlab.freedesktop.org/drm/intel/issues/8233
Build changes
-------------
* Linux: CI_DRM_12790 -> Patchwork_114473v1
CI-20190529: 20190529
CI_DRM_12790: 92b7ba2b502495a393b6db904061b6938a09db17 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7175: e825eb183729902489365e56bd99f15af2aa3316 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_114473v1: 92b7ba2b502495a393b6db904061b6938a09db17 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114473v1/index.html
[-- Attachment #2: Type: text/html, Size: 7663 bytes --]
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 02/10] drm/i915/dsc: move rc_buf_thresh values to common helper
2023-02-28 12:49 ` Jani Nikula
(?)
@ 2023-02-28 13:02 ` Dmitry Baryshkov
-1 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 13:02 UTC (permalink / raw)
To: Jani Nikula
Cc: David Airlie, Daniel Vetter, Joonas Lahtinen, Rodrigo Vivi,
Tvrtko Ursulin, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, Ville Syrjälä,
dri-devel, intel-gfx, linux-arm-msm, freedreno
On 28/02/2023 14:49, Jani Nikula wrote:
> On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
>> On Tue, 28 Feb 2023 at 14:25, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>>
>>> On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
>>>> The rc_buf_thresh values are common to all DSC implementations. Move
>>>> them to the common helper together with the code to propagage them to
>>>> the drm_dsc_config.
>>>>
>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>> ---
>>>> drivers/gpu/drm/display/drm_dsc_helper.c | 37 +++++++++++++++++++++++
>>>> drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +--------------
>>>> include/drm/display/drm_dsc_helper.h | 1 +
>>>> 3 files changed, 39 insertions(+), 23 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
>>>> index c869c6e51e2b..ab8679c158b5 100644
>>>> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
>>>> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
>>>> @@ -270,6 +270,43 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
>>>> }
>>>> EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
>>>>
>>>> +/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
>>>> +const u16 drm_dsc_rc_buf_thresh[] = {
>>>> + 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
>>>> + 7744, 7872, 8000, 8064
>>>> +};
>>>> +EXPORT_SYMBOL(drm_dsc_rc_buf_thresh);
>>>
>>> This needs to be static, without exports.
>>
>> Exported this to let other drivers use it, while skipping the
>> drm_dsc_set_rc_buf_thresh(). For example amdgpu driver sets buffer
>> thresholds on the interim structure, so the helper is not directly
>> applicable. See _do_calc_rc_params().
>
> Regardless, I'm still saying don't do that.
>
> Data is not an interface.
>
> If you make it easy to just use the data, nobody will ever fix their
> drivers to use proper interfaces, and you'll lock yourself to a
> particular representation of the data even though it's supposed to be a
> hidden implementation detail.
Yes, I usually do not export data, exactly for these reasons. I could
have argued here that the data is constant here, etc. etc.
However let's stop caring about other drivers. I'll drop the export for v2.
>
>
> BR,
> Jani.
>
>
>>
>>>
>>>> +
>>>> +/**
>>>> + * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
>>>> + * in accordance with the DSC 1.2 specification.
>>>> + *
>>>> + * @vdsc_cfg: DSC Configuration data partially filled by driver
>>>> + */
>>>> +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
>>>> +{
>>>> + int i = 0;
>>>
>>> Unnecessary initialization.
>>
>> My bad.
>>
>>>
>>>> +
>>>> + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
>>>
>>> Please use ARRAY_SIZE(). Maybe add BUILD_BUG_ON() for DSC_NUM_BUF_RANGES
>>> vs. ARRAY_SIZE(). (Yes, we should've used ARRAY_SIZE() in i915.)
>>
>> Ack
>>
>>>
>>>> + /*
>>>> + * six 0s are appended to the lsb of each threshold value
>>>> + * internally in h/w.
>>>> + * Only 8 bits are allowed for programming RcBufThreshold
>>>> + */
>>>> + vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
>>>> + }
>>>> +
>>>> + /*
>>>> + * For 6bpp, RC Buffer threshold 12 and 13 need a different value
>>>> + * as per C Model
>>>> + */
>>>> + if (vdsc_cfg->bits_per_pixel == 6 << 4) {
>>>> + vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
>>>> + vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
>>>> + }
>>>> +}
>>>> +EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
>>>> +
>>>> /**
>>>> * drm_dsc_compute_rc_parameters() - Write rate control
>>>> * parameters to the dsc configuration defined in
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>>>> index d080741fd0b3..b4faab4c8fb3 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>>>> @@ -36,12 +36,6 @@ enum COLUMN_INDEX_BPC {
>>>> MAX_COLUMN_INDEX
>>>> };
>>>>
>>>> -/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
>>>> -static const u16 rc_buf_thresh[] = {
>>>> - 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
>>>> - 7744, 7872, 8000, 8064
>>>> -};
>>>> -
>>>> struct rc_parameters {
>>>> u16 initial_xmit_delay;
>>>> u8 first_line_bpg_offset;
>>>> @@ -474,23 +468,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
>>>> vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
>>>> vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
>>>>
>>>> - for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
>>>> - /*
>>>> - * six 0s are appended to the lsb of each threshold value
>>>> - * internally in h/w.
>>>> - * Only 8 bits are allowed for programming RcBufThreshold
>>>> - */
>>>> - vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
>>>> - }
>>>> -
>>>> - /*
>>>> - * For 6bpp, RC Buffer threshold 12 and 13 need a different value
>>>> - * as per C Model
>>>> - */
>>>> - if (compressed_bpp == 6) {
>>>> - vdsc_cfg->rc_buf_thresh[12] = 0x7C;
>>>> - vdsc_cfg->rc_buf_thresh[13] = 0x7D;
>>>> - }
>>>> + drm_dsc_set_rc_buf_thresh(vdsc_cfg);
>>>>
>>>> /*
>>>> * From XE_LPD onwards we supports compression bpps in steps of 1
>>>> diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
>>>> index 8b41edbbabab..706ba1d34742 100644
>>>> --- a/include/drm/display/drm_dsc_helper.h
>>>> +++ b/include/drm/display/drm_dsc_helper.h
>>>> @@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
>>>> int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
>>>> void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
>>>> const struct drm_dsc_config *dsc_cfg);
>>>> +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
>>>> int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>>>>
>>>> #endif /* _DRM_DSC_HELPER_H_ */
>>>
>>> --
>>> Jani Nikula, Intel Open Source Graphics Center
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 02/10] drm/i915/dsc: move rc_buf_thresh values to common helper
@ 2023-02-28 13:02 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 13:02 UTC (permalink / raw)
To: Jani Nikula
Cc: linux-arm-msm, Tvrtko Ursulin, Sean Paul, intel-gfx,
Abhinav Kumar, dri-devel, Rodrigo Vivi, Marijn Suijten,
freedreno
On 28/02/2023 14:49, Jani Nikula wrote:
> On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
>> On Tue, 28 Feb 2023 at 14:25, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>>
>>> On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
>>>> The rc_buf_thresh values are common to all DSC implementations. Move
>>>> them to the common helper together with the code to propagage them to
>>>> the drm_dsc_config.
>>>>
>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>> ---
>>>> drivers/gpu/drm/display/drm_dsc_helper.c | 37 +++++++++++++++++++++++
>>>> drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +--------------
>>>> include/drm/display/drm_dsc_helper.h | 1 +
>>>> 3 files changed, 39 insertions(+), 23 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
>>>> index c869c6e51e2b..ab8679c158b5 100644
>>>> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
>>>> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
>>>> @@ -270,6 +270,43 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
>>>> }
>>>> EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
>>>>
>>>> +/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
>>>> +const u16 drm_dsc_rc_buf_thresh[] = {
>>>> + 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
>>>> + 7744, 7872, 8000, 8064
>>>> +};
>>>> +EXPORT_SYMBOL(drm_dsc_rc_buf_thresh);
>>>
>>> This needs to be static, without exports.
>>
>> Exported this to let other drivers use it, while skipping the
>> drm_dsc_set_rc_buf_thresh(). For example amdgpu driver sets buffer
>> thresholds on the interim structure, so the helper is not directly
>> applicable. See _do_calc_rc_params().
>
> Regardless, I'm still saying don't do that.
>
> Data is not an interface.
>
> If you make it easy to just use the data, nobody will ever fix their
> drivers to use proper interfaces, and you'll lock yourself to a
> particular representation of the data even though it's supposed to be a
> hidden implementation detail.
Yes, I usually do not export data, exactly for these reasons. I could
have argued here that the data is constant here, etc. etc.
However let's stop caring about other drivers. I'll drop the export for v2.
>
>
> BR,
> Jani.
>
>
>>
>>>
>>>> +
>>>> +/**
>>>> + * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
>>>> + * in accordance with the DSC 1.2 specification.
>>>> + *
>>>> + * @vdsc_cfg: DSC Configuration data partially filled by driver
>>>> + */
>>>> +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
>>>> +{
>>>> + int i = 0;
>>>
>>> Unnecessary initialization.
>>
>> My bad.
>>
>>>
>>>> +
>>>> + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
>>>
>>> Please use ARRAY_SIZE(). Maybe add BUILD_BUG_ON() for DSC_NUM_BUF_RANGES
>>> vs. ARRAY_SIZE(). (Yes, we should've used ARRAY_SIZE() in i915.)
>>
>> Ack
>>
>>>
>>>> + /*
>>>> + * six 0s are appended to the lsb of each threshold value
>>>> + * internally in h/w.
>>>> + * Only 8 bits are allowed for programming RcBufThreshold
>>>> + */
>>>> + vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
>>>> + }
>>>> +
>>>> + /*
>>>> + * For 6bpp, RC Buffer threshold 12 and 13 need a different value
>>>> + * as per C Model
>>>> + */
>>>> + if (vdsc_cfg->bits_per_pixel == 6 << 4) {
>>>> + vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
>>>> + vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
>>>> + }
>>>> +}
>>>> +EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
>>>> +
>>>> /**
>>>> * drm_dsc_compute_rc_parameters() - Write rate control
>>>> * parameters to the dsc configuration defined in
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>>>> index d080741fd0b3..b4faab4c8fb3 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>>>> @@ -36,12 +36,6 @@ enum COLUMN_INDEX_BPC {
>>>> MAX_COLUMN_INDEX
>>>> };
>>>>
>>>> -/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
>>>> -static const u16 rc_buf_thresh[] = {
>>>> - 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
>>>> - 7744, 7872, 8000, 8064
>>>> -};
>>>> -
>>>> struct rc_parameters {
>>>> u16 initial_xmit_delay;
>>>> u8 first_line_bpg_offset;
>>>> @@ -474,23 +468,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
>>>> vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
>>>> vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
>>>>
>>>> - for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
>>>> - /*
>>>> - * six 0s are appended to the lsb of each threshold value
>>>> - * internally in h/w.
>>>> - * Only 8 bits are allowed for programming RcBufThreshold
>>>> - */
>>>> - vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
>>>> - }
>>>> -
>>>> - /*
>>>> - * For 6bpp, RC Buffer threshold 12 and 13 need a different value
>>>> - * as per C Model
>>>> - */
>>>> - if (compressed_bpp == 6) {
>>>> - vdsc_cfg->rc_buf_thresh[12] = 0x7C;
>>>> - vdsc_cfg->rc_buf_thresh[13] = 0x7D;
>>>> - }
>>>> + drm_dsc_set_rc_buf_thresh(vdsc_cfg);
>>>>
>>>> /*
>>>> * From XE_LPD onwards we supports compression bpps in steps of 1
>>>> diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
>>>> index 8b41edbbabab..706ba1d34742 100644
>>>> --- a/include/drm/display/drm_dsc_helper.h
>>>> +++ b/include/drm/display/drm_dsc_helper.h
>>>> @@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
>>>> int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
>>>> void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
>>>> const struct drm_dsc_config *dsc_cfg);
>>>> +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
>>>> int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>>>>
>>>> #endif /* _DRM_DSC_HELPER_H_ */
>>>
>>> --
>>> Jani Nikula, Intel Open Source Graphics Center
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH 02/10] drm/i915/dsc: move rc_buf_thresh values to common helper
@ 2023-02-28 13:02 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 13:02 UTC (permalink / raw)
To: Jani Nikula
Cc: linux-arm-msm, intel-gfx, Abhinav Kumar, dri-devel,
Daniel Vetter, Rodrigo Vivi, Marijn Suijten, freedreno,
David Airlie
On 28/02/2023 14:49, Jani Nikula wrote:
> On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
>> On Tue, 28 Feb 2023 at 14:25, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>>
>>> On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
>>>> The rc_buf_thresh values are common to all DSC implementations. Move
>>>> them to the common helper together with the code to propagage them to
>>>> the drm_dsc_config.
>>>>
>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>> ---
>>>> drivers/gpu/drm/display/drm_dsc_helper.c | 37 +++++++++++++++++++++++
>>>> drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +--------------
>>>> include/drm/display/drm_dsc_helper.h | 1 +
>>>> 3 files changed, 39 insertions(+), 23 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
>>>> index c869c6e51e2b..ab8679c158b5 100644
>>>> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
>>>> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
>>>> @@ -270,6 +270,43 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
>>>> }
>>>> EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
>>>>
>>>> +/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
>>>> +const u16 drm_dsc_rc_buf_thresh[] = {
>>>> + 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
>>>> + 7744, 7872, 8000, 8064
>>>> +};
>>>> +EXPORT_SYMBOL(drm_dsc_rc_buf_thresh);
>>>
>>> This needs to be static, without exports.
>>
>> Exported this to let other drivers use it, while skipping the
>> drm_dsc_set_rc_buf_thresh(). For example amdgpu driver sets buffer
>> thresholds on the interim structure, so the helper is not directly
>> applicable. See _do_calc_rc_params().
>
> Regardless, I'm still saying don't do that.
>
> Data is not an interface.
>
> If you make it easy to just use the data, nobody will ever fix their
> drivers to use proper interfaces, and you'll lock yourself to a
> particular representation of the data even though it's supposed to be a
> hidden implementation detail.
Yes, I usually do not export data, exactly for these reasons. I could
have argued here that the data is constant here, etc. etc.
However let's stop caring about other drivers. I'll drop the export for v2.
>
>
> BR,
> Jani.
>
>
>>
>>>
>>>> +
>>>> +/**
>>>> + * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
>>>> + * in accordance with the DSC 1.2 specification.
>>>> + *
>>>> + * @vdsc_cfg: DSC Configuration data partially filled by driver
>>>> + */
>>>> +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
>>>> +{
>>>> + int i = 0;
>>>
>>> Unnecessary initialization.
>>
>> My bad.
>>
>>>
>>>> +
>>>> + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
>>>
>>> Please use ARRAY_SIZE(). Maybe add BUILD_BUG_ON() for DSC_NUM_BUF_RANGES
>>> vs. ARRAY_SIZE(). (Yes, we should've used ARRAY_SIZE() in i915.)
>>
>> Ack
>>
>>>
>>>> + /*
>>>> + * six 0s are appended to the lsb of each threshold value
>>>> + * internally in h/w.
>>>> + * Only 8 bits are allowed for programming RcBufThreshold
>>>> + */
>>>> + vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
>>>> + }
>>>> +
>>>> + /*
>>>> + * For 6bpp, RC Buffer threshold 12 and 13 need a different value
>>>> + * as per C Model
>>>> + */
>>>> + if (vdsc_cfg->bits_per_pixel == 6 << 4) {
>>>> + vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
>>>> + vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
>>>> + }
>>>> +}
>>>> +EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
>>>> +
>>>> /**
>>>> * drm_dsc_compute_rc_parameters() - Write rate control
>>>> * parameters to the dsc configuration defined in
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>>>> index d080741fd0b3..b4faab4c8fb3 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>>>> @@ -36,12 +36,6 @@ enum COLUMN_INDEX_BPC {
>>>> MAX_COLUMN_INDEX
>>>> };
>>>>
>>>> -/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
>>>> -static const u16 rc_buf_thresh[] = {
>>>> - 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
>>>> - 7744, 7872, 8000, 8064
>>>> -};
>>>> -
>>>> struct rc_parameters {
>>>> u16 initial_xmit_delay;
>>>> u8 first_line_bpg_offset;
>>>> @@ -474,23 +468,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
>>>> vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
>>>> vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
>>>>
>>>> - for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
>>>> - /*
>>>> - * six 0s are appended to the lsb of each threshold value
>>>> - * internally in h/w.
>>>> - * Only 8 bits are allowed for programming RcBufThreshold
>>>> - */
>>>> - vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
>>>> - }
>>>> -
>>>> - /*
>>>> - * For 6bpp, RC Buffer threshold 12 and 13 need a different value
>>>> - * as per C Model
>>>> - */
>>>> - if (compressed_bpp == 6) {
>>>> - vdsc_cfg->rc_buf_thresh[12] = 0x7C;
>>>> - vdsc_cfg->rc_buf_thresh[13] = 0x7D;
>>>> - }
>>>> + drm_dsc_set_rc_buf_thresh(vdsc_cfg);
>>>>
>>>> /*
>>>> * From XE_LPD onwards we supports compression bpps in steps of 1
>>>> diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
>>>> index 8b41edbbabab..706ba1d34742 100644
>>>> --- a/include/drm/display/drm_dsc_helper.h
>>>> +++ b/include/drm/display/drm_dsc_helper.h
>>>> @@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
>>>> int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
>>>> void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
>>>> const struct drm_dsc_config *dsc_cfg);
>>>> +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
>>>> int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>>>>
>>>> #endif /* _DRM_DSC_HELPER_H_ */
>>>
>>> --
>>> Jani Nikula, Intel Open Source Graphics Center
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper
2023-02-28 11:33 ` Dmitry Baryshkov
(?)
@ 2023-02-28 14:49 ` kernel test robot
-1 siblings, 0 replies; 80+ messages in thread
From: kernel test robot @ 2023-02-28 14:49 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Jani Nikula,
Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin, Rob Clark,
Abhinav Kumar, Sean Paul, Marijn Suijten
Cc: oe-kbuild-all, linux-arm-msm, intel-gfx, freedreno, dri-devel
Hi Dmitry,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm/drm-next linus/master v6.2 next-20230228]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Dmitry-Baryshkov/drm-i915-dsc-change-DSC-param-tables-to-follow-the-DSC-model/20230228-193505
base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link: https://lore.kernel.org/r/20230228113342.2051425-4-dmitry.baryshkov%40linaro.org
patch subject: [PATCH 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper
config: ia64-allyesconfig (https://download.01.org/0day-ci/archive/20230228/202302282203.ghUPsryf-lkp@intel.com/config)
compiler: ia64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/ee048cb6c2ec7f7f92bea6b72e8cd3ef9921993e
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Dmitry-Baryshkov/drm-i915-dsc-change-DSC-param-tables-to-follow-the-DSC-model/20230228-193505
git checkout ee048cb6c2ec7f7f92bea6b72e8cd3ef9921993e
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=ia64 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=ia64 SHELL=/bin/bash drivers/gpu/drm/display/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202302282203.ghUPsryf-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/display/drm_dsc_helper.c:635: warning: expecting prototype for drm_dsc_compute_rc_parameters(). Prototype was for drm_dsc_setup_rc_params() instead
vim +635 drivers/gpu/drm/display/drm_dsc_helper.c
627
628 /**
629 * drm_dsc_compute_rc_parameters() - Set parameters and limits for RC model in
630 * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
631 *
632 * @vdsc_cfg: DSC Configuration data partially filled by driver
633 */
634 int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> 635 {
636 const struct rc_parameters *rc_params;
637 int i;
638
639 /* fractional BPP is not supported */
640 if (vdsc_cfg->bits_per_pixel & 0xf)
641 return -EINVAL;
642
643 rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
644 vdsc_cfg->bits_per_component);
645 if (!rc_params)
646 return -EINVAL;
647
648 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
649 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
650 vdsc_cfg->initial_offset = rc_params->initial_offset;
651 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
652 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
653 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
654 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
655
656 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
657 vdsc_cfg->rc_range_params[i].range_min_qp =
658 rc_params->rc_range_params[i].range_min_qp;
659 vdsc_cfg->rc_range_params[i].range_max_qp =
660 rc_params->rc_range_params[i].range_max_qp;
661 /*
662 * Range BPG Offset uses 2's complement and is only a 6 bits. So
663 * mask it to get only 6 bits.
664 */
665 vdsc_cfg->rc_range_params[i].range_bpg_offset =
666 rc_params->rc_range_params[i].range_bpg_offset &
667 DSC_RANGE_BPG_OFFSET_MASK;
668 }
669
670 return 0;
671 }
672 EXPORT_SYMBOL(drm_dsc_setup_rc_params);
673
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper
@ 2023-02-28 14:49 ` kernel test robot
0 siblings, 0 replies; 80+ messages in thread
From: kernel test robot @ 2023-02-28 14:49 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Jani Nikula,
Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin, Rob Clark,
Abhinav Kumar, Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel, oe-kbuild-all
Hi Dmitry,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm/drm-next linus/master v6.2 next-20230228]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Dmitry-Baryshkov/drm-i915-dsc-change-DSC-param-tables-to-follow-the-DSC-model/20230228-193505
base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link: https://lore.kernel.org/r/20230228113342.2051425-4-dmitry.baryshkov%40linaro.org
patch subject: [PATCH 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper
config: ia64-allyesconfig (https://download.01.org/0day-ci/archive/20230228/202302282203.ghUPsryf-lkp@intel.com/config)
compiler: ia64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/ee048cb6c2ec7f7f92bea6b72e8cd3ef9921993e
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Dmitry-Baryshkov/drm-i915-dsc-change-DSC-param-tables-to-follow-the-DSC-model/20230228-193505
git checkout ee048cb6c2ec7f7f92bea6b72e8cd3ef9921993e
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=ia64 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=ia64 SHELL=/bin/bash drivers/gpu/drm/display/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202302282203.ghUPsryf-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/display/drm_dsc_helper.c:635: warning: expecting prototype for drm_dsc_compute_rc_parameters(). Prototype was for drm_dsc_setup_rc_params() instead
vim +635 drivers/gpu/drm/display/drm_dsc_helper.c
627
628 /**
629 * drm_dsc_compute_rc_parameters() - Set parameters and limits for RC model in
630 * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
631 *
632 * @vdsc_cfg: DSC Configuration data partially filled by driver
633 */
634 int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> 635 {
636 const struct rc_parameters *rc_params;
637 int i;
638
639 /* fractional BPP is not supported */
640 if (vdsc_cfg->bits_per_pixel & 0xf)
641 return -EINVAL;
642
643 rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
644 vdsc_cfg->bits_per_component);
645 if (!rc_params)
646 return -EINVAL;
647
648 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
649 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
650 vdsc_cfg->initial_offset = rc_params->initial_offset;
651 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
652 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
653 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
654 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
655
656 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
657 vdsc_cfg->rc_range_params[i].range_min_qp =
658 rc_params->rc_range_params[i].range_min_qp;
659 vdsc_cfg->rc_range_params[i].range_max_qp =
660 rc_params->rc_range_params[i].range_max_qp;
661 /*
662 * Range BPG Offset uses 2's complement and is only a 6 bits. So
663 * mask it to get only 6 bits.
664 */
665 vdsc_cfg->rc_range_params[i].range_bpg_offset =
666 rc_params->rc_range_params[i].range_bpg_offset &
667 DSC_RANGE_BPG_OFFSET_MASK;
668 }
669
670 return 0;
671 }
672 EXPORT_SYMBOL(drm_dsc_setup_rc_params);
673
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper
@ 2023-02-28 14:49 ` kernel test robot
0 siblings, 0 replies; 80+ messages in thread
From: kernel test robot @ 2023-02-28 14:49 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Jani Nikula,
Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin, Rob Clark,
Abhinav Kumar, Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel, oe-kbuild-all
Hi Dmitry,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm/drm-next linus/master v6.2 next-20230228]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Dmitry-Baryshkov/drm-i915-dsc-change-DSC-param-tables-to-follow-the-DSC-model/20230228-193505
base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link: https://lore.kernel.org/r/20230228113342.2051425-4-dmitry.baryshkov%40linaro.org
patch subject: [PATCH 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper
config: ia64-allyesconfig (https://download.01.org/0day-ci/archive/20230228/202302282203.ghUPsryf-lkp@intel.com/config)
compiler: ia64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/ee048cb6c2ec7f7f92bea6b72e8cd3ef9921993e
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Dmitry-Baryshkov/drm-i915-dsc-change-DSC-param-tables-to-follow-the-DSC-model/20230228-193505
git checkout ee048cb6c2ec7f7f92bea6b72e8cd3ef9921993e
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=ia64 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=ia64 SHELL=/bin/bash drivers/gpu/drm/display/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202302282203.ghUPsryf-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/display/drm_dsc_helper.c:635: warning: expecting prototype for drm_dsc_compute_rc_parameters(). Prototype was for drm_dsc_setup_rc_params() instead
vim +635 drivers/gpu/drm/display/drm_dsc_helper.c
627
628 /**
629 * drm_dsc_compute_rc_parameters() - Set parameters and limits for RC model in
630 * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
631 *
632 * @vdsc_cfg: DSC Configuration data partially filled by driver
633 */
634 int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> 635 {
636 const struct rc_parameters *rc_params;
637 int i;
638
639 /* fractional BPP is not supported */
640 if (vdsc_cfg->bits_per_pixel & 0xf)
641 return -EINVAL;
642
643 rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
644 vdsc_cfg->bits_per_component);
645 if (!rc_params)
646 return -EINVAL;
647
648 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
649 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
650 vdsc_cfg->initial_offset = rc_params->initial_offset;
651 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
652 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
653 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
654 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
655
656 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
657 vdsc_cfg->rc_range_params[i].range_min_qp =
658 rc_params->rc_range_params[i].range_min_qp;
659 vdsc_cfg->rc_range_params[i].range_max_qp =
660 rc_params->rc_range_params[i].range_max_qp;
661 /*
662 * Range BPG Offset uses 2's complement and is only a 6 bits. So
663 * mask it to get only 6 bits.
664 */
665 vdsc_cfg->rc_range_params[i].range_bpg_offset =
666 rc_params->rc_range_params[i].range_bpg_offset &
667 DSC_RANGE_BPG_OFFSET_MASK;
668 }
669
670 return 0;
671 }
672 EXPORT_SYMBOL(drm_dsc_setup_rc_params);
673
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper
2023-02-28 11:33 ` Dmitry Baryshkov
(?)
@ 2023-02-28 15:10 ` kernel test robot
-1 siblings, 0 replies; 80+ messages in thread
From: kernel test robot @ 2023-02-28 15:10 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Jani Nikula,
Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin, Rob Clark,
Abhinav Kumar, Sean Paul, Marijn Suijten
Cc: llvm, oe-kbuild-all, linux-arm-msm, intel-gfx, freedreno, dri-devel
Hi Dmitry,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm/drm-next v6.2]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Dmitry-Baryshkov/drm-i915-dsc-change-DSC-param-tables-to-follow-the-DSC-model/20230228-193505
base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link: https://lore.kernel.org/r/20230228113342.2051425-4-dmitry.baryshkov%40linaro.org
patch subject: [PATCH 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper
config: x86_64-randconfig-a002-20230227 (https://download.01.org/0day-ci/archive/20230228/202302282241.qRMAjDx8-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/ee048cb6c2ec7f7f92bea6b72e8cd3ef9921993e
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Dmitry-Baryshkov/drm-i915-dsc-change-DSC-param-tables-to-follow-the-DSC-model/20230228-193505
git checkout ee048cb6c2ec7f7f92bea6b72e8cd3ef9921993e
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/display/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202302282241.qRMAjDx8-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/display/drm_dsc_helper.c:635: warning: expecting prototype for drm_dsc_compute_rc_parameters(). Prototype was for drm_dsc_setup_rc_params() instead
vim +635 drivers/gpu/drm/display/drm_dsc_helper.c
627
628 /**
629 * drm_dsc_compute_rc_parameters() - Set parameters and limits for RC model in
630 * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
631 *
632 * @vdsc_cfg: DSC Configuration data partially filled by driver
633 */
634 int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> 635 {
636 const struct rc_parameters *rc_params;
637 int i;
638
639 /* fractional BPP is not supported */
640 if (vdsc_cfg->bits_per_pixel & 0xf)
641 return -EINVAL;
642
643 rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
644 vdsc_cfg->bits_per_component);
645 if (!rc_params)
646 return -EINVAL;
647
648 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
649 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
650 vdsc_cfg->initial_offset = rc_params->initial_offset;
651 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
652 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
653 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
654 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
655
656 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
657 vdsc_cfg->rc_range_params[i].range_min_qp =
658 rc_params->rc_range_params[i].range_min_qp;
659 vdsc_cfg->rc_range_params[i].range_max_qp =
660 rc_params->rc_range_params[i].range_max_qp;
661 /*
662 * Range BPG Offset uses 2's complement and is only a 6 bits. So
663 * mask it to get only 6 bits.
664 */
665 vdsc_cfg->rc_range_params[i].range_bpg_offset =
666 rc_params->rc_range_params[i].range_bpg_offset &
667 DSC_RANGE_BPG_OFFSET_MASK;
668 }
669
670 return 0;
671 }
672 EXPORT_SYMBOL(drm_dsc_setup_rc_params);
673
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper
@ 2023-02-28 15:10 ` kernel test robot
0 siblings, 0 replies; 80+ messages in thread
From: kernel test robot @ 2023-02-28 15:10 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Jani Nikula,
Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin, Rob Clark,
Abhinav Kumar, Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, llvm, dri-devel, oe-kbuild-all, freedreno
Hi Dmitry,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm/drm-next v6.2]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Dmitry-Baryshkov/drm-i915-dsc-change-DSC-param-tables-to-follow-the-DSC-model/20230228-193505
base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link: https://lore.kernel.org/r/20230228113342.2051425-4-dmitry.baryshkov%40linaro.org
patch subject: [PATCH 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper
config: x86_64-randconfig-a002-20230227 (https://download.01.org/0day-ci/archive/20230228/202302282241.qRMAjDx8-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/ee048cb6c2ec7f7f92bea6b72e8cd3ef9921993e
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Dmitry-Baryshkov/drm-i915-dsc-change-DSC-param-tables-to-follow-the-DSC-model/20230228-193505
git checkout ee048cb6c2ec7f7f92bea6b72e8cd3ef9921993e
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/display/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202302282241.qRMAjDx8-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/display/drm_dsc_helper.c:635: warning: expecting prototype for drm_dsc_compute_rc_parameters(). Prototype was for drm_dsc_setup_rc_params() instead
vim +635 drivers/gpu/drm/display/drm_dsc_helper.c
627
628 /**
629 * drm_dsc_compute_rc_parameters() - Set parameters and limits for RC model in
630 * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
631 *
632 * @vdsc_cfg: DSC Configuration data partially filled by driver
633 */
634 int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> 635 {
636 const struct rc_parameters *rc_params;
637 int i;
638
639 /* fractional BPP is not supported */
640 if (vdsc_cfg->bits_per_pixel & 0xf)
641 return -EINVAL;
642
643 rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
644 vdsc_cfg->bits_per_component);
645 if (!rc_params)
646 return -EINVAL;
647
648 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
649 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
650 vdsc_cfg->initial_offset = rc_params->initial_offset;
651 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
652 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
653 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
654 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
655
656 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
657 vdsc_cfg->rc_range_params[i].range_min_qp =
658 rc_params->rc_range_params[i].range_min_qp;
659 vdsc_cfg->rc_range_params[i].range_max_qp =
660 rc_params->rc_range_params[i].range_max_qp;
661 /*
662 * Range BPG Offset uses 2's complement and is only a 6 bits. So
663 * mask it to get only 6 bits.
664 */
665 vdsc_cfg->rc_range_params[i].range_bpg_offset =
666 rc_params->rc_range_params[i].range_bpg_offset &
667 DSC_RANGE_BPG_OFFSET_MASK;
668 }
669
670 return 0;
671 }
672 EXPORT_SYMBOL(drm_dsc_setup_rc_params);
673
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper
@ 2023-02-28 15:10 ` kernel test robot
0 siblings, 0 replies; 80+ messages in thread
From: kernel test robot @ 2023-02-28 15:10 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Jani Nikula,
Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin, Rob Clark,
Abhinav Kumar, Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, llvm, dri-devel, oe-kbuild-all, freedreno
Hi Dmitry,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm/drm-next v6.2]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Dmitry-Baryshkov/drm-i915-dsc-change-DSC-param-tables-to-follow-the-DSC-model/20230228-193505
base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link: https://lore.kernel.org/r/20230228113342.2051425-4-dmitry.baryshkov%40linaro.org
patch subject: [PATCH 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper
config: x86_64-randconfig-a002-20230227 (https://download.01.org/0day-ci/archive/20230228/202302282241.qRMAjDx8-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/ee048cb6c2ec7f7f92bea6b72e8cd3ef9921993e
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Dmitry-Baryshkov/drm-i915-dsc-change-DSC-param-tables-to-follow-the-DSC-model/20230228-193505
git checkout ee048cb6c2ec7f7f92bea6b72e8cd3ef9921993e
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/display/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202302282241.qRMAjDx8-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/display/drm_dsc_helper.c:635: warning: expecting prototype for drm_dsc_compute_rc_parameters(). Prototype was for drm_dsc_setup_rc_params() instead
vim +635 drivers/gpu/drm/display/drm_dsc_helper.c
627
628 /**
629 * drm_dsc_compute_rc_parameters() - Set parameters and limits for RC model in
630 * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
631 *
632 * @vdsc_cfg: DSC Configuration data partially filled by driver
633 */
634 int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> 635 {
636 const struct rc_parameters *rc_params;
637 int i;
638
639 /* fractional BPP is not supported */
640 if (vdsc_cfg->bits_per_pixel & 0xf)
641 return -EINVAL;
642
643 rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
644 vdsc_cfg->bits_per_component);
645 if (!rc_params)
646 return -EINVAL;
647
648 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
649 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
650 vdsc_cfg->initial_offset = rc_params->initial_offset;
651 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
652 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
653 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
654 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
655
656 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
657 vdsc_cfg->rc_range_params[i].range_min_qp =
658 rc_params->rc_range_params[i].range_min_qp;
659 vdsc_cfg->rc_range_params[i].range_max_qp =
660 rc_params->rc_range_params[i].range_max_qp;
661 /*
662 * Range BPG Offset uses 2's complement and is only a 6 bits. So
663 * mask it to get only 6 bits.
664 */
665 vdsc_cfg->rc_range_params[i].range_bpg_offset =
666 rc_params->rc_range_params[i].range_bpg_offset &
667 DSC_RANGE_BPG_OFFSET_MASK;
668 }
669
670 return 0;
671 }
672 EXPORT_SYMBOL(drm_dsc_setup_rc_params);
673
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 01/10] drm/i915/dsc: change DSC param tables to follow the DSC model
2023-02-28 11:33 ` Dmitry Baryshkov
(?)
@ 2023-02-28 15:56 ` Jani Nikula
-1 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 15:56 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> After cross-checking DSC models (20150914, 20161212, 20210623) change
> values in rc_parameters tables to follow config files present inside
> the DSC model. Handle two places, where i915 tables diverged from the
> model, by patching the rc values in the code.
>
> Note: I left one case uncorrected, 8bpp/10bpc/range_max_qp[0], because
> the table in the VESA DSC 1.1 sets it to 4.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/i915/display/intel_vdsc.c | 18 ++++++++++++++++--
> 1 file changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 207b2a648d32..d080741fd0b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -86,7 +86,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> }
> },
> /* 6BPP/14BPC */
> - { 768, 15, 6144, 15, 25, 23, 27, {
> + { 768, 15, 6144, 15, 25, 23, 23, {
> { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
> { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
> { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
> @@ -115,6 +115,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> },
> /* 8BPP/10BPC */
> { 512, 12, 6144, 7, 16, 15, 15, {
> + /*
> + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> + * VESA DSC 1.1 Table E-5 sets it to 4.
> + */
> { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> @@ -132,7 +136,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> },
> /* 8BPP/14BPC */
> { 512, 12, 6144, 15, 24, 23, 23, {
> - { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
> + { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
> { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
> { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
> @@ -529,6 +533,16 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> DSC_RANGE_BPG_OFFSET_MASK;
> }
>
> + if (DISPLAY_VER(dev_priv) < 13) {
> + if (compressed_bpp == 6 &&
> + vdsc_cfg->bits_per_component == 8)
> + vdsc_cfg->rc_quant_incr_limit1 = 23;
> +
> + if (compressed_bpp == 8 &&
> + vdsc_cfg->bits_per_component == 14)
> + vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
> + }
> +
I wonder if we shouldn't just use the updated values...
Maybe add a FIXME comment above the block to consider removing it?
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> /*
> * BitsPerComponent value determines mux_word_size:
> * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 01/10] drm/i915/dsc: change DSC param tables to follow the DSC model
@ 2023-02-28 15:56 ` Jani Nikula
0 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 15:56 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> After cross-checking DSC models (20150914, 20161212, 20210623) change
> values in rc_parameters tables to follow config files present inside
> the DSC model. Handle two places, where i915 tables diverged from the
> model, by patching the rc values in the code.
>
> Note: I left one case uncorrected, 8bpp/10bpc/range_max_qp[0], because
> the table in the VESA DSC 1.1 sets it to 4.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/i915/display/intel_vdsc.c | 18 ++++++++++++++++--
> 1 file changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 207b2a648d32..d080741fd0b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -86,7 +86,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> }
> },
> /* 6BPP/14BPC */
> - { 768, 15, 6144, 15, 25, 23, 27, {
> + { 768, 15, 6144, 15, 25, 23, 23, {
> { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
> { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
> { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
> @@ -115,6 +115,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> },
> /* 8BPP/10BPC */
> { 512, 12, 6144, 7, 16, 15, 15, {
> + /*
> + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> + * VESA DSC 1.1 Table E-5 sets it to 4.
> + */
> { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> @@ -132,7 +136,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> },
> /* 8BPP/14BPC */
> { 512, 12, 6144, 15, 24, 23, 23, {
> - { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
> + { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
> { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
> { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
> @@ -529,6 +533,16 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> DSC_RANGE_BPG_OFFSET_MASK;
> }
>
> + if (DISPLAY_VER(dev_priv) < 13) {
> + if (compressed_bpp == 6 &&
> + vdsc_cfg->bits_per_component == 8)
> + vdsc_cfg->rc_quant_incr_limit1 = 23;
> +
> + if (compressed_bpp == 8 &&
> + vdsc_cfg->bits_per_component == 14)
> + vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
> + }
> +
I wonder if we shouldn't just use the updated values...
Maybe add a FIXME comment above the block to consider removing it?
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> /*
> * BitsPerComponent value determines mux_word_size:
> * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH 01/10] drm/i915/dsc: change DSC param tables to follow the DSC model
@ 2023-02-28 15:56 ` Jani Nikula
0 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 15:56 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> After cross-checking DSC models (20150914, 20161212, 20210623) change
> values in rc_parameters tables to follow config files present inside
> the DSC model. Handle two places, where i915 tables diverged from the
> model, by patching the rc values in the code.
>
> Note: I left one case uncorrected, 8bpp/10bpc/range_max_qp[0], because
> the table in the VESA DSC 1.1 sets it to 4.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/i915/display/intel_vdsc.c | 18 ++++++++++++++++--
> 1 file changed, 16 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 207b2a648d32..d080741fd0b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -86,7 +86,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> }
> },
> /* 6BPP/14BPC */
> - { 768, 15, 6144, 15, 25, 23, 27, {
> + { 768, 15, 6144, 15, 25, 23, 23, {
> { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
> { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
> { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
> @@ -115,6 +115,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> },
> /* 8BPP/10BPC */
> { 512, 12, 6144, 7, 16, 15, 15, {
> + /*
> + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> + * VESA DSC 1.1 Table E-5 sets it to 4.
> + */
> { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> @@ -132,7 +136,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> },
> /* 8BPP/14BPC */
> { 512, 12, 6144, 15, 24, 23, 23, {
> - { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
> + { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
> { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
> { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
> @@ -529,6 +533,16 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> DSC_RANGE_BPG_OFFSET_MASK;
> }
>
> + if (DISPLAY_VER(dev_priv) < 13) {
> + if (compressed_bpp == 6 &&
> + vdsc_cfg->bits_per_component == 8)
> + vdsc_cfg->rc_quant_incr_limit1 = 23;
> +
> + if (compressed_bpp == 8 &&
> + vdsc_cfg->bits_per_component == 14)
> + vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
> + }
> +
I wonder if we shouldn't just use the updated values...
Maybe add a FIXME comment above the block to consider removing it?
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> /*
> * BitsPerComponent value determines mux_word_size:
> * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 02/10] drm/i915/dsc: move rc_buf_thresh values to common helper
2023-02-28 11:33 ` Dmitry Baryshkov
(?)
@ 2023-02-28 16:01 ` Jani Nikula
-1 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 16:01 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> The rc_buf_thresh values are common to all DSC implementations. Move
> them to the common helper together with the code to propagage them to
> the drm_dsc_config.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 37 +++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +--------------
> include/drm/display/drm_dsc_helper.h | 1 +
> 3 files changed, 39 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> index c869c6e51e2b..ab8679c158b5 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -270,6 +270,43 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
> }
> EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
>
> +/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
> +const u16 drm_dsc_rc_buf_thresh[] = {
> + 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
> + 7744, 7872, 8000, 8064
> +};
> +EXPORT_SYMBOL(drm_dsc_rc_buf_thresh);
> +
> +/**
> + * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
> + * in accordance with the DSC 1.2 specification.
> + *
> + * @vdsc_cfg: DSC Configuration data partially filled by driver
> + */
> +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
> +{
> + int i = 0;
> +
> + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
> + /*
> + * six 0s are appended to the lsb of each threshold value
> + * internally in h/w.
> + * Only 8 bits are allowed for programming RcBufThreshold
> + */
Not sure how appropriate the hardware references are, maybe clean it up
a bit.
With that, and +static and -export mentioned earlier,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> + vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
> + }
> +
> + /*
> + * For 6bpp, RC Buffer threshold 12 and 13 need a different value
> + * as per C Model
> + */
> + if (vdsc_cfg->bits_per_pixel == 6 << 4) {
> + vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
> + vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
> + }
> +}
> +EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
> +
> /**
> * drm_dsc_compute_rc_parameters() - Write rate control
> * parameters to the dsc configuration defined in
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index d080741fd0b3..b4faab4c8fb3 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -36,12 +36,6 @@ enum COLUMN_INDEX_BPC {
> MAX_COLUMN_INDEX
> };
>
> -/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
> -static const u16 rc_buf_thresh[] = {
> - 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
> - 7744, 7872, 8000, 8064
> -};
> -
> struct rc_parameters {
> u16 initial_xmit_delay;
> u8 first_line_bpg_offset;
> @@ -474,23 +468,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
> vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
>
> - for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
> - /*
> - * six 0s are appended to the lsb of each threshold value
> - * internally in h/w.
> - * Only 8 bits are allowed for programming RcBufThreshold
> - */
> - vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
> - }
> -
> - /*
> - * For 6bpp, RC Buffer threshold 12 and 13 need a different value
> - * as per C Model
> - */
> - if (compressed_bpp == 6) {
> - vdsc_cfg->rc_buf_thresh[12] = 0x7C;
> - vdsc_cfg->rc_buf_thresh[13] = 0x7D;
> - }
> + drm_dsc_set_rc_buf_thresh(vdsc_cfg);
>
> /*
> * From XE_LPD onwards we supports compression bpps in steps of 1
> diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> index 8b41edbbabab..706ba1d34742 100644
> --- a/include/drm/display/drm_dsc_helper.h
> +++ b/include/drm/display/drm_dsc_helper.h
> @@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
> int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> const struct drm_dsc_config *dsc_cfg);
> +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>
> #endif /* _DRM_DSC_HELPER_H_ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 02/10] drm/i915/dsc: move rc_buf_thresh values to common helper
@ 2023-02-28 16:01 ` Jani Nikula
0 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 16:01 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> The rc_buf_thresh values are common to all DSC implementations. Move
> them to the common helper together with the code to propagage them to
> the drm_dsc_config.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 37 +++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +--------------
> include/drm/display/drm_dsc_helper.h | 1 +
> 3 files changed, 39 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> index c869c6e51e2b..ab8679c158b5 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -270,6 +270,43 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
> }
> EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
>
> +/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
> +const u16 drm_dsc_rc_buf_thresh[] = {
> + 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
> + 7744, 7872, 8000, 8064
> +};
> +EXPORT_SYMBOL(drm_dsc_rc_buf_thresh);
> +
> +/**
> + * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
> + * in accordance with the DSC 1.2 specification.
> + *
> + * @vdsc_cfg: DSC Configuration data partially filled by driver
> + */
> +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
> +{
> + int i = 0;
> +
> + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
> + /*
> + * six 0s are appended to the lsb of each threshold value
> + * internally in h/w.
> + * Only 8 bits are allowed for programming RcBufThreshold
> + */
Not sure how appropriate the hardware references are, maybe clean it up
a bit.
With that, and +static and -export mentioned earlier,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> + vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
> + }
> +
> + /*
> + * For 6bpp, RC Buffer threshold 12 and 13 need a different value
> + * as per C Model
> + */
> + if (vdsc_cfg->bits_per_pixel == 6 << 4) {
> + vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
> + vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
> + }
> +}
> +EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
> +
> /**
> * drm_dsc_compute_rc_parameters() - Write rate control
> * parameters to the dsc configuration defined in
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index d080741fd0b3..b4faab4c8fb3 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -36,12 +36,6 @@ enum COLUMN_INDEX_BPC {
> MAX_COLUMN_INDEX
> };
>
> -/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
> -static const u16 rc_buf_thresh[] = {
> - 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
> - 7744, 7872, 8000, 8064
> -};
> -
> struct rc_parameters {
> u16 initial_xmit_delay;
> u8 first_line_bpg_offset;
> @@ -474,23 +468,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
> vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
>
> - for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
> - /*
> - * six 0s are appended to the lsb of each threshold value
> - * internally in h/w.
> - * Only 8 bits are allowed for programming RcBufThreshold
> - */
> - vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
> - }
> -
> - /*
> - * For 6bpp, RC Buffer threshold 12 and 13 need a different value
> - * as per C Model
> - */
> - if (compressed_bpp == 6) {
> - vdsc_cfg->rc_buf_thresh[12] = 0x7C;
> - vdsc_cfg->rc_buf_thresh[13] = 0x7D;
> - }
> + drm_dsc_set_rc_buf_thresh(vdsc_cfg);
>
> /*
> * From XE_LPD onwards we supports compression bpps in steps of 1
> diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> index 8b41edbbabab..706ba1d34742 100644
> --- a/include/drm/display/drm_dsc_helper.h
> +++ b/include/drm/display/drm_dsc_helper.h
> @@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
> int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> const struct drm_dsc_config *dsc_cfg);
> +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>
> #endif /* _DRM_DSC_HELPER_H_ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH 02/10] drm/i915/dsc: move rc_buf_thresh values to common helper
@ 2023-02-28 16:01 ` Jani Nikula
0 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 16:01 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> The rc_buf_thresh values are common to all DSC implementations. Move
> them to the common helper together with the code to propagage them to
> the drm_dsc_config.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 37 +++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +--------------
> include/drm/display/drm_dsc_helper.h | 1 +
> 3 files changed, 39 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> index c869c6e51e2b..ab8679c158b5 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -270,6 +270,43 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
> }
> EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
>
> +/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
> +const u16 drm_dsc_rc_buf_thresh[] = {
> + 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
> + 7744, 7872, 8000, 8064
> +};
> +EXPORT_SYMBOL(drm_dsc_rc_buf_thresh);
> +
> +/**
> + * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
> + * in accordance with the DSC 1.2 specification.
> + *
> + * @vdsc_cfg: DSC Configuration data partially filled by driver
> + */
> +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
> +{
> + int i = 0;
> +
> + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
> + /*
> + * six 0s are appended to the lsb of each threshold value
> + * internally in h/w.
> + * Only 8 bits are allowed for programming RcBufThreshold
> + */
Not sure how appropriate the hardware references are, maybe clean it up
a bit.
With that, and +static and -export mentioned earlier,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> + vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
> + }
> +
> + /*
> + * For 6bpp, RC Buffer threshold 12 and 13 need a different value
> + * as per C Model
> + */
> + if (vdsc_cfg->bits_per_pixel == 6 << 4) {
> + vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
> + vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
> + }
> +}
> +EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
> +
> /**
> * drm_dsc_compute_rc_parameters() - Write rate control
> * parameters to the dsc configuration defined in
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index d080741fd0b3..b4faab4c8fb3 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -36,12 +36,6 @@ enum COLUMN_INDEX_BPC {
> MAX_COLUMN_INDEX
> };
>
> -/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
> -static const u16 rc_buf_thresh[] = {
> - 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
> - 7744, 7872, 8000, 8064
> -};
> -
> struct rc_parameters {
> u16 initial_xmit_delay;
> u8 first_line_bpg_offset;
> @@ -474,23 +468,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
> vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
>
> - for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
> - /*
> - * six 0s are appended to the lsb of each threshold value
> - * internally in h/w.
> - * Only 8 bits are allowed for programming RcBufThreshold
> - */
> - vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
> - }
> -
> - /*
> - * For 6bpp, RC Buffer threshold 12 and 13 need a different value
> - * as per C Model
> - */
> - if (compressed_bpp == 6) {
> - vdsc_cfg->rc_buf_thresh[12] = 0x7C;
> - vdsc_cfg->rc_buf_thresh[13] = 0x7D;
> - }
> + drm_dsc_set_rc_buf_thresh(vdsc_cfg);
>
> /*
> * From XE_LPD onwards we supports compression bpps in steps of 1
> diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> index 8b41edbbabab..706ba1d34742 100644
> --- a/include/drm/display/drm_dsc_helper.h
> +++ b/include/drm/display/drm_dsc_helper.h
> @@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
> int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> const struct drm_dsc_config *dsc_cfg);
> +void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>
> #endif /* _DRM_DSC_HELPER_H_ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 01/10] drm/i915/dsc: change DSC param tables to follow the DSC model
2023-02-28 15:56 ` Jani Nikula
(?)
@ 2023-02-28 16:10 ` Dmitry Baryshkov
-1 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 16:10 UTC (permalink / raw)
To: Jani Nikula, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
On 28/02/2023 17:56, Jani Nikula wrote:
> On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
>> After cross-checking DSC models (20150914, 20161212, 20210623) change
>> values in rc_parameters tables to follow config files present inside
>> the DSC model. Handle two places, where i915 tables diverged from the
>> model, by patching the rc values in the code.
>>
>> Note: I left one case uncorrected, 8bpp/10bpc/range_max_qp[0], because
>> the table in the VESA DSC 1.1 sets it to 4.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>> drivers/gpu/drm/i915/display/intel_vdsc.c | 18 ++++++++++++++++--
>> 1 file changed, 16 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> index 207b2a648d32..d080741fd0b3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> @@ -86,7 +86,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
>> }
>> },
>> /* 6BPP/14BPC */
>> - { 768, 15, 6144, 15, 25, 23, 27, {
>> + { 768, 15, 6144, 15, 25, 23, 23, {
>> { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
>> { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
>> { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
>> @@ -115,6 +115,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
>> },
>> /* 8BPP/10BPC */
>> { 512, 12, 6144, 7, 16, 15, 15, {
>> + /*
>> + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
>> + * VESA DSC 1.1 Table E-5 sets it to 4.
>> + */
>> { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
>> { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
>> { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
>> @@ -132,7 +136,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
>> },
>> /* 8BPP/14BPC */
>> { 512, 12, 6144, 15, 24, 23, 23, {
>> - { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
>> + { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
>> { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
>> { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
>> { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
>> @@ -529,6 +533,16 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
>> DSC_RANGE_BPG_OFFSET_MASK;
>> }
>>
>> + if (DISPLAY_VER(dev_priv) < 13) {
>> + if (compressed_bpp == 6 &&
>> + vdsc_cfg->bits_per_component == 8)
>> + vdsc_cfg->rc_quant_incr_limit1 = 23;
>> +
>> + if (compressed_bpp == 8 &&
>> + vdsc_cfg->bits_per_component == 14)
>> + vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
>> + }
>> +
>
> I wonder if we shouldn't just use the updated values...
I also wondered about this, so I wanted to get a double check from
somebody having better knowledge of this part, if it is a typo in the
original patch or a typo in the cfg files.
E.g. the pre_scr_cfg_files_for_reference/rc_10bpc_8bpp.cfg has 8 as
RX_MAXQP[0], which (for me) looks like a typo in the CFG file itself,
rather than being a typo in the driver.
On the other hand, these two issues belong to the 'current' CFG files,
so they, most probably, received more attention from anybody working
with the standard and with the model.
I can change this patch to become a fix for the tables (dropping the if
clause), if you can confirm that these values are typos in the driver.
>
> Maybe add a FIXME comment above the block to consider removing it?
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>
>> /*
>> * BitsPerComponent value determines mux_word_size:
>> * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 01/10] drm/i915/dsc: change DSC param tables to follow the DSC model
@ 2023-02-28 16:10 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 16:10 UTC (permalink / raw)
To: Jani Nikula, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
On 28/02/2023 17:56, Jani Nikula wrote:
> On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
>> After cross-checking DSC models (20150914, 20161212, 20210623) change
>> values in rc_parameters tables to follow config files present inside
>> the DSC model. Handle two places, where i915 tables diverged from the
>> model, by patching the rc values in the code.
>>
>> Note: I left one case uncorrected, 8bpp/10bpc/range_max_qp[0], because
>> the table in the VESA DSC 1.1 sets it to 4.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>> drivers/gpu/drm/i915/display/intel_vdsc.c | 18 ++++++++++++++++--
>> 1 file changed, 16 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> index 207b2a648d32..d080741fd0b3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> @@ -86,7 +86,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
>> }
>> },
>> /* 6BPP/14BPC */
>> - { 768, 15, 6144, 15, 25, 23, 27, {
>> + { 768, 15, 6144, 15, 25, 23, 23, {
>> { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
>> { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
>> { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
>> @@ -115,6 +115,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
>> },
>> /* 8BPP/10BPC */
>> { 512, 12, 6144, 7, 16, 15, 15, {
>> + /*
>> + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
>> + * VESA DSC 1.1 Table E-5 sets it to 4.
>> + */
>> { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
>> { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
>> { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
>> @@ -132,7 +136,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
>> },
>> /* 8BPP/14BPC */
>> { 512, 12, 6144, 15, 24, 23, 23, {
>> - { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
>> + { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
>> { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
>> { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
>> { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
>> @@ -529,6 +533,16 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
>> DSC_RANGE_BPG_OFFSET_MASK;
>> }
>>
>> + if (DISPLAY_VER(dev_priv) < 13) {
>> + if (compressed_bpp == 6 &&
>> + vdsc_cfg->bits_per_component == 8)
>> + vdsc_cfg->rc_quant_incr_limit1 = 23;
>> +
>> + if (compressed_bpp == 8 &&
>> + vdsc_cfg->bits_per_component == 14)
>> + vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
>> + }
>> +
>
> I wonder if we shouldn't just use the updated values...
I also wondered about this, so I wanted to get a double check from
somebody having better knowledge of this part, if it is a typo in the
original patch or a typo in the cfg files.
E.g. the pre_scr_cfg_files_for_reference/rc_10bpc_8bpp.cfg has 8 as
RX_MAXQP[0], which (for me) looks like a typo in the CFG file itself,
rather than being a typo in the driver.
On the other hand, these two issues belong to the 'current' CFG files,
so they, most probably, received more attention from anybody working
with the standard and with the model.
I can change this patch to become a fix for the tables (dropping the if
clause), if you can confirm that these values are typos in the driver.
>
> Maybe add a FIXME comment above the block to consider removing it?
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>
>> /*
>> * BitsPerComponent value determines mux_word_size:
>> * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH 01/10] drm/i915/dsc: change DSC param tables to follow the DSC model
@ 2023-02-28 16:10 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-02-28 16:10 UTC (permalink / raw)
To: Jani Nikula, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
On 28/02/2023 17:56, Jani Nikula wrote:
> On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
>> After cross-checking DSC models (20150914, 20161212, 20210623) change
>> values in rc_parameters tables to follow config files present inside
>> the DSC model. Handle two places, where i915 tables diverged from the
>> model, by patching the rc values in the code.
>>
>> Note: I left one case uncorrected, 8bpp/10bpc/range_max_qp[0], because
>> the table in the VESA DSC 1.1 sets it to 4.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>> drivers/gpu/drm/i915/display/intel_vdsc.c | 18 ++++++++++++++++--
>> 1 file changed, 16 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> index 207b2a648d32..d080741fd0b3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> @@ -86,7 +86,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
>> }
>> },
>> /* 6BPP/14BPC */
>> - { 768, 15, 6144, 15, 25, 23, 27, {
>> + { 768, 15, 6144, 15, 25, 23, 23, {
>> { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
>> { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
>> { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
>> @@ -115,6 +115,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
>> },
>> /* 8BPP/10BPC */
>> { 512, 12, 6144, 7, 16, 15, 15, {
>> + /*
>> + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
>> + * VESA DSC 1.1 Table E-5 sets it to 4.
>> + */
>> { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
>> { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
>> { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
>> @@ -132,7 +136,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
>> },
>> /* 8BPP/14BPC */
>> { 512, 12, 6144, 15, 24, 23, 23, {
>> - { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
>> + { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
>> { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
>> { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
>> { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
>> @@ -529,6 +533,16 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
>> DSC_RANGE_BPG_OFFSET_MASK;
>> }
>>
>> + if (DISPLAY_VER(dev_priv) < 13) {
>> + if (compressed_bpp == 6 &&
>> + vdsc_cfg->bits_per_component == 8)
>> + vdsc_cfg->rc_quant_incr_limit1 = 23;
>> +
>> + if (compressed_bpp == 8 &&
>> + vdsc_cfg->bits_per_component == 14)
>> + vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
>> + }
>> +
>
> I wonder if we shouldn't just use the updated values...
I also wondered about this, so I wanted to get a double check from
somebody having better knowledge of this part, if it is a typo in the
original patch or a typo in the cfg files.
E.g. the pre_scr_cfg_files_for_reference/rc_10bpc_8bpp.cfg has 8 as
RX_MAXQP[0], which (for me) looks like a typo in the CFG file itself,
rather than being a typo in the driver.
On the other hand, these two issues belong to the 'current' CFG files,
so they, most probably, received more attention from anybody working
with the standard and with the model.
I can change this patch to become a fix for the tables (dropping the if
clause), if you can confirm that these values are typos in the driver.
>
> Maybe add a FIXME comment above the block to consider removing it?
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>
>> /*
>> * BitsPerComponent value determines mux_word_size:
>> * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper
2023-02-28 11:33 ` Dmitry Baryshkov
(?)
@ 2023-02-28 16:11 ` Jani Nikula
-1 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 16:11 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> This moves DSC RC tables to DRM DSC helper. No additional code changes
> and/or cleanups are a part of this commit, it will be cleaned up in the
> followup commits.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 364 ++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_vdsc.c | 319 +------------------
> include/drm/display/drm_dsc_helper.h | 1 +
> 3 files changed, 372 insertions(+), 312 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> index ab8679c158b5..deaa84722bd4 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -307,6 +307,370 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
> }
> EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
>
> +enum ROW_INDEX_BPP {
> + ROW_INDEX_6BPP = 0,
> + ROW_INDEX_8BPP,
> + ROW_INDEX_10BPP,
> + ROW_INDEX_12BPP,
> + ROW_INDEX_15BPP,
> + MAX_ROW_INDEX
> +};
> +
> +enum COLUMN_INDEX_BPC {
> + COLUMN_INDEX_8BPC = 0,
> + COLUMN_INDEX_10BPC,
> + COLUMN_INDEX_12BPC,
> + COLUMN_INDEX_14BPC,
> + COLUMN_INDEX_16BPC,
> + MAX_COLUMN_INDEX
> +};
> +
> +struct rc_parameters {
> + u16 initial_xmit_delay;
> + u8 first_line_bpg_offset;
> + u16 initial_offset;
> + u8 flatness_min_qp;
> + u8 flatness_max_qp;
> + u8 rc_quant_incr_limit0;
> + u8 rc_quant_incr_limit1;
> + struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
> +};
> +
> +/*
> + * Selected Rate Control Related Parameter Recommended Values
> + * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> + */
> +static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> +{
> + /* 6BPP/8BPC */
> + { 768, 15, 6144, 3, 13, 11, 11, {
> + { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
> + { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
> + { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
> + { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
> + }
> + },
> + /* 6BPP/10BPC */
> + { 768, 15, 6144, 7, 17, 15, 15, {
> + { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
> + { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
> + { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
> + { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
> + { 17, 18, -12 }
> + }
> + },
> + /* 6BPP/12BPC */
> + { 768, 15, 6144, 11, 21, 19, 19, {
> + { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
> + { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
> + { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
> + { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
> + { 21, 22, -12 }
> + }
> + },
> + /* 6BPP/14BPC */
> + { 768, 15, 6144, 15, 25, 23, 23, {
> + { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
> + { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
> + { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
> + { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
> + { 25, 26, -12 }
> + }
> + },
> + /* 6BPP/16BPC */
> + { 768, 15, 6144, 19, 29, 27, 27, {
> + { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
> + { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
> + { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
> + { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
> + { 29, 30, -12 }
> + }
> + },
> +},
> +{
> + /* 8BPP/8BPC */
> + { 512, 12, 6144, 3, 12, 11, 11, {
> + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + },
> + /* 8BPP/10BPC */
> + { 512, 12, 6144, 7, 16, 15, 15, {
> + /*
> + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> + * VESA DSC 1.1 Table E-5 sets it to 4.
> + */
> + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + },
> + /* 8BPP/12BPC */
> + { 512, 12, 6144, 11, 20, 19, 19, {
> + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + },
> + /* 8BPP/14BPC */
> + { 512, 12, 6144, 15, 24, 23, 23, {
> + { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
> + { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> + { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
> + { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
> + { 24, 25, -12 }
> + }
> + },
> + /* 8BPP/16BPC */
> + { 512, 12, 6144, 19, 28, 27, 27, {
> + { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
> + { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> + { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
> + { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
> + { 28, 29, -12 }
> + }
> + },
> +},
> +{
> + /* 10BPP/8BPC */
> + { 410, 15, 5632, 3, 12, 11, 11, {
> + { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
> + { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
> + }
> + },
> + /* 10BPP/10BPC */
> + { 410, 15, 5632, 7, 16, 15, 15, {
> + { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
> + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
> + { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
> + }
> + },
> + /* 10BPP/12BPC */
> + { 410, 15, 5632, 11, 20, 19, 19, {
> + { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
> + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
> + { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
> + { 19, 20, -12 }
> + }
> + },
> + /* 10BPP/14BPC */
> + { 410, 15, 5632, 15, 24, 23, 23, {
> + { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
> + { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> + { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
> + { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
> + { 23, 24, -12 }
> + }
> + },
> + /* 10BPP/16BPC */
> + { 410, 15, 5632, 19, 28, 27, 27, {
> + { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
> + { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> + { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
> + { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
> + { 27, 28, -12 }
> + }
> + },
> +},
> +{
> + /* 12BPP/8BPC */
> + { 341, 15, 2048, 3, 12, 11, 11, {
> + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + },
> + /* 12BPP/10BPC */
> + { 341, 15, 2048, 7, 16, 15, 15, {
> + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + },
> + /* 12BPP/12BPC */
> + { 341, 15, 2048, 11, 20, 19, 19, {
> + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + },
> + /* 12BPP/14BPC */
> + { 341, 15, 2048, 15, 24, 23, 23, {
> + { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
> + { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> + { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
> + { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
> + { 22, 23, -12 }
> + }
> + },
> + /* 12BPP/16BPC */
> + { 341, 15, 2048, 19, 28, 27, 27, {
> + { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
> + { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> + { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
> + { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
> + { 26, 27, -12 }
> + }
> + },
> +},
> +{
> + /* 15BPP/8BPC */
> + { 273, 15, 2048, 3, 12, 11, 11, {
> + { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
> + { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
> + { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
> + { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
> + }
> + },
> + /* 15BPP/10BPC */
> + { 273, 15, 2048, 7, 16, 15, 15, {
> + { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
> + { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
> + { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
> + { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
> + }
> + },
> + /* 15BPP/12BPC */
> + { 273, 15, 2048, 11, 20, 19, 19, {
> + { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
> + { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
> + { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
> + { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
> + { 16, 17, -12 }
> + }
> + },
> + /* 15BPP/14BPC */
> + { 273, 15, 2048, 15, 24, 23, 23, {
> + { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
> + { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
> + { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
> + { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
> + { 20, 21, -12 }
> + }
> + },
> + /* 15BPP/16BPC */
> + { 273, 15, 2048, 19, 28, 27, 27, {
> + { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
> + { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
> + { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
> + { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
> + { 24, 25, -12 }
> + }
> + }
> +}
> +};
> +
> +static int get_row_index_for_rc_params(u16 compressed_bpp)
> +{
> + switch (compressed_bpp) {
> + case 6:
> + return ROW_INDEX_6BPP;
> + case 8:
> + return ROW_INDEX_8BPP;
> + case 10:
> + return ROW_INDEX_10BPP;
> + case 12:
> + return ROW_INDEX_12BPP;
> + case 15:
> + return ROW_INDEX_15BPP;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int get_column_index_for_rc_params(u8 bits_per_component)
> +{
> + switch (bits_per_component) {
> + case 8:
> + return COLUMN_INDEX_8BPC;
> + case 10:
> + return COLUMN_INDEX_10BPC;
> + case 12:
> + return COLUMN_INDEX_12BPC;
> + case 14:
> + return COLUMN_INDEX_14BPC;
> + case 16:
> + return COLUMN_INDEX_16BPC;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
> + u8 bits_per_component)
> +{
> + int row_index, column_index;
> +
> + row_index = get_row_index_for_rc_params(compressed_bpp);
> + if (row_index < 0)
> + return NULL;
> +
> + column_index = get_column_index_for_rc_params(bits_per_component);
> + if (column_index < 0)
> + return NULL;
> +
> + return &rc_parameters[row_index][column_index];
> +}
> +
> +/**
> + * drm_dsc_compute_rc_parameters() - Set parameters and limits for RC model in
Copy-paste function name left in. ;)
> + * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
> + *
> + * @vdsc_cfg: DSC Configuration data partially filled by driver
Maybe mention what needs to be set beforehands? Or better yet, warn
about missing setup and return -EINVAL? *shrug*
Returns?
Other than that,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> + */
> +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> +{
> + const struct rc_parameters *rc_params;
> + int i;
> +
> + /* fractional BPP is not supported */
> + if (vdsc_cfg->bits_per_pixel & 0xf)
> + return -EINVAL;
> +
> + rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
> + vdsc_cfg->bits_per_component);
> + if (!rc_params)
> + return -EINVAL;
> +
> + vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
> + vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
> + vdsc_cfg->initial_offset = rc_params->initial_offset;
> + vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
> + vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
> + vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
> + vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
> +
> + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> + vdsc_cfg->rc_range_params[i].range_min_qp =
> + rc_params->rc_range_params[i].range_min_qp;
> + vdsc_cfg->rc_range_params[i].range_max_qp =
> + rc_params->rc_range_params[i].range_max_qp;
> + /*
> + * Range BPG Offset uses 2's complement and is only a 6 bits. So
> + * mask it to get only 6 bits.
> + */
> + vdsc_cfg->rc_range_params[i].range_bpg_offset =
> + rc_params->rc_range_params[i].range_bpg_offset &
> + DSC_RANGE_BPG_OFFSET_MASK;
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_dsc_setup_rc_params);
> +
> /**
> * drm_dsc_compute_rc_parameters() - Write rate control
> * parameters to the dsc configuration defined in
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index b4faab4c8fb3..d5a7e9494b23 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -18,24 +18,6 @@
> #include "intel_qp_tables.h"
> #include "intel_vdsc.h"
>
> -enum ROW_INDEX_BPP {
> - ROW_INDEX_6BPP = 0,
> - ROW_INDEX_8BPP,
> - ROW_INDEX_10BPP,
> - ROW_INDEX_12BPP,
> - ROW_INDEX_15BPP,
> - MAX_ROW_INDEX
> -};
> -
> -enum COLUMN_INDEX_BPC {
> - COLUMN_INDEX_8BPC = 0,
> - COLUMN_INDEX_10BPC,
> - COLUMN_INDEX_12BPC,
> - COLUMN_INDEX_14BPC,
> - COLUMN_INDEX_16BPC,
> - MAX_COLUMN_INDEX
> -};
> -
> struct rc_parameters {
> u16 initial_xmit_delay;
> u8 first_line_bpg_offset;
> @@ -47,296 +29,6 @@ struct rc_parameters {
> struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
> };
>
> -/*
> - * Selected Rate Control Related Parameter Recommended Values
> - * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> - */
> -static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> -{
> - /* 6BPP/8BPC */
> - { 768, 15, 6144, 3, 13, 11, 11, {
> - { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
> - { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
> - { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
> - { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
> - }
> - },
> - /* 6BPP/10BPC */
> - { 768, 15, 6144, 7, 17, 15, 15, {
> - { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
> - { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
> - { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
> - { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
> - { 17, 18, -12 }
> - }
> - },
> - /* 6BPP/12BPC */
> - { 768, 15, 6144, 11, 21, 19, 19, {
> - { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
> - { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
> - { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
> - { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
> - { 21, 22, -12 }
> - }
> - },
> - /* 6BPP/14BPC */
> - { 768, 15, 6144, 15, 25, 23, 23, {
> - { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
> - { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
> - { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
> - { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
> - { 25, 26, -12 }
> - }
> - },
> - /* 6BPP/16BPC */
> - { 768, 15, 6144, 19, 29, 27, 27, {
> - { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
> - { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
> - { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
> - { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
> - { 29, 30, -12 }
> - }
> - },
> -},
> -{
> - /* 8BPP/8BPC */
> - { 512, 12, 6144, 3, 12, 11, 11, {
> - { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> - { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> - { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> - }
> - },
> - /* 8BPP/10BPC */
> - { 512, 12, 6144, 7, 16, 15, 15, {
> - /*
> - * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> - * VESA DSC 1.1 Table E-5 sets it to 4.
> - */
> - { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> - { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> - }
> - },
> - /* 8BPP/12BPC */
> - { 512, 12, 6144, 11, 20, 19, 19, {
> - { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> - { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> - { 21, 23, -12 }
> - }
> - },
> - /* 8BPP/14BPC */
> - { 512, 12, 6144, 15, 24, 23, 23, {
> - { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
> - { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> - { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
> - { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
> - { 24, 25, -12 }
> - }
> - },
> - /* 8BPP/16BPC */
> - { 512, 12, 6144, 19, 28, 27, 27, {
> - { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
> - { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> - { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
> - { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
> - { 28, 29, -12 }
> - }
> - },
> -},
> -{
> - /* 10BPP/8BPC */
> - { 410, 15, 5632, 3, 12, 11, 11, {
> - { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
> - { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> - { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
> - { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
> - }
> - },
> - /* 10BPP/10BPC */
> - { 410, 15, 5632, 7, 16, 15, 15, {
> - { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
> - { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> - { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
> - { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
> - }
> - },
> - /* 10BPP/12BPC */
> - { 410, 15, 5632, 11, 20, 19, 19, {
> - { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
> - { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> - { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
> - { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
> - { 19, 20, -12 }
> - }
> - },
> - /* 10BPP/14BPC */
> - { 410, 15, 5632, 15, 24, 23, 23, {
> - { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
> - { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> - { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
> - { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
> - { 23, 24, -12 }
> - }
> - },
> - /* 10BPP/16BPC */
> - { 410, 15, 5632, 19, 28, 27, 27, {
> - { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
> - { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> - { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
> - { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
> - { 27, 28, -12 }
> - }
> - },
> -},
> -{
> - /* 12BPP/8BPC */
> - { 341, 15, 2048, 3, 12, 11, 11, {
> - { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> - { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> - { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> - }
> - },
> - /* 12BPP/10BPC */
> - { 341, 15, 2048, 7, 16, 15, 15, {
> - { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> - { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> - }
> - },
> - /* 12BPP/12BPC */
> - { 341, 15, 2048, 11, 20, 19, 19, {
> - { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> - { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> - { 21, 23, -12 }
> - }
> - },
> - /* 12BPP/14BPC */
> - { 341, 15, 2048, 15, 24, 23, 23, {
> - { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
> - { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> - { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
> - { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
> - { 22, 23, -12 }
> - }
> - },
> - /* 12BPP/16BPC */
> - { 341, 15, 2048, 19, 28, 27, 27, {
> - { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
> - { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> - { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
> - { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
> - { 26, 27, -12 }
> - }
> - },
> -},
> -{
> - /* 15BPP/8BPC */
> - { 273, 15, 2048, 3, 12, 11, 11, {
> - { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
> - { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
> - { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
> - { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
> - }
> - },
> - /* 15BPP/10BPC */
> - { 273, 15, 2048, 7, 16, 15, 15, {
> - { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
> - { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
> - { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
> - { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
> - }
> - },
> - /* 15BPP/12BPC */
> - { 273, 15, 2048, 11, 20, 19, 19, {
> - { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
> - { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
> - { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
> - { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
> - { 16, 17, -12 }
> - }
> - },
> - /* 15BPP/14BPC */
> - { 273, 15, 2048, 15, 24, 23, 23, {
> - { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
> - { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
> - { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
> - { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
> - { 20, 21, -12 }
> - }
> - },
> - /* 15BPP/16BPC */
> - { 273, 15, 2048, 19, 28, 27, 27, {
> - { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
> - { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
> - { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
> - { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
> - { 24, 25, -12 }
> - }
> - }
> -}
> -
> -};
> -
> -static int get_row_index_for_rc_params(u16 compressed_bpp)
> -{
> - switch (compressed_bpp) {
> - case 6:
> - return ROW_INDEX_6BPP;
> - case 8:
> - return ROW_INDEX_8BPP;
> - case 10:
> - return ROW_INDEX_10BPP;
> - case 12:
> - return ROW_INDEX_12BPP;
> - case 15:
> - return ROW_INDEX_15BPP;
> - default:
> - return -EINVAL;
> - }
> -}
> -
> -static int get_column_index_for_rc_params(u8 bits_per_component)
> -{
> - switch (bits_per_component) {
> - case 8:
> - return COLUMN_INDEX_8BPC;
> - case 10:
> - return COLUMN_INDEX_10BPC;
> - case 12:
> - return COLUMN_INDEX_12BPC;
> - case 14:
> - return COLUMN_INDEX_14BPC;
> - case 16:
> - return COLUMN_INDEX_16BPC;
> - default:
> - return -EINVAL;
> - }
> -}
> -
> -static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
> - u8 bits_per_component)
> -{
> - int row_index, column_index;
> -
> - row_index = get_row_index_for_rc_params(compressed_bpp);
> - if (row_index < 0)
> - return NULL;
> -
> - column_index = get_column_index_for_rc_params(bits_per_component);
> - if (column_index < 0)
> - return NULL;
> -
> - return &rc_parameters[row_index][column_index];
> -}
> -
> bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
> {
> const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -454,6 +146,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> const struct rc_parameters *rc_params;
> struct rc_parameters *rc = NULL;
> u8 i = 0;
> + int ret;
>
> vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
> vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
> @@ -483,10 +176,11 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> calculate_rc_params(rc, vdsc_cfg);
> rc_params = rc;
> } else {
> - rc_params = get_rc_params(compressed_bpp,
> - vdsc_cfg->bits_per_component);
> - if (!rc_params)
> - return -EINVAL;
> + ret = drm_dsc_setup_rc_params(vdsc_cfg);
> + if (ret)
> + return ret;
> +
> + goto out;
> }
>
> vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
> @@ -521,6 +215,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
> }
>
> +out:
> /*
> * BitsPerComponent value determines mux_word_size:
> * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
> diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> index 706ba1d34742..1681791f65a5 100644
> --- a/include/drm/display/drm_dsc_helper.h
> +++ b/include/drm/display/drm_dsc_helper.h
> @@ -15,6 +15,7 @@ int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> const struct drm_dsc_config *dsc_cfg);
> void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
> int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>
> #endif /* _DRM_DSC_HELPER_H_ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper
@ 2023-02-28 16:11 ` Jani Nikula
0 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 16:11 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> This moves DSC RC tables to DRM DSC helper. No additional code changes
> and/or cleanups are a part of this commit, it will be cleaned up in the
> followup commits.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 364 ++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_vdsc.c | 319 +------------------
> include/drm/display/drm_dsc_helper.h | 1 +
> 3 files changed, 372 insertions(+), 312 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> index ab8679c158b5..deaa84722bd4 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -307,6 +307,370 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
> }
> EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
>
> +enum ROW_INDEX_BPP {
> + ROW_INDEX_6BPP = 0,
> + ROW_INDEX_8BPP,
> + ROW_INDEX_10BPP,
> + ROW_INDEX_12BPP,
> + ROW_INDEX_15BPP,
> + MAX_ROW_INDEX
> +};
> +
> +enum COLUMN_INDEX_BPC {
> + COLUMN_INDEX_8BPC = 0,
> + COLUMN_INDEX_10BPC,
> + COLUMN_INDEX_12BPC,
> + COLUMN_INDEX_14BPC,
> + COLUMN_INDEX_16BPC,
> + MAX_COLUMN_INDEX
> +};
> +
> +struct rc_parameters {
> + u16 initial_xmit_delay;
> + u8 first_line_bpg_offset;
> + u16 initial_offset;
> + u8 flatness_min_qp;
> + u8 flatness_max_qp;
> + u8 rc_quant_incr_limit0;
> + u8 rc_quant_incr_limit1;
> + struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
> +};
> +
> +/*
> + * Selected Rate Control Related Parameter Recommended Values
> + * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> + */
> +static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> +{
> + /* 6BPP/8BPC */
> + { 768, 15, 6144, 3, 13, 11, 11, {
> + { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
> + { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
> + { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
> + { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
> + }
> + },
> + /* 6BPP/10BPC */
> + { 768, 15, 6144, 7, 17, 15, 15, {
> + { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
> + { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
> + { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
> + { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
> + { 17, 18, -12 }
> + }
> + },
> + /* 6BPP/12BPC */
> + { 768, 15, 6144, 11, 21, 19, 19, {
> + { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
> + { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
> + { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
> + { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
> + { 21, 22, -12 }
> + }
> + },
> + /* 6BPP/14BPC */
> + { 768, 15, 6144, 15, 25, 23, 23, {
> + { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
> + { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
> + { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
> + { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
> + { 25, 26, -12 }
> + }
> + },
> + /* 6BPP/16BPC */
> + { 768, 15, 6144, 19, 29, 27, 27, {
> + { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
> + { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
> + { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
> + { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
> + { 29, 30, -12 }
> + }
> + },
> +},
> +{
> + /* 8BPP/8BPC */
> + { 512, 12, 6144, 3, 12, 11, 11, {
> + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + },
> + /* 8BPP/10BPC */
> + { 512, 12, 6144, 7, 16, 15, 15, {
> + /*
> + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> + * VESA DSC 1.1 Table E-5 sets it to 4.
> + */
> + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + },
> + /* 8BPP/12BPC */
> + { 512, 12, 6144, 11, 20, 19, 19, {
> + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + },
> + /* 8BPP/14BPC */
> + { 512, 12, 6144, 15, 24, 23, 23, {
> + { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
> + { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> + { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
> + { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
> + { 24, 25, -12 }
> + }
> + },
> + /* 8BPP/16BPC */
> + { 512, 12, 6144, 19, 28, 27, 27, {
> + { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
> + { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> + { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
> + { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
> + { 28, 29, -12 }
> + }
> + },
> +},
> +{
> + /* 10BPP/8BPC */
> + { 410, 15, 5632, 3, 12, 11, 11, {
> + { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
> + { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
> + }
> + },
> + /* 10BPP/10BPC */
> + { 410, 15, 5632, 7, 16, 15, 15, {
> + { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
> + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
> + { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
> + }
> + },
> + /* 10BPP/12BPC */
> + { 410, 15, 5632, 11, 20, 19, 19, {
> + { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
> + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
> + { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
> + { 19, 20, -12 }
> + }
> + },
> + /* 10BPP/14BPC */
> + { 410, 15, 5632, 15, 24, 23, 23, {
> + { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
> + { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> + { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
> + { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
> + { 23, 24, -12 }
> + }
> + },
> + /* 10BPP/16BPC */
> + { 410, 15, 5632, 19, 28, 27, 27, {
> + { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
> + { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> + { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
> + { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
> + { 27, 28, -12 }
> + }
> + },
> +},
> +{
> + /* 12BPP/8BPC */
> + { 341, 15, 2048, 3, 12, 11, 11, {
> + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + },
> + /* 12BPP/10BPC */
> + { 341, 15, 2048, 7, 16, 15, 15, {
> + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + },
> + /* 12BPP/12BPC */
> + { 341, 15, 2048, 11, 20, 19, 19, {
> + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + },
> + /* 12BPP/14BPC */
> + { 341, 15, 2048, 15, 24, 23, 23, {
> + { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
> + { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> + { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
> + { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
> + { 22, 23, -12 }
> + }
> + },
> + /* 12BPP/16BPC */
> + { 341, 15, 2048, 19, 28, 27, 27, {
> + { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
> + { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> + { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
> + { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
> + { 26, 27, -12 }
> + }
> + },
> +},
> +{
> + /* 15BPP/8BPC */
> + { 273, 15, 2048, 3, 12, 11, 11, {
> + { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
> + { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
> + { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
> + { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
> + }
> + },
> + /* 15BPP/10BPC */
> + { 273, 15, 2048, 7, 16, 15, 15, {
> + { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
> + { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
> + { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
> + { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
> + }
> + },
> + /* 15BPP/12BPC */
> + { 273, 15, 2048, 11, 20, 19, 19, {
> + { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
> + { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
> + { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
> + { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
> + { 16, 17, -12 }
> + }
> + },
> + /* 15BPP/14BPC */
> + { 273, 15, 2048, 15, 24, 23, 23, {
> + { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
> + { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
> + { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
> + { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
> + { 20, 21, -12 }
> + }
> + },
> + /* 15BPP/16BPC */
> + { 273, 15, 2048, 19, 28, 27, 27, {
> + { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
> + { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
> + { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
> + { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
> + { 24, 25, -12 }
> + }
> + }
> +}
> +};
> +
> +static int get_row_index_for_rc_params(u16 compressed_bpp)
> +{
> + switch (compressed_bpp) {
> + case 6:
> + return ROW_INDEX_6BPP;
> + case 8:
> + return ROW_INDEX_8BPP;
> + case 10:
> + return ROW_INDEX_10BPP;
> + case 12:
> + return ROW_INDEX_12BPP;
> + case 15:
> + return ROW_INDEX_15BPP;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int get_column_index_for_rc_params(u8 bits_per_component)
> +{
> + switch (bits_per_component) {
> + case 8:
> + return COLUMN_INDEX_8BPC;
> + case 10:
> + return COLUMN_INDEX_10BPC;
> + case 12:
> + return COLUMN_INDEX_12BPC;
> + case 14:
> + return COLUMN_INDEX_14BPC;
> + case 16:
> + return COLUMN_INDEX_16BPC;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
> + u8 bits_per_component)
> +{
> + int row_index, column_index;
> +
> + row_index = get_row_index_for_rc_params(compressed_bpp);
> + if (row_index < 0)
> + return NULL;
> +
> + column_index = get_column_index_for_rc_params(bits_per_component);
> + if (column_index < 0)
> + return NULL;
> +
> + return &rc_parameters[row_index][column_index];
> +}
> +
> +/**
> + * drm_dsc_compute_rc_parameters() - Set parameters and limits for RC model in
Copy-paste function name left in. ;)
> + * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
> + *
> + * @vdsc_cfg: DSC Configuration data partially filled by driver
Maybe mention what needs to be set beforehands? Or better yet, warn
about missing setup and return -EINVAL? *shrug*
Returns?
Other than that,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> + */
> +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> +{
> + const struct rc_parameters *rc_params;
> + int i;
> +
> + /* fractional BPP is not supported */
> + if (vdsc_cfg->bits_per_pixel & 0xf)
> + return -EINVAL;
> +
> + rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
> + vdsc_cfg->bits_per_component);
> + if (!rc_params)
> + return -EINVAL;
> +
> + vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
> + vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
> + vdsc_cfg->initial_offset = rc_params->initial_offset;
> + vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
> + vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
> + vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
> + vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
> +
> + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> + vdsc_cfg->rc_range_params[i].range_min_qp =
> + rc_params->rc_range_params[i].range_min_qp;
> + vdsc_cfg->rc_range_params[i].range_max_qp =
> + rc_params->rc_range_params[i].range_max_qp;
> + /*
> + * Range BPG Offset uses 2's complement and is only a 6 bits. So
> + * mask it to get only 6 bits.
> + */
> + vdsc_cfg->rc_range_params[i].range_bpg_offset =
> + rc_params->rc_range_params[i].range_bpg_offset &
> + DSC_RANGE_BPG_OFFSET_MASK;
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_dsc_setup_rc_params);
> +
> /**
> * drm_dsc_compute_rc_parameters() - Write rate control
> * parameters to the dsc configuration defined in
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index b4faab4c8fb3..d5a7e9494b23 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -18,24 +18,6 @@
> #include "intel_qp_tables.h"
> #include "intel_vdsc.h"
>
> -enum ROW_INDEX_BPP {
> - ROW_INDEX_6BPP = 0,
> - ROW_INDEX_8BPP,
> - ROW_INDEX_10BPP,
> - ROW_INDEX_12BPP,
> - ROW_INDEX_15BPP,
> - MAX_ROW_INDEX
> -};
> -
> -enum COLUMN_INDEX_BPC {
> - COLUMN_INDEX_8BPC = 0,
> - COLUMN_INDEX_10BPC,
> - COLUMN_INDEX_12BPC,
> - COLUMN_INDEX_14BPC,
> - COLUMN_INDEX_16BPC,
> - MAX_COLUMN_INDEX
> -};
> -
> struct rc_parameters {
> u16 initial_xmit_delay;
> u8 first_line_bpg_offset;
> @@ -47,296 +29,6 @@ struct rc_parameters {
> struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
> };
>
> -/*
> - * Selected Rate Control Related Parameter Recommended Values
> - * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> - */
> -static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> -{
> - /* 6BPP/8BPC */
> - { 768, 15, 6144, 3, 13, 11, 11, {
> - { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
> - { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
> - { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
> - { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
> - }
> - },
> - /* 6BPP/10BPC */
> - { 768, 15, 6144, 7, 17, 15, 15, {
> - { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
> - { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
> - { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
> - { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
> - { 17, 18, -12 }
> - }
> - },
> - /* 6BPP/12BPC */
> - { 768, 15, 6144, 11, 21, 19, 19, {
> - { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
> - { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
> - { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
> - { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
> - { 21, 22, -12 }
> - }
> - },
> - /* 6BPP/14BPC */
> - { 768, 15, 6144, 15, 25, 23, 23, {
> - { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
> - { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
> - { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
> - { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
> - { 25, 26, -12 }
> - }
> - },
> - /* 6BPP/16BPC */
> - { 768, 15, 6144, 19, 29, 27, 27, {
> - { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
> - { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
> - { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
> - { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
> - { 29, 30, -12 }
> - }
> - },
> -},
> -{
> - /* 8BPP/8BPC */
> - { 512, 12, 6144, 3, 12, 11, 11, {
> - { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> - { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> - { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> - }
> - },
> - /* 8BPP/10BPC */
> - { 512, 12, 6144, 7, 16, 15, 15, {
> - /*
> - * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> - * VESA DSC 1.1 Table E-5 sets it to 4.
> - */
> - { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> - { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> - }
> - },
> - /* 8BPP/12BPC */
> - { 512, 12, 6144, 11, 20, 19, 19, {
> - { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> - { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> - { 21, 23, -12 }
> - }
> - },
> - /* 8BPP/14BPC */
> - { 512, 12, 6144, 15, 24, 23, 23, {
> - { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
> - { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> - { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
> - { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
> - { 24, 25, -12 }
> - }
> - },
> - /* 8BPP/16BPC */
> - { 512, 12, 6144, 19, 28, 27, 27, {
> - { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
> - { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> - { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
> - { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
> - { 28, 29, -12 }
> - }
> - },
> -},
> -{
> - /* 10BPP/8BPC */
> - { 410, 15, 5632, 3, 12, 11, 11, {
> - { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
> - { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> - { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
> - { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
> - }
> - },
> - /* 10BPP/10BPC */
> - { 410, 15, 5632, 7, 16, 15, 15, {
> - { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
> - { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> - { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
> - { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
> - }
> - },
> - /* 10BPP/12BPC */
> - { 410, 15, 5632, 11, 20, 19, 19, {
> - { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
> - { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> - { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
> - { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
> - { 19, 20, -12 }
> - }
> - },
> - /* 10BPP/14BPC */
> - { 410, 15, 5632, 15, 24, 23, 23, {
> - { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
> - { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> - { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
> - { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
> - { 23, 24, -12 }
> - }
> - },
> - /* 10BPP/16BPC */
> - { 410, 15, 5632, 19, 28, 27, 27, {
> - { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
> - { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> - { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
> - { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
> - { 27, 28, -12 }
> - }
> - },
> -},
> -{
> - /* 12BPP/8BPC */
> - { 341, 15, 2048, 3, 12, 11, 11, {
> - { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> - { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> - { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> - }
> - },
> - /* 12BPP/10BPC */
> - { 341, 15, 2048, 7, 16, 15, 15, {
> - { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> - { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> - }
> - },
> - /* 12BPP/12BPC */
> - { 341, 15, 2048, 11, 20, 19, 19, {
> - { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> - { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> - { 21, 23, -12 }
> - }
> - },
> - /* 12BPP/14BPC */
> - { 341, 15, 2048, 15, 24, 23, 23, {
> - { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
> - { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> - { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
> - { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
> - { 22, 23, -12 }
> - }
> - },
> - /* 12BPP/16BPC */
> - { 341, 15, 2048, 19, 28, 27, 27, {
> - { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
> - { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> - { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
> - { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
> - { 26, 27, -12 }
> - }
> - },
> -},
> -{
> - /* 15BPP/8BPC */
> - { 273, 15, 2048, 3, 12, 11, 11, {
> - { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
> - { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
> - { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
> - { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
> - }
> - },
> - /* 15BPP/10BPC */
> - { 273, 15, 2048, 7, 16, 15, 15, {
> - { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
> - { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
> - { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
> - { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
> - }
> - },
> - /* 15BPP/12BPC */
> - { 273, 15, 2048, 11, 20, 19, 19, {
> - { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
> - { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
> - { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
> - { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
> - { 16, 17, -12 }
> - }
> - },
> - /* 15BPP/14BPC */
> - { 273, 15, 2048, 15, 24, 23, 23, {
> - { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
> - { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
> - { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
> - { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
> - { 20, 21, -12 }
> - }
> - },
> - /* 15BPP/16BPC */
> - { 273, 15, 2048, 19, 28, 27, 27, {
> - { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
> - { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
> - { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
> - { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
> - { 24, 25, -12 }
> - }
> - }
> -}
> -
> -};
> -
> -static int get_row_index_for_rc_params(u16 compressed_bpp)
> -{
> - switch (compressed_bpp) {
> - case 6:
> - return ROW_INDEX_6BPP;
> - case 8:
> - return ROW_INDEX_8BPP;
> - case 10:
> - return ROW_INDEX_10BPP;
> - case 12:
> - return ROW_INDEX_12BPP;
> - case 15:
> - return ROW_INDEX_15BPP;
> - default:
> - return -EINVAL;
> - }
> -}
> -
> -static int get_column_index_for_rc_params(u8 bits_per_component)
> -{
> - switch (bits_per_component) {
> - case 8:
> - return COLUMN_INDEX_8BPC;
> - case 10:
> - return COLUMN_INDEX_10BPC;
> - case 12:
> - return COLUMN_INDEX_12BPC;
> - case 14:
> - return COLUMN_INDEX_14BPC;
> - case 16:
> - return COLUMN_INDEX_16BPC;
> - default:
> - return -EINVAL;
> - }
> -}
> -
> -static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
> - u8 bits_per_component)
> -{
> - int row_index, column_index;
> -
> - row_index = get_row_index_for_rc_params(compressed_bpp);
> - if (row_index < 0)
> - return NULL;
> -
> - column_index = get_column_index_for_rc_params(bits_per_component);
> - if (column_index < 0)
> - return NULL;
> -
> - return &rc_parameters[row_index][column_index];
> -}
> -
> bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
> {
> const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -454,6 +146,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> const struct rc_parameters *rc_params;
> struct rc_parameters *rc = NULL;
> u8 i = 0;
> + int ret;
>
> vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
> vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
> @@ -483,10 +176,11 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> calculate_rc_params(rc, vdsc_cfg);
> rc_params = rc;
> } else {
> - rc_params = get_rc_params(compressed_bpp,
> - vdsc_cfg->bits_per_component);
> - if (!rc_params)
> - return -EINVAL;
> + ret = drm_dsc_setup_rc_params(vdsc_cfg);
> + if (ret)
> + return ret;
> +
> + goto out;
> }
>
> vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
> @@ -521,6 +215,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
> }
>
> +out:
> /*
> * BitsPerComponent value determines mux_word_size:
> * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
> diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> index 706ba1d34742..1681791f65a5 100644
> --- a/include/drm/display/drm_dsc_helper.h
> +++ b/include/drm/display/drm_dsc_helper.h
> @@ -15,6 +15,7 @@ int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> const struct drm_dsc_config *dsc_cfg);
> void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
> int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>
> #endif /* _DRM_DSC_HELPER_H_ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper
@ 2023-02-28 16:11 ` Jani Nikula
0 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 16:11 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> This moves DSC RC tables to DRM DSC helper. No additional code changes
> and/or cleanups are a part of this commit, it will be cleaned up in the
> followup commits.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 364 ++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_vdsc.c | 319 +------------------
> include/drm/display/drm_dsc_helper.h | 1 +
> 3 files changed, 372 insertions(+), 312 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> index ab8679c158b5..deaa84722bd4 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -307,6 +307,370 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
> }
> EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
>
> +enum ROW_INDEX_BPP {
> + ROW_INDEX_6BPP = 0,
> + ROW_INDEX_8BPP,
> + ROW_INDEX_10BPP,
> + ROW_INDEX_12BPP,
> + ROW_INDEX_15BPP,
> + MAX_ROW_INDEX
> +};
> +
> +enum COLUMN_INDEX_BPC {
> + COLUMN_INDEX_8BPC = 0,
> + COLUMN_INDEX_10BPC,
> + COLUMN_INDEX_12BPC,
> + COLUMN_INDEX_14BPC,
> + COLUMN_INDEX_16BPC,
> + MAX_COLUMN_INDEX
> +};
> +
> +struct rc_parameters {
> + u16 initial_xmit_delay;
> + u8 first_line_bpg_offset;
> + u16 initial_offset;
> + u8 flatness_min_qp;
> + u8 flatness_max_qp;
> + u8 rc_quant_incr_limit0;
> + u8 rc_quant_incr_limit1;
> + struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
> +};
> +
> +/*
> + * Selected Rate Control Related Parameter Recommended Values
> + * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> + */
> +static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> +{
> + /* 6BPP/8BPC */
> + { 768, 15, 6144, 3, 13, 11, 11, {
> + { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
> + { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
> + { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
> + { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
> + }
> + },
> + /* 6BPP/10BPC */
> + { 768, 15, 6144, 7, 17, 15, 15, {
> + { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
> + { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
> + { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
> + { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
> + { 17, 18, -12 }
> + }
> + },
> + /* 6BPP/12BPC */
> + { 768, 15, 6144, 11, 21, 19, 19, {
> + { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
> + { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
> + { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
> + { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
> + { 21, 22, -12 }
> + }
> + },
> + /* 6BPP/14BPC */
> + { 768, 15, 6144, 15, 25, 23, 23, {
> + { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
> + { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
> + { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
> + { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
> + { 25, 26, -12 }
> + }
> + },
> + /* 6BPP/16BPC */
> + { 768, 15, 6144, 19, 29, 27, 27, {
> + { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
> + { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
> + { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
> + { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
> + { 29, 30, -12 }
> + }
> + },
> +},
> +{
> + /* 8BPP/8BPC */
> + { 512, 12, 6144, 3, 12, 11, 11, {
> + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + },
> + /* 8BPP/10BPC */
> + { 512, 12, 6144, 7, 16, 15, 15, {
> + /*
> + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> + * VESA DSC 1.1 Table E-5 sets it to 4.
> + */
> + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + },
> + /* 8BPP/12BPC */
> + { 512, 12, 6144, 11, 20, 19, 19, {
> + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + },
> + /* 8BPP/14BPC */
> + { 512, 12, 6144, 15, 24, 23, 23, {
> + { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
> + { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> + { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
> + { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
> + { 24, 25, -12 }
> + }
> + },
> + /* 8BPP/16BPC */
> + { 512, 12, 6144, 19, 28, 27, 27, {
> + { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
> + { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> + { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
> + { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
> + { 28, 29, -12 }
> + }
> + },
> +},
> +{
> + /* 10BPP/8BPC */
> + { 410, 15, 5632, 3, 12, 11, 11, {
> + { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
> + { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
> + }
> + },
> + /* 10BPP/10BPC */
> + { 410, 15, 5632, 7, 16, 15, 15, {
> + { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
> + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
> + { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
> + }
> + },
> + /* 10BPP/12BPC */
> + { 410, 15, 5632, 11, 20, 19, 19, {
> + { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
> + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
> + { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
> + { 19, 20, -12 }
> + }
> + },
> + /* 10BPP/14BPC */
> + { 410, 15, 5632, 15, 24, 23, 23, {
> + { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
> + { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> + { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
> + { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
> + { 23, 24, -12 }
> + }
> + },
> + /* 10BPP/16BPC */
> + { 410, 15, 5632, 19, 28, 27, 27, {
> + { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
> + { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> + { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
> + { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
> + { 27, 28, -12 }
> + }
> + },
> +},
> +{
> + /* 12BPP/8BPC */
> + { 341, 15, 2048, 3, 12, 11, 11, {
> + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + },
> + /* 12BPP/10BPC */
> + { 341, 15, 2048, 7, 16, 15, 15, {
> + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + },
> + /* 12BPP/12BPC */
> + { 341, 15, 2048, 11, 20, 19, 19, {
> + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + },
> + /* 12BPP/14BPC */
> + { 341, 15, 2048, 15, 24, 23, 23, {
> + { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
> + { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> + { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
> + { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
> + { 22, 23, -12 }
> + }
> + },
> + /* 12BPP/16BPC */
> + { 341, 15, 2048, 19, 28, 27, 27, {
> + { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
> + { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> + { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
> + { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
> + { 26, 27, -12 }
> + }
> + },
> +},
> +{
> + /* 15BPP/8BPC */
> + { 273, 15, 2048, 3, 12, 11, 11, {
> + { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
> + { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
> + { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
> + { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
> + }
> + },
> + /* 15BPP/10BPC */
> + { 273, 15, 2048, 7, 16, 15, 15, {
> + { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
> + { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
> + { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
> + { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
> + }
> + },
> + /* 15BPP/12BPC */
> + { 273, 15, 2048, 11, 20, 19, 19, {
> + { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
> + { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
> + { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
> + { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
> + { 16, 17, -12 }
> + }
> + },
> + /* 15BPP/14BPC */
> + { 273, 15, 2048, 15, 24, 23, 23, {
> + { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
> + { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
> + { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
> + { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
> + { 20, 21, -12 }
> + }
> + },
> + /* 15BPP/16BPC */
> + { 273, 15, 2048, 19, 28, 27, 27, {
> + { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
> + { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
> + { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
> + { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
> + { 24, 25, -12 }
> + }
> + }
> +}
> +};
> +
> +static int get_row_index_for_rc_params(u16 compressed_bpp)
> +{
> + switch (compressed_bpp) {
> + case 6:
> + return ROW_INDEX_6BPP;
> + case 8:
> + return ROW_INDEX_8BPP;
> + case 10:
> + return ROW_INDEX_10BPP;
> + case 12:
> + return ROW_INDEX_12BPP;
> + case 15:
> + return ROW_INDEX_15BPP;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int get_column_index_for_rc_params(u8 bits_per_component)
> +{
> + switch (bits_per_component) {
> + case 8:
> + return COLUMN_INDEX_8BPC;
> + case 10:
> + return COLUMN_INDEX_10BPC;
> + case 12:
> + return COLUMN_INDEX_12BPC;
> + case 14:
> + return COLUMN_INDEX_14BPC;
> + case 16:
> + return COLUMN_INDEX_16BPC;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
> + u8 bits_per_component)
> +{
> + int row_index, column_index;
> +
> + row_index = get_row_index_for_rc_params(compressed_bpp);
> + if (row_index < 0)
> + return NULL;
> +
> + column_index = get_column_index_for_rc_params(bits_per_component);
> + if (column_index < 0)
> + return NULL;
> +
> + return &rc_parameters[row_index][column_index];
> +}
> +
> +/**
> + * drm_dsc_compute_rc_parameters() - Set parameters and limits for RC model in
Copy-paste function name left in. ;)
> + * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
> + *
> + * @vdsc_cfg: DSC Configuration data partially filled by driver
Maybe mention what needs to be set beforehands? Or better yet, warn
about missing setup and return -EINVAL? *shrug*
Returns?
Other than that,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> + */
> +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> +{
> + const struct rc_parameters *rc_params;
> + int i;
> +
> + /* fractional BPP is not supported */
> + if (vdsc_cfg->bits_per_pixel & 0xf)
> + return -EINVAL;
> +
> + rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
> + vdsc_cfg->bits_per_component);
> + if (!rc_params)
> + return -EINVAL;
> +
> + vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
> + vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
> + vdsc_cfg->initial_offset = rc_params->initial_offset;
> + vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
> + vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
> + vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
> + vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
> +
> + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> + vdsc_cfg->rc_range_params[i].range_min_qp =
> + rc_params->rc_range_params[i].range_min_qp;
> + vdsc_cfg->rc_range_params[i].range_max_qp =
> + rc_params->rc_range_params[i].range_max_qp;
> + /*
> + * Range BPG Offset uses 2's complement and is only a 6 bits. So
> + * mask it to get only 6 bits.
> + */
> + vdsc_cfg->rc_range_params[i].range_bpg_offset =
> + rc_params->rc_range_params[i].range_bpg_offset &
> + DSC_RANGE_BPG_OFFSET_MASK;
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_dsc_setup_rc_params);
> +
> /**
> * drm_dsc_compute_rc_parameters() - Write rate control
> * parameters to the dsc configuration defined in
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index b4faab4c8fb3..d5a7e9494b23 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -18,24 +18,6 @@
> #include "intel_qp_tables.h"
> #include "intel_vdsc.h"
>
> -enum ROW_INDEX_BPP {
> - ROW_INDEX_6BPP = 0,
> - ROW_INDEX_8BPP,
> - ROW_INDEX_10BPP,
> - ROW_INDEX_12BPP,
> - ROW_INDEX_15BPP,
> - MAX_ROW_INDEX
> -};
> -
> -enum COLUMN_INDEX_BPC {
> - COLUMN_INDEX_8BPC = 0,
> - COLUMN_INDEX_10BPC,
> - COLUMN_INDEX_12BPC,
> - COLUMN_INDEX_14BPC,
> - COLUMN_INDEX_16BPC,
> - MAX_COLUMN_INDEX
> -};
> -
> struct rc_parameters {
> u16 initial_xmit_delay;
> u8 first_line_bpg_offset;
> @@ -47,296 +29,6 @@ struct rc_parameters {
> struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
> };
>
> -/*
> - * Selected Rate Control Related Parameter Recommended Values
> - * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> - */
> -static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> -{
> - /* 6BPP/8BPC */
> - { 768, 15, 6144, 3, 13, 11, 11, {
> - { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
> - { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
> - { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
> - { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
> - }
> - },
> - /* 6BPP/10BPC */
> - { 768, 15, 6144, 7, 17, 15, 15, {
> - { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
> - { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
> - { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
> - { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
> - { 17, 18, -12 }
> - }
> - },
> - /* 6BPP/12BPC */
> - { 768, 15, 6144, 11, 21, 19, 19, {
> - { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
> - { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
> - { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
> - { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
> - { 21, 22, -12 }
> - }
> - },
> - /* 6BPP/14BPC */
> - { 768, 15, 6144, 15, 25, 23, 23, {
> - { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
> - { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
> - { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
> - { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
> - { 25, 26, -12 }
> - }
> - },
> - /* 6BPP/16BPC */
> - { 768, 15, 6144, 19, 29, 27, 27, {
> - { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
> - { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
> - { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
> - { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
> - { 29, 30, -12 }
> - }
> - },
> -},
> -{
> - /* 8BPP/8BPC */
> - { 512, 12, 6144, 3, 12, 11, 11, {
> - { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> - { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> - { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> - }
> - },
> - /* 8BPP/10BPC */
> - { 512, 12, 6144, 7, 16, 15, 15, {
> - /*
> - * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> - * VESA DSC 1.1 Table E-5 sets it to 4.
> - */
> - { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> - { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> - }
> - },
> - /* 8BPP/12BPC */
> - { 512, 12, 6144, 11, 20, 19, 19, {
> - { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> - { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> - { 21, 23, -12 }
> - }
> - },
> - /* 8BPP/14BPC */
> - { 512, 12, 6144, 15, 24, 23, 23, {
> - { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
> - { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> - { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
> - { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
> - { 24, 25, -12 }
> - }
> - },
> - /* 8BPP/16BPC */
> - { 512, 12, 6144, 19, 28, 27, 27, {
> - { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
> - { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> - { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
> - { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
> - { 28, 29, -12 }
> - }
> - },
> -},
> -{
> - /* 10BPP/8BPC */
> - { 410, 15, 5632, 3, 12, 11, 11, {
> - { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
> - { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> - { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
> - { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
> - }
> - },
> - /* 10BPP/10BPC */
> - { 410, 15, 5632, 7, 16, 15, 15, {
> - { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
> - { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> - { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
> - { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
> - }
> - },
> - /* 10BPP/12BPC */
> - { 410, 15, 5632, 11, 20, 19, 19, {
> - { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
> - { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> - { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
> - { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
> - { 19, 20, -12 }
> - }
> - },
> - /* 10BPP/14BPC */
> - { 410, 15, 5632, 15, 24, 23, 23, {
> - { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
> - { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> - { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
> - { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
> - { 23, 24, -12 }
> - }
> - },
> - /* 10BPP/16BPC */
> - { 410, 15, 5632, 19, 28, 27, 27, {
> - { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
> - { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> - { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
> - { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
> - { 27, 28, -12 }
> - }
> - },
> -},
> -{
> - /* 12BPP/8BPC */
> - { 341, 15, 2048, 3, 12, 11, 11, {
> - { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> - { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> - { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> - }
> - },
> - /* 12BPP/10BPC */
> - { 341, 15, 2048, 7, 16, 15, 15, {
> - { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> - { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> - }
> - },
> - /* 12BPP/12BPC */
> - { 341, 15, 2048, 11, 20, 19, 19, {
> - { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> - { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> - { 21, 23, -12 }
> - }
> - },
> - /* 12BPP/14BPC */
> - { 341, 15, 2048, 15, 24, 23, 23, {
> - { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
> - { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> - { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
> - { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
> - { 22, 23, -12 }
> - }
> - },
> - /* 12BPP/16BPC */
> - { 341, 15, 2048, 19, 28, 27, 27, {
> - { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
> - { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> - { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
> - { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
> - { 26, 27, -12 }
> - }
> - },
> -},
> -{
> - /* 15BPP/8BPC */
> - { 273, 15, 2048, 3, 12, 11, 11, {
> - { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
> - { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
> - { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
> - { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
> - }
> - },
> - /* 15BPP/10BPC */
> - { 273, 15, 2048, 7, 16, 15, 15, {
> - { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
> - { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
> - { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
> - { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
> - }
> - },
> - /* 15BPP/12BPC */
> - { 273, 15, 2048, 11, 20, 19, 19, {
> - { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
> - { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
> - { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
> - { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
> - { 16, 17, -12 }
> - }
> - },
> - /* 15BPP/14BPC */
> - { 273, 15, 2048, 15, 24, 23, 23, {
> - { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
> - { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
> - { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
> - { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
> - { 20, 21, -12 }
> - }
> - },
> - /* 15BPP/16BPC */
> - { 273, 15, 2048, 19, 28, 27, 27, {
> - { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
> - { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
> - { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
> - { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
> - { 24, 25, -12 }
> - }
> - }
> -}
> -
> -};
> -
> -static int get_row_index_for_rc_params(u16 compressed_bpp)
> -{
> - switch (compressed_bpp) {
> - case 6:
> - return ROW_INDEX_6BPP;
> - case 8:
> - return ROW_INDEX_8BPP;
> - case 10:
> - return ROW_INDEX_10BPP;
> - case 12:
> - return ROW_INDEX_12BPP;
> - case 15:
> - return ROW_INDEX_15BPP;
> - default:
> - return -EINVAL;
> - }
> -}
> -
> -static int get_column_index_for_rc_params(u8 bits_per_component)
> -{
> - switch (bits_per_component) {
> - case 8:
> - return COLUMN_INDEX_8BPC;
> - case 10:
> - return COLUMN_INDEX_10BPC;
> - case 12:
> - return COLUMN_INDEX_12BPC;
> - case 14:
> - return COLUMN_INDEX_14BPC;
> - case 16:
> - return COLUMN_INDEX_16BPC;
> - default:
> - return -EINVAL;
> - }
> -}
> -
> -static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
> - u8 bits_per_component)
> -{
> - int row_index, column_index;
> -
> - row_index = get_row_index_for_rc_params(compressed_bpp);
> - if (row_index < 0)
> - return NULL;
> -
> - column_index = get_column_index_for_rc_params(bits_per_component);
> - if (column_index < 0)
> - return NULL;
> -
> - return &rc_parameters[row_index][column_index];
> -}
> -
> bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
> {
> const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -454,6 +146,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> const struct rc_parameters *rc_params;
> struct rc_parameters *rc = NULL;
> u8 i = 0;
> + int ret;
>
> vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
> vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
> @@ -483,10 +176,11 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> calculate_rc_params(rc, vdsc_cfg);
> rc_params = rc;
> } else {
> - rc_params = get_rc_params(compressed_bpp,
> - vdsc_cfg->bits_per_component);
> - if (!rc_params)
> - return -EINVAL;
> + ret = drm_dsc_setup_rc_params(vdsc_cfg);
> + if (ret)
> + return ret;
> +
> + goto out;
> }
>
> vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
> @@ -521,6 +215,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
> }
>
> +out:
> /*
> * BitsPerComponent value determines mux_word_size:
> * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
> diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> index 706ba1d34742..1681791f65a5 100644
> --- a/include/drm/display/drm_dsc_helper.h
> +++ b/include/drm/display/drm_dsc_helper.h
> @@ -15,6 +15,7 @@ int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> const struct drm_dsc_config *dsc_cfg);
> void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
> int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>
> #endif /* _DRM_DSC_HELPER_H_ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 04/10] drm/i915/dsc: stop using interim structure for calculated params
2023-02-28 11:33 ` Dmitry Baryshkov
(?)
@ 2023-02-28 16:19 ` Jani Nikula
-1 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 16:19 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> Stop using an interim structure rc_parameters for storing calculated
> params and then setting drm_dsc_config using that structure. Instead put
> calculated params into the struct drm_dsc_config directly.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/i915/display/intel_vdsc.c | 89 +++++------------------
> 1 file changed, 20 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index d5a7e9494b23..1ee8d13c9d64 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -18,17 +18,6 @@
> #include "intel_qp_tables.h"
> #include "intel_vdsc.h"
>
> -struct rc_parameters {
> - u16 initial_xmit_delay;
> - u8 first_line_bpg_offset;
> - u16 initial_offset;
> - u8 flatness_min_qp;
> - u8 flatness_max_qp;
> - u8 rc_quant_incr_limit0;
> - u8 rc_quant_incr_limit1;
> - struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
> -};
> -
> bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
> {
> const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -63,8 +52,7 @@ static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
> }
>
> static void
> -calculate_rc_params(struct rc_parameters *rc,
> - struct drm_dsc_config *vdsc_cfg)
> +calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
> {
> int bpc = vdsc_cfg->bits_per_component;
> int bpp = vdsc_cfg->bits_per_pixel >> 4;
> @@ -84,54 +72,54 @@ calculate_rc_params(struct rc_parameters *rc,
> u32 res, buf_i, bpp_i;
>
> if (vdsc_cfg->slice_height >= 8)
> - rc->first_line_bpg_offset =
> + vdsc_cfg->first_line_bpg_offset =
> 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);
> else
> - rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
> + vdsc_cfg->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
>
> /* Our hw supports only 444 modes as of today */
> if (bpp >= 12)
> - rc->initial_offset = 2048;
> + vdsc_cfg->initial_offset = 2048;
> else if (bpp >= 10)
> - rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
> + vdsc_cfg->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
> else if (bpp >= 8)
> - rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
> + vdsc_cfg->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
> else
> - rc->initial_offset = 6144;
> + vdsc_cfg->initial_offset = 6144;
>
> /* initial_xmit_delay = rc_model_size/2/compression_bpp */
> - rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
> + vdsc_cfg->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
>
> - rc->flatness_min_qp = 3 + qp_bpc_modifier;
> - rc->flatness_max_qp = 12 + qp_bpc_modifier;
> + vdsc_cfg->flatness_min_qp = 3 + qp_bpc_modifier;
> + vdsc_cfg->flatness_max_qp = 12 + qp_bpc_modifier;
>
> - rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
> - rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
> + vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
> + vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
>
> bpp_i = (2 * (bpp - 6));
> for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
> /* Read range_minqp and range_max_qp from qp tables */
> - rc->rc_range_params[buf_i].range_min_qp =
> + vdsc_cfg->rc_range_params[buf_i].range_min_qp =
> intel_lookup_range_min_qp(bpc, buf_i, bpp_i);
> - rc->rc_range_params[buf_i].range_max_qp =
> + vdsc_cfg->rc_range_params[buf_i].range_max_qp =
> intel_lookup_range_max_qp(bpc, buf_i, bpp_i);
>
> /* Calculate range_bgp_offset */
> if (bpp <= 6) {
> - rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
> + vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
> } else if (bpp <= 8) {
> res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
> - rc->rc_range_params[buf_i].range_bpg_offset =
> + vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
> ofs_und6[buf_i] + res;
> } else if (bpp <= 12) {
> - rc->rc_range_params[buf_i].range_bpg_offset =
> + vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
> ofs_und8[buf_i];
> } else if (bpp <= 15) {
> res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
> - rc->rc_range_params[buf_i].range_bpg_offset =
> + vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
> ofs_und12[buf_i] + res;
> } else {
> - rc->rc_range_params[buf_i].range_bpg_offset =
> + vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
> ofs_und15[buf_i];
This would benefit from a temp range_bpg_offset variable, assigned to
vdsc_cfg->rc_range_params[buf_i].range_bpg_offset after the if ladder.
> }
> }
> @@ -143,9 +131,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
> u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
> - const struct rc_parameters *rc_params;
> - struct rc_parameters *rc = NULL;
> - u8 i = 0;
> int ret;
>
> vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
> @@ -169,43 +154,12 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> * parameters
> */
> if (DISPLAY_VER(dev_priv) >= 13) {
> - rc = kmalloc(sizeof(*rc), GFP_KERNEL);
> - if (!rc)
> - return -ENOMEM;
> -
> - calculate_rc_params(rc, vdsc_cfg);
> - rc_params = rc;
> + calculate_rc_params(vdsc_cfg);
> } else {
> ret = drm_dsc_setup_rc_params(vdsc_cfg);
> if (ret)
> return ret;
>
> - goto out;
> - }
> -
> - vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
> - vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
> - vdsc_cfg->initial_offset = rc_params->initial_offset;
> - vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
> - vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
> - vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
> - vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
> -
> - for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> - vdsc_cfg->rc_range_params[i].range_min_qp =
> - rc_params->rc_range_params[i].range_min_qp;
> - vdsc_cfg->rc_range_params[i].range_max_qp =
> - rc_params->rc_range_params[i].range_max_qp;
> - /*
> - * Range BPG Offset uses 2's complement and is only a 6 bits. So
> - * mask it to get only 6 bits.
> - */
> - vdsc_cfg->rc_range_params[i].range_bpg_offset =
> - rc_params->rc_range_params[i].range_bpg_offset &
> - DSC_RANGE_BPG_OFFSET_MASK;
This masking needs to be added to the loop in
calculate_rc_params(). With the temp variable I suggested above, it
could be done while assigning.
With that fixed,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Also, this is awesome stuff, thanks!
> - }
> -
> - if (DISPLAY_VER(dev_priv) < 13) {
> if (compressed_bpp == 6 &&
> vdsc_cfg->bits_per_component == 8)
> vdsc_cfg->rc_quant_incr_limit1 = 23;
> @@ -215,7 +169,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
> }
>
> -out:
> /*
> * BitsPerComponent value determines mux_word_size:
> * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
> @@ -230,8 +183,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
> (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
>
> - kfree(rc);
> -
> return 0;
> }
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 04/10] drm/i915/dsc: stop using interim structure for calculated params
@ 2023-02-28 16:19 ` Jani Nikula
0 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 16:19 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> Stop using an interim structure rc_parameters for storing calculated
> params and then setting drm_dsc_config using that structure. Instead put
> calculated params into the struct drm_dsc_config directly.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/i915/display/intel_vdsc.c | 89 +++++------------------
> 1 file changed, 20 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index d5a7e9494b23..1ee8d13c9d64 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -18,17 +18,6 @@
> #include "intel_qp_tables.h"
> #include "intel_vdsc.h"
>
> -struct rc_parameters {
> - u16 initial_xmit_delay;
> - u8 first_line_bpg_offset;
> - u16 initial_offset;
> - u8 flatness_min_qp;
> - u8 flatness_max_qp;
> - u8 rc_quant_incr_limit0;
> - u8 rc_quant_incr_limit1;
> - struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
> -};
> -
> bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
> {
> const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -63,8 +52,7 @@ static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
> }
>
> static void
> -calculate_rc_params(struct rc_parameters *rc,
> - struct drm_dsc_config *vdsc_cfg)
> +calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
> {
> int bpc = vdsc_cfg->bits_per_component;
> int bpp = vdsc_cfg->bits_per_pixel >> 4;
> @@ -84,54 +72,54 @@ calculate_rc_params(struct rc_parameters *rc,
> u32 res, buf_i, bpp_i;
>
> if (vdsc_cfg->slice_height >= 8)
> - rc->first_line_bpg_offset =
> + vdsc_cfg->first_line_bpg_offset =
> 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);
> else
> - rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
> + vdsc_cfg->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
>
> /* Our hw supports only 444 modes as of today */
> if (bpp >= 12)
> - rc->initial_offset = 2048;
> + vdsc_cfg->initial_offset = 2048;
> else if (bpp >= 10)
> - rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
> + vdsc_cfg->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
> else if (bpp >= 8)
> - rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
> + vdsc_cfg->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
> else
> - rc->initial_offset = 6144;
> + vdsc_cfg->initial_offset = 6144;
>
> /* initial_xmit_delay = rc_model_size/2/compression_bpp */
> - rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
> + vdsc_cfg->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
>
> - rc->flatness_min_qp = 3 + qp_bpc_modifier;
> - rc->flatness_max_qp = 12 + qp_bpc_modifier;
> + vdsc_cfg->flatness_min_qp = 3 + qp_bpc_modifier;
> + vdsc_cfg->flatness_max_qp = 12 + qp_bpc_modifier;
>
> - rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
> - rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
> + vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
> + vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
>
> bpp_i = (2 * (bpp - 6));
> for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
> /* Read range_minqp and range_max_qp from qp tables */
> - rc->rc_range_params[buf_i].range_min_qp =
> + vdsc_cfg->rc_range_params[buf_i].range_min_qp =
> intel_lookup_range_min_qp(bpc, buf_i, bpp_i);
> - rc->rc_range_params[buf_i].range_max_qp =
> + vdsc_cfg->rc_range_params[buf_i].range_max_qp =
> intel_lookup_range_max_qp(bpc, buf_i, bpp_i);
>
> /* Calculate range_bgp_offset */
> if (bpp <= 6) {
> - rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
> + vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
> } else if (bpp <= 8) {
> res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
> - rc->rc_range_params[buf_i].range_bpg_offset =
> + vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
> ofs_und6[buf_i] + res;
> } else if (bpp <= 12) {
> - rc->rc_range_params[buf_i].range_bpg_offset =
> + vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
> ofs_und8[buf_i];
> } else if (bpp <= 15) {
> res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
> - rc->rc_range_params[buf_i].range_bpg_offset =
> + vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
> ofs_und12[buf_i] + res;
> } else {
> - rc->rc_range_params[buf_i].range_bpg_offset =
> + vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
> ofs_und15[buf_i];
This would benefit from a temp range_bpg_offset variable, assigned to
vdsc_cfg->rc_range_params[buf_i].range_bpg_offset after the if ladder.
> }
> }
> @@ -143,9 +131,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
> u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
> - const struct rc_parameters *rc_params;
> - struct rc_parameters *rc = NULL;
> - u8 i = 0;
> int ret;
>
> vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
> @@ -169,43 +154,12 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> * parameters
> */
> if (DISPLAY_VER(dev_priv) >= 13) {
> - rc = kmalloc(sizeof(*rc), GFP_KERNEL);
> - if (!rc)
> - return -ENOMEM;
> -
> - calculate_rc_params(rc, vdsc_cfg);
> - rc_params = rc;
> + calculate_rc_params(vdsc_cfg);
> } else {
> ret = drm_dsc_setup_rc_params(vdsc_cfg);
> if (ret)
> return ret;
>
> - goto out;
> - }
> -
> - vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
> - vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
> - vdsc_cfg->initial_offset = rc_params->initial_offset;
> - vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
> - vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
> - vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
> - vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
> -
> - for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> - vdsc_cfg->rc_range_params[i].range_min_qp =
> - rc_params->rc_range_params[i].range_min_qp;
> - vdsc_cfg->rc_range_params[i].range_max_qp =
> - rc_params->rc_range_params[i].range_max_qp;
> - /*
> - * Range BPG Offset uses 2's complement and is only a 6 bits. So
> - * mask it to get only 6 bits.
> - */
> - vdsc_cfg->rc_range_params[i].range_bpg_offset =
> - rc_params->rc_range_params[i].range_bpg_offset &
> - DSC_RANGE_BPG_OFFSET_MASK;
This masking needs to be added to the loop in
calculate_rc_params(). With the temp variable I suggested above, it
could be done while assigning.
With that fixed,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Also, this is awesome stuff, thanks!
> - }
> -
> - if (DISPLAY_VER(dev_priv) < 13) {
> if (compressed_bpp == 6 &&
> vdsc_cfg->bits_per_component == 8)
> vdsc_cfg->rc_quant_incr_limit1 = 23;
> @@ -215,7 +169,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
> }
>
> -out:
> /*
> * BitsPerComponent value determines mux_word_size:
> * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
> @@ -230,8 +183,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
> (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
>
> - kfree(rc);
> -
> return 0;
> }
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH 04/10] drm/i915/dsc: stop using interim structure for calculated params
@ 2023-02-28 16:19 ` Jani Nikula
0 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 16:19 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> Stop using an interim structure rc_parameters for storing calculated
> params and then setting drm_dsc_config using that structure. Instead put
> calculated params into the struct drm_dsc_config directly.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/i915/display/intel_vdsc.c | 89 +++++------------------
> 1 file changed, 20 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index d5a7e9494b23..1ee8d13c9d64 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -18,17 +18,6 @@
> #include "intel_qp_tables.h"
> #include "intel_vdsc.h"
>
> -struct rc_parameters {
> - u16 initial_xmit_delay;
> - u8 first_line_bpg_offset;
> - u16 initial_offset;
> - u8 flatness_min_qp;
> - u8 flatness_max_qp;
> - u8 rc_quant_incr_limit0;
> - u8 rc_quant_incr_limit1;
> - struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
> -};
> -
> bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
> {
> const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -63,8 +52,7 @@ static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
> }
>
> static void
> -calculate_rc_params(struct rc_parameters *rc,
> - struct drm_dsc_config *vdsc_cfg)
> +calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
> {
> int bpc = vdsc_cfg->bits_per_component;
> int bpp = vdsc_cfg->bits_per_pixel >> 4;
> @@ -84,54 +72,54 @@ calculate_rc_params(struct rc_parameters *rc,
> u32 res, buf_i, bpp_i;
>
> if (vdsc_cfg->slice_height >= 8)
> - rc->first_line_bpg_offset =
> + vdsc_cfg->first_line_bpg_offset =
> 12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);
> else
> - rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
> + vdsc_cfg->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
>
> /* Our hw supports only 444 modes as of today */
> if (bpp >= 12)
> - rc->initial_offset = 2048;
> + vdsc_cfg->initial_offset = 2048;
> else if (bpp >= 10)
> - rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
> + vdsc_cfg->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
> else if (bpp >= 8)
> - rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
> + vdsc_cfg->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
> else
> - rc->initial_offset = 6144;
> + vdsc_cfg->initial_offset = 6144;
>
> /* initial_xmit_delay = rc_model_size/2/compression_bpp */
> - rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
> + vdsc_cfg->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
>
> - rc->flatness_min_qp = 3 + qp_bpc_modifier;
> - rc->flatness_max_qp = 12 + qp_bpc_modifier;
> + vdsc_cfg->flatness_min_qp = 3 + qp_bpc_modifier;
> + vdsc_cfg->flatness_max_qp = 12 + qp_bpc_modifier;
>
> - rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
> - rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
> + vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
> + vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
>
> bpp_i = (2 * (bpp - 6));
> for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
> /* Read range_minqp and range_max_qp from qp tables */
> - rc->rc_range_params[buf_i].range_min_qp =
> + vdsc_cfg->rc_range_params[buf_i].range_min_qp =
> intel_lookup_range_min_qp(bpc, buf_i, bpp_i);
> - rc->rc_range_params[buf_i].range_max_qp =
> + vdsc_cfg->rc_range_params[buf_i].range_max_qp =
> intel_lookup_range_max_qp(bpc, buf_i, bpp_i);
>
> /* Calculate range_bgp_offset */
> if (bpp <= 6) {
> - rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
> + vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
> } else if (bpp <= 8) {
> res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
> - rc->rc_range_params[buf_i].range_bpg_offset =
> + vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
> ofs_und6[buf_i] + res;
> } else if (bpp <= 12) {
> - rc->rc_range_params[buf_i].range_bpg_offset =
> + vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
> ofs_und8[buf_i];
> } else if (bpp <= 15) {
> res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
> - rc->rc_range_params[buf_i].range_bpg_offset =
> + vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
> ofs_und12[buf_i] + res;
> } else {
> - rc->rc_range_params[buf_i].range_bpg_offset =
> + vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
> ofs_und15[buf_i];
This would benefit from a temp range_bpg_offset variable, assigned to
vdsc_cfg->rc_range_params[buf_i].range_bpg_offset after the if ladder.
> }
> }
> @@ -143,9 +131,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
> u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
> - const struct rc_parameters *rc_params;
> - struct rc_parameters *rc = NULL;
> - u8 i = 0;
> int ret;
>
> vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
> @@ -169,43 +154,12 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> * parameters
> */
> if (DISPLAY_VER(dev_priv) >= 13) {
> - rc = kmalloc(sizeof(*rc), GFP_KERNEL);
> - if (!rc)
> - return -ENOMEM;
> -
> - calculate_rc_params(rc, vdsc_cfg);
> - rc_params = rc;
> + calculate_rc_params(vdsc_cfg);
> } else {
> ret = drm_dsc_setup_rc_params(vdsc_cfg);
> if (ret)
> return ret;
>
> - goto out;
> - }
> -
> - vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
> - vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
> - vdsc_cfg->initial_offset = rc_params->initial_offset;
> - vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
> - vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
> - vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
> - vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
> -
> - for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> - vdsc_cfg->rc_range_params[i].range_min_qp =
> - rc_params->rc_range_params[i].range_min_qp;
> - vdsc_cfg->rc_range_params[i].range_max_qp =
> - rc_params->rc_range_params[i].range_max_qp;
> - /*
> - * Range BPG Offset uses 2's complement and is only a 6 bits. So
> - * mask it to get only 6 bits.
> - */
> - vdsc_cfg->rc_range_params[i].range_bpg_offset =
> - rc_params->rc_range_params[i].range_bpg_offset &
> - DSC_RANGE_BPG_OFFSET_MASK;
This masking needs to be added to the loop in
calculate_rc_params(). With the temp variable I suggested above, it
could be done while assigning.
With that fixed,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Also, this is awesome stuff, thanks!
> - }
> -
> - if (DISPLAY_VER(dev_priv) < 13) {
> if (compressed_bpp == 6 &&
> vdsc_cfg->bits_per_component == 8)
> vdsc_cfg->rc_quant_incr_limit1 = 23;
> @@ -215,7 +169,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
> }
>
> -out:
> /*
> * BitsPerComponent value determines mux_word_size:
> * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
> @@ -230,8 +183,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
> (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
>
> - kfree(rc);
> -
> return 0;
> }
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 05/10] drm/display/dsc: use flat array for rc_parameters lookup
2023-02-28 11:33 ` Dmitry Baryshkov
(?)
@ 2023-02-28 16:28 ` Jani Nikula
-1 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 16:28 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> Next commits are going to add support for additional RC parameter lookup
> tables. These tables are going to use different bpp/bpc combinations,
> thus it makes little sense to keep the 2d array for RC parameters.
> Switch to using the flat array.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 188 +++++++++++------------
> 1 file changed, 88 insertions(+), 100 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> index deaa84722bd4..a6d11f474656 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -307,24 +307,6 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
> }
> EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
>
> -enum ROW_INDEX_BPP {
> - ROW_INDEX_6BPP = 0,
> - ROW_INDEX_8BPP,
> - ROW_INDEX_10BPP,
> - ROW_INDEX_12BPP,
> - ROW_INDEX_15BPP,
> - MAX_ROW_INDEX
> -};
> -
> -enum COLUMN_INDEX_BPC {
> - COLUMN_INDEX_8BPC = 0,
> - COLUMN_INDEX_10BPC,
> - COLUMN_INDEX_12BPC,
> - COLUMN_INDEX_14BPC,
> - COLUMN_INDEX_16BPC,
> - MAX_COLUMN_INDEX
> -};
> -
> struct rc_parameters {
> u16 initial_xmit_delay;
> u8 first_line_bpg_offset;
> @@ -336,12 +318,20 @@ struct rc_parameters {
> struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
> };
>
> +struct rc_parameters_data {
> + u8 bpp;
> + u8 bpc;
> + struct rc_parameters params;
> +};
> +
> +#define DSC_BPP(bpp) ((bpp) << 4)
> +
> /*
> * Selected Rate Control Related Parameter Recommended Values
> * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> */
> -static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> -{
> +static const struct rc_parameters_data rc_parameters[] = {
> +{ DSC_BPP(6), 8,
I was kind of hoping for a patch that would clean up the hideous
indentation in the tables. Please at least let's not add more with the
one space indent?
> /* 6BPP/8BPC */
With designated initializers I think we could just toss the comments
out.
.bpp = DSC_BPP(6), .bpc = 8,
With that,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> { 768, 15, 6144, 3, 13, 11, 11, {
> { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
> @@ -349,7 +339,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
> { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(6), 10,
> /* 6BPP/10BPC */
> { 768, 15, 6144, 7, 17, 15, 15, {
> { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
> @@ -358,7 +350,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
> { 17, 18, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(6), 12,
> /* 6BPP/12BPC */
> { 768, 15, 6144, 11, 21, 19, 19, {
> { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
> @@ -367,7 +361,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
> { 21, 22, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(6), 14,
> /* 6BPP/14BPC */
> { 768, 15, 6144, 15, 25, 23, 23, {
> { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
> @@ -376,7 +372,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
> { 25, 26, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(6), 16,
> /* 6BPP/16BPC */
> { 768, 15, 6144, 19, 29, 27, 27, {
> { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
> @@ -385,9 +383,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
> { 29, 30, -12 }
> }
> - },
> + }
> },
> -{
> +{ DSC_BPP(8), 8,
> /* 8BPP/8BPC */
> { 512, 12, 6144, 3, 12, 11, 11, {
> { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> @@ -395,7 +393,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(8), 10,
> /* 8BPP/10BPC */
> { 512, 12, 6144, 7, 16, 15, 15, {
> /*
> @@ -407,7 +407,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(8), 12,
> /* 8BPP/12BPC */
> { 512, 12, 6144, 11, 20, 19, 19, {
> { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> @@ -416,7 +418,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> { 21, 23, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(8), 14,
> /* 8BPP/14BPC */
> { 512, 12, 6144, 15, 24, 23, 23, {
> { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
> @@ -425,7 +429,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
> { 24, 25, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(8), 16,
> /* 8BPP/16BPC */
> { 512, 12, 6144, 19, 28, 27, 27, {
> { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
> @@ -434,9 +440,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
> { 28, 29, -12 }
> }
> - },
> + }
> },
> -{
> +{ DSC_BPP(10), 8,
> /* 10BPP/8BPC */
> { 410, 15, 5632, 3, 12, 11, 11, {
> { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
> @@ -444,7 +450,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
> { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(10), 10,
> /* 10BPP/10BPC */
> { 410, 15, 5632, 7, 16, 15, 15, {
> { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
> @@ -452,7 +460,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
> { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(10), 12,
> /* 10BPP/12BPC */
> { 410, 15, 5632, 11, 20, 19, 19, {
> { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
> @@ -461,7 +471,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
> { 19, 20, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(10), 14,
> /* 10BPP/14BPC */
> { 410, 15, 5632, 15, 24, 23, 23, {
> { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
> @@ -470,7 +482,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
> { 23, 24, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(10), 16,
> /* 10BPP/16BPC */
> { 410, 15, 5632, 19, 28, 27, 27, {
> { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
> @@ -479,9 +493,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
> { 27, 28, -12 }
> }
> - },
> + }
> },
> -{
> +{ DSC_BPP(12), 8,
> /* 12BPP/8BPC */
> { 341, 15, 2048, 3, 12, 11, 11, {
> { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> @@ -489,7 +503,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(12), 10,
> /* 12BPP/10BPC */
> { 341, 15, 2048, 7, 16, 15, 15, {
> { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> @@ -497,7 +513,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(12), 12,
> /* 12BPP/12BPC */
> { 341, 15, 2048, 11, 20, 19, 19, {
> { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> @@ -506,7 +524,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> { 21, 23, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(12), 14,
> /* 12BPP/14BPC */
> { 341, 15, 2048, 15, 24, 23, 23, {
> { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
> @@ -515,7 +535,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
> { 22, 23, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(12), 16,
> /* 12BPP/16BPC */
> { 341, 15, 2048, 19, 28, 27, 27, {
> { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
> @@ -524,9 +546,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
> { 26, 27, -12 }
> }
> - },
> + }
> },
> -{
> +{ DSC_BPP(15), 8,
> /* 15BPP/8BPC */
> { 273, 15, 2048, 3, 12, 11, 11, {
> { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
> @@ -534,7 +556,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
> { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(15), 10,
> /* 15BPP/10BPC */
> { 273, 15, 2048, 7, 16, 15, 15, {
> { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
> @@ -542,7 +566,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
> { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(15), 12,
> /* 15BPP/12BPC */
> { 273, 15, 2048, 11, 20, 19, 19, {
> { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
> @@ -551,7 +577,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
> { 16, 17, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(15), 14,
> /* 15BPP/14BPC */
> { 273, 15, 2048, 15, 24, 23, 23, {
> { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
> @@ -560,7 +588,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
> { 20, 21, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(15), 16,
> /* 15BPP/16BPC */
> { 273, 15, 2048, 19, 28, 27, 27, {
> { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
> @@ -570,59 +600,21 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 24, 25, -12 }
> }
> }
> -}
> +},
> +{ /* sentinel */ }
> };
>
> -static int get_row_index_for_rc_params(u16 compressed_bpp)
> -{
> - switch (compressed_bpp) {
> - case 6:
> - return ROW_INDEX_6BPP;
> - case 8:
> - return ROW_INDEX_8BPP;
> - case 10:
> - return ROW_INDEX_10BPP;
> - case 12:
> - return ROW_INDEX_12BPP;
> - case 15:
> - return ROW_INDEX_15BPP;
> - default:
> - return -EINVAL;
> - }
> -}
> -
> -static int get_column_index_for_rc_params(u8 bits_per_component)
> -{
> - switch (bits_per_component) {
> - case 8:
> - return COLUMN_INDEX_8BPC;
> - case 10:
> - return COLUMN_INDEX_10BPC;
> - case 12:
> - return COLUMN_INDEX_12BPC;
> - case 14:
> - return COLUMN_INDEX_14BPC;
> - case 16:
> - return COLUMN_INDEX_16BPC;
> - default:
> - return -EINVAL;
> - }
> -}
> -
> -static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
> +static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> u8 bits_per_component)
> {
> - int row_index, column_index;
> -
> - row_index = get_row_index_for_rc_params(compressed_bpp);
> - if (row_index < 0)
> - return NULL;
> + int i;
>
> - column_index = get_column_index_for_rc_params(bits_per_component);
> - if (column_index < 0)
> - return NULL;
> + for (i = 0; rc_parameters[i].bpp; i++)
> + if (rc_parameters[i].bpp == dsc_bpp &&
> + rc_parameters[i].bpc == bits_per_component)
> + return &rc_parameters[i].params;
>
> - return &rc_parameters[row_index][column_index];
> + return NULL;
> }
>
> /**
> @@ -636,11 +628,7 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> const struct rc_parameters *rc_params;
> int i;
>
> - /* fractional BPP is not supported */
> - if (vdsc_cfg->bits_per_pixel & 0xf)
> - return -EINVAL;
> -
> - rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
> + rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
> vdsc_cfg->bits_per_component);
> if (!rc_params)
> return -EINVAL;
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH 05/10] drm/display/dsc: use flat array for rc_parameters lookup
@ 2023-02-28 16:28 ` Jani Nikula
0 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 16:28 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> Next commits are going to add support for additional RC parameter lookup
> tables. These tables are going to use different bpp/bpc combinations,
> thus it makes little sense to keep the 2d array for RC parameters.
> Switch to using the flat array.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 188 +++++++++++------------
> 1 file changed, 88 insertions(+), 100 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> index deaa84722bd4..a6d11f474656 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -307,24 +307,6 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
> }
> EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
>
> -enum ROW_INDEX_BPP {
> - ROW_INDEX_6BPP = 0,
> - ROW_INDEX_8BPP,
> - ROW_INDEX_10BPP,
> - ROW_INDEX_12BPP,
> - ROW_INDEX_15BPP,
> - MAX_ROW_INDEX
> -};
> -
> -enum COLUMN_INDEX_BPC {
> - COLUMN_INDEX_8BPC = 0,
> - COLUMN_INDEX_10BPC,
> - COLUMN_INDEX_12BPC,
> - COLUMN_INDEX_14BPC,
> - COLUMN_INDEX_16BPC,
> - MAX_COLUMN_INDEX
> -};
> -
> struct rc_parameters {
> u16 initial_xmit_delay;
> u8 first_line_bpg_offset;
> @@ -336,12 +318,20 @@ struct rc_parameters {
> struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
> };
>
> +struct rc_parameters_data {
> + u8 bpp;
> + u8 bpc;
> + struct rc_parameters params;
> +};
> +
> +#define DSC_BPP(bpp) ((bpp) << 4)
> +
> /*
> * Selected Rate Control Related Parameter Recommended Values
> * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> */
> -static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> -{
> +static const struct rc_parameters_data rc_parameters[] = {
> +{ DSC_BPP(6), 8,
I was kind of hoping for a patch that would clean up the hideous
indentation in the tables. Please at least let's not add more with the
one space indent?
> /* 6BPP/8BPC */
With designated initializers I think we could just toss the comments
out.
.bpp = DSC_BPP(6), .bpc = 8,
With that,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> { 768, 15, 6144, 3, 13, 11, 11, {
> { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
> @@ -349,7 +339,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
> { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(6), 10,
> /* 6BPP/10BPC */
> { 768, 15, 6144, 7, 17, 15, 15, {
> { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
> @@ -358,7 +350,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
> { 17, 18, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(6), 12,
> /* 6BPP/12BPC */
> { 768, 15, 6144, 11, 21, 19, 19, {
> { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
> @@ -367,7 +361,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
> { 21, 22, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(6), 14,
> /* 6BPP/14BPC */
> { 768, 15, 6144, 15, 25, 23, 23, {
> { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
> @@ -376,7 +372,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
> { 25, 26, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(6), 16,
> /* 6BPP/16BPC */
> { 768, 15, 6144, 19, 29, 27, 27, {
> { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
> @@ -385,9 +383,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
> { 29, 30, -12 }
> }
> - },
> + }
> },
> -{
> +{ DSC_BPP(8), 8,
> /* 8BPP/8BPC */
> { 512, 12, 6144, 3, 12, 11, 11, {
> { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> @@ -395,7 +393,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(8), 10,
> /* 8BPP/10BPC */
> { 512, 12, 6144, 7, 16, 15, 15, {
> /*
> @@ -407,7 +407,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(8), 12,
> /* 8BPP/12BPC */
> { 512, 12, 6144, 11, 20, 19, 19, {
> { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> @@ -416,7 +418,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> { 21, 23, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(8), 14,
> /* 8BPP/14BPC */
> { 512, 12, 6144, 15, 24, 23, 23, {
> { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
> @@ -425,7 +429,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
> { 24, 25, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(8), 16,
> /* 8BPP/16BPC */
> { 512, 12, 6144, 19, 28, 27, 27, {
> { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
> @@ -434,9 +440,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
> { 28, 29, -12 }
> }
> - },
> + }
> },
> -{
> +{ DSC_BPP(10), 8,
> /* 10BPP/8BPC */
> { 410, 15, 5632, 3, 12, 11, 11, {
> { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
> @@ -444,7 +450,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
> { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(10), 10,
> /* 10BPP/10BPC */
> { 410, 15, 5632, 7, 16, 15, 15, {
> { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
> @@ -452,7 +460,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
> { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(10), 12,
> /* 10BPP/12BPC */
> { 410, 15, 5632, 11, 20, 19, 19, {
> { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
> @@ -461,7 +471,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
> { 19, 20, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(10), 14,
> /* 10BPP/14BPC */
> { 410, 15, 5632, 15, 24, 23, 23, {
> { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
> @@ -470,7 +482,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
> { 23, 24, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(10), 16,
> /* 10BPP/16BPC */
> { 410, 15, 5632, 19, 28, 27, 27, {
> { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
> @@ -479,9 +493,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
> { 27, 28, -12 }
> }
> - },
> + }
> },
> -{
> +{ DSC_BPP(12), 8,
> /* 12BPP/8BPC */
> { 341, 15, 2048, 3, 12, 11, 11, {
> { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> @@ -489,7 +503,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(12), 10,
> /* 12BPP/10BPC */
> { 341, 15, 2048, 7, 16, 15, 15, {
> { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> @@ -497,7 +513,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(12), 12,
> /* 12BPP/12BPC */
> { 341, 15, 2048, 11, 20, 19, 19, {
> { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> @@ -506,7 +524,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> { 21, 23, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(12), 14,
> /* 12BPP/14BPC */
> { 341, 15, 2048, 15, 24, 23, 23, {
> { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
> @@ -515,7 +535,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
> { 22, 23, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(12), 16,
> /* 12BPP/16BPC */
> { 341, 15, 2048, 19, 28, 27, 27, {
> { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
> @@ -524,9 +546,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
> { 26, 27, -12 }
> }
> - },
> + }
> },
> -{
> +{ DSC_BPP(15), 8,
> /* 15BPP/8BPC */
> { 273, 15, 2048, 3, 12, 11, 11, {
> { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
> @@ -534,7 +556,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
> { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(15), 10,
> /* 15BPP/10BPC */
> { 273, 15, 2048, 7, 16, 15, 15, {
> { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
> @@ -542,7 +566,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
> { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(15), 12,
> /* 15BPP/12BPC */
> { 273, 15, 2048, 11, 20, 19, 19, {
> { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
> @@ -551,7 +577,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
> { 16, 17, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(15), 14,
> /* 15BPP/14BPC */
> { 273, 15, 2048, 15, 24, 23, 23, {
> { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
> @@ -560,7 +588,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
> { 20, 21, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(15), 16,
> /* 15BPP/16BPC */
> { 273, 15, 2048, 19, 28, 27, 27, {
> { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
> @@ -570,59 +600,21 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 24, 25, -12 }
> }
> }
> -}
> +},
> +{ /* sentinel */ }
> };
>
> -static int get_row_index_for_rc_params(u16 compressed_bpp)
> -{
> - switch (compressed_bpp) {
> - case 6:
> - return ROW_INDEX_6BPP;
> - case 8:
> - return ROW_INDEX_8BPP;
> - case 10:
> - return ROW_INDEX_10BPP;
> - case 12:
> - return ROW_INDEX_12BPP;
> - case 15:
> - return ROW_INDEX_15BPP;
> - default:
> - return -EINVAL;
> - }
> -}
> -
> -static int get_column_index_for_rc_params(u8 bits_per_component)
> -{
> - switch (bits_per_component) {
> - case 8:
> - return COLUMN_INDEX_8BPC;
> - case 10:
> - return COLUMN_INDEX_10BPC;
> - case 12:
> - return COLUMN_INDEX_12BPC;
> - case 14:
> - return COLUMN_INDEX_14BPC;
> - case 16:
> - return COLUMN_INDEX_16BPC;
> - default:
> - return -EINVAL;
> - }
> -}
> -
> -static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
> +static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> u8 bits_per_component)
> {
> - int row_index, column_index;
> -
> - row_index = get_row_index_for_rc_params(compressed_bpp);
> - if (row_index < 0)
> - return NULL;
> + int i;
>
> - column_index = get_column_index_for_rc_params(bits_per_component);
> - if (column_index < 0)
> - return NULL;
> + for (i = 0; rc_parameters[i].bpp; i++)
> + if (rc_parameters[i].bpp == dsc_bpp &&
> + rc_parameters[i].bpc == bits_per_component)
> + return &rc_parameters[i].params;
>
> - return &rc_parameters[row_index][column_index];
> + return NULL;
> }
>
> /**
> @@ -636,11 +628,7 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> const struct rc_parameters *rc_params;
> int i;
>
> - /* fractional BPP is not supported */
> - if (vdsc_cfg->bits_per_pixel & 0xf)
> - return -EINVAL;
> -
> - rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
> + rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
> vdsc_cfg->bits_per_component);
> if (!rc_params)
> return -EINVAL;
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 05/10] drm/display/dsc: use flat array for rc_parameters lookup
@ 2023-02-28 16:28 ` Jani Nikula
0 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 16:28 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> Next commits are going to add support for additional RC parameter lookup
> tables. These tables are going to use different bpp/bpc combinations,
> thus it makes little sense to keep the 2d array for RC parameters.
> Switch to using the flat array.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 188 +++++++++++------------
> 1 file changed, 88 insertions(+), 100 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> index deaa84722bd4..a6d11f474656 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -307,24 +307,6 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
> }
> EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
>
> -enum ROW_INDEX_BPP {
> - ROW_INDEX_6BPP = 0,
> - ROW_INDEX_8BPP,
> - ROW_INDEX_10BPP,
> - ROW_INDEX_12BPP,
> - ROW_INDEX_15BPP,
> - MAX_ROW_INDEX
> -};
> -
> -enum COLUMN_INDEX_BPC {
> - COLUMN_INDEX_8BPC = 0,
> - COLUMN_INDEX_10BPC,
> - COLUMN_INDEX_12BPC,
> - COLUMN_INDEX_14BPC,
> - COLUMN_INDEX_16BPC,
> - MAX_COLUMN_INDEX
> -};
> -
> struct rc_parameters {
> u16 initial_xmit_delay;
> u8 first_line_bpg_offset;
> @@ -336,12 +318,20 @@ struct rc_parameters {
> struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
> };
>
> +struct rc_parameters_data {
> + u8 bpp;
> + u8 bpc;
> + struct rc_parameters params;
> +};
> +
> +#define DSC_BPP(bpp) ((bpp) << 4)
> +
> /*
> * Selected Rate Control Related Parameter Recommended Values
> * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> */
> -static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> -{
> +static const struct rc_parameters_data rc_parameters[] = {
> +{ DSC_BPP(6), 8,
I was kind of hoping for a patch that would clean up the hideous
indentation in the tables. Please at least let's not add more with the
one space indent?
> /* 6BPP/8BPC */
With designated initializers I think we could just toss the comments
out.
.bpp = DSC_BPP(6), .bpc = 8,
With that,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> { 768, 15, 6144, 3, 13, 11, 11, {
> { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
> @@ -349,7 +339,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
> { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(6), 10,
> /* 6BPP/10BPC */
> { 768, 15, 6144, 7, 17, 15, 15, {
> { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
> @@ -358,7 +350,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
> { 17, 18, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(6), 12,
> /* 6BPP/12BPC */
> { 768, 15, 6144, 11, 21, 19, 19, {
> { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
> @@ -367,7 +361,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
> { 21, 22, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(6), 14,
> /* 6BPP/14BPC */
> { 768, 15, 6144, 15, 25, 23, 23, {
> { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
> @@ -376,7 +372,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
> { 25, 26, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(6), 16,
> /* 6BPP/16BPC */
> { 768, 15, 6144, 19, 29, 27, 27, {
> { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
> @@ -385,9 +383,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
> { 29, 30, -12 }
> }
> - },
> + }
> },
> -{
> +{ DSC_BPP(8), 8,
> /* 8BPP/8BPC */
> { 512, 12, 6144, 3, 12, 11, 11, {
> { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> @@ -395,7 +393,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(8), 10,
> /* 8BPP/10BPC */
> { 512, 12, 6144, 7, 16, 15, 15, {
> /*
> @@ -407,7 +407,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(8), 12,
> /* 8BPP/12BPC */
> { 512, 12, 6144, 11, 20, 19, 19, {
> { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> @@ -416,7 +418,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> { 21, 23, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(8), 14,
> /* 8BPP/14BPC */
> { 512, 12, 6144, 15, 24, 23, 23, {
> { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
> @@ -425,7 +429,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
> { 24, 25, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(8), 16,
> /* 8BPP/16BPC */
> { 512, 12, 6144, 19, 28, 27, 27, {
> { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
> @@ -434,9 +440,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
> { 28, 29, -12 }
> }
> - },
> + }
> },
> -{
> +{ DSC_BPP(10), 8,
> /* 10BPP/8BPC */
> { 410, 15, 5632, 3, 12, 11, 11, {
> { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
> @@ -444,7 +450,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
> { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(10), 10,
> /* 10BPP/10BPC */
> { 410, 15, 5632, 7, 16, 15, 15, {
> { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
> @@ -452,7 +460,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
> { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(10), 12,
> /* 10BPP/12BPC */
> { 410, 15, 5632, 11, 20, 19, 19, {
> { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
> @@ -461,7 +471,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
> { 19, 20, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(10), 14,
> /* 10BPP/14BPC */
> { 410, 15, 5632, 15, 24, 23, 23, {
> { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
> @@ -470,7 +482,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
> { 23, 24, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(10), 16,
> /* 10BPP/16BPC */
> { 410, 15, 5632, 19, 28, 27, 27, {
> { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
> @@ -479,9 +493,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
> { 27, 28, -12 }
> }
> - },
> + }
> },
> -{
> +{ DSC_BPP(12), 8,
> /* 12BPP/8BPC */
> { 341, 15, 2048, 3, 12, 11, 11, {
> { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> @@ -489,7 +503,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(12), 10,
> /* 12BPP/10BPC */
> { 341, 15, 2048, 7, 16, 15, 15, {
> { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> @@ -497,7 +513,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(12), 12,
> /* 12BPP/12BPC */
> { 341, 15, 2048, 11, 20, 19, 19, {
> { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> @@ -506,7 +524,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> { 21, 23, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(12), 14,
> /* 12BPP/14BPC */
> { 341, 15, 2048, 15, 24, 23, 23, {
> { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
> @@ -515,7 +535,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
> { 22, 23, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(12), 16,
> /* 12BPP/16BPC */
> { 341, 15, 2048, 19, 28, 27, 27, {
> { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
> @@ -524,9 +546,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
> { 26, 27, -12 }
> }
> - },
> + }
> },
> -{
> +{ DSC_BPP(15), 8,
> /* 15BPP/8BPC */
> { 273, 15, 2048, 3, 12, 11, 11, {
> { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
> @@ -534,7 +556,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
> { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(15), 10,
> /* 15BPP/10BPC */
> { 273, 15, 2048, 7, 16, 15, 15, {
> { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
> @@ -542,7 +566,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
> { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(15), 12,
> /* 15BPP/12BPC */
> { 273, 15, 2048, 11, 20, 19, 19, {
> { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
> @@ -551,7 +577,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
> { 16, 17, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(15), 14,
> /* 15BPP/14BPC */
> { 273, 15, 2048, 15, 24, 23, 23, {
> { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
> @@ -560,7 +588,9 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
> { 20, 21, -12 }
> }
> - },
> + }
> +},
> +{ DSC_BPP(15), 16,
> /* 15BPP/16BPC */
> { 273, 15, 2048, 19, 28, 27, 27, {
> { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
> @@ -570,59 +600,21 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> { 24, 25, -12 }
> }
> }
> -}
> +},
> +{ /* sentinel */ }
> };
>
> -static int get_row_index_for_rc_params(u16 compressed_bpp)
> -{
> - switch (compressed_bpp) {
> - case 6:
> - return ROW_INDEX_6BPP;
> - case 8:
> - return ROW_INDEX_8BPP;
> - case 10:
> - return ROW_INDEX_10BPP;
> - case 12:
> - return ROW_INDEX_12BPP;
> - case 15:
> - return ROW_INDEX_15BPP;
> - default:
> - return -EINVAL;
> - }
> -}
> -
> -static int get_column_index_for_rc_params(u8 bits_per_component)
> -{
> - switch (bits_per_component) {
> - case 8:
> - return COLUMN_INDEX_8BPC;
> - case 10:
> - return COLUMN_INDEX_10BPC;
> - case 12:
> - return COLUMN_INDEX_12BPC;
> - case 14:
> - return COLUMN_INDEX_14BPC;
> - case 16:
> - return COLUMN_INDEX_16BPC;
> - default:
> - return -EINVAL;
> - }
> -}
> -
> -static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
> +static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> u8 bits_per_component)
> {
> - int row_index, column_index;
> -
> - row_index = get_row_index_for_rc_params(compressed_bpp);
> - if (row_index < 0)
> - return NULL;
> + int i;
>
> - column_index = get_column_index_for_rc_params(bits_per_component);
> - if (column_index < 0)
> - return NULL;
> + for (i = 0; rc_parameters[i].bpp; i++)
> + if (rc_parameters[i].bpp == dsc_bpp &&
> + rc_parameters[i].bpc == bits_per_component)
> + return &rc_parameters[i].params;
>
> - return &rc_parameters[row_index][column_index];
> + return NULL;
> }
>
> /**
> @@ -636,11 +628,7 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> const struct rc_parameters *rc_params;
> int i;
>
> - /* fractional BPP is not supported */
> - if (vdsc_cfg->bits_per_pixel & 0xf)
> - return -EINVAL;
> -
> - rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
> + rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
> vdsc_cfg->bits_per_component);
> if (!rc_params)
> return -EINVAL;
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 07/10] drm/display/dsc: include the rest of pre-SCR parameters
2023-02-28 11:33 ` Dmitry Baryshkov
(?)
@ 2023-02-28 16:31 ` Jani Nikula
-1 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 16:31 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> DSC model contains pre-SCR RC parameters for other bpp/bpc combinations,
> include them here for completeness.
Need to run now, note to self:
Does i915 use the arrays to limit the bpp/bpc combos supported by
hardware? Do we need to add separate limiting in i915.
BR,
Jani.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 72 ++++++++++++++++++++++++
> 1 file changed, 72 insertions(+)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> index 51794b40526a..1612536014ea 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -327,6 +327,16 @@ struct rc_parameters_data {
> #define DSC_BPP(bpp) ((bpp) << 4)
>
> static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> +{ DSC_BPP(6), 8,
> + /* 6BPP/8BPC */
> + { 683, 15, 6144, 3, 13, 11, 11, {
> + { 0, 2, 0 }, { 1, 4, -2 }, { 3, 6, -2 }, { 4, 6, -4 },
> + { 5, 7, -6 }, { 5, 7, -6 }, { 6, 7, -6 }, { 6, 8, -8 },
> + { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 }, { 10, 12, -12 },
> + { 10, 13, -12 }, { 12, 14, -12 }, { 15, 15, -12 }
> + }
> + }
> +},
> { DSC_BPP(8), 8,
> /* 8BPP/8BPC */
> { 512, 12, 6144, 3, 12, 11, 11, {
> @@ -362,6 +372,37 @@ static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> }
> }
> },
> +{ DSC_BPP(10), 8,
> + /* 10BPP/8BPC */
> + { 410, 12, 5632, 3, 12, 11, 11, {
> + { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 11, -10 },
> + { 5, 12, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(10), 10,
> + /* 10BPP/10BPC */
> + { 410, 12, 5632, 7, 16, 15, 15, {
> + { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
> + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 15, -10 },
> + { 9, 16, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(10), 12,
> + /* 10BPP/12BPC */
> + { 410, 12, 5632, 11, 20, 19, 19, {
> + { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
> + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
> + { 13, 19, -10 }, { 13, 20, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> +},
> { DSC_BPP(12), 8,
> /* 12BPP/8BPC */
> { 341, 15, 2048, 3, 12, 11, 11, {
> @@ -393,6 +434,37 @@ static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> }
> }
> },
> +{ DSC_BPP(15), 8,
> + /* 15BPP/8BPC */
> + { 273, 15, 2048, 3, 12, 11, 11, {
> + { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
> + { 1, 2, 2 }, { 1, 3, 0 }, { 1, 4, -2 }, { 2, 4, -4 },
> + { 3, 4, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 5, 7, -10 },
> + { 5, 8, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(15), 10,
> + /* 15BPP/10BPC */
> + { 273, 15, 2048, 7, 16, 15, 15, {
> + { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
> + { 5, 6, 2 }, { 5, 7, 0 }, { 5, 8, -2 }, { 6, 8, -4 },
> + { 7, 8, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 },
> + { 9, 12, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(15), 12,
> + /* 15BPP/12BPC */
> + { 273, 15, 2048, 11, 20, 19, 19, {
> + { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
> + { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
> + { 11, 12, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
> + { 13, 15, -10 }, { 13, 16, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> +},
> { /* sentinel */ }
> };
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 07/10] drm/display/dsc: include the rest of pre-SCR parameters
@ 2023-02-28 16:31 ` Jani Nikula
0 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 16:31 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> DSC model contains pre-SCR RC parameters for other bpp/bpc combinations,
> include them here for completeness.
Need to run now, note to self:
Does i915 use the arrays to limit the bpp/bpc combos supported by
hardware? Do we need to add separate limiting in i915.
BR,
Jani.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 72 ++++++++++++++++++++++++
> 1 file changed, 72 insertions(+)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> index 51794b40526a..1612536014ea 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -327,6 +327,16 @@ struct rc_parameters_data {
> #define DSC_BPP(bpp) ((bpp) << 4)
>
> static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> +{ DSC_BPP(6), 8,
> + /* 6BPP/8BPC */
> + { 683, 15, 6144, 3, 13, 11, 11, {
> + { 0, 2, 0 }, { 1, 4, -2 }, { 3, 6, -2 }, { 4, 6, -4 },
> + { 5, 7, -6 }, { 5, 7, -6 }, { 6, 7, -6 }, { 6, 8, -8 },
> + { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 }, { 10, 12, -12 },
> + { 10, 13, -12 }, { 12, 14, -12 }, { 15, 15, -12 }
> + }
> + }
> +},
> { DSC_BPP(8), 8,
> /* 8BPP/8BPC */
> { 512, 12, 6144, 3, 12, 11, 11, {
> @@ -362,6 +372,37 @@ static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> }
> }
> },
> +{ DSC_BPP(10), 8,
> + /* 10BPP/8BPC */
> + { 410, 12, 5632, 3, 12, 11, 11, {
> + { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 11, -10 },
> + { 5, 12, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(10), 10,
> + /* 10BPP/10BPC */
> + { 410, 12, 5632, 7, 16, 15, 15, {
> + { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
> + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 15, -10 },
> + { 9, 16, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(10), 12,
> + /* 10BPP/12BPC */
> + { 410, 12, 5632, 11, 20, 19, 19, {
> + { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
> + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
> + { 13, 19, -10 }, { 13, 20, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> +},
> { DSC_BPP(12), 8,
> /* 12BPP/8BPC */
> { 341, 15, 2048, 3, 12, 11, 11, {
> @@ -393,6 +434,37 @@ static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> }
> }
> },
> +{ DSC_BPP(15), 8,
> + /* 15BPP/8BPC */
> + { 273, 15, 2048, 3, 12, 11, 11, {
> + { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
> + { 1, 2, 2 }, { 1, 3, 0 }, { 1, 4, -2 }, { 2, 4, -4 },
> + { 3, 4, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 5, 7, -10 },
> + { 5, 8, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(15), 10,
> + /* 15BPP/10BPC */
> + { 273, 15, 2048, 7, 16, 15, 15, {
> + { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
> + { 5, 6, 2 }, { 5, 7, 0 }, { 5, 8, -2 }, { 6, 8, -4 },
> + { 7, 8, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 },
> + { 9, 12, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(15), 12,
> + /* 15BPP/12BPC */
> + { 273, 15, 2048, 11, 20, 19, 19, {
> + { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
> + { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
> + { 11, 12, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
> + { 13, 15, -10 }, { 13, 16, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> +},
> { /* sentinel */ }
> };
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH 07/10] drm/display/dsc: include the rest of pre-SCR parameters
@ 2023-02-28 16:31 ` Jani Nikula
0 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 16:31 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> DSC model contains pre-SCR RC parameters for other bpp/bpc combinations,
> include them here for completeness.
Need to run now, note to self:
Does i915 use the arrays to limit the bpp/bpc combos supported by
hardware? Do we need to add separate limiting in i915.
BR,
Jani.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 72 ++++++++++++++++++++++++
> 1 file changed, 72 insertions(+)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> index 51794b40526a..1612536014ea 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -327,6 +327,16 @@ struct rc_parameters_data {
> #define DSC_BPP(bpp) ((bpp) << 4)
>
> static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> +{ DSC_BPP(6), 8,
> + /* 6BPP/8BPC */
> + { 683, 15, 6144, 3, 13, 11, 11, {
> + { 0, 2, 0 }, { 1, 4, -2 }, { 3, 6, -2 }, { 4, 6, -4 },
> + { 5, 7, -6 }, { 5, 7, -6 }, { 6, 7, -6 }, { 6, 8, -8 },
> + { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 }, { 10, 12, -12 },
> + { 10, 13, -12 }, { 12, 14, -12 }, { 15, 15, -12 }
> + }
> + }
> +},
> { DSC_BPP(8), 8,
> /* 8BPP/8BPC */
> { 512, 12, 6144, 3, 12, 11, 11, {
> @@ -362,6 +372,37 @@ static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> }
> }
> },
> +{ DSC_BPP(10), 8,
> + /* 10BPP/8BPC */
> + { 410, 12, 5632, 3, 12, 11, 11, {
> + { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 11, -10 },
> + { 5, 12, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(10), 10,
> + /* 10BPP/10BPC */
> + { 410, 12, 5632, 7, 16, 15, 15, {
> + { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
> + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 15, -10 },
> + { 9, 16, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(10), 12,
> + /* 10BPP/12BPC */
> + { 410, 12, 5632, 11, 20, 19, 19, {
> + { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
> + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
> + { 13, 19, -10 }, { 13, 20, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> +},
> { DSC_BPP(12), 8,
> /* 12BPP/8BPC */
> { 341, 15, 2048, 3, 12, 11, 11, {
> @@ -393,6 +434,37 @@ static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> }
> }
> },
> +{ DSC_BPP(15), 8,
> + /* 15BPP/8BPC */
> + { 273, 15, 2048, 3, 12, 11, 11, {
> + { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
> + { 1, 2, 2 }, { 1, 3, 0 }, { 1, 4, -2 }, { 2, 4, -4 },
> + { 3, 4, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 5, 7, -10 },
> + { 5, 8, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(15), 10,
> + /* 15BPP/10BPC */
> + { 273, 15, 2048, 7, 16, 15, 15, {
> + { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
> + { 5, 6, 2 }, { 5, 7, 0 }, { 5, 8, -2 }, { 6, 8, -4 },
> + { 7, 8, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 },
> + { 9, 12, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(15), 12,
> + /* 15BPP/12BPC */
> + { 273, 15, 2048, 11, 20, 19, 19, {
> + { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
> + { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
> + { 11, 12, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
> + { 13, 15, -10 }, { 13, 16, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> +},
> { /* sentinel */ }
> };
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 06/10] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
2023-02-28 11:33 ` Dmitry Baryshkov
(?)
@ 2023-02-28 16:33 ` Jani Nikula
-1 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 16:33 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> The array of rc_parameters contains a mixture of parameters from DSC 1.1
> and DSC 1.2 standards. Split these tow configuration arrays in
> preparation to adding more configuration data.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 127 ++++++++++++++++++----
> drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
> include/drm/display/drm_dsc_helper.h | 7 +-
> 3 files changed, 119 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> index a6d11f474656..51794b40526a 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -326,11 +326,81 @@ struct rc_parameters_data {
>
> #define DSC_BPP(bpp) ((bpp) << 4)
>
> +static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> +{ DSC_BPP(8), 8,
> + /* 8BPP/8BPC */
I still dislike this indentation...
> + { 512, 12, 6144, 3, 12, 11, 11, {
> + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(8), 10,
> + /* 8BPP/10BPC */
> + { 512, 12, 6144, 7, 16, 15, 15, {
> + /*
> + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> + * VESA DSC 1.1 Table E-5 sets it to 4.
> + */
> + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(8), 12,
> + /* 8BPP/12BPC */
> + { 512, 12, 6144, 11, 20, 19, 19, {
> + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(12), 8,
> + /* 12BPP/8BPC */
> + { 341, 15, 2048, 3, 12, 11, 11, {
> + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(12), 10,
> + /* 12BPP/10BPC */
> + { 341, 15, 2048, 7, 16, 15, 15, {
> + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(12), 12,
> + /* 12BPP/12BPC */
> + { 341, 15, 2048, 11, 20, 19, 19, {
> + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> +},
> +{ /* sentinel */ }
> +};
> +
> /*
> * Selected Rate Control Related Parameter Recommended Values
> * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> */
> -static const struct rc_parameters_data rc_parameters[] = {
> +static const struct rc_parameters_data rc_parameters_1_2_444[] = {
> { DSC_BPP(6), 8,
> /* 6BPP/8BPC */
> { 768, 15, 6144, 3, 13, 11, 11, {
> @@ -390,22 +460,18 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 512, 12, 6144, 3, 12, 11, 11, {
> { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> - { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
> + { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
> }
> }
> },
> { DSC_BPP(8), 10,
> /* 8BPP/10BPC */
> { 512, 12, 6144, 7, 16, 15, 15, {
> - /*
> - * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> - * VESA DSC 1.1 Table E-5 sets it to 4.
> - */
> - { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> + { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
> + { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
> }
> }
> },
> @@ -414,9 +480,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 512, 12, 6144, 11, 20, 19, 19, {
> { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> - { 21, 23, -12 }
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
> + { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
> + { 20, 21, -12 }
> }
> }
> },
> @@ -500,8 +566,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 341, 15, 2048, 3, 12, 11, 11, {
> { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> - { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
> + { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
> }
> }
> },
> @@ -510,8 +576,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 341, 15, 2048, 7, 16, 15, 15, {
> { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
> + { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
> }
> }
> },
> @@ -520,9 +586,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 341, 15, 2048, 11, 20, 19, 19, {
> { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> - { 21, 23, -12 }
> + { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
> + { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
> + { 18, 19, -12 }
> }
> }
> },
> @@ -604,7 +670,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> { /* sentinel */ }
> };
>
> -static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> +static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
> + u16 dsc_bpp,
> u8 bits_per_component)
> {
> int i;
> @@ -622,13 +689,27 @@ static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
> *
> * @vdsc_cfg: DSC Configuration data partially filled by driver
> + * @kind: operating mode and standard to follow
> */
> -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind)
> {
> + const struct rc_parameters_data *data;
> const struct rc_parameters *rc_params;
> int i;
>
> - rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
> + switch (kind) {
> + case DRM_DSC_1_2_444:
> + data = rc_parameters_1_2_444;
> + break;
> + case DRM_DSC_1_1_PRE_SCR:
> + data = rc_parameters_pre_scr;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + rc_params = get_rc_params(data,
> + vdsc_cfg->bits_per_pixel,
> vdsc_cfg->bits_per_component);
> if (!rc_params)
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 1ee8d13c9d64..4d220d24fa73 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -156,7 +156,15 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> if (DISPLAY_VER(dev_priv) >= 13) {
> calculate_rc_params(vdsc_cfg);
> } else {
> - ret = drm_dsc_setup_rc_params(vdsc_cfg);
> + if ((compressed_bpp == 8 ||
> + compressed_bpp == 12) &&
> + (vdsc_cfg->bits_per_pixel == 8 ||
> + vdsc_cfg->bits_per_pixel == 10 ||
> + vdsc_cfg->bits_per_pixel == 12))
> + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
> + else
> + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
> +
> if (ret)
> return ret;
>
> diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> index 1681791f65a5..c634bb2935d3 100644
> --- a/include/drm/display/drm_dsc_helper.h
> +++ b/include/drm/display/drm_dsc_helper.h
> @@ -10,12 +10,17 @@
>
> #include <drm/display/drm_dsc.h>
>
> +enum drm_dsc_params_kind {
> + DRM_DSC_1_2_444,
> + DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
> +};
> +
> void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
> int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> const struct drm_dsc_config *dsc_cfg);
> void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
> +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
> int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>
> #endif /* _DRM_DSC_HELPER_H_ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 06/10] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
@ 2023-02-28 16:33 ` Jani Nikula
0 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 16:33 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> The array of rc_parameters contains a mixture of parameters from DSC 1.1
> and DSC 1.2 standards. Split these tow configuration arrays in
> preparation to adding more configuration data.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 127 ++++++++++++++++++----
> drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
> include/drm/display/drm_dsc_helper.h | 7 +-
> 3 files changed, 119 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> index a6d11f474656..51794b40526a 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -326,11 +326,81 @@ struct rc_parameters_data {
>
> #define DSC_BPP(bpp) ((bpp) << 4)
>
> +static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> +{ DSC_BPP(8), 8,
> + /* 8BPP/8BPC */
I still dislike this indentation...
> + { 512, 12, 6144, 3, 12, 11, 11, {
> + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(8), 10,
> + /* 8BPP/10BPC */
> + { 512, 12, 6144, 7, 16, 15, 15, {
> + /*
> + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> + * VESA DSC 1.1 Table E-5 sets it to 4.
> + */
> + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(8), 12,
> + /* 8BPP/12BPC */
> + { 512, 12, 6144, 11, 20, 19, 19, {
> + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(12), 8,
> + /* 12BPP/8BPC */
> + { 341, 15, 2048, 3, 12, 11, 11, {
> + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(12), 10,
> + /* 12BPP/10BPC */
> + { 341, 15, 2048, 7, 16, 15, 15, {
> + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(12), 12,
> + /* 12BPP/12BPC */
> + { 341, 15, 2048, 11, 20, 19, 19, {
> + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> +},
> +{ /* sentinel */ }
> +};
> +
> /*
> * Selected Rate Control Related Parameter Recommended Values
> * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> */
> -static const struct rc_parameters_data rc_parameters[] = {
> +static const struct rc_parameters_data rc_parameters_1_2_444[] = {
> { DSC_BPP(6), 8,
> /* 6BPP/8BPC */
> { 768, 15, 6144, 3, 13, 11, 11, {
> @@ -390,22 +460,18 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 512, 12, 6144, 3, 12, 11, 11, {
> { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> - { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
> + { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
> }
> }
> },
> { DSC_BPP(8), 10,
> /* 8BPP/10BPC */
> { 512, 12, 6144, 7, 16, 15, 15, {
> - /*
> - * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> - * VESA DSC 1.1 Table E-5 sets it to 4.
> - */
> - { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> + { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
> + { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
> }
> }
> },
> @@ -414,9 +480,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 512, 12, 6144, 11, 20, 19, 19, {
> { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> - { 21, 23, -12 }
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
> + { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
> + { 20, 21, -12 }
> }
> }
> },
> @@ -500,8 +566,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 341, 15, 2048, 3, 12, 11, 11, {
> { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> - { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
> + { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
> }
> }
> },
> @@ -510,8 +576,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 341, 15, 2048, 7, 16, 15, 15, {
> { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
> + { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
> }
> }
> },
> @@ -520,9 +586,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 341, 15, 2048, 11, 20, 19, 19, {
> { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> - { 21, 23, -12 }
> + { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
> + { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
> + { 18, 19, -12 }
> }
> }
> },
> @@ -604,7 +670,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> { /* sentinel */ }
> };
>
> -static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> +static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
> + u16 dsc_bpp,
> u8 bits_per_component)
> {
> int i;
> @@ -622,13 +689,27 @@ static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
> *
> * @vdsc_cfg: DSC Configuration data partially filled by driver
> + * @kind: operating mode and standard to follow
> */
> -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind)
> {
> + const struct rc_parameters_data *data;
> const struct rc_parameters *rc_params;
> int i;
>
> - rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
> + switch (kind) {
> + case DRM_DSC_1_2_444:
> + data = rc_parameters_1_2_444;
> + break;
> + case DRM_DSC_1_1_PRE_SCR:
> + data = rc_parameters_pre_scr;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + rc_params = get_rc_params(data,
> + vdsc_cfg->bits_per_pixel,
> vdsc_cfg->bits_per_component);
> if (!rc_params)
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 1ee8d13c9d64..4d220d24fa73 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -156,7 +156,15 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> if (DISPLAY_VER(dev_priv) >= 13) {
> calculate_rc_params(vdsc_cfg);
> } else {
> - ret = drm_dsc_setup_rc_params(vdsc_cfg);
> + if ((compressed_bpp == 8 ||
> + compressed_bpp == 12) &&
> + (vdsc_cfg->bits_per_pixel == 8 ||
> + vdsc_cfg->bits_per_pixel == 10 ||
> + vdsc_cfg->bits_per_pixel == 12))
> + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
> + else
> + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
> +
> if (ret)
> return ret;
>
> diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> index 1681791f65a5..c634bb2935d3 100644
> --- a/include/drm/display/drm_dsc_helper.h
> +++ b/include/drm/display/drm_dsc_helper.h
> @@ -10,12 +10,17 @@
>
> #include <drm/display/drm_dsc.h>
>
> +enum drm_dsc_params_kind {
> + DRM_DSC_1_2_444,
> + DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
> +};
> +
> void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
> int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> const struct drm_dsc_config *dsc_cfg);
> void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
> +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
> int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>
> #endif /* _DRM_DSC_HELPER_H_ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH 06/10] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
@ 2023-02-28 16:33 ` Jani Nikula
0 siblings, 0 replies; 80+ messages in thread
From: Jani Nikula @ 2023-02-28 16:33 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> The array of rc_parameters contains a mixture of parameters from DSC 1.1
> and DSC 1.2 standards. Split these tow configuration arrays in
> preparation to adding more configuration data.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 127 ++++++++++++++++++----
> drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
> include/drm/display/drm_dsc_helper.h | 7 +-
> 3 files changed, 119 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> index a6d11f474656..51794b40526a 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -326,11 +326,81 @@ struct rc_parameters_data {
>
> #define DSC_BPP(bpp) ((bpp) << 4)
>
> +static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> +{ DSC_BPP(8), 8,
> + /* 8BPP/8BPC */
I still dislike this indentation...
> + { 512, 12, 6144, 3, 12, 11, 11, {
> + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(8), 10,
> + /* 8BPP/10BPC */
> + { 512, 12, 6144, 7, 16, 15, 15, {
> + /*
> + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> + * VESA DSC 1.1 Table E-5 sets it to 4.
> + */
> + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(8), 12,
> + /* 8BPP/12BPC */
> + { 512, 12, 6144, 11, 20, 19, 19, {
> + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(12), 8,
> + /* 12BPP/8BPC */
> + { 341, 15, 2048, 3, 12, 11, 11, {
> + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(12), 10,
> + /* 12BPP/10BPC */
> + { 341, 15, 2048, 7, 16, 15, 15, {
> + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> +},
> +{ DSC_BPP(12), 12,
> + /* 12BPP/12BPC */
> + { 341, 15, 2048, 11, 20, 19, 19, {
> + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> +},
> +{ /* sentinel */ }
> +};
> +
> /*
> * Selected Rate Control Related Parameter Recommended Values
> * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> */
> -static const struct rc_parameters_data rc_parameters[] = {
> +static const struct rc_parameters_data rc_parameters_1_2_444[] = {
> { DSC_BPP(6), 8,
> /* 6BPP/8BPC */
> { 768, 15, 6144, 3, 13, 11, 11, {
> @@ -390,22 +460,18 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 512, 12, 6144, 3, 12, 11, 11, {
> { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> - { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
> + { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
> }
> }
> },
> { DSC_BPP(8), 10,
> /* 8BPP/10BPC */
> { 512, 12, 6144, 7, 16, 15, 15, {
> - /*
> - * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> - * VESA DSC 1.1 Table E-5 sets it to 4.
> - */
> - { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> + { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
> + { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
> }
> }
> },
> @@ -414,9 +480,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 512, 12, 6144, 11, 20, 19, 19, {
> { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> - { 21, 23, -12 }
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
> + { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
> + { 20, 21, -12 }
> }
> }
> },
> @@ -500,8 +566,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 341, 15, 2048, 3, 12, 11, 11, {
> { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> - { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
> + { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
> }
> }
> },
> @@ -510,8 +576,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 341, 15, 2048, 7, 16, 15, 15, {
> { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
> + { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
> }
> }
> },
> @@ -520,9 +586,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 341, 15, 2048, 11, 20, 19, 19, {
> { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> - { 21, 23, -12 }
> + { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
> + { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
> + { 18, 19, -12 }
> }
> }
> },
> @@ -604,7 +670,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> { /* sentinel */ }
> };
>
> -static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> +static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
> + u16 dsc_bpp,
> u8 bits_per_component)
> {
> int i;
> @@ -622,13 +689,27 @@ static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
> *
> * @vdsc_cfg: DSC Configuration data partially filled by driver
> + * @kind: operating mode and standard to follow
> */
> -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind)
> {
> + const struct rc_parameters_data *data;
> const struct rc_parameters *rc_params;
> int i;
>
> - rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
> + switch (kind) {
> + case DRM_DSC_1_2_444:
> + data = rc_parameters_1_2_444;
> + break;
> + case DRM_DSC_1_1_PRE_SCR:
> + data = rc_parameters_pre_scr;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + rc_params = get_rc_params(data,
> + vdsc_cfg->bits_per_pixel,
> vdsc_cfg->bits_per_component);
> if (!rc_params)
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 1ee8d13c9d64..4d220d24fa73 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -156,7 +156,15 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> if (DISPLAY_VER(dev_priv) >= 13) {
> calculate_rc_params(vdsc_cfg);
> } else {
> - ret = drm_dsc_setup_rc_params(vdsc_cfg);
> + if ((compressed_bpp == 8 ||
> + compressed_bpp == 12) &&
> + (vdsc_cfg->bits_per_pixel == 8 ||
> + vdsc_cfg->bits_per_pixel == 10 ||
> + vdsc_cfg->bits_per_pixel == 12))
> + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
> + else
> + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
> +
> if (ret)
> return ret;
>
> diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> index 1681791f65a5..c634bb2935d3 100644
> --- a/include/drm/display/drm_dsc_helper.h
> +++ b/include/drm/display/drm_dsc_helper.h
> @@ -10,12 +10,17 @@
>
> #include <drm/display/drm_dsc.h>
>
> +enum drm_dsc_params_kind {
> + DRM_DSC_1_2_444,
> + DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
> +};
> +
> void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
> int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> const struct drm_dsc_config *dsc_cfg);
> void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
> +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
> int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>
> #endif /* _DRM_DSC_HELPER_H_ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH 07/10] drm/display/dsc: include the rest of pre-SCR parameters
2023-02-28 16:31 ` Jani Nikula
(?)
@ 2023-03-07 13:37 ` Dmitry Baryshkov
-1 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:37 UTC (permalink / raw)
To: Jani Nikula, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
On 28/02/2023 18:31, Jani Nikula wrote:
> On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
>> DSC model contains pre-SCR RC parameters for other bpp/bpc combinations,
>> include them here for completeness.
>
> Need to run now, note to self:
>
> Does i915 use the arrays to limit the bpp/bpc combos supported by
> hardware? Do we need to add separate limiting in i915.
There is already a limitation in intel_dsc_compute_params(): the driver
uses DRM_DSC_1_1_PRE_SCR only in a limited amount of cases (bpp 8 or 12,
bpc 8, 10 or 12). But thanks, I noticed a bug there.
>
> BR,
> Jani.
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 07/10] drm/display/dsc: include the rest of pre-SCR parameters
@ 2023-03-07 13:37 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:37 UTC (permalink / raw)
To: Jani Nikula, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
On 28/02/2023 18:31, Jani Nikula wrote:
> On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
>> DSC model contains pre-SCR RC parameters for other bpp/bpc combinations,
>> include them here for completeness.
>
> Need to run now, note to self:
>
> Does i915 use the arrays to limit the bpp/bpc combos supported by
> hardware? Do we need to add separate limiting in i915.
There is already a limitation in intel_dsc_compute_params(): the driver
uses DRM_DSC_1_1_PRE_SCR only in a limited amount of cases (bpp 8 or 12,
bpc 8, 10 or 12). But thanks, I noticed a bug there.
>
> BR,
> Jani.
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 07/10] drm/display/dsc: include the rest of pre-SCR parameters
@ 2023-03-07 13:37 ` Dmitry Baryshkov
0 siblings, 0 replies; 80+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:37 UTC (permalink / raw)
To: Jani Nikula, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
On 28/02/2023 18:31, Jani Nikula wrote:
> On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
>> DSC model contains pre-SCR RC parameters for other bpp/bpc combinations,
>> include them here for completeness.
>
> Need to run now, note to self:
>
> Does i915 use the arrays to limit the bpp/bpc combos supported by
> hardware? Do we need to add separate limiting in i915.
There is already a limitation in intel_dsc_compute_params(): the driver
uses DRM_DSC_1_1_PRE_SCR only in a limited amount of cases (bpp 8 or 12,
bpc 8, 10 or 12). But thanks, I noticed a bug there.
>
> BR,
> Jani.
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 80+ messages in thread
end of thread, other threads:[~2023-03-07 13:37 UTC | newest]
Thread overview: 80+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-02-28 11:33 [PATCH 00/10] drm/i915: move DSC RC tables to drm_dsc_helper.c Dmitry Baryshkov
2023-02-28 11:33 ` [Intel-gfx] " Dmitry Baryshkov
2023-02-28 11:33 ` Dmitry Baryshkov
2023-02-28 11:33 ` [PATCH 01/10] drm/i915/dsc: change DSC param tables to follow the DSC model Dmitry Baryshkov
2023-02-28 11:33 ` [Intel-gfx] " Dmitry Baryshkov
2023-02-28 11:33 ` Dmitry Baryshkov
2023-02-28 15:56 ` Jani Nikula
2023-02-28 15:56 ` [Intel-gfx] " Jani Nikula
2023-02-28 15:56 ` Jani Nikula
2023-02-28 16:10 ` Dmitry Baryshkov
2023-02-28 16:10 ` [Intel-gfx] " Dmitry Baryshkov
2023-02-28 16:10 ` Dmitry Baryshkov
2023-02-28 11:33 ` [PATCH 02/10] drm/i915/dsc: move rc_buf_thresh values to common helper Dmitry Baryshkov
2023-02-28 11:33 ` [Intel-gfx] " Dmitry Baryshkov
2023-02-28 11:33 ` Dmitry Baryshkov
2023-02-28 12:24 ` Jani Nikula
2023-02-28 12:24 ` [Intel-gfx] " Jani Nikula
2023-02-28 12:24 ` Jani Nikula
2023-02-28 12:35 ` Dmitry Baryshkov
2023-02-28 12:35 ` [Intel-gfx] " Dmitry Baryshkov
2023-02-28 12:35 ` Dmitry Baryshkov
2023-02-28 12:49 ` Jani Nikula
2023-02-28 12:49 ` [Intel-gfx] " Jani Nikula
2023-02-28 12:49 ` Jani Nikula
2023-02-28 13:02 ` Dmitry Baryshkov
2023-02-28 13:02 ` [Intel-gfx] " Dmitry Baryshkov
2023-02-28 13:02 ` Dmitry Baryshkov
2023-02-28 16:01 ` Jani Nikula
2023-02-28 16:01 ` [Intel-gfx] " Jani Nikula
2023-02-28 16:01 ` Jani Nikula
2023-02-28 11:33 ` [PATCH 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper Dmitry Baryshkov
2023-02-28 11:33 ` [Intel-gfx] " Dmitry Baryshkov
2023-02-28 11:33 ` Dmitry Baryshkov
2023-02-28 14:49 ` kernel test robot
2023-02-28 14:49 ` [Intel-gfx] " kernel test robot
2023-02-28 14:49 ` kernel test robot
2023-02-28 15:10 ` kernel test robot
2023-02-28 15:10 ` [Intel-gfx] " kernel test robot
2023-02-28 15:10 ` kernel test robot
2023-02-28 16:11 ` Jani Nikula
2023-02-28 16:11 ` [Intel-gfx] " Jani Nikula
2023-02-28 16:11 ` Jani Nikula
2023-02-28 11:33 ` [PATCH 04/10] drm/i915/dsc: stop using interim structure for calculated params Dmitry Baryshkov
2023-02-28 11:33 ` [Intel-gfx] " Dmitry Baryshkov
2023-02-28 11:33 ` Dmitry Baryshkov
2023-02-28 16:19 ` Jani Nikula
2023-02-28 16:19 ` [Intel-gfx] " Jani Nikula
2023-02-28 16:19 ` Jani Nikula
2023-02-28 11:33 ` [PATCH 05/10] drm/display/dsc: use flat array for rc_parameters lookup Dmitry Baryshkov
2023-02-28 11:33 ` [Intel-gfx] " Dmitry Baryshkov
2023-02-28 11:33 ` Dmitry Baryshkov
2023-02-28 16:28 ` Jani Nikula
2023-02-28 16:28 ` Jani Nikula
2023-02-28 16:28 ` [Intel-gfx] " Jani Nikula
2023-02-28 11:33 ` [PATCH 06/10] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters Dmitry Baryshkov
2023-02-28 11:33 ` [Intel-gfx] " Dmitry Baryshkov
2023-02-28 11:33 ` Dmitry Baryshkov
2023-02-28 16:33 ` Jani Nikula
2023-02-28 16:33 ` [Intel-gfx] " Jani Nikula
2023-02-28 16:33 ` Jani Nikula
2023-02-28 11:33 ` [PATCH 07/10] drm/display/dsc: include the rest of pre-SCR parameters Dmitry Baryshkov
2023-02-28 11:33 ` [Intel-gfx] " Dmitry Baryshkov
2023-02-28 11:33 ` Dmitry Baryshkov
2023-02-28 16:31 ` Jani Nikula
2023-02-28 16:31 ` [Intel-gfx] " Jani Nikula
2023-02-28 16:31 ` Jani Nikula
2023-03-07 13:37 ` [Intel-gfx] " Dmitry Baryshkov
2023-03-07 13:37 ` Dmitry Baryshkov
2023-03-07 13:37 ` Dmitry Baryshkov
2023-02-28 11:33 ` [PATCH 08/10] drm/display/dsc: add YCbCr 4:2:2 and 4:2:0 RC parameters Dmitry Baryshkov
2023-02-28 11:33 ` [Intel-gfx] " Dmitry Baryshkov
2023-02-28 11:33 ` Dmitry Baryshkov
2023-02-28 11:33 ` [PATCH 09/10] drm/display/dsc: add helper to set semi-const parameters Dmitry Baryshkov
2023-02-28 11:33 ` [Intel-gfx] " Dmitry Baryshkov
2023-02-28 11:33 ` Dmitry Baryshkov
2023-02-28 11:33 ` [PATCH 10/10] drm/msm/dsi: use new helpers for DSC setup Dmitry Baryshkov
2023-02-28 11:33 ` [Intel-gfx] " Dmitry Baryshkov
2023-02-28 11:33 ` Dmitry Baryshkov
2023-02-28 12:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: move DSC RC tables to drm_dsc_helper.c Patchwork
2023-02-28 12:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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