* [Intel-gfx] [PATCH v3 0/5] Misc Meteorlake patches
@ 2023-03-01 20:10 Radhakrishna Sripada
2023-03-01 20:10 ` [Intel-gfx] [PATCH v3 1/5] drm/i915/mtl: Fix Wa_16015201720 implementation Radhakrishna Sripada
` (7 more replies)
0 siblings, 8 replies; 23+ messages in thread
From: Radhakrishna Sripada @ 2023-03-01 20:10 UTC (permalink / raw)
To: intel-gfx
This series adds misc MTL patches. This is a new rev of
earlier series with dropped CCS patches. Review feedback for other
patches included.
Andi Shyti (1):
drm/i915/gt: generate per tile debugfs files
José Roberto de Souza (1):
drm/i915/display/mtl: Program latch to phy reset
Radhakrishna Sripada (2):
drm/i915/mtl: Fix Wa_16015201720 implementation
drm/i915/mtl: make IRQ reset and postinstall multi-gt aware
Tejas Upadhyay (1):
drm/i915/fbdev: lock the fbdev obj before vma pin
.../drm/i915/display/intel_display_power.c | 8 +++++
drivers/gpu/drm/i915/display/intel_dmc.c | 26 ++++++++++++----
drivers/gpu/drm/i915/display/intel_fbdev.c | 24 +++++++++++----
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 4 ++-
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 5 +++-
drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c | 2 ++
drivers/gpu/drm/i915/i915_irq.c | 30 +++++++++++--------
drivers/gpu/drm/i915/i915_reg.h | 12 ++++++--
9 files changed, 85 insertions(+), 28 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Intel-gfx] [PATCH v3 1/5] drm/i915/mtl: Fix Wa_16015201720 implementation
2023-03-01 20:10 [Intel-gfx] [PATCH v3 0/5] Misc Meteorlake patches Radhakrishna Sripada
@ 2023-03-01 20:10 ` Radhakrishna Sripada
2023-03-06 22:45 ` Matt Roper
2023-03-09 16:30 ` Andi Shyti
2023-03-01 20:10 ` [Intel-gfx] [PATCH v3 2/5] drm/i915/gt: generate per tile debugfs files Radhakrishna Sripada
` (6 subsequent siblings)
7 siblings, 2 replies; 23+ messages in thread
From: Radhakrishna Sripada @ 2023-03-01 20:10 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
The commit 2357f2b271ad ("drm/i915/mtl: Initial display workarounds")
extended the workaround Wa_16015201720 to MTL. However the registers
that the original WA implemented moved for MTL.
Implement the workaround with the correct register.
v3: Skip clock gating for pipe C, D DMC's and fix the title
Fixes: 2357f2b271ad ("drm/i915/mtl: Initial display workarounds")
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/display/intel_dmc.c | 26 +++++++++++++++++++-----
drivers/gpu/drm/i915/i915_reg.h | 10 ++++++---
2 files changed, 28 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index f70ada2357dc..b4283cf319f2 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -389,15 +389,12 @@ static void disable_all_event_handlers(struct drm_i915_private *i915)
}
}
-static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
+static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
{
enum pipe pipe;
- if (DISPLAY_VER(i915) < 13)
- return;
-
/*
- * Wa_16015201720:adl-p,dg2, mtl
+ * Wa_16015201720:adl-p,dg2
* The WA requires clock gating to be disabled all the time
* for pipe A and B.
* For pipe C and D clock gating needs to be disabled only
@@ -413,6 +410,25 @@ static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
PIPEDMC_GATING_DIS, 0);
}
+static void mtl_pipedmc_clock_gating_wa(struct drm_i915_private *i915)
+{
+ /*
+ * Wa_16015201720
+ * The WA requires clock gating to be disabled all the time
+ * for pipe A and B.
+ */
+ intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0,
+ MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B);
+}
+
+static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
+{
+ if (DISPLAY_VER(i915) >= 14 && enable)
+ return mtl_pipedmc_clock_gating_wa(i915);
+ else if (DISPLAY_VER(i915) == 13)
+ return adlp_pipedmc_clock_gating_wa(i915, enable);
+}
+
void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe)
{
enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1efa655fb68..7c9ac5b43831 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1794,9 +1794,13 @@
* GEN9 clock gating regs
*/
#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
-#define DARBF_GATING_DIS (1 << 27)
-#define PWM2_GATING_DIS (1 << 14)
-#define PWM1_GATING_DIS (1 << 13)
+#define DARBF_GATING_DIS REG_BIT(27)
+#define MTL_PIPEDMC_GATING_DIS_A REG_BIT(15)
+#define MTL_PIPEDMC_GATING_DIS_B REG_BIT(14)
+#define PWM2_GATING_DIS REG_BIT(14)
+#define MTL_PIPEDMC_GATING_DIS_C REG_BIT(13)
+#define PWM1_GATING_DIS REG_BIT(13)
+#define MTL_PIPEDMC_GATING_DIS_D REG_BIT(12)
#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
#define TGL_VRH_GATING_DIS REG_BIT(31)
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Intel-gfx] [PATCH v3 2/5] drm/i915/gt: generate per tile debugfs files
2023-03-01 20:10 [Intel-gfx] [PATCH v3 0/5] Misc Meteorlake patches Radhakrishna Sripada
2023-03-01 20:10 ` [Intel-gfx] [PATCH v3 1/5] drm/i915/mtl: Fix Wa_16015201720 implementation Radhakrishna Sripada
@ 2023-03-01 20:10 ` Radhakrishna Sripada
2023-03-01 21:03 ` Sripada, Radhakrishna
2023-03-01 20:10 ` [Intel-gfx] [PATCH v3 3/5] drm/i915/mtl: make IRQ reset and postinstall multi-gt aware Radhakrishna Sripada
` (5 subsequent siblings)
7 siblings, 1 reply; 23+ messages in thread
From: Radhakrishna Sripada @ 2023-03-01 20:10 UTC (permalink / raw)
To: intel-gfx; +Cc: Andi Shyti
From: Andi Shyti <andi.shyti@intel.com>
In the view of multi-gt we want independent per gt debug files.
In debugfs create gt0/ gt1/ ... gtN/ for tile related files. In 4
tiles, the debugfs would be structured as follows:
/sys/kernel/debug/dri
└── 0
├── gt0
│ ├── drpc
│ ├── engines
│ ├── forcewake
│ ├── frequency
│ └── rps_boost
├── gt1
│ ├── drpc
│ ├── engines
│ ├── forcewake
│ ├── frequency
│ └── rps_boost
├── gt2
│ ├── drpc
│ ├── engines
│ ├── forcewake
│ ├── frequency
│ └── rps_boost
└─- gt3
: ├── drpc
: ├── engines
: ├── forcewake
├── frequency
└── rps_boost
v2: Fix the missed assignment dbgfs_node
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 4 +++-
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 5 ++++-
drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c | 2 ++
4 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
index 5fc2df01aa0d..4dc23b8d3aa2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
@@ -83,11 +83,13 @@ static void gt_debugfs_register(struct intel_gt *gt, struct dentry *root)
void intel_gt_debugfs_register(struct intel_gt *gt)
{
struct dentry *root;
+ char gtname[4];
if (!gt->i915->drm.primary->debugfs_root)
return;
- root = debugfs_create_dir("gt", gt->i915->drm.primary->debugfs_root);
+ snprintf(gtname, sizeof(gtname), "gt%u", gt->info.id);
+ root = debugfs_create_dir(gtname, gt->i915->drm.primary->debugfs_root);
if (IS_ERR(root))
return;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index bb4dfe707a7d..e46aac1a41e6 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -42,6 +42,8 @@ struct intel_guc {
/** @capture: the error-state-capture module's data and objects */
struct intel_guc_state_capture *capture;
+ struct dentry *dbgfs_node;
+
/** @sched_engine: Global engine used to submit requests to GuC */
struct i915_sched_engine *sched_engine;
/**
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 195db8c9d420..55bc8b55fbc0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -542,8 +542,11 @@ static int guc_log_relay_create(struct intel_guc_log *log)
*/
n_subbufs = 8;
+ if (!guc->dbgfs_node)
+ return -ENOENT;
+
guc_log_relay_chan = relay_open("guc_log",
- i915->drm.primary->debugfs_root,
+ guc->dbgfs_node,
subbuf_size, n_subbufs,
&relay_callbacks, i915);
if (!guc_log_relay_chan) {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
index 284d6fbc2d08..2f93cc4e408a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
@@ -54,6 +54,8 @@ void intel_uc_debugfs_register(struct intel_uc *uc, struct dentry *gt_root)
if (IS_ERR(root))
return;
+ uc->guc.dbgfs_node = root;
+
intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), uc);
intel_guc_debugfs_register(&uc->guc, root);
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Intel-gfx] [PATCH v3 3/5] drm/i915/mtl: make IRQ reset and postinstall multi-gt aware
2023-03-01 20:10 [Intel-gfx] [PATCH v3 0/5] Misc Meteorlake patches Radhakrishna Sripada
2023-03-01 20:10 ` [Intel-gfx] [PATCH v3 1/5] drm/i915/mtl: Fix Wa_16015201720 implementation Radhakrishna Sripada
2023-03-01 20:10 ` [Intel-gfx] [PATCH v3 2/5] drm/i915/gt: generate per tile debugfs files Radhakrishna Sripada
@ 2023-03-01 20:10 ` Radhakrishna Sripada
2023-03-06 22:54 ` Matt Roper
2023-03-01 20:10 ` [Intel-gfx] [PATCH v3 4/5] drm/i915/fbdev: lock the fbdev obj before vma pin Radhakrishna Sripada
` (4 subsequent siblings)
7 siblings, 1 reply; 23+ messages in thread
From: Radhakrishna Sripada @ 2023-03-01 20:10 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Paulo Zanoni
Irq reset and post install are to be made multi-gt aware for the
interrupts to work for the media tile on Meteorlake. Iterate through
all the gts to process irq reset for each gt.
Based on original version by Paulo and Tvrtko
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 30 ++++++++++++++++++------------
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 417c981e4968..9377f59c1ac2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2759,16 +2759,19 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv)
static void dg1_irq_reset(struct drm_i915_private *dev_priv)
{
- struct intel_gt *gt = to_gt(dev_priv);
- struct intel_uncore *uncore = gt->uncore;
+ struct intel_gt *gt;
+ unsigned int i;
dg1_master_intr_disable(dev_priv->uncore.regs);
- gen11_gt_irq_reset(gt);
- gen11_display_irq_reset(dev_priv);
+ for_each_gt(gt, dev_priv, i) {
+ gen11_gt_irq_reset(gt);
- GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
- GEN3_IRQ_RESET(uncore, GEN8_PCU_);
+ GEN3_IRQ_RESET(gt->uncore, GEN11_GU_MISC_);
+ GEN3_IRQ_RESET(gt->uncore, GEN8_PCU_);
+ }
+
+ gen11_display_irq_reset(dev_priv);
}
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
@@ -3422,13 +3425,16 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
{
- struct intel_gt *gt = to_gt(dev_priv);
- struct intel_uncore *uncore = gt->uncore;
u32 gu_misc_masked = GEN11_GU_MISC_GSE;
+ struct intel_gt *gt;
+ unsigned int i;
- gen11_gt_irq_postinstall(gt);
+ for_each_gt(gt, dev_priv, i) {
+ gen11_gt_irq_postinstall(gt);
- GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
+ GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_, ~gu_misc_masked,
+ gu_misc_masked);
+ }
if (HAS_DISPLAY(dev_priv)) {
icp_irq_postinstall(dev_priv);
@@ -3437,8 +3443,8 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
GEN11_DISPLAY_IRQ_ENABLE);
}
- dg1_master_intr_enable(uncore->regs);
- intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
+ dg1_master_intr_enable(to_gt(dev_priv)->uncore->regs);
+ intel_uncore_posting_read(to_gt(dev_priv)->uncore, DG1_MSTR_TILE_INTR);
}
static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Intel-gfx] [PATCH v3 4/5] drm/i915/fbdev: lock the fbdev obj before vma pin
2023-03-01 20:10 [Intel-gfx] [PATCH v3 0/5] Misc Meteorlake patches Radhakrishna Sripada
` (2 preceding siblings ...)
2023-03-01 20:10 ` [Intel-gfx] [PATCH v3 3/5] drm/i915/mtl: make IRQ reset and postinstall multi-gt aware Radhakrishna Sripada
@ 2023-03-01 20:10 ` Radhakrishna Sripada
2023-03-09 17:18 ` Andi Shyti
2023-03-01 20:10 ` [Intel-gfx] [PATCH v3 5/5] drm/i915/display/mtl: Program latch to phy reset Radhakrishna Sripada
` (3 subsequent siblings)
7 siblings, 1 reply; 23+ messages in thread
From: Radhakrishna Sripada @ 2023-03-01 20:10 UTC (permalink / raw)
To: intel-gfx; +Cc: Matthew Auld, Chris Wilson
From: Tejas Upadhyay <tejas.upadhyay@intel.com>
lock the fbdev obj before calling into
i915_vma_pin_iomap(). This helps to solve below :
<7>[ 93.563308] i915 0000:00:02.0: [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
<4>[ 93.581844] ------------[ cut here ]------------
<4>[ 93.581855] WARNING: CPU: 12 PID: 625 at drivers/gpu/drm/i915/gem/i915_gem_pages.c:424 i915_gem_object_pin_map+0x152/0x1c0 [i915]
Fixes: f0b6b01b3efe ("drm/i915: Add ww context to intel_dpt_pin, v2.")
Cc: Chris Wilson <chris.p.wilson@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 24 ++++++++++++++++------
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 3659350061a7..2766d7ef0128 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -210,6 +210,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
bool prealloc = false;
void __iomem *vaddr;
struct drm_i915_gem_object *obj;
+ struct i915_gem_ww_ctx ww;
int ret;
mutex_lock(&ifbdev->hpd_lock);
@@ -283,13 +284,24 @@ static int intelfb_create(struct drm_fb_helper *helper,
info->fix.smem_len = vma->size;
}
- vaddr = i915_vma_pin_iomap(vma);
- if (IS_ERR(vaddr)) {
- drm_err(&dev_priv->drm,
- "Failed to remap framebuffer into virtual memory (%pe)\n", vaddr);
- ret = PTR_ERR(vaddr);
- goto out_unpin;
+ for_i915_gem_ww(&ww, ret, false) {
+ ret = i915_gem_object_lock(vma->obj, &ww);
+
+ if (ret)
+ continue;
+
+ vaddr = i915_vma_pin_iomap(vma);
+ if (IS_ERR(vaddr)) {
+ drm_err(&dev_priv->drm,
+ "Failed to remap framebuffer into virtual memory (%pe)\n", vaddr);
+ ret = PTR_ERR(vaddr);
+ continue;
+ }
}
+
+ if (ret)
+ goto out_unpin;
+
info->screen_base = vaddr;
info->screen_size = vma->size;
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Intel-gfx] [PATCH v3 5/5] drm/i915/display/mtl: Program latch to phy reset
2023-03-01 20:10 [Intel-gfx] [PATCH v3 0/5] Misc Meteorlake patches Radhakrishna Sripada
` (3 preceding siblings ...)
2023-03-01 20:10 ` [Intel-gfx] [PATCH v3 4/5] drm/i915/fbdev: lock the fbdev obj before vma pin Radhakrishna Sripada
@ 2023-03-01 20:10 ` Radhakrishna Sripada
2023-03-09 17:28 ` Andi Shyti
2023-03-01 22:50 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Misc Meteorlake patches (rev3) Patchwork
` (2 subsequent siblings)
7 siblings, 1 reply; 23+ messages in thread
From: Radhakrishna Sripada @ 2023-03-01 20:10 UTC (permalink / raw)
To: intel-gfx; +Cc: Matt Roper
From: José Roberto de Souza <jose.souza@intel.com>
Latch reset of phys during DC9 and when driver is unloaded to avoid
phy reset.
Specification ask us to program it closer to the step that enables
DC9 in DC_STATE_EN but doing this way allow us to sanitize the phy
latch during driver load.
BSpec: 49197
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 743b919bb2cf..50098c77e3be 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1624,6 +1624,10 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
intel_power_well_enable(dev_priv, well);
mutex_unlock(&power_domains->lock);
+ if (DISPLAY_VER(dev_priv) == 14)
+ intel_de_rmw(dev_priv, DC_STATE_EN,
+ HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH, 0);
+
/* 4. Enable CDCLK. */
intel_cdclk_init_hw(dev_priv);
@@ -1677,6 +1681,10 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
/* 3. Disable CD clock */
intel_cdclk_uninit_hw(dev_priv);
+ if (DISPLAY_VER(dev_priv) == 14)
+ intel_de_rmw(dev_priv, DC_STATE_EN, 0,
+ HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH);
+
/*
* 4. Disable Power Well 1 (PG1).
* The AUX IO power wells are toggled on demand, so they are already
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7c9ac5b43831..fa1905cc5a99 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7360,6 +7360,8 @@ enum skl_power_gate {
#define DC_STATE_DISABLE 0
#define DC_STATE_EN_DC3CO REG_BIT(30)
#define DC_STATE_DC3CO_STATUS REG_BIT(29)
+#define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21)
+#define HOLD_PHY_PG1_LATCH REG_BIT(20)
#define DC_STATE_EN_UPTO_DC5 (1 << 0)
#define DC_STATE_EN_DC9 (1 << 3)
#define DC_STATE_EN_UPTO_DC6 (2 << 0)
--
2.34.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH v3 2/5] drm/i915/gt: generate per tile debugfs files
2023-03-01 20:10 ` [Intel-gfx] [PATCH v3 2/5] drm/i915/gt: generate per tile debugfs files Radhakrishna Sripada
@ 2023-03-01 21:03 ` Sripada, Radhakrishna
0 siblings, 0 replies; 23+ messages in thread
From: Sripada, Radhakrishna @ 2023-03-01 21:03 UTC (permalink / raw)
To: intel-gfx; +Cc: Shyti, Andi
This patch can be ignored. As the original Author submitted the series here
https://patchwork.freedesktop.org/series/114510/
- Radhakrishna(RK) Sripada
> -----Original Message-----
> From: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> Sent: Wednesday, March 1, 2023 12:11 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Shyti, Andi <andi.shyti@intel.com>; Ursulin, Tvrtko
> <tvrtko.ursulin@intel.com>; Sripada, Radhakrishna
> <radhakrishna.sripada@intel.com>
> Subject: [PATCH v3 2/5] drm/i915/gt: generate per tile debugfs files
>
> From: Andi Shyti <andi.shyti@intel.com>
>
> In the view of multi-gt we want independent per gt debug files.
>
> In debugfs create gt0/ gt1/ ... gtN/ for tile related files. In 4
> tiles, the debugfs would be structured as follows:
>
> /sys/kernel/debug/dri
> └── 0
> ├── gt0
> │ ├── drpc
> │ ├── engines
> │ ├── forcewake
> │ ├── frequency
> │ └── rps_boost
> ├── gt1
> │ ├── drpc
> │ ├── engines
> │ ├── forcewake
> │ ├── frequency
> │ └── rps_boost
> ├── gt2
> │ ├── drpc
> │ ├── engines
> │ ├── forcewake
> │ ├── frequency
> │ └── rps_boost
> └─- gt3
> : ├── drpc
> : ├── engines
> : ├── forcewake
> ├── frequency
> └── rps_boost
>
> v2: Fix the missed assignment dbgfs_node
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 4 +++-
> drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 ++
> drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 5 ++++-
> drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c | 2 ++
> 4 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> index 5fc2df01aa0d..4dc23b8d3aa2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> @@ -83,11 +83,13 @@ static void gt_debugfs_register(struct intel_gt *gt,
> struct dentry *root)
> void intel_gt_debugfs_register(struct intel_gt *gt)
> {
> struct dentry *root;
> + char gtname[4];
>
> if (!gt->i915->drm.primary->debugfs_root)
> return;
>
> - root = debugfs_create_dir("gt", gt->i915->drm.primary->debugfs_root);
> + snprintf(gtname, sizeof(gtname), "gt%u", gt->info.id);
> + root = debugfs_create_dir(gtname, gt->i915->drm.primary-
> >debugfs_root);
> if (IS_ERR(root))
> return;
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index bb4dfe707a7d..e46aac1a41e6 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -42,6 +42,8 @@ struct intel_guc {
> /** @capture: the error-state-capture module's data and objects */
> struct intel_guc_state_capture *capture;
>
> + struct dentry *dbgfs_node;
> +
> /** @sched_engine: Global engine used to submit requests to GuC */
> struct i915_sched_engine *sched_engine;
> /**
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> index 195db8c9d420..55bc8b55fbc0 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> @@ -542,8 +542,11 @@ static int guc_log_relay_create(struct intel_guc_log
> *log)
> */
> n_subbufs = 8;
>
> + if (!guc->dbgfs_node)
> + return -ENOENT;
> +
> guc_log_relay_chan = relay_open("guc_log",
> - i915->drm.primary->debugfs_root,
> + guc->dbgfs_node,
> subbuf_size, n_subbufs,
> &relay_callbacks, i915);
> if (!guc_log_relay_chan) {
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
> index 284d6fbc2d08..2f93cc4e408a 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c
> @@ -54,6 +54,8 @@ void intel_uc_debugfs_register(struct intel_uc *uc, struct
> dentry *gt_root)
> if (IS_ERR(root))
> return;
>
> + uc->guc.dbgfs_node = root;
> +
> intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), uc);
>
> intel_guc_debugfs_register(&uc->guc, root);
> --
> 2.34.1
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Misc Meteorlake patches (rev3)
2023-03-01 20:10 [Intel-gfx] [PATCH v3 0/5] Misc Meteorlake patches Radhakrishna Sripada
` (4 preceding siblings ...)
2023-03-01 20:10 ` [Intel-gfx] [PATCH v3 5/5] drm/i915/display/mtl: Program latch to phy reset Radhakrishna Sripada
@ 2023-03-01 22:50 ` Patchwork
2023-03-01 23:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-05 8:52 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
7 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2023-03-01 22:50 UTC (permalink / raw)
To: Sripada, Radhakrishna; +Cc: intel-gfx
== Series Details ==
Series: Misc Meteorlake patches (rev3)
URL : https://patchwork.freedesktop.org/series/112700/
State : warning
== Summary ==
Error: dim checkpatch failed
f2efa48f76b8 drm/i915/mtl: Fix Wa_16015201720 implementation
3d4b9acde185 drm/i915/gt: generate per tile debugfs files
300a16a2c511 drm/i915/mtl: make IRQ reset and postinstall multi-gt aware
1af00da0945d drm/i915/fbdev: lock the fbdev obj before vma pin
-:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#9:
<7>[ 93.563308] i915 0000:00:02.0: [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
-:51: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#51: FILE: drivers/gpu/drm/i915/display/intel_fbdev.c:296:
+ "Failed to remap framebuffer into virtual memory (%pe)\n", vaddr);
-:51: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#51: FILE: drivers/gpu/drm/i915/display/intel_fbdev.c:296:
+ drm_err(&dev_priv->drm,
+ "Failed to remap framebuffer into virtual memory (%pe)\n", vaddr);
total: 0 errors, 2 warnings, 1 checks, 37 lines checked
4be18c15f3ba drm/i915/display/mtl: Program latch to phy reset
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Misc Meteorlake patches (rev3)
2023-03-01 20:10 [Intel-gfx] [PATCH v3 0/5] Misc Meteorlake patches Radhakrishna Sripada
` (5 preceding siblings ...)
2023-03-01 22:50 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Misc Meteorlake patches (rev3) Patchwork
@ 2023-03-01 23:13 ` Patchwork
2023-03-05 8:52 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
7 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2023-03-01 23:13 UTC (permalink / raw)
To: Sripada, Radhakrishna; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 7511 bytes --]
== Series Details ==
Series: Misc Meteorlake patches (rev3)
URL : https://patchwork.freedesktop.org/series/112700/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12799 -> Patchwork_112700v3
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/index.html
Participating hosts (40 -> 39)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_112700v3 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_gttfill@basic:
- fi-pnv-d510: [PASS][1] -> [FAIL][2] ([i915#7229])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
* igt@i915_selftest@live@requests:
- bat-rpls-1: [PASS][3] -> [ABORT][4] ([i915#7694] / [i915#7911])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-1/igt@i915_selftest@live@requests.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-rpls-1/igt@i915_selftest@live@requests.html
#### Possible fixes ####
* igt@i915_pm_rps@basic-api:
- bat-rpls-2: [SKIP][5] ([i915#6621]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-2/igt@i915_pm_rps@basic-api.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-rpls-2/igt@i915_pm_rps@basic-api.html
- bat-dg1-6: [SKIP][7] ([i915#6621]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-dg1-6/igt@i915_pm_rps@basic-api.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-dg1-6/igt@i915_pm_rps@basic-api.html
- bat-adlp-6: [SKIP][9] ([i915#6621]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-adlp-6/igt@i915_pm_rps@basic-api.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-adlp-6/igt@i915_pm_rps@basic-api.html
- bat-atsm-1: [SKIP][11] ([i915#6621]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-atsm-1/igt@i915_pm_rps@basic-api.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-atsm-1/igt@i915_pm_rps@basic-api.html
- bat-dg2-11: [SKIP][13] ([i915#6621]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-dg2-11/igt@i915_pm_rps@basic-api.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-dg2-11/igt@i915_pm_rps@basic-api.html
- bat-dg2-8: [SKIP][15] ([i915#6621]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-dg2-8/igt@i915_pm_rps@basic-api.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-dg2-8/igt@i915_pm_rps@basic-api.html
- bat-adlm-1: [SKIP][17] ([i915#6621]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-adlm-1/igt@i915_pm_rps@basic-api.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-adlm-1/igt@i915_pm_rps@basic-api.html
- bat-rpls-1: [SKIP][19] ([i915#6621]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-1/igt@i915_pm_rps@basic-api.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-rpls-1/igt@i915_pm_rps@basic-api.html
- bat-dg1-7: [SKIP][21] ([i915#6621]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-dg1-7/igt@i915_pm_rps@basic-api.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-dg1-7/igt@i915_pm_rps@basic-api.html
- bat-adlp-9: [SKIP][23] ([i915#6621]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-adlp-9/igt@i915_pm_rps@basic-api.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-adlp-9/igt@i915_pm_rps@basic-api.html
- bat-rplp-1: [SKIP][25] ([i915#6621]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rplp-1/igt@i915_pm_rps@basic-api.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-rplp-1/igt@i915_pm_rps@basic-api.html
- bat-dg1-5: [SKIP][27] ([i915#6621]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-dg1-5/igt@i915_pm_rps@basic-api.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-dg1-5/igt@i915_pm_rps@basic-api.html
- bat-dg2-9: [SKIP][29] ([i915#6621]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-dg2-9/igt@i915_pm_rps@basic-api.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-dg2-9/igt@i915_pm_rps@basic-api.html
- bat-adln-1: [SKIP][31] ([i915#6621]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-adln-1/igt@i915_pm_rps@basic-api.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-adln-1/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@migrate:
- bat-atsm-1: [DMESG-FAIL][33] ([i915#7699]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-atsm-1/igt@i915_selftest@live@migrate.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-atsm-1/igt@i915_selftest@live@migrate.html
#### Warnings ####
* igt@i915_selftest@live@slpc:
- bat-rpls-2: [DMESG-FAIL][35] ([i915#6997] / [i915#7913]) -> [DMESG-FAIL][36] ([i915#6367] / [i915#7913] / [i915#7996])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-2/igt@i915_selftest@live@slpc.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/bat-rpls-2/igt@i915_selftest@live@slpc.html
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
[i915#7694]: https://gitlab.freedesktop.org/drm/intel/issues/7694
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996
Build changes
-------------
* Linux: CI_DRM_12799 -> Patchwork_112700v3
CI-20190529: 20190529
CI_DRM_12799: 5f6631c00a7f226c990aecc643bc9fa70da1599a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7178: ffe3f6670b91ab975f90799ab3fd0941b6eae019 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_112700v3: 5f6631c00a7f226c990aecc643bc9fa70da1599a @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
19fc116a7f96 drm/i915/display/mtl: Program latch to phy reset
c7eebc5ece9d drm/i915/fbdev: lock the fbdev obj before vma pin
e5f88626416f drm/i915/mtl: make IRQ reset and postinstall multi-gt aware
0e879199a226 drm/i915/gt: generate per tile debugfs files
dface7c2b094 drm/i915/mtl: Fix Wa_16015201720 implementation
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/index.html
[-- Attachment #2: Type: text/html, Size: 9332 bytes --]
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Misc Meteorlake patches (rev3)
2023-03-01 20:10 [Intel-gfx] [PATCH v3 0/5] Misc Meteorlake patches Radhakrishna Sripada
` (6 preceding siblings ...)
2023-03-01 23:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-03-05 8:52 ` Patchwork
7 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2023-03-05 8:52 UTC (permalink / raw)
To: Sripada, Radhakrishna; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 50885 bytes --]
== Series Details ==
Series: Misc Meteorlake patches (rev3)
URL : https://patchwork.freedesktop.org/series/112700/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12799_full -> Patchwork_112700v3_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (19 -> 19)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_112700v3_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_atomic_transition@modeset-transition-fencing@3x-outputs (NEW):
- {shard-dg2-11}: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-dg2-11/igt@kms_atomic_transition@modeset-transition-fencing@3x-outputs.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_barrier_race@remote-request@rcs0}:
- {shard-dg2-7}: NOTRUN -> [ABORT][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-dg2-7/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_create@create-ext-cpu-access-big:
- {shard-dg2-5}: NOTRUN -> [ABORT][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-dg2-5/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_exec_whisper@basic-fds-priority:
- {shard-rkl}: [PASS][4] -> [DMESG-WARN][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-5/igt@gem_exec_whisper@basic-fds-priority.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-rkl-6/igt@gem_exec_whisper@basic-fds-priority.html
* igt@kms_content_protection@atomic@pipe-a-dp-4:
- {shard-dg2-11}: NOTRUN -> [TIMEOUT][6]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-dg2-11/igt@kms_content_protection@atomic@pipe-a-dp-4.html
* igt@kms_content_protection@uevent@pipe-a-dp-2:
- {shard-dg2-12}: NOTRUN -> [FAIL][7]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-dg2-12/igt@kms_content_protection@uevent@pipe-a-dp-2.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu:
- {shard-dg2-8}: NOTRUN -> [FAIL][8]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- {shard-dg2-5}: NOTRUN -> [FAIL][9]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html
* {igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d-dp-4}:
- {shard-dg2-11}: NOTRUN -> [SKIP][10]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-dg2-11/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d-dp-4.html
New tests
---------
New tests have been introduced between CI_DRM_12799_full and Patchwork_112700v3_full:
### New IGT tests (39) ###
* igt@kms_atomic_transition@modeset-transition-fencing@3x-outputs:
- Statuses : 1 fail(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-onscreen-64x21@pipe-d-dp-4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-random-64x21@pipe-d-dp-4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-rapid-movement-64x64@pipe-d-dp-4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_edge_walk@128x128-top-bottom@pipe-a-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_edge_walk@128x128-top-bottom@pipe-d-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_edge_walk@64x64-top-edge@pipe-a-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_edge_walk@64x64-top-edge@pipe-d-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-flip-vs-modeset@ab-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-flip-vs-modeset@ab-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-flip-vs-modeset@ab-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-flip-vs-modeset@ac-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-flip-vs-modeset@ac-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-flip-vs-modeset@ac-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-flip-vs-modeset@ad-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-flip-vs-modeset@ad-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-flip-vs-modeset@ad-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-flip-vs-modeset@bc-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-flip-vs-modeset@bc-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-flip-vs-modeset@bc-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-flip-vs-modeset@bd-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-flip-vs-modeset@bd-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-flip-vs-modeset@bd-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-flip-vs-modeset@cd-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-flip-vs-modeset@cd-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-flip-vs-modeset@cd-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@nonexisting-fb-interruptible@d-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@plain-flip-ts-check@d-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-0-25@pipe-a-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-0-25@pipe-c-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-0-25@pipe-d-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_setmode@basic@pipe-a-dp-1-pipe-b-dp-3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_setmode@basic@pipe-a-dp-2-pipe-b-dp-3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_setmode@basic@pipe-a-dp-2-pipe-b-dp-4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_setmode@basic@pipe-a-dp-3-pipe-b-dp-4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_setmode@basic@pipe-b-dp-1-pipe-a-dp-3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_setmode@basic@pipe-b-dp-2-pipe-a-dp-3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_setmode@basic@pipe-b-dp-2-pipe-a-dp-4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_setmode@basic@pipe-b-dp-3-pipe-a-dp-4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_112700v3_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@device_reset@unbind-cold-reset-rebind:
- shard-tglu-9: NOTRUN -> [SKIP][11] ([i915#7701])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@device_reset@unbind-cold-reset-rebind.html
* igt@gem_ccs@ctrl-surf-copy:
- shard-tglu-10: NOTRUN -> [SKIP][12] ([i915#3555] / [i915#5325])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@gem_ccs@ctrl-surf-copy.html
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-tglu-10: NOTRUN -> [SKIP][13] ([i915#5325])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
* igt@gem_ctx_sseu@mmap-args:
- shard-tglu-10: NOTRUN -> [SKIP][14] ([i915#280])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [PASS][15] -> [FAIL][16] ([i915#2842])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-glk5/igt@gem_exec_fair@basic-none-share@rcs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-glk1/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][17] -> [FAIL][18] ([i915#2842])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-apl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs:
- shard-tglu-10: NOTRUN -> [SKIP][19] ([i915#4613]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
* igt@gem_lmem_swapping@parallel-random:
- shard-tglu-9: NOTRUN -> [SKIP][20] ([i915#4613]) +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_media_vme:
- shard-tglu-10: NOTRUN -> [SKIP][21] ([i915#284])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@gem_media_vme.html
* igt@gem_pwrite@basic-exhaustion:
- shard-tglu-10: NOTRUN -> [WARN][22] ([i915#2658])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_pxp@reject-modify-context-protection-off-3:
- shard-tglu-9: NOTRUN -> [SKIP][23] ([i915#4270])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@gem_pxp@reject-modify-context-protection-off-3.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-tglu-10: NOTRUN -> [SKIP][24] ([i915#4270]) +2 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_userptr_blits@coherency-sync:
- shard-tglu-10: NOTRUN -> [SKIP][25] ([fdo#110542])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@gem_userptr_blits@coherency-sync.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][26] -> [ABORT][27] ([i915#5566])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-apl7/igt@gen9_exec_parse@allowed-single.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-apl4/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@basic-rejected-ctx-param:
- shard-tglu-9: NOTRUN -> [SKIP][28] ([i915#2527] / [i915#2856])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@gen9_exec_parse@basic-rejected-ctx-param.html
* igt@gen9_exec_parse@batch-zero-length:
- shard-tglu-10: NOTRUN -> [SKIP][29] ([i915#2527] / [i915#2856]) +4 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@gen9_exec_parse@batch-zero-length.html
* igt@i915_pm_backlight@bad-brightness:
- shard-tglu-10: NOTRUN -> [SKIP][30] ([i915#7561]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@i915_pm_backlight@bad-brightness.html
* igt@i915_pm_dc@dc6-dpms:
- shard-tglu-9: NOTRUN -> [FAIL][31] ([i915#3989] / [i915#454])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rc6_residency@rc6-idle@rcs0:
- shard-tglu-10: NOTRUN -> [WARN][32] ([i915#2681]) +3 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-tglu-9: NOTRUN -> [SKIP][33] ([fdo#111644] / [i915#1397])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- shard-tglu-10: NOTRUN -> [SKIP][34] ([fdo#111644] / [i915#1397])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@i915_pm_rpm@dpms-non-lpsp.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-tglu-10: NOTRUN -> [SKIP][35] ([fdo#109506])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-tglu-10: NOTRUN -> [SKIP][36] ([i915#5286]) +4 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@linear-16bpp-rotate-90:
- shard-tglu-10: NOTRUN -> [SKIP][37] ([fdo#111614]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_big_fb@linear-16bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
- shard-tglu-9: NOTRUN -> [SKIP][38] ([fdo#111615] / [i915#1845] / [i915#7651]) +2 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
- shard-tglu-10: NOTRUN -> [SKIP][39] ([fdo#111615]) +4 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
* igt@kms_big_joiner@2x-modeset:
- shard-tglu-9: NOTRUN -> [SKIP][40] ([i915#2705])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@kms_big_joiner@2x-modeset.html
* igt@kms_big_joiner@invalid-modeset:
- shard-tglu-10: NOTRUN -> [SKIP][41] ([i915#2705])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_dg2_rc_ccs:
- shard-tglu-10: NOTRUN -> [SKIP][42] ([i915#6095]) +2 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_dg2_rc_ccs.html
* igt@kms_ccs@pipe-c-bad-pixel-format-yf_tiled_ccs:
- shard-tglu-10: NOTRUN -> [SKIP][43] ([fdo#111615] / [i915#3689]) +5 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_ccs@pipe-c-bad-pixel-format-yf_tiled_ccs.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-tglu-10: NOTRUN -> [SKIP][44] ([i915#3689] / [i915#3886]) +4 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_dg2_rc_ccs:
- shard-tglu-9: NOTRUN -> [SKIP][45] ([i915#1845] / [i915#7651]) +50 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_dg2_rc_ccs.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs:
- shard-tglu-10: NOTRUN -> [SKIP][46] ([i915#3689] / [i915#6095]) +2 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs.html
* igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-tglu-10: NOTRUN -> [SKIP][47] ([i915#3689]) +5 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_cdclk@mode-transition-all-outputs:
- shard-tglu-9: NOTRUN -> [SKIP][48] ([i915#3742])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@kms_cdclk@mode-transition-all-outputs.html
* igt@kms_chamelium_hpd@dp-hpd-after-suspend:
- shard-tglu-10: NOTRUN -> [SKIP][49] ([i915#7828]) +5 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html
* igt@kms_chamelium_hpd@vga-hpd-without-ddc:
- shard-tglu-9: NOTRUN -> [SKIP][50] ([i915#7828]) +5 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@kms_chamelium_hpd@vga-hpd-without-ddc.html
* igt@kms_color@ctm-0-25@pipe-b-hdmi-a-1:
- shard-tglu-10: NOTRUN -> [FAIL][51] ([i915#315] / [i915#6946]) +3 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_color@ctm-0-25@pipe-b-hdmi-a-1.html
* igt@kms_content_protection@content_type_change:
- shard-tglu-10: NOTRUN -> [SKIP][52] ([i915#6944] / [i915#7116] / [i915#7118])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_content_protection@content_type_change.html
* igt@kms_cursor_crc@cursor-offscreen-512x512:
- shard-tglu-10: NOTRUN -> [SKIP][53] ([i915#3359])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_cursor_crc@cursor-offscreen-512x512.html
* igt@kms_cursor_crc@cursor-onscreen-256x256:
- shard-tglu-9: NOTRUN -> [SKIP][54] ([i915#1845]) +10 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@kms_cursor_crc@cursor-onscreen-256x256.html
* igt@kms_cursor_crc@cursor-sliding-max-size:
- shard-tglu-10: NOTRUN -> [SKIP][55] ([i915#3555]) +6 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_cursor_crc@cursor-sliding-max-size.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
- shard-tglu-10: NOTRUN -> [SKIP][56] ([fdo#109274])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [PASS][57] -> [FAIL][58] ([i915#72])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-glk6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-glk5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-tglu-10: NOTRUN -> [SKIP][59] ([i915#4103])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [PASS][60] -> [FAIL][61] ([i915#2346])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
- shard-glk: [PASS][62] -> [FAIL][63] ([i915#2346])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-tglu-10: NOTRUN -> [FAIL][64] ([i915#4767])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-tglu-10: NOTRUN -> [SKIP][65] ([fdo#109274] / [i915#3637] / [i915#3966])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-tglu-10: NOTRUN -> [SKIP][66] ([fdo#109274] / [i915#3637]) +6 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-tglu-9: NOTRUN -> [SKIP][67] ([fdo#109274] / [i915#3637]) +2 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip@flip-vs-fences-interruptible:
- shard-tglu-9: NOTRUN -> [SKIP][68] ([i915#3637]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@kms_flip@flip-vs-fences-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling:
- shard-tglu-9: NOTRUN -> [SKIP][69] ([i915#3555]) +7 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-tglu-10: NOTRUN -> [SKIP][70] ([i915#2587] / [i915#2672]) +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_force_connector_basic@force-load-detect:
- shard-tglu-10: NOTRUN -> [SKIP][71] ([fdo#109285])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-pwrite:
- shard-tglu-9: NOTRUN -> [SKIP][72] ([i915#1849]) +34 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-tglu-10: NOTRUN -> [SKIP][73] ([fdo#109280]) +18 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt:
- shard-tglu-10: NOTRUN -> [SKIP][74] ([fdo#110189]) +24 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-tglu-9: NOTRUN -> [SKIP][75] ([i915#1839])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c:
- shard-tglu-10: NOTRUN -> [SKIP][76] ([fdo#109289]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c.html
* igt@kms_plane@plane-position-covered@pipe-a-planes:
- shard-tglu-9: NOTRUN -> [SKIP][77] ([i915#1849] / [i915#3558]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@kms_plane@plane-position-covered@pipe-a-planes.html
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-vga-1:
- shard-snb: NOTRUN -> [SKIP][78] ([fdo#109271]) +12 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-snb4/igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-vga-1.html
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-1:
- shard-tglu-10: NOTRUN -> [SKIP][79] ([i915#5176]) +7 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25:
- shard-tglu-9: NOTRUN -> [SKIP][80] ([i915#6953] / [i915#8152])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@kms_plane_scaling@planes-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-1:
- shard-tglu-10: NOTRUN -> [SKIP][81] ([i915#5235]) +7 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-1.html
* igt@kms_prime@basic-crc-hybrid:
- shard-tglu-10: NOTRUN -> [SKIP][82] ([i915#6524])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_prime@basic-modeset-hybrid:
- shard-tglu-9: NOTRUN -> [SKIP][83] ([i915#6524])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@kms_prime@basic-modeset-hybrid.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf:
- shard-tglu-10: NOTRUN -> [SKIP][84] ([i915#658])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-tglu-10: NOTRUN -> [SKIP][85] ([fdo#111068] / [i915#658])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-tglu-9: NOTRUN -> [SKIP][86] ([fdo#111068] / [i915#658])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-tglu-9: NOTRUN -> [SKIP][87] ([fdo#109642] / [fdo#111068] / [i915#658])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@sprite_mmap_cpu:
- shard-tglu-9: NOTRUN -> [SKIP][88] ([fdo#110189]) +2 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@kms_psr@sprite_mmap_cpu.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
- shard-tglu-10: NOTRUN -> [SKIP][89] ([i915#5289])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-tglu-9: NOTRUN -> [SKIP][90] ([fdo#111615] / [i915#1845])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_universal_plane@disable-primary-vs-flip-pipe-c:
- shard-tglu-9: NOTRUN -> [SKIP][91] ([fdo#109274])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@kms_universal_plane@disable-primary-vs-flip-pipe-c.html
* igt@perf@gen8-unprivileged-single-ctx-counters:
- shard-tglu-9: NOTRUN -> [SKIP][92] ([fdo#109289])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@perf@gen8-unprivileged-single-ctx-counters.html
* igt@perf@polling-small-buf:
- shard-tglu-9: NOTRUN -> [FAIL][93] ([i915#1722])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@perf@polling-small-buf.html
* igt@perf_pmu@event-wait@rcs0:
- shard-tglu-10: NOTRUN -> [SKIP][94] ([fdo#112283])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@perf_pmu@event-wait@rcs0.html
* igt@prime_vgem@basic-fence-flip:
- shard-tglu-9: NOTRUN -> [SKIP][95] ([fdo#109295])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@prime_vgem@basic-fence-flip.html
* igt@v3d/v3d_get_param@get-bad-param:
- shard-tglu-10: NOTRUN -> [SKIP][96] ([fdo#109315] / [i915#2575]) +1 similar issue
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@v3d/v3d_get_param@get-bad-param.html
* igt@v3d/v3d_mmap@mmap-bad-flags:
- shard-tglu-9: NOTRUN -> [SKIP][97] ([fdo#109315] / [i915#2575]) +1 similar issue
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@v3d/v3d_mmap@mmap-bad-flags.html
* igt@vc4/vc4_create_bo@create-bo-4096:
- shard-tglu-10: NOTRUN -> [SKIP][98] ([i915#2575]) +6 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-10/igt@vc4/vc4_create_bo@create-bo-4096.html
* igt@vc4/vc4_purgeable_bo@access-purgeable-bo-mem:
- shard-tglu-9: NOTRUN -> [SKIP][99] ([i915#2575]) +4 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-tglu-9/igt@vc4/vc4_purgeable_bo@access-purgeable-bo-mem.html
#### Possible fixes ####
* igt@fbdev@read:
- {shard-rkl}: [SKIP][100] ([i915#2582]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-5/igt@fbdev@read.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-rkl-6/igt@fbdev@read.html
* igt@gem_eio@in-flight-suspend:
- {shard-rkl}: [FAIL][102] ([fdo#103375]) -> [PASS][103] +1 similar issue
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-4/igt@gem_eio@in-flight-suspend.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-rkl-2/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_reloc@basic-write-gtt-active:
- {shard-rkl}: [SKIP][104] ([i915#3281]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-2/igt@gem_exec_reloc@basic-write-gtt-active.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-rkl-5/igt@gem_exec_reloc@basic-write-gtt-active.html
* igt@gem_madvise@dontneed-before-exec:
- {shard-rkl}: [SKIP][106] ([i915#3282]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-2/igt@gem_madvise@dontneed-before-exec.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-rkl-5/igt@gem_madvise@dontneed-before-exec.html
* igt@gen9_exec_parse@allowed-all:
- {shard-rkl}: [SKIP][108] ([i915#2527]) -> [PASS][109] +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-2/igt@gen9_exec_parse@allowed-all.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-rkl-5/igt@gen9_exec_parse@allowed-all.html
* igt@i915_hangman@gt-engine-error@bcs0:
- {shard-rkl}: [SKIP][110] ([i915#6258]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-5/igt@i915_hangman@gt-engine-error@bcs0.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-rkl-2/igt@i915_hangman@gt-engine-error@bcs0.html
* igt@i915_pm_dc@dc6-psr:
- {shard-rkl}: [SKIP][112] ([i915#658]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-4/igt@i915_pm_dc@dc6-psr.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-rkl-6/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@pm-tiling:
- {shard-rkl}: [SKIP][114] ([fdo#109308]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-5/igt@i915_pm_rpm@pm-tiling.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-rkl-6/igt@i915_pm_rpm@pm-tiling.html
* igt@i915_pm_rps@basic-api:
- {shard-dg2-10}: [SKIP][116] ([i915#6621]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-dg2-10/igt@i915_pm_rps@basic-api.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-dg2-10/igt@i915_pm_rps@basic-api.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-apl: [FAIL][118] ([i915#2346]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2:
- shard-glk: [FAIL][120] ([i915#79]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-glk8/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-glk7/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
- {shard-rkl}: [SKIP][122] ([i915#1849] / [i915#4098]) -> [PASS][123] +16 similar issues
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_psr@primary_mmap_gtt:
- {shard-rkl}: [SKIP][124] ([i915#1072]) -> [PASS][125] +2 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-5/igt@kms_psr@primary_mmap_gtt.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-rkl-6/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_rotation_crc@exhaust-fences:
- {shard-rkl}: [SKIP][126] ([i915#1845] / [i915#4098]) -> [PASS][127] +21 similar issues
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-5/igt@kms_rotation_crc@exhaust-fences.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-rkl-6/igt@kms_rotation_crc@exhaust-fences.html
* igt@perf@gen12-oa-tlb-invalidate:
- {shard-rkl}: [SKIP][128] ([fdo#109289]) -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-5/igt@perf@gen12-oa-tlb-invalidate.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/shard-rkl-6/igt@perf@gen12-oa-tlb-invalidate.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958
[i915#5107]: https://gitlab.freedesktop.org/drm/intel/issues/5107
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5410]: https://gitlab.freedesktop.org/drm/intel/issues/5410
[i915#5431]: https://gitlab.freedesktop.org/drm/intel/issues/5431
[i915#5433]: https://gitlab.freedesktop.org/drm/intel/issues/5433
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5445]: https://gitlab.freedesktop.org/drm/intel/issues/5445
[i915#5460]: https://gitlab.freedesktop.org/drm/intel/issues/5460
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5464]: https://gitlab.freedesktop.org/drm/intel/issues/5464
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5882]: https://gitlab.freedesktop.org/drm/intel/issues/5882
[i915#5889]: https://gitlab.freedesktop.org/drm/intel/issues/5889
[i915#5892]: https://gitlab.freedesktop.org/drm/intel/issues/5892
[i915#5978]: https://gitlab.freedesktop.org/drm/intel/issues/5978
[i915#6032]: https://gitlab.freedesktop.org/drm/intel/issues/6032
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6118]: https://gitlab.freedesktop.org/drm/intel/issues/6118
[i915#6122]: https://gitlab.freedesktop.org/drm/intel/issues/6122
[i915#6188]: https://gitlab.freedesktop.org/drm/intel/issues/6188
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6228]: https://gitlab.freedesktop.org/drm/intel/issues/6228
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
[i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6333]: https://gitlab.freedesktop.org/drm/intel/issues/6333
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#6530]: https://gitlab.freedesktop.org/drm/intel/issues/6530
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7061]: https://gitlab.freedesktop.org/drm/intel/issues/7061
[i915#7091]: https://gitlab.freedesktop.org/drm/intel/issues/7091
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
[i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7507]: https://gitlab.freedesktop.org/drm/intel/issues/7507
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7679]: https://gitlab.freedesktop.org/drm/intel/issues/7679
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7949]: https://gitlab.freedesktop.org/drm/intel/issues/7949
[i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#7997]: https://gitlab.freedesktop.org/drm/intel/issues/7997
[i915#8077]: https://gitlab.freedesktop.org/drm/intel/issues/8077
[i915#8150]: https://gitlab.freedesktop.org/drm/intel/issues/8150
[i915#8152]: https://gitlab.freedesktop.org/drm/intel/issues/8152
[i915#8154]: https://gitlab.freedesktop.org/drm/intel/issues/8154
[i915#8155]: https://gitlab.freedesktop.org/drm/intel/issues/8155
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8231]: https://gitlab.freedesktop.org/drm/intel/issues/8231
Build changes
-------------
* Linux: CI_DRM_12799 -> Patchwork_112700v3
CI-20190529: 20190529
CI_DRM_12799: 5f6631c00a7f226c990aecc643bc9fa70da1599a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7178: ffe3f6670b91ab975f90799ab3fd0941b6eae019 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_112700v3: 5f6631c00a7f226c990aecc643bc9fa70da1599a @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112700v3/index.html
[-- Attachment #2: Type: text/html, Size: 49155 bytes --]
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH v3 1/5] drm/i915/mtl: Fix Wa_16015201720 implementation
2023-03-01 20:10 ` [Intel-gfx] [PATCH v3 1/5] drm/i915/mtl: Fix Wa_16015201720 implementation Radhakrishna Sripada
@ 2023-03-06 22:45 ` Matt Roper
2023-03-09 16:30 ` Andi Shyti
1 sibling, 0 replies; 23+ messages in thread
From: Matt Roper @ 2023-03-06 22:45 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx, Lucas De Marchi
On Wed, Mar 01, 2023 at 12:10:49PM -0800, Radhakrishna Sripada wrote:
> The commit 2357f2b271ad ("drm/i915/mtl: Initial display workarounds")
> extended the workaround Wa_16015201720 to MTL. However the registers
> that the original WA implemented moved for MTL.
>
> Implement the workaround with the correct register.
>
> v3: Skip clock gating for pipe C, D DMC's and fix the title
>
> Fixes: 2357f2b271ad ("drm/i915/mtl: Initial display workarounds")
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 26 +++++++++++++++++++-----
> drivers/gpu/drm/i915/i915_reg.h | 10 ++++++---
> 2 files changed, 28 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index f70ada2357dc..b4283cf319f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -389,15 +389,12 @@ static void disable_all_event_handlers(struct drm_i915_private *i915)
> }
> }
>
> -static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
> +static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
> {
> enum pipe pipe;
>
> - if (DISPLAY_VER(i915) < 13)
> - return;
> -
> /*
> - * Wa_16015201720:adl-p,dg2, mtl
> + * Wa_16015201720:adl-p,dg2
> * The WA requires clock gating to be disabled all the time
> * for pipe A and B.
> * For pipe C and D clock gating needs to be disabled only
> @@ -413,6 +410,25 @@ static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
> PIPEDMC_GATING_DIS, 0);
> }
>
> +static void mtl_pipedmc_clock_gating_wa(struct drm_i915_private *i915)
> +{
> + /*
> + * Wa_16015201720
> + * The WA requires clock gating to be disabled all the time
> + * for pipe A and B.
> + */
> + intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0,
> + MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B);
> +}
> +
> +static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
> +{
> + if (DISPLAY_VER(i915) >= 14 && enable)
> + return mtl_pipedmc_clock_gating_wa(i915);
> + else if (DISPLAY_VER(i915) == 13)
> + return adlp_pipedmc_clock_gating_wa(i915, enable);
Both of these functions return 'void' so the 'return' on each of these
lines is a bit strange. I'd remove the 'return' at the beginning of
these lines.
> +}
> +
> void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe)
> {
> enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c1efa655fb68..7c9ac5b43831 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1794,9 +1794,13 @@
> * GEN9 clock gating regs
> */
> #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
> -#define DARBF_GATING_DIS (1 << 27)
> -#define PWM2_GATING_DIS (1 << 14)
> -#define PWM1_GATING_DIS (1 << 13)
> +#define DARBF_GATING_DIS REG_BIT(27)
> +#define MTL_PIPEDMC_GATING_DIS_A REG_BIT(15)
> +#define MTL_PIPEDMC_GATING_DIS_B REG_BIT(14)
> +#define PWM2_GATING_DIS REG_BIT(14)
> +#define MTL_PIPEDMC_GATING_DIS_C REG_BIT(13)
> +#define PWM1_GATING_DIS REG_BIT(13)
> +#define MTL_PIPEDMC_GATING_DIS_D REG_BIT(12)
It's not really worth adding bits that we don't use anywhere. I'd drop
the DIS_C and DIS_D defines here, otherwise people will wonder whether
it's a mistake that they're added but not used.
Aside from the unnecessary bits here and the returns above, the rest
looks okay, so
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
with those changes.
Matt
>
> #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
> #define TGL_VRH_GATING_DIS REG_BIT(31)
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/mtl: make IRQ reset and postinstall multi-gt aware
2023-03-01 20:10 ` [Intel-gfx] [PATCH v3 3/5] drm/i915/mtl: make IRQ reset and postinstall multi-gt aware Radhakrishna Sripada
@ 2023-03-06 22:54 ` Matt Roper
2023-03-07 0:14 ` Sripada, Radhakrishna
0 siblings, 1 reply; 23+ messages in thread
From: Matt Roper @ 2023-03-06 22:54 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx, Lucas De Marchi, Paulo Zanoni
On Wed, Mar 01, 2023 at 12:10:51PM -0800, Radhakrishna Sripada wrote:
> Irq reset and post install are to be made multi-gt aware for the
> interrupts to work for the media tile on Meteorlake. Iterate through
> all the gts to process irq reset for each gt.
I think I mentioned on the previous version, but this isn't right. MTL
does not have separate interrupt registers for each GT the way
multi-tile platforms like PVC do. The GT interrupt registers you're
handling here are in the sgunit so there's only a single copy of them;
iterating over them multiple times in a row doesn't accomplish anything.
The media engine bits are still on the same registers as the primary GT
and the GSC and media GuC are new additional bits that need to be
handled. The necessary handling for the GSC and media GuC should have
already landed in a187f13d51fa ("drm/i915/guc: handle interrupts from
media GuC") and c07ee636901d ("drm/i915/mtl: add GSC CS interrupt
support"), but if there's another bit that was missed somewhere (or if
we were doing something like looking at the wrong intel_gt's engine mask
somewhere), that would need to be addressed directly rather than just
looping over the same IRQ registers multiple times.
Matt
>
> Based on original version by Paulo and Tvrtko
>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 30 ++++++++++++++++++------------
> 1 file changed, 18 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 417c981e4968..9377f59c1ac2 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2759,16 +2759,19 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv)
>
> static void dg1_irq_reset(struct drm_i915_private *dev_priv)
> {
> - struct intel_gt *gt = to_gt(dev_priv);
> - struct intel_uncore *uncore = gt->uncore;
> + struct intel_gt *gt;
> + unsigned int i;
>
> dg1_master_intr_disable(dev_priv->uncore.regs);
>
> - gen11_gt_irq_reset(gt);
> - gen11_display_irq_reset(dev_priv);
> + for_each_gt(gt, dev_priv, i) {
> + gen11_gt_irq_reset(gt);
>
> - GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
> - GEN3_IRQ_RESET(uncore, GEN8_PCU_);
> + GEN3_IRQ_RESET(gt->uncore, GEN11_GU_MISC_);
> + GEN3_IRQ_RESET(gt->uncore, GEN8_PCU_);
> + }
> +
> + gen11_display_irq_reset(dev_priv);
> }
>
> void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
> @@ -3422,13 +3425,16 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
>
> static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> - struct intel_gt *gt = to_gt(dev_priv);
> - struct intel_uncore *uncore = gt->uncore;
> u32 gu_misc_masked = GEN11_GU_MISC_GSE;
> + struct intel_gt *gt;
> + unsigned int i;
>
> - gen11_gt_irq_postinstall(gt);
> + for_each_gt(gt, dev_priv, i) {
> + gen11_gt_irq_postinstall(gt);
>
> - GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
> + GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_, ~gu_misc_masked,
> + gu_misc_masked);
> + }
>
> if (HAS_DISPLAY(dev_priv)) {
> icp_irq_postinstall(dev_priv);
> @@ -3437,8 +3443,8 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
> GEN11_DISPLAY_IRQ_ENABLE);
> }
>
> - dg1_master_intr_enable(uncore->regs);
> - intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
> + dg1_master_intr_enable(to_gt(dev_priv)->uncore->regs);
> + intel_uncore_posting_read(to_gt(dev_priv)->uncore, DG1_MSTR_TILE_INTR);
> }
>
> static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/mtl: make IRQ reset and postinstall multi-gt aware
2023-03-06 22:54 ` Matt Roper
@ 2023-03-07 0:14 ` Sripada, Radhakrishna
2023-03-07 0:24 ` Matt Roper
0 siblings, 1 reply; 23+ messages in thread
From: Sripada, Radhakrishna @ 2023-03-07 0:14 UTC (permalink / raw)
To: Roper, Matthew D, Ceraolo Spurio, Daniele
Cc: intel-gfx, De Marchi, Lucas, Zanoni, Paulo R
+Daniele,
Hi Matt,
> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Monday, March 6, 2023 2:55 PM
> To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; De Marchi, Lucas
> <lucas.demarchi@intel.com>; Zanoni, Paulo R <paulo.r.zanoni@intel.com>
> Subject: Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/mtl: make IRQ reset and
> postinstall multi-gt aware
>
> On Wed, Mar 01, 2023 at 12:10:51PM -0800, Radhakrishna Sripada wrote:
> > Irq reset and post install are to be made multi-gt aware for the
> > interrupts to work for the media tile on Meteorlake. Iterate through
> > all the gts to process irq reset for each gt.
>
> I think I mentioned on the previous version, but this isn't right. MTL
> does not have separate interrupt registers for each GT the way
> multi-tile platforms like PVC do. The GT interrupt registers you're
> handling here are in the sgunit so there's only a single copy of them;
> iterating over them multiple times in a row doesn't accomplish anything.
>
> The media engine bits are still on the same registers as the primary GT
> and the GSC and media GuC are new additional bits that need to be
> handled. The necessary handling for the GSC and media GuC should have
> already landed in a187f13d51fa ("drm/i915/guc: handle interrupts from
> media GuC") and c07ee636901d ("drm/i915/mtl: add GSC CS interrupt
> support"), but if there's another bit that was missed somewhere (or if
> we were doing something like looking at the wrong intel_gt's engine mask
> somewhere), that would need to be addressed directly rather than just
> looping over the same IRQ registers multiple times.
This patch is needed to handle media interrupts. Without this patch we observed
GuC not loading/communication errors on media gt.
My understanding is that Sgunit is embedded into the SAMedia block and hence need
To be iterated over separately.
Daniele,
Can you confirm if that is accurate.
Thanks,
RK
>
>
> Matt
>
> >
> > Based on original version by Paulo and Tvrtko
> >
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 30 ++++++++++++++++++------------
> > 1 file changed, 18 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 417c981e4968..9377f59c1ac2 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -2759,16 +2759,19 @@ static void gen11_irq_reset(struct
> drm_i915_private *dev_priv)
> >
> > static void dg1_irq_reset(struct drm_i915_private *dev_priv)
> > {
> > - struct intel_gt *gt = to_gt(dev_priv);
> > - struct intel_uncore *uncore = gt->uncore;
> > + struct intel_gt *gt;
> > + unsigned int i;
> >
> > dg1_master_intr_disable(dev_priv->uncore.regs);
> >
> > - gen11_gt_irq_reset(gt);
> > - gen11_display_irq_reset(dev_priv);
> > + for_each_gt(gt, dev_priv, i) {
> > + gen11_gt_irq_reset(gt);
> >
> > - GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
> > - GEN3_IRQ_RESET(uncore, GEN8_PCU_);
> > + GEN3_IRQ_RESET(gt->uncore, GEN11_GU_MISC_);
> > + GEN3_IRQ_RESET(gt->uncore, GEN8_PCU_);
> > + }
> > +
> > + gen11_display_irq_reset(dev_priv);
> > }
> >
> > void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
> > @@ -3422,13 +3425,16 @@ static void gen11_irq_postinstall(struct
> drm_i915_private *dev_priv)
> >
> > static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
> > {
> > - struct intel_gt *gt = to_gt(dev_priv);
> > - struct intel_uncore *uncore = gt->uncore;
> > u32 gu_misc_masked = GEN11_GU_MISC_GSE;
> > + struct intel_gt *gt;
> > + unsigned int i;
> >
> > - gen11_gt_irq_postinstall(gt);
> > + for_each_gt(gt, dev_priv, i) {
> > + gen11_gt_irq_postinstall(gt);
> >
> > - GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked,
> gu_misc_masked);
> > + GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_,
> ~gu_misc_masked,
> > + gu_misc_masked);
> > + }
> >
> > if (HAS_DISPLAY(dev_priv)) {
> > icp_irq_postinstall(dev_priv);
> > @@ -3437,8 +3443,8 @@ static void dg1_irq_postinstall(struct
> drm_i915_private *dev_priv)
> > GEN11_DISPLAY_IRQ_ENABLE);
> > }
> >
> > - dg1_master_intr_enable(uncore->regs);
> > - intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
> > + dg1_master_intr_enable(to_gt(dev_priv)->uncore->regs);
> > + intel_uncore_posting_read(to_gt(dev_priv)->uncore,
> DG1_MSTR_TILE_INTR);
> > }
> >
> > static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
> > --
> > 2.34.1
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/mtl: make IRQ reset and postinstall multi-gt aware
2023-03-07 0:14 ` Sripada, Radhakrishna
@ 2023-03-07 0:24 ` Matt Roper
2023-03-07 0:51 ` Ceraolo Spurio, Daniele
0 siblings, 1 reply; 23+ messages in thread
From: Matt Roper @ 2023-03-07 0:24 UTC (permalink / raw)
To: Sripada, Radhakrishna; +Cc: intel-gfx, De Marchi, Lucas, Zanoni, Paulo R
On Mon, Mar 06, 2023 at 04:14:49PM -0800, Sripada, Radhakrishna wrote:
> +Daniele,
>
> Hi Matt,
>
> > -----Original Message-----
> > From: Roper, Matthew D <matthew.d.roper@intel.com>
> > Sent: Monday, March 6, 2023 2:55 PM
> > To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; De Marchi, Lucas
> > <lucas.demarchi@intel.com>; Zanoni, Paulo R <paulo.r.zanoni@intel.com>
> > Subject: Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/mtl: make IRQ reset and
> > postinstall multi-gt aware
> >
> > On Wed, Mar 01, 2023 at 12:10:51PM -0800, Radhakrishna Sripada wrote:
> > > Irq reset and post install are to be made multi-gt aware for the
> > > interrupts to work for the media tile on Meteorlake. Iterate through
> > > all the gts to process irq reset for each gt.
> >
> > I think I mentioned on the previous version, but this isn't right. MTL
> > does not have separate interrupt registers for each GT the way
> > multi-tile platforms like PVC do. The GT interrupt registers you're
> > handling here are in the sgunit so there's only a single copy of them;
> > iterating over them multiple times in a row doesn't accomplish anything.
> >
> > The media engine bits are still on the same registers as the primary GT
> > and the GSC and media GuC are new additional bits that need to be
> > handled. The necessary handling for the GSC and media GuC should have
> > already landed in a187f13d51fa ("drm/i915/guc: handle interrupts from
> > media GuC") and c07ee636901d ("drm/i915/mtl: add GSC CS interrupt
> > support"), but if there's another bit that was missed somewhere (or if
> > we were doing something like looking at the wrong intel_gt's engine mask
> > somewhere), that would need to be addressed directly rather than just
> > looping over the same IRQ registers multiple times.
>
> This patch is needed to handle media interrupts. Without this patch we observed
> GuC not loading/communication errors on media gt.
>
> My understanding is that Sgunit is embedded into the SAMedia block and hence need
> To be iterated over separately.
No, the sgunit is not replicated. You can confirm by just going to the
various IRQ register pages in the bspec...there's only a single register
offset rather than (offset) and (offset+0x380000) like there are for GT
GSI registers. The i915 code also only adds the GSI offset to register
operations in the 0x0 - 0x40000 range.
Matt
>
> Daniele,
> Can you confirm if that is accurate.
>
> Thanks,
> RK
> >
> >
> > Matt
> >
> > >
> > > Based on original version by Paulo and Tvrtko
> > >
> > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_irq.c | 30 ++++++++++++++++++------------
> > > 1 file changed, 18 insertions(+), 12 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > > index 417c981e4968..9377f59c1ac2 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -2759,16 +2759,19 @@ static void gen11_irq_reset(struct
> > drm_i915_private *dev_priv)
> > >
> > > static void dg1_irq_reset(struct drm_i915_private *dev_priv)
> > > {
> > > - struct intel_gt *gt = to_gt(dev_priv);
> > > - struct intel_uncore *uncore = gt->uncore;
> > > + struct intel_gt *gt;
> > > + unsigned int i;
> > >
> > > dg1_master_intr_disable(dev_priv->uncore.regs);
> > >
> > > - gen11_gt_irq_reset(gt);
> > > - gen11_display_irq_reset(dev_priv);
> > > + for_each_gt(gt, dev_priv, i) {
> > > + gen11_gt_irq_reset(gt);
> > >
> > > - GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
> > > - GEN3_IRQ_RESET(uncore, GEN8_PCU_);
> > > + GEN3_IRQ_RESET(gt->uncore, GEN11_GU_MISC_);
> > > + GEN3_IRQ_RESET(gt->uncore, GEN8_PCU_);
> > > + }
> > > +
> > > + gen11_display_irq_reset(dev_priv);
> > > }
> > >
> > > void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
> > > @@ -3422,13 +3425,16 @@ static void gen11_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > >
> > > static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
> > > {
> > > - struct intel_gt *gt = to_gt(dev_priv);
> > > - struct intel_uncore *uncore = gt->uncore;
> > > u32 gu_misc_masked = GEN11_GU_MISC_GSE;
> > > + struct intel_gt *gt;
> > > + unsigned int i;
> > >
> > > - gen11_gt_irq_postinstall(gt);
> > > + for_each_gt(gt, dev_priv, i) {
> > > + gen11_gt_irq_postinstall(gt);
> > >
> > > - GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked,
> > gu_misc_masked);
> > > + GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_,
> > ~gu_misc_masked,
> > > + gu_misc_masked);
> > > + }
> > >
> > > if (HAS_DISPLAY(dev_priv)) {
> > > icp_irq_postinstall(dev_priv);
> > > @@ -3437,8 +3443,8 @@ static void dg1_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > > GEN11_DISPLAY_IRQ_ENABLE);
> > > }
> > >
> > > - dg1_master_intr_enable(uncore->regs);
> > > - intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
> > > + dg1_master_intr_enable(to_gt(dev_priv)->uncore->regs);
> > > + intel_uncore_posting_read(to_gt(dev_priv)->uncore,
> > DG1_MSTR_TILE_INTR);
> > > }
> > >
> > > static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
> > > --
> > > 2.34.1
> > >
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/mtl: make IRQ reset and postinstall multi-gt aware
2023-03-07 0:24 ` Matt Roper
@ 2023-03-07 0:51 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 23+ messages in thread
From: Ceraolo Spurio, Daniele @ 2023-03-07 0:51 UTC (permalink / raw)
To: Matt Roper, Sripada, Radhakrishna
Cc: intel-gfx, De Marchi, Lucas, Zanoni, Paulo R
On 3/6/2023 4:24 PM, Matt Roper wrote:
> On Mon, Mar 06, 2023 at 04:14:49PM -0800, Sripada, Radhakrishna wrote:
>> +Daniele,
>>
>> Hi Matt,
>>
>>> -----Original Message-----
>>> From: Roper, Matthew D <matthew.d.roper@intel.com>
>>> Sent: Monday, March 6, 2023 2:55 PM
>>> To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
>>> Cc: intel-gfx@lists.freedesktop.org; De Marchi, Lucas
>>> <lucas.demarchi@intel.com>; Zanoni, Paulo R <paulo.r.zanoni@intel.com>
>>> Subject: Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/mtl: make IRQ reset and
>>> postinstall multi-gt aware
>>>
>>> On Wed, Mar 01, 2023 at 12:10:51PM -0800, Radhakrishna Sripada wrote:
>>>> Irq reset and post install are to be made multi-gt aware for the
>>>> interrupts to work for the media tile on Meteorlake. Iterate through
>>>> all the gts to process irq reset for each gt.
>>> I think I mentioned on the previous version, but this isn't right. MTL
>>> does not have separate interrupt registers for each GT the way
>>> multi-tile platforms like PVC do. The GT interrupt registers you're
>>> handling here are in the sgunit so there's only a single copy of them;
>>> iterating over them multiple times in a row doesn't accomplish anything.
>>>
>>> The media engine bits are still on the same registers as the primary GT
>>> and the GSC and media GuC are new additional bits that need to be
>>> handled. The necessary handling for the GSC and media GuC should have
>>> already landed in a187f13d51fa ("drm/i915/guc: handle interrupts from
>>> media GuC") and c07ee636901d ("drm/i915/mtl: add GSC CS interrupt
>>> support"), but if there's another bit that was missed somewhere (or if
>>> we were doing something like looking at the wrong intel_gt's engine mask
>>> somewhere), that would need to be addressed directly rather than just
>>> looping over the same IRQ registers multiple times.
>> This patch is needed to handle media interrupts. Without this patch we observed
>> GuC not loading/communication errors on media gt.
>>
>> My understanding is that Sgunit is embedded into the SAMedia block and hence need
>> To be iterated over separately.
> No, the sgunit is not replicated. You can confirm by just going to the
> various IRQ register pages in the bspec...there's only a single register
> offset rather than (offset) and (offset+0x380000) like there are for GT
> GSI registers. The i915 code also only adds the GSI offset to register
> operations in the 0x0 - 0x40000 range.
I agree with Matt that this is how the HW works. The issue here is that
the gen11_gt_irq_* functions only program the interrupts for GuC and
engines on the given GT, so when calling them for the root GT they will
only program the interrupts for RCS, BCS, CCS and the root GuC. We could
modify the functions to program all registers from the root GT, but IMO
that doesn't work very well with how other parts of the driver implement
the MTL multi-gt flow.
Daniele
>
> Matt
>
>> Daniele,
>> Can you confirm if that is accurate.
>>
>> Thanks,
>> RK
>>>
>>> Matt
>>>
>>>> Based on original version by Paulo and Tvrtko
>>>>
>>>> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
>>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>>> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/i915_irq.c | 30 ++++++++++++++++++------------
>>>> 1 file changed, 18 insertions(+), 12 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>>>> index 417c981e4968..9377f59c1ac2 100644
>>>> --- a/drivers/gpu/drm/i915/i915_irq.c
>>>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>>>> @@ -2759,16 +2759,19 @@ static void gen11_irq_reset(struct
>>> drm_i915_private *dev_priv)
>>>> static void dg1_irq_reset(struct drm_i915_private *dev_priv)
>>>> {
>>>> - struct intel_gt *gt = to_gt(dev_priv);
>>>> - struct intel_uncore *uncore = gt->uncore;
>>>> + struct intel_gt *gt;
>>>> + unsigned int i;
>>>>
>>>> dg1_master_intr_disable(dev_priv->uncore.regs);
>>>>
>>>> - gen11_gt_irq_reset(gt);
>>>> - gen11_display_irq_reset(dev_priv);
>>>> + for_each_gt(gt, dev_priv, i) {
>>>> + gen11_gt_irq_reset(gt);
>>>>
>>>> - GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
>>>> - GEN3_IRQ_RESET(uncore, GEN8_PCU_);
>>>> + GEN3_IRQ_RESET(gt->uncore, GEN11_GU_MISC_);
>>>> + GEN3_IRQ_RESET(gt->uncore, GEN8_PCU_);
>>>> + }
>>>> +
>>>> + gen11_display_irq_reset(dev_priv);
>>>> }
>>>>
>>>> void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
>>>> @@ -3422,13 +3425,16 @@ static void gen11_irq_postinstall(struct
>>> drm_i915_private *dev_priv)
>>>> static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
>>>> {
>>>> - struct intel_gt *gt = to_gt(dev_priv);
>>>> - struct intel_uncore *uncore = gt->uncore;
>>>> u32 gu_misc_masked = GEN11_GU_MISC_GSE;
>>>> + struct intel_gt *gt;
>>>> + unsigned int i;
>>>>
>>>> - gen11_gt_irq_postinstall(gt);
>>>> + for_each_gt(gt, dev_priv, i) {
>>>> + gen11_gt_irq_postinstall(gt);
>>>>
>>>> - GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked,
>>> gu_misc_masked);
>>>> + GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_,
>>> ~gu_misc_masked,
>>>> + gu_misc_masked);
>>>> + }
>>>>
>>>> if (HAS_DISPLAY(dev_priv)) {
>>>> icp_irq_postinstall(dev_priv);
>>>> @@ -3437,8 +3443,8 @@ static void dg1_irq_postinstall(struct
>>> drm_i915_private *dev_priv)
>>>> GEN11_DISPLAY_IRQ_ENABLE);
>>>> }
>>>>
>>>> - dg1_master_intr_enable(uncore->regs);
>>>> - intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
>>>> + dg1_master_intr_enable(to_gt(dev_priv)->uncore->regs);
>>>> + intel_uncore_posting_read(to_gt(dev_priv)->uncore,
>>> DG1_MSTR_TILE_INTR);
>>>> }
>>>>
>>>> static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
>>>> --
>>>> 2.34.1
>>>>
>>> --
>>> Matt Roper
>>> Graphics Software Engineer
>>> Linux GPU Platform Enablement
>>> Intel Corporation
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH v3 1/5] drm/i915/mtl: Fix Wa_16015201720 implementation
2023-03-01 20:10 ` [Intel-gfx] [PATCH v3 1/5] drm/i915/mtl: Fix Wa_16015201720 implementation Radhakrishna Sripada
2023-03-06 22:45 ` Matt Roper
@ 2023-03-09 16:30 ` Andi Shyti
2023-03-09 18:01 ` Sripada, Radhakrishna
1 sibling, 1 reply; 23+ messages in thread
From: Andi Shyti @ 2023-03-09 16:30 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx, Lucas De Marchi
Hi Radhakrishna,
On Wed, Mar 01, 2023 at 12:10:49PM -0800, Radhakrishna Sripada wrote:
> The commit 2357f2b271ad ("drm/i915/mtl: Initial display workarounds")
> extended the workaround Wa_16015201720 to MTL. However the registers
> that the original WA implemented moved for MTL.
>
> Implement the workaround with the correct register.
>
> v3: Skip clock gating for pipe C, D DMC's and fix the title
>
> Fixes: 2357f2b271ad ("drm/i915/mtl: Initial display workarounds")
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 26 +++++++++++++++++++-----
> drivers/gpu/drm/i915/i915_reg.h | 10 ++++++---
> 2 files changed, 28 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index f70ada2357dc..b4283cf319f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -389,15 +389,12 @@ static void disable_all_event_handlers(struct drm_i915_private *i915)
> }
> }
>
> -static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
> +static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
> {
> enum pipe pipe;
>
> - if (DISPLAY_VER(i915) < 13)
> - return;
> -
Why is this not needed anyomore?
> /*
> - * Wa_16015201720:adl-p,dg2, mtl
> + * Wa_16015201720:adl-p,dg2
> * The WA requires clock gating to be disabled all the time
> * for pipe A and B.
> * For pipe C and D clock gating needs to be disabled only
> @@ -413,6 +410,25 @@ static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
> PIPEDMC_GATING_DIS, 0);
> }
>
> +static void mtl_pipedmc_clock_gating_wa(struct drm_i915_private *i915)
> +{
> + /*
> + * Wa_16015201720
> + * The WA requires clock gating to be disabled all the time
> + * for pipe A and B.
> + */
> + intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0,
> + MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B);
> +}
> +
> +static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)
> +{
> + if (DISPLAY_VER(i915) >= 14 && enable)
> + return mtl_pipedmc_clock_gating_wa(i915);
> + else if (DISPLAY_VER(i915) == 13)
> + return adlp_pipedmc_clock_gating_wa(i915, enable);
don't you get an error here? Please don't return anything.
> +}
> +
> void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe)
> {
> enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c1efa655fb68..7c9ac5b43831 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1794,9 +1794,13 @@
> * GEN9 clock gating regs
> */
> #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
> -#define DARBF_GATING_DIS (1 << 27)
> -#define PWM2_GATING_DIS (1 << 14)
> -#define PWM1_GATING_DIS (1 << 13)
> +#define DARBF_GATING_DIS REG_BIT(27)
> +#define MTL_PIPEDMC_GATING_DIS_A REG_BIT(15)
> +#define MTL_PIPEDMC_GATING_DIS_B REG_BIT(14)
you could eventually use a GENMASK here and it can be:
#define MTL_PIPEDMC_GATING_DIS REG_GENMASK(15, 14)
> +#define PWM2_GATING_DIS REG_BIT(14)
> +#define MTL_PIPEDMC_GATING_DIS_C REG_BIT(13)
Is this needed?
> +#define PWM1_GATING_DIS REG_BIT(13)
> +#define MTL_PIPEDMC_GATING_DIS_D REG_BIT(12)
Is this needed?
Thanks,
Andi
> #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
> #define TGL_VRH_GATING_DIS REG_BIT(31)
> --
> 2.34.1
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH v3 4/5] drm/i915/fbdev: lock the fbdev obj before vma pin
2023-03-01 20:10 ` [Intel-gfx] [PATCH v3 4/5] drm/i915/fbdev: lock the fbdev obj before vma pin Radhakrishna Sripada
@ 2023-03-09 17:18 ` Andi Shyti
2023-03-09 17:55 ` Sripada, Radhakrishna
0 siblings, 1 reply; 23+ messages in thread
From: Andi Shyti @ 2023-03-09 17:18 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx, Matthew Auld, Chris Wilson
Hi Radhakrishna,
On Wed, Mar 01, 2023 at 12:10:52PM -0800, Radhakrishna Sripada wrote:
> From: Tejas Upadhyay <tejas.upadhyay@intel.com>
>
> lock the fbdev obj before calling into
> i915_vma_pin_iomap(). This helps to solve below :
>
> <7>[ 93.563308] i915 0000:00:02.0: [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
> <4>[ 93.581844] ------------[ cut here ]------------
> <4>[ 93.581855] WARNING: CPU: 12 PID: 625 at drivers/gpu/drm/i915/gem/i915_gem_pages.c:424 i915_gem_object_pin_map+0x152/0x1c0 [i915]
>
> Fixes: f0b6b01b3efe ("drm/i915: Add ww context to intel_dpt_pin, v2.")
> Cc: Chris Wilson <chris.p.wilson@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Andi
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH v3 5/5] drm/i915/display/mtl: Program latch to phy reset
2023-03-01 20:10 ` [Intel-gfx] [PATCH v3 5/5] drm/i915/display/mtl: Program latch to phy reset Radhakrishna Sripada
@ 2023-03-09 17:28 ` Andi Shyti
2023-03-09 17:55 ` Sripada, Radhakrishna
0 siblings, 1 reply; 23+ messages in thread
From: Andi Shyti @ 2023-03-09 17:28 UTC (permalink / raw)
To: Radhakrishna Sripada; +Cc: intel-gfx, Matt Roper
Hi,
On Wed, Mar 01, 2023 at 12:10:53PM -0800, Radhakrishna Sripada wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
>
> Latch reset of phys during DC9 and when driver is unloaded to avoid
> phy reset.
>
> Specification ask us to program it closer to the step that enables
> DC9 in DC_STATE_EN but doing this way allow us to sanitize the phy
> latch during driver load.
>
> BSpec: 49197
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Thanks,
Andi
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH v3 5/5] drm/i915/display/mtl: Program latch to phy reset
2023-03-09 17:28 ` Andi Shyti
@ 2023-03-09 17:55 ` Sripada, Radhakrishna
0 siblings, 0 replies; 23+ messages in thread
From: Sripada, Radhakrishna @ 2023-03-09 17:55 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx, Roper, Matthew D
Thank you for the Review. Pushed.
-Radhakrishna Sripada
> -----Original Message-----
> From: Andi Shyti <andi.shyti@linux.intel.com>
> Sent: Thursday, March 9, 2023 9:29 AM
> To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: Re: [Intel-gfx] [PATCH v3 5/5] drm/i915/display/mtl: Program latch to
> phy reset
>
> Hi,
>
> On Wed, Mar 01, 2023 at 12:10:53PM -0800, Radhakrishna Sripada wrote:
> > From: José Roberto de Souza <jose.souza@intel.com>
> >
> > Latch reset of phys during DC9 and when driver is unloaded to avoid
> > phy reset.
> >
> > Specification ask us to program it closer to the step that enables
> > DC9 in DC_STATE_EN but doing this way allow us to sanitize the phy
> > latch during driver load.
> >
> > BSpec: 49197
> > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>
> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
>
> Thanks,
> Andi
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH v3 4/5] drm/i915/fbdev: lock the fbdev obj before vma pin
2023-03-09 17:18 ` Andi Shyti
@ 2023-03-09 17:55 ` Sripada, Radhakrishna
0 siblings, 0 replies; 23+ messages in thread
From: Sripada, Radhakrishna @ 2023-03-09 17:55 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx, Auld, Matthew, Wilson, Chris P
Thank you for the Review. Pushed.
-Radhakrishna Sripada
> -----Original Message-----
> From: Andi Shyti <andi.shyti@linux.intel.com>
> Sent: Thursday, March 9, 2023 9:18 AM
> To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Auld, Matthew <matthew.auld@intel.com>;
> Wilson, Chris P <chris.p.wilson@intel.com>
> Subject: Re: [Intel-gfx] [PATCH v3 4/5] drm/i915/fbdev: lock the fbdev obj
> before vma pin
>
> Hi Radhakrishna,
>
> On Wed, Mar 01, 2023 at 12:10:52PM -0800, Radhakrishna Sripada wrote:
> > From: Tejas Upadhyay <tejas.upadhyay@intel.com>
> >
> > lock the fbdev obj before calling into
> > i915_vma_pin_iomap(). This helps to solve below :
> >
> > <7>[ 93.563308] i915 0000:00:02.0: [drm:intelfb_create [i915]] no BIOS fb,
> allocating a new one
> > <4>[ 93.581844] ------------[ cut here ]------------
> > <4>[ 93.581855] WARNING: CPU: 12 PID: 625 at
> drivers/gpu/drm/i915/gem/i915_gem_pages.c:424
> i915_gem_object_pin_map+0x152/0x1c0 [i915]
> >
> > Fixes: f0b6b01b3efe ("drm/i915: Add ww context to intel_dpt_pin, v2.")
> > Cc: Chris Wilson <chris.p.wilson@intel.com>
> > Cc: Matthew Auld <matthew.auld@intel.com>
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>
> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
>
> Andi
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH v3 1/5] drm/i915/mtl: Fix Wa_16015201720 implementation
2023-03-09 16:30 ` Andi Shyti
@ 2023-03-09 18:01 ` Sripada, Radhakrishna
2023-03-09 23:08 ` Andi Shyti
0 siblings, 1 reply; 23+ messages in thread
From: Sripada, Radhakrishna @ 2023-03-09 18:01 UTC (permalink / raw)
To: Andi Shyti; +Cc: Roper, Matthew D, intel-gfx, De Marchi, Lucas
Hi Andi,
> -----Original Message-----
> From: Andi Shyti <andi.shyti@linux.intel.com>
> Sent: Thursday, March 9, 2023 8:30 AM
> To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: Re: [Intel-gfx] [PATCH v3 1/5] drm/i915/mtl: Fix Wa_16015201720
> implementation
>
> Hi Radhakrishna,
>
> On Wed, Mar 01, 2023 at 12:10:49PM -0800, Radhakrishna Sripada wrote:
> > The commit 2357f2b271ad ("drm/i915/mtl: Initial display workarounds")
> > extended the workaround Wa_16015201720 to MTL. However the registers
> > that the original WA implemented moved for MTL.
> >
> > Implement the workaround with the correct register.
> >
> > v3: Skip clock gating for pipe C, D DMC's and fix the title
> >
> > Fixes: 2357f2b271ad ("drm/i915/mtl: Initial display workarounds")
> > Cc: Matt Atwood <matthew.s.atwood@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dmc.c | 26 +++++++++++++++++++-----
> > drivers/gpu/drm/i915/i915_reg.h | 10 ++++++---
> > 2 files changed, 28 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> > index f70ada2357dc..b4283cf319f2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > @@ -389,15 +389,12 @@ static void disable_all_event_handlers(struct
> drm_i915_private *i915)
> > }
> > }
> >
> > -static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool
> enable)
> > +static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915,
> bool enable)
> > {
> > enum pipe pipe;
> >
> > - if (DISPLAY_VER(i915) < 13)
> > - return;
> > -
>
> Why is this not needed anyomore?
With the check below while calling the function the check here becomes redundant.
>
> > /*
> > - * Wa_16015201720:adl-p,dg2, mtl
> > + * Wa_16015201720:adl-p,dg2
> > * The WA requires clock gating to be disabled all the time
> > * for pipe A and B.
> > * For pipe C and D clock gating needs to be disabled only
> > @@ -413,6 +410,25 @@ static void pipedmc_clock_gating_wa(struct
> drm_i915_private *i915, bool enable)
> > PIPEDMC_GATING_DIS, 0);
> > }
> >
> > +static void mtl_pipedmc_clock_gating_wa(struct drm_i915_private *i915)
> > +{
> > + /*
> > + * Wa_16015201720
> > + * The WA requires clock gating to be disabled all the time
> > + * for pipe A and B.
> > + */
> > + intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0,
> > + MTL_PIPEDMC_GATING_DIS_A |
> MTL_PIPEDMC_GATING_DIS_B);
> > +}
> > +
> > +static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool
> enable)
> > +{
> > + if (DISPLAY_VER(i915) >= 14 && enable)
> > + return mtl_pipedmc_clock_gating_wa(i915);
> > + else if (DISPLAY_VER(i915) == 13)
> > + return adlp_pipedmc_clock_gating_wa(i915, enable);
>
> don't you get an error here? Please don't return anything.
Addressed based on review comments from Matt Roper.
>
> > +}
> > +
> > void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe)
> > {
> > enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> > index c1efa655fb68..7c9ac5b43831 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1794,9 +1794,13 @@
> > * GEN9 clock gating regs
> > */
> > #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
> > -#define DARBF_GATING_DIS (1 << 27)
> > -#define PWM2_GATING_DIS (1 << 14)
> > -#define PWM1_GATING_DIS (1 << 13)
> > +#define DARBF_GATING_DIS REG_BIT(27)
> > +#define MTL_PIPEDMC_GATING_DIS_A REG_BIT(15)
> > +#define MTL_PIPEDMC_GATING_DIS_B REG_BIT(14)
>
> you could eventually use a GENMASK here and it can be:
We may have to play with individual pipes here and b-spec defines them as
Individual bits. So leaving them as is.
>
> #define MTL_PIPEDMC_GATING_DIS REG_GENMASK(15, 14)
>
> > +#define PWM2_GATING_DIS REG_BIT(14)
> > +#define MTL_PIPEDMC_GATING_DIS_C REG_BIT(13)
>
> Is this needed?
Below
>
> > +#define PWM1_GATING_DIS REG_BIT(13)
> > +#define MTL_PIPEDMC_GATING_DIS_D REG_BIT(12)
>
> Is this needed?
Removed MTL_PIPEDMC_GATING_DIS_D and MTL_PIPEDMC_GATING_DIS_C
Based on review feedback from MattR.
Since most of the comments aligned with Matt's suggestion pushed with Matt's r-b.
Thanks you for the review.
-Radhakrishna Sripada
>
> Thanks,
> Andi
>
> > #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
> > #define TGL_VRH_GATING_DIS REG_BIT(31)
> > --
> > 2.34.1
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH v3 1/5] drm/i915/mtl: Fix Wa_16015201720 implementation
2023-03-09 18:01 ` Sripada, Radhakrishna
@ 2023-03-09 23:08 ` Andi Shyti
2023-03-10 6:06 ` Sripada, Radhakrishna
0 siblings, 1 reply; 23+ messages in thread
From: Andi Shyti @ 2023-03-09 23:08 UTC (permalink / raw)
To: Sripada, Radhakrishna; +Cc: Roper, Matthew D, intel-gfx, De Marchi, Lucas
Hi Radhakrishna,
> Since most of the comments aligned with Matt's suggestion pushed with Matt's r-b.
OK, but next time, please hold on a bit as I might also have had
disagreements on your answers or I want to see it tested again
with the new changes.
It's not the case as I would have r-b it anyway and the changes
were trivial, but next time, please give it a bit more time until
all questions are answered.
> Thanks you for the review.
You're welcome :)
Thanks,
Andi
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH v3 1/5] drm/i915/mtl: Fix Wa_16015201720 implementation
2023-03-09 23:08 ` Andi Shyti
@ 2023-03-10 6:06 ` Sripada, Radhakrishna
0 siblings, 0 replies; 23+ messages in thread
From: Sripada, Radhakrishna @ 2023-03-10 6:06 UTC (permalink / raw)
To: Andi Shyti; +Cc: Roper, Matthew D, intel-gfx, De Marchi, Lucas
Sure Andi. Will be more cautious.
Radhakrishna Sripada
> -----Original Message-----
> From: Andi Shyti <andi.shyti@linux.intel.com>
> Sent: Thursday, March 9, 2023 3:09 PM
> To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> Cc: Andi Shyti <andi.shyti@linux.intel.com>; intel-gfx@lists.freedesktop.org; De
> Marchi, Lucas <lucas.demarchi@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: Re: [Intel-gfx] [PATCH v3 1/5] drm/i915/mtl: Fix Wa_16015201720
> implementation
>
> Hi Radhakrishna,
>
> > Since most of the comments aligned with Matt's suggestion pushed with
> Matt's r-b.
>
> OK, but next time, please hold on a bit as I might also have had
> disagreements on your answers or I want to see it tested again
> with the new changes.
>
> It's not the case as I would have r-b it anyway and the changes
> were trivial, but next time, please give it a bit more time until
> all questions are answered.
>
> > Thanks you for the review.
>
> You're welcome :)
>
> Thanks,
> Andi
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2023-03-10 6:06 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-01 20:10 [Intel-gfx] [PATCH v3 0/5] Misc Meteorlake patches Radhakrishna Sripada
2023-03-01 20:10 ` [Intel-gfx] [PATCH v3 1/5] drm/i915/mtl: Fix Wa_16015201720 implementation Radhakrishna Sripada
2023-03-06 22:45 ` Matt Roper
2023-03-09 16:30 ` Andi Shyti
2023-03-09 18:01 ` Sripada, Radhakrishna
2023-03-09 23:08 ` Andi Shyti
2023-03-10 6:06 ` Sripada, Radhakrishna
2023-03-01 20:10 ` [Intel-gfx] [PATCH v3 2/5] drm/i915/gt: generate per tile debugfs files Radhakrishna Sripada
2023-03-01 21:03 ` Sripada, Radhakrishna
2023-03-01 20:10 ` [Intel-gfx] [PATCH v3 3/5] drm/i915/mtl: make IRQ reset and postinstall multi-gt aware Radhakrishna Sripada
2023-03-06 22:54 ` Matt Roper
2023-03-07 0:14 ` Sripada, Radhakrishna
2023-03-07 0:24 ` Matt Roper
2023-03-07 0:51 ` Ceraolo Spurio, Daniele
2023-03-01 20:10 ` [Intel-gfx] [PATCH v3 4/5] drm/i915/fbdev: lock the fbdev obj before vma pin Radhakrishna Sripada
2023-03-09 17:18 ` Andi Shyti
2023-03-09 17:55 ` Sripada, Radhakrishna
2023-03-01 20:10 ` [Intel-gfx] [PATCH v3 5/5] drm/i915/display/mtl: Program latch to phy reset Radhakrishna Sripada
2023-03-09 17:28 ` Andi Shyti
2023-03-09 17:55 ` Sripada, Radhakrishna
2023-03-01 22:50 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Misc Meteorlake patches (rev3) Patchwork
2023-03-01 23:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-05 8:52 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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