* [Intel-gfx] [PATCH 01/11] drm/i915/perf: Drop wakeref on GuC RC error
2023-03-23 22:58 [Intel-gfx] [PATCH 00/11] Add OAM support for MTL Umesh Nerlige Ramappa
@ 2023-03-23 22:58 ` Umesh Nerlige Ramappa
2023-03-23 22:58 ` [Intel-gfx] [PATCH 02/11] drm/i915/mtl: Synchronize i915/BIOS on C6 enabling Umesh Nerlige Ramappa
` (12 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2023-03-23 22:58 UTC (permalink / raw)
To: intel-gfx
From: Chris Wilson <chris.p.wilson@linux.intel.com>
If we fail to adjust the GuC run-control on opening the perf stream,
make sure we unwind the wakeref just taken.
v2: Retain old goto label names (Ashutosh)
v3: Drop bitfield boolean
Fixes: 01e742746785 ("drm/i915/guc: Support OA when Wa_16011777198 is enabled")
Signed-off-by: Chris Wilson <chris.p.wilson@linux.intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 14 +++++++++-----
drivers/gpu/drm/i915/i915_perf_types.h | 6 ++++++
2 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 824a34ec0b83..283a4a3c6862 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1592,9 +1592,7 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
/*
* Wa_16011777198:dg2: Unset the override of GUCRC mode to enable rc6.
*/
- if (intel_uc_uses_guc_rc(>->uc) &&
- (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
- IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)))
+ if (stream->override_gucrc)
drm_WARN_ON(>->i915->drm,
intel_guc_slpc_unset_gucrc_mode(>->uc.guc.slpc));
@@ -3305,8 +3303,10 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
if (ret) {
drm_dbg(&stream->perf->i915->drm,
"Unable to override gucrc mode\n");
- goto err_config;
+ goto err_gucrc;
}
+
+ stream->override_gucrc = true;
}
ret = alloc_oa_buffer(stream);
@@ -3345,11 +3345,15 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
free_oa_buffer(stream);
err_oa_buf_alloc:
- free_oa_configs(stream);
+ if (stream->override_gucrc)
+ intel_guc_slpc_unset_gucrc_mode(>->uc.guc.slpc);
+err_gucrc:
intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);
intel_engine_pm_put(stream->engine);
+ free_oa_configs(stream);
+
err_config:
free_noa_wait(stream);
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h b/drivers/gpu/drm/i915/i915_perf_types.h
index ca150b7af3f2..4d5d8c365d9e 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -316,6 +316,12 @@ struct i915_perf_stream {
* buffer should be checked for available data.
*/
u64 poll_oa_period;
+
+ /**
+ * @override_gucrc: GuC RC has been overridden for the perf stream,
+ * and we need to restore the default configuration on release.
+ */
+ bool override_gucrc;
};
/**
--
2.36.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Intel-gfx] [PATCH 02/11] drm/i915/mtl: Synchronize i915/BIOS on C6 enabling
2023-03-23 22:58 [Intel-gfx] [PATCH 00/11] Add OAM support for MTL Umesh Nerlige Ramappa
2023-03-23 22:58 ` [Intel-gfx] [PATCH 01/11] drm/i915/perf: Drop wakeref on GuC RC error Umesh Nerlige Ramappa
@ 2023-03-23 22:58 ` Umesh Nerlige Ramappa
2023-03-23 22:58 ` [Intel-gfx] [PATCH 03/11] drm/i915/perf: Validate OA sseu config outside switch Umesh Nerlige Ramappa
` (11 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2023-03-23 22:58 UTC (permalink / raw)
To: intel-gfx
From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
If BIOS enables/disables C6, i915 should do the same. Also, retain
this value across driver reloads. This is needed only for MTL as
of now due to an existing bug in OA which needs C6 disabled for
it to function. BIOS behavior is also different across platforms
in terms of how C6 is enabled.
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 26 ++++++++++++++++++++---
drivers/gpu/drm/i915/gt/intel_rc6.h | 2 ++
drivers/gpu/drm/i915/gt/intel_rc6_types.h | 2 ++
3 files changed, 27 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index f4150f61f39c..f760586f9f46 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -420,6 +420,21 @@ static void vlv_rc6_enable(struct intel_rc6 *rc6)
GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
}
+bool intel_check_bios_c6_setup(struct intel_rc6 *rc6)
+{
+ if (!rc6->bios_state_captured) {
+ struct intel_uncore *uncore = rc6_to_uncore(rc6);
+ intel_wakeref_t wakeref;
+
+ with_intel_runtime_pm(uncore->rpm, wakeref)
+ rc6->bios_rc_state = intel_uncore_read(uncore, GEN6_RC_STATE);
+
+ rc6->bios_state_captured = true;
+ }
+
+ return rc6->bios_rc_state & RC_SW_TARGET_STATE_MASK;
+}
+
static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
{
struct intel_uncore *uncore = rc6_to_uncore(rc6);
@@ -503,10 +518,10 @@ static bool rc6_supported(struct intel_rc6 *rc6)
return false;
}
- if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
- gt->type == GT_MEDIA) {
+ if (IS_METEORLAKE(gt->i915) &&
+ !intel_check_bios_c6_setup(rc6)) {
drm_notice(&i915->drm,
- "Media RC6 disabled on A step\n");
+ "C6 disabled by BIOS\n");
return false;
}
@@ -707,9 +722,14 @@ void intel_rc6_disable(struct intel_rc6 *rc6)
void intel_rc6_fini(struct intel_rc6 *rc6)
{
struct drm_i915_gem_object *pctx;
+ struct intel_uncore *uncore = rc6_to_uncore(rc6);
intel_rc6_disable(rc6);
+ /* We want the BIOS C6 state preserved across loads for MTL */
+ if (IS_METEORLAKE(rc6_to_i915(rc6)) && rc6->bios_state_captured)
+ set(uncore, GEN6_RC_STATE, rc6->bios_rc_state);
+
pctx = fetch_and_zero(&rc6->pctx);
if (pctx)
i915_gem_object_put(pctx);
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.h b/drivers/gpu/drm/i915/gt/intel_rc6.h
index 456fa668a276..e137c2c397c2 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.h
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.h
@@ -27,4 +27,6 @@ u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id);
void intel_rc6_print_residency(struct seq_file *m, const char *title,
enum intel_rc6_res_type id);
+bool intel_check_bios_c6_setup(struct intel_rc6 *rc6);
+
#endif /* INTEL_RC6_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6_types.h b/drivers/gpu/drm/i915/gt/intel_rc6_types.h
index fa23c4dce00b..cd4587098162 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_rc6_types.h
@@ -29,6 +29,7 @@ struct intel_rc6 {
u64 cur_residency[INTEL_RC6_RES_MAX];
u32 ctl_enable;
+ u32 bios_rc_state;
struct drm_i915_gem_object *pctx;
@@ -36,6 +37,7 @@ struct intel_rc6 {
bool enabled : 1;
bool manual : 1;
bool wakeref : 1;
+ bool bios_state_captured : 1;
};
#endif /* INTEL_RC6_TYPES_H */
--
2.36.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Intel-gfx] [PATCH 03/11] drm/i915/perf: Validate OA sseu config outside switch
2023-03-23 22:58 [Intel-gfx] [PATCH 00/11] Add OAM support for MTL Umesh Nerlige Ramappa
2023-03-23 22:58 ` [Intel-gfx] [PATCH 01/11] drm/i915/perf: Drop wakeref on GuC RC error Umesh Nerlige Ramappa
2023-03-23 22:58 ` [Intel-gfx] [PATCH 02/11] drm/i915/mtl: Synchronize i915/BIOS on C6 enabling Umesh Nerlige Ramappa
@ 2023-03-23 22:58 ` Umesh Nerlige Ramappa
2023-03-23 22:58 ` [Intel-gfx] [PATCH 04/11] drm/i915/perf: Group engines into respective OA groups Umesh Nerlige Ramappa
` (10 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2023-03-23 22:58 UTC (permalink / raw)
To: intel-gfx
Once OA supports media engine class:instance, the engine can only be
validated outside the switch since class and instance parameters are
separate entities. Since OA sseu config depends on engine
class:instance, validate OA sseu config outside the switch.
v2: (Ashutosh)
- Clarify commit message
- Use drm_dbg instead of DRM_DEBUG
- Reorder stack variables
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 23 +++++++++++++----------
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 283a4a3c6862..ebd76b5c9712 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3940,7 +3940,9 @@ static int read_properties_unlocked(struct i915_perf *perf,
u32 n_props,
struct perf_open_properties *props)
{
+ struct drm_i915_gem_context_param_sseu user_sseu;
u64 __user *uprop = uprops;
+ bool config_sseu = false;
u32 i;
int ret;
@@ -4069,8 +4071,6 @@ static int read_properties_unlocked(struct i915_perf *perf,
props->hold_preemption = !!value;
break;
case DRM_I915_PERF_PROP_GLOBAL_SSEU: {
- struct drm_i915_gem_context_param_sseu user_sseu;
-
if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 50)) {
drm_dbg(&perf->i915->drm,
"SSEU config not supported on gfx %x\n",
@@ -4085,14 +4085,7 @@ static int read_properties_unlocked(struct i915_perf *perf,
"Unable to copy global sseu parameter\n");
return -EFAULT;
}
-
- ret = get_sseu_config(&props->sseu, props->engine, &user_sseu);
- if (ret) {
- drm_dbg(&perf->i915->drm,
- "Invalid SSEU configuration\n");
- return ret;
- }
- props->has_sseu = true;
+ config_sseu = true;
break;
}
case DRM_I915_PERF_PROP_POLL_OA_PERIOD:
@@ -4112,6 +4105,16 @@ static int read_properties_unlocked(struct i915_perf *perf,
uprop += 2;
}
+ if (config_sseu) {
+ ret = get_sseu_config(&props->sseu, props->engine, &user_sseu);
+ if (ret) {
+ drm_dbg(&perf->i915->drm,
+ "Invalid SSEU configuration\n");
+ return ret;
+ }
+ props->has_sseu = true;
+ }
+
return 0;
}
--
2.36.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Intel-gfx] [PATCH 04/11] drm/i915/perf: Group engines into respective OA groups
2023-03-23 22:58 [Intel-gfx] [PATCH 00/11] Add OAM support for MTL Umesh Nerlige Ramappa
` (2 preceding siblings ...)
2023-03-23 22:58 ` [Intel-gfx] [PATCH 03/11] drm/i915/perf: Validate OA sseu config outside switch Umesh Nerlige Ramappa
@ 2023-03-23 22:58 ` Umesh Nerlige Ramappa
2023-03-23 22:58 ` [Intel-gfx] [PATCH 05/11] drm/i915/perf: Fail modprobe if i915_perf_init fails on OOM Umesh Nerlige Ramappa
` (9 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2023-03-23 22:58 UTC (permalink / raw)
To: intel-gfx
Now that we may have multiple OA units in a single GT as well as on
separate GTs, create an engine group that maps to a single OA unit.
v2: (Jani)
- Drop warning on ENOMEM
- Reorder patch in the series
v3: (Ashutosh)
- Remove unused members from perf structs
- Update comments
- Update engine_supports_oa check
- Just return 1 in num_perf_groups_per_gt for now
- Set engine->oa_group to NULL to begin with
v4: Use engine_supports_oa() check in oa_init_reg_state (Ashutosh)
v5: Rebase after dropping engine_supports_oa helper
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 10 +++
drivers/gpu/drm/i915/gt/intel_sseu.c | 3 +-
drivers/gpu/drm/i915/i915_perf.c | 93 ++++++++++++++++++--
drivers/gpu/drm/i915/i915_perf_types.h | 33 ++++++-
4 files changed, 127 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 0a071e5da1a8..960291f88fd6 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -53,6 +53,8 @@ struct intel_gt;
struct intel_ring;
struct intel_uncore;
struct intel_breadcrumbs;
+struct intel_engine_cs;
+struct i915_perf_group;
typedef u32 intel_engine_mask_t;
#define ALL_ENGINES ((intel_engine_mask_t)~0ul)
@@ -617,6 +619,14 @@ struct intel_engine_cs {
} props, defaults;
I915_SELFTEST_DECLARE(struct fault_attr reset_timeout);
+
+ /*
+ * The perf group maps to one OA unit which controls one OA buffer. All
+ * reports corresponding to this engine will be reported to this OA
+ * buffer. An engine will map to a single OA unit, but a single OA unit
+ * can generate reports for multiple engines.
+ */
+ struct i915_perf_group *oa_group;
};
static inline bool
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 6c6198a257ac..1141f875f5bd 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -6,6 +6,7 @@
#include <linux/string_helpers.h>
#include "i915_drv.h"
+#include "i915_perf_types.h"
#include "intel_engine_regs.h"
#include "intel_gt_regs.h"
#include "intel_sseu.h"
@@ -677,7 +678,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
* If i915/perf is active, we want a stable powergating configuration
* on the system. Use the configuration pinned by i915/perf.
*/
- if (gt->perf.exclusive_stream)
+ if (gt->perf.group && gt->perf.group[PERF_GROUP_OAG].exclusive_stream)
req_sseu = >->perf.sseu;
slices = hweight8(req_sseu->slice_mask);
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index ebd76b5c9712..cf4ea5e389a5 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1570,12 +1570,18 @@ free_noa_wait(struct i915_perf_stream *stream)
i915_vma_unpin_and_release(&stream->noa_wait, 0);
}
+static bool engine_supports_oa(const struct intel_engine_cs *engine)
+{
+ return engine->oa_group;
+}
+
static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
{
struct i915_perf *perf = stream->perf;
struct intel_gt *gt = stream->engine->gt;
+ struct i915_perf_group *g = stream->engine->oa_group;
- if (WARN_ON(stream != gt->perf.exclusive_stream))
+ if (WARN_ON(stream != g->exclusive_stream))
return;
/*
@@ -1584,7 +1590,7 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
*
* See i915_oa_init_reg_state() and lrc_configure_all_contexts()
*/
- WRITE_ONCE(gt->perf.exclusive_stream, NULL);
+ WRITE_ONCE(g->exclusive_stream, NULL);
perf->ops.disable_metric_set(stream);
free_oa_buffer(stream);
@@ -3182,6 +3188,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
{
struct drm_i915_private *i915 = stream->perf->i915;
struct i915_perf *perf = stream->perf;
+ struct i915_perf_group *g;
struct intel_gt *gt;
int ret;
@@ -3191,6 +3198,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
return -EINVAL;
}
gt = props->engine->gt;
+ g = props->engine->oa_group;
/*
* If the sysfs metrics/ directory wasn't registered for some
@@ -3221,7 +3229,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
* counter reports and marshal to the appropriate client
* we currently only allow exclusive access
*/
- if (gt->perf.exclusive_stream) {
+ if (g->exclusive_stream) {
drm_dbg(&stream->perf->i915->drm,
"OA unit already in use\n");
return -EBUSY;
@@ -3316,7 +3324,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
stream->ops = &i915_oa_stream_ops;
stream->engine->gt->perf.sseu = props->sseu;
- WRITE_ONCE(gt->perf.exclusive_stream, stream);
+ WRITE_ONCE(g->exclusive_stream, stream);
ret = i915_perf_stream_enable_sync(stream);
if (ret) {
@@ -3339,7 +3347,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
return 0;
err_enable:
- WRITE_ONCE(gt->perf.exclusive_stream, NULL);
+ WRITE_ONCE(g->exclusive_stream, NULL);
perf->ops.disable_metric_set(stream);
free_oa_buffer(stream);
@@ -3373,7 +3381,7 @@ void i915_oa_init_reg_state(const struct intel_context *ce,
return;
/* perf.exclusive_stream serialised by lrc_configure_all_contexts() */
- stream = READ_ONCE(engine->gt->perf.exclusive_stream);
+ stream = READ_ONCE(engine->oa_group->exclusive_stream);
if (stream && GRAPHICS_VER(stream->perf->i915) < 12)
gen8_update_reg_state_unlocked(ce, stream);
}
@@ -3965,6 +3973,13 @@ static int read_properties_unlocked(struct i915_perf *perf,
return -EINVAL;
}
+ if (!engine_supports_oa(props->engine)) {
+ drm_dbg(&perf->i915->drm,
+ "Engine not supported by OA %d:%d\n",
+ I915_ENGINE_CLASS_RENDER, 0);
+ return -EINVAL;
+ }
+
/* Considering that ID = 0 is reserved and assuming that we don't
* (currently) expect any configurations to ever specify duplicate
* values for a particular property ID then the last _PROP_MAX value is
@@ -4743,6 +4758,60 @@ static struct ctl_table oa_table[] = {
{}
};
+static u32 num_perf_groups_per_gt(struct intel_gt *gt)
+{
+ return 1;
+}
+
+static u32 __oa_engine_group(struct intel_engine_cs *engine)
+{
+ if (engine->class == RENDER_CLASS)
+ return PERF_GROUP_OAG;
+ else
+ return PERF_GROUP_INVALID;
+}
+
+static int oa_init_gt(struct intel_gt *gt)
+{
+ u32 num_groups = num_perf_groups_per_gt(gt);
+ struct intel_engine_cs *engine;
+ struct i915_perf_group *g;
+ intel_engine_mask_t tmp;
+
+ g = kcalloc(num_groups, sizeof(*g), GFP_KERNEL);
+ if (!g)
+ return -ENOMEM;
+
+ for_each_engine_masked(engine, gt, ALL_ENGINES, tmp) {
+ u32 index = __oa_engine_group(engine);
+
+ engine->oa_group = NULL;
+ if (index < num_groups) {
+ g[index].num_engines++;
+ engine->oa_group = &g[index];
+ }
+ }
+
+ gt->perf.num_perf_groups = num_groups;
+ gt->perf.group = g;
+
+ return 0;
+}
+
+static int oa_init_engine_groups(struct i915_perf *perf)
+{
+ struct intel_gt *gt;
+ int i, ret;
+
+ for_each_gt(gt, perf->i915, i) {
+ ret = oa_init_gt(gt);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static void oa_init_supported_formats(struct i915_perf *perf)
{
struct drm_i915_private *i915 = perf->i915;
@@ -4909,7 +4978,7 @@ void i915_perf_init(struct drm_i915_private *i915)
if (perf->ops.enable_metric_set) {
struct intel_gt *gt;
- int i;
+ int i, ret;
for_each_gt(gt, i915, i)
mutex_init(>->perf.lock);
@@ -4948,6 +5017,11 @@ void i915_perf_init(struct drm_i915_private *i915)
perf->i915 = i915;
+ ret = oa_init_engine_groups(perf);
+ if (ret)
+ drm_err(&i915->drm,
+ "OA initialization failed %d\n", ret);
+
oa_init_supported_formats(perf);
}
}
@@ -4976,10 +5050,15 @@ void i915_perf_sysctl_unregister(void)
void i915_perf_fini(struct drm_i915_private *i915)
{
struct i915_perf *perf = &i915->perf;
+ struct intel_gt *gt;
+ int i;
if (!perf->i915)
return;
+ for_each_gt(gt, perf->i915, i)
+ kfree(gt->perf.group);
+
idr_for_each(&perf->metrics_idr, destroy_config, perf);
idr_destroy(&perf->metrics_idr);
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h b/drivers/gpu/drm/i915/i915_perf_types.h
index 4d5d8c365d9e..e7c83dcbec08 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -17,6 +17,7 @@
#include <linux/wait.h>
#include <uapi/drm/i915_drm.h>
+#include "gt/intel_engine_types.h"
#include "gt/intel_sseu.h"
#include "i915_reg_defs.h"
#include "intel_wakeref.h"
@@ -30,6 +31,13 @@ struct i915_vma;
struct intel_context;
struct intel_engine_cs;
+enum {
+ PERF_GROUP_OAG = 0,
+
+ PERF_GROUP_MAX,
+ PERF_GROUP_INVALID = U32_MAX,
+};
+
struct i915_oa_format {
u32 format;
int size;
@@ -390,6 +398,20 @@ struct i915_oa_ops {
u32 (*oa_hw_tail_read)(struct i915_perf_stream *stream);
};
+struct i915_perf_group {
+ /*
+ * @exclusive_stream: The stream currently using the OA unit. This is
+ * sometimes accessed outside a syscall associated to its file
+ * descriptor.
+ */
+ struct i915_perf_stream *exclusive_stream;
+
+ /*
+ * @num_engines: The number of engines using this OA unit.
+ */
+ u32 num_engines;
+};
+
struct i915_perf_gt {
/*
* Lock associated with anything below within this structure.
@@ -402,12 +424,15 @@ struct i915_perf_gt {
*/
struct intel_sseu sseu;
+ /**
+ * @num_perf_groups: number of perf groups per gt.
+ */
+ u32 num_perf_groups;
+
/*
- * @exclusive_stream: The stream currently using the OA unit. This is
- * sometimes accessed outside a syscall associated to its file
- * descriptor.
+ * @group: list of OA groups - one for each OA buffer.
*/
- struct i915_perf_stream *exclusive_stream;
+ struct i915_perf_group *group;
};
struct i915_perf {
--
2.36.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Intel-gfx] [PATCH 05/11] drm/i915/perf: Fail modprobe if i915_perf_init fails on OOM
2023-03-23 22:58 [Intel-gfx] [PATCH 00/11] Add OAM support for MTL Umesh Nerlige Ramappa
` (3 preceding siblings ...)
2023-03-23 22:58 ` [Intel-gfx] [PATCH 04/11] drm/i915/perf: Group engines into respective OA groups Umesh Nerlige Ramappa
@ 2023-03-23 22:58 ` Umesh Nerlige Ramappa
2023-03-23 22:58 ` [Intel-gfx] [PATCH 06/11] drm/i915/perf: Parse 64bit report header formats correctly Umesh Nerlige Ramappa
` (8 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2023-03-23 22:58 UTC (permalink / raw)
To: intel-gfx
i915_perf_init can fail due to OOM. Fail driver init if i915_perf_init
fails.
v2: (Jani)
- Reorder patch in the series
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
drivers/gpu/drm/i915/i915_driver.c | 4 +++-
drivers/gpu/drm/i915/i915_perf.c | 8 ++++++--
drivers/gpu/drm/i915/i915_perf.h | 2 +-
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index da249337c23b..8dde3512d2d1 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -469,7 +469,9 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
if (ret)
return ret;
- i915_perf_init(dev_priv);
+ ret = i915_perf_init(dev_priv);
+ if (ret)
+ return ret;
ret = i915_ggtt_probe_hw(dev_priv);
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index cf4ea5e389a5..584e3e7b9e77 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4902,7 +4902,7 @@ static void i915_perf_init_info(struct drm_i915_private *i915)
* Note: i915-perf initialization is split into an 'init' and 'register'
* phase with the i915_perf_register() exposing state to userspace.
*/
-void i915_perf_init(struct drm_i915_private *i915)
+int i915_perf_init(struct drm_i915_private *i915)
{
struct i915_perf *perf = &i915->perf;
@@ -5018,12 +5018,16 @@ void i915_perf_init(struct drm_i915_private *i915)
perf->i915 = i915;
ret = oa_init_engine_groups(perf);
- if (ret)
+ if (ret) {
drm_err(&i915->drm,
"OA initialization failed %d\n", ret);
+ return ret;
+ }
oa_init_supported_formats(perf);
}
+
+ return 0;
}
static int destroy_config(int id, void *p, void *data)
diff --git a/drivers/gpu/drm/i915/i915_perf.h b/drivers/gpu/drm/i915/i915_perf.h
index f96e09a4af04..253637651d5e 100644
--- a/drivers/gpu/drm/i915/i915_perf.h
+++ b/drivers/gpu/drm/i915/i915_perf.h
@@ -18,7 +18,7 @@ struct i915_oa_config;
struct intel_context;
struct intel_engine_cs;
-void i915_perf_init(struct drm_i915_private *i915);
+int i915_perf_init(struct drm_i915_private *i915);
void i915_perf_fini(struct drm_i915_private *i915);
void i915_perf_register(struct drm_i915_private *i915);
void i915_perf_unregister(struct drm_i915_private *i915);
--
2.36.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Intel-gfx] [PATCH 06/11] drm/i915/perf: Parse 64bit report header formats correctly
2023-03-23 22:58 [Intel-gfx] [PATCH 00/11] Add OAM support for MTL Umesh Nerlige Ramappa
` (4 preceding siblings ...)
2023-03-23 22:58 ` [Intel-gfx] [PATCH 05/11] drm/i915/perf: Fail modprobe if i915_perf_init fails on OOM Umesh Nerlige Ramappa
@ 2023-03-23 22:58 ` Umesh Nerlige Ramappa
2023-03-23 22:58 ` [Intel-gfx] [PATCH 07/11] drm/i915/perf: Handle non-power-of-2 reports Umesh Nerlige Ramappa
` (7 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2023-03-23 22:58 UTC (permalink / raw)
To: intel-gfx
Now that OA formats come in flavor of 64 bit reports, the report header
has 64 bit report-id, timestamp, context-id and gpu-ticks fields. When
filtering these reports, use the right width for these fields.
Note that upper dword of context id is reserved, so squash lower dword
only.
v2: (Ashutosh)
- Drop inline
- Update comment with dword definitions - report id and timestamp
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 109 +++++++++++++++++++------
drivers/gpu/drm/i915/i915_perf_types.h | 6 ++
2 files changed, 90 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 584e3e7b9e77..d1f7266bec6d 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -441,6 +441,67 @@ static u32 gen7_oa_hw_tail_read(struct i915_perf_stream *stream)
return oastatus1 & GEN7_OASTATUS1_TAIL_MASK;
}
+#define oa_report_header_64bit(__s) \
+ ((__s)->oa_buffer.format->header == HDR_64_BIT)
+
+static u64 oa_report_id(struct i915_perf_stream *stream, void *report)
+{
+ return oa_report_header_64bit(stream) ? *(u64 *)report : *(u32 *)report;
+}
+
+static u64 oa_report_reason(struct i915_perf_stream *stream, void *report)
+{
+ return (oa_report_id(stream, report) >> OAREPORT_REASON_SHIFT) &
+ (GRAPHICS_VER(stream->perf->i915) == 12 ?
+ OAREPORT_REASON_MASK_EXTENDED :
+ OAREPORT_REASON_MASK);
+}
+
+static void oa_report_id_clear(struct i915_perf_stream *stream, u32 *report)
+{
+ if (oa_report_header_64bit(stream))
+ *(u64 *)report = 0;
+ else
+ *report = 0;
+}
+
+static bool oa_report_ctx_invalid(struct i915_perf_stream *stream, void *report)
+{
+ return !(oa_report_id(stream, report) &
+ stream->perf->gen8_valid_ctx_bit) &&
+ GRAPHICS_VER(stream->perf->i915) <= 11;
+}
+
+static u64 oa_timestamp(struct i915_perf_stream *stream, void *report)
+{
+ return oa_report_header_64bit(stream) ?
+ *((u64 *)report + 1) :
+ *((u32 *)report + 1);
+}
+
+static void oa_timestamp_clear(struct i915_perf_stream *stream, u32 *report)
+{
+ if (oa_report_header_64bit(stream))
+ *(u64 *)&report[2] = 0;
+ else
+ report[1] = 0;
+}
+
+static u32 oa_context_id(struct i915_perf_stream *stream, u32 *report)
+{
+ u32 ctx_id = oa_report_header_64bit(stream) ? report[4] : report[2];
+
+ return ctx_id & stream->specific_ctx_id_mask;
+}
+
+static void oa_context_id_squash(struct i915_perf_stream *stream, u32 *report)
+{
+ if (oa_report_header_64bit(stream))
+ report[4] = INVALID_CTX_ID;
+ else
+ report[2] = INVALID_CTX_ID;
+}
+
/**
* oa_buffer_check_unlocked - check for data and update tail ptr state
* @stream: i915 stream instance
@@ -509,21 +570,22 @@ static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream)
hw_tail -= gtt_offset;
tail = hw_tail;
- /* Walk the stream backward until we find a report with dword 0
- * & 1 not at 0. Since the circular buffer pointers progress by
- * increments of 64 bytes and that reports can be up to 256
- * bytes long, we can't tell whether a report has fully landed
- * in memory before the first 2 dwords of the following report
- * have effectively landed.
+ /* Walk the stream backward until we find a report with report
+ * id and timestmap not at 0. Since the circular buffer pointers
+ * progress by increments of 64 bytes and that reports can be up
+ * to 256 bytes long, we can't tell whether a report has fully
+ * landed in memory before the report id and timestamp of the
+ * following report have effectively landed.
*
* This is assuming that the writes of the OA unit land in
* memory in the order they were written to.
* If not : (╯°□°）╯︵ ┻━┻
*/
while (OA_TAKEN(tail, aged_tail) >= report_size) {
- u32 *report32 = (void *)(stream->oa_buffer.vaddr + tail);
+ void *report = stream->oa_buffer.vaddr + tail;
- if (report32[0] != 0 || report32[1] != 0)
+ if (oa_report_id(stream, report) ||
+ oa_timestamp(stream, report))
break;
tail = (tail - report_size) & (OA_BUFFER_SIZE - 1);
@@ -702,7 +764,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
u8 *report = oa_buf_base + head;
u32 *report32 = (void *)report;
u32 ctx_id;
- u32 reason;
+ u64 reason;
/*
* All the report sizes factor neatly into the buffer
@@ -725,16 +787,12 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
* triggered this specific report (mostly timer
* triggered or e.g. due to a context switch).
*
- * This field is never expected to be zero so we can
- * check that the report isn't invalid before copying
- * it to userspace...
+ * In MMIO triggered reports, some platforms do not set the
+ * reason bit in this field and it is valid to have a reason
+ * field of zero.
*/
- reason = ((report32[0] >> OAREPORT_REASON_SHIFT) &
- (GRAPHICS_VER(stream->perf->i915) == 12 ?
- OAREPORT_REASON_MASK_EXTENDED :
- OAREPORT_REASON_MASK));
-
- ctx_id = report32[2] & stream->specific_ctx_id_mask;
+ reason = oa_report_reason(stream, report);
+ ctx_id = oa_context_id(stream, report32);
/*
* Squash whatever is in the CTX_ID field if it's marked as
@@ -744,9 +802,10 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
* Note: that we don't clear the valid_ctx_bit so userspace can
* understand that the ID has been squashed by the kernel.
*/
- if (!(report32[0] & stream->perf->gen8_valid_ctx_bit) &&
- GRAPHICS_VER(stream->perf->i915) <= 11)
- ctx_id = report32[2] = INVALID_CTX_ID;
+ if (oa_report_ctx_invalid(stream, report)) {
+ ctx_id = INVALID_CTX_ID;
+ oa_context_id_squash(stream, report32);
+ }
/*
* NB: For Gen 8 the OA unit no longer supports clock gating
@@ -790,7 +849,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
*/
if (stream->ctx &&
stream->specific_ctx_id != ctx_id) {
- report32[2] = INVALID_CTX_ID;
+ oa_context_id_squash(stream, report32);
}
ret = append_oa_sample(stream, buf, count, offset,
@@ -802,11 +861,11 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
}
/*
- * Clear out the first 2 dword as a mean to detect unlanded
+ * Clear out the report id and timestamp as a means to detect unlanded
* reports.
*/
- report32[0] = 0;
- report32[1] = 0;
+ oa_report_id_clear(stream, report32);
+ oa_timestamp_clear(stream, report32);
}
if (start_offset != *offset) {
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h b/drivers/gpu/drm/i915/i915_perf_types.h
index e7c83dcbec08..d8b92508a632 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -38,9 +38,15 @@ enum {
PERF_GROUP_INVALID = U32_MAX,
};
+enum report_header {
+ HDR_32_BIT = 0,
+ HDR_64_BIT,
+};
+
struct i915_oa_format {
u32 format;
int size;
+ enum report_header header;
};
struct i915_oa_reg {
--
2.36.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Intel-gfx] [PATCH 07/11] drm/i915/perf: Handle non-power-of-2 reports
2023-03-23 22:58 [Intel-gfx] [PATCH 00/11] Add OAM support for MTL Umesh Nerlige Ramappa
` (5 preceding siblings ...)
2023-03-23 22:58 ` [Intel-gfx] [PATCH 06/11] drm/i915/perf: Parse 64bit report header formats correctly Umesh Nerlige Ramappa
@ 2023-03-23 22:58 ` Umesh Nerlige Ramappa
2023-03-23 22:58 ` [Intel-gfx] [PATCH 08/11] drm/i915/perf: Add engine class instance parameters to perf Umesh Nerlige Ramappa
` (6 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2023-03-23 22:58 UTC (permalink / raw)
To: intel-gfx
Some of the newer OA formats are not powers of 2. For those formats,
adjust the hw_tail accordingly when checking for new reports.
v2: (Ashutosh)
- Switch to OA_TAKEN for diff calculation
- Use OA_BUFFER_SIZE instead of the vma size
- Update comments
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 51 +++++++++++++++++---------------
1 file changed, 27 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index d1f7266bec6d..8c4bcdce8019 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -534,6 +534,7 @@ static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream)
bool pollin;
u32 hw_tail;
u64 now;
+ u32 partial_report_size;
/* We have to consider the (unlikely) possibility that read() errors
* could result in an OA buffer reset which might reset the head and
@@ -543,10 +544,15 @@ static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream)
hw_tail = stream->perf->ops.oa_hw_tail_read(stream);
- /* The tail pointer increases in 64 byte increments,
- * not in report_size steps...
+ /* The tail pointer increases in 64 byte increments, not in report_size
+ * steps. Also the report size may not be a power of 2. Compute
+ * potentially partially landed report in the OA buffer
*/
- hw_tail &= ~(report_size - 1);
+ partial_report_size = OA_TAKEN(hw_tail, stream->oa_buffer.tail);
+ partial_report_size %= report_size;
+
+ /* Subtract partial amount off the tail */
+ hw_tail = gtt_offset + OA_TAKEN(hw_tail, partial_report_size);
now = ktime_get_mono_fast_ns();
@@ -669,6 +675,8 @@ static int append_oa_sample(struct i915_perf_stream *stream,
{
int report_size = stream->oa_buffer.format->size;
struct drm_i915_perf_record_header header;
+ int report_size_partial;
+ u8 *oa_buf_end;
header.type = DRM_I915_PERF_RECORD_SAMPLE;
header.pad = 0;
@@ -682,8 +690,20 @@ static int append_oa_sample(struct i915_perf_stream *stream,
return -EFAULT;
buf += sizeof(header);
- if (copy_to_user(buf, report, report_size))
+ oa_buf_end = stream->oa_buffer.vaddr + OA_BUFFER_SIZE;
+ report_size_partial = oa_buf_end - report;
+
+ if (report_size_partial < report_size) {
+ if (copy_to_user(buf, report, report_size_partial))
+ return -EFAULT;
+ buf += report_size_partial;
+
+ if (copy_to_user(buf, stream->oa_buffer.vaddr,
+ report_size - report_size_partial))
+ return -EFAULT;
+ } else if (copy_to_user(buf, report, report_size)) {
return -EFAULT;
+ }
(*offset) += header.size;
@@ -747,12 +767,11 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
* An out of bounds or misaligned head or tail pointer implies a driver
* bug since we validate + align the tail pointers we read from the
* hardware and we are in full control of the head pointer which should
- * only be incremented by multiples of the report size (notably also
- * all a power of two).
+ * only be incremented by multiples of the report size.
*/
if (drm_WARN_ONCE(&uncore->i915->drm,
- head > OA_BUFFER_SIZE || head % report_size ||
- tail > OA_BUFFER_SIZE || tail % report_size,
+ head > OA_BUFFER_SIZE ||
+ tail > OA_BUFFER_SIZE,
"Inconsistent OA buffer pointers: head = %u, tail = %u\n",
head, tail))
return -EIO;
@@ -766,22 +785,6 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
u32 ctx_id;
u64 reason;
- /*
- * All the report sizes factor neatly into the buffer
- * size so we never expect to see a report split
- * between the beginning and end of the buffer.
- *
- * Given the initial alignment check a misalignment
- * here would imply a driver bug that would result
- * in an overrun.
- */
- if (drm_WARN_ON(&uncore->i915->drm,
- (OA_BUFFER_SIZE - head) < report_size)) {
- drm_err(&uncore->i915->drm,
- "Spurious OA head ptr: non-integral report offset\n");
- break;
- }
-
/*
* The reason field includes flags identifying what
* triggered this specific report (mostly timer
--
2.36.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Intel-gfx] [PATCH 08/11] drm/i915/perf: Add engine class instance parameters to perf
2023-03-23 22:58 [Intel-gfx] [PATCH 00/11] Add OAM support for MTL Umesh Nerlige Ramappa
` (6 preceding siblings ...)
2023-03-23 22:58 ` [Intel-gfx] [PATCH 07/11] drm/i915/perf: Handle non-power-of-2 reports Umesh Nerlige Ramappa
@ 2023-03-23 22:58 ` Umesh Nerlige Ramappa
2023-03-23 22:58 ` [Intel-gfx] [PATCH 09/11] drm/i915/perf: Add support for OA media units Umesh Nerlige Ramappa
` (5 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2023-03-23 22:58 UTC (permalink / raw)
To: intel-gfx
One or more engines map to a specific OA unit. All reports from these
engines are captured in the OA buffer managed by this OA unit.
Current i915 OA implementation supports only the OAG unit. OAG primarily
caters to render engine, so i915 OA uses render as the default engine
in the OA implementation. Since there are more OA units on newer
hardware that map to other engines, allow user to pass engine class and
instance to select and program specific OA units.
UMD specific changes for GPUvis support:
https://patchwork.freedesktop.org/patch/522827/?series=114023
https://patchwork.freedesktop.org/patch/522822/?series=114023
https://patchwork.freedesktop.org/patch/522826/?series=114023
https://patchwork.freedesktop.org/patch/522828/?series=114023
https://patchwork.freedesktop.org/patch/522816/?series=114023
https://patchwork.freedesktop.org/patch/522825/?series=114023
v2: (Ashutosh)
- Clarify commit message
- Add drm_dbg
- Clarify uapi description
v3: (Ashutosh)
- Remove irrelevant info from the uapi comment
v4: Ensure engine class:instance is passed together (Ashutosh)
v5: Remove unnecessary quote (Ashutosh)
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 71 ++++++++++++++++++++------------
include/uapi/drm/i915_drm.h | 19 +++++++++
2 files changed, 63 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 8c4bcdce8019..081d1dd743e0 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4012,48 +4012,32 @@ static int read_properties_unlocked(struct i915_perf *perf,
{
struct drm_i915_gem_context_param_sseu user_sseu;
u64 __user *uprop = uprops;
+ bool config_instance = false;
+ bool config_class = false;
bool config_sseu = false;
+ u8 class, instance;
u32 i;
int ret;
memset(props, 0, sizeof(struct perf_open_properties));
props->poll_oa_period = DEFAULT_POLL_PERIOD_NS;
- if (!n_props) {
- drm_dbg(&perf->i915->drm,
- "No i915 perf properties given\n");
- return -EINVAL;
- }
-
- /* At the moment we only support using i915-perf on the RCS. */
- props->engine = intel_engine_lookup_user(perf->i915,
- I915_ENGINE_CLASS_RENDER,
- 0);
- if (!props->engine) {
- drm_dbg(&perf->i915->drm,
- "No RENDER-capable engines\n");
- return -EINVAL;
- }
-
- if (!engine_supports_oa(props->engine)) {
- drm_dbg(&perf->i915->drm,
- "Engine not supported by OA %d:%d\n",
- I915_ENGINE_CLASS_RENDER, 0);
- return -EINVAL;
- }
-
/* Considering that ID = 0 is reserved and assuming that we don't
* (currently) expect any configurations to ever specify duplicate
* values for a particular property ID then the last _PROP_MAX value is
* one greater than the maximum number of properties we expect to get
* from userspace.
*/
- if (n_props >= DRM_I915_PERF_PROP_MAX) {
+ if (!n_props || n_props >= DRM_I915_PERF_PROP_MAX) {
drm_dbg(&perf->i915->drm,
- "More i915 perf properties specified than exist\n");
+ "Invalid number of i915 perf properties given\n");
return -EINVAL;
}
+ /* Defaults when class:instance is not passed */
+ class = I915_ENGINE_CLASS_RENDER;
+ instance = 0;
+
for (i = 0; i < n_props; i++) {
u64 oa_period, oa_freq_hz;
u64 id, value;
@@ -4174,7 +4158,15 @@ static int read_properties_unlocked(struct i915_perf *perf,
}
props->poll_oa_period = value;
break;
- case DRM_I915_PERF_PROP_MAX:
+ case DRM_I915_PERF_PROP_OA_ENGINE_CLASS:
+ class = (u8)value;
+ config_class = true;
+ break;
+ case DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE:
+ instance = (u8)value;
+ config_instance = true;
+ break;
+ default:
MISSING_CASE(id);
return -EINVAL;
}
@@ -4182,6 +4174,28 @@ static int read_properties_unlocked(struct i915_perf *perf,
uprop += 2;
}
+ if ((config_class && !config_instance) ||
+ (config_instance && !config_class)) {
+ drm_dbg(&perf->i915->drm,
+ "OA engine-class and engine-instance parameters must be passed together\n");
+ return -EINVAL;
+ }
+
+ props->engine = intel_engine_lookup_user(perf->i915, class, instance);
+ if (!props->engine) {
+ drm_dbg(&perf->i915->drm,
+ "OA engine class and instance invalid %d:%d\n",
+ class, instance);
+ return -EINVAL;
+ }
+
+ if (!engine_supports_oa(props->engine)) {
+ drm_dbg(&perf->i915->drm,
+ "Engine not supported by OA %d:%d\n",
+ class, instance);
+ return -EINVAL;
+ }
+
if (config_sseu) {
ret = get_sseu_config(&props->sseu, props->engine, &user_sseu);
if (ret) {
@@ -5158,8 +5172,11 @@ int i915_perf_ioctl_version(void)
*
* 5: Add DRM_I915_PERF_PROP_POLL_OA_PERIOD parameter that controls the
* interval for the hrtimer used to check for OA data.
+ *
+ * 6: Add DRM_I915_PERF_PROP_OA_ENGINE_CLASS and
+ * DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE
*/
- return 5;
+ return 6;
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 5e458d6f2895..384e74cac539 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2758,6 +2758,25 @@ enum drm_i915_perf_property_id {
*/
DRM_I915_PERF_PROP_POLL_OA_PERIOD,
+ /**
+ * Multiple engines may be mapped to the same OA unit. The OA unit is
+ * identified by class:instance of any engine mapped to it.
+ *
+ * This parameter specifies the engine class and must be passed along
+ * with DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE.
+ *
+ * This property is available in perf revision 6.
+ */
+ DRM_I915_PERF_PROP_OA_ENGINE_CLASS,
+
+ /**
+ * This parameter specifies the engine instance and must be passed along
+ * with DRM_I915_PERF_PROP_OA_ENGINE_CLASS.
+ *
+ * This property is available in perf revision 6.
+ */
+ DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE,
+
DRM_I915_PERF_PROP_MAX /* non-ABI */
};
--
2.36.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Intel-gfx] [PATCH 09/11] drm/i915/perf: Add support for OA media units
2023-03-23 22:58 [Intel-gfx] [PATCH 00/11] Add OAM support for MTL Umesh Nerlige Ramappa
` (7 preceding siblings ...)
2023-03-23 22:58 ` [Intel-gfx] [PATCH 08/11] drm/i915/perf: Add engine class instance parameters to perf Umesh Nerlige Ramappa
@ 2023-03-23 22:58 ` Umesh Nerlige Ramappa
2023-03-23 22:59 ` [Intel-gfx] [PATCH 10/11] drm/i915/perf: Pass i915 object to perf revision helper Umesh Nerlige Ramappa
` (4 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2023-03-23 22:58 UTC (permalink / raw)
To: intel-gfx
MTL introduces additional OA units dedicated to media use cases. Add
support for programming these OA units by passing the media engine class
and instance parameters.
UMD specific changes for GPUvis support:
https://patchwork.freedesktop.org/patch/522827/?series=114023
https://patchwork.freedesktop.org/patch/522822/?series=114023
https://patchwork.freedesktop.org/patch/522826/?series=114023
https://patchwork.freedesktop.org/patch/522828/?series=114023
https://patchwork.freedesktop.org/patch/522816/?series=114023
https://patchwork.freedesktop.org/patch/522825/?series=114023
v2: (Ashutosh)
- check for IP_VER(12, 70) instead of MTL
- remove PERF_GROUP_OAG comment in mtl_oa_base
- remove oa_buffer.group
- use engine->oa_group->type in engine_supports_oa_format
- remove fw_domains and use FORCEWAKE_ALL
- remove MPES/MPEC comment
- s/xehp/mtl/ in b counter validation function name
- remove engine_supports_oa in __oa_engine_group
- remove warn_ON from __oam_engine_group
- refactor oa_init_groups and oa_init_regs
- assign g->type correctly
- use enum oa_type definition
v3: (Ashutosh)
- Drop oa_unit_functional as engine_supports_oa is enough
v4:
- s/DRM_DEBUG/drm_dbg/
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_perf.c | 184 ++++++++++++++++++++---
drivers/gpu/drm/i915/i915_perf_oa_regs.h | 78 ++++++++++
drivers/gpu/drm/i915/i915_perf_types.h | 30 ++++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
include/uapi/drm/i915_drm.h | 4 +
7 files changed, 278 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6254aa977398..d81c35407d25 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -858,6 +858,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
(INTEL_INFO(dev_priv)->has_oa_bpc_reporting)
#define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \
(INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits)
+#define HAS_OAM(dev_priv) \
+ (INTEL_INFO(dev_priv)->has_oam)
/*
* Set this flag, when platform requires 64K GTT page sizes or larger for
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a8d942b16223..621730b6551c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1028,6 +1028,7 @@ static const struct intel_device_info adl_p_info = {
.has_mslice_steering = 1, \
.has_oa_bpc_reporting = 1, \
.has_oa_slice_contrib_limits = 1, \
+ .has_oam = 1, \
.has_rc6 = 1, \
.has_reset_engine = 1, \
.has_rps = 1, \
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 081d1dd743e0..247dad57ab89 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -192,6 +192,7 @@
*/
#include <linux/anon_inodes.h>
+#include <linux/nospec.h>
#include <linux/sizes.h>
#include <linux/uuid.h>
@@ -326,6 +327,12 @@ static const struct i915_oa_format oa_formats[I915_OA_FORMAT_MAX] = {
[I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
[I915_OAR_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
[I915_OA_FORMAT_A24u40_A14u32_B8_C8] = { 5, 256 },
+ [I915_OAM_FORMAT_MPEC8u64_B8_C8] = { 1, 192, TYPE_OAM, HDR_64_BIT },
+ [I915_OAM_FORMAT_MPEC8u32_B8_C8] = { 2, 128, TYPE_OAM, HDR_64_BIT },
+};
+
+static const u32 mtl_oa_base[] = {
+ [PERF_GROUP_OAM_SAMEDIA_0] = 0x393000,
};
#define SAMPLE_OA_REPORT (1<<0)
@@ -418,11 +425,17 @@ static void free_oa_config_bo(struct i915_oa_config_bo *oa_bo)
kfree(oa_bo);
}
+static inline const
+struct i915_perf_regs *__oa_regs(struct i915_perf_stream *stream)
+{
+ return &stream->engine->oa_group->regs;
+}
+
static u32 gen12_oa_hw_tail_read(struct i915_perf_stream *stream)
{
struct intel_uncore *uncore = stream->uncore;
- return intel_uncore_read(uncore, GEN12_OAG_OATAILPTR) &
+ return intel_uncore_read(uncore, __oa_regs(stream)->oa_tail_ptr) &
GEN12_OAG_OATAILPTR_MASK;
}
@@ -875,7 +888,8 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
i915_reg_t oaheadptr;
oaheadptr = GRAPHICS_VER(stream->perf->i915) == 12 ?
- GEN12_OAG_OAHEADPTR : GEN8_OAHEADPTR;
+ __oa_regs(stream)->oa_head_ptr :
+ GEN8_OAHEADPTR;
spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
@@ -928,7 +942,8 @@ static int gen8_oa_read(struct i915_perf_stream *stream,
return -EIO;
oastatus_reg = GRAPHICS_VER(stream->perf->i915) == 12 ?
- GEN12_OAG_OASTATUS : GEN8_OASTATUS;
+ __oa_regs(stream)->oa_status :
+ GEN8_OASTATUS;
oastatus = intel_uncore_read(uncore, oastatus_reg);
@@ -1637,6 +1652,11 @@ static bool engine_supports_oa(const struct intel_engine_cs *engine)
return engine->oa_group;
}
+static bool engine_supports_oa_format(struct intel_engine_cs *engine, int type)
+{
+ return engine->oa_group && engine->oa_group->type == type;
+}
+
static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
{
struct i915_perf *perf = stream->perf;
@@ -1788,8 +1808,8 @@ static void gen12_init_oa_buffer(struct i915_perf_stream *stream)
spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
- intel_uncore_write(uncore, GEN12_OAG_OASTATUS, 0);
- intel_uncore_write(uncore, GEN12_OAG_OAHEADPTR,
+ intel_uncore_write(uncore, __oa_regs(stream)->oa_status, 0);
+ intel_uncore_write(uncore, __oa_regs(stream)->oa_head_ptr,
gtt_offset & GEN12_OAG_OAHEADPTR_MASK);
stream->oa_buffer.head = gtt_offset;
@@ -1801,9 +1821,9 @@ static void gen12_init_oa_buffer(struct i915_perf_stream *stream)
* to enable proper functionality of the overflow
* bit."
*/
- intel_uncore_write(uncore, GEN12_OAG_OABUFFER, gtt_offset |
+ intel_uncore_write(uncore, __oa_regs(stream)->oa_buffer, gtt_offset |
OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);
- intel_uncore_write(uncore, GEN12_OAG_OATAILPTR,
+ intel_uncore_write(uncore, __oa_regs(stream)->oa_tail_ptr,
gtt_offset & GEN12_OAG_OATAILPTR_MASK);
/* Mark that we need updated tail pointers to read from... */
@@ -2563,7 +2583,8 @@ gen8_modify_self(struct intel_context *ce,
return err;
}
-static int gen8_configure_context(struct i915_gem_context *ctx,
+static int gen8_configure_context(struct i915_perf_stream *stream,
+ struct i915_gem_context *ctx,
struct flex *flex, unsigned int count)
{
struct i915_gem_engines_iter it;
@@ -2704,7 +2725,7 @@ oa_configure_all_contexts(struct i915_perf_stream *stream,
spin_unlock(&i915->gem.contexts.lock);
- err = gen8_configure_context(ctx, regs, num_regs);
+ err = gen8_configure_context(stream, ctx, regs, num_regs);
if (err) {
i915_gem_context_put(ctx);
return err;
@@ -2749,6 +2770,9 @@ gen12_configure_all_contexts(struct i915_perf_stream *stream,
},
};
+ if (stream->engine->class != RENDER_CLASS)
+ return 0;
+
return oa_configure_all_contexts(stream,
regs, ARRAY_SIZE(regs),
active);
@@ -2878,7 +2902,7 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
_MASKED_BIT_ENABLE(GEN12_DISABLE_DOP_GATING));
}
- intel_uncore_write(uncore, GEN12_OAG_OA_DEBUG,
+ intel_uncore_write(uncore, __oa_regs(stream)->oa_debug,
/* Disable clk ratio reports, like previous Gens. */
_MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO) |
@@ -2888,7 +2912,7 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
*/
oag_report_ctx_switches(stream));
- intel_uncore_write(uncore, GEN12_OAG_OAGLBCTXCTRL, periodic ?
+ intel_uncore_write(uncore, __oa_regs(stream)->oa_ctx_ctrl, periodic ?
(GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME |
GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE |
(period_exponent << GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT))
@@ -3042,8 +3066,8 @@ static void gen8_oa_enable(struct i915_perf_stream *stream)
static void gen12_oa_enable(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->uncore;
- u32 report_format = stream->oa_buffer.format->format;
+ const struct i915_perf_regs *regs;
+ u32 val;
/*
* If we don't want OA reports from the OA buffer, then we don't even
@@ -3054,9 +3078,11 @@ static void gen12_oa_enable(struct i915_perf_stream *stream)
gen12_init_oa_buffer(stream);
- intel_uncore_write(uncore, GEN12_OAG_OACONTROL,
- (report_format << GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT) |
- GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE);
+ regs = __oa_regs(stream);
+ val = (stream->oa_buffer.format->format << regs->oa_ctrl_counter_format_shift) |
+ GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE;
+
+ intel_uncore_write(stream->uncore, regs->oa_ctrl, val);
}
/**
@@ -3108,9 +3134,9 @@ static void gen12_oa_disable(struct i915_perf_stream *stream)
{
struct intel_uncore *uncore = stream->uncore;
- intel_uncore_write(uncore, GEN12_OAG_OACONTROL, 0);
+ intel_uncore_write(uncore, __oa_regs(stream)->oa_ctrl, 0);
if (intel_wait_for_register(uncore,
- GEN12_OAG_OACONTROL,
+ __oa_regs(stream)->oa_ctrl,
GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE, 0,
50))
drm_err(&stream->perf->i915->drm,
@@ -4011,6 +4037,7 @@ static int read_properties_unlocked(struct i915_perf *perf,
struct perf_open_properties *props)
{
struct drm_i915_gem_context_param_sseu user_sseu;
+ const struct i915_oa_format *f;
u64 __user *uprop = uprops;
bool config_instance = false;
bool config_class = false;
@@ -4196,6 +4223,15 @@ static int read_properties_unlocked(struct i915_perf *perf,
return -EINVAL;
}
+ i = array_index_nospec(props->oa_format, I915_OA_FORMAT_MAX);
+ f = &perf->oa_formats[i];
+ if (!engine_supports_oa_format(props->engine, f->type)) {
+ drm_dbg(&perf->i915->drm,
+ "Invalid OA format %d for class %d\n",
+ f->type, props->engine->class);
+ return -EINVAL;
+ }
+
if (config_sseu) {
ret = get_sseu_config(&props->sseu, props->engine, &user_sseu);
if (ret) {
@@ -4376,6 +4412,14 @@ static const struct i915_range gen12_oa_b_counters[] = {
{}
};
+static const struct i915_range mtl_oam_b_counters[] = {
+ { .start = 0x393000, .end = 0x39301c }, /* GEN12_OAM_STARTTRIG1[1-8] */
+ { .start = 0x393020, .end = 0x39303c }, /* GEN12_OAM_REPORTTRIG1[1-8] */
+ { .start = 0x393040, .end = 0x39307c }, /* GEN12_OAM_CEC[0-7][0-1] */
+ { .start = 0x393200, .end = 0x39323C }, /* MPES[0-7] */
+ {}
+};
+
static const struct i915_range xehp_oa_b_counters[] = {
{ .start = 0xdc48, .end = 0xdc48 }, /* OAA_ENABLE_REG */
{ .start = 0xdd00, .end = 0xdd48 }, /* OAG_LCE0_0 - OAA_LENABLE_REG */
@@ -4429,6 +4473,8 @@ static const struct i915_range mtl_oa_mux_regs[] = {
{ .start = 0x0d0c, .end = 0x0d2c }, /* NOA_CONFIG[0-8] */
{ .start = 0x9840, .end = 0x9840 }, /* GDT_CHICKEN_BITS */
{ .start = 0x9884, .end = 0x9888 }, /* NOA_WRITE */
+ { .start = 0x38d100, .end = 0x38d114}, /* VISACTL */
+ {}
};
static bool gen7_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
@@ -4466,10 +4512,20 @@ static bool gen12_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
return reg_in_range_table(addr, gen12_oa_b_counters);
}
+static bool mtl_is_valid_oam_b_counter_addr(struct i915_perf *perf, u32 addr)
+{
+ if (HAS_OAM(perf->i915) &&
+ GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 70))
+ return reg_in_range_table(addr, mtl_oam_b_counters);
+
+ return false;
+}
+
static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
{
return reg_in_range_table(addr, xehp_oa_b_counters) ||
- reg_in_range_table(addr, gen12_oa_b_counters);
+ reg_in_range_table(addr, gen12_oa_b_counters) ||
+ mtl_is_valid_oam_b_counter_addr(perf, addr);
}
static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
@@ -4839,12 +4895,86 @@ static u32 num_perf_groups_per_gt(struct intel_gt *gt)
return 1;
}
+static u32 __oam_engine_group(struct intel_engine_cs *engine)
+{
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70)) {
+ /*
+ * There's 1 SAMEDIA gt and 1 OAM per SAMEDIA gt. All media slices
+ * within the gt use the same OAM. All MTL SKUs list 1 SA MEDIA.
+ */
+ drm_WARN_ON(&engine->i915->drm,
+ engine->gt->type != GT_MEDIA);
+
+ return PERF_GROUP_OAM_SAMEDIA_0;
+ }
+
+ return PERF_GROUP_INVALID;
+}
+
static u32 __oa_engine_group(struct intel_engine_cs *engine)
{
- if (engine->class == RENDER_CLASS)
+ switch (engine->class) {
+ case RENDER_CLASS:
return PERF_GROUP_OAG;
- else
+
+ case VIDEO_DECODE_CLASS:
+ case VIDEO_ENHANCEMENT_CLASS:
+ return __oam_engine_group(engine);
+
+ default:
return PERF_GROUP_INVALID;
+ }
+}
+
+static struct i915_perf_regs __oam_regs(u32 base)
+{
+ return (struct i915_perf_regs) {
+ base,
+ GEN12_OAM_HEAD_POINTER(base),
+ GEN12_OAM_TAIL_POINTER(base),
+ GEN12_OAM_BUFFER(base),
+ GEN12_OAM_CONTEXT_CONTROL(base),
+ GEN12_OAM_CONTROL(base),
+ GEN12_OAM_DEBUG(base),
+ GEN12_OAM_STATUS(base),
+ GEN12_OAM_CONTROL_COUNTER_FORMAT_SHIFT,
+ };
+}
+
+static struct i915_perf_regs __oag_regs(void)
+{
+ return (struct i915_perf_regs) {
+ 0,
+ GEN12_OAG_OAHEADPTR,
+ GEN12_OAG_OATAILPTR,
+ GEN12_OAG_OABUFFER,
+ GEN12_OAG_OAGLBCTXCTRL,
+ GEN12_OAG_OACONTROL,
+ GEN12_OAG_OA_DEBUG,
+ GEN12_OAG_OASTATUS,
+ GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT,
+ };
+}
+
+static void oa_init_groups(struct intel_gt *gt)
+{
+ int i, num_groups = gt->perf.num_perf_groups;
+
+ for (i = 0; i < num_groups; i++) {
+ struct i915_perf_group *g = >->perf.group[i];
+
+ /* Fused off engines can result in a group with num_engines == 0 */
+ if (g->num_engines == 0)
+ continue;
+
+ if (i == PERF_GROUP_OAG && gt->type != GT_MEDIA) {
+ g->regs = __oag_regs();
+ g->type = TYPE_OAG;
+ } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) {
+ g->regs = __oam_regs(mtl_oa_base[i]);
+ g->type = TYPE_OAM;
+ }
+ }
}
static int oa_init_gt(struct intel_gt *gt)
@@ -4871,6 +5001,8 @@ static int oa_init_gt(struct intel_gt *gt)
gt->perf.num_perf_groups = num_groups;
gt->perf.group = g;
+ oa_init_groups(gt);
+
return 0;
}
@@ -4928,9 +5060,15 @@ static void oa_init_supported_formats(struct i915_perf *perf)
break;
case INTEL_DG2:
+ oa_format_add(perf, I915_OAR_FORMAT_A32u40_A4u32_B8_C8);
+ oa_format_add(perf, I915_OA_FORMAT_A24u40_A14u32_B8_C8);
+ break;
+
case INTEL_METEORLAKE:
oa_format_add(perf, I915_OAR_FORMAT_A32u40_A4u32_B8_C8);
oa_format_add(perf, I915_OA_FORMAT_A24u40_A14u32_B8_C8);
+ oa_format_add(perf, I915_OAM_FORMAT_MPEC8u64_B8_C8);
+ oa_format_add(perf, I915_OAM_FORMAT_MPEC8u32_B8_C8);
break;
default:
@@ -5175,8 +5313,10 @@ int i915_perf_ioctl_version(void)
*
* 6: Add DRM_I915_PERF_PROP_OA_ENGINE_CLASS and
* DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE
+ *
+ * 7: Add support for video decode and enhancement classes.
*/
- return 6;
+ return 7;
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/i915_perf_oa_regs.h b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
index 381d94101610..ba103875e19f 100644
--- a/drivers/gpu/drm/i915/i915_perf_oa_regs.h
+++ b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
@@ -138,4 +138,82 @@
#define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
#define GEN12_SQCNT1_OABPC REG_BIT(29)
+/* Gen12 OAM unit */
+#define GEN12_OAM_HEAD_POINTER_OFFSET (0x1a0)
+#define GEN12_OAM_HEAD_POINTER_MASK 0xffffffc0
+
+#define GEN12_OAM_TAIL_POINTER_OFFSET (0x1a4)
+#define GEN12_OAM_TAIL_POINTER_MASK 0xffffffc0
+
+#define GEN12_OAM_BUFFER_OFFSET (0x1a8)
+#define GEN12_OAM_BUFFER_SIZE_MASK (0x7)
+#define GEN12_OAM_BUFFER_SIZE_SHIFT (3)
+#define GEN12_OAM_BUFFER_MEMORY_SELECT REG_BIT(0) /* 0: PPGTT, 1: GGTT */
+
+#define GEN12_OAM_CONTEXT_CONTROL_OFFSET (0x1bc)
+#define GEN12_OAM_CONTEXT_CONTROL_TIMER_PERIOD_SHIFT 2
+#define GEN12_OAM_CONTEXT_CONTROL_TIMER_ENABLE REG_BIT(1)
+#define GEN12_OAM_CONTEXT_CONTROL_COUNTER_RESUME REG_BIT(0)
+
+#define GEN12_OAM_CONTROL_OFFSET (0x194)
+#define GEN12_OAM_CONTROL_COUNTER_FORMAT_SHIFT 1
+#define GEN12_OAM_CONTROL_COUNTER_ENABLE REG_BIT(0)
+
+#define GEN12_OAM_DEBUG_OFFSET (0x198)
+#define GEN12_OAM_DEBUG_BUFFER_SIZE_SELECT REG_BIT(12)
+#define GEN12_OAM_DEBUG_INCLUDE_CLK_RATIO REG_BIT(6)
+#define GEN12_OAM_DEBUG_DISABLE_CLK_RATIO_REPORTS REG_BIT(5)
+#define GEN12_OAM_DEBUG_DISABLE_GO_1_0_REPORTS REG_BIT(2)
+#define GEN12_OAM_DEBUG_DISABLE_CTX_SWITCH_REPORTS REG_BIT(1)
+
+#define GEN12_OAM_STATUS_OFFSET (0x19c)
+#define GEN12_OAM_STATUS_COUNTER_OVERFLOW REG_BIT(2)
+#define GEN12_OAM_STATUS_BUFFER_OVERFLOW REG_BIT(1)
+#define GEN12_OAM_STATUS_REPORT_LOST REG_BIT(0)
+
+#define GEN12_OAM_MMIO_TRG_OFFSET (0x1d0)
+
+#define GEN12_OAM_MMIO_TRG(base) \
+ _MMIO((base) + GEN12_OAM_MMIO_TRG_OFFSET)
+
+#define GEN12_OAM_HEAD_POINTER(base) \
+ _MMIO((base) + GEN12_OAM_HEAD_POINTER_OFFSET)
+#define GEN12_OAM_TAIL_POINTER(base) \
+ _MMIO((base) + GEN12_OAM_TAIL_POINTER_OFFSET)
+#define GEN12_OAM_BUFFER(base) \
+ _MMIO((base) + GEN12_OAM_BUFFER_OFFSET)
+#define GEN12_OAM_CONTEXT_CONTROL(base) \
+ _MMIO((base) + GEN12_OAM_CONTEXT_CONTROL_OFFSET)
+#define GEN12_OAM_CONTROL(base) \
+ _MMIO((base) + GEN12_OAM_CONTROL_OFFSET)
+#define GEN12_OAM_DEBUG(base) \
+ _MMIO((base) + GEN12_OAM_DEBUG_OFFSET)
+#define GEN12_OAM_STATUS(base) \
+ _MMIO((base) + GEN12_OAM_STATUS_OFFSET)
+
+#define GEN12_OAM_CEC0_0_OFFSET (0x40)
+#define GEN12_OAM_CEC7_1_OFFSET (0x7c)
+#define GEN12_OAM_CEC0_0(base) \
+ _MMIO((base) + GEN12_OAM_CEC0_0_OFFSET)
+#define GEN12_OAM_CEC7_1(base) \
+ _MMIO((base) + GEN12_OAM_CEC7_1_OFFSET)
+
+#define GEN12_OAM_STARTTRIG1_OFFSET (0x00)
+#define GEN12_OAM_STARTTRIG8_OFFSET (0x1c)
+#define GEN12_OAM_STARTTRIG1(base) \
+ _MMIO((base) + GEN12_OAM_STARTTRIG1_OFFSET)
+#define GEN12_OAM_STARTTRIG8(base) \
+ _MMIO((base) + GEN12_OAM_STARTTRIG8_OFFSET)
+
+#define GEN12_OAM_REPORTTRIG1_OFFSET (0x20)
+#define GEN12_OAM_REPORTTRIG8_OFFSET (0x3c)
+#define GEN12_OAM_REPORTTRIG1(base) \
+ _MMIO((base) + GEN12_OAM_REPORTTRIG1_OFFSET)
+#define GEN12_OAM_REPORTTRIG8(base) \
+ _MMIO((base) + GEN12_OAM_REPORTTRIG8_OFFSET)
+
+#define GEN12_OAM_PERF_COUNTER_B0_OFFSET (0x84)
+#define GEN12_OAM_PERF_COUNTER_B(base, idx) \
+ _MMIO((base) + GEN12_OAM_PERF_COUNTER_B0_OFFSET + 4 * (idx))
+
#endif /* __INTEL_PERF_OA_REGS__ */
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h b/drivers/gpu/drm/i915/i915_perf_types.h
index d8b92508a632..66dd5f74de05 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -20,6 +20,7 @@
#include "gt/intel_engine_types.h"
#include "gt/intel_sseu.h"
#include "i915_reg_defs.h"
+#include "intel_uncore.h"
#include "intel_wakeref.h"
struct drm_i915_private;
@@ -33,6 +34,7 @@ struct intel_engine_cs;
enum {
PERF_GROUP_OAG = 0,
+ PERF_GROUP_OAM_SAMEDIA_0 = 0,
PERF_GROUP_MAX,
PERF_GROUP_INVALID = U32_MAX,
@@ -43,9 +45,27 @@ enum report_header {
HDR_64_BIT,
};
+struct i915_perf_regs {
+ u32 base;
+ i915_reg_t oa_head_ptr;
+ i915_reg_t oa_tail_ptr;
+ i915_reg_t oa_buffer;
+ i915_reg_t oa_ctx_ctrl;
+ i915_reg_t oa_ctrl;
+ i915_reg_t oa_debug;
+ i915_reg_t oa_status;
+ u32 oa_ctrl_counter_format_shift;
+};
+
+enum oa_type {
+ TYPE_OAG,
+ TYPE_OAM,
+};
+
struct i915_oa_format {
u32 format;
int size;
+ int type;
enum report_header header;
};
@@ -416,6 +436,16 @@ struct i915_perf_group {
* @num_engines: The number of engines using this OA unit.
*/
u32 num_engines;
+
+ /*
+ * @regs: OA buffer register group for programming the OA unit.
+ */
+ struct i915_perf_regs regs;
+
+ /*
+ * @type: Type of OA unit - OAM, OAG etc.
+ */
+ enum oa_type type;
};
struct i915_perf_gt {
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index b30cc8b97c3a..0aad8e48d27d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -167,6 +167,7 @@ enum intel_ppgtt_type {
func(has_mslice_steering); \
func(has_oa_bpc_reporting); \
func(has_oa_slice_contrib_limits); \
+ func(has_oam); \
func(has_one_eu_per_fuse_bit); \
func(has_pxp); \
func(has_rc6); \
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 384e74cac539..dba7c5a5b25e 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2676,6 +2676,10 @@ enum drm_i915_oa_format {
I915_OAR_FORMAT_A32u40_A4u32_B8_C8,
I915_OA_FORMAT_A24u40_A14u32_B8_C8,
+ /* MTL OAM */
+ I915_OAM_FORMAT_MPEC8u64_B8_C8,
+ I915_OAM_FORMAT_MPEC8u32_B8_C8,
+
I915_OA_FORMAT_MAX /* non-ABI */
};
--
2.36.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Intel-gfx] [PATCH 10/11] drm/i915/perf: Pass i915 object to perf revision helper
2023-03-23 22:58 [Intel-gfx] [PATCH 00/11] Add OAM support for MTL Umesh Nerlige Ramappa
` (8 preceding siblings ...)
2023-03-23 22:58 ` [Intel-gfx] [PATCH 09/11] drm/i915/perf: Add support for OA media units Umesh Nerlige Ramappa
@ 2023-03-23 22:59 ` Umesh Nerlige Ramappa
2023-03-23 22:59 ` [Intel-gfx] [PATCH 11/11] drm/i915/perf: Wa_14017512683: Disable OAM if media C6 is enabled in BIOS Umesh Nerlige Ramappa
` (3 subsequent siblings)
13 siblings, 0 replies; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2023-03-23 22:59 UTC (permalink / raw)
To: intel-gfx
In some cases, perf revision may rely on specific steppings of a
platform. To determine the platform, pass i915 object to the perf
revision helper.
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
drivers/gpu/drm/i915/i915_getparam.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 2 +-
drivers/gpu/drm/i915/i915_perf.h | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index 61ef2d9cfa62..2238e096c957 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -173,7 +173,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = INTEL_INFO(i915)->has_coherent_ggtt;
break;
case I915_PARAM_PERF_REVISION:
- value = i915_perf_ioctl_version();
+ value = i915_perf_ioctl_version(i915);
break;
case I915_PARAM_OA_TIMESTAMP_FREQUENCY:
value = i915_perf_oa_timestamp_frequency(i915);
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 247dad57ab89..18afa76653b7 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -5289,7 +5289,7 @@ void i915_perf_fini(struct drm_i915_private *i915)
*
* This version number is used by userspace to detect available features.
*/
-int i915_perf_ioctl_version(void)
+int i915_perf_ioctl_version(struct drm_i915_private *i915)
{
/*
* 1: Initial version
diff --git a/drivers/gpu/drm/i915/i915_perf.h b/drivers/gpu/drm/i915/i915_perf.h
index 253637651d5e..accf626f2b13 100644
--- a/drivers/gpu/drm/i915/i915_perf.h
+++ b/drivers/gpu/drm/i915/i915_perf.h
@@ -22,7 +22,7 @@ int i915_perf_init(struct drm_i915_private *i915);
void i915_perf_fini(struct drm_i915_private *i915);
void i915_perf_register(struct drm_i915_private *i915);
void i915_perf_unregister(struct drm_i915_private *i915);
-int i915_perf_ioctl_version(void);
+int i915_perf_ioctl_version(struct drm_i915_private *i915);
int i915_perf_sysctl_register(void);
void i915_perf_sysctl_unregister(void);
--
2.36.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [Intel-gfx] [PATCH 11/11] drm/i915/perf: Wa_14017512683: Disable OAM if media C6 is enabled in BIOS
2023-03-23 22:58 [Intel-gfx] [PATCH 00/11] Add OAM support for MTL Umesh Nerlige Ramappa
` (9 preceding siblings ...)
2023-03-23 22:59 ` [Intel-gfx] [PATCH 10/11] drm/i915/perf: Pass i915 object to perf revision helper Umesh Nerlige Ramappa
@ 2023-03-23 22:59 ` Umesh Nerlige Ramappa
2023-07-18 19:49 ` Matt Roper
2023-03-24 1:27 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add OAM support for MTL Patchwork
` (2 subsequent siblings)
13 siblings, 1 reply; 21+ messages in thread
From: Umesh Nerlige Ramappa @ 2023-03-23 22:59 UTC (permalink / raw)
To: intel-gfx
OAM does not work with media C6 enabled on some steppings of MTL.
Disable OAM if we detect that media C6 was enabled in bios.
v2: (Ashutosh)
- Remove drm_notice from the driver load path
- Log a drm_err when opening an OAM stream on affected steppings
v3:
- Initialize the engine group even if mc6 is enabled (Ashutosh)
- Checkpatch fix
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 18afa76653b7..c035dbb84c9b 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -209,6 +209,7 @@
#include "gt/intel_gt_regs.h"
#include "gt/intel_lrc.h"
#include "gt/intel_lrc_reg.h"
+#include "gt/intel_rc6.h"
#include "gt/intel_ring.h"
#include "gt/uc/intel_guc_slpc.h"
@@ -4223,6 +4224,19 @@ static int read_properties_unlocked(struct i915_perf *perf,
return -EINVAL;
}
+ /*
+ * Wa_14017512683: mtl[a0..c0): Use of OAM must be preceded with Media
+ * C6 disable in BIOS. Fail if Media C6 is enabled on steppings where OAM
+ * does not work as expected.
+ */
+ if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
+ props->engine->oa_group->type == TYPE_OAM &&
+ intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
+ drm_dbg(&perf->i915->drm,
+ "OAM requires media C6 to be disabled in BIOS\n");
+ return -EINVAL;
+ }
+
i = array_index_nospec(props->oa_format, I915_OA_FORMAT_MAX);
f = &perf->oa_formats[i];
if (!engine_supports_oa_format(props->engine, f->type)) {
@@ -5316,6 +5330,23 @@ int i915_perf_ioctl_version(struct drm_i915_private *i915)
*
* 7: Add support for video decode and enhancement classes.
*/
+
+ /*
+ * Wa_14017512683: mtl[a0..c0): Use of OAM must be preceded with Media
+ * C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
+ * to indicate that OA media is not supported.
+ */
+ if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
+ struct intel_gt *gt;
+ int i;
+
+ for_each_gt(gt, i915, i) {
+ if (gt->type == GT_MEDIA &&
+ intel_check_bios_c6_setup(>->rc6))
+ return 6;
+ }
+ }
+
return 7;
}
--
2.36.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [Intel-gfx] [PATCH 11/11] drm/i915/perf: Wa_14017512683: Disable OAM if media C6 is enabled in BIOS
2023-03-23 22:59 ` [Intel-gfx] [PATCH 11/11] drm/i915/perf: Wa_14017512683: Disable OAM if media C6 is enabled in BIOS Umesh Nerlige Ramappa
@ 2023-07-18 19:49 ` Matt Roper
2023-07-19 0:20 ` Dixit, Ashutosh
0 siblings, 1 reply; 21+ messages in thread
From: Matt Roper @ 2023-07-18 19:49 UTC (permalink / raw)
To: Umesh Nerlige Ramappa; +Cc: intel-gfx
On Thu, Mar 23, 2023 at 03:59:01PM -0700, Umesh Nerlige Ramappa wrote:
> OAM does not work with media C6 enabled on some steppings of MTL.
I just stumbled across this while looking at something else, but
14017512683 isn't a valid workaround number; that's just a per-platform
identifier associated with Wa_18023884638. The actual Wa_18023884638
applies not only to MTL, but also to DG2 which it looks like we're not
handling below.
Matt
> Disable OAM if we detect that media C6 was enabled in bios.
>
> v2: (Ashutosh)
> - Remove drm_notice from the driver load path
> - Log a drm_err when opening an OAM stream on affected steppings
>
> v3:
> - Initialize the engine group even if mc6 is enabled (Ashutosh)
> - Checkpatch fix
>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> ---
> drivers/gpu/drm/i915/i915_perf.c | 31 +++++++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 18afa76653b7..c035dbb84c9b 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -209,6 +209,7 @@
> #include "gt/intel_gt_regs.h"
> #include "gt/intel_lrc.h"
> #include "gt/intel_lrc_reg.h"
> +#include "gt/intel_rc6.h"
> #include "gt/intel_ring.h"
> #include "gt/uc/intel_guc_slpc.h"
>
> @@ -4223,6 +4224,19 @@ static int read_properties_unlocked(struct i915_perf *perf,
> return -EINVAL;
> }
>
> + /*
> + * Wa_14017512683: mtl[a0..c0): Use of OAM must be preceded with Media
> + * C6 disable in BIOS. Fail if Media C6 is enabled on steppings where OAM
> + * does not work as expected.
> + */
> + if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
> + props->engine->oa_group->type == TYPE_OAM &&
> + intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
> + drm_dbg(&perf->i915->drm,
> + "OAM requires media C6 to be disabled in BIOS\n");
> + return -EINVAL;
> + }
> +
> i = array_index_nospec(props->oa_format, I915_OA_FORMAT_MAX);
> f = &perf->oa_formats[i];
> if (!engine_supports_oa_format(props->engine, f->type)) {
> @@ -5316,6 +5330,23 @@ int i915_perf_ioctl_version(struct drm_i915_private *i915)
> *
> * 7: Add support for video decode and enhancement classes.
> */
> +
> + /*
> + * Wa_14017512683: mtl[a0..c0): Use of OAM must be preceded with Media
> + * C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
> + * to indicate that OA media is not supported.
> + */
> + if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
> + struct intel_gt *gt;
> + int i;
> +
> + for_each_gt(gt, i915, i) {
> + if (gt->type == GT_MEDIA &&
> + intel_check_bios_c6_setup(>->rc6))
> + return 6;
> + }
> + }
> +
> return 7;
> }
>
> --
> 2.36.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [Intel-gfx] [PATCH 11/11] drm/i915/perf: Wa_14017512683: Disable OAM if media C6 is enabled in BIOS
2023-07-18 19:49 ` Matt Roper
@ 2023-07-19 0:20 ` Dixit, Ashutosh
0 siblings, 0 replies; 21+ messages in thread
From: Dixit, Ashutosh @ 2023-07-19 0:20 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Tue, 18 Jul 2023 12:49:47 -0700, Matt Roper wrote:
>
Hi Matt,
> On Thu, Mar 23, 2023 at 03:59:01PM -0700, Umesh Nerlige Ramappa wrote:
> > OAM does not work with media C6 enabled on some steppings of MTL.
>
> I just stumbled across this while looking at something else, but
> 14017512683 isn't a valid workaround number; that's just a per-platform
> identifier associated with Wa_18023884638. The actual Wa_18023884638
> applies not only to MTL, but also to DG2 which it looks like we're not
> handling below.
Thanks for letting us know about this. You're right, all our (our team's)
WA numbers are a complete horror show, we'll need to do something about it.
Ashutosh
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add OAM support for MTL
2023-03-23 22:58 [Intel-gfx] [PATCH 00/11] Add OAM support for MTL Umesh Nerlige Ramappa
` (10 preceding siblings ...)
2023-03-23 22:59 ` [Intel-gfx] [PATCH 11/11] drm/i915/perf: Wa_14017512683: Disable OAM if media C6 is enabled in BIOS Umesh Nerlige Ramappa
@ 2023-03-24 1:27 ` Patchwork
2023-03-24 1:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-24 8:16 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
13 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2023-03-24 1:27 UTC (permalink / raw)
To: Umesh Nerlige Ramappa; +Cc: intel-gfx
== Series Details ==
Series: Add OAM support for MTL
URL : https://patchwork.freedesktop.org/series/115570/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 21+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for Add OAM support for MTL
2023-03-23 22:58 [Intel-gfx] [PATCH 00/11] Add OAM support for MTL Umesh Nerlige Ramappa
` (11 preceding siblings ...)
2023-03-24 1:27 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add OAM support for MTL Patchwork
@ 2023-03-24 1:36 ` Patchwork
2023-03-24 8:16 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
13 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2023-03-24 1:36 UTC (permalink / raw)
To: Umesh Nerlige Ramappa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4732 bytes --]
== Series Details ==
Series: Add OAM support for MTL
URL : https://patchwork.freedesktop.org/series/115570/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12907 -> Patchwork_115570v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/index.html
Participating hosts (38 -> 36)
------------------------------
Missing (2): fi-kbl-soraka fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_115570v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@mman:
- bat-rpls-1: [PASS][1] -> [TIMEOUT][2] ([i915#6794])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/bat-rpls-1/igt@i915_selftest@live@mman.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/bat-rpls-1/igt@i915_selftest@live@mman.html
* igt@i915_selftest@live@reset:
- bat-rpls-2: NOTRUN -> [ABORT][3] ([i915#4983] / [i915#7913])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/bat-rpls-2/igt@i915_selftest@live@reset.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-rpls-1: NOTRUN -> [SKIP][4] ([i915#7828])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/bat-rpls-1/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-rpls-1: NOTRUN -> [SKIP][5] ([i915#1845])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/bat-rpls-1/igt@kms_pipe_crc_basic@suspend-read-crc.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3@smem:
- bat-rpls-1: [ABORT][6] ([i915#6687] / [i915#7978]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_pm_rps@basic-api:
- bat-dg2-11: [FAIL][8] ([i915#8308]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/bat-dg2-11/igt@i915_pm_rps@basic-api.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/bat-dg2-11/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@requests:
- bat-rpls-2: [ABORT][10] ([i915#7913] / [i915#7982]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/bat-rpls-2/igt@i915_selftest@live@requests.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/bat-rpls-2/igt@i915_selftest@live@requests.html
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#7982]: https://gitlab.freedesktop.org/drm/intel/issues/7982
[i915#8308]: https://gitlab.freedesktop.org/drm/intel/issues/8308
Build changes
-------------
* IGT: IGT_7215 -> IGTPW_8672
* Linux: CI_DRM_12907 -> Patchwork_115570v1
CI-20190529: 20190529
CI_DRM_12907: 3e6be7c63e438996c88d6ba51a7d3025c56086d0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_8672: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8672/index.html
IGT_7215: 78703333d5852a9d5790ca249b313f792fb24cf2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_115570v1: 3e6be7c63e438996c88d6ba51a7d3025c56086d0 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
019f2d76520f drm/i915/perf: Wa_14017512683: Disable OAM if media C6 is enabled in BIOS
04b4ee0c0db7 drm/i915/perf: Pass i915 object to perf revision helper
e859760c6e49 drm/i915/perf: Add support for OA media units
1081d67b1c46 drm/i915/perf: Add engine class instance parameters to perf
a05725718a56 drm/i915/perf: Handle non-power-of-2 reports
e543ef010ac3 drm/i915/perf: Parse 64bit report header formats correctly
fb5da6783a0b drm/i915/perf: Fail modprobe if i915_perf_init fails on OOM
fac1d0e86c90 drm/i915/perf: Group engines into respective OA groups
b8e49dbf8eae drm/i915/perf: Validate OA sseu config outside switch
f304ee83ce5b drm/i915/mtl: Synchronize i915/BIOS on C6 enabling
f00b434ef766 drm/i915/perf: Drop wakeref on GuC RC error
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/index.html
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^ permalink raw reply [flat|nested] 21+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for Add OAM support for MTL
2023-03-23 22:58 [Intel-gfx] [PATCH 00/11] Add OAM support for MTL Umesh Nerlige Ramappa
` (12 preceding siblings ...)
2023-03-24 1:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-03-24 8:16 ` Patchwork
13 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2023-03-24 8:16 UTC (permalink / raw)
To: Umesh Nerlige Ramappa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 27540 bytes --]
== Series Details ==
Series: Add OAM support for MTL
URL : https://patchwork.freedesktop.org/series/115570/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12907_full -> Patchwork_115570v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (8 -> 8)
------------------------------
No changes in participating hosts
New tests
---------
New tests have been introduced between CI_DRM_12907_full and Patchwork_115570v1_full:
### New IGT tests (17) ###
* igt@perf@blocking@0-rcs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@perf@buffer-fill@0-rcs0:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@perf@enable-disable@0-rcs0:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@perf@gen12-group-concurrent-oa-buffer-read:
- Statuses : 4 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@perf@gen12-group-exclusive-stream-ctx-handle:
- Statuses : 3 pass(s) 2 skip(s)
- Exec time: [0.0] s
* igt@perf@gen12-group-exclusive-stream-sample-oa:
- Statuses : 3 pass(s) 3 skip(s)
- Exec time: [0.0] s
* igt@perf@gen12-invalid-class-instance:
- Statuses : 4 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@perf@gen12-mi-rpc@rcs0:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@perf@gen12-oa-tlb-invalidate@0-rcs0:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@perf@gen12-unprivileged-single-ctx-counters@rcs0:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@perf@global-sseu-config-invalid@0-rcs0:
- Statuses : 5 pass(s)
- Exec time: [0.0] s
* igt@perf@global-sseu-config@0-rcs0:
- Statuses : 5 pass(s)
- Exec time: [0.0] s
* igt@perf@non-zero-reason@0-rcs0:
- Statuses : 5 pass(s)
- Exec time: [0.0] s
* igt@perf@oa-exponents@0-rcs0:
- Statuses : 5 pass(s)
- Exec time: [0.0] s
* igt@perf@oa-formats@0-rcs0:
- Statuses : 5 pass(s)
- Exec time: [0.0] s
* igt@perf@polling@0-rcs0:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@perf@stress-open-close@0-rcs0:
- Statuses : 5 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_115570v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][1] -> [FAIL][2] ([i915#2846])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-glk4/igt@gem_exec_fair@basic-deadline.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-glk7/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842]) +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [PASS][5] -> [FAIL][6] ([i915#2842])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-apl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-apl4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-apl: [PASS][7] -> [DMESG-FAIL][8] ([i915#5334])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-apl1/igt@i915_selftest@live@gt_heartbeat.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-apl6/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_ccs@pipe-a-bad-pixel-format-4_tiled_dg2_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][9] ([fdo#109271]) +50 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-apl2/igt@kms_ccs@pipe-a-bad-pixel-format-4_tiled_dg2_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#3886]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-apl1/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_cursor_crc@cursor-rapid-movement-256x85:
- shard-snb: NOTRUN -> [SKIP][11] ([fdo#109271]) +59 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-snb2/igt@kms_cursor_crc@cursor-rapid-movement-256x85.html
* igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1:
- shard-apl: [PASS][12] -> [ABORT][13] ([i915#180])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-apl6/igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-apl1/igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-glk1/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_flip@2x-plain-flip-ts-check@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][15] -> [FAIL][16] ([i915#2122])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-glk6/igt@kms_flip@2x-plain-flip-ts-check@ab-hdmi-a1-hdmi-a2.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-glk1/igt@kms_flip@2x-plain-flip-ts-check@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank@c-dp1:
- shard-apl: [PASS][17] -> [FAIL][18] ([i915#79])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-apl4/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-apl1/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#658])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-apl7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
#### Possible fixes ####
* igt@fbdev@info:
- {shard-rkl}: [SKIP][20] ([i915#2582]) -> [PASS][21] +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-rkl-2/igt@fbdev@info.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-rkl-5/igt@fbdev@info.html
* igt@gem_eio@hibernate:
- {shard-tglu}: [ABORT][22] ([i915#7975]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-tglu-10/igt@gem_eio@hibernate.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-tglu-9/igt@gem_eio@hibernate.html
* igt@gem_eio@in-flight-contexts-10ms:
- {shard-tglu}: [TIMEOUT][24] ([i915#3063]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-tglu-7/igt@gem_eio@in-flight-contexts-10ms.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-tglu-9/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- {shard-rkl}: [FAIL][26] ([i915#2842]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-rkl-5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-rkl-4/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_reloc@basic-gtt-read-noreloc:
- {shard-rkl}: [SKIP][28] ([i915#3281]) -> [PASS][29] +4 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-rkl-3/igt@gem_exec_reloc@basic-gtt-read-noreloc.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-rkl-5/igt@gem_exec_reloc@basic-gtt-read-noreloc.html
* igt@gem_mmap_gtt@coherency:
- {shard-rkl}: [SKIP][30] ([fdo#111656]) -> [PASS][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-rkl-6/igt@gem_mmap_gtt@coherency.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-rkl-5/igt@gem_mmap_gtt@coherency.html
* igt@gem_partial_pwrite_pread@reads-uncached:
- {shard-rkl}: [SKIP][32] ([i915#3282]) -> [PASS][33] +3 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-rkl-1/igt@gem_partial_pwrite_pread@reads-uncached.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-rkl-5/igt@gem_partial_pwrite_pread@reads-uncached.html
* igt@gen9_exec_parse@batch-invalid-length:
- {shard-rkl}: [SKIP][34] ([i915#2527]) -> [PASS][35] +2 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-rkl-1/igt@gen9_exec_parse@batch-invalid-length.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-rkl-5/igt@gen9_exec_parse@batch-invalid-length.html
* igt@i915_module_load@reload:
- shard-snb: [ABORT][36] ([i915#4528]) -> [PASS][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-snb2/igt@i915_module_load@reload.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-snb5/igt@i915_module_load@reload.html
* igt@i915_pm_dc@dc6-dpms:
- {shard-rkl}: [SKIP][38] ([i915#3361]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-rkl-5/igt@i915_pm_dc@dc6-dpms.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-rkl-3/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_dc@dc9-dpms:
- shard-apl: [SKIP][40] ([fdo#109271]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-apl6/igt@i915_pm_dc@dc9-dpms.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-apl7/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rpm@cursor-dpms:
- {shard-rkl}: [SKIP][42] ([i915#1849]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-rkl-1/igt@i915_pm_rpm@cursor-dpms.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-rkl-6/igt@i915_pm_rpm@cursor-dpms.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- {shard-tglu}: [SKIP][44] ([i915#1397]) -> [PASS][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-tglu-9/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-tglu-3/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- {shard-rkl}: [SKIP][46] ([i915#1397]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-rkl-1/igt@i915_pm_rpm@modeset-lpsp-stress.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@kms_addfb_basic@bad-pitch-63:
- {shard-dg1}: [DMESG-WARN][48] ([i915#4391]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-dg1-18/igt@kms_addfb_basic@bad-pitch-63.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-dg1-14/igt@kms_addfb_basic@bad-pitch-63.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1:
- shard-glk: [FAIL][50] ([i915#2521]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-glk3/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-glk6/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- {shard-tglu}: [SKIP][52] ([i915#1845]) -> [PASS][53] +22 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-tglu-10/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-tglu-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- {shard-rkl}: [SKIP][54] ([i915#1845] / [i915#4098]) -> [PASS][55] +16 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-rkl-2/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-rkl-6/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [FAIL][56] ([i915#2346]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [FAIL][58] ([i915#2346]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@forked-move@pipe-b:
- {shard-tglu}: [INCOMPLETE][60] ([i915#8011]) -> [PASS][61] +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-tglu-1/igt@kms_cursor_legacy@forked-move@pipe-b.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-tglu-8/igt@kms_cursor_legacy@forked-move@pipe-b.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [ABORT][62] ([i915#180]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-apl4/igt@kms_fbcon_fbt@fbc-suspend.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-apl3/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt:
- {shard-tglu}: [SKIP][64] ([i915#1849]) -> [PASS][65] +7 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-tglu-9/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-tglu-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
- {shard-rkl}: [SKIP][66] ([i915#1849] / [i915#4098]) -> [PASS][67] +5 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
* igt@kms_psr@sprite_plane_move:
- {shard-rkl}: [SKIP][68] ([i915#1072]) -> [PASS][69] +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-rkl-4/igt@kms_psr@sprite_plane_move.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-rkl-6/igt@kms_psr@sprite_plane_move.html
* igt@kms_vblank@pipe-b-wait-forked-busy-hang:
- {shard-tglu}: [SKIP][70] ([i915#1845] / [i915#7651]) -> [PASS][71] +6 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-tglu-9/igt@kms_vblank@pipe-b-wait-forked-busy-hang.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-tglu-3/igt@kms_vblank@pipe-b-wait-forked-busy-hang.html
* igt@perf@mi-rpc:
- {shard-rkl}: [SKIP][72] ([i915#2434]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12907/shard-rkl-2/igt@perf@mi-rpc.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/shard-rkl-5/igt@perf@mi-rpc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
[i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7949]: https://gitlab.freedesktop.org/drm/intel/issues/7949
[i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#7988]: https://gitlab.freedesktop.org/drm/intel/issues/7988
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8018]: https://gitlab.freedesktop.org/drm/intel/issues/8018
[i915#8150]: https://gitlab.freedesktop.org/drm/intel/issues/8150
[i915#8152]: https://gitlab.freedesktop.org/drm/intel/issues/8152
[i915#8154]: https://gitlab.freedesktop.org/drm/intel/issues/8154
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8308]: https://gitlab.freedesktop.org/drm/intel/issues/8308
Build changes
-------------
* IGT: IGT_7215 -> IGTPW_8672
* Linux: CI_DRM_12907 -> Patchwork_115570v1
CI-20190529: 20190529
CI_DRM_12907: 3e6be7c63e438996c88d6ba51a7d3025c56086d0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_8672: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8672/index.html
IGT_7215: 78703333d5852a9d5790ca249b313f792fb24cf2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_115570v1: 3e6be7c63e438996c88d6ba51a7d3025c56086d0 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115570v1/index.html
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