* [PATCH v2 0/7] drm/i915: CTM stuff mostly
@ 2023-04-13 16:49 ` Ville Syrjala
0 siblings, 0 replies; 43+ messages in thread
From: Ville Syrjala @ 2023-04-13 16:49 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Mostly some CTM stuff:
- document the uapi better
- fix CHV CSC negative coefficients
- expose CTM on ilk/snb/vlv
- a bonus gamma patch for gen3
- cure CGM CSC underruns on CHV (new in v2)
Test-with: 20230411161555.10001-1-ville.syrjala@linux.intel.com
Ville Syrjälä (7):
drm/uapi: Document CTM matrix better
drm/i915: Expose crtc CTM property on ilk/snb
drm/i915: Fix CHV CGM CSC coefficient sign handling
drm/i915: Always enable CGM CSC on CHV
drm/i915: Implement CTM property support for VLV
drm/i915: No 10bit gamma on desktop gen3 parts
drm/i915: Do state check for color management changes
drivers/gpu/drm/i915/display/intel_color.c | 237 ++++++++++++++++--
.../drm/i915/display/intel_crtc_state_dump.c | 6 +-
drivers/gpu/drm/i915/display/intel_display.c | 8 +
.../drm/i915/display/intel_display_types.h | 3 +
.../drm/i915/display/intel_modeset_verify.c | 2 +
drivers/gpu/drm/i915/i915_pci.c | 8 +-
drivers/gpu/drm/i915/i915_reg.h | 15 ++
include/uapi/drm/drm_mode.h | 5 +
8 files changed, 260 insertions(+), 24 deletions(-)
--
2.39.2
^ permalink raw reply [flat|nested] 43+ messages in thread
* [Intel-gfx] [PATCH v2 0/7] drm/i915: CTM stuff mostly
@ 2023-04-13 16:49 ` Ville Syrjala
0 siblings, 0 replies; 43+ messages in thread
From: Ville Syrjala @ 2023-04-13 16:49 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Mostly some CTM stuff:
- document the uapi better
- fix CHV CSC negative coefficients
- expose CTM on ilk/snb/vlv
- a bonus gamma patch for gen3
- cure CGM CSC underruns on CHV (new in v2)
Test-with: 20230411161555.10001-1-ville.syrjala@linux.intel.com
Ville Syrjälä (7):
drm/uapi: Document CTM matrix better
drm/i915: Expose crtc CTM property on ilk/snb
drm/i915: Fix CHV CGM CSC coefficient sign handling
drm/i915: Always enable CGM CSC on CHV
drm/i915: Implement CTM property support for VLV
drm/i915: No 10bit gamma on desktop gen3 parts
drm/i915: Do state check for color management changes
drivers/gpu/drm/i915/display/intel_color.c | 237 ++++++++++++++++--
.../drm/i915/display/intel_crtc_state_dump.c | 6 +-
drivers/gpu/drm/i915/display/intel_display.c | 8 +
.../drm/i915/display/intel_display_types.h | 3 +
.../drm/i915/display/intel_modeset_verify.c | 2 +
drivers/gpu/drm/i915/i915_pci.c | 8 +-
drivers/gpu/drm/i915/i915_reg.h | 15 ++
include/uapi/drm/drm_mode.h | 5 +
8 files changed, 260 insertions(+), 24 deletions(-)
--
2.39.2
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v2 1/7] drm/uapi: Document CTM matrix better
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
@ 2023-04-13 16:49 ` Ville Syrjala
-1 siblings, 0 replies; 43+ messages in thread
From: Ville Syrjala @ 2023-04-13 16:49 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Document in which order the CTM matrix elements are stored.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
include/uapi/drm/drm_mode.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 46becedf5b2f..43691058d28f 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -834,6 +834,11 @@ struct drm_color_ctm {
/*
* Conversion matrix in S31.32 sign-magnitude
* (not two's complement!) format.
+ *
+ * out matrix in
+ * |R| |0 1 2| |R|
+ * |G| = |3 4 5| x |G|
+ * |B| |6 7 8| |B|
*/
__u64 matrix[9];
};
--
2.39.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [Intel-gfx] [PATCH v2 1/7] drm/uapi: Document CTM matrix better
@ 2023-04-13 16:49 ` Ville Syrjala
0 siblings, 0 replies; 43+ messages in thread
From: Ville Syrjala @ 2023-04-13 16:49 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Document in which order the CTM matrix elements are stored.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
include/uapi/drm/drm_mode.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 46becedf5b2f..43691058d28f 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -834,6 +834,11 @@ struct drm_color_ctm {
/*
* Conversion matrix in S31.32 sign-magnitude
* (not two's complement!) format.
+ *
+ * out matrix in
+ * |R| |0 1 2| |R|
+ * |G| = |3 4 5| x |G|
+ * |B| |6 7 8| |B|
*/
__u64 matrix[9];
};
--
2.39.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 2/7] drm/i915: Expose crtc CTM property on ilk/snb
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
@ 2023-04-13 16:49 ` Ville Syrjala
-1 siblings, 0 replies; 43+ messages in thread
From: Ville Syrjala @ 2023-04-13 16:49 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The ilk/snb code is internally fully capable of handling the
CTM property, so expose it.
Note that we still choose not to expose DEGAMMA_LUT though.
The hardware is capable if degamma or gamma, but not both
similtanously due to lack of the split gamma mode. Exposing
both LUTs might encourage userspace to try enabling both
at the same time.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 07f1afe1d406..4fc16cac052d 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -3473,7 +3473,7 @@ void intel_color_crtc_init(struct intel_crtc *crtc)
gamma_lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
degamma_lut_size = INTEL_INFO(i915)->display.color.degamma_lut_size;
- has_ctm = degamma_lut_size != 0;
+ has_ctm = DISPLAY_VER(i915) >= 5 && !IS_VALLEYVIEW(i915);
/*
* "DPALETTE_A: NOTE: The 8-bit (non-10-bit) mode is the
--
2.39.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [Intel-gfx] [PATCH v2 2/7] drm/i915: Expose crtc CTM property on ilk/snb
@ 2023-04-13 16:49 ` Ville Syrjala
0 siblings, 0 replies; 43+ messages in thread
From: Ville Syrjala @ 2023-04-13 16:49 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The ilk/snb code is internally fully capable of handling the
CTM property, so expose it.
Note that we still choose not to expose DEGAMMA_LUT though.
The hardware is capable if degamma or gamma, but not both
similtanously due to lack of the split gamma mode. Exposing
both LUTs might encourage userspace to try enabling both
at the same time.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 07f1afe1d406..4fc16cac052d 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -3473,7 +3473,7 @@ void intel_color_crtc_init(struct intel_crtc *crtc)
gamma_lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
degamma_lut_size = INTEL_INFO(i915)->display.color.degamma_lut_size;
- has_ctm = degamma_lut_size != 0;
+ has_ctm = DISPLAY_VER(i915) >= 5 && !IS_VALLEYVIEW(i915);
/*
* "DPALETTE_A: NOTE: The 8-bit (non-10-bit) mode is the
--
2.39.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
@ 2023-04-13 16:49 ` Ville Syrjala
-1 siblings, 0 replies; 43+ messages in thread
From: Ville Syrjala @ 2023-04-13 16:49 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The CHV CGM CSC coefficients are in s4.12 two's complement
format. Fix the CTM->CGM conversion to handle that correctly
instead of pretending that the hw coefficients are also
in some sign-magnitude format.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 46 ++++++++++++++--------
1 file changed, 29 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 4fc16cac052d..63141f4ed372 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -568,29 +568,41 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
icl_update_output_csc(crtc, &crtc_state->output_csc);
}
+static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int frac_bits)
+{
+ s64 c = CTM_COEFF_ABS(coeff);
+
+ /* leave an extra bit for rounding */
+ c >>= 32 - frac_bits - 1;
+
+ /* round and drop the extra bit */
+ c = (c + 1) >> 1;
+
+ if (CTM_COEFF_NEGATIVE(coeff))
+ c = -c;
+
+ c = clamp(c, -(s64)BIT(int_bits + frac_bits - 1),
+ (s64)(BIT(int_bits + frac_bits - 1) - 1));
+
+ return c & (BIT(int_bits + frac_bits) - 1);
+}
+
+/*
+ * CHV Color Gamut Mapping (CGM) CSC
+ * |r| | c0 c1 c2 | |r|
+ * |g| = | c3 c4 c5 | x |g|
+ * |b| | c6 c7 c8 | |b|
+ *
+ * Coefficients are two's complement s4.12.
+ */
static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
struct intel_csc_matrix *csc)
{
const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
int i;
- for (i = 0; i < 9; i++) {
- u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
-
- /* Round coefficient. */
- abs_coeff += 1 << (32 - 13);
- /* Clamp to hardware limits. */
- abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
-
- csc->coeff[i] = 0;
-
- /* Write coefficients in S3.12 format. */
- if (ctm->matrix[i] & (1ULL << 63))
- csc->coeff[i] |= 1 << 15;
-
- csc->coeff[i] |= ((abs_coeff >> 32) & 7) << 12;
- csc->coeff[i] |= (abs_coeff >> 20) & 0xfff;
- }
+ for (i = 0; i < 9; i++)
+ csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12);
}
static void chv_load_cgm_csc(struct intel_crtc *crtc,
--
2.39.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [Intel-gfx] [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling
@ 2023-04-13 16:49 ` Ville Syrjala
0 siblings, 0 replies; 43+ messages in thread
From: Ville Syrjala @ 2023-04-13 16:49 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The CHV CGM CSC coefficients are in s4.12 two's complement
format. Fix the CTM->CGM conversion to handle that correctly
instead of pretending that the hw coefficients are also
in some sign-magnitude format.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 46 ++++++++++++++--------
1 file changed, 29 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 4fc16cac052d..63141f4ed372 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -568,29 +568,41 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
icl_update_output_csc(crtc, &crtc_state->output_csc);
}
+static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int frac_bits)
+{
+ s64 c = CTM_COEFF_ABS(coeff);
+
+ /* leave an extra bit for rounding */
+ c >>= 32 - frac_bits - 1;
+
+ /* round and drop the extra bit */
+ c = (c + 1) >> 1;
+
+ if (CTM_COEFF_NEGATIVE(coeff))
+ c = -c;
+
+ c = clamp(c, -(s64)BIT(int_bits + frac_bits - 1),
+ (s64)(BIT(int_bits + frac_bits - 1) - 1));
+
+ return c & (BIT(int_bits + frac_bits) - 1);
+}
+
+/*
+ * CHV Color Gamut Mapping (CGM) CSC
+ * |r| | c0 c1 c2 | |r|
+ * |g| = | c3 c4 c5 | x |g|
+ * |b| | c6 c7 c8 | |b|
+ *
+ * Coefficients are two's complement s4.12.
+ */
static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
struct intel_csc_matrix *csc)
{
const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
int i;
- for (i = 0; i < 9; i++) {
- u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
-
- /* Round coefficient. */
- abs_coeff += 1 << (32 - 13);
- /* Clamp to hardware limits. */
- abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
-
- csc->coeff[i] = 0;
-
- /* Write coefficients in S3.12 format. */
- if (ctm->matrix[i] & (1ULL << 63))
- csc->coeff[i] |= 1 << 15;
-
- csc->coeff[i] |= ((abs_coeff >> 32) & 7) << 12;
- csc->coeff[i] |= (abs_coeff >> 20) & 0xfff;
- }
+ for (i = 0; i < 9; i++)
+ csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12);
}
static void chv_load_cgm_csc(struct intel_crtc *crtc,
--
2.39.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 4/7] drm/i915: Always enable CGM CSC on CHV
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
@ 2023-04-13 16:49 ` Ville Syrjala
-1 siblings, 0 replies; 43+ messages in thread
From: Ville Syrjala @ 2023-04-13 16:49 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
On CHV toggling the CGM CSC on/off while the pipe is running leads
to underruns. Looks like we'd have to do the toggling strictly inside
the start_of_vblank-frame_start window to avoid this, but that window
is less than a scanline so there's no way we can guarantee hitting it.
As a workaround let's just leave the CGM CSC permanently enabled.
Fortunately the CGM gamma/degamma units don't seem to suffer from
this malady.
I also tried turning off CGM unit clock gating, but that did not
help.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 21 +++++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 63141f4ed372..7a705e7d8776 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -605,6 +605,16 @@ static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12);
}
+#define CHV_CGM_CSC_COEFF_1_0 (1 << 12)
+
+static const struct intel_csc_matrix chv_cgm_csc_matrix_identity = {
+ .coeff = {
+ CHV_CGM_CSC_COEFF_1_0, 0, 0,
+ 0, CHV_CGM_CSC_COEFF_1_0, 0,
+ 0, 0, CHV_CGM_CSC_COEFF_1_0,
+ },
+};
+
static void chv_load_cgm_csc(struct intel_crtc *crtc,
const struct intel_csc_matrix *csc)
{
@@ -667,9 +677,9 @@ static void chv_assign_csc(struct intel_crtc_state *crtc_state)
chv_cgm_csc_convert_ctm(crtc_state, &crtc_state->csc);
} else {
- drm_WARN_ON(&i915->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) != 0);
+ drm_WARN_ON(&i915->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) == 0);
- intel_csc_clear(&crtc_state->csc);
+ crtc_state->csc = chv_cgm_csc_matrix_identity;
}
}
@@ -2033,6 +2043,13 @@ static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
!lut_is_legacy(crtc_state->hw.gamma_lut))
cgm_mode |= CGM_PIPE_MODE_GAMMA;
+ /*
+ * Toggling the CGM CSC on/off outside of the tiny window
+ * between start of vblank and frame start causes underruns.
+ * Always enable the CGM CSC as a workaround.
+ */
+ cgm_mode |= CGM_PIPE_MODE_CSC;
+
return cgm_mode;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [Intel-gfx] [PATCH v2 4/7] drm/i915: Always enable CGM CSC on CHV
@ 2023-04-13 16:49 ` Ville Syrjala
0 siblings, 0 replies; 43+ messages in thread
From: Ville Syrjala @ 2023-04-13 16:49 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
On CHV toggling the CGM CSC on/off while the pipe is running leads
to underruns. Looks like we'd have to do the toggling strictly inside
the start_of_vblank-frame_start window to avoid this, but that window
is less than a scanline so there's no way we can guarantee hitting it.
As a workaround let's just leave the CGM CSC permanently enabled.
Fortunately the CGM gamma/degamma units don't seem to suffer from
this malady.
I also tried turning off CGM unit clock gating, but that did not
help.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 21 +++++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 63141f4ed372..7a705e7d8776 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -605,6 +605,16 @@ static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12);
}
+#define CHV_CGM_CSC_COEFF_1_0 (1 << 12)
+
+static const struct intel_csc_matrix chv_cgm_csc_matrix_identity = {
+ .coeff = {
+ CHV_CGM_CSC_COEFF_1_0, 0, 0,
+ 0, CHV_CGM_CSC_COEFF_1_0, 0,
+ 0, 0, CHV_CGM_CSC_COEFF_1_0,
+ },
+};
+
static void chv_load_cgm_csc(struct intel_crtc *crtc,
const struct intel_csc_matrix *csc)
{
@@ -667,9 +677,9 @@ static void chv_assign_csc(struct intel_crtc_state *crtc_state)
chv_cgm_csc_convert_ctm(crtc_state, &crtc_state->csc);
} else {
- drm_WARN_ON(&i915->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) != 0);
+ drm_WARN_ON(&i915->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) == 0);
- intel_csc_clear(&crtc_state->csc);
+ crtc_state->csc = chv_cgm_csc_matrix_identity;
}
}
@@ -2033,6 +2043,13 @@ static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
!lut_is_legacy(crtc_state->hw.gamma_lut))
cgm_mode |= CGM_PIPE_MODE_GAMMA;
+ /*
+ * Toggling the CGM CSC on/off outside of the tiny window
+ * between start of vblank and frame start causes underruns.
+ * Always enable the CGM CSC as a workaround.
+ */
+ cgm_mode |= CGM_PIPE_MODE_CSC;
+
return cgm_mode;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 5/7] drm/i915: Implement CTM property support for VLV
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
@ 2023-04-13 16:49 ` Ville Syrjala
-1 siblings, 0 replies; 43+ messages in thread
From: Ville Syrjala @ 2023-04-13 16:49 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
VLV has a so called "wide gamut color correction" unit (WGC).
What it is is a 3x3 matrix similar to the later CHV CGM
CSC, which less precisions/range. In fact CHV also has the WGC
but using it there doesn't reall make sense when you have the
superior CGM CSC around.
Hook up the necessary stuff to expose the WGC as the CTM
crtc property.
One additional crazy idea that came to mind would be to use
the WGC as an output CSC on CHV for YCbCr output. But it
would be incompatible with the legacy LUT usage. In fact
since the WGC lacks post-offsets we'd probably have to
use the legacy LUT to do that final part of the RGB->YCbCr
conversion. Sounds doable, but perhaps not worth the hassle.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 170 +++++++++++++++++-
.../drm/i915/display/intel_crtc_state_dump.c | 6 +-
drivers/gpu/drm/i915/display/intel_display.c | 8 +
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/i915_reg.h | 15 ++
5 files changed, 198 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 7a705e7d8776..e36d8c248b84 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -587,6 +587,98 @@ static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int frac_bits)
return c & (BIT(int_bits + frac_bits) - 1);
}
+/*
+ * VLV/CHV Wide Gamut Color Correction (WGC) CSC
+ * |r| | c0 c1 c2 | |r|
+ * |g| = | c3 c4 c5 | x |g|
+ * |b| | c6 c7 c8 | |b|
+ *
+ * Coefficients are two's complement s2.10.
+ */
+static void vlv_wgc_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
+ struct intel_csc_matrix *csc)
+{
+ const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
+ int i;
+
+ for (i = 0; i < 9; i++)
+ csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 2, 10);
+}
+
+static void vlv_load_wgc_csc(struct intel_crtc *crtc,
+ const struct intel_csc_matrix *csc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+
+ intel_de_write_fw(dev_priv, PIPE_WGC_C01_C00(pipe),
+ csc->coeff[1] << 16 | csc->coeff[0]);
+ intel_de_write_fw(dev_priv, PIPE_WGC_C02(pipe),
+ csc->coeff[2]);
+
+ intel_de_write_fw(dev_priv, PIPE_WGC_C11_C10(pipe),
+ csc->coeff[4] << 16 | csc->coeff[3]);
+ intel_de_write_fw(dev_priv, PIPE_WGC_C12(pipe),
+ csc->coeff[5]);
+
+ intel_de_write_fw(dev_priv, PIPE_WGC_C21_C20(pipe),
+ csc->coeff[7] << 16 | csc->coeff[6]);
+ intel_de_write_fw(dev_priv, PIPE_WGC_C22(pipe),
+ csc->coeff[8]);
+}
+
+static void vlv_read_wgc_csc(struct intel_crtc *crtc,
+ struct intel_csc_matrix *csc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 tmp;
+
+ tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C01_C00(pipe));
+ csc->coeff[0] = tmp & 0xffff;
+ csc->coeff[1] = tmp >> 16;
+
+ tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C02(pipe));
+ csc->coeff[2] = tmp & 0xffff;
+
+ tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C11_C10(pipe));
+ csc->coeff[3] = tmp & 0xffff;
+ csc->coeff[4] = tmp >> 16;
+
+ tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C12(pipe));
+ csc->coeff[5] = tmp & 0xffff;
+
+ tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C21_C20(pipe));
+ csc->coeff[6] = tmp & 0xffff;
+ csc->coeff[7] = tmp >> 16;
+
+ tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C22(pipe));
+ csc->coeff[8] = tmp & 0xffff;
+}
+
+static void vlv_read_csc(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ if (crtc_state->wgc_enable)
+ vlv_read_wgc_csc(crtc, &crtc_state->csc);
+}
+
+static void vlv_assign_csc(struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+
+ if (crtc_state->hw.ctm) {
+ drm_WARN_ON(&i915->drm, !crtc_state->wgc_enable);
+
+ vlv_wgc_csc_convert_ctm(crtc_state, &crtc_state->csc);
+ } else {
+ drm_WARN_ON(&i915->drm, crtc_state->wgc_enable);
+
+ intel_csc_clear(&crtc_state->csc);
+ }
+}
+
/*
* CHV Color Gamut Mapping (CGM) CSC
* |r| | c0 c1 c2 | |r|
@@ -672,6 +764,8 @@ static void chv_assign_csc(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ drm_WARN_ON(&i915->drm, crtc_state->wgc_enable);
+
if (crtc_state->hw.ctm) {
drm_WARN_ON(&i915->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) == 0);
@@ -1574,6 +1668,16 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
}
}
+static void vlv_load_luts(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ if (crtc_state->wgc_enable)
+ vlv_load_wgc_csc(crtc, &crtc_state->csc);
+
+ i965_load_luts(crtc_state);
+}
+
static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color)
{
return REG_FIELD_PREP(CGM_PIPE_DEGAMMA_GREEN_LDW_MASK, drm_color_lut_extract(color->green, 14)) |
@@ -1728,6 +1832,18 @@ static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state
!old_crtc_state->pre_csc_lut;
}
+static bool vlv_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ struct intel_atomic_state *state =
+ to_intel_atomic_state(new_crtc_state->uapi.state);
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+
+ return !old_crtc_state->wgc_enable &&
+ !old_crtc_state->post_csc_lut;
+}
+
static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
@@ -1744,7 +1860,7 @@ static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode)
return false;
- return !old_crtc_state->post_csc_lut;
+ return vlv_can_preload_luts(new_crtc_state);
}
int intel_color_check(struct intel_crtc_state *crtc_state)
@@ -2031,6 +2147,39 @@ static int i9xx_color_check(struct intel_crtc_state *crtc_state)
return 0;
}
+/*
+ * VLV color pipeline:
+ * u0.10 -> WGC csc -> u0.10 -> pipe gamma -> u0.10
+ */
+static int vlv_color_check(struct intel_crtc_state *crtc_state)
+{
+ int ret;
+
+ ret = check_luts(crtc_state);
+ if (ret)
+ return ret;
+
+ crtc_state->gamma_enable =
+ crtc_state->hw.gamma_lut &&
+ !crtc_state->c8_planes;
+
+ crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);
+
+ crtc_state->wgc_enable = crtc_state->hw.ctm;
+
+ ret = intel_color_add_affected_planes(crtc_state);
+ if (ret)
+ return ret;
+
+ intel_assign_luts(crtc_state);
+
+ vlv_assign_csc(crtc_state);
+
+ crtc_state->preload_luts = vlv_can_preload_luts(crtc_state);
+
+ return 0;
+}
+
static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
{
u32 cgm_mode = 0;
@@ -2081,6 +2230,12 @@ static int chv_color_check(struct intel_crtc_state *crtc_state)
crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
+ /*
+ * We always bypass the WGC CSC and use the CGM CSC
+ * instead since it has degamma and better precision.
+ */
+ crtc_state->wgc_enable = false;
+
ret = intel_color_add_affected_planes(crtc_state);
if (ret)
return ret;
@@ -3395,6 +3550,15 @@ static const struct intel_color_funcs chv_color_funcs = {
.read_csc = chv_read_csc,
};
+static const struct intel_color_funcs vlv_color_funcs = {
+ .color_check = vlv_color_check,
+ .color_commit_arm = i9xx_color_commit_arm,
+ .load_luts = vlv_load_luts,
+ .read_luts = i965_read_luts,
+ .lut_equal = i965_lut_equal,
+ .read_csc = vlv_read_csc,
+};
+
static const struct intel_color_funcs i965_color_funcs = {
.color_check = i9xx_color_check,
.color_commit_arm = i9xx_color_commit_arm,
@@ -3502,7 +3666,7 @@ void intel_color_crtc_init(struct intel_crtc *crtc)
gamma_lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
degamma_lut_size = INTEL_INFO(i915)->display.color.degamma_lut_size;
- has_ctm = DISPLAY_VER(i915) >= 5 && !IS_VALLEYVIEW(i915);
+ has_ctm = DISPLAY_VER(i915) >= 5;
/*
* "DPALETTE_A: NOTE: The 8-bit (non-10-bit) mode is the
@@ -3540,6 +3704,8 @@ void intel_color_init_hooks(struct drm_i915_private *i915)
if (HAS_GMCH(i915)) {
if (IS_CHERRYVIEW(i915))
i915->display.funcs.color = &chv_color_funcs;
+ else if (IS_VALLEYVIEW(i915))
+ i915->display.funcs.color = &vlv_color_funcs;
else if (DISPLAY_VER(i915) >= 4)
i915->display.funcs.color = &i965_color_funcs;
else
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 0cdcaa49656f..dd0895b24682 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -184,7 +184,7 @@ ilk_dump_csc(struct drm_i915_private *i915, const char *name,
}
static void
-chv_dump_csc(struct drm_i915_private *i915, const char *name,
+vlv_dump_csc(struct drm_i915_private *i915, const char *name,
const struct intel_csc_matrix *csc)
{
int i;
@@ -370,7 +370,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
if (!HAS_GMCH(i915))
ilk_dump_csc(i915, "pipe csc", &pipe_config->csc);
else if (IS_CHERRYVIEW(i915))
- chv_dump_csc(i915, "cgm csc", &pipe_config->csc);
+ vlv_dump_csc(i915, "cgm csc", &pipe_config->csc);
+ else if (IS_VALLEYVIEW(i915))
+ vlv_dump_csc(i915, "wgc csc", &pipe_config->csc);
dump_planes:
if (!state)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0334565cec82..962bbd13a5bf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2931,6 +2931,9 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
+ if (crtc_state->wgc_enable)
+ val |= TRANSCONF_WGC_ENABLE;
+
val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
@@ -3123,6 +3126,10 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
+ if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
+ (tmp & TRANSCONF_WGC_ENABLE))
+ pipe_config->wgc_enable = true;
+
if (IS_CHERRYVIEW(dev_priv))
pipe_config->cgm_mode = intel_de_read(dev_priv,
CGM_PIPE_MODE(crtc->pipe));
@@ -5711,6 +5718,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_X(csc_mode);
PIPE_CONF_CHECK_BOOL(gamma_enable);
PIPE_CONF_CHECK_BOOL(csc_enable);
+ PIPE_CONF_CHECK_BOOL(wgc_enable);
PIPE_CONF_CHECK_I(linetime);
PIPE_CONF_CHECK_I(ips_linetime);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b28c8dc48e24..5357664cdf55 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1295,6 +1295,9 @@ struct intel_crtc_state {
/* enable pipe csc? */
bool csc_enable;
+ /* enable vlv/chv wgc csc? */
+ bool wgc_enable;
+
/* big joiner pipe bitmask */
u8 bigjoiner_pipes;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e9dd19cc66a2..e1a6ba6839b6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2550,6 +2550,7 @@
#define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */
#define TRANSCONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x))
#define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16)
+#define TRANSCONF_WGC_ENABLE REG_BIT(15) /* vlv/chv only */
#define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14)
#define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13)
#define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
@@ -6382,6 +6383,20 @@ enum skl_power_gate {
(index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
(index) * 4)
+#define _PIPE_A_WGC_C01_C00 0x600B0 /* s2.10 */
+#define _PIPE_A_WGC_C02 0x600B4 /* s2.10 */
+#define _PIPE_A_WGC_C11_C10 0x600B8 /* s2.10 */
+#define _PIPE_A_WGC_C12 0x600BC /* s2.10 */
+#define _PIPE_A_WGC_C21_C20 0x600C0 /* s2.10 */
+#define _PIPE_A_WGC_C22 0x600C4 /* s2.10 */
+
+#define PIPE_WGC_C01_C00(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C01_C00)
+#define PIPE_WGC_C02(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C02)
+#define PIPE_WGC_C11_C10(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C11_C10)
+#define PIPE_WGC_C12(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C12)
+#define PIPE_WGC_C21_C20(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C21_C20)
+#define PIPE_WGC_C22(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C22)
+
/* pipe CSC & degamma/gamma LUTs on CHV */
#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
#define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
--
2.39.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [Intel-gfx] [PATCH v2 5/7] drm/i915: Implement CTM property support for VLV
@ 2023-04-13 16:49 ` Ville Syrjala
0 siblings, 0 replies; 43+ messages in thread
From: Ville Syrjala @ 2023-04-13 16:49 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
VLV has a so called "wide gamut color correction" unit (WGC).
What it is is a 3x3 matrix similar to the later CHV CGM
CSC, which less precisions/range. In fact CHV also has the WGC
but using it there doesn't reall make sense when you have the
superior CGM CSC around.
Hook up the necessary stuff to expose the WGC as the CTM
crtc property.
One additional crazy idea that came to mind would be to use
the WGC as an output CSC on CHV for YCbCr output. But it
would be incompatible with the legacy LUT usage. In fact
since the WGC lacks post-offsets we'd probably have to
use the legacy LUT to do that final part of the RGB->YCbCr
conversion. Sounds doable, but perhaps not worth the hassle.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 170 +++++++++++++++++-
.../drm/i915/display/intel_crtc_state_dump.c | 6 +-
drivers/gpu/drm/i915/display/intel_display.c | 8 +
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/i915_reg.h | 15 ++
5 files changed, 198 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 7a705e7d8776..e36d8c248b84 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -587,6 +587,98 @@ static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int frac_bits)
return c & (BIT(int_bits + frac_bits) - 1);
}
+/*
+ * VLV/CHV Wide Gamut Color Correction (WGC) CSC
+ * |r| | c0 c1 c2 | |r|
+ * |g| = | c3 c4 c5 | x |g|
+ * |b| | c6 c7 c8 | |b|
+ *
+ * Coefficients are two's complement s2.10.
+ */
+static void vlv_wgc_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
+ struct intel_csc_matrix *csc)
+{
+ const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
+ int i;
+
+ for (i = 0; i < 9; i++)
+ csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 2, 10);
+}
+
+static void vlv_load_wgc_csc(struct intel_crtc *crtc,
+ const struct intel_csc_matrix *csc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+
+ intel_de_write_fw(dev_priv, PIPE_WGC_C01_C00(pipe),
+ csc->coeff[1] << 16 | csc->coeff[0]);
+ intel_de_write_fw(dev_priv, PIPE_WGC_C02(pipe),
+ csc->coeff[2]);
+
+ intel_de_write_fw(dev_priv, PIPE_WGC_C11_C10(pipe),
+ csc->coeff[4] << 16 | csc->coeff[3]);
+ intel_de_write_fw(dev_priv, PIPE_WGC_C12(pipe),
+ csc->coeff[5]);
+
+ intel_de_write_fw(dev_priv, PIPE_WGC_C21_C20(pipe),
+ csc->coeff[7] << 16 | csc->coeff[6]);
+ intel_de_write_fw(dev_priv, PIPE_WGC_C22(pipe),
+ csc->coeff[8]);
+}
+
+static void vlv_read_wgc_csc(struct intel_crtc *crtc,
+ struct intel_csc_matrix *csc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
+ u32 tmp;
+
+ tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C01_C00(pipe));
+ csc->coeff[0] = tmp & 0xffff;
+ csc->coeff[1] = tmp >> 16;
+
+ tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C02(pipe));
+ csc->coeff[2] = tmp & 0xffff;
+
+ tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C11_C10(pipe));
+ csc->coeff[3] = tmp & 0xffff;
+ csc->coeff[4] = tmp >> 16;
+
+ tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C12(pipe));
+ csc->coeff[5] = tmp & 0xffff;
+
+ tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C21_C20(pipe));
+ csc->coeff[6] = tmp & 0xffff;
+ csc->coeff[7] = tmp >> 16;
+
+ tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C22(pipe));
+ csc->coeff[8] = tmp & 0xffff;
+}
+
+static void vlv_read_csc(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ if (crtc_state->wgc_enable)
+ vlv_read_wgc_csc(crtc, &crtc_state->csc);
+}
+
+static void vlv_assign_csc(struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+
+ if (crtc_state->hw.ctm) {
+ drm_WARN_ON(&i915->drm, !crtc_state->wgc_enable);
+
+ vlv_wgc_csc_convert_ctm(crtc_state, &crtc_state->csc);
+ } else {
+ drm_WARN_ON(&i915->drm, crtc_state->wgc_enable);
+
+ intel_csc_clear(&crtc_state->csc);
+ }
+}
+
/*
* CHV Color Gamut Mapping (CGM) CSC
* |r| | c0 c1 c2 | |r|
@@ -672,6 +764,8 @@ static void chv_assign_csc(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ drm_WARN_ON(&i915->drm, crtc_state->wgc_enable);
+
if (crtc_state->hw.ctm) {
drm_WARN_ON(&i915->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) == 0);
@@ -1574,6 +1668,16 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
}
}
+static void vlv_load_luts(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ if (crtc_state->wgc_enable)
+ vlv_load_wgc_csc(crtc, &crtc_state->csc);
+
+ i965_load_luts(crtc_state);
+}
+
static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color)
{
return REG_FIELD_PREP(CGM_PIPE_DEGAMMA_GREEN_LDW_MASK, drm_color_lut_extract(color->green, 14)) |
@@ -1728,6 +1832,18 @@ static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state
!old_crtc_state->pre_csc_lut;
}
+static bool vlv_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ struct intel_atomic_state *state =
+ to_intel_atomic_state(new_crtc_state->uapi.state);
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+
+ return !old_crtc_state->wgc_enable &&
+ !old_crtc_state->post_csc_lut;
+}
+
static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
@@ -1744,7 +1860,7 @@ static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode)
return false;
- return !old_crtc_state->post_csc_lut;
+ return vlv_can_preload_luts(new_crtc_state);
}
int intel_color_check(struct intel_crtc_state *crtc_state)
@@ -2031,6 +2147,39 @@ static int i9xx_color_check(struct intel_crtc_state *crtc_state)
return 0;
}
+/*
+ * VLV color pipeline:
+ * u0.10 -> WGC csc -> u0.10 -> pipe gamma -> u0.10
+ */
+static int vlv_color_check(struct intel_crtc_state *crtc_state)
+{
+ int ret;
+
+ ret = check_luts(crtc_state);
+ if (ret)
+ return ret;
+
+ crtc_state->gamma_enable =
+ crtc_state->hw.gamma_lut &&
+ !crtc_state->c8_planes;
+
+ crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);
+
+ crtc_state->wgc_enable = crtc_state->hw.ctm;
+
+ ret = intel_color_add_affected_planes(crtc_state);
+ if (ret)
+ return ret;
+
+ intel_assign_luts(crtc_state);
+
+ vlv_assign_csc(crtc_state);
+
+ crtc_state->preload_luts = vlv_can_preload_luts(crtc_state);
+
+ return 0;
+}
+
static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
{
u32 cgm_mode = 0;
@@ -2081,6 +2230,12 @@ static int chv_color_check(struct intel_crtc_state *crtc_state)
crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
+ /*
+ * We always bypass the WGC CSC and use the CGM CSC
+ * instead since it has degamma and better precision.
+ */
+ crtc_state->wgc_enable = false;
+
ret = intel_color_add_affected_planes(crtc_state);
if (ret)
return ret;
@@ -3395,6 +3550,15 @@ static const struct intel_color_funcs chv_color_funcs = {
.read_csc = chv_read_csc,
};
+static const struct intel_color_funcs vlv_color_funcs = {
+ .color_check = vlv_color_check,
+ .color_commit_arm = i9xx_color_commit_arm,
+ .load_luts = vlv_load_luts,
+ .read_luts = i965_read_luts,
+ .lut_equal = i965_lut_equal,
+ .read_csc = vlv_read_csc,
+};
+
static const struct intel_color_funcs i965_color_funcs = {
.color_check = i9xx_color_check,
.color_commit_arm = i9xx_color_commit_arm,
@@ -3502,7 +3666,7 @@ void intel_color_crtc_init(struct intel_crtc *crtc)
gamma_lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
degamma_lut_size = INTEL_INFO(i915)->display.color.degamma_lut_size;
- has_ctm = DISPLAY_VER(i915) >= 5 && !IS_VALLEYVIEW(i915);
+ has_ctm = DISPLAY_VER(i915) >= 5;
/*
* "DPALETTE_A: NOTE: The 8-bit (non-10-bit) mode is the
@@ -3540,6 +3704,8 @@ void intel_color_init_hooks(struct drm_i915_private *i915)
if (HAS_GMCH(i915)) {
if (IS_CHERRYVIEW(i915))
i915->display.funcs.color = &chv_color_funcs;
+ else if (IS_VALLEYVIEW(i915))
+ i915->display.funcs.color = &vlv_color_funcs;
else if (DISPLAY_VER(i915) >= 4)
i915->display.funcs.color = &i965_color_funcs;
else
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 0cdcaa49656f..dd0895b24682 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -184,7 +184,7 @@ ilk_dump_csc(struct drm_i915_private *i915, const char *name,
}
static void
-chv_dump_csc(struct drm_i915_private *i915, const char *name,
+vlv_dump_csc(struct drm_i915_private *i915, const char *name,
const struct intel_csc_matrix *csc)
{
int i;
@@ -370,7 +370,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
if (!HAS_GMCH(i915))
ilk_dump_csc(i915, "pipe csc", &pipe_config->csc);
else if (IS_CHERRYVIEW(i915))
- chv_dump_csc(i915, "cgm csc", &pipe_config->csc);
+ vlv_dump_csc(i915, "cgm csc", &pipe_config->csc);
+ else if (IS_VALLEYVIEW(i915))
+ vlv_dump_csc(i915, "wgc csc", &pipe_config->csc);
dump_planes:
if (!state)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0334565cec82..962bbd13a5bf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2931,6 +2931,9 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
+ if (crtc_state->wgc_enable)
+ val |= TRANSCONF_WGC_ENABLE;
+
val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
@@ -3123,6 +3126,10 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
+ if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
+ (tmp & TRANSCONF_WGC_ENABLE))
+ pipe_config->wgc_enable = true;
+
if (IS_CHERRYVIEW(dev_priv))
pipe_config->cgm_mode = intel_de_read(dev_priv,
CGM_PIPE_MODE(crtc->pipe));
@@ -5711,6 +5718,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_X(csc_mode);
PIPE_CONF_CHECK_BOOL(gamma_enable);
PIPE_CONF_CHECK_BOOL(csc_enable);
+ PIPE_CONF_CHECK_BOOL(wgc_enable);
PIPE_CONF_CHECK_I(linetime);
PIPE_CONF_CHECK_I(ips_linetime);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b28c8dc48e24..5357664cdf55 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1295,6 +1295,9 @@ struct intel_crtc_state {
/* enable pipe csc? */
bool csc_enable;
+ /* enable vlv/chv wgc csc? */
+ bool wgc_enable;
+
/* big joiner pipe bitmask */
u8 bigjoiner_pipes;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e9dd19cc66a2..e1a6ba6839b6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2550,6 +2550,7 @@
#define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */
#define TRANSCONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x))
#define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16)
+#define TRANSCONF_WGC_ENABLE REG_BIT(15) /* vlv/chv only */
#define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14)
#define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13)
#define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
@@ -6382,6 +6383,20 @@ enum skl_power_gate {
(index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
(index) * 4)
+#define _PIPE_A_WGC_C01_C00 0x600B0 /* s2.10 */
+#define _PIPE_A_WGC_C02 0x600B4 /* s2.10 */
+#define _PIPE_A_WGC_C11_C10 0x600B8 /* s2.10 */
+#define _PIPE_A_WGC_C12 0x600BC /* s2.10 */
+#define _PIPE_A_WGC_C21_C20 0x600C0 /* s2.10 */
+#define _PIPE_A_WGC_C22 0x600C4 /* s2.10 */
+
+#define PIPE_WGC_C01_C00(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C01_C00)
+#define PIPE_WGC_C02(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C02)
+#define PIPE_WGC_C11_C10(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C11_C10)
+#define PIPE_WGC_C12(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C12)
+#define PIPE_WGC_C21_C20(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C21_C20)
+#define PIPE_WGC_C22(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C22)
+
/* pipe CSC & degamma/gamma LUTs on CHV */
#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
#define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
--
2.39.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 6/7] drm/i915: No 10bit gamma on desktop gen3 parts
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
@ 2023-04-13 16:49 ` Ville Syrjala
-1 siblings, 0 replies; 43+ messages in thread
From: Ville Syrjala @ 2023-04-13 16:49 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Apparently desktop gen3 parts don't support the
10bit gamma mode at all. Stop claiming otherwise.
As is the case with pipe A on gen3 mobile parts, the
PIPECONF gamma mode bit can be set but it has no
effect on the output.
PNV seems to be the only slight exception, but generally
the desktop PNV variant looks more like a mobile part so
this is not entirely surprising.
Fixes: 67630bacae23 ("drm/i915: Add 10bit gamma mode for gen2/3")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index cddb6e197972..305c05c3f93b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -250,13 +250,13 @@ static const struct intel_device_info i865g_info = {
.dma_mask_size = 32, \
I9XX_PIPE_OFFSETS, \
I9XX_CURSOR_OFFSETS, \
- I9XX_COLORS, \
GEN_DEFAULT_PAGE_SIZES, \
GEN_DEFAULT_REGIONS
static const struct intel_device_info i915g_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I915G),
+ I845_COLORS,
.has_coherent_ggtt = false,
.display.cursor_needs_physical = 1,
.display.has_overlay = 1,
@@ -268,6 +268,7 @@ static const struct intel_device_info i915g_info = {
static const struct intel_device_info i915gm_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I915GM),
+ I9XX_COLORS,
.is_mobile = 1,
.display.cursor_needs_physical = 1,
.display.has_overlay = 1,
@@ -281,6 +282,7 @@ static const struct intel_device_info i915gm_info = {
static const struct intel_device_info i945g_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I945G),
+ I845_COLORS,
.display.has_hotplug = 1,
.display.cursor_needs_physical = 1,
.display.has_overlay = 1,
@@ -292,6 +294,7 @@ static const struct intel_device_info i945g_info = {
static const struct intel_device_info i945gm_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I945GM),
+ I9XX_COLORS,
.is_mobile = 1,
.display.has_hotplug = 1,
.display.cursor_needs_physical = 1,
@@ -306,6 +309,7 @@ static const struct intel_device_info i945gm_info = {
static const struct intel_device_info g33_info = {
GEN3_FEATURES,
PLATFORM(INTEL_G33),
+ I845_COLORS,
.display.has_hotplug = 1,
.display.has_overlay = 1,
.dma_mask_size = 36,
@@ -314,6 +318,7 @@ static const struct intel_device_info g33_info = {
static const struct intel_device_info pnv_g_info = {
GEN3_FEATURES,
PLATFORM(INTEL_PINEVIEW),
+ I9XX_COLORS,
.display.has_hotplug = 1,
.display.has_overlay = 1,
.dma_mask_size = 36,
@@ -322,6 +327,7 @@ static const struct intel_device_info pnv_g_info = {
static const struct intel_device_info pnv_m_info = {
GEN3_FEATURES,
PLATFORM(INTEL_PINEVIEW),
+ I9XX_COLORS,
.is_mobile = 1,
.display.has_hotplug = 1,
.display.has_overlay = 1,
--
2.39.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [Intel-gfx] [PATCH v2 6/7] drm/i915: No 10bit gamma on desktop gen3 parts
@ 2023-04-13 16:49 ` Ville Syrjala
0 siblings, 0 replies; 43+ messages in thread
From: Ville Syrjala @ 2023-04-13 16:49 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Apparently desktop gen3 parts don't support the
10bit gamma mode at all. Stop claiming otherwise.
As is the case with pipe A on gen3 mobile parts, the
PIPECONF gamma mode bit can be set but it has no
effect on the output.
PNV seems to be the only slight exception, but generally
the desktop PNV variant looks more like a mobile part so
this is not entirely surprising.
Fixes: 67630bacae23 ("drm/i915: Add 10bit gamma mode for gen2/3")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index cddb6e197972..305c05c3f93b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -250,13 +250,13 @@ static const struct intel_device_info i865g_info = {
.dma_mask_size = 32, \
I9XX_PIPE_OFFSETS, \
I9XX_CURSOR_OFFSETS, \
- I9XX_COLORS, \
GEN_DEFAULT_PAGE_SIZES, \
GEN_DEFAULT_REGIONS
static const struct intel_device_info i915g_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I915G),
+ I845_COLORS,
.has_coherent_ggtt = false,
.display.cursor_needs_physical = 1,
.display.has_overlay = 1,
@@ -268,6 +268,7 @@ static const struct intel_device_info i915g_info = {
static const struct intel_device_info i915gm_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I915GM),
+ I9XX_COLORS,
.is_mobile = 1,
.display.cursor_needs_physical = 1,
.display.has_overlay = 1,
@@ -281,6 +282,7 @@ static const struct intel_device_info i915gm_info = {
static const struct intel_device_info i945g_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I945G),
+ I845_COLORS,
.display.has_hotplug = 1,
.display.cursor_needs_physical = 1,
.display.has_overlay = 1,
@@ -292,6 +294,7 @@ static const struct intel_device_info i945g_info = {
static const struct intel_device_info i945gm_info = {
GEN3_FEATURES,
PLATFORM(INTEL_I945GM),
+ I9XX_COLORS,
.is_mobile = 1,
.display.has_hotplug = 1,
.display.cursor_needs_physical = 1,
@@ -306,6 +309,7 @@ static const struct intel_device_info i945gm_info = {
static const struct intel_device_info g33_info = {
GEN3_FEATURES,
PLATFORM(INTEL_G33),
+ I845_COLORS,
.display.has_hotplug = 1,
.display.has_overlay = 1,
.dma_mask_size = 36,
@@ -314,6 +318,7 @@ static const struct intel_device_info g33_info = {
static const struct intel_device_info pnv_g_info = {
GEN3_FEATURES,
PLATFORM(INTEL_PINEVIEW),
+ I9XX_COLORS,
.display.has_hotplug = 1,
.display.has_overlay = 1,
.dma_mask_size = 36,
@@ -322,6 +327,7 @@ static const struct intel_device_info pnv_g_info = {
static const struct intel_device_info pnv_m_info = {
GEN3_FEATURES,
PLATFORM(INTEL_PINEVIEW),
+ I9XX_COLORS,
.is_mobile = 1,
.display.has_hotplug = 1,
.display.has_overlay = 1,
--
2.39.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [PATCH v2 7/7] drm/i915: Do state check for color management changes
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
@ 2023-04-13 16:49 ` Ville Syrjala
-1 siblings, 0 replies; 43+ messages in thread
From: Ville Syrjala @ 2023-04-13 16:49 UTC (permalink / raw)
To: intel-gfx; +Cc: Uma Shankar, dri-devel
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
In order to validate LUT programming more thoroughly let's
do a state check for all color management updates as well.
Not sure we really want this outside CI. It is rather heavy
and color management updates could become rather common
with all the HDR/etc. stuff happening. Maybe we should have
an extra knob for this that we could enable in CI?
v2: Skip for initial_commit to avoid FDI dotclock
sanity checks/etc. tripping up
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_modeset_verify.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index 842d70f0dfd2..9e4767e1b900 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -228,6 +228,8 @@ void intel_modeset_verify_crtc(struct intel_crtc *crtc,
struct intel_crtc_state *new_crtc_state)
{
if (!intel_crtc_needs_modeset(new_crtc_state) &&
+ (!intel_crtc_needs_color_update(new_crtc_state) ||
+ new_crtc_state->inherited) &&
!intel_crtc_needs_fastset(new_crtc_state))
return;
--
2.39.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [Intel-gfx] [PATCH v2 7/7] drm/i915: Do state check for color management changes
@ 2023-04-13 16:49 ` Ville Syrjala
0 siblings, 0 replies; 43+ messages in thread
From: Ville Syrjala @ 2023-04-13 16:49 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
In order to validate LUT programming more thoroughly let's
do a state check for all color management updates as well.
Not sure we really want this outside CI. It is rather heavy
and color management updates could become rather common
with all the HDR/etc. stuff happening. Maybe we should have
an extra knob for this that we could enable in CI?
v2: Skip for initial_commit to avoid FDI dotclock
sanity checks/etc. tripping up
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_modeset_verify.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index 842d70f0dfd2..9e4767e1b900 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -228,6 +228,8 @@ void intel_modeset_verify_crtc(struct intel_crtc *crtc,
struct intel_crtc_state *new_crtc_state)
{
if (!intel_crtc_needs_modeset(new_crtc_state) &&
+ (!intel_crtc_needs_color_update(new_crtc_state) ||
+ new_crtc_state->inherited) &&
!intel_crtc_needs_fastset(new_crtc_state))
return;
--
2.39.2
^ permalink raw reply related [flat|nested] 43+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: CTM stuff mostly (rev3)
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
` (7 preceding siblings ...)
(?)
@ 2023-04-13 18:28 ` Patchwork
-1 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2023-04-13 18:28 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: CTM stuff mostly (rev3)
URL : https://patchwork.freedesktop.org/series/116345/
State : warning
== Summary ==
Error: dim checkpatch failed
78b5c06e6a08 drm/uapi: Document CTM matrix better
040d34333d15 drm/i915: Expose crtc CTM property on ilk/snb
025b0a294b12 drm/i915: Fix CHV CGM CSC coefficient sign handling
4c183dda16bc drm/i915: Always enable CGM CSC on CHV
9b4ab15ce12b drm/i915: Implement CTM property support for VLV
-:10: WARNING:REPEATED_WORD: Possible repeated word: 'is'
#10:
What it is is a 3x3 matrix similar to the later CHV CGM
total: 0 errors, 1 warnings, 0 checks, 310 lines checked
28846b2d788c drm/i915: No 10bit gamma on desktop gen3 parts
deec600a1da5 drm/i915: Do state check for color management changes
^ permalink raw reply [flat|nested] 43+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: CTM stuff mostly (rev3)
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
` (8 preceding siblings ...)
(?)
@ 2023-04-13 18:28 ` Patchwork
-1 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2023-04-13 18:28 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: CTM stuff mostly (rev3)
URL : https://patchwork.freedesktop.org/series/116345/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 43+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: CTM stuff mostly (rev3)
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
` (9 preceding siblings ...)
(?)
@ 2023-04-13 18:49 ` Patchwork
-1 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2023-04-13 18:49 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 14691 bytes --]
== Series Details ==
Series: drm/i915: CTM stuff mostly (rev3)
URL : https://patchwork.freedesktop.org/series/116345/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13003 -> Patchwork_116345v3
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_116345v3 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_116345v3, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/index.html
Participating hosts (36 -> 36)
------------------------------
Additional (1): fi-kbl-soraka
Missing (1): fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_116345v3:
### IGT changes ###
#### Possible regressions ####
* igt@kms_color@ctm-red-to-blue@pipe-a (NEW):
- bat-dg2-11: NOTRUN -> [ABORT][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/bat-dg2-11/igt@kms_color@ctm-red-to-blue@pipe-a.html
- bat-dg2-8: NOTRUN -> [ABORT][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/bat-dg2-8/igt@kms_color@ctm-red-to-blue@pipe-a.html
- bat-dg2-9: NOTRUN -> [ABORT][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/bat-dg2-9/igt@kms_color@ctm-red-to-blue@pipe-a.html
New tests
---------
New tests have been introduced between CI_DRM_13003 and Patchwork_116345v3:
### New IGT tests (37) ###
* igt@kms_color@ctm-0-25@pipe-a:
- Statuses : 20 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-25@pipe-b:
- Statuses : 20 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-25@pipe-c:
- Statuses : 20 pass(s) 6 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-25@pipe-d:
- Statuses : 5 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-50@pipe-a:
- Statuses : 20 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-50@pipe-b:
- Statuses : 20 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-50@pipe-c:
- Statuses : 20 pass(s) 6 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-50@pipe-d:
- Statuses : 5 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-75@pipe-a:
- Statuses : 20 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-75@pipe-b:
- Statuses : 20 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-75@pipe-c:
- Statuses : 20 pass(s) 6 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-75@pipe-d:
- Statuses : 5 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-blue-to-red@pipe-a:
- Statuses : 20 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-blue-to-red@pipe-b:
- Statuses : 20 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-blue-to-red@pipe-c:
- Statuses : 20 pass(s) 6 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-blue-to-red@pipe-d:
- Statuses : 5 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-green-to-red@pipe-a:
- Statuses : 20 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-green-to-red@pipe-b:
- Statuses : 20 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-green-to-red@pipe-c:
- Statuses : 20 pass(s) 6 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-green-to-red@pipe-d:
- Statuses : 5 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-max@pipe-a:
- Statuses : 20 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-max@pipe-b:
- Statuses : 20 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-max@pipe-c:
- Statuses : 20 pass(s) 6 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-max@pipe-d:
- Statuses : 5 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-negative@pipe-a:
- Statuses : 20 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-negative@pipe-b:
- Statuses : 20 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-negative@pipe-c:
- Statuses : 20 pass(s) 6 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-negative@pipe-d:
- Statuses : 5 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-red-to-blue@pipe-a:
- Statuses : 3 abort(s) 20 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-red-to-blue@pipe-b:
- Statuses : 20 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-red-to-blue@pipe-c:
- Statuses : 20 pass(s) 6 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-red-to-blue@pipe-d:
- Statuses : 5 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-signed:
- Statuses :
- Exec time: [None] s
* igt@kms_color@ctm-signed@pipe-a:
- Statuses : 20 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-signed@pipe-b:
- Statuses : 20 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-signed@pipe-c:
- Statuses : 20 pass(s) 6 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-signed@pipe-d:
- Statuses : 5 pass(s) 1 skip(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_116345v3 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-7567u: [PASS][6] -> [DMESG-FAIL][7] ([i915#5334] / [i915#7872])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/fi-kbl-7567u/igt@i915_selftest@live@gt_heartbeat.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/fi-kbl-7567u/igt@i915_selftest@live@gt_heartbeat.html
- fi-cfl-8109u: [PASS][8] -> [DMESG-FAIL][9] ([i915#5334])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/fi-cfl-8109u/igt@i915_selftest@live@gt_heartbeat.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/fi-cfl-8109u/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][10] ([i915#1886])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@requests:
- bat-rpls-1: [PASS][11] -> [ABORT][12] ([i915#7911])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/bat-rpls-1/igt@i915_selftest@live@requests.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/bat-rpls-1/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-FAIL][13] ([i915#6367] / [i915#7913] / [i915#7996])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/bat-rpls-2/igt@i915_selftest@live@slpc.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][14] ([fdo#109271]) +16 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/fi-kbl-soraka/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-rpls-2: NOTRUN -> [SKIP][15] ([i915#7828])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/bat-rpls-2/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
- bat-adlp-9: NOTRUN -> [SKIP][16] ([i915#7828])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/bat-adlp-9/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_color@ctm-0-25@pipe-b (NEW):
- {bat-kbl-2}: NOTRUN -> [SKIP][17] ([fdo#109271]) +26 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/bat-kbl-2/igt@kms_color@ctm-0-25@pipe-b.html
* igt@kms_color@ctm-0-50@pipe-b (NEW):
- fi-bsw-n3050: NOTRUN -> [SKIP][18] ([fdo#109271]) +17 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/fi-bsw-n3050/igt@kms_color@ctm-0-50@pipe-b.html
* igt@kms_color@ctm-0-75@pipe-a (NEW):
- bat-rpls-2: NOTRUN -> [SKIP][19] ([i915#5354]) +17 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/bat-rpls-2/igt@kms_color@ctm-0-75@pipe-a.html
* igt@kms_color@ctm-blue-to-red@pipe-c (NEW):
- fi-bsw-nick: NOTRUN -> [SKIP][20] ([fdo#109271]) +26 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/fi-bsw-nick/igt@kms_color@ctm-blue-to-red@pipe-c.html
- fi-kbl-guc: NOTRUN -> [SKIP][21] ([fdo#109271]) +26 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/fi-kbl-guc/igt@kms_color@ctm-blue-to-red@pipe-c.html
* igt@kms_color@ctm-green-to-red@pipe-c (NEW):
- fi-kbl-8809g: NOTRUN -> [SKIP][22] ([fdo#109271]) +26 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/fi-kbl-8809g/igt@kms_color@ctm-green-to-red@pipe-c.html
* igt@kms_color@ctm-max@pipe-b (NEW):
- bat-dg1-7: NOTRUN -> [SKIP][23] ([i915#5354]) +35 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/bat-dg1-7/igt@kms_color@ctm-max@pipe-b.html
* {igt@kms_color@ctm-signed@pipe-a} (NEW):
- fi-kbl-x1275: NOTRUN -> [SKIP][24] ([fdo#109271]) +26 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/fi-kbl-x1275/igt@kms_color@ctm-signed@pipe-a.html
* {igt@kms_color@ctm-signed@pipe-b} (NEW):
- fi-elk-e7500: NOTRUN -> [SKIP][25] ([fdo#109271]) +19 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/fi-elk-e7500/igt@kms_color@ctm-signed@pipe-b.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1:
- bat-dg2-8: [PASS][26] -> [FAIL][27] ([i915#7932])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1.html
* igt@kms_pipe_crc_basic@read-crc:
- bat-adlp-9: NOTRUN -> [SKIP][28] ([i915#3546]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/bat-adlp-9/igt@kms_pipe_crc_basic@read-crc.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-rpls-2: NOTRUN -> [SKIP][29] ([i915#1845])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/bat-rpls-2/igt@kms_pipe_crc_basic@suspend-read-crc.html
#### Possible fixes ####
* igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][30] ([i915#4983] / [i915#7913] / [i915#7981]) -> [PASS][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/bat-rpls-2/igt@i915_selftest@live@reset.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/bat-rpls-2/igt@i915_selftest@live@reset.html
* igt@i915_selftest@live@uncore:
- bat-adlp-9: [ABORT][32] -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/bat-adlp-9/igt@i915_selftest@live@uncore.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/bat-adlp-9/igt@i915_selftest@live@uncore.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-1:
- bat-dg2-8: [FAIL][34] ([i915#7932]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13003/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-1.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-c-dp-1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
[i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996
Build changes
-------------
* IGT: IGT_7254 -> IGTPW_8780
* Linux: CI_DRM_13003 -> Patchwork_116345v3
CI-20190529: 20190529
CI_DRM_13003: 9452fe4b47da924d60188cd39d263e5a980db5df @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_8780: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8780/index.html
IGT_7254: 7fab01340a3f360abacd7914015be1ad485363d7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116345v3: 9452fe4b47da924d60188cd39d263e5a980db5df @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
1ebc4ff8110f drm/i915: Do state check for color management changes
58bb4021515b drm/i915: No 10bit gamma on desktop gen3 parts
43f193c0b1c9 drm/i915: Implement CTM property support for VLV
5cc6f8550ee4 drm/i915: Always enable CGM CSC on CHV
e249909a0b1e drm/i915: Fix CHV CGM CSC coefficient sign handling
a8f97b8c86aa drm/i915: Expose crtc CTM property on ilk/snb
f47e7db4c997 drm/uapi: Document CTM matrix better
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v3/index.html
[-- Attachment #2: Type: text/html, Size: 18108 bytes --]
^ permalink raw reply [flat|nested] 43+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: CTM stuff mostly (rev4)
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
` (10 preceding siblings ...)
(?)
@ 2023-04-15 12:56 ` Patchwork
-1 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2023-04-15 12:56 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: CTM stuff mostly (rev4)
URL : https://patchwork.freedesktop.org/series/116345/
State : warning
== Summary ==
Error: dim checkpatch failed
047d4bfb8f8a drm/uapi: Document CTM matrix better
6bb0580031e8 drm/i915: Expose crtc CTM property on ilk/snb
e8cf7eed080a drm/i915: Fix CHV CGM CSC coefficient sign handling
fa548815165c drm/i915: Always enable CGM CSC on CHV
38fe12b5723d drm/i915: Implement CTM property support for VLV
-:10: WARNING:REPEATED_WORD: Possible repeated word: 'is'
#10:
What it is is a 3x3 matrix similar to the later CHV CGM
total: 0 errors, 1 warnings, 0 checks, 310 lines checked
5bc9c17fdde8 drm/i915: No 10bit gamma on desktop gen3 parts
660763193ca8 drm/i915: Do state check for color management changes
^ permalink raw reply [flat|nested] 43+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: CTM stuff mostly (rev4)
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
` (11 preceding siblings ...)
(?)
@ 2023-04-15 13:09 ` Patchwork
-1 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2023-04-15 13:09 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 11037 bytes --]
== Series Details ==
Series: drm/i915: CTM stuff mostly (rev4)
URL : https://patchwork.freedesktop.org/series/116345/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13010 -> Patchwork_116345v4
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_116345v4 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_116345v4, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v4/index.html
Participating hosts (38 -> 36)
------------------------------
Missing (2): fi-kbl-soraka fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_116345v4:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@hangcheck:
- bat-adln-1: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/bat-adln-1/igt@i915_selftest@live@hangcheck.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v4/bat-adln-1/igt@i915_selftest@live@hangcheck.html
* igt@kms_color@ctm-blue-to-red@pipe-d (NEW):
- bat-adlp-9: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v4/bat-adlp-9/igt@kms_color@ctm-blue-to-red@pipe-d.html
New tests
---------
New tests have been introduced between CI_DRM_13010 and Patchwork_116345v4:
### New IGT tests (37) ###
* igt@kms_color@ctm-0-25@pipe-a:
- Statuses : 21 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-25@pipe-b:
- Statuses : 21 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-25@pipe-c:
- Statuses : 21 pass(s) 7 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-25@pipe-d:
- Statuses : 7 pass(s) 2 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-50@pipe-a:
- Statuses : 21 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-50@pipe-b:
- Statuses : 21 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-50@pipe-c:
- Statuses : 21 pass(s) 7 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-50@pipe-d:
- Statuses : 7 pass(s) 2 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-75@pipe-a:
- Statuses : 21 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-75@pipe-b:
- Statuses : 21 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-75@pipe-c:
- Statuses : 21 pass(s) 7 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-75@pipe-d:
- Statuses : 7 pass(s) 2 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-blue-to-red@pipe-a:
- Statuses : 22 pass(s) 8 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-blue-to-red@pipe-b:
- Statuses : 22 pass(s) 8 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-blue-to-red@pipe-c:
- Statuses : 22 pass(s) 6 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-blue-to-red@pipe-d:
- Statuses : 1 fail(s) 7 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-green-to-red@pipe-a:
- Statuses : 22 pass(s) 8 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-green-to-red@pipe-b:
- Statuses : 22 pass(s) 8 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-green-to-red@pipe-c:
- Statuses : 22 pass(s) 6 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-green-to-red@pipe-d:
- Statuses : 8 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-max@pipe-a:
- Statuses : 22 pass(s) 8 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-max@pipe-b:
- Statuses : 22 pass(s) 8 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-max@pipe-c:
- Statuses : 22 pass(s) 6 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-max@pipe-d:
- Statuses : 8 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-negative@pipe-a:
- Statuses : 21 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-negative@pipe-b:
- Statuses : 21 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-negative@pipe-c:
- Statuses : 21 pass(s) 7 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-negative@pipe-d:
- Statuses : 7 pass(s) 2 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-red-to-blue@pipe-a:
- Statuses : 22 pass(s) 8 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-red-to-blue@pipe-b:
- Statuses : 21 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-red-to-blue@pipe-c:
- Statuses : 21 pass(s) 7 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-red-to-blue@pipe-d:
- Statuses : 7 pass(s) 2 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-signed:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-signed@pipe-a:
- Statuses : 22 pass(s) 8 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-signed@pipe-b:
- Statuses : 22 pass(s) 8 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-signed@pipe-c:
- Statuses : 22 pass(s) 6 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-signed@pipe-d:
- Statuses : 8 pass(s) 1 skip(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_116345v4 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@slpc:
- bat-rpls-1: [PASS][4] -> [DMESG-FAIL][5] ([i915#6367] / [i915#7996])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/bat-rpls-1/igt@i915_selftest@live@slpc.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v4/bat-rpls-1/igt@i915_selftest@live@slpc.html
* igt@kms_color@ctm-0-25:
- bat-atsm-1: NOTRUN -> [SKIP][6] ([i915#6078]) +9 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v4/bat-atsm-1/igt@kms_color@ctm-0-25.html
* igt@kms_color@ctm-0-25@pipe-b (NEW):
- {bat-kbl-2}: NOTRUN -> [SKIP][7] ([fdo#109271]) +26 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v4/bat-kbl-2/igt@kms_color@ctm-0-25@pipe-b.html
* igt@kms_color@ctm-0-25@pipe-d (NEW):
- bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#5354]) +15 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v4/bat-dg2-11/igt@kms_color@ctm-0-25@pipe-d.html
* igt@kms_color@ctm-0-50@pipe-b (NEW):
- fi-bsw-n3050: NOTRUN -> [SKIP][9] ([fdo#109271]) +17 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v4/fi-bsw-n3050/igt@kms_color@ctm-0-50@pipe-b.html
* igt@kms_color@ctm-blue-to-red@pipe-c (NEW):
- fi-bsw-nick: NOTRUN -> [SKIP][10] ([fdo#109271]) +26 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v4/fi-bsw-nick/igt@kms_color@ctm-blue-to-red@pipe-c.html
- fi-kbl-guc: NOTRUN -> [SKIP][11] ([fdo#109271]) +26 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v4/fi-kbl-guc/igt@kms_color@ctm-blue-to-red@pipe-c.html
* igt@kms_color@ctm-green-to-red@pipe-a (NEW):
- fi-elk-e7500: NOTRUN -> [SKIP][12] ([fdo#109271]) +19 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v4/fi-elk-e7500/igt@kms_color@ctm-green-to-red@pipe-a.html
* igt@kms_color@ctm-green-to-red@pipe-c (NEW):
- fi-kbl-8809g: NOTRUN -> [SKIP][13] ([fdo#109271]) +26 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v4/fi-kbl-8809g/igt@kms_color@ctm-green-to-red@pipe-c.html
* igt@kms_color@ctm-max@pipe-b (NEW):
- bat-dg1-7: NOTRUN -> [SKIP][14] ([i915#5354]) +35 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v4/bat-dg1-7/igt@kms_color@ctm-max@pipe-b.html
* igt@kms_color@ctm-red-to-blue@pipe-c (NEW):
- bat-dg2-9: NOTRUN -> [SKIP][15] ([i915#5354]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v4/bat-dg2-9/igt@kms_color@ctm-red-to-blue@pipe-c.html
* {igt@kms_color@ctm-signed@pipe-a} (NEW):
- fi-kbl-x1275: NOTRUN -> [SKIP][16] ([fdo#109271]) +26 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v4/fi-kbl-x1275/igt@kms_color@ctm-signed@pipe-a.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
- bat-dg2-8: [PASS][17] -> [FAIL][18] ([i915#7932])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v4/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html
#### Possible fixes ####
* igt@i915_selftest@live@migrate:
- bat-adlp-9: [DMESG-FAIL][19] ([i915#7699]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/bat-adlp-9/igt@i915_selftest@live@migrate.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v4/bat-adlp-9/igt@i915_selftest@live@migrate.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6078]: https://gitlab.freedesktop.org/drm/intel/issues/6078
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996
Build changes
-------------
* IGT: IGT_7256 -> IGTPW_8780
* Linux: CI_DRM_13010 -> Patchwork_116345v4
CI-20190529: 20190529
CI_DRM_13010: a3cb6a082228cf82afbc828b6074b53b118144cf @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_8780: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8780/index.html
IGT_7256: 066fa5410180730b85f61e4f3073da9a2055dc49 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116345v4: a3cb6a082228cf82afbc828b6074b53b118144cf @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
af259a32e71b drm/i915: Do state check for color management changes
28c881be352d drm/i915: No 10bit gamma on desktop gen3 parts
9437db2d8a7e drm/i915: Implement CTM property support for VLV
b4d07a3e43c8 drm/i915: Always enable CGM CSC on CHV
27a5115c8722 drm/i915: Fix CHV CGM CSC coefficient sign handling
b84b3cad1253 drm/i915: Expose crtc CTM property on ilk/snb
5aff7356c78f drm/uapi: Document CTM matrix better
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v4/index.html
[-- Attachment #2: Type: text/html, Size: 13770 bytes --]
^ permalink raw reply [flat|nested] 43+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: CTM stuff mostly (rev5)
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
` (12 preceding siblings ...)
(?)
@ 2023-04-15 20:11 ` Patchwork
-1 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2023-04-15 20:11 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: CTM stuff mostly (rev5)
URL : https://patchwork.freedesktop.org/series/116345/
State : warning
== Summary ==
Error: dim checkpatch failed
2b54d7a8aa92 drm/uapi: Document CTM matrix better
7127e86b5c95 drm/i915: Expose crtc CTM property on ilk/snb
488c3c2914a6 drm/i915: Fix CHV CGM CSC coefficient sign handling
1bab5384e6de drm/i915: Always enable CGM CSC on CHV
47aaf0c7468c drm/i915: Implement CTM property support for VLV
-:10: WARNING:REPEATED_WORD: Possible repeated word: 'is'
#10:
What it is is a 3x3 matrix similar to the later CHV CGM
total: 0 errors, 1 warnings, 0 checks, 310 lines checked
8360eef9d74d drm/i915: No 10bit gamma on desktop gen3 parts
598528cce151 drm/i915: Do state check for color management changes
^ permalink raw reply [flat|nested] 43+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: CTM stuff mostly (rev5)
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
` (13 preceding siblings ...)
(?)
@ 2023-04-15 20:11 ` Patchwork
-1 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2023-04-15 20:11 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: CTM stuff mostly (rev5)
URL : https://patchwork.freedesktop.org/series/116345/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 43+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: CTM stuff mostly (rev5)
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
` (14 preceding siblings ...)
(?)
@ 2023-04-15 20:23 ` Patchwork
-1 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2023-04-15 20:23 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 12334 bytes --]
== Series Details ==
Series: drm/i915: CTM stuff mostly (rev5)
URL : https://patchwork.freedesktop.org/series/116345/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13010 -> Patchwork_116345v5
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/index.html
Participating hosts (38 -> 36)
------------------------------
Missing (2): fi-kbl-soraka fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_116345v5:
### IGT changes ###
#### Possible regressions ####
* {igt@kms_color@ctm-signed@pipe-a} (NEW):
- bat-dg2-11: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/bat-dg2-11/igt@kms_color@ctm-signed@pipe-a.html
New tests
---------
New tests have been introduced between CI_DRM_13010 and Patchwork_116345v5:
### New IGT tests (37) ###
* igt@kms_color@ctm-0-25@pipe-a:
- Statuses : 21 pass(s) 10 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-25@pipe-b:
- Statuses : 21 pass(s) 10 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-25@pipe-c:
- Statuses : 21 pass(s) 7 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-25@pipe-d:
- Statuses : 6 pass(s) 2 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-50@pipe-a:
- Statuses : 21 pass(s) 10 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-50@pipe-b:
- Statuses : 21 pass(s) 10 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-50@pipe-c:
- Statuses : 21 pass(s) 7 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-50@pipe-d:
- Statuses : 6 pass(s) 2 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-75@pipe-a:
- Statuses : 22 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-75@pipe-b:
- Statuses : 22 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-75@pipe-c:
- Statuses : 22 pass(s) 6 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-75@pipe-d:
- Statuses : 7 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-blue-to-red@pipe-a:
- Statuses : 22 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-blue-to-red@pipe-b:
- Statuses : 22 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-blue-to-red@pipe-c:
- Statuses : 22 pass(s) 6 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-blue-to-red@pipe-d:
- Statuses : 7 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-green-to-red@pipe-a:
- Statuses : 22 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-green-to-red@pipe-b:
- Statuses : 22 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-green-to-red@pipe-c:
- Statuses : 22 pass(s) 6 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-green-to-red@pipe-d:
- Statuses : 7 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-max@pipe-a:
- Statuses : 22 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-max@pipe-b:
- Statuses : 22 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-max@pipe-c:
- Statuses : 22 pass(s) 6 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-max@pipe-d:
- Statuses : 6 pass(s) 2 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-negative@pipe-a:
- Statuses : 21 pass(s) 10 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-negative@pipe-b:
- Statuses : 21 pass(s) 10 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-negative@pipe-c:
- Statuses : 21 pass(s) 7 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-negative@pipe-d:
- Statuses : 6 pass(s) 2 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-red-to-blue@pipe-a:
- Statuses : 22 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-red-to-blue@pipe-b:
- Statuses : 22 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-red-to-blue@pipe-c:
- Statuses : 22 pass(s) 6 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-red-to-blue@pipe-d:
- Statuses : 7 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-signed:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-signed@pipe-a:
- Statuses : 1 fail(s) 21 pass(s) 9 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-signed@pipe-b:
- Statuses : 21 pass(s) 10 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-signed@pipe-c:
- Statuses : 21 pass(s) 7 skip(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-signed@pipe-d:
- Statuses : 6 pass(s) 2 skip(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_116345v5 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gt_lrc:
- bat-rplp-1: [PASS][2] -> [INCOMPLETE][3] ([i915#7609] / [i915#7913])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/bat-rplp-1/igt@i915_selftest@live@gt_lrc.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/bat-rplp-1/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@migrate:
- bat-dg2-11: [PASS][4] -> [DMESG-WARN][5] ([i915#7699])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/bat-dg2-11/igt@i915_selftest@live@migrate.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/bat-dg2-11/igt@i915_selftest@live@migrate.html
* igt@i915_selftest@live@requests:
- bat-rpls-1: [PASS][6] -> [ABORT][7] ([i915#4983] / [i915#7911])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/bat-rpls-1/igt@i915_selftest@live@requests.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/bat-rpls-1/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-FAIL][8] ([i915#6367] / [i915#7913])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/bat-rpls-2/igt@i915_selftest@live@slpc.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-rpls-2: NOTRUN -> [SKIP][9] ([i915#7828])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/bat-rpls-2/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_color@ctm-0-25:
- bat-atsm-1: NOTRUN -> [SKIP][10] ([i915#6078]) +9 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/bat-atsm-1/igt@kms_color@ctm-0-25.html
* igt@kms_color@ctm-0-25@pipe-b (NEW):
- {bat-kbl-2}: NOTRUN -> [SKIP][11] ([fdo#109271]) +26 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/bat-kbl-2/igt@kms_color@ctm-0-25@pipe-b.html
* igt@kms_color@ctm-0-25@pipe-d (NEW):
- bat-dg2-11: NOTRUN -> [SKIP][12] ([i915#5354]) +15 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/bat-dg2-11/igt@kms_color@ctm-0-25@pipe-d.html
* igt@kms_color@ctm-0-50@pipe-b (NEW):
- fi-bsw-n3050: NOTRUN -> [SKIP][13] ([fdo#109271]) +17 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/fi-bsw-n3050/igt@kms_color@ctm-0-50@pipe-b.html
* igt@kms_color@ctm-0-75@pipe-a (NEW):
- bat-rpls-2: NOTRUN -> [SKIP][14] ([i915#5354]) +17 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/bat-rpls-2/igt@kms_color@ctm-0-75@pipe-a.html
* igt@kms_color@ctm-blue-to-red@pipe-c (NEW):
- fi-bsw-nick: NOTRUN -> [SKIP][15] ([fdo#109271]) +26 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/fi-bsw-nick/igt@kms_color@ctm-blue-to-red@pipe-c.html
- fi-kbl-guc: NOTRUN -> [SKIP][16] ([fdo#109271]) +26 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/fi-kbl-guc/igt@kms_color@ctm-blue-to-red@pipe-c.html
* igt@kms_color@ctm-green-to-red@pipe-c (NEW):
- fi-kbl-8809g: NOTRUN -> [SKIP][17] ([fdo#109271]) +26 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/fi-kbl-8809g/igt@kms_color@ctm-green-to-red@pipe-c.html
* igt@kms_color@ctm-max@pipe-b (NEW):
- bat-dg1-7: NOTRUN -> [SKIP][18] ([i915#5354]) +35 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/bat-dg1-7/igt@kms_color@ctm-max@pipe-b.html
* {igt@kms_color@ctm-signed@pipe-a} (NEW):
- fi-kbl-x1275: NOTRUN -> [SKIP][19] ([fdo#109271]) +26 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/fi-kbl-x1275/igt@kms_color@ctm-signed@pipe-a.html
* {igt@kms_color@ctm-signed@pipe-b} (NEW):
- fi-elk-e7500: NOTRUN -> [SKIP][20] ([fdo#109271]) +19 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/fi-elk-e7500/igt@kms_color@ctm-signed@pipe-b.html
* igt@kms_pipe_crc_basic@read-crc:
- bat-adlp-9: NOTRUN -> [SKIP][21] ([i915#3546]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/bat-adlp-9/igt@kms_pipe_crc_basic@read-crc.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-rpls-2: NOTRUN -> [SKIP][22] ([i915#1845])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/bat-rpls-2/igt@kms_pipe_crc_basic@suspend-read-crc.html
#### Possible fixes ####
* igt@i915_selftest@live@migrate:
- bat-adlp-9: [DMESG-FAIL][23] ([i915#7699]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/bat-adlp-9/igt@i915_selftest@live@migrate.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/bat-adlp-9/igt@i915_selftest@live@migrate.html
* igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][25] ([i915#4983] / [i915#7913] / [i915#7981]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/bat-rpls-2/igt@i915_selftest@live@reset.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/bat-rpls-2/igt@i915_selftest@live@reset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6078]: https://gitlab.freedesktop.org/drm/intel/issues/6078
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#7609]: https://gitlab.freedesktop.org/drm/intel/issues/7609
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
Build changes
-------------
* IGT: IGT_7256 -> IGTPW_8780
* Linux: CI_DRM_13010 -> Patchwork_116345v5
CI-20190529: 20190529
CI_DRM_13010: a3cb6a082228cf82afbc828b6074b53b118144cf @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_8780: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8780/index.html
IGT_7256: 066fa5410180730b85f61e4f3073da9a2055dc49 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116345v5: a3cb6a082228cf82afbc828b6074b53b118144cf @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
d12db96c87c7 drm/i915: Do state check for color management changes
0bcbf5cbe2d8 drm/i915: No 10bit gamma on desktop gen3 parts
c9c0d20df271 drm/i915: Implement CTM property support for VLV
b814b27cecd8 drm/i915: Always enable CGM CSC on CHV
cc8ea7ed3bdb drm/i915: Fix CHV CGM CSC coefficient sign handling
d6fb60e7053f drm/i915: Expose crtc CTM property on ilk/snb
7096d228beef drm/uapi: Document CTM matrix better
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/index.html
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^ permalink raw reply [flat|nested] 43+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: CTM stuff mostly (rev5)
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
` (15 preceding siblings ...)
(?)
@ 2023-04-15 21:33 ` Patchwork
-1 siblings, 0 replies; 43+ messages in thread
From: Patchwork @ 2023-04-15 21:33 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 23840 bytes --]
== Series Details ==
Series: drm/i915: CTM stuff mostly (rev5)
URL : https://patchwork.freedesktop.org/series/116345/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13010_full -> Patchwork_116345v5_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (8 -> 7)
------------------------------
Missing (1): shard-tglu0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_116345v5_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_whisper@basic-contexts-priority-all:
- {shard-rkl}: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/shard-rkl-6/igt@gem_exec_whisper@basic-contexts-priority-all.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-rkl-4/igt@gem_exec_whisper@basic-contexts-priority-all.html
New tests
---------
New tests have been introduced between CI_DRM_13010_full and Patchwork_116345v5_full:
### New IGT tests (53) ###
* igt@kms_color@ctm-0-25@pipe-a:
- Statuses : 6 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-25@pipe-b:
- Statuses : 6 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-25@pipe-c:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-25@pipe-d:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-50@pipe-a:
- Statuses : 6 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-50@pipe-b:
- Statuses : 6 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-50@pipe-c:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-50@pipe-d:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-75@pipe-a:
- Statuses : 5 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-75@pipe-b:
- Statuses : 5 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-75@pipe-c:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-0-75@pipe-d:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-blue-to-red@pipe-a:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-blue-to-red@pipe-b:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-blue-to-red@pipe-c:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-blue-to-red@pipe-d:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-green-to-red@pipe-a:
- Statuses : 6 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-green-to-red@pipe-b:
- Statuses : 6 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-green-to-red@pipe-c:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-green-to-red@pipe-d:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-max@pipe-a:
- Statuses : 5 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-max@pipe-b:
- Statuses : 5 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-max@pipe-c:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-max@pipe-d:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-negative@pipe-a:
- Statuses : 5 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-negative@pipe-b:
- Statuses : 5 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-negative@pipe-c:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-negative@pipe-d:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-red-to-blue@pipe-a:
- Statuses : 5 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-red-to-blue@pipe-b:
- Statuses : 5 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-red-to-blue@pipe-c:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-red-to-blue@pipe-d:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-signed:
- Statuses :
- Exec time: [None] s
* igt@kms_color@ctm-signed@pipe-a:
- Statuses : 6 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-signed@pipe-b:
- Statuses : 6 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-signed@pipe-c:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@kms_color@ctm-signed@pipe-d:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_color@degamma@pipe-a:
- Statuses : 5 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_color@degamma@pipe-b:
- Statuses : 5 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_color@degamma@pipe-c:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@kms_color@degamma@pipe-d:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_color@gamma@pipe-a:
- Statuses : 5 pass(s)
- Exec time: [0.0] s
* igt@kms_color@gamma@pipe-b:
- Statuses : 5 pass(s)
- Exec time: [0.0] s
* igt@kms_color@gamma@pipe-c:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@kms_color@gamma@pipe-d:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_color@legacy-gamma-reset@pipe-a:
- Statuses : 5 pass(s)
- Exec time: [0.0] s
* igt@kms_color@legacy-gamma-reset@pipe-b:
- Statuses : 5 pass(s)
- Exec time: [0.0] s
* igt@kms_color@legacy-gamma-reset@pipe-c:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@kms_color@legacy-gamma-reset@pipe-d:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_color@legacy-gamma@pipe-a:
- Statuses : 5 pass(s)
- Exec time: [0.0] s
* igt@kms_color@legacy-gamma@pipe-b:
- Statuses : 5 pass(s)
- Exec time: [0.0] s
* igt@kms_color@legacy-gamma@pipe-c:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@kms_color@legacy-gamma@pipe-d:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_116345v5_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@hang:
- shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-snb7/igt@gem_ctx_persistence@hang.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][4] -> [FAIL][5] ([i915#2842]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-apl: [PASS][6] -> [FAIL][7] ([i915#2842])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/shard-apl7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-apl6/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-apl: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-apl3/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][9] -> [ABORT][10] ([i915#5566])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/shard-apl1/igt@gen9_exec_parse@allowed-single.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-apl1/igt@gen9_exec_parse@allowed-single.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-apl: [PASS][11] -> [DMESG-FAIL][12] ([i915#5334])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/shard-apl2/igt@i915_selftest@live@gt_heartbeat.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-apl2/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#3886]) +5 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-apl6/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc:
- shard-snb: NOTRUN -> [SKIP][14] ([fdo#109271]) +83 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-snb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-0-25@pipe-c-dp-1:
- shard-apl: NOTRUN -> [SKIP][15] ([fdo#109271]) +103 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-apl1/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-0-25@pipe-c-dp-1.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
- shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#658]) +1 similar issue
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-apl4/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
#### Possible fixes ####
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-tglu}: [FAIL][17] ([i915#6268]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/shard-tglu-9/igt@gem_ctx_exec@basic-nohangcheck.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-tglu-10/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_eio@reset-stress:
- {shard-dg1}: [FAIL][19] ([i915#5784]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/shard-dg1-14/igt@gem_eio@reset-stress.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-dg1-17/igt@gem_eio@reset-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: [FAIL][21] ([i915#2846]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/shard-apl1/igt@gem_exec_fair@basic-deadline.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-apl4/igt@gem_exec_fair@basic-deadline.html
- shard-glk: [FAIL][23] ([i915#2846]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/shard-glk8/igt@gem_exec_fair@basic-deadline.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-glk9/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][25] ([i915#2842]) -> [PASS][26] +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/shard-apl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-apl2/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- {shard-rkl}: [FAIL][27] ([i915#2842]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/shard-rkl-1/igt@gem_exec_fair@basic-none@vecs0.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-rkl-7/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_suspend@basic-s4-devices@smem:
- {shard-tglu}: [ABORT][29] ([i915#7975]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/shard-tglu-10/igt@gem_exec_suspend@basic-s4-devices@smem.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-tglu-3/igt@gem_exec_suspend@basic-s4-devices@smem.html
* igt@i915_pm_dc@dc6-dpms:
- {shard-tglu}: [FAIL][31] ([i915#3989] / [i915#454]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/shard-tglu-3/igt@i915_pm_dc@dc6-dpms.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-tglu-2/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_dc@dc9-dpms:
- shard-apl: [SKIP][33] ([fdo#109271]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/shard-apl3/igt@i915_pm_dc@dc9-dpms.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-apl6/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- {shard-rkl}: [SKIP][35] ([i915#1397]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/shard-rkl-3/igt@i915_pm_rpm@modeset-lpsp-stress.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-rkl-7/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@kms_color@invalid-ctm-matrix-sizes@pipe-a:
- shard-snb: [SKIP][37] ([fdo#109271]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/shard-snb2/igt@kms_color@invalid-ctm-matrix-sizes@pipe-a.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-snb7/igt@kms_color@invalid-ctm-matrix-sizes@pipe-a.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [FAIL][39] ([i915#72]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-glk4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@forked-move@pipe-b:
- {shard-rkl}: [INCOMPLETE][41] ([i915#8011]) -> [PASS][42] +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/shard-rkl-7/igt@kms_cursor_legacy@forked-move@pipe-b.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-rkl-1/igt@kms_cursor_legacy@forked-move@pipe-b.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [ABORT][43] ([i915#180]) -> [PASS][44] +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/shard-apl2/igt@kms_flip@flip-vs-suspend@a-dp1.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-apl6/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_flip@flip-vs-suspend@a-vga1:
- shard-snb: [INCOMPLETE][45] ([i915#4839]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13010/shard-snb5/igt@kms_flip@flip-vs-suspend@a-vga1.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/shard-snb2/igt@kms_flip@flip-vs-suspend@a-vga1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4839]: https://gitlab.freedesktop.org/drm/intel/issues/4839
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7178]: https://gitlab.freedesktop.org/drm/intel/issues/7178
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8150]: https://gitlab.freedesktop.org/drm/intel/issues/8150
[i915#8155]: https://gitlab.freedesktop.org/drm/intel/issues/8155
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8308]: https://gitlab.freedesktop.org/drm/intel/issues/8308
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
Build changes
-------------
* IGT: IGT_7256 -> IGTPW_8780
* Linux: CI_DRM_13010 -> Patchwork_116345v5
CI-20190529: 20190529
CI_DRM_13010: a3cb6a082228cf82afbc828b6074b53b118144cf @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_8780: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8780/index.html
IGT_7256: 066fa5410180730b85f61e4f3073da9a2055dc49 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116345v5: a3cb6a082228cf82afbc828b6074b53b118144cf @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116345v5/index.html
[-- Attachment #2: Type: text/html, Size: 20291 bytes --]
^ permalink raw reply [flat|nested] 43+ messages in thread
* RE: [Intel-gfx] [PATCH v2 2/7] drm/i915: Expose crtc CTM property on ilk/snb
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
@ 2023-05-25 20:13 ` Shankar, Uma
-1 siblings, 0 replies; 43+ messages in thread
From: Shankar, Uma @ 2023-05-25 20:13 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: dri-devel
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Thursday, April 13, 2023 10:19 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 2/7] drm/i915: Expose crtc CTM property on ilk/snb
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The ilk/snb code is internally fully capable of handling the CTM property, so expose
> it.
>
> Note that we still choose not to expose DEGAMMA_LUT though.
> The hardware is capable if degamma or gamma, but not both similtanously due to
Nit: Typo in "simultaneously"
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> lack of the split gamma mode. Exposing both LUTs might encourage userspace to try
> enabling both at the same time.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 07f1afe1d406..4fc16cac052d 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -3473,7 +3473,7 @@ void intel_color_crtc_init(struct intel_crtc *crtc)
>
> gamma_lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
> degamma_lut_size = INTEL_INFO(i915)->display.color.degamma_lut_size;
> - has_ctm = degamma_lut_size != 0;
> + has_ctm = DISPLAY_VER(i915) >= 5 && !IS_VALLEYVIEW(i915);
>
> /*
> * "DPALETTE_A: NOTE: The 8-bit (non-10-bit) mode is the
> --
> 2.39.2
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/7] drm/i915: Expose crtc CTM property on ilk/snb
@ 2023-05-25 20:13 ` Shankar, Uma
0 siblings, 0 replies; 43+ messages in thread
From: Shankar, Uma @ 2023-05-25 20:13 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: dri-devel
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Thursday, April 13, 2023 10:19 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 2/7] drm/i915: Expose crtc CTM property on ilk/snb
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The ilk/snb code is internally fully capable of handling the CTM property, so expose
> it.
>
> Note that we still choose not to expose DEGAMMA_LUT though.
> The hardware is capable if degamma or gamma, but not both similtanously due to
Nit: Typo in "simultaneously"
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> lack of the split gamma mode. Exposing both LUTs might encourage userspace to try
> enabling both at the same time.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 07f1afe1d406..4fc16cac052d 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -3473,7 +3473,7 @@ void intel_color_crtc_init(struct intel_crtc *crtc)
>
> gamma_lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
> degamma_lut_size = INTEL_INFO(i915)->display.color.degamma_lut_size;
> - has_ctm = degamma_lut_size != 0;
> + has_ctm = DISPLAY_VER(i915) >= 5 && !IS_VALLEYVIEW(i915);
>
> /*
> * "DPALETTE_A: NOTE: The 8-bit (non-10-bit) mode is the
> --
> 2.39.2
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
@ 2023-05-25 20:55 ` Shankar, Uma
-1 siblings, 0 replies; 43+ messages in thread
From: Shankar, Uma @ 2023-05-25 20:55 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: dri-devel
> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Thursday, April 13, 2023 10:19 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org
> Subject: [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The CHV CGM CSC coefficients are in s4.12 two's complement format. Fix the CTM-
> >CGM conversion to handle that correctly instead of pretending that the hw
> coefficients are also in some sign-magnitude format.
Spec is slightly confusing when it says:
"CGM CSC : Input pixels to the CGM CSC are 14 bits. (u.14 format). Coefficients are 16 bits (s3.12)."
Also here:
"Programmable parameters :
c0[15 :0], c1[15 :0], c2[15 :0], c3[15 :0], c4[15 :0], c5[15 :0], c6[15 :0], c7[15 :0], c8[15 :0] ; // signed matrix coefficients (s3.12)"
But the coefficients are 16bits, can you help understand how were you able to crack this 😊
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 46 ++++++++++++++--------
> 1 file changed, 29 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 4fc16cac052d..63141f4ed372 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -568,29 +568,41 @@ static void icl_load_csc_matrix(const struct
> intel_crtc_state *crtc_state)
> icl_update_output_csc(crtc, &crtc_state->output_csc); }
>
> +static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int
> +frac_bits) {
> + s64 c = CTM_COEFF_ABS(coeff);
> +
> + /* leave an extra bit for rounding */
> + c >>= 32 - frac_bits - 1;
> +
> + /* round and drop the extra bit */
> + c = (c + 1) >> 1;
> +
> + if (CTM_COEFF_NEGATIVE(coeff))
> + c = -c;
> +
> + c = clamp(c, -(s64)BIT(int_bits + frac_bits - 1),
> + (s64)(BIT(int_bits + frac_bits - 1) - 1));
> +
> + return c & (BIT(int_bits + frac_bits) - 1); }
> +
> +/*
> + * CHV Color Gamut Mapping (CGM) CSC
> + * |r| | c0 c1 c2 | |r|
> + * |g| = | c3 c4 c5 | x |g|
> + * |b| | c6 c7 c8 | |b|
> + *
> + * Coefficients are two's complement s4.12.
> + */
> static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
> struct intel_csc_matrix *csc)
> {
> const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
> int i;
>
> - for (i = 0; i < 9; i++) {
> - u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
> -
> - /* Round coefficient. */
> - abs_coeff += 1 << (32 - 13);
> - /* Clamp to hardware limits. */
> - abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
> -
> - csc->coeff[i] = 0;
> -
> - /* Write coefficients in S3.12 format. */
> - if (ctm->matrix[i] & (1ULL << 63))
> - csc->coeff[i] |= 1 << 15;
> -
> - csc->coeff[i] |= ((abs_coeff >> 32) & 7) << 12;
> - csc->coeff[i] |= (abs_coeff >> 20) & 0xfff;
> - }
> + for (i = 0; i < 9; i++)
> + csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12);
> }
>
> static void chv_load_cgm_csc(struct intel_crtc *crtc,
> --
> 2.39.2
^ permalink raw reply [flat|nested] 43+ messages in thread
* RE: [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling
@ 2023-05-25 20:55 ` Shankar, Uma
0 siblings, 0 replies; 43+ messages in thread
From: Shankar, Uma @ 2023-05-25 20:55 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: dri-devel
> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Thursday, April 13, 2023 10:19 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org
> Subject: [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The CHV CGM CSC coefficients are in s4.12 two's complement format. Fix the CTM-
> >CGM conversion to handle that correctly instead of pretending that the hw
> coefficients are also in some sign-magnitude format.
Spec is slightly confusing when it says:
"CGM CSC : Input pixels to the CGM CSC are 14 bits. (u.14 format). Coefficients are 16 bits (s3.12)."
Also here:
"Programmable parameters :
c0[15 :0], c1[15 :0], c2[15 :0], c3[15 :0], c4[15 :0], c5[15 :0], c6[15 :0], c7[15 :0], c8[15 :0] ; // signed matrix coefficients (s3.12)"
But the coefficients are 16bits, can you help understand how were you able to crack this 😊
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 46 ++++++++++++++--------
> 1 file changed, 29 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 4fc16cac052d..63141f4ed372 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -568,29 +568,41 @@ static void icl_load_csc_matrix(const struct
> intel_crtc_state *crtc_state)
> icl_update_output_csc(crtc, &crtc_state->output_csc); }
>
> +static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int
> +frac_bits) {
> + s64 c = CTM_COEFF_ABS(coeff);
> +
> + /* leave an extra bit for rounding */
> + c >>= 32 - frac_bits - 1;
> +
> + /* round and drop the extra bit */
> + c = (c + 1) >> 1;
> +
> + if (CTM_COEFF_NEGATIVE(coeff))
> + c = -c;
> +
> + c = clamp(c, -(s64)BIT(int_bits + frac_bits - 1),
> + (s64)(BIT(int_bits + frac_bits - 1) - 1));
> +
> + return c & (BIT(int_bits + frac_bits) - 1); }
> +
> +/*
> + * CHV Color Gamut Mapping (CGM) CSC
> + * |r| | c0 c1 c2 | |r|
> + * |g| = | c3 c4 c5 | x |g|
> + * |b| | c6 c7 c8 | |b|
> + *
> + * Coefficients are two's complement s4.12.
> + */
> static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
> struct intel_csc_matrix *csc)
> {
> const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
> int i;
>
> - for (i = 0; i < 9; i++) {
> - u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
> -
> - /* Round coefficient. */
> - abs_coeff += 1 << (32 - 13);
> - /* Clamp to hardware limits. */
> - abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
> -
> - csc->coeff[i] = 0;
> -
> - /* Write coefficients in S3.12 format. */
> - if (ctm->matrix[i] & (1ULL << 63))
> - csc->coeff[i] |= 1 << 15;
> -
> - csc->coeff[i] |= ((abs_coeff >> 32) & 7) << 12;
> - csc->coeff[i] |= (abs_coeff >> 20) & 0xfff;
> - }
> + for (i = 0; i < 9; i++)
> + csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12);
> }
>
> static void chv_load_cgm_csc(struct intel_crtc *crtc,
> --
> 2.39.2
^ permalink raw reply [flat|nested] 43+ messages in thread
* RE: [Intel-gfx] [PATCH v2 4/7] drm/i915: Always enable CGM CSC on CHV
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
@ 2023-05-25 20:58 ` Shankar, Uma
-1 siblings, 0 replies; 43+ messages in thread
From: Shankar, Uma @ 2023-05-25 20:58 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: dri-devel
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Thursday, April 13, 2023 10:19 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 4/7] drm/i915: Always enable CGM CSC on CHV
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> On CHV toggling the CGM CSC on/off while the pipe is running leads to underruns.
> Looks like we'd have to do the toggling strictly inside the start_of_vblank-
> frame_start window to avoid this, but that window is less than a scanline so there's
> no way we can guarantee hitting it.
>
> As a workaround let's just leave the CGM CSC permanently enabled.
> Fortunately the CGM gamma/degamma units don't seem to suffer from this malady.
>
> I also tried turning off CGM unit clock gating, but that did not help.
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 21 +++++++++++++++++++--
> 1 file changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 63141f4ed372..7a705e7d8776 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -605,6 +605,16 @@ static void chv_cgm_csc_convert_ctm(const struct
> intel_crtc_state *crtc_state,
> csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12); }
>
> +#define CHV_CGM_CSC_COEFF_1_0 (1 << 12)
> +
> +static const struct intel_csc_matrix chv_cgm_csc_matrix_identity = {
> + .coeff = {
> + CHV_CGM_CSC_COEFF_1_0, 0, 0,
> + 0, CHV_CGM_CSC_COEFF_1_0, 0,
> + 0, 0, CHV_CGM_CSC_COEFF_1_0,
> + },
> +};
> +
> static void chv_load_cgm_csc(struct intel_crtc *crtc,
> const struct intel_csc_matrix *csc) { @@ -667,9 +677,9
> @@ static void chv_assign_csc(struct intel_crtc_state *crtc_state)
>
> chv_cgm_csc_convert_ctm(crtc_state, &crtc_state->csc);
> } else {
> - drm_WARN_ON(&i915->drm, (crtc_state->cgm_mode &
> CGM_PIPE_MODE_CSC) != 0);
> + drm_WARN_ON(&i915->drm, (crtc_state->cgm_mode &
> CGM_PIPE_MODE_CSC) ==
> +0);
>
> - intel_csc_clear(&crtc_state->csc);
> + crtc_state->csc = chv_cgm_csc_matrix_identity;
> }
> }
>
> @@ -2033,6 +2043,13 @@ static u32 chv_cgm_mode(const struct intel_crtc_state
> *crtc_state)
> !lut_is_legacy(crtc_state->hw.gamma_lut))
> cgm_mode |= CGM_PIPE_MODE_GAMMA;
>
> + /*
> + * Toggling the CGM CSC on/off outside of the tiny window
> + * between start of vblank and frame start causes underruns.
> + * Always enable the CGM CSC as a workaround.
> + */
> + cgm_mode |= CGM_PIPE_MODE_CSC;
> +
> return cgm_mode;
> }
>
> --
> 2.39.2
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/7] drm/i915: Always enable CGM CSC on CHV
@ 2023-05-25 20:58 ` Shankar, Uma
0 siblings, 0 replies; 43+ messages in thread
From: Shankar, Uma @ 2023-05-25 20:58 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: dri-devel
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Thursday, April 13, 2023 10:19 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 4/7] drm/i915: Always enable CGM CSC on CHV
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> On CHV toggling the CGM CSC on/off while the pipe is running leads to underruns.
> Looks like we'd have to do the toggling strictly inside the start_of_vblank-
> frame_start window to avoid this, but that window is less than a scanline so there's
> no way we can guarantee hitting it.
>
> As a workaround let's just leave the CGM CSC permanently enabled.
> Fortunately the CGM gamma/degamma units don't seem to suffer from this malady.
>
> I also tried turning off CGM unit clock gating, but that did not help.
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 21 +++++++++++++++++++--
> 1 file changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 63141f4ed372..7a705e7d8776 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -605,6 +605,16 @@ static void chv_cgm_csc_convert_ctm(const struct
> intel_crtc_state *crtc_state,
> csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12); }
>
> +#define CHV_CGM_CSC_COEFF_1_0 (1 << 12)
> +
> +static const struct intel_csc_matrix chv_cgm_csc_matrix_identity = {
> + .coeff = {
> + CHV_CGM_CSC_COEFF_1_0, 0, 0,
> + 0, CHV_CGM_CSC_COEFF_1_0, 0,
> + 0, 0, CHV_CGM_CSC_COEFF_1_0,
> + },
> +};
> +
> static void chv_load_cgm_csc(struct intel_crtc *crtc,
> const struct intel_csc_matrix *csc) { @@ -667,9 +677,9
> @@ static void chv_assign_csc(struct intel_crtc_state *crtc_state)
>
> chv_cgm_csc_convert_ctm(crtc_state, &crtc_state->csc);
> } else {
> - drm_WARN_ON(&i915->drm, (crtc_state->cgm_mode &
> CGM_PIPE_MODE_CSC) != 0);
> + drm_WARN_ON(&i915->drm, (crtc_state->cgm_mode &
> CGM_PIPE_MODE_CSC) ==
> +0);
>
> - intel_csc_clear(&crtc_state->csc);
> + crtc_state->csc = chv_cgm_csc_matrix_identity;
> }
> }
>
> @@ -2033,6 +2043,13 @@ static u32 chv_cgm_mode(const struct intel_crtc_state
> *crtc_state)
> !lut_is_legacy(crtc_state->hw.gamma_lut))
> cgm_mode |= CGM_PIPE_MODE_GAMMA;
>
> + /*
> + * Toggling the CGM CSC on/off outside of the tiny window
> + * between start of vblank and frame start causes underruns.
> + * Always enable the CGM CSC as a workaround.
> + */
> + cgm_mode |= CGM_PIPE_MODE_CSC;
> +
> return cgm_mode;
> }
>
> --
> 2.39.2
^ permalink raw reply [flat|nested] 43+ messages in thread
* RE: [Intel-gfx] [PATCH v2 5/7] drm/i915: Implement CTM property support for VLV
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
@ 2023-05-25 21:23 ` Shankar, Uma
-1 siblings, 0 replies; 43+ messages in thread
From: Shankar, Uma @ 2023-05-25 21:23 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: dri-devel
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Thursday, April 13, 2023 10:19 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 5/7] drm/i915: Implement CTM property support for
> VLV
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> VLV has a so called "wide gamut color correction" unit (WGC).
> What it is is a 3x3 matrix similar to the later CHV CGM CSC, which less
> precisions/range. In fact CHV also has the WGC but using it there doesn't reall make
> sense when you have the superior CGM CSC around.
>
> Hook up the necessary stuff to expose the WGC as the CTM crtc property.
>
> One additional crazy idea that came to mind would be to use the WGC as an output
> CSC on CHV for YCbCr output. But it would be incompatible with the legacy LUT
> usage. In fact since the WGC lacks post-offsets we'd probably have to use the legacy
> LUT to do that final part of the RGB->YCbCr conversion. Sounds doable, but perhaps
> not worth the hassle.
Yeah WGC on CHV was just kept for safety against any hw issue, with plan to drop in future platforms.
Exposing it for VLV is nice.
Changes look good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 170 +++++++++++++++++-
> .../drm/i915/display/intel_crtc_state_dump.c | 6 +-
> drivers/gpu/drm/i915/display/intel_display.c | 8 +
> .../drm/i915/display/intel_display_types.h | 3 +
> drivers/gpu/drm/i915/i915_reg.h | 15 ++
> 5 files changed, 198 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 7a705e7d8776..e36d8c248b84 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -587,6 +587,98 @@ static u16 ctm_to_twos_complement(u64 coeff, int
> int_bits, int frac_bits)
> return c & (BIT(int_bits + frac_bits) - 1); }
>
> +/*
> + * VLV/CHV Wide Gamut Color Correction (WGC) CSC
> + * |r| | c0 c1 c2 | |r|
> + * |g| = | c3 c4 c5 | x |g|
> + * |b| | c6 c7 c8 | |b|
> + *
> + * Coefficients are two's complement s2.10.
> + */
> +static void vlv_wgc_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
> + struct intel_csc_matrix *csc)
> +{
> + const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
> + int i;
> +
> + for (i = 0; i < 9; i++)
> + csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 2, 10); }
> +
> +static void vlv_load_wgc_csc(struct intel_crtc *crtc,
> + const struct intel_csc_matrix *csc) {
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> +
> + intel_de_write_fw(dev_priv, PIPE_WGC_C01_C00(pipe),
> + csc->coeff[1] << 16 | csc->coeff[0]);
> + intel_de_write_fw(dev_priv, PIPE_WGC_C02(pipe),
> + csc->coeff[2]);
> +
> + intel_de_write_fw(dev_priv, PIPE_WGC_C11_C10(pipe),
> + csc->coeff[4] << 16 | csc->coeff[3]);
> + intel_de_write_fw(dev_priv, PIPE_WGC_C12(pipe),
> + csc->coeff[5]);
> +
> + intel_de_write_fw(dev_priv, PIPE_WGC_C21_C20(pipe),
> + csc->coeff[7] << 16 | csc->coeff[6]);
> + intel_de_write_fw(dev_priv, PIPE_WGC_C22(pipe),
> + csc->coeff[8]);
> +}
> +
> +static void vlv_read_wgc_csc(struct intel_crtc *crtc,
> + struct intel_csc_matrix *csc)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> + u32 tmp;
> +
> + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C01_C00(pipe));
> + csc->coeff[0] = tmp & 0xffff;
> + csc->coeff[1] = tmp >> 16;
> +
> + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C02(pipe));
> + csc->coeff[2] = tmp & 0xffff;
> +
> + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C11_C10(pipe));
> + csc->coeff[3] = tmp & 0xffff;
> + csc->coeff[4] = tmp >> 16;
> +
> + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C12(pipe));
> + csc->coeff[5] = tmp & 0xffff;
> +
> + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C21_C20(pipe));
> + csc->coeff[6] = tmp & 0xffff;
> + csc->coeff[7] = tmp >> 16;
> +
> + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C22(pipe));
> + csc->coeff[8] = tmp & 0xffff;
> +}
> +
> +static void vlv_read_csc(struct intel_crtc_state *crtc_state) {
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +
> + if (crtc_state->wgc_enable)
> + vlv_read_wgc_csc(crtc, &crtc_state->csc); }
> +
> +static void vlv_assign_csc(struct intel_crtc_state *crtc_state) {
> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> +
> + if (crtc_state->hw.ctm) {
> + drm_WARN_ON(&i915->drm, !crtc_state->wgc_enable);
> +
> + vlv_wgc_csc_convert_ctm(crtc_state, &crtc_state->csc);
> + } else {
> + drm_WARN_ON(&i915->drm, crtc_state->wgc_enable);
> +
> + intel_csc_clear(&crtc_state->csc);
> + }
> +}
> +
> /*
> * CHV Color Gamut Mapping (CGM) CSC
> * |r| | c0 c1 c2 | |r|
> @@ -672,6 +764,8 @@ static void chv_assign_csc(struct intel_crtc_state
> *crtc_state) {
> struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>
> + drm_WARN_ON(&i915->drm, crtc_state->wgc_enable);
> +
> if (crtc_state->hw.ctm) {
> drm_WARN_ON(&i915->drm, (crtc_state->cgm_mode &
> CGM_PIPE_MODE_CSC) == 0);
>
> @@ -1574,6 +1668,16 @@ static void icl_load_luts(const struct intel_crtc_state
> *crtc_state)
> }
> }
>
> +static void vlv_load_luts(const struct intel_crtc_state *crtc_state) {
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +
> + if (crtc_state->wgc_enable)
> + vlv_load_wgc_csc(crtc, &crtc_state->csc);
> +
> + i965_load_luts(crtc_state);
> +}
> +
> static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color) {
> return REG_FIELD_PREP(CGM_PIPE_DEGAMMA_GREEN_LDW_MASK,
> drm_color_lut_extract(color->green, 14)) | @@ -1728,6 +1832,18 @@ static bool
> intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state
> !old_crtc_state->pre_csc_lut;
> }
>
> +static bool vlv_can_preload_luts(const struct intel_crtc_state
> +*new_crtc_state) {
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> + struct intel_atomic_state *state =
> + to_intel_atomic_state(new_crtc_state->uapi.state);
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> +
> + return !old_crtc_state->wgc_enable &&
> + !old_crtc_state->post_csc_lut;
> +}
> +
> static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state) {
> struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> @@ -1744,7 +1860,7 @@ static bool chv_can_preload_luts(const struct
> intel_crtc_state *new_crtc_state)
> if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode)
> return false;
>
> - return !old_crtc_state->post_csc_lut;
> + return vlv_can_preload_luts(new_crtc_state);
> }
>
> int intel_color_check(struct intel_crtc_state *crtc_state) @@ -2031,6 +2147,39 @@
> static int i9xx_color_check(struct intel_crtc_state *crtc_state)
> return 0;
> }
>
> +/*
> + * VLV color pipeline:
> + * u0.10 -> WGC csc -> u0.10 -> pipe gamma -> u0.10 */ static int
> +vlv_color_check(struct intel_crtc_state *crtc_state) {
> + int ret;
> +
> + ret = check_luts(crtc_state);
> + if (ret)
> + return ret;
> +
> + crtc_state->gamma_enable =
> + crtc_state->hw.gamma_lut &&
> + !crtc_state->c8_planes;
> +
> + crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);
> +
> + crtc_state->wgc_enable = crtc_state->hw.ctm;
> +
> + ret = intel_color_add_affected_planes(crtc_state);
> + if (ret)
> + return ret;
> +
> + intel_assign_luts(crtc_state);
> +
> + vlv_assign_csc(crtc_state);
> +
> + crtc_state->preload_luts = vlv_can_preload_luts(crtc_state);
> +
> + return 0;
> +}
> +
> static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state) {
> u32 cgm_mode = 0;
> @@ -2081,6 +2230,12 @@ static int chv_color_check(struct intel_crtc_state
> *crtc_state)
>
> crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
>
> + /*
> + * We always bypass the WGC CSC and use the CGM CSC
> + * instead since it has degamma and better precision.
> + */
> + crtc_state->wgc_enable = false;
> +
> ret = intel_color_add_affected_planes(crtc_state);
> if (ret)
> return ret;
> @@ -3395,6 +3550,15 @@ static const struct intel_color_funcs chv_color_funcs = {
> .read_csc = chv_read_csc,
> };
>
> +static const struct intel_color_funcs vlv_color_funcs = {
> + .color_check = vlv_color_check,
> + .color_commit_arm = i9xx_color_commit_arm,
> + .load_luts = vlv_load_luts,
> + .read_luts = i965_read_luts,
> + .lut_equal = i965_lut_equal,
> + .read_csc = vlv_read_csc,
> +};
> +
> static const struct intel_color_funcs i965_color_funcs = {
> .color_check = i9xx_color_check,
> .color_commit_arm = i9xx_color_commit_arm, @@ -3502,7 +3666,7 @@
> void intel_color_crtc_init(struct intel_crtc *crtc)
>
> gamma_lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
> degamma_lut_size = INTEL_INFO(i915)->display.color.degamma_lut_size;
> - has_ctm = DISPLAY_VER(i915) >= 5 && !IS_VALLEYVIEW(i915);
> + has_ctm = DISPLAY_VER(i915) >= 5;
>
> /*
> * "DPALETTE_A: NOTE: The 8-bit (non-10-bit) mode is the @@ -3540,6
> +3704,8 @@ void intel_color_init_hooks(struct drm_i915_private *i915)
> if (HAS_GMCH(i915)) {
> if (IS_CHERRYVIEW(i915))
> i915->display.funcs.color = &chv_color_funcs;
> + else if (IS_VALLEYVIEW(i915))
> + i915->display.funcs.color = &vlv_color_funcs;
> else if (DISPLAY_VER(i915) >= 4)
> i915->display.funcs.color = &i965_color_funcs;
> else
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index 0cdcaa49656f..dd0895b24682 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -184,7 +184,7 @@ ilk_dump_csc(struct drm_i915_private *i915, const char
> *name, }
>
> static void
> -chv_dump_csc(struct drm_i915_private *i915, const char *name,
> +vlv_dump_csc(struct drm_i915_private *i915, const char *name,
> const struct intel_csc_matrix *csc) {
> int i;
> @@ -370,7 +370,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state
> *pipe_config,
> if (!HAS_GMCH(i915))
> ilk_dump_csc(i915, "pipe csc", &pipe_config->csc);
> else if (IS_CHERRYVIEW(i915))
> - chv_dump_csc(i915, "cgm csc", &pipe_config->csc);
> + vlv_dump_csc(i915, "cgm csc", &pipe_config->csc);
> + else if (IS_VALLEYVIEW(i915))
> + vlv_dump_csc(i915, "wgc csc", &pipe_config->csc);
>
> dump_planes:
> if (!state)
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 0334565cec82..962bbd13a5bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2931,6 +2931,9 @@ void i9xx_set_pipeconf(const struct intel_crtc_state
> *crtc_state)
>
> val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
>
> + if (crtc_state->wgc_enable)
> + val |= TRANSCONF_WGC_ENABLE;
> +
> val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay -
> 1);
>
> intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); @@ -3123,6
> +3126,10 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>
> pipe_config->framestart_delay =
> REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
>
> + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> + (tmp & TRANSCONF_WGC_ENABLE))
> + pipe_config->wgc_enable = true;
> +
> if (IS_CHERRYVIEW(dev_priv))
> pipe_config->cgm_mode = intel_de_read(dev_priv,
> CGM_PIPE_MODE(crtc->pipe));
> @@ -5711,6 +5718,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
> *current_config,
> PIPE_CONF_CHECK_X(csc_mode);
> PIPE_CONF_CHECK_BOOL(gamma_enable);
> PIPE_CONF_CHECK_BOOL(csc_enable);
> + PIPE_CONF_CHECK_BOOL(wgc_enable);
>
> PIPE_CONF_CHECK_I(linetime);
> PIPE_CONF_CHECK_I(ips_linetime);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b28c8dc48e24..5357664cdf55 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1295,6 +1295,9 @@ struct intel_crtc_state {
> /* enable pipe csc? */
> bool csc_enable;
>
> + /* enable vlv/chv wgc csc? */
> + bool wgc_enable;
> +
> /* big joiner pipe bitmask */
> u8 bigjoiner_pipes;
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e9dd19cc66a2..e1a6ba6839b6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2550,6 +2550,7 @@
> #define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /*
> ilk/snb/ivb */
> #define TRANSCONF_MSA_TIMING_DELAY(x)
> REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x))
> #define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16)
> +#define TRANSCONF_WGC_ENABLE REG_BIT(15) /* vlv/chv
> only */
> #define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14)
> #define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13)
> #define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /*
> ilk-ivb */
> @@ -6382,6 +6383,20 @@ enum skl_power_gate {
> (index) * 4,
> _PLANE_CSC_POSTOFF_HI_2(pipe) + \
> (index) * 4)
>
> +#define _PIPE_A_WGC_C01_C00 0x600B0 /* s2.10 */
> +#define _PIPE_A_WGC_C02 0x600B4 /* s2.10 */
> +#define _PIPE_A_WGC_C11_C10 0x600B8 /* s2.10 */
> +#define _PIPE_A_WGC_C12 0x600BC /* s2.10 */
> +#define _PIPE_A_WGC_C21_C20 0x600C0 /* s2.10 */
> +#define _PIPE_A_WGC_C22 0x600C4 /* s2.10 */
> +
> +#define PIPE_WGC_C01_C00(pipe) _MMIO_TRANS2(pipe,
> _PIPE_A_WGC_C01_C00)
> +#define PIPE_WGC_C02(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C02)
> +#define PIPE_WGC_C11_C10(pipe) _MMIO_TRANS2(pipe,
> _PIPE_A_WGC_C11_C10)
> +#define PIPE_WGC_C12(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C12)
> +#define PIPE_WGC_C21_C20(pipe) _MMIO_TRANS2(pipe,
> _PIPE_A_WGC_C21_C20)
> +#define PIPE_WGC_C22(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C22)
> +
> /* pipe CSC & degamma/gamma LUTs on CHV */
> #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
> #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
> --
> 2.39.2
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] [PATCH v2 5/7] drm/i915: Implement CTM property support for VLV
@ 2023-05-25 21:23 ` Shankar, Uma
0 siblings, 0 replies; 43+ messages in thread
From: Shankar, Uma @ 2023-05-25 21:23 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: dri-devel
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Thursday, April 13, 2023 10:19 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 5/7] drm/i915: Implement CTM property support for
> VLV
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> VLV has a so called "wide gamut color correction" unit (WGC).
> What it is is a 3x3 matrix similar to the later CHV CGM CSC, which less
> precisions/range. In fact CHV also has the WGC but using it there doesn't reall make
> sense when you have the superior CGM CSC around.
>
> Hook up the necessary stuff to expose the WGC as the CTM crtc property.
>
> One additional crazy idea that came to mind would be to use the WGC as an output
> CSC on CHV for YCbCr output. But it would be incompatible with the legacy LUT
> usage. In fact since the WGC lacks post-offsets we'd probably have to use the legacy
> LUT to do that final part of the RGB->YCbCr conversion. Sounds doable, but perhaps
> not worth the hassle.
Yeah WGC on CHV was just kept for safety against any hw issue, with plan to drop in future platforms.
Exposing it for VLV is nice.
Changes look good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 170 +++++++++++++++++-
> .../drm/i915/display/intel_crtc_state_dump.c | 6 +-
> drivers/gpu/drm/i915/display/intel_display.c | 8 +
> .../drm/i915/display/intel_display_types.h | 3 +
> drivers/gpu/drm/i915/i915_reg.h | 15 ++
> 5 files changed, 198 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 7a705e7d8776..e36d8c248b84 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -587,6 +587,98 @@ static u16 ctm_to_twos_complement(u64 coeff, int
> int_bits, int frac_bits)
> return c & (BIT(int_bits + frac_bits) - 1); }
>
> +/*
> + * VLV/CHV Wide Gamut Color Correction (WGC) CSC
> + * |r| | c0 c1 c2 | |r|
> + * |g| = | c3 c4 c5 | x |g|
> + * |b| | c6 c7 c8 | |b|
> + *
> + * Coefficients are two's complement s2.10.
> + */
> +static void vlv_wgc_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
> + struct intel_csc_matrix *csc)
> +{
> + const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
> + int i;
> +
> + for (i = 0; i < 9; i++)
> + csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 2, 10); }
> +
> +static void vlv_load_wgc_csc(struct intel_crtc *crtc,
> + const struct intel_csc_matrix *csc) {
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> +
> + intel_de_write_fw(dev_priv, PIPE_WGC_C01_C00(pipe),
> + csc->coeff[1] << 16 | csc->coeff[0]);
> + intel_de_write_fw(dev_priv, PIPE_WGC_C02(pipe),
> + csc->coeff[2]);
> +
> + intel_de_write_fw(dev_priv, PIPE_WGC_C11_C10(pipe),
> + csc->coeff[4] << 16 | csc->coeff[3]);
> + intel_de_write_fw(dev_priv, PIPE_WGC_C12(pipe),
> + csc->coeff[5]);
> +
> + intel_de_write_fw(dev_priv, PIPE_WGC_C21_C20(pipe),
> + csc->coeff[7] << 16 | csc->coeff[6]);
> + intel_de_write_fw(dev_priv, PIPE_WGC_C22(pipe),
> + csc->coeff[8]);
> +}
> +
> +static void vlv_read_wgc_csc(struct intel_crtc *crtc,
> + struct intel_csc_matrix *csc)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> + u32 tmp;
> +
> + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C01_C00(pipe));
> + csc->coeff[0] = tmp & 0xffff;
> + csc->coeff[1] = tmp >> 16;
> +
> + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C02(pipe));
> + csc->coeff[2] = tmp & 0xffff;
> +
> + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C11_C10(pipe));
> + csc->coeff[3] = tmp & 0xffff;
> + csc->coeff[4] = tmp >> 16;
> +
> + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C12(pipe));
> + csc->coeff[5] = tmp & 0xffff;
> +
> + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C21_C20(pipe));
> + csc->coeff[6] = tmp & 0xffff;
> + csc->coeff[7] = tmp >> 16;
> +
> + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C22(pipe));
> + csc->coeff[8] = tmp & 0xffff;
> +}
> +
> +static void vlv_read_csc(struct intel_crtc_state *crtc_state) {
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +
> + if (crtc_state->wgc_enable)
> + vlv_read_wgc_csc(crtc, &crtc_state->csc); }
> +
> +static void vlv_assign_csc(struct intel_crtc_state *crtc_state) {
> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> +
> + if (crtc_state->hw.ctm) {
> + drm_WARN_ON(&i915->drm, !crtc_state->wgc_enable);
> +
> + vlv_wgc_csc_convert_ctm(crtc_state, &crtc_state->csc);
> + } else {
> + drm_WARN_ON(&i915->drm, crtc_state->wgc_enable);
> +
> + intel_csc_clear(&crtc_state->csc);
> + }
> +}
> +
> /*
> * CHV Color Gamut Mapping (CGM) CSC
> * |r| | c0 c1 c2 | |r|
> @@ -672,6 +764,8 @@ static void chv_assign_csc(struct intel_crtc_state
> *crtc_state) {
> struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>
> + drm_WARN_ON(&i915->drm, crtc_state->wgc_enable);
> +
> if (crtc_state->hw.ctm) {
> drm_WARN_ON(&i915->drm, (crtc_state->cgm_mode &
> CGM_PIPE_MODE_CSC) == 0);
>
> @@ -1574,6 +1668,16 @@ static void icl_load_luts(const struct intel_crtc_state
> *crtc_state)
> }
> }
>
> +static void vlv_load_luts(const struct intel_crtc_state *crtc_state) {
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +
> + if (crtc_state->wgc_enable)
> + vlv_load_wgc_csc(crtc, &crtc_state->csc);
> +
> + i965_load_luts(crtc_state);
> +}
> +
> static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color) {
> return REG_FIELD_PREP(CGM_PIPE_DEGAMMA_GREEN_LDW_MASK,
> drm_color_lut_extract(color->green, 14)) | @@ -1728,6 +1832,18 @@ static bool
> intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state
> !old_crtc_state->pre_csc_lut;
> }
>
> +static bool vlv_can_preload_luts(const struct intel_crtc_state
> +*new_crtc_state) {
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> + struct intel_atomic_state *state =
> + to_intel_atomic_state(new_crtc_state->uapi.state);
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> +
> + return !old_crtc_state->wgc_enable &&
> + !old_crtc_state->post_csc_lut;
> +}
> +
> static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state) {
> struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> @@ -1744,7 +1860,7 @@ static bool chv_can_preload_luts(const struct
> intel_crtc_state *new_crtc_state)
> if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode)
> return false;
>
> - return !old_crtc_state->post_csc_lut;
> + return vlv_can_preload_luts(new_crtc_state);
> }
>
> int intel_color_check(struct intel_crtc_state *crtc_state) @@ -2031,6 +2147,39 @@
> static int i9xx_color_check(struct intel_crtc_state *crtc_state)
> return 0;
> }
>
> +/*
> + * VLV color pipeline:
> + * u0.10 -> WGC csc -> u0.10 -> pipe gamma -> u0.10 */ static int
> +vlv_color_check(struct intel_crtc_state *crtc_state) {
> + int ret;
> +
> + ret = check_luts(crtc_state);
> + if (ret)
> + return ret;
> +
> + crtc_state->gamma_enable =
> + crtc_state->hw.gamma_lut &&
> + !crtc_state->c8_planes;
> +
> + crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);
> +
> + crtc_state->wgc_enable = crtc_state->hw.ctm;
> +
> + ret = intel_color_add_affected_planes(crtc_state);
> + if (ret)
> + return ret;
> +
> + intel_assign_luts(crtc_state);
> +
> + vlv_assign_csc(crtc_state);
> +
> + crtc_state->preload_luts = vlv_can_preload_luts(crtc_state);
> +
> + return 0;
> +}
> +
> static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state) {
> u32 cgm_mode = 0;
> @@ -2081,6 +2230,12 @@ static int chv_color_check(struct intel_crtc_state
> *crtc_state)
>
> crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
>
> + /*
> + * We always bypass the WGC CSC and use the CGM CSC
> + * instead since it has degamma and better precision.
> + */
> + crtc_state->wgc_enable = false;
> +
> ret = intel_color_add_affected_planes(crtc_state);
> if (ret)
> return ret;
> @@ -3395,6 +3550,15 @@ static const struct intel_color_funcs chv_color_funcs = {
> .read_csc = chv_read_csc,
> };
>
> +static const struct intel_color_funcs vlv_color_funcs = {
> + .color_check = vlv_color_check,
> + .color_commit_arm = i9xx_color_commit_arm,
> + .load_luts = vlv_load_luts,
> + .read_luts = i965_read_luts,
> + .lut_equal = i965_lut_equal,
> + .read_csc = vlv_read_csc,
> +};
> +
> static const struct intel_color_funcs i965_color_funcs = {
> .color_check = i9xx_color_check,
> .color_commit_arm = i9xx_color_commit_arm, @@ -3502,7 +3666,7 @@
> void intel_color_crtc_init(struct intel_crtc *crtc)
>
> gamma_lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size;
> degamma_lut_size = INTEL_INFO(i915)->display.color.degamma_lut_size;
> - has_ctm = DISPLAY_VER(i915) >= 5 && !IS_VALLEYVIEW(i915);
> + has_ctm = DISPLAY_VER(i915) >= 5;
>
> /*
> * "DPALETTE_A: NOTE: The 8-bit (non-10-bit) mode is the @@ -3540,6
> +3704,8 @@ void intel_color_init_hooks(struct drm_i915_private *i915)
> if (HAS_GMCH(i915)) {
> if (IS_CHERRYVIEW(i915))
> i915->display.funcs.color = &chv_color_funcs;
> + else if (IS_VALLEYVIEW(i915))
> + i915->display.funcs.color = &vlv_color_funcs;
> else if (DISPLAY_VER(i915) >= 4)
> i915->display.funcs.color = &i965_color_funcs;
> else
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index 0cdcaa49656f..dd0895b24682 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -184,7 +184,7 @@ ilk_dump_csc(struct drm_i915_private *i915, const char
> *name, }
>
> static void
> -chv_dump_csc(struct drm_i915_private *i915, const char *name,
> +vlv_dump_csc(struct drm_i915_private *i915, const char *name,
> const struct intel_csc_matrix *csc) {
> int i;
> @@ -370,7 +370,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state
> *pipe_config,
> if (!HAS_GMCH(i915))
> ilk_dump_csc(i915, "pipe csc", &pipe_config->csc);
> else if (IS_CHERRYVIEW(i915))
> - chv_dump_csc(i915, "cgm csc", &pipe_config->csc);
> + vlv_dump_csc(i915, "cgm csc", &pipe_config->csc);
> + else if (IS_VALLEYVIEW(i915))
> + vlv_dump_csc(i915, "wgc csc", &pipe_config->csc);
>
> dump_planes:
> if (!state)
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 0334565cec82..962bbd13a5bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2931,6 +2931,9 @@ void i9xx_set_pipeconf(const struct intel_crtc_state
> *crtc_state)
>
> val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
>
> + if (crtc_state->wgc_enable)
> + val |= TRANSCONF_WGC_ENABLE;
> +
> val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay -
> 1);
>
> intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); @@ -3123,6
> +3126,10 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>
> pipe_config->framestart_delay =
> REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
>
> + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> + (tmp & TRANSCONF_WGC_ENABLE))
> + pipe_config->wgc_enable = true;
> +
> if (IS_CHERRYVIEW(dev_priv))
> pipe_config->cgm_mode = intel_de_read(dev_priv,
> CGM_PIPE_MODE(crtc->pipe));
> @@ -5711,6 +5718,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
> *current_config,
> PIPE_CONF_CHECK_X(csc_mode);
> PIPE_CONF_CHECK_BOOL(gamma_enable);
> PIPE_CONF_CHECK_BOOL(csc_enable);
> + PIPE_CONF_CHECK_BOOL(wgc_enable);
>
> PIPE_CONF_CHECK_I(linetime);
> PIPE_CONF_CHECK_I(ips_linetime);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b28c8dc48e24..5357664cdf55 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1295,6 +1295,9 @@ struct intel_crtc_state {
> /* enable pipe csc? */
> bool csc_enable;
>
> + /* enable vlv/chv wgc csc? */
> + bool wgc_enable;
> +
> /* big joiner pipe bitmask */
> u8 bigjoiner_pipes;
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e9dd19cc66a2..e1a6ba6839b6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2550,6 +2550,7 @@
> #define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /*
> ilk/snb/ivb */
> #define TRANSCONF_MSA_TIMING_DELAY(x)
> REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x))
> #define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16)
> +#define TRANSCONF_WGC_ENABLE REG_BIT(15) /* vlv/chv
> only */
> #define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14)
> #define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13)
> #define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /*
> ilk-ivb */
> @@ -6382,6 +6383,20 @@ enum skl_power_gate {
> (index) * 4,
> _PLANE_CSC_POSTOFF_HI_2(pipe) + \
> (index) * 4)
>
> +#define _PIPE_A_WGC_C01_C00 0x600B0 /* s2.10 */
> +#define _PIPE_A_WGC_C02 0x600B4 /* s2.10 */
> +#define _PIPE_A_WGC_C11_C10 0x600B8 /* s2.10 */
> +#define _PIPE_A_WGC_C12 0x600BC /* s2.10 */
> +#define _PIPE_A_WGC_C21_C20 0x600C0 /* s2.10 */
> +#define _PIPE_A_WGC_C22 0x600C4 /* s2.10 */
> +
> +#define PIPE_WGC_C01_C00(pipe) _MMIO_TRANS2(pipe,
> _PIPE_A_WGC_C01_C00)
> +#define PIPE_WGC_C02(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C02)
> +#define PIPE_WGC_C11_C10(pipe) _MMIO_TRANS2(pipe,
> _PIPE_A_WGC_C11_C10)
> +#define PIPE_WGC_C12(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C12)
> +#define PIPE_WGC_C21_C20(pipe) _MMIO_TRANS2(pipe,
> _PIPE_A_WGC_C21_C20)
> +#define PIPE_WGC_C22(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C22)
> +
> /* pipe CSC & degamma/gamma LUTs on CHV */
> #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
> #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
> --
> 2.39.2
^ permalink raw reply [flat|nested] 43+ messages in thread
* RE: [Intel-gfx] [PATCH v2 6/7] drm/i915: No 10bit gamma on desktop gen3 parts
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
@ 2023-05-25 21:25 ` Shankar, Uma
-1 siblings, 0 replies; 43+ messages in thread
From: Shankar, Uma @ 2023-05-25 21:25 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: dri-devel
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Thursday, April 13, 2023 10:19 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 6/7] drm/i915: No 10bit gamma on desktop gen3 parts
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Apparently desktop gen3 parts don't support the 10bit gamma mode at all. Stop
> claiming otherwise.
>
> As is the case with pipe A on gen3 mobile parts, the PIPECONF gamma mode bit can
> be set but it has no effect on the output.
>
> PNV seems to be the only slight exception, but generally the desktop PNV variant
> looks more like a mobile part so this is not entirely surprising.
Couldn't check the relevant spec to re-confirm, trusting your judgment here.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Fixes: 67630bacae23 ("drm/i915: Add 10bit gamma mode for gen2/3")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_pci.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index
> cddb6e197972..305c05c3f93b 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -250,13 +250,13 @@ static const struct intel_device_info i865g_info = {
> .dma_mask_size = 32, \
> I9XX_PIPE_OFFSETS, \
> I9XX_CURSOR_OFFSETS, \
> - I9XX_COLORS, \
> GEN_DEFAULT_PAGE_SIZES, \
> GEN_DEFAULT_REGIONS
>
> static const struct intel_device_info i915g_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_I915G),
> + I845_COLORS,
> .has_coherent_ggtt = false,
> .display.cursor_needs_physical = 1,
> .display.has_overlay = 1,
> @@ -268,6 +268,7 @@ static const struct intel_device_info i915g_info = { static
> const struct intel_device_info i915gm_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_I915GM),
> + I9XX_COLORS,
> .is_mobile = 1,
> .display.cursor_needs_physical = 1,
> .display.has_overlay = 1,
> @@ -281,6 +282,7 @@ static const struct intel_device_info i915gm_info = { static
> const struct intel_device_info i945g_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_I945G),
> + I845_COLORS,
> .display.has_hotplug = 1,
> .display.cursor_needs_physical = 1,
> .display.has_overlay = 1,
> @@ -292,6 +294,7 @@ static const struct intel_device_info i945g_info = { static
> const struct intel_device_info i945gm_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_I945GM),
> + I9XX_COLORS,
> .is_mobile = 1,
> .display.has_hotplug = 1,
> .display.cursor_needs_physical = 1,
> @@ -306,6 +309,7 @@ static const struct intel_device_info i945gm_info = { static
> const struct intel_device_info g33_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_G33),
> + I845_COLORS,
> .display.has_hotplug = 1,
> .display.has_overlay = 1,
> .dma_mask_size = 36,
> @@ -314,6 +318,7 @@ static const struct intel_device_info g33_info = { static
> const struct intel_device_info pnv_g_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_PINEVIEW),
> + I9XX_COLORS,
> .display.has_hotplug = 1,
> .display.has_overlay = 1,
> .dma_mask_size = 36,
> @@ -322,6 +327,7 @@ static const struct intel_device_info pnv_g_info = { static
> const struct intel_device_info pnv_m_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_PINEVIEW),
> + I9XX_COLORS,
> .is_mobile = 1,
> .display.has_hotplug = 1,
> .display.has_overlay = 1,
> --
> 2.39.2
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] [PATCH v2 6/7] drm/i915: No 10bit gamma on desktop gen3 parts
@ 2023-05-25 21:25 ` Shankar, Uma
0 siblings, 0 replies; 43+ messages in thread
From: Shankar, Uma @ 2023-05-25 21:25 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: dri-devel
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Thursday, April 13, 2023 10:19 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v2 6/7] drm/i915: No 10bit gamma on desktop gen3 parts
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Apparently desktop gen3 parts don't support the 10bit gamma mode at all. Stop
> claiming otherwise.
>
> As is the case with pipe A on gen3 mobile parts, the PIPECONF gamma mode bit can
> be set but it has no effect on the output.
>
> PNV seems to be the only slight exception, but generally the desktop PNV variant
> looks more like a mobile part so this is not entirely surprising.
Couldn't check the relevant spec to re-confirm, trusting your judgment here.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Fixes: 67630bacae23 ("drm/i915: Add 10bit gamma mode for gen2/3")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_pci.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index
> cddb6e197972..305c05c3f93b 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -250,13 +250,13 @@ static const struct intel_device_info i865g_info = {
> .dma_mask_size = 32, \
> I9XX_PIPE_OFFSETS, \
> I9XX_CURSOR_OFFSETS, \
> - I9XX_COLORS, \
> GEN_DEFAULT_PAGE_SIZES, \
> GEN_DEFAULT_REGIONS
>
> static const struct intel_device_info i915g_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_I915G),
> + I845_COLORS,
> .has_coherent_ggtt = false,
> .display.cursor_needs_physical = 1,
> .display.has_overlay = 1,
> @@ -268,6 +268,7 @@ static const struct intel_device_info i915g_info = { static
> const struct intel_device_info i915gm_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_I915GM),
> + I9XX_COLORS,
> .is_mobile = 1,
> .display.cursor_needs_physical = 1,
> .display.has_overlay = 1,
> @@ -281,6 +282,7 @@ static const struct intel_device_info i915gm_info = { static
> const struct intel_device_info i945g_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_I945G),
> + I845_COLORS,
> .display.has_hotplug = 1,
> .display.cursor_needs_physical = 1,
> .display.has_overlay = 1,
> @@ -292,6 +294,7 @@ static const struct intel_device_info i945g_info = { static
> const struct intel_device_info i945gm_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_I945GM),
> + I9XX_COLORS,
> .is_mobile = 1,
> .display.has_hotplug = 1,
> .display.cursor_needs_physical = 1,
> @@ -306,6 +309,7 @@ static const struct intel_device_info i945gm_info = { static
> const struct intel_device_info g33_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_G33),
> + I845_COLORS,
> .display.has_hotplug = 1,
> .display.has_overlay = 1,
> .dma_mask_size = 36,
> @@ -314,6 +318,7 @@ static const struct intel_device_info g33_info = { static
> const struct intel_device_info pnv_g_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_PINEVIEW),
> + I9XX_COLORS,
> .display.has_hotplug = 1,
> .display.has_overlay = 1,
> .dma_mask_size = 36,
> @@ -322,6 +327,7 @@ static const struct intel_device_info pnv_g_info = { static
> const struct intel_device_info pnv_m_info = {
> GEN3_FEATURES,
> PLATFORM(INTEL_PINEVIEW),
> + I9XX_COLORS,
> .is_mobile = 1,
> .display.has_hotplug = 1,
> .display.has_overlay = 1,
> --
> 2.39.2
^ permalink raw reply [flat|nested] 43+ messages in thread
* RE: [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling
2023-05-25 20:55 ` Shankar, Uma
@ 2023-05-25 21:27 ` Shankar, Uma
-1 siblings, 0 replies; 43+ messages in thread
From: Shankar, Uma @ 2023-05-25 21:27 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: dri-devel
> -----Original Message-----
> From: Shankar, Uma
> Sent: Friday, May 26, 2023 2:25 AM
> To: Ville Syrjala <ville.syrjala@linux.intel.com>; intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org
> Subject: RE: [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling
>
>
>
> > -----Original Message-----
> > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of
> > Ville Syrjala
> > Sent: Thursday, April 13, 2023 10:19 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: dri-devel@lists.freedesktop.org
> > Subject: [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign
> > handling
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > The CHV CGM CSC coefficients are in s4.12 two's complement format. Fix
> > the CTM-
> > >CGM conversion to handle that correctly instead of pretending that
> > >the hw
> > coefficients are also in some sign-magnitude format.
>
> Spec is slightly confusing when it says:
> "CGM CSC : Input pixels to the CGM CSC are 14 bits. (u.14 format). Coefficients are
> 16 bits (s3.12)."
> Also here:
> "Programmable parameters :
> c0[15 :0], c1[15 :0], c2[15 :0], c3[15 :0], c4[15 :0], c5[15 :0], c6[15 :0], c7[15 :0],
> c8[15 :0] ; // signed matrix coefficients (s3.12)"
>
> But the coefficients are 16bits, can you help understand how were you able to crack
> this 😊
I think I got it. Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_color.c | 46
> > ++++++++++++++--------
> > 1 file changed, 29 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> > b/drivers/gpu/drm/i915/display/intel_color.c
> > index 4fc16cac052d..63141f4ed372 100644
> > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > @@ -568,29 +568,41 @@ static void icl_load_csc_matrix(const struct
> > intel_crtc_state *crtc_state)
> > icl_update_output_csc(crtc, &crtc_state->output_csc); }
> >
> > +static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int
> > +frac_bits) {
> > + s64 c = CTM_COEFF_ABS(coeff);
> > +
> > + /* leave an extra bit for rounding */
> > + c >>= 32 - frac_bits - 1;
> > +
> > + /* round and drop the extra bit */
> > + c = (c + 1) >> 1;
> > +
> > + if (CTM_COEFF_NEGATIVE(coeff))
> > + c = -c;
> > +
> > + c = clamp(c, -(s64)BIT(int_bits + frac_bits - 1),
> > + (s64)(BIT(int_bits + frac_bits - 1) - 1));
> > +
> > + return c & (BIT(int_bits + frac_bits) - 1); }
> > +
> > +/*
> > + * CHV Color Gamut Mapping (CGM) CSC
> > + * |r| | c0 c1 c2 | |r|
> > + * |g| = | c3 c4 c5 | x |g|
> > + * |b| | c6 c7 c8 | |b|
> > + *
> > + * Coefficients are two's complement s4.12.
> > + */
> > static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
> > struct intel_csc_matrix *csc) {
> > const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
> > int i;
> >
> > - for (i = 0; i < 9; i++) {
> > - u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
> > -
> > - /* Round coefficient. */
> > - abs_coeff += 1 << (32 - 13);
> > - /* Clamp to hardware limits. */
> > - abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
> > -
> > - csc->coeff[i] = 0;
> > -
> > - /* Write coefficients in S3.12 format. */
> > - if (ctm->matrix[i] & (1ULL << 63))
> > - csc->coeff[i] |= 1 << 15;
> > -
> > - csc->coeff[i] |= ((abs_coeff >> 32) & 7) << 12;
> > - csc->coeff[i] |= (abs_coeff >> 20) & 0xfff;
> > - }
> > + for (i = 0; i < 9; i++)
> > + csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12);
> > }
> >
> > static void chv_load_cgm_csc(struct intel_crtc *crtc,
> > --
> > 2.39.2
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling
@ 2023-05-25 21:27 ` Shankar, Uma
0 siblings, 0 replies; 43+ messages in thread
From: Shankar, Uma @ 2023-05-25 21:27 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: dri-devel
> -----Original Message-----
> From: Shankar, Uma
> Sent: Friday, May 26, 2023 2:25 AM
> To: Ville Syrjala <ville.syrjala@linux.intel.com>; intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org
> Subject: RE: [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling
>
>
>
> > -----Original Message-----
> > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of
> > Ville Syrjala
> > Sent: Thursday, April 13, 2023 10:19 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: dri-devel@lists.freedesktop.org
> > Subject: [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign
> > handling
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > The CHV CGM CSC coefficients are in s4.12 two's complement format. Fix
> > the CTM-
> > >CGM conversion to handle that correctly instead of pretending that
> > >the hw
> > coefficients are also in some sign-magnitude format.
>
> Spec is slightly confusing when it says:
> "CGM CSC : Input pixels to the CGM CSC are 14 bits. (u.14 format). Coefficients are
> 16 bits (s3.12)."
> Also here:
> "Programmable parameters :
> c0[15 :0], c1[15 :0], c2[15 :0], c3[15 :0], c4[15 :0], c5[15 :0], c6[15 :0], c7[15 :0],
> c8[15 :0] ; // signed matrix coefficients (s3.12)"
>
> But the coefficients are 16bits, can you help understand how were you able to crack
> this 😊
I think I got it. Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_color.c | 46
> > ++++++++++++++--------
> > 1 file changed, 29 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> > b/drivers/gpu/drm/i915/display/intel_color.c
> > index 4fc16cac052d..63141f4ed372 100644
> > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > @@ -568,29 +568,41 @@ static void icl_load_csc_matrix(const struct
> > intel_crtc_state *crtc_state)
> > icl_update_output_csc(crtc, &crtc_state->output_csc); }
> >
> > +static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int
> > +frac_bits) {
> > + s64 c = CTM_COEFF_ABS(coeff);
> > +
> > + /* leave an extra bit for rounding */
> > + c >>= 32 - frac_bits - 1;
> > +
> > + /* round and drop the extra bit */
> > + c = (c + 1) >> 1;
> > +
> > + if (CTM_COEFF_NEGATIVE(coeff))
> > + c = -c;
> > +
> > + c = clamp(c, -(s64)BIT(int_bits + frac_bits - 1),
> > + (s64)(BIT(int_bits + frac_bits - 1) - 1));
> > +
> > + return c & (BIT(int_bits + frac_bits) - 1); }
> > +
> > +/*
> > + * CHV Color Gamut Mapping (CGM) CSC
> > + * |r| | c0 c1 c2 | |r|
> > + * |g| = | c3 c4 c5 | x |g|
> > + * |b| | c6 c7 c8 | |b|
> > + *
> > + * Coefficients are two's complement s4.12.
> > + */
> > static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
> > struct intel_csc_matrix *csc) {
> > const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
> > int i;
> >
> > - for (i = 0; i < 9; i++) {
> > - u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
> > -
> > - /* Round coefficient. */
> > - abs_coeff += 1 << (32 - 13);
> > - /* Clamp to hardware limits. */
> > - abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
> > -
> > - csc->coeff[i] = 0;
> > -
> > - /* Write coefficients in S3.12 format. */
> > - if (ctm->matrix[i] & (1ULL << 63))
> > - csc->coeff[i] |= 1 << 15;
> > -
> > - csc->coeff[i] |= ((abs_coeff >> 32) & 7) << 12;
> > - csc->coeff[i] |= (abs_coeff >> 20) & 0xfff;
> > - }
> > + for (i = 0; i < 9; i++)
> > + csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12);
> > }
> >
> > static void chv_load_cgm_csc(struct intel_crtc *crtc,
> > --
> > 2.39.2
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] [PATCH v2 6/7] drm/i915: No 10bit gamma on desktop gen3 parts
2023-05-25 21:25 ` Shankar, Uma
(?)
@ 2023-05-26 10:59 ` Jani Nikula
-1 siblings, 0 replies; 43+ messages in thread
From: Jani Nikula @ 2023-05-26 10:59 UTC (permalink / raw)
To: Shankar, Uma, Ville Syrjala, intel-gfx; +Cc: dri-devel
On Thu, 25 May 2023, "Shankar, Uma" <uma.shankar@intel.com> wrote:
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
>> Sent: Thursday, April 13, 2023 10:19 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: dri-devel@lists.freedesktop.org
>> Subject: [Intel-gfx] [PATCH v2 6/7] drm/i915: No 10bit gamma on desktop gen3 parts
>>
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Apparently desktop gen3 parts don't support the 10bit gamma mode at all. Stop
>> claiming otherwise.
>>
>> As is the case with pipe A on gen3 mobile parts, the PIPECONF gamma mode bit can
>> be set but it has no effect on the output.
>>
>> PNV seems to be the only slight exception, but generally the desktop PNV variant
>> looks more like a mobile part so this is not entirely surprising.
>
> Couldn't check the relevant spec to re-confirm, trusting your judgment here.
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
This needs a rebase on display/intel_display_device.[ch] stuff.
BR,
Jani.
>
>> Fixes: 67630bacae23 ("drm/i915: Add 10bit gamma mode for gen2/3")
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_pci.c | 8 +++++++-
>> 1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index
>> cddb6e197972..305c05c3f93b 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -250,13 +250,13 @@ static const struct intel_device_info i865g_info = {
>> .dma_mask_size = 32, \
>> I9XX_PIPE_OFFSETS, \
>> I9XX_CURSOR_OFFSETS, \
>> - I9XX_COLORS, \
>> GEN_DEFAULT_PAGE_SIZES, \
>> GEN_DEFAULT_REGIONS
>>
>> static const struct intel_device_info i915g_info = {
>> GEN3_FEATURES,
>> PLATFORM(INTEL_I915G),
>> + I845_COLORS,
>> .has_coherent_ggtt = false,
>> .display.cursor_needs_physical = 1,
>> .display.has_overlay = 1,
>> @@ -268,6 +268,7 @@ static const struct intel_device_info i915g_info = { static
>> const struct intel_device_info i915gm_info = {
>> GEN3_FEATURES,
>> PLATFORM(INTEL_I915GM),
>> + I9XX_COLORS,
>> .is_mobile = 1,
>> .display.cursor_needs_physical = 1,
>> .display.has_overlay = 1,
>> @@ -281,6 +282,7 @@ static const struct intel_device_info i915gm_info = { static
>> const struct intel_device_info i945g_info = {
>> GEN3_FEATURES,
>> PLATFORM(INTEL_I945G),
>> + I845_COLORS,
>> .display.has_hotplug = 1,
>> .display.cursor_needs_physical = 1,
>> .display.has_overlay = 1,
>> @@ -292,6 +294,7 @@ static const struct intel_device_info i945g_info = { static
>> const struct intel_device_info i945gm_info = {
>> GEN3_FEATURES,
>> PLATFORM(INTEL_I945GM),
>> + I9XX_COLORS,
>> .is_mobile = 1,
>> .display.has_hotplug = 1,
>> .display.cursor_needs_physical = 1,
>> @@ -306,6 +309,7 @@ static const struct intel_device_info i945gm_info = { static
>> const struct intel_device_info g33_info = {
>> GEN3_FEATURES,
>> PLATFORM(INTEL_G33),
>> + I845_COLORS,
>> .display.has_hotplug = 1,
>> .display.has_overlay = 1,
>> .dma_mask_size = 36,
>> @@ -314,6 +318,7 @@ static const struct intel_device_info g33_info = { static
>> const struct intel_device_info pnv_g_info = {
>> GEN3_FEATURES,
>> PLATFORM(INTEL_PINEVIEW),
>> + I9XX_COLORS,
>> .display.has_hotplug = 1,
>> .display.has_overlay = 1,
>> .dma_mask_size = 36,
>> @@ -322,6 +327,7 @@ static const struct intel_device_info pnv_g_info = { static
>> const struct intel_device_info pnv_m_info = {
>> GEN3_FEATURES,
>> PLATFORM(INTEL_PINEVIEW),
>> + I9XX_COLORS,
>> .is_mobile = 1,
>> .display.has_hotplug = 1,
>> .display.has_overlay = 1,
>> --
>> 2.39.2
>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling
2023-05-25 20:55 ` Shankar, Uma
@ 2023-05-26 13:48 ` Ville Syrjälä
-1 siblings, 0 replies; 43+ messages in thread
From: Ville Syrjälä @ 2023-05-26 13:48 UTC (permalink / raw)
To: Shankar, Uma; +Cc: intel-gfx, dri-devel
On Thu, May 25, 2023 at 08:55:08PM +0000, Shankar, Uma wrote:
>
>
> > -----Original Message-----
> > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> > Sent: Thursday, April 13, 2023 10:19 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: dri-devel@lists.freedesktop.org
> > Subject: [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > The CHV CGM CSC coefficients are in s4.12 two's complement format. Fix the CTM-
> > >CGM conversion to handle that correctly instead of pretending that the hw
> > coefficients are also in some sign-magnitude format.
>
> Spec is slightly confusing when it says:
> "CGM CSC : Input pixels to the CGM CSC are 14 bits. (u.14 format). Coefficients are 16 bits (s3.12)."
> Also here:
> "Programmable parameters :
> c0[15 :0], c1[15 :0], c2[15 :0], c3[15 :0], c4[15 :0], c5[15 :0], c6[15 :0], c7[15 :0], c8[15 :0] ; // signed matrix coefficients (s3.12)"
Yeah, the spec just uses a weird notation where it doesn't count the msb
in the bits.
>
> But the coefficients are 16bits, can you help understand how were you able to crack this 😊
The 16bit coefficient already made me suspect they screwed up
the notation. Testing specific values on real hardware
confirmed that.
>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_color.c | 46 ++++++++++++++--------
> > 1 file changed, 29 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> > b/drivers/gpu/drm/i915/display/intel_color.c
> > index 4fc16cac052d..63141f4ed372 100644
> > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > @@ -568,29 +568,41 @@ static void icl_load_csc_matrix(const struct
> > intel_crtc_state *crtc_state)
> > icl_update_output_csc(crtc, &crtc_state->output_csc); }
> >
> > +static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int
> > +frac_bits) {
> > + s64 c = CTM_COEFF_ABS(coeff);
> > +
> > + /* leave an extra bit for rounding */
> > + c >>= 32 - frac_bits - 1;
> > +
> > + /* round and drop the extra bit */
> > + c = (c + 1) >> 1;
> > +
> > + if (CTM_COEFF_NEGATIVE(coeff))
> > + c = -c;
> > +
> > + c = clamp(c, -(s64)BIT(int_bits + frac_bits - 1),
> > + (s64)(BIT(int_bits + frac_bits - 1) - 1));
> > +
> > + return c & (BIT(int_bits + frac_bits) - 1); }
> > +
> > +/*
> > + * CHV Color Gamut Mapping (CGM) CSC
> > + * |r| | c0 c1 c2 | |r|
> > + * |g| = | c3 c4 c5 | x |g|
> > + * |b| | c6 c7 c8 | |b|
> > + *
> > + * Coefficients are two's complement s4.12.
> > + */
> > static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
> > struct intel_csc_matrix *csc)
> > {
> > const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
> > int i;
> >
> > - for (i = 0; i < 9; i++) {
> > - u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
> > -
> > - /* Round coefficient. */
> > - abs_coeff += 1 << (32 - 13);
> > - /* Clamp to hardware limits. */
> > - abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
> > -
> > - csc->coeff[i] = 0;
> > -
> > - /* Write coefficients in S3.12 format. */
> > - if (ctm->matrix[i] & (1ULL << 63))
> > - csc->coeff[i] |= 1 << 15;
> > -
> > - csc->coeff[i] |= ((abs_coeff >> 32) & 7) << 12;
> > - csc->coeff[i] |= (abs_coeff >> 20) & 0xfff;
> > - }
> > + for (i = 0; i < 9; i++)
> > + csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12);
> > }
> >
> > static void chv_load_cgm_csc(struct intel_crtc *crtc,
> > --
> > 2.39.2
>
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling
@ 2023-05-26 13:48 ` Ville Syrjälä
0 siblings, 0 replies; 43+ messages in thread
From: Ville Syrjälä @ 2023-05-26 13:48 UTC (permalink / raw)
To: Shankar, Uma; +Cc: intel-gfx, dri-devel
On Thu, May 25, 2023 at 08:55:08PM +0000, Shankar, Uma wrote:
>
>
> > -----Original Message-----
> > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> > Sent: Thursday, April 13, 2023 10:19 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: dri-devel@lists.freedesktop.org
> > Subject: [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > The CHV CGM CSC coefficients are in s4.12 two's complement format. Fix the CTM-
> > >CGM conversion to handle that correctly instead of pretending that the hw
> > coefficients are also in some sign-magnitude format.
>
> Spec is slightly confusing when it says:
> "CGM CSC : Input pixels to the CGM CSC are 14 bits. (u.14 format). Coefficients are 16 bits (s3.12)."
> Also here:
> "Programmable parameters :
> c0[15 :0], c1[15 :0], c2[15 :0], c3[15 :0], c4[15 :0], c5[15 :0], c6[15 :0], c7[15 :0], c8[15 :0] ; // signed matrix coefficients (s3.12)"
Yeah, the spec just uses a weird notation where it doesn't count the msb
in the bits.
>
> But the coefficients are 16bits, can you help understand how were you able to crack this 😊
The 16bit coefficient already made me suspect they screwed up
the notation. Testing specific values on real hardware
confirmed that.
>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_color.c | 46 ++++++++++++++--------
> > 1 file changed, 29 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> > b/drivers/gpu/drm/i915/display/intel_color.c
> > index 4fc16cac052d..63141f4ed372 100644
> > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > @@ -568,29 +568,41 @@ static void icl_load_csc_matrix(const struct
> > intel_crtc_state *crtc_state)
> > icl_update_output_csc(crtc, &crtc_state->output_csc); }
> >
> > +static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int
> > +frac_bits) {
> > + s64 c = CTM_COEFF_ABS(coeff);
> > +
> > + /* leave an extra bit for rounding */
> > + c >>= 32 - frac_bits - 1;
> > +
> > + /* round and drop the extra bit */
> > + c = (c + 1) >> 1;
> > +
> > + if (CTM_COEFF_NEGATIVE(coeff))
> > + c = -c;
> > +
> > + c = clamp(c, -(s64)BIT(int_bits + frac_bits - 1),
> > + (s64)(BIT(int_bits + frac_bits - 1) - 1));
> > +
> > + return c & (BIT(int_bits + frac_bits) - 1); }
> > +
> > +/*
> > + * CHV Color Gamut Mapping (CGM) CSC
> > + * |r| | c0 c1 c2 | |r|
> > + * |g| = | c3 c4 c5 | x |g|
> > + * |b| | c6 c7 c8 | |b|
> > + *
> > + * Coefficients are two's complement s4.12.
> > + */
> > static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
> > struct intel_csc_matrix *csc)
> > {
> > const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
> > int i;
> >
> > - for (i = 0; i < 9; i++) {
> > - u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
> > -
> > - /* Round coefficient. */
> > - abs_coeff += 1 << (32 - 13);
> > - /* Clamp to hardware limits. */
> > - abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
> > -
> > - csc->coeff[i] = 0;
> > -
> > - /* Write coefficients in S3.12 format. */
> > - if (ctm->matrix[i] & (1ULL << 63))
> > - csc->coeff[i] |= 1 << 15;
> > -
> > - csc->coeff[i] |= ((abs_coeff >> 32) & 7) << 12;
> > - csc->coeff[i] |= (abs_coeff >> 20) & 0xfff;
> > - }
> > + for (i = 0; i < 9; i++)
> > + csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12);
> > }
> >
> > static void chv_load_cgm_csc(struct intel_crtc *crtc,
> > --
> > 2.39.2
>
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] [PATCH v2 6/7] drm/i915: No 10bit gamma on desktop gen3 parts
2023-05-25 21:25 ` Shankar, Uma
(?)
(?)
@ 2023-05-26 13:51 ` Ville Syrjälä
-1 siblings, 0 replies; 43+ messages in thread
From: Ville Syrjälä @ 2023-05-26 13:51 UTC (permalink / raw)
To: Shankar, Uma; +Cc: intel-gfx, dri-devel
On Thu, May 25, 2023 at 09:25:46PM +0000, Shankar, Uma wrote:
>
>
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> > Sent: Thursday, April 13, 2023 10:19 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: dri-devel@lists.freedesktop.org
> > Subject: [Intel-gfx] [PATCH v2 6/7] drm/i915: No 10bit gamma on desktop gen3 parts
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Apparently desktop gen3 parts don't support the 10bit gamma mode at all. Stop
> > claiming otherwise.
> >
> > As is the case with pipe A on gen3 mobile parts, the PIPECONF gamma mode bit can
> > be set but it has no effect on the output.
> >
> > PNV seems to be the only slight exception, but generally the desktop PNV variant
> > looks more like a mobile part so this is not entirely surprising.
>
> Couldn't check the relevant spec to re-confirm, trusting your judgment here.
The spec isn't helpful here actually. Real world testing on every
gen3 platform was needed to be sure how this works.
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Thanks.
>
> > Fixes: 67630bacae23 ("drm/i915: Add 10bit gamma mode for gen2/3")
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_pci.c | 8 +++++++-
> > 1 file changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index
> > cddb6e197972..305c05c3f93b 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -250,13 +250,13 @@ static const struct intel_device_info i865g_info = {
> > .dma_mask_size = 32, \
> > I9XX_PIPE_OFFSETS, \
> > I9XX_CURSOR_OFFSETS, \
> > - I9XX_COLORS, \
> > GEN_DEFAULT_PAGE_SIZES, \
> > GEN_DEFAULT_REGIONS
> >
> > static const struct intel_device_info i915g_info = {
> > GEN3_FEATURES,
> > PLATFORM(INTEL_I915G),
> > + I845_COLORS,
> > .has_coherent_ggtt = false,
> > .display.cursor_needs_physical = 1,
> > .display.has_overlay = 1,
> > @@ -268,6 +268,7 @@ static const struct intel_device_info i915g_info = { static
> > const struct intel_device_info i915gm_info = {
> > GEN3_FEATURES,
> > PLATFORM(INTEL_I915GM),
> > + I9XX_COLORS,
> > .is_mobile = 1,
> > .display.cursor_needs_physical = 1,
> > .display.has_overlay = 1,
> > @@ -281,6 +282,7 @@ static const struct intel_device_info i915gm_info = { static
> > const struct intel_device_info i945g_info = {
> > GEN3_FEATURES,
> > PLATFORM(INTEL_I945G),
> > + I845_COLORS,
> > .display.has_hotplug = 1,
> > .display.cursor_needs_physical = 1,
> > .display.has_overlay = 1,
> > @@ -292,6 +294,7 @@ static const struct intel_device_info i945g_info = { static
> > const struct intel_device_info i945gm_info = {
> > GEN3_FEATURES,
> > PLATFORM(INTEL_I945GM),
> > + I9XX_COLORS,
> > .is_mobile = 1,
> > .display.has_hotplug = 1,
> > .display.cursor_needs_physical = 1,
> > @@ -306,6 +309,7 @@ static const struct intel_device_info i945gm_info = { static
> > const struct intel_device_info g33_info = {
> > GEN3_FEATURES,
> > PLATFORM(INTEL_G33),
> > + I845_COLORS,
> > .display.has_hotplug = 1,
> > .display.has_overlay = 1,
> > .dma_mask_size = 36,
> > @@ -314,6 +318,7 @@ static const struct intel_device_info g33_info = { static
> > const struct intel_device_info pnv_g_info = {
> > GEN3_FEATURES,
> > PLATFORM(INTEL_PINEVIEW),
> > + I9XX_COLORS,
> > .display.has_hotplug = 1,
> > .display.has_overlay = 1,
> > .dma_mask_size = 36,
> > @@ -322,6 +327,7 @@ static const struct intel_device_info pnv_g_info = { static
> > const struct intel_device_info pnv_m_info = {
> > GEN3_FEATURES,
> > PLATFORM(INTEL_PINEVIEW),
> > + I9XX_COLORS,
> > .is_mobile = 1,
> > .display.has_hotplug = 1,
> > .display.has_overlay = 1,
> > --
> > 2.39.2
>
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
* RE: [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling
2023-05-26 13:48 ` [Intel-gfx] " Ville Syrjälä
@ 2023-05-29 5:13 ` Shankar, Uma
-1 siblings, 0 replies; 43+ messages in thread
From: Shankar, Uma @ 2023-05-29 5:13 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, dri-devel
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Friday, May 26, 2023 7:18 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Subject: Re: [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling
>
> On Thu, May 25, 2023 at 08:55:08PM +0000, Shankar, Uma wrote:
> >
> >
> > > -----Original Message-----
> > > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf
> > > Of Ville Syrjala
> > > Sent: Thursday, April 13, 2023 10:19 PM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: dri-devel@lists.freedesktop.org
> > > Subject: [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign
> > > handling
> > >
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > The CHV CGM CSC coefficients are in s4.12 two's complement format.
> > > Fix the CTM-
> > > >CGM conversion to handle that correctly instead of pretending that
> > > >the hw
> > > coefficients are also in some sign-magnitude format.
> >
> > Spec is slightly confusing when it says:
> > "CGM CSC : Input pixels to the CGM CSC are 14 bits. (u.14 format). Coefficients are
> 16 bits (s3.12)."
> > Also here:
> > "Programmable parameters :
> > c0[15 :0], c1[15 :0], c2[15 :0], c3[15 :0], c4[15 :0], c5[15 :0], c6[15 :0], c7[15 :0],
> c8[15 :0] ; // signed matrix coefficients (s3.12)"
>
> Yeah, the spec just uses a weird notation where it doesn't count the msb in the bits.
>
> >
> > But the coefficients are 16bits, can you help understand how were you
> > able to crack this 😊
>
> The 16bit coefficient already made me suspect they screwed up the notation.
> Testing specific values on real hardware confirmed that.
Got it, thanks Ville for the clarification.
> >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_color.c | 46
> > > ++++++++++++++--------
> > > 1 file changed, 29 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> > > b/drivers/gpu/drm/i915/display/intel_color.c
> > > index 4fc16cac052d..63141f4ed372 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > > @@ -568,29 +568,41 @@ static void icl_load_csc_matrix(const struct
> > > intel_crtc_state *crtc_state)
> > > icl_update_output_csc(crtc, &crtc_state->output_csc); }
> > >
> > > +static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int
> > > +frac_bits) {
> > > + s64 c = CTM_COEFF_ABS(coeff);
> > > +
> > > + /* leave an extra bit for rounding */
> > > + c >>= 32 - frac_bits - 1;
> > > +
> > > + /* round and drop the extra bit */
> > > + c = (c + 1) >> 1;
> > > +
> > > + if (CTM_COEFF_NEGATIVE(coeff))
> > > + c = -c;
> > > +
> > > + c = clamp(c, -(s64)BIT(int_bits + frac_bits - 1),
> > > + (s64)(BIT(int_bits + frac_bits - 1) - 1));
> > > +
> > > + return c & (BIT(int_bits + frac_bits) - 1); }
> > > +
> > > +/*
> > > + * CHV Color Gamut Mapping (CGM) CSC
> > > + * |r| | c0 c1 c2 | |r|
> > > + * |g| = | c3 c4 c5 | x |g|
> > > + * |b| | c6 c7 c8 | |b|
> > > + *
> > > + * Coefficients are two's complement s4.12.
> > > + */
> > > static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
> > > struct intel_csc_matrix *csc) {
> > > const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
> > > int i;
> > >
> > > - for (i = 0; i < 9; i++) {
> > > - u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
> > > -
> > > - /* Round coefficient. */
> > > - abs_coeff += 1 << (32 - 13);
> > > - /* Clamp to hardware limits. */
> > > - abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
> > > -
> > > - csc->coeff[i] = 0;
> > > -
> > > - /* Write coefficients in S3.12 format. */
> > > - if (ctm->matrix[i] & (1ULL << 63))
> > > - csc->coeff[i] |= 1 << 15;
> > > -
> > > - csc->coeff[i] |= ((abs_coeff >> 32) & 7) << 12;
> > > - csc->coeff[i] |= (abs_coeff >> 20) & 0xfff;
> > > - }
> > > + for (i = 0; i < 9; i++)
> > > + csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12);
> > > }
> > >
> > > static void chv_load_cgm_csc(struct intel_crtc *crtc,
> > > --
> > > 2.39.2
> >
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [Intel-gfx] [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling
@ 2023-05-29 5:13 ` Shankar, Uma
0 siblings, 0 replies; 43+ messages in thread
From: Shankar, Uma @ 2023-05-29 5:13 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, dri-devel
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Friday, May 26, 2023 7:18 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Subject: Re: [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling
>
> On Thu, May 25, 2023 at 08:55:08PM +0000, Shankar, Uma wrote:
> >
> >
> > > -----Original Message-----
> > > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf
> > > Of Ville Syrjala
> > > Sent: Thursday, April 13, 2023 10:19 PM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: dri-devel@lists.freedesktop.org
> > > Subject: [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign
> > > handling
> > >
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > The CHV CGM CSC coefficients are in s4.12 two's complement format.
> > > Fix the CTM-
> > > >CGM conversion to handle that correctly instead of pretending that
> > > >the hw
> > > coefficients are also in some sign-magnitude format.
> >
> > Spec is slightly confusing when it says:
> > "CGM CSC : Input pixels to the CGM CSC are 14 bits. (u.14 format). Coefficients are
> 16 bits (s3.12)."
> > Also here:
> > "Programmable parameters :
> > c0[15 :0], c1[15 :0], c2[15 :0], c3[15 :0], c4[15 :0], c5[15 :0], c6[15 :0], c7[15 :0],
> c8[15 :0] ; // signed matrix coefficients (s3.12)"
>
> Yeah, the spec just uses a weird notation where it doesn't count the msb in the bits.
>
> >
> > But the coefficients are 16bits, can you help understand how were you
> > able to crack this 😊
>
> The 16bit coefficient already made me suspect they screwed up the notation.
> Testing specific values on real hardware confirmed that.
Got it, thanks Ville for the clarification.
> >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_color.c | 46
> > > ++++++++++++++--------
> > > 1 file changed, 29 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> > > b/drivers/gpu/drm/i915/display/intel_color.c
> > > index 4fc16cac052d..63141f4ed372 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > > @@ -568,29 +568,41 @@ static void icl_load_csc_matrix(const struct
> > > intel_crtc_state *crtc_state)
> > > icl_update_output_csc(crtc, &crtc_state->output_csc); }
> > >
> > > +static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int
> > > +frac_bits) {
> > > + s64 c = CTM_COEFF_ABS(coeff);
> > > +
> > > + /* leave an extra bit for rounding */
> > > + c >>= 32 - frac_bits - 1;
> > > +
> > > + /* round and drop the extra bit */
> > > + c = (c + 1) >> 1;
> > > +
> > > + if (CTM_COEFF_NEGATIVE(coeff))
> > > + c = -c;
> > > +
> > > + c = clamp(c, -(s64)BIT(int_bits + frac_bits - 1),
> > > + (s64)(BIT(int_bits + frac_bits - 1) - 1));
> > > +
> > > + return c & (BIT(int_bits + frac_bits) - 1); }
> > > +
> > > +/*
> > > + * CHV Color Gamut Mapping (CGM) CSC
> > > + * |r| | c0 c1 c2 | |r|
> > > + * |g| = | c3 c4 c5 | x |g|
> > > + * |b| | c6 c7 c8 | |b|
> > > + *
> > > + * Coefficients are two's complement s4.12.
> > > + */
> > > static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
> > > struct intel_csc_matrix *csc) {
> > > const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
> > > int i;
> > >
> > > - for (i = 0; i < 9; i++) {
> > > - u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
> > > -
> > > - /* Round coefficient. */
> > > - abs_coeff += 1 << (32 - 13);
> > > - /* Clamp to hardware limits. */
> > > - abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
> > > -
> > > - csc->coeff[i] = 0;
> > > -
> > > - /* Write coefficients in S3.12 format. */
> > > - if (ctm->matrix[i] & (1ULL << 63))
> > > - csc->coeff[i] |= 1 << 15;
> > > -
> > > - csc->coeff[i] |= ((abs_coeff >> 32) & 7) << 12;
> > > - csc->coeff[i] |= (abs_coeff >> 20) & 0xfff;
> > > - }
> > > + for (i = 0; i < 9; i++)
> > > + csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12);
> > > }
> > >
> > > static void chv_load_cgm_csc(struct intel_crtc *crtc,
> > > --
> > > 2.39.2
> >
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 43+ messages in thread
end of thread, other threads:[~2023-05-29 5:13 UTC | newest]
Thread overview: 43+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-04-13 16:49 [PATCH v2 0/7] drm/i915: CTM stuff mostly Ville Syrjala
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
2023-04-13 16:49 ` [PATCH v2 1/7] drm/uapi: Document CTM matrix better Ville Syrjala
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
2023-04-13 16:49 ` [PATCH v2 2/7] drm/i915: Expose crtc CTM property on ilk/snb Ville Syrjala
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
2023-05-25 20:13 ` Shankar, Uma
2023-05-25 20:13 ` Shankar, Uma
2023-04-13 16:49 ` [PATCH v2 3/7] drm/i915: Fix CHV CGM CSC coefficient sign handling Ville Syrjala
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
2023-05-25 20:55 ` Shankar, Uma
2023-05-25 20:55 ` Shankar, Uma
2023-05-25 21:27 ` Shankar, Uma
2023-05-25 21:27 ` [Intel-gfx] " Shankar, Uma
2023-05-26 13:48 ` Ville Syrjälä
2023-05-26 13:48 ` [Intel-gfx] " Ville Syrjälä
2023-05-29 5:13 ` Shankar, Uma
2023-05-29 5:13 ` [Intel-gfx] " Shankar, Uma
2023-04-13 16:49 ` [PATCH v2 4/7] drm/i915: Always enable CGM CSC on CHV Ville Syrjala
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
2023-05-25 20:58 ` Shankar, Uma
2023-05-25 20:58 ` Shankar, Uma
2023-04-13 16:49 ` [PATCH v2 5/7] drm/i915: Implement CTM property support for VLV Ville Syrjala
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
2023-05-25 21:23 ` Shankar, Uma
2023-05-25 21:23 ` Shankar, Uma
2023-04-13 16:49 ` [PATCH v2 6/7] drm/i915: No 10bit gamma on desktop gen3 parts Ville Syrjala
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
2023-05-25 21:25 ` Shankar, Uma
2023-05-25 21:25 ` Shankar, Uma
2023-05-26 10:59 ` Jani Nikula
2023-05-26 13:51 ` Ville Syrjälä
2023-04-13 16:49 ` [PATCH v2 7/7] drm/i915: Do state check for color management changes Ville Syrjala
2023-04-13 16:49 ` [Intel-gfx] " Ville Syrjala
2023-04-13 18:28 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: CTM stuff mostly (rev3) Patchwork
2023-04-13 18:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-04-13 18:49 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-04-15 12:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: CTM stuff mostly (rev4) Patchwork
2023-04-15 13:09 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-04-15 20:11 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: CTM stuff mostly (rev5) Patchwork
2023-04-15 20:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-04-15 20:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-04-15 21:33 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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