* [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe.
@ 2023-05-22 12:36 sai.gowtham.ch
2023-05-22 12:36 ` [igt-dev] [PATCH i-g-t 1/2] lib/xe/xe_spin: " sai.gowtham.ch
` (3 more replies)
0 siblings, 4 replies; 12+ messages in thread
From: sai.gowtham.ch @ 2023-05-22 12:36 UTC (permalink / raw)
To: igt-dev, zbigniew.kempczynski, sai.gowtham.ch
From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Sai Gowtham Ch (2):
lib/xe/xe_spin: Integrate igt_spin_new with Xe.
tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe.
lib/igt_dummyload.c | 24 ++++++---
lib/igt_dummyload.h | 11 ++++
lib/xe/xe_spin.c | 68 +++++++++++++++++++++++
lib/xe/xe_spin.h | 7 +++
tests/meson.build | 1 +
tests/xe/xe_spin_batch.c | 113 +++++++++++++++++++++++++++++++++++++++
6 files changed, 218 insertions(+), 6 deletions(-)
create mode 100644 tests/xe/xe_spin_batch.c
--
2.39.1
^ permalink raw reply [flat|nested] 12+ messages in thread
* [igt-dev] [PATCH i-g-t 1/2] lib/xe/xe_spin: Integrate igt_spin_new with Xe.
2023-05-22 12:36 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
@ 2023-05-22 12:36 ` sai.gowtham.ch
2023-05-22 16:19 ` Zbigniew Kempczyński
2023-05-23 15:58 ` Zbigniew Kempczyński
2023-05-22 12:36 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
` (2 subsequent siblings)
3 siblings, 2 replies; 12+ messages in thread
From: sai.gowtham.ch @ 2023-05-22 12:36 UTC (permalink / raw)
To: igt-dev, zbigniew.kempczynski, sai.gowtham.ch
From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
Extending the spin_create implementation and allocator handle support in xe,
where it submits dummy work loads to engine. This Implementation is wrapped
around vm_bind and unbind as we are supposed to do it manually for xe.
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
lib/igt_dummyload.c | 24 ++++++++++++----
lib/igt_dummyload.h | 11 ++++++++
lib/xe/xe_spin.c | 68 +++++++++++++++++++++++++++++++++++++++++++++
lib/xe/xe_spin.h | 7 +++++
4 files changed, 104 insertions(+), 6 deletions(-)
diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 740a58f3..6e89b72d 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -46,6 +46,7 @@
#include "intel_reg.h"
#include "ioctl_wrappers.h"
#include "sw_sync.h"
+#include "xe/xe_spin.h"
/**
* SECTION:igt_dummyload
@@ -447,7 +448,10 @@ spin_create(int fd, const struct igt_spin_factory *opts)
igt_spin_t *
__igt_spin_factory(int fd, const struct igt_spin_factory *opts)
{
- return spin_create(fd, opts);
+ if (is_xe_device(fd))
+ return xe_spin_create(fd, opts);
+ else
+ return spin_create(fd, opts);
}
/**
@@ -467,6 +471,11 @@ igt_spin_factory(int fd, const struct igt_spin_factory *opts)
{
igt_spin_t *spin;
+ if (is_xe_device(fd)) {
+ spin = xe_spin_create(fd, opts);
+ return spin;
+ }
+
if ((opts->flags & IGT_SPIN_POLL_RUN) && opts->engine != ALL_ENGINES) {
unsigned int class;
@@ -647,11 +656,14 @@ void igt_spin_free(int fd, igt_spin_t *spin)
if (!spin)
return;
- pthread_mutex_lock(&list_lock);
- igt_list_del(&spin->link);
- pthread_mutex_unlock(&list_lock);
-
- __igt_spin_free(fd, spin);
+ if (is_xe_device(fd)) {
+ xe_spin_free(fd, spin);
+ } else {
+ pthread_mutex_lock(&list_lock);
+ igt_list_del(&spin->link);
+ pthread_mutex_unlock(&list_lock);
+ __igt_spin_free(fd, spin);
+ }
}
void igt_terminate_spins(void)
diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
index b247ab02..4da4e5a5 100644
--- a/lib/igt_dummyload.h
+++ b/lib/igt_dummyload.h
@@ -51,8 +51,10 @@ typedef struct igt_spin_factory {
uint32_t dependency;
uint64_t dependency_size;
unsigned int engine;
+ struct drm_xe_engine_class_instance *hwe;
unsigned int flags;
int fence;
+ uint32_t vm;
uint64_t ahnd;
} igt_spin_factory_t;
@@ -83,6 +85,15 @@ typedef struct igt_spin {
#define SPIN_CLFLUSH (1 << 0)
struct igt_spin_factory opts;
+
+ uint32_t start;
+ uint32_t end;
+ size_t bo_size;
+ uint64_t address;
+ unsigned int engine;
+ uint32_t vm;
+ uint32_t syncobj;
+
} igt_spin_t;
diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
index 856d0ba2..9a4fbeb8 100644
--- a/lib/xe/xe_spin.c
+++ b/lib/xe/xe_spin.c
@@ -15,6 +15,7 @@
#include "intel_reg.h"
#include "xe_ioctl.h"
#include "xe_spin.h"
+#include "lib/igt_dummyload.h"
/**
* xe_spin_init:
@@ -82,6 +83,73 @@ void xe_spin_end(struct xe_spin *spin)
spin->end = 0;
}
+igt_spin_t *
+xe_spin_create(int fd, const struct igt_spin_factory *opt)
+{
+ size_t bo_size = xe_get_default_alignment(fd);
+ uint32_t bo;
+ uint64_t ahnd = opt->ahnd, addr;
+ struct igt_spin *spin;
+ struct xe_spin *xe_spin;
+ struct drm_xe_sync sync = {
+ .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
+ };
+ struct drm_xe_exec exec = {
+ .num_batch_buffer = 1,
+ .num_syncs = 1,
+ .syncs = to_user_pointer(&sync),
+ };
+
+ igt_assert(ahnd);
+ xe_spin = calloc(1, sizeof(struct xe_spin));
+ igt_assert(xe_spin);
+ spin = calloc(1, sizeof(struct igt_spin));
+ igt_assert(spin);
+
+ if (opt->engine) {
+ spin->engine = opt->engine;
+ spin->vm = opt->vm;
+ } else {
+ spin->vm = xe_vm_create(fd, 0, 0);
+ spin->engine = xe_engine_create(fd, spin->vm, opt->hwe, 0);
+ }
+
+ bo = xe_bo_create(fd, opt->hwe->gt_id, spin->vm, bo_size);
+ spin->handle = bo;
+ spin->syncobj = syncobj_create(fd, 0);
+ addr = intel_allocator_alloc_with_strategy(ahnd, spin->handle, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH);
+ xe_vm_bind_sync(fd, spin->vm, spin->handle, 0, addr, bo_size);
+
+ xe_spin_init(xe_spin, addr, true);
+ exec.engine_id = spin->engine;
+ exec.address = addr;
+ sync.handle = spin->syncobj;
+ igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC, &exec), 0);
+
+ spin->batch = xe_spin->batch;
+ spin->start = xe_spin->start;
+ spin->end = xe_spin->end;
+ spin->bo_size = bo_size;
+ spin->address = addr;
+ return spin;
+
+}
+
+void xe_spin_sync_wait(int fd, struct igt_spin *spin)
+{
+ igt_assert(syncobj_wait(fd, &spin->syncobj, 1, INT64_MAX, 0,
+ NULL));
+}
+
+void xe_spin_free(int fd, struct igt_spin *spin)
+{
+ xe_vm_unbind_sync(fd, spin->vm, 0, spin->address, spin->bo_size);
+ spin->end = 0;
+ syncobj_destroy(fd, spin->syncobj);
+ xe_engine_destroy(fd, spin->engine);
+ gem_close(fd, spin->handle);
+}
+
void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
struct xe_cork *cork)
{
diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
index 73f9a026..48867eb8 100644
--- a/lib/xe/xe_spin.h
+++ b/lib/xe/xe_spin.h
@@ -13,19 +13,26 @@
#include <stdbool.h>
#include "xe_query.h"
+#include "lib/igt_dummyload.h"
/* Mapped GPU object */
+
struct xe_spin {
uint32_t batch[16];
uint64_t pad;
uint32_t start;
uint32_t end;
+
};
+igt_spin_t *
+xe_spin_create(int fd, const struct igt_spin_factory *opt);
void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt);
bool xe_spin_started(struct xe_spin *spin);
+void xe_spin_sync_wait(int fd, struct igt_spin *spin);
void xe_spin_wait_started(struct xe_spin *spin);
void xe_spin_end(struct xe_spin *spin);
+void xe_spin_free(int fd, struct igt_spin *spin);
struct xe_cork {
struct xe_spin *spin;
--
2.39.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe.
2023-05-22 12:36 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
2023-05-22 12:36 ` [igt-dev] [PATCH i-g-t 1/2] lib/xe/xe_spin: " sai.gowtham.ch
@ 2023-05-22 12:36 ` sai.gowtham.ch
2023-05-24 7:11 ` Modem, Bhanuprakash
2023-05-22 13:45 ` [igt-dev] ✓ Fi.CI.BAT: success for Integrate igt_spin_new with Xe Patchwork
2023-05-22 19:28 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
3 siblings, 1 reply; 12+ messages in thread
From: sai.gowtham.ch @ 2023-05-22 12:36 UTC (permalink / raw)
To: igt-dev, zbigniew.kempczynski, sai.gowtham.ch
From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
xe_spin_batch test exercises basic igt_spin_new submissions and
and with all engines.
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
---
tests/meson.build | 1 +
tests/xe/xe_spin_batch.c | 113 +++++++++++++++++++++++++++++++++++++++
2 files changed, 114 insertions(+)
create mode 100644 tests/xe/xe_spin_batch.c
diff --git a/tests/meson.build b/tests/meson.build
index f71be1db..e794b75a 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -268,6 +268,7 @@ xe_progs = [
'xe_query',
'xe_vm',
'xe_waitfence',
+ 'xe_spin_batch',
]
msm_progs = [
diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
new file mode 100644
index 00000000..55fbca92
--- /dev/null
+++ b/tests/xe/xe_spin_batch.c
@@ -0,0 +1,113 @@
+#include "igt.h"
+#include "lib/intel_reg.h"
+#include "xe_drm.h"
+#include "xe/xe_ioctl.h"
+#include "xe/xe_query.h"
+
+#define MAX_INSTANCE 9
+/**
+ * TEST: Basic test for spin batch submission.
+ *
+ * SUBTEST: spin-batch
+ * Description: Simple test!
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
+{
+ uint64_t ahnd;
+ unsigned int engine;
+ uint32_t vm;
+ igt_spin_t *spin;
+
+ vm = xe_vm_create(fd, 0, 0);
+ engine = xe_engine_create(fd, vm, hwe, 0);
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+ spin = __igt_spin_new(fd, .ahnd = ahnd, .hwe = hwe, .engine = engine, .vm = vm);
+ igt_assert(spin);
+
+ igt_spin_free(fd, spin);
+ put_ahnd(ahnd);
+}
+
+/**
+ * TEST: Test for spin batch submissions.
+ * SUBTEST: spin-all
+ * Description: Spinner test to run on all the engines!
+ * Run type: FULL
+ * TODO: change ``'Run type' == FULL`` to a better category
+ *
+ */
+
+static void spin_all (int fd, int gt, int class)
+{
+ uint64_t ahnd;
+ uint32_t engines[MAX_INSTANCE];
+ uint32_t vm[MAX_INSTANCE];
+ int i, num_placements = 0;
+ struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
+ igt_spin_t *spin[MAX_INSTANCE];
+ struct drm_xe_engine_class_instance *hwe;
+
+ ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
+ xe_for_each_hw_engine(fd, hwe) {
+ if (hwe->engine_class != class || hwe->gt_id != gt)
+ continue;
+ eci[num_placements++] = *hwe;
+ }
+ if (num_placements < 2)
+ return;
+
+ for (i = 0; i < num_placements; i++) {
+ struct drm_xe_engine_create create;
+ vm[i] = xe_vm_create(fd, 0, 0);
+
+ create.vm_id = vm[i];
+ create.width = 1;
+ create.num_placements = num_placements;
+ create.instances = to_user_pointer(eci);
+
+ igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
+ &create), 0);
+ engines[i] = create.engine_id;
+ spin[i] = __igt_spin_new(fd, .ahnd = ahnd, .hwe = eci, .engine = engines[i], .vm = vm[i]);
+ }
+
+ for (i = 0; i < num_placements; i++) {
+ igt_assert(spin[i]);
+ igt_spin_free(fd, spin[i]);
+ }
+}
+
+igt_main
+{
+ struct drm_xe_engine_class_instance *hwe;
+ int fd;
+ int gt, class;
+
+ igt_fixture {
+ fd = drm_open_driver(DRIVER_XE);
+ xe_device_get(fd);
+ }
+
+ igt_subtest("spin-batch")
+ xe_for_each_hw_engine(fd, hwe)
+ spin(fd, hwe);
+
+ igt_subtest("spin-all") {
+ xe_for_each_gt(fd, gt)
+ xe_for_each_hw_engine_class(class)
+ spin_all(fd, gt, class);
+ }
+
+ igt_fixture {
+ xe_device_put(fd);
+ close(fd);
+ }
+}
+
+
--
2.39.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Integrate igt_spin_new with Xe.
2023-05-22 12:36 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
2023-05-22 12:36 ` [igt-dev] [PATCH i-g-t 1/2] lib/xe/xe_spin: " sai.gowtham.ch
2023-05-22 12:36 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
@ 2023-05-22 13:45 ` Patchwork
2023-05-22 19:28 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
3 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2023-05-22 13:45 UTC (permalink / raw)
To: sai.gowtham.ch; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 3546 bytes --]
== Series Details ==
Series: Integrate igt_spin_new with Xe.
URL : https://patchwork.freedesktop.org/series/118121/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13173 -> IGTPW_9017
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/index.html
Participating hosts (38 -> 37)
------------------------------
Additional (1): bat-adlp-11
Missing (2): bat-rpls-2 fi-snb-2520m
Known issues
------------
Here are the changes found in IGTPW_9017 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][1] ([i915#1845] / [i915#5354]) +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1:
- bat-dg2-8: [PASS][2] -> [FAIL][3] ([i915#7932])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-d-dp-1.html
#### Possible fixes ####
* igt@i915_selftest@live@gem_migrate:
- {bat-mtlp-6}: [INCOMPLETE][4] -> [PASS][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/bat-mtlp-6/igt@i915_selftest@live@gem_migrate.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/bat-mtlp-6/igt@i915_selftest@live@gem_migrate.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1:
- bat-dg2-8: [FAIL][6] ([i915#7932]) -> [PASS][7] +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#8189]: https://gitlab.freedesktop.org/drm/intel/issues/8189
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7299 -> IGTPW_9017
CI-20190529: 20190529
CI_DRM_13173: ec24952f0cdb991b5a210ade43a479d293c054d6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9017: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/index.html
IGT_7299: 3effd4be7f6c867d942532b3fe18d6c54fffbd7a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Testlist changes
----------------
+igt@xe_spin_batch@spin-all
+igt@xe_spin_batch@spin-batch
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/index.html
[-- Attachment #2: Type: text/html, Size: 3843 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/2] lib/xe/xe_spin: Integrate igt_spin_new with Xe.
2023-05-22 12:36 ` [igt-dev] [PATCH i-g-t 1/2] lib/xe/xe_spin: " sai.gowtham.ch
@ 2023-05-22 16:19 ` Zbigniew Kempczyński
2023-05-23 8:41 ` Ch, Sai Gowtham
2023-05-23 15:58 ` Zbigniew Kempczyński
1 sibling, 1 reply; 12+ messages in thread
From: Zbigniew Kempczyński @ 2023-05-22 16:19 UTC (permalink / raw)
To: sai.gowtham.ch; +Cc: igt-dev
On Mon, May 22, 2023 at 06:06:04PM +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>
> Extending the spin_create implementation and allocator handle support in xe,
> where it submits dummy work loads to engine. This Implementation is wrapped
> around vm_bind and unbind as we are supposed to do it manually for xe.
>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
> lib/igt_dummyload.c | 24 ++++++++++++----
> lib/igt_dummyload.h | 11 ++++++++
> lib/xe/xe_spin.c | 68 +++++++++++++++++++++++++++++++++++++++++++++
> lib/xe/xe_spin.h | 7 +++++
> 4 files changed, 104 insertions(+), 6 deletions(-)
>
> diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
> index 740a58f3..6e89b72d 100644
> --- a/lib/igt_dummyload.c
> +++ b/lib/igt_dummyload.c
> @@ -46,6 +46,7 @@
> #include "intel_reg.h"
> #include "ioctl_wrappers.h"
> #include "sw_sync.h"
> +#include "xe/xe_spin.h"
>
> /**
> * SECTION:igt_dummyload
> @@ -447,7 +448,10 @@ spin_create(int fd, const struct igt_spin_factory *opts)
> igt_spin_t *
> __igt_spin_factory(int fd, const struct igt_spin_factory *opts)
> {
> - return spin_create(fd, opts);
> + if (is_xe_device(fd))
> + return xe_spin_create(fd, opts);
> + else
> + return spin_create(fd, opts);
> }
>
> /**
> @@ -467,6 +471,11 @@ igt_spin_factory(int fd, const struct igt_spin_factory *opts)
> {
> igt_spin_t *spin;
>
> + if (is_xe_device(fd)) {
> + spin = xe_spin_create(fd, opts);
> + return spin;
> + }
> +
> if ((opts->flags & IGT_SPIN_POLL_RUN) && opts->engine != ALL_ENGINES) {
> unsigned int class;
>
> @@ -647,11 +656,14 @@ void igt_spin_free(int fd, igt_spin_t *spin)
> if (!spin)
> return;
>
> - pthread_mutex_lock(&list_lock);
> - igt_list_del(&spin->link);
> - pthread_mutex_unlock(&list_lock);
> -
> - __igt_spin_free(fd, spin);
> + if (is_xe_device(fd)) {
> + xe_spin_free(fd, spin);
> + } else {
> + pthread_mutex_lock(&list_lock);
> + igt_list_del(&spin->link);
> + pthread_mutex_unlock(&list_lock);
> + __igt_spin_free(fd, spin);
> + }
> }
>
> void igt_terminate_spins(void)
> diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
> index b247ab02..4da4e5a5 100644
> --- a/lib/igt_dummyload.h
> +++ b/lib/igt_dummyload.h
> @@ -51,8 +51,10 @@ typedef struct igt_spin_factory {
> uint32_t dependency;
> uint64_t dependency_size;
> unsigned int engine;
> + struct drm_xe_engine_class_instance *hwe;
> unsigned int flags;
> int fence;
> + uint32_t vm;
> uint64_t ahnd;
> } igt_spin_factory_t;
>
> @@ -83,6 +85,15 @@ typedef struct igt_spin {
> #define SPIN_CLFLUSH (1 << 0)
>
> struct igt_spin_factory opts;
> +
> + uint32_t start;
> + uint32_t end;
> + size_t bo_size;
> + uint64_t address;
> + unsigned int engine;
> + uint32_t vm;
> + uint32_t syncobj;
> +
> } igt_spin_t;
>
>
> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
> index 856d0ba2..9a4fbeb8 100644
> --- a/lib/xe/xe_spin.c
> +++ b/lib/xe/xe_spin.c
> @@ -15,6 +15,7 @@
> #include "intel_reg.h"
> #include "xe_ioctl.h"
> #include "xe_spin.h"
> +#include "lib/igt_dummyload.h"
>
> /**
> * xe_spin_init:
> @@ -82,6 +83,73 @@ void xe_spin_end(struct xe_spin *spin)
> spin->end = 0;
> }
>
> +igt_spin_t *
> +xe_spin_create(int fd, const struct igt_spin_factory *opt)
> +{
> + size_t bo_size = xe_get_default_alignment(fd);
> + uint32_t bo;
> + uint64_t ahnd = opt->ahnd, addr;
> + struct igt_spin *spin;
> + struct xe_spin *xe_spin;
> + struct drm_xe_sync sync = {
> + .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
> + };
> + struct drm_xe_exec exec = {
> + .num_batch_buffer = 1,
> + .num_syncs = 1,
> + .syncs = to_user_pointer(&sync),
> + };
> +
> + igt_assert(ahnd);
> + xe_spin = calloc(1, sizeof(struct xe_spin));
> + igt_assert(xe_spin);
What is happening with xe_spin later? I mean it is allocated and?
> + spin = calloc(1, sizeof(struct igt_spin));
> + igt_assert(spin);
> +
> + if (opt->engine) {
> + spin->engine = opt->engine;
> + spin->vm = opt->vm;
> + } else {
> + spin->vm = xe_vm_create(fd, 0, 0);
> + spin->engine = xe_engine_create(fd, spin->vm, opt->hwe, 0);
> + }
> +
> + bo = xe_bo_create(fd, opt->hwe->gt_id, spin->vm, bo_size);
> + spin->handle = bo;
> + spin->syncobj = syncobj_create(fd, 0);
> + addr = intel_allocator_alloc_with_strategy(ahnd, spin->handle, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH);
> + xe_vm_bind_sync(fd, spin->vm, spin->handle, 0, addr, bo_size);
> +
> + xe_spin_init(xe_spin, addr, true);
> + exec.engine_id = spin->engine;
> + exec.address = addr;
> + sync.handle = spin->syncobj;
> + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC, &exec), 0);
This code submits the job, but there're no instructions in bo
dmesg complains with errors. Check your spin is not starting by
adding here:
xe_spin_wait_started(xe_spin);
cpu will stuck waiting for uncompleted store-dword.
Hint: check your bo.
--
Zbigniew
> +
> + spin->batch = xe_spin->batch;
> + spin->start = xe_spin->start;
> + spin->end = xe_spin->end;
> + spin->bo_size = bo_size;
> + spin->address = addr;
> + return spin;
> +
> +}
> +
> +void xe_spin_sync_wait(int fd, struct igt_spin *spin)
> +{
> + igt_assert(syncobj_wait(fd, &spin->syncobj, 1, INT64_MAX, 0,
> + NULL));
> +}
> +
> +void xe_spin_free(int fd, struct igt_spin *spin)
> +{
> + xe_vm_unbind_sync(fd, spin->vm, 0, spin->address, spin->bo_size);
> + spin->end = 0;
> + syncobj_destroy(fd, spin->syncobj);
> + xe_engine_destroy(fd, spin->engine);
> + gem_close(fd, spin->handle);
> +}
> +
> void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
> struct xe_cork *cork)
> {
> diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
> index 73f9a026..48867eb8 100644
> --- a/lib/xe/xe_spin.h
> +++ b/lib/xe/xe_spin.h
> @@ -13,19 +13,26 @@
> #include <stdbool.h>
>
> #include "xe_query.h"
> +#include "lib/igt_dummyload.h"
>
> /* Mapped GPU object */
> +
> struct xe_spin {
> uint32_t batch[16];
> uint64_t pad;
> uint32_t start;
> uint32_t end;
> +
> };
>
> +igt_spin_t *
> +xe_spin_create(int fd, const struct igt_spin_factory *opt);
> void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt);
> bool xe_spin_started(struct xe_spin *spin);
> +void xe_spin_sync_wait(int fd, struct igt_spin *spin);
> void xe_spin_wait_started(struct xe_spin *spin);
> void xe_spin_end(struct xe_spin *spin);
> +void xe_spin_free(int fd, struct igt_spin *spin);
>
> struct xe_cork {
> struct xe_spin *spin;
> --
> 2.39.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for Integrate igt_spin_new with Xe.
2023-05-22 12:36 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
` (2 preceding siblings ...)
2023-05-22 13:45 ` [igt-dev] ✓ Fi.CI.BAT: success for Integrate igt_spin_new with Xe Patchwork
@ 2023-05-22 19:28 ` Patchwork
3 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2023-05-22 19:28 UTC (permalink / raw)
To: sai.gowtham.ch; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 18790 bytes --]
== Series Details ==
Series: Integrate igt_spin_new with Xe.
URL : https://patchwork.freedesktop.org/series/118121/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13173_full -> IGTPW_9017_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/index.html
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_9017_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
- {shard-tglu}: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/shard-tglu-9/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-tglu-3/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
Known issues
------------
Here are the changes found in IGTPW_9017_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_barrier_race@remote-request@rcs0:
- shard-apl: [PASS][3] -> [ABORT][4] ([i915#7461] / [i915#8211] / [i915#8234])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/shard-apl3/igt@gem_barrier_race@remote-request@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-apl4/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_close_race@multigpu-basic-process:
- shard-apl: NOTRUN -> [SKIP][5] ([fdo#109271]) +61 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-apl1/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_exec_capture@capture-invisible@smem0:
- shard-apl: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4579] / [i915#6334])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-apl2/igt@gem_exec_capture@capture-invisible@smem0.html
* igt@gem_exec_schedule@thriceslice:
- shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271]) +49 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-snb2/igt@gem_exec_schedule@thriceslice.html
* igt@gem_lmem_evict@dontneed-evict-race:
- shard-glk: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-glk5/igt@gem_lmem_evict@dontneed-evict-race.html
* igt@gem_lmem_swapping@verify-random-ccs:
- shard-apl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-apl2/igt@gem_lmem_swapping@verify-random-ccs.html
* igt@gem_mmap_gtt@hang-busy:
- shard-glk: [PASS][10] -> [SKIP][11] ([fdo#109271])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/shard-glk1/igt@gem_mmap_gtt@hang-busy.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-glk6/igt@gem_mmap_gtt@hang-busy.html
* igt@gem_pread@exhaustion:
- shard-glk: NOTRUN -> [WARN][12] ([i915#2658])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-glk6/igt@gem_pread@exhaustion.html
* igt@gem_userptr_blits@vma-merge:
- shard-apl: NOTRUN -> [FAIL][13] ([i915#3318])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-apl4/igt@gem_userptr_blits@vma-merge.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-vga:
- shard-snb: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4579]) +10 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-snb6/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-vga.html
* igt@i915_pm_rps@engine-order:
- shard-apl: NOTRUN -> [FAIL][15] ([i915#6537])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-apl1/igt@i915_pm_rps@engine-order.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-apl: [PASS][16] -> [DMESG-FAIL][17] ([i915#5334])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/shard-apl4/igt@i915_selftest@live@gt_heartbeat.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-apl6/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3886])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-apl2/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium_hpd@vga-hpd:
- shard-glk: NOTRUN -> [SKIP][19] ([fdo#109271]) +16 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-glk3/igt@kms_chamelium_hpd@vga-hpd.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2:
- shard-glk: [PASS][20] -> [FAIL][21] ([i915#79])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-glk4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2.html
* igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [FAIL][22] ([i915#4573]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-glk8/igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-c-dp-1:
- shard-apl: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#4579]) +5 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-apl4/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-c-dp-1.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-apl: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#658])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-apl7/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
#### Possible fixes ####
* igt@gem_eio@hibernate:
- {shard-tglu}: [ABORT][25] ([i915#7975] / [i915#8213] / [i915#8398]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/shard-tglu-10/igt@gem_eio@hibernate.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-tglu-6/igt@gem_eio@hibernate.html
* igt@gem_eio@reset-stress:
- {shard-dg1}: [FAIL][27] ([i915#5784]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/shard-dg1-18/igt@gem_eio@reset-stress.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-dg1-16/igt@gem_eio@reset-stress.html
* igt@gem_exec_fair@basic-deadline:
- {shard-rkl}: [FAIL][29] ([i915#2846]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/shard-rkl-7/igt@gem_exec_fair@basic-deadline.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-rkl-6/igt@gem_exec_fair@basic-deadline.html
- shard-glk: [FAIL][31] ([i915#2846]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/shard-glk7/igt@gem_exec_fair@basic-deadline.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-glk9/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none@vecs0:
- {shard-rkl}: [FAIL][33] ([i915#2842]) -> [PASS][34] +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/shard-rkl-3/igt@gem_exec_fair@basic-none@vecs0.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-rkl-7/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_whisper@basic-fds-priority-all:
- {shard-tglu}: [INCOMPLETE][35] ([i915#6755] / [i915#7392] / [i915#7967]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/shard-tglu-10/igt@gem_exec_whisper@basic-fds-priority-all.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-tglu-9/igt@gem_exec_whisper@basic-fds-priority-all.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- {shard-dg1}: [TIMEOUT][37] ([i915#5493]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/shard-dg1-16/igt@gem_lmem_swapping@smem-oom@lmem0.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@i915_pm_dc@dc9-dpms:
- {shard-tglu}: [SKIP][39] ([i915#4281]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/shard-tglu-3/igt@i915_pm_dc@dc9-dpms.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-tglu-2/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- {shard-rkl}: [SKIP][41] ([i915#1397]) -> [PASS][42] +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/shard-rkl-3/igt@i915_pm_rpm@modeset-lpsp-stress.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-rkl-7/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@i915_pm_rps@reset:
- shard-snb: [INCOMPLETE][43] ([i915#7790]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/shard-snb5/igt@i915_pm_rps@reset.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-snb5/igt@i915_pm_rps@reset.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [FAIL][45] ([i915#2346]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
- shard-apl: [FAIL][47] ([i915#2346]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][49] ([i915#2122]) -> [PASS][50] +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][51] ([i915#79]) -> [PASS][52] +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt:
- {shard-dg1}: [DMESG-WARN][53] -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/shard-dg1-17/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html
* igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1:
- shard-apl: [ABORT][55] ([i915#180]) -> [PASS][56] +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13173/shard-apl2/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/shard-apl7/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6537]: https://gitlab.freedesktop.org/drm/intel/issues/6537
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6755]: https://gitlab.freedesktop.org/drm/intel/issues/6755
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7790]: https://gitlab.freedesktop.org/drm/intel/issues/7790
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7967]: https://gitlab.freedesktop.org/drm/intel/issues/7967
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234
[i915#8398]: https://gitlab.freedesktop.org/drm/intel/issues/8398
[i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7299 -> IGTPW_9017
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_13173: ec24952f0cdb991b5a210ade43a479d293c054d6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9017: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/index.html
IGT_7299: 3effd4be7f6c867d942532b3fe18d6c54fffbd7a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9017/index.html
[-- Attachment #2: Type: text/html, Size: 17315 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/2] lib/xe/xe_spin: Integrate igt_spin_new with Xe.
2023-05-22 16:19 ` Zbigniew Kempczyński
@ 2023-05-23 8:41 ` Ch, Sai Gowtham
2023-05-23 11:29 ` Zbigniew Kempczyński
0 siblings, 1 reply; 12+ messages in thread
From: Ch, Sai Gowtham @ 2023-05-23 8:41 UTC (permalink / raw)
To: Kempczynski, Zbigniew; +Cc: igt-dev
> -----Original Message-----
> From: Kempczynski, Zbigniew <zbigniew.kempczynski@intel.com>
> Sent: Monday, May 22, 2023 9:50 PM
> To: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>
> Cc: igt-dev@lists.freedesktop.org
> Subject: Re: [PATCH i-g-t 1/2] lib/xe/xe_spin: Integrate igt_spin_new with Xe.
>
> On Mon, May 22, 2023 at 06:06:04PM +0530, sai.gowtham.ch@intel.com
> wrote:
> > From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> >
> > Extending the spin_create implementation and allocator handle support
> > in xe, where it submits dummy work loads to engine. This
> > Implementation is wrapped around vm_bind and unbind as we are supposed to
> do it manually for xe.
> >
> > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> > ---
> > lib/igt_dummyload.c | 24 ++++++++++++---- lib/igt_dummyload.h | 11
> > ++++++++
> > lib/xe/xe_spin.c | 68 +++++++++++++++++++++++++++++++++++++++++++++
> > lib/xe/xe_spin.h | 7 +++++
> > 4 files changed, 104 insertions(+), 6 deletions(-)
> >
> > diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c index
> > 740a58f3..6e89b72d 100644
> > --- a/lib/igt_dummyload.c
> > +++ b/lib/igt_dummyload.c
> > @@ -46,6 +46,7 @@
> > #include "intel_reg.h"
> > #include "ioctl_wrappers.h"
> > #include "sw_sync.h"
> > +#include "xe/xe_spin.h"
> >
> > /**
> > * SECTION:igt_dummyload
> > @@ -447,7 +448,10 @@ spin_create(int fd, const struct igt_spin_factory
> > *opts) igt_spin_t * __igt_spin_factory(int fd, const struct
> > igt_spin_factory *opts) {
> > - return spin_create(fd, opts);
> > + if (is_xe_device(fd))
> > + return xe_spin_create(fd, opts);
> > + else
> > + return spin_create(fd, opts);
> > }
> >
> > /**
> > @@ -467,6 +471,11 @@ igt_spin_factory(int fd, const struct
> > igt_spin_factory *opts) {
> > igt_spin_t *spin;
> >
> > + if (is_xe_device(fd)) {
> > + spin = xe_spin_create(fd, opts);
> > + return spin;
> > + }
> > +
> > if ((opts->flags & IGT_SPIN_POLL_RUN) && opts->engine !=
> ALL_ENGINES) {
> > unsigned int class;
> >
> > @@ -647,11 +656,14 @@ void igt_spin_free(int fd, igt_spin_t *spin)
> > if (!spin)
> > return;
> >
> > - pthread_mutex_lock(&list_lock);
> > - igt_list_del(&spin->link);
> > - pthread_mutex_unlock(&list_lock);
> > -
> > - __igt_spin_free(fd, spin);
> > + if (is_xe_device(fd)) {
> > + xe_spin_free(fd, spin);
> > + } else {
> > + pthread_mutex_lock(&list_lock);
> > + igt_list_del(&spin->link);
> > + pthread_mutex_unlock(&list_lock);
> > + __igt_spin_free(fd, spin);
> > + }
> > }
> >
> > void igt_terminate_spins(void)
> > diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h index
> > b247ab02..4da4e5a5 100644
> > --- a/lib/igt_dummyload.h
> > +++ b/lib/igt_dummyload.h
> > @@ -51,8 +51,10 @@ typedef struct igt_spin_factory {
> > uint32_t dependency;
> > uint64_t dependency_size;
> > unsigned int engine;
> > + struct drm_xe_engine_class_instance *hwe;
> > unsigned int flags;
> > int fence;
> > + uint32_t vm;
> > uint64_t ahnd;
> > } igt_spin_factory_t;
> >
> > @@ -83,6 +85,15 @@ typedef struct igt_spin { #define SPIN_CLFLUSH (1
> > << 0)
> >
> > struct igt_spin_factory opts;
> > +
> > + uint32_t start;
> > + uint32_t end;
> > + size_t bo_size;
> > + uint64_t address;
> > + unsigned int engine;
> > + uint32_t vm;
> > + uint32_t syncobj;
> > +
> > } igt_spin_t;
> >
> >
> > diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c index
> > 856d0ba2..9a4fbeb8 100644
> > --- a/lib/xe/xe_spin.c
> > +++ b/lib/xe/xe_spin.c
> > @@ -15,6 +15,7 @@
> > #include "intel_reg.h"
> > #include "xe_ioctl.h"
> > #include "xe_spin.h"
> > +#include "lib/igt_dummyload.h"
> >
> > /**
> > * xe_spin_init:
> > @@ -82,6 +83,73 @@ void xe_spin_end(struct xe_spin *spin)
> > spin->end = 0;
> > }
> >
> > +igt_spin_t *
> > +xe_spin_create(int fd, const struct igt_spin_factory *opt) {
> > + size_t bo_size = xe_get_default_alignment(fd);
> > + uint32_t bo;
> > + uint64_t ahnd = opt->ahnd, addr;
> > + struct igt_spin *spin;
> > + struct xe_spin *xe_spin;
> > + struct drm_xe_sync sync = {
> > + .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
> > + };
> > + struct drm_xe_exec exec = {
> > + .num_batch_buffer = 1,
> > + .num_syncs = 1,
> > + .syncs = to_user_pointer(&sync),
> > + };
> > +
> > + igt_assert(ahnd);
> > + xe_spin = calloc(1, sizeof(struct xe_spin));
> > + igt_assert(xe_spin);
>
> What is happening with xe_spin later? I mean it is allocated and?
>
> > + spin = calloc(1, sizeof(struct igt_spin));
> > + igt_assert(spin);
> > +
> > + if (opt->engine) {
> > + spin->engine = opt->engine;
> > + spin->vm = opt->vm;
> > + } else {
> > + spin->vm = xe_vm_create(fd, 0, 0);
> > + spin->engine = xe_engine_create(fd, spin->vm, opt->hwe, 0);
> > + }
> > +
> > + bo = xe_bo_create(fd, opt->hwe->gt_id, spin->vm, bo_size);
> > + spin->handle = bo;
> > + spin->syncobj = syncobj_create(fd, 0);
> > + addr = intel_allocator_alloc_with_strategy(ahnd, spin->handle, bo_size,
> 0, ALLOC_STRATEGY_LOW_TO_HIGH);
> > + xe_vm_bind_sync(fd, spin->vm, spin->handle, 0, addr, bo_size);
> > +
> > + xe_spin_init(xe_spin, addr, true);
> > + exec.engine_id = spin->engine;
> > + exec.address = addr;
> > + sync.handle = spin->syncobj;
> > + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC, &exec), 0);
>
> This code submits the job, but there're no instructions in bo dmesg complains
> with errors. Check your spin is not starting by adding here:
>
I'm trying to understand more here, what do you mean by no instructions in bo ?
> xe_spin_wait_started(xe_spin);
>
Do you mean we have to wait spin for uncompleted store-dword after submitting exec ?
> cpu will stuck waiting for uncompleted store-dword.
>
> Hint: check your bo.
>
> --
> Zbigniew
>
> > +
> > + spin->batch = xe_spin->batch;
> > + spin->start = xe_spin->start;
> > + spin->end = xe_spin->end;
> > + spin->bo_size = bo_size;
> > + spin->address = addr;
> > + return spin;
> > +
> > +}
> > +
> > +void xe_spin_sync_wait(int fd, struct igt_spin *spin) {
> > + igt_assert(syncobj_wait(fd, &spin->syncobj, 1, INT64_MAX, 0,
> > + NULL));
> > +}
> > +
> > +void xe_spin_free(int fd, struct igt_spin *spin) {
> > + xe_vm_unbind_sync(fd, spin->vm, 0, spin->address, spin->bo_size);
> > + spin->end = 0;
> > + syncobj_destroy(fd, spin->syncobj);
> > + xe_engine_destroy(fd, spin->engine);
> > + gem_close(fd, spin->handle);
> > +}
> > +
> > void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
> > struct xe_cork *cork)
> > {
> > diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h index
> > 73f9a026..48867eb8 100644
> > --- a/lib/xe/xe_spin.h
> > +++ b/lib/xe/xe_spin.h
> > @@ -13,19 +13,26 @@
> > #include <stdbool.h>
> >
> > #include "xe_query.h"
> > +#include "lib/igt_dummyload.h"
> >
> > /* Mapped GPU object */
> > +
> > struct xe_spin {
> > uint32_t batch[16];
> > uint64_t pad;
> > uint32_t start;
> > uint32_t end;
> > +
> > };
> >
> > +igt_spin_t *
> > +xe_spin_create(int fd, const struct igt_spin_factory *opt);
> > void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt);
> > bool xe_spin_started(struct xe_spin *spin);
> > +void xe_spin_sync_wait(int fd, struct igt_spin *spin);
> > void xe_spin_wait_started(struct xe_spin *spin); void
> > xe_spin_end(struct xe_spin *spin);
> > +void xe_spin_free(int fd, struct igt_spin *spin);
> >
> > struct xe_cork {
> > struct xe_spin *spin;
> > --
> > 2.39.1
> >
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/2] lib/xe/xe_spin: Integrate igt_spin_new with Xe.
2023-05-23 8:41 ` Ch, Sai Gowtham
@ 2023-05-23 11:29 ` Zbigniew Kempczyński
0 siblings, 0 replies; 12+ messages in thread
From: Zbigniew Kempczyński @ 2023-05-23 11:29 UTC (permalink / raw)
To: Ch, Sai Gowtham; +Cc: igt-dev
On Tue, May 23, 2023 at 10:41:08AM +0200, Ch, Sai Gowtham wrote:
>
>
> > -----Original Message-----
> > From: Kempczynski, Zbigniew <zbigniew.kempczynski@intel.com>
> > Sent: Monday, May 22, 2023 9:50 PM
> > To: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>
> > Cc: igt-dev@lists.freedesktop.org
> > Subject: Re: [PATCH i-g-t 1/2] lib/xe/xe_spin: Integrate igt_spin_new with Xe.
> >
> > On Mon, May 22, 2023 at 06:06:04PM +0530, sai.gowtham.ch@intel.com
> > wrote:
> > > From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> > >
> > > Extending the spin_create implementation and allocator handle support
> > > in xe, where it submits dummy work loads to engine. This
> > > Implementation is wrapped around vm_bind and unbind as we are supposed to
> > do it manually for xe.
> > >
> > > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > > Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> > > ---
> > > lib/igt_dummyload.c | 24 ++++++++++++---- lib/igt_dummyload.h | 11
> > > ++++++++
> > > lib/xe/xe_spin.c | 68 +++++++++++++++++++++++++++++++++++++++++++++
> > > lib/xe/xe_spin.h | 7 +++++
> > > 4 files changed, 104 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c index
> > > 740a58f3..6e89b72d 100644
> > > --- a/lib/igt_dummyload.c
> > > +++ b/lib/igt_dummyload.c
> > > @@ -46,6 +46,7 @@
> > > #include "intel_reg.h"
> > > #include "ioctl_wrappers.h"
> > > #include "sw_sync.h"
> > > +#include "xe/xe_spin.h"
> > >
> > > /**
> > > * SECTION:igt_dummyload
> > > @@ -447,7 +448,10 @@ spin_create(int fd, const struct igt_spin_factory
> > > *opts) igt_spin_t * __igt_spin_factory(int fd, const struct
> > > igt_spin_factory *opts) {
> > > - return spin_create(fd, opts);
> > > + if (is_xe_device(fd))
> > > + return xe_spin_create(fd, opts);
> > > + else
> > > + return spin_create(fd, opts);
> > > }
> > >
> > > /**
> > > @@ -467,6 +471,11 @@ igt_spin_factory(int fd, const struct
> > > igt_spin_factory *opts) {
> > > igt_spin_t *spin;
> > >
> > > + if (is_xe_device(fd)) {
> > > + spin = xe_spin_create(fd, opts);
> > > + return spin;
> > > + }
> > > +
> > > if ((opts->flags & IGT_SPIN_POLL_RUN) && opts->engine !=
> > ALL_ENGINES) {
> > > unsigned int class;
> > >
> > > @@ -647,11 +656,14 @@ void igt_spin_free(int fd, igt_spin_t *spin)
> > > if (!spin)
> > > return;
> > >
> > > - pthread_mutex_lock(&list_lock);
> > > - igt_list_del(&spin->link);
> > > - pthread_mutex_unlock(&list_lock);
> > > -
> > > - __igt_spin_free(fd, spin);
> > > + if (is_xe_device(fd)) {
> > > + xe_spin_free(fd, spin);
> > > + } else {
> > > + pthread_mutex_lock(&list_lock);
> > > + igt_list_del(&spin->link);
> > > + pthread_mutex_unlock(&list_lock);
> > > + __igt_spin_free(fd, spin);
> > > + }
> > > }
> > >
> > > void igt_terminate_spins(void)
> > > diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h index
> > > b247ab02..4da4e5a5 100644
> > > --- a/lib/igt_dummyload.h
> > > +++ b/lib/igt_dummyload.h
> > > @@ -51,8 +51,10 @@ typedef struct igt_spin_factory {
> > > uint32_t dependency;
> > > uint64_t dependency_size;
> > > unsigned int engine;
> > > + struct drm_xe_engine_class_instance *hwe;
> > > unsigned int flags;
> > > int fence;
> > > + uint32_t vm;
> > > uint64_t ahnd;
> > > } igt_spin_factory_t;
> > >
> > > @@ -83,6 +85,15 @@ typedef struct igt_spin { #define SPIN_CLFLUSH (1
> > > << 0)
> > >
> > > struct igt_spin_factory opts;
> > > +
> > > + uint32_t start;
> > > + uint32_t end;
> > > + size_t bo_size;
> > > + uint64_t address;
> > > + unsigned int engine;
> > > + uint32_t vm;
> > > + uint32_t syncobj;
> > > +
> > > } igt_spin_t;
> > >
> > >
> > > diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c index
> > > 856d0ba2..9a4fbeb8 100644
> > > --- a/lib/xe/xe_spin.c
> > > +++ b/lib/xe/xe_spin.c
> > > @@ -15,6 +15,7 @@
> > > #include "intel_reg.h"
> > > #include "xe_ioctl.h"
> > > #include "xe_spin.h"
> > > +#include "lib/igt_dummyload.h"
> > >
> > > /**
> > > * xe_spin_init:
> > > @@ -82,6 +83,73 @@ void xe_spin_end(struct xe_spin *spin)
> > > spin->end = 0;
> > > }
> > >
> > > +igt_spin_t *
> > > +xe_spin_create(int fd, const struct igt_spin_factory *opt) {
> > > + size_t bo_size = xe_get_default_alignment(fd);
> > > + uint32_t bo;
> > > + uint64_t ahnd = opt->ahnd, addr;
> > > + struct igt_spin *spin;
> > > + struct xe_spin *xe_spin;
> > > + struct drm_xe_sync sync = {
> > > + .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
> > > + };
> > > + struct drm_xe_exec exec = {
> > > + .num_batch_buffer = 1,
> > > + .num_syncs = 1,
> > > + .syncs = to_user_pointer(&sync),
> > > + };
> > > +
> > > + igt_assert(ahnd);
> > > + xe_spin = calloc(1, sizeof(struct xe_spin));
> > > + igt_assert(xe_spin);
> >
> > What is happening with xe_spin later? I mean it is allocated and?
> >
> > > + spin = calloc(1, sizeof(struct igt_spin));
> > > + igt_assert(spin);
> > > +
> > > + if (opt->engine) {
> > > + spin->engine = opt->engine;
> > > + spin->vm = opt->vm;
> > > + } else {
> > > + spin->vm = xe_vm_create(fd, 0, 0);
> > > + spin->engine = xe_engine_create(fd, spin->vm, opt->hwe, 0);
> > > + }
> > > +
> > > + bo = xe_bo_create(fd, opt->hwe->gt_id, spin->vm, bo_size);
> > > + spin->handle = bo;
> > > + spin->syncobj = syncobj_create(fd, 0);
> > > + addr = intel_allocator_alloc_with_strategy(ahnd, spin->handle, bo_size,
> > 0, ALLOC_STRATEGY_LOW_TO_HIGH);
> > > + xe_vm_bind_sync(fd, spin->vm, spin->handle, 0, addr, bo_size);
> > > +
> > > + xe_spin_init(xe_spin, addr, true);
> > > + exec.engine_id = spin->engine;
> > > + exec.address = addr;
> > > + sync.handle = spin->syncobj;
> > > + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC, &exec), 0);
> >
> > This code submits the job, but there're no instructions in bo dmesg complains
> > with errors. Check your spin is not starting by adding here:
> >
> I'm trying to understand more here, what do you mean by no instructions in bo ?
Map your 'bo' (batch), dump 16 instructions and see what's there.
> > xe_spin_wait_started(xe_spin);
> >
> Do you mean we have to wait spin for uncompleted store-dword after submitting exec ?
Yes, this will reveal you're stucking here with current code.
--
Zbigniew
> > cpu will stuck waiting for uncompleted store-dword.
> >
> > Hint: check your bo.
> >
> > --
> > Zbigniew
> >
> > > +
> > > + spin->batch = xe_spin->batch;
> > > + spin->start = xe_spin->start;
> > > + spin->end = xe_spin->end;
> > > + spin->bo_size = bo_size;
> > > + spin->address = addr;
> > > + return spin;
> > > +
> > > +}
> > > +
> > > +void xe_spin_sync_wait(int fd, struct igt_spin *spin) {
> > > + igt_assert(syncobj_wait(fd, &spin->syncobj, 1, INT64_MAX, 0,
> > > + NULL));
> > > +}
> > > +
> > > +void xe_spin_free(int fd, struct igt_spin *spin) {
> > > + xe_vm_unbind_sync(fd, spin->vm, 0, spin->address, spin->bo_size);
> > > + spin->end = 0;
> > > + syncobj_destroy(fd, spin->syncobj);
> > > + xe_engine_destroy(fd, spin->engine);
> > > + gem_close(fd, spin->handle);
> > > +}
> > > +
> > > void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
> > > struct xe_cork *cork)
> > > {
> > > diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h index
> > > 73f9a026..48867eb8 100644
> > > --- a/lib/xe/xe_spin.h
> > > +++ b/lib/xe/xe_spin.h
> > > @@ -13,19 +13,26 @@
> > > #include <stdbool.h>
> > >
> > > #include "xe_query.h"
> > > +#include "lib/igt_dummyload.h"
> > >
> > > /* Mapped GPU object */
> > > +
> > > struct xe_spin {
> > > uint32_t batch[16];
> > > uint64_t pad;
> > > uint32_t start;
> > > uint32_t end;
> > > +
> > > };
> > >
> > > +igt_spin_t *
> > > +xe_spin_create(int fd, const struct igt_spin_factory *opt);
> > > void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt);
> > > bool xe_spin_started(struct xe_spin *spin);
> > > +void xe_spin_sync_wait(int fd, struct igt_spin *spin);
> > > void xe_spin_wait_started(struct xe_spin *spin); void
> > > xe_spin_end(struct xe_spin *spin);
> > > +void xe_spin_free(int fd, struct igt_spin *spin);
> > >
> > > struct xe_cork {
> > > struct xe_spin *spin;
> > > --
> > > 2.39.1
> > >
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/2] lib/xe/xe_spin: Integrate igt_spin_new with Xe.
2023-05-22 12:36 ` [igt-dev] [PATCH i-g-t 1/2] lib/xe/xe_spin: " sai.gowtham.ch
2023-05-22 16:19 ` Zbigniew Kempczyński
@ 2023-05-23 15:58 ` Zbigniew Kempczyński
1 sibling, 0 replies; 12+ messages in thread
From: Zbigniew Kempczyński @ 2023-05-23 15:58 UTC (permalink / raw)
To: sai.gowtham.ch; +Cc: igt-dev
On Mon, May 22, 2023 at 06:06:04PM +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>
> Extending the spin_create implementation and allocator handle support in xe,
> where it submits dummy work loads to engine. This Implementation is wrapped
> around vm_bind and unbind as we are supposed to do it manually for xe.
>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
> lib/igt_dummyload.c | 24 ++++++++++++----
> lib/igt_dummyload.h | 11 ++++++++
> lib/xe/xe_spin.c | 68 +++++++++++++++++++++++++++++++++++++++++++++
> lib/xe/xe_spin.h | 7 +++++
> 4 files changed, 104 insertions(+), 6 deletions(-)
>
> diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
> index 740a58f3..6e89b72d 100644
> --- a/lib/igt_dummyload.c
> +++ b/lib/igt_dummyload.c
> @@ -46,6 +46,7 @@
> #include "intel_reg.h"
> #include "ioctl_wrappers.h"
> #include "sw_sync.h"
> +#include "xe/xe_spin.h"
>
> /**
> * SECTION:igt_dummyload
> @@ -447,7 +448,10 @@ spin_create(int fd, const struct igt_spin_factory *opts)
> igt_spin_t *
> __igt_spin_factory(int fd, const struct igt_spin_factory *opts)
> {
> - return spin_create(fd, opts);
> + if (is_xe_device(fd))
> + return xe_spin_create(fd, opts);
> + else
> + return spin_create(fd, opts);
> }
You may use enum intel_driver and cache what's the device underneath to
avoid this check in free path. See __intel_bb_create() as a reference.
>
> /**
> @@ -467,6 +471,11 @@ igt_spin_factory(int fd, const struct igt_spin_factory *opts)
> {
> igt_spin_t *spin;
>
> + if (is_xe_device(fd)) {
> + spin = xe_spin_create(fd, opts);
> + return spin;
> + }
> +
> if ((opts->flags & IGT_SPIN_POLL_RUN) && opts->engine != ALL_ENGINES) {
> unsigned int class;
>
> @@ -647,11 +656,14 @@ void igt_spin_free(int fd, igt_spin_t *spin)
> if (!spin)
> return;
>
> - pthread_mutex_lock(&list_lock);
> - igt_list_del(&spin->link);
> - pthread_mutex_unlock(&list_lock);
> -
> - __igt_spin_free(fd, spin);
> + if (is_xe_device(fd)) {
> + xe_spin_free(fd, spin);
> + } else {
> + pthread_mutex_lock(&list_lock);
> + igt_list_del(&spin->link);
> + pthread_mutex_unlock(&list_lock);
> + __igt_spin_free(fd, spin);
> + }
> }
>
> void igt_terminate_spins(void)
> diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
> index b247ab02..4da4e5a5 100644
> --- a/lib/igt_dummyload.h
> +++ b/lib/igt_dummyload.h
> @@ -51,8 +51,10 @@ typedef struct igt_spin_factory {
> uint32_t dependency;
> uint64_t dependency_size;
> unsigned int engine;
> + struct drm_xe_engine_class_instance *hwe;
> unsigned int flags;
> int fence;
> + uint32_t vm;
> uint64_t ahnd;
Keep xe arguments on the end.
> } igt_spin_factory_t;
>
> @@ -83,6 +85,15 @@ typedef struct igt_spin {
> #define SPIN_CLFLUSH (1 << 0)
>
> struct igt_spin_factory opts;
> +
> + uint32_t start;
> + uint32_t end;
> + size_t bo_size;
> + uint64_t address;
> + unsigned int engine;
> + uint32_t vm;
> + uint32_t syncobj;
> +
start and end are not necessary. Use struct xe_spin *xe_spin instead.
Other fields are ok.
> } igt_spin_t;
>
>
> diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
> index 856d0ba2..9a4fbeb8 100644
> --- a/lib/xe/xe_spin.c
> +++ b/lib/xe/xe_spin.c
> @@ -15,6 +15,7 @@
> #include "intel_reg.h"
> #include "xe_ioctl.h"
> #include "xe_spin.h"
> +#include "lib/igt_dummyload.h"
>
> /**
> * xe_spin_init:
> @@ -82,6 +83,73 @@ void xe_spin_end(struct xe_spin *spin)
> spin->end = 0;
> }
>
> +igt_spin_t *
> +xe_spin_create(int fd, const struct igt_spin_factory *opt)
> +{
> + size_t bo_size = xe_get_default_alignment(fd);
> + uint32_t bo;
> + uint64_t ahnd = opt->ahnd, addr;
> + struct igt_spin *spin;
> + struct xe_spin *xe_spin;
> + struct drm_xe_sync sync = {
> + .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
> + };
> + struct drm_xe_exec exec = {
> + .num_batch_buffer = 1,
> + .num_syncs = 1,
> + .syncs = to_user_pointer(&sync),
> + };
> +
> + igt_assert(ahnd);
> + xe_spin = calloc(1, sizeof(struct xe_spin));
> + igt_assert(xe_spin);
> + spin = calloc(1, sizeof(struct igt_spin));
> + igt_assert(spin);
> +
> + if (opt->engine) {
> + spin->engine = opt->engine;
> + spin->vm = opt->vm;
> + } else {
> + spin->vm = xe_vm_create(fd, 0, 0);
> + spin->engine = xe_engine_create(fd, spin->vm, opt->hwe, 0);
> + }
> +
> + bo = xe_bo_create(fd, opt->hwe->gt_id, spin->vm, bo_size);
> + spin->handle = bo;
> + spin->syncobj = syncobj_create(fd, 0);
> + addr = intel_allocator_alloc_with_strategy(ahnd, spin->handle, bo_size, 0, ALLOC_STRATEGY_LOW_TO_HIGH);
> + xe_vm_bind_sync(fd, spin->vm, spin->handle, 0, addr, bo_size);
> +
> + xe_spin_init(xe_spin, addr, true);
> + exec.engine_id = spin->engine;
> + exec.address = addr;
> + sync.handle = spin->syncobj;
> + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_EXEC, &exec), 0);
> +
> + spin->batch = xe_spin->batch;
> + spin->start = xe_spin->start;
> + spin->end = xe_spin->end;
> + spin->bo_size = bo_size;
> + spin->address = addr;
Blank line here will make this code more readable.
> + return spin;
> +
And this blank line is unnecessary.
> +}
> +
> +void xe_spin_sync_wait(int fd, struct igt_spin *spin)
> +{
> + igt_assert(syncobj_wait(fd, &spin->syncobj, 1, INT64_MAX, 0,
> + NULL));
> +}
> +
> +void xe_spin_free(int fd, struct igt_spin *spin)
> +{
> + xe_vm_unbind_sync(fd, spin->vm, 0, spin->address, spin->bo_size);
> + spin->end = 0;
Are you really sure you want to unbind then stop the spinner?
And use xe_spin_end() for stopping the spinner.
> + syncobj_destroy(fd, spin->syncobj);
> + xe_engine_destroy(fd, spin->engine);
> + gem_close(fd, spin->handle);
Spin memory will leak here.
--
Zbigniew
> +}
> +
> void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
> struct xe_cork *cork)
> {
> diff --git a/lib/xe/xe_spin.h b/lib/xe/xe_spin.h
> index 73f9a026..48867eb8 100644
> --- a/lib/xe/xe_spin.h
> +++ b/lib/xe/xe_spin.h
> @@ -13,19 +13,26 @@
> #include <stdbool.h>
>
> #include "xe_query.h"
> +#include "lib/igt_dummyload.h"
>
> /* Mapped GPU object */
> +
> struct xe_spin {
> uint32_t batch[16];
> uint64_t pad;
> uint32_t start;
> uint32_t end;
> +
> };
>
> +igt_spin_t *
> +xe_spin_create(int fd, const struct igt_spin_factory *opt);
> void xe_spin_init(struct xe_spin *spin, uint64_t addr, bool preempt);
> bool xe_spin_started(struct xe_spin *spin);
> +void xe_spin_sync_wait(int fd, struct igt_spin *spin);
> void xe_spin_wait_started(struct xe_spin *spin);
> void xe_spin_end(struct xe_spin *spin);
> +void xe_spin_free(int fd, struct igt_spin *spin);
>
> struct xe_cork {
> struct xe_spin *spin;
> --
> 2.39.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe.
2023-05-22 12:36 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
@ 2023-05-24 7:11 ` Modem, Bhanuprakash
2023-05-24 19:47 ` Ch, Sai Gowtham
2023-05-25 5:46 ` Zbigniew Kempczyński
0 siblings, 2 replies; 12+ messages in thread
From: Modem, Bhanuprakash @ 2023-05-24 7:11 UTC (permalink / raw)
To: sai.gowtham.ch, igt-dev, zbigniew.kempczynski
On Mon-22-05-2023 06:06 pm, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
>
> xe_spin_batch test exercises basic igt_spin_new submissions and
> and with all engines.
>
> Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
> tests/meson.build | 1 +
> tests/xe/xe_spin_batch.c | 113 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 114 insertions(+)
> create mode 100644 tests/xe/xe_spin_batch.c
>
> diff --git a/tests/meson.build b/tests/meson.build
> index f71be1db..e794b75a 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -268,6 +268,7 @@ xe_progs = [
> 'xe_query',
> 'xe_vm',
> 'xe_waitfence',
> + 'xe_spin_batch',
> ]
>
> msm_progs = [
> diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
> new file mode 100644
> index 00000000..55fbca92
> --- /dev/null
> +++ b/tests/xe/xe_spin_batch.c
> @@ -0,0 +1,113 @@
> +#include "igt.h"
> +#include "lib/intel_reg.h"
> +#include "xe_drm.h"
> +#include "xe/xe_ioctl.h"
> +#include "xe/xe_query.h"
> +
> +#define MAX_INSTANCE 9
> +/**
> + * TEST: Basic test for spin batch submission.
> + *
> + * SUBTEST: spin-batch
> + * Description: Simple test!
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
> +{
> + uint64_t ahnd;
> + unsigned int engine;
> + uint32_t vm;
> + igt_spin_t *spin;
> +
> + vm = xe_vm_create(fd, 0, 0);
> + engine = xe_engine_create(fd, vm, hwe, 0);
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> + spin = __igt_spin_new(fd, .ahnd = ahnd, .hwe = hwe, .engine = engine, .vm = vm);
> + igt_assert(spin);
> +
> + igt_spin_free(fd, spin);
> + put_ahnd(ahnd);
> +}
> +
> +/**
> + * TEST: Test for spin batch submissions.
> + * SUBTEST: spin-all
> + * Description: Spinner test to run on all the engines!
> + * Run type: FULL
> + * TODO: change ``'Run type' == FULL`` to a better category
> + *
> + */
> +
> +static void spin_all (int fd, int gt, int class)
> +{
> + uint64_t ahnd;
> + uint32_t engines[MAX_INSTANCE];
> + uint32_t vm[MAX_INSTANCE];
> + int i, num_placements = 0;
> + struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> + igt_spin_t *spin[MAX_INSTANCE];
> + struct drm_xe_engine_class_instance *hwe;
> +
> + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> +
> + xe_for_each_hw_engine(fd, hwe) {
> + if (hwe->engine_class != class || hwe->gt_id != gt)
> + continue;
> + eci[num_placements++] = *hwe;
> + }
> + if (num_placements < 2)
> + return;
> +
> + for (i = 0; i < num_placements; i++) {
> + struct drm_xe_engine_create create;
> + vm[i] = xe_vm_create(fd, 0, 0);
> +
> + create.vm_id = vm[i];
> + create.width = 1;
> + create.num_placements = num_placements;
> + create.instances = to_user_pointer(eci);
> +
> + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
> + &create), 0);
> + engines[i] = create.engine_id;
> + spin[i] = __igt_spin_new(fd, .ahnd = ahnd, .hwe = eci, .engine = engines[i], .vm = vm[i]);
> + }
> +
> + for (i = 0; i < num_placements; i++) {
> + igt_assert(spin[i]);
> + igt_spin_free(fd, spin[i]);
> + }
> +}
> +
> +igt_main
> +{
> + struct drm_xe_engine_class_instance *hwe;
> + int fd;
> + int gt, class;
> +
> + igt_fixture {
> + fd = drm_open_driver(DRIVER_XE);
> + xe_device_get(fd);
> + }
> +
> + igt_subtest("spin-batch")
> + xe_for_each_hw_engine(fd, hwe)
I think, this loop should be handled inside the xe spin helper (like
spin_create()). Since KMS also trying to use the same helper & really
don't care about hardware engines.
- Bhanu
> + spin(fd, hwe);
> +
> + igt_subtest("spin-all") {
> + xe_for_each_gt(fd, gt)
> + xe_for_each_hw_engine_class(class)
> + spin_all(fd, gt, class);
> + }
> +
> + igt_fixture {
> + xe_device_put(fd);
> + close(fd);
> + }
> +}
> +
> +
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe.
2023-05-24 7:11 ` Modem, Bhanuprakash
@ 2023-05-24 19:47 ` Ch, Sai Gowtham
2023-05-25 5:46 ` Zbigniew Kempczyński
1 sibling, 0 replies; 12+ messages in thread
From: Ch, Sai Gowtham @ 2023-05-24 19:47 UTC (permalink / raw)
To: Modem, Bhanuprakash, igt-dev, Kempczynski, Zbigniew
> -----Original Message-----
> From: Modem, Bhanuprakash <bhanuprakash.modem@intel.com>
> Sent: Wednesday, May 24, 2023 12:41 PM
> To: Ch, Sai Gowtham <sai.gowtham.ch@intel.com>; igt-
> dev@lists.freedesktop.org; Kempczynski, Zbigniew
> <zbigniew.kempczynski@intel.com>
> Subject: Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to
> exercise igt_spin_new for xe.
>
>
> On Mon-22-05-2023 06:06 pm, sai.gowtham.ch@intel.com wrote:
> > From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> >
> > xe_spin_batch test exercises basic igt_spin_new submissions and and
> > with all engines.
> >
> > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> > ---
> > tests/meson.build | 1 +
> > tests/xe/xe_spin_batch.c | 113
> +++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 114 insertions(+)
> > create mode 100644 tests/xe/xe_spin_batch.c
> >
> > diff --git a/tests/meson.build b/tests/meson.build index
> > f71be1db..e794b75a 100644
> > --- a/tests/meson.build
> > +++ b/tests/meson.build
> > @@ -268,6 +268,7 @@ xe_progs = [
> > 'xe_query',
> > 'xe_vm',
> > 'xe_waitfence',
> > + 'xe_spin_batch',
> > ]
> >
> > msm_progs = [
> > diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c new
> > file mode 100644 index 00000000..55fbca92
> > --- /dev/null
> > +++ b/tests/xe/xe_spin_batch.c
> > @@ -0,0 +1,113 @@
> > +#include "igt.h"
> > +#include "lib/intel_reg.h"
> > +#include "xe_drm.h"
> > +#include "xe/xe_ioctl.h"
> > +#include "xe/xe_query.h"
> > +
> > +#define MAX_INSTANCE 9
> > +/**
> > + * TEST: Basic test for spin batch submission.
> > + *
> > + * SUBTEST: spin-batch
> > + * Description: Simple test!
> > + * Run type: FULL
> > + * TODO: change ``'Run type' == FULL`` to a better category
> > + *
> > + */
> > +
> > +static void spin(int fd, struct drm_xe_engine_class_instance *hwe) {
> > + uint64_t ahnd;
> > + unsigned int engine;
> > + uint32_t vm;
> > + igt_spin_t *spin;
> > +
> > + vm = xe_vm_create(fd, 0, 0);
> > + engine = xe_engine_create(fd, vm, hwe, 0);
> > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> > +
> > + spin = __igt_spin_new(fd, .ahnd = ahnd, .hwe = hwe, .engine = engine,
> .vm = vm);
> > + igt_assert(spin);
> > +
> > + igt_spin_free(fd, spin);
> > + put_ahnd(ahnd);
> > +}
> > +
> > +/**
> > + * TEST: Test for spin batch submissions.
> > + * SUBTEST: spin-all
> > + * Description: Spinner test to run on all the engines!
> > + * Run type: FULL
> > + * TODO: change ``'Run type' == FULL`` to a better category
> > + *
> > + */
> > +
> > +static void spin_all (int fd, int gt, int class) {
> > + uint64_t ahnd;
> > + uint32_t engines[MAX_INSTANCE];
> > + uint32_t vm[MAX_INSTANCE];
> > + int i, num_placements = 0;
> > + struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> > + igt_spin_t *spin[MAX_INSTANCE];
> > + struct drm_xe_engine_class_instance *hwe;
> > +
> > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> > +
> > + xe_for_each_hw_engine(fd, hwe) {
> > + if (hwe->engine_class != class || hwe->gt_id != gt)
> > + continue;
> > + eci[num_placements++] = *hwe;
> > + }
> > + if (num_placements < 2)
> > + return;
> > +
> > + for (i = 0; i < num_placements; i++) {
> > + struct drm_xe_engine_create create;
> > + vm[i] = xe_vm_create(fd, 0, 0);
> > +
> > + create.vm_id = vm[i];
> > + create.width = 1;
> > + create.num_placements = num_placements;
> > + create.instances = to_user_pointer(eci);
> > +
> > + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
> > + &create), 0);
> > + engines[i] = create.engine_id;
> > + spin[i] = __igt_spin_new(fd, .ahnd = ahnd, .hwe = eci, .engine =
> engines[i], .vm = vm[i]);
> > + }
> > +
> > + for (i = 0; i < num_placements; i++) {
> > + igt_assert(spin[i]);
> > + igt_spin_free(fd, spin[i]);
> > + }
> > +}
> > +
> > +igt_main
> > +{
> > + struct drm_xe_engine_class_instance *hwe;
> > + int fd;
> > + int gt, class;
> > +
> > + igt_fixture {
> > + fd = drm_open_driver(DRIVER_XE);
> > + xe_device_get(fd);
> > + }
> > +
> > + igt_subtest("spin-batch")
> > + xe_for_each_hw_engine(fd, hwe)
>
> I think, this loop should be handled inside the xe spin helper (like spin_create()).
> Since KMS also trying to use the same helper & really don't care about hardware
> engines.
>
That would be tricky because we need hwe for engine, I just tried something like below, however it's throwing an errno : 16, Device or resource busy while doing xe_vm_bind.
igt_spin_t *
__igt_spin_factory(int fd, const struct igt_spin_factory *opts)
{
if (is_xe_device(fd)) {
struct drm_xe_engine_class_instance *hwe;
igt_spin_t *spin;
xe_for_each_hw_engine(fd, hwe)
spin = xe_spin_create(fd, opts, hwe);
-----
Gowtham
> - Bhanu
>
> > + spin(fd, hwe);
> > +
> > + igt_subtest("spin-all") {
> > + xe_for_each_gt(fd, gt)
> > + xe_for_each_hw_engine_class(class)
> > + spin_all(fd, gt, class);
> > + }
> > +
> > + igt_fixture {
> > + xe_device_put(fd);
> > + close(fd);
> > + }
> > +}
> > +
> > +
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe.
2023-05-24 7:11 ` Modem, Bhanuprakash
2023-05-24 19:47 ` Ch, Sai Gowtham
@ 2023-05-25 5:46 ` Zbigniew Kempczyński
1 sibling, 0 replies; 12+ messages in thread
From: Zbigniew Kempczyński @ 2023-05-25 5:46 UTC (permalink / raw)
To: Modem, Bhanuprakash; +Cc: igt-dev, sai.gowtham.ch
On Wed, May 24, 2023 at 12:41:09PM +0530, Modem, Bhanuprakash wrote:
>
> On Mon-22-05-2023 06:06 pm, sai.gowtham.ch@intel.com wrote:
> > From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> >
> > xe_spin_batch test exercises basic igt_spin_new submissions and
> > and with all engines.
> >
> > Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> > ---
> > tests/meson.build | 1 +
> > tests/xe/xe_spin_batch.c | 113 +++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 114 insertions(+)
> > create mode 100644 tests/xe/xe_spin_batch.c
> >
> > diff --git a/tests/meson.build b/tests/meson.build
> > index f71be1db..e794b75a 100644
> > --- a/tests/meson.build
> > +++ b/tests/meson.build
> > @@ -268,6 +268,7 @@ xe_progs = [
> > 'xe_query',
> > 'xe_vm',
> > 'xe_waitfence',
> > + 'xe_spin_batch',
> > ]
> > msm_progs = [
> > diff --git a/tests/xe/xe_spin_batch.c b/tests/xe/xe_spin_batch.c
> > new file mode 100644
> > index 00000000..55fbca92
> > --- /dev/null
> > +++ b/tests/xe/xe_spin_batch.c
> > @@ -0,0 +1,113 @@
> > +#include "igt.h"
> > +#include "lib/intel_reg.h"
> > +#include "xe_drm.h"
> > +#include "xe/xe_ioctl.h"
> > +#include "xe/xe_query.h"
> > +
> > +#define MAX_INSTANCE 9
> > +/**
> > + * TEST: Basic test for spin batch submission.
> > + *
> > + * SUBTEST: spin-batch
> > + * Description: Simple test!
> > + * Run type: FULL
> > + * TODO: change ``'Run type' == FULL`` to a better category
> > + *
> > + */
> > +
> > +static void spin(int fd, struct drm_xe_engine_class_instance *hwe)
> > +{
> > + uint64_t ahnd;
> > + unsigned int engine;
> > + uint32_t vm;
> > + igt_spin_t *spin;
> > +
> > + vm = xe_vm_create(fd, 0, 0);
> > + engine = xe_engine_create(fd, vm, hwe, 0);
> > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> > +
> > + spin = __igt_spin_new(fd, .ahnd = ahnd, .hwe = hwe, .engine = engine, .vm = vm);
> > + igt_assert(spin);
> > +
> > + igt_spin_free(fd, spin);
> > + put_ahnd(ahnd);
> > +}
> > +
> > +/**
> > + * TEST: Test for spin batch submissions.
> > + * SUBTEST: spin-all
> > + * Description: Spinner test to run on all the engines!
> > + * Run type: FULL
> > + * TODO: change ``'Run type' == FULL`` to a better category
> > + *
> > + */
> > +
> > +static void spin_all (int fd, int gt, int class)
> > +{
> > + uint64_t ahnd;
> > + uint32_t engines[MAX_INSTANCE];
> > + uint32_t vm[MAX_INSTANCE];
> > + int i, num_placements = 0;
> > + struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
> > + igt_spin_t *spin[MAX_INSTANCE];
> > + struct drm_xe_engine_class_instance *hwe;
> > +
> > + ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
> > +
> > + xe_for_each_hw_engine(fd, hwe) {
> > + if (hwe->engine_class != class || hwe->gt_id != gt)
> > + continue;
> > + eci[num_placements++] = *hwe;
> > + }
> > + if (num_placements < 2)
> > + return;
> > +
> > + for (i = 0; i < num_placements; i++) {
> > + struct drm_xe_engine_create create;
> > + vm[i] = xe_vm_create(fd, 0, 0);
> > +
> > + create.vm_id = vm[i];
> > + create.width = 1;
> > + create.num_placements = num_placements;
> > + create.instances = to_user_pointer(eci);
> > +
> > + igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_ENGINE_CREATE,
> > + &create), 0);
> > + engines[i] = create.engine_id;
> > + spin[i] = __igt_spin_new(fd, .ahnd = ahnd, .hwe = eci, .engine = engines[i], .vm = vm[i]);
> > + }
> > +
> > + for (i = 0; i < num_placements; i++) {
> > + igt_assert(spin[i]);
> > + igt_spin_free(fd, spin[i]);
> > + }
> > +}
> > +
> > +igt_main
> > +{
> > + struct drm_xe_engine_class_instance *hwe;
> > + int fd;
> > + int gt, class;
> > +
> > + igt_fixture {
> > + fd = drm_open_driver(DRIVER_XE);
> > + xe_device_get(fd);
> > + }
> > +
> > + igt_subtest("spin-batch")
> > + xe_for_each_hw_engine(fd, hwe)
>
> I think, this loop should be handled inside the xe spin helper (like
> spin_create()). Since KMS also trying to use the same helper & really don't
> care about hardware engines.
You mean to mimic ALL_ENGINES flag? Makes sense for me. Without flag we
may try to pick blitter as it should work on all platforms (if it won't
we may pick first engine from xe engines exposed to userspace).
--
Zbigniew
>
> - Bhanu
>
> > + spin(fd, hwe);
> > +
> > + igt_subtest("spin-all") {
> > + xe_for_each_gt(fd, gt)
> > + xe_for_each_hw_engine_class(class)
> > + spin_all(fd, gt, class);
> > + }
> > +
> > + igt_fixture {
> > + xe_device_put(fd);
> > + close(fd);
> > + }
> > +}
> > +
> > +
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2023-05-25 5:46 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-22 12:36 [igt-dev] [PATCH i-g-t 0/2] Integrate igt_spin_new with Xe sai.gowtham.ch
2023-05-22 12:36 ` [igt-dev] [PATCH i-g-t 1/2] lib/xe/xe_spin: " sai.gowtham.ch
2023-05-22 16:19 ` Zbigniew Kempczyński
2023-05-23 8:41 ` Ch, Sai Gowtham
2023-05-23 11:29 ` Zbigniew Kempczyński
2023-05-23 15:58 ` Zbigniew Kempczyński
2023-05-22 12:36 ` [igt-dev] [PATCH i-g-t 2/2] tests/xe/xe_spin_batch: Add new test to exercise igt_spin_new for xe sai.gowtham.ch
2023-05-24 7:11 ` Modem, Bhanuprakash
2023-05-24 19:47 ` Ch, Sai Gowtham
2023-05-25 5:46 ` Zbigniew Kempczyński
2023-05-22 13:45 ` [igt-dev] ✓ Fi.CI.BAT: success for Integrate igt_spin_new with Xe Patchwork
2023-05-22 19:28 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
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