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From: Dan Williams <dan.j.williams@intel.com>
To: linux-cxl@vger.kernel.org
Cc: ira.weiny@intel.com, navneet.singh@intel.com
Subject: [PATCH 19/19] tools/testing/cxl: Emulate a CXL accelerator with local memory
Date: Sun, 04 Jun 2023 16:33:23 -0700	[thread overview]
Message-ID: <168592160379.1948938.12863272903570476312.stgit@dwillia2-xfh.jf.intel.com> (raw)
In-Reply-To: <168592149709.1948938.8663425987110396027.stgit@dwillia2-xfh.jf.intel.com>

Mock-up a device that does not have a standard mailbox, i.e. a device
that does not implement the CXL memory-device class code, but wants to
map "device" memory (aka Type-2, aka HDM-D[B], aka accelerator memory).

For extra code coverage make this device an RCD to test region creation
flows in the presence of an RCH topology (memory device modeled as a
root-complex-integrated-endpoint RCIEP).

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
 drivers/cxl/core/memdev.c    |   15 +++++++
 drivers/cxl/cxlmem.h         |    1 
 tools/testing/cxl/test/cxl.c |   16 +++++++-
 tools/testing/cxl/test/mem.c |   85 +++++++++++++++++++++++++++++++++++++++++-
 4 files changed, 112 insertions(+), 5 deletions(-)

diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
index 859c43c340bb..5d1ba7a72567 100644
--- a/drivers/cxl/core/memdev.c
+++ b/drivers/cxl/core/memdev.c
@@ -467,6 +467,21 @@ static void detach_memdev(struct work_struct *work)
 	put_device(&cxlmd->dev);
 }
 
+struct cxl_dev_state *cxl_accel_state_create(struct device *dev)
+{
+	struct cxl_dev_state *cxlds;
+
+	cxlds = devm_kzalloc(dev, sizeof(*cxlds), GFP_KERNEL);
+	if (!cxlds)
+		return ERR_PTR(-ENOMEM);
+
+	cxlds->dev = dev;
+	cxlds->type = CXL_DEVTYPE_DEVMEM;
+
+	return cxlds;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_accel_state_create, CXL);
+
 static struct lock_class_key cxl_memdev_key;
 
 static struct cxl_memdev *cxl_memdev_alloc(struct cxl_dev_state *cxlds,
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index ad7f806549d3..89e560ea14c0 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -746,6 +746,7 @@ int cxl_await_media_ready(struct cxl_dev_state *cxlds);
 int cxl_enumerate_cmds(struct cxl_memdev_state *mds);
 int cxl_mem_create_range_info(struct cxl_memdev_state *mds);
 struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev);
+struct cxl_dev_state *cxl_accel_state_create(struct device *dev);
 void set_exclusive_cxl_commands(struct cxl_memdev_state *mds,
 				unsigned long *cmds);
 void clear_exclusive_cxl_commands(struct cxl_memdev_state *mds,
diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
index e3f1b2e88e3e..385cdeeab22c 100644
--- a/tools/testing/cxl/test/cxl.c
+++ b/tools/testing/cxl/test/cxl.c
@@ -278,7 +278,7 @@ static struct {
 			},
 			.interleave_ways = 0,
 			.granularity = 4,
-			.restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
+			.restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE2 |
 					ACPI_CEDT_CFMWS_RESTRICT_VOLATILE,
 			.qtg_id = 5,
 			.window_size = SZ_256M,
@@ -713,7 +713,19 @@ static void default_mock_decoder(struct cxl_decoder *cxld)
 
 	cxld->interleave_ways = 1;
 	cxld->interleave_granularity = 256;
-	cxld->target_type = CXL_DECODER_HOSTMEM;
+	if (is_endpoint_decoder(&cxld->dev)) {
+		struct cxl_endpoint_decoder *cxled;
+		struct cxl_dev_state *cxlds;
+		struct cxl_memdev *cxlmd;
+
+		cxled = to_cxl_endpoint_decoder(&cxld->dev);
+		cxlmd = cxled_to_memdev(cxled);
+		cxlds = cxlmd->cxlds;
+		if (cxlds->type == CXL_DEVTYPE_CLASSMEM)
+			cxld->target_type = CXL_DECODER_HOSTMEM;
+		else
+			cxld->target_type = CXL_DECODER_DEVMEM;
+	}
 	cxld->commit = mock_decoder_commit;
 	cxld->reset = mock_decoder_reset;
 }
diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c
index 6fb5718588f3..620bfcf5e5a5 100644
--- a/tools/testing/cxl/test/mem.c
+++ b/tools/testing/cxl/test/mem.c
@@ -1189,11 +1189,21 @@ static void label_area_release(void *lsa)
 	vfree(lsa);
 }
 
+#define CXL_MOCKMEM_RCD BIT(0)
+#define CXL_MOCKMEM_TYPE2 BIT(1)
+
 static bool is_rcd(struct platform_device *pdev)
 {
 	const struct platform_device_id *id = platform_get_device_id(pdev);
 
-	return !!id->driver_data;
+	return !!(id->driver_data & CXL_MOCKMEM_RCD);
+}
+
+static bool is_type2(struct platform_device *pdev)
+{
+	const struct platform_device_id *id = platform_get_device_id(pdev);
+
+	return !!(id->driver_data & CXL_MOCKMEM_TYPE2);
 }
 
 static ssize_t event_trigger_store(struct device *dev,
@@ -1205,7 +1215,7 @@ static ssize_t event_trigger_store(struct device *dev,
 }
 static DEVICE_ATTR_WO(event_trigger);
 
-static int cxl_mock_mem_probe(struct platform_device *pdev)
+static int __cxl_mock_mem_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct cxl_memdev *cxlmd;
@@ -1274,6 +1284,75 @@ static int cxl_mock_mem_probe(struct platform_device *pdev)
 	return 0;
 }
 
+static int cxl_mock_type2_probe(struct platform_device *pdev)
+{
+	struct cxl_endpoint_decoder *cxled;
+	struct device *dev = &pdev->dev;
+	struct cxl_root_decoder *cxlrd;
+	struct cxl_dev_state *cxlds;
+	struct cxl_port *endpoint;
+	struct cxl_memdev *cxlmd;
+	resource_size_t max = 0;
+	int rc;
+
+	cxlds = cxl_accel_state_create(dev);
+	if (IS_ERR(cxlds))
+		return PTR_ERR(cxlds);
+
+	cxlds->serial = pdev->id;
+	cxlds->component_reg_phys = CXL_RESOURCE_NONE;
+	cxlds->dpa_res = DEFINE_RES_MEM(0, DEV_SIZE);
+	cxlds->ram_res = DEFINE_RES_MEM_NAMED(0, DEV_SIZE, "ram");
+	cxlds->pmem_res = DEFINE_RES_MEM_NAMED(DEV_SIZE, 0, "pmem");
+	if (is_rcd(pdev))
+		cxlds->rcd = true;
+
+	rc = request_resource(&cxlds->dpa_res, &cxlds->ram_res);
+	if (rc)
+		return rc;
+
+	cxlmd = devm_cxl_add_memdev(cxlds);
+	if (IS_ERR(cxlmd))
+		return PTR_ERR(cxlmd);
+
+	endpoint = cxl_acquire_endpoint(cxlmd);
+	if (IS_ERR(endpoint))
+		return PTR_ERR(endpoint);
+
+	cxlrd = cxl_hpa_freespace(endpoint, &endpoint->host_bridge, 1,
+				  CXL_DECODER_F_RAM | CXL_DECODER_F_TYPE2,
+				  &max);
+
+	if (IS_ERR(cxlrd)) {
+		rc = PTR_ERR(cxlrd);
+		goto out;
+	}
+
+	cxled = cxl_request_dpa(endpoint, CXL_DECODER_RAM, 0, max);
+	if (IS_ERR(cxled)) {
+		rc = PTR_ERR(cxled);
+		goto out_cxlrd;
+	}
+
+	/* A real driver would do something with the returned region */
+	rc = PTR_ERR_OR_ZERO(cxl_create_region(cxlrd, &cxled, 1));
+
+	put_device(cxled_dev(cxled));
+out_cxlrd:
+	put_device(cxlrd_dev(cxlrd));
+out:
+	cxl_release_endpoint(cxlmd, endpoint);
+
+	return rc;
+}
+
+static int cxl_mock_mem_probe(struct platform_device *pdev)
+{
+	if (is_type2(pdev))
+		return cxl_mock_type2_probe(pdev);
+	return __cxl_mock_mem_probe(pdev);
+}
+
 static ssize_t security_lock_show(struct device *dev,
 				  struct device_attribute *attr, char *buf)
 {
@@ -1316,7 +1395,7 @@ ATTRIBUTE_GROUPS(cxl_mock_mem);
 
 static const struct platform_device_id cxl_mock_mem_ids[] = {
 	{ .name = "cxl_mem", 0 },
-	{ .name = "cxl_rcd", 1 },
+	{ .name = "cxl_rcd", CXL_MOCKMEM_RCD | CXL_MOCKMEM_TYPE2 },
 	{ },
 };
 MODULE_DEVICE_TABLE(platform, cxl_mock_mem_ids);


  parent reply	other threads:[~2023-06-04 23:33 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-04 23:31 [PATCH 00/19] cxl: Device memory setup Dan Williams
2023-06-04 23:31 ` [PATCH 01/19] cxl/regs: Clarify when a 'struct cxl_register_map' is input vs output Dan Williams
2023-06-05  8:46   ` Jonathan Cameron
2023-06-13 22:03   ` Dave Jiang
2023-06-04 23:31 ` [PATCH 02/19] tools/testing/cxl: Remove unused @cxlds argument Dan Williams
2023-06-06 10:53   ` Jonathan Cameron
2023-06-13 22:08   ` Dave Jiang
2023-06-04 23:31 ` [PATCH 03/19] cxl/mbox: Move mailbox related driver state to its own data structure Dan Williams
2023-06-06 11:10   ` Jonathan Cameron
2023-06-14  0:45     ` Dan Williams
2023-06-13 22:15   ` Dave Jiang
2023-06-04 23:31 ` [PATCH 04/19] cxl/memdev: Make mailbox functionality optional Dan Williams
2023-06-06 11:15   ` Jonathan Cameron
2023-06-13 20:53     ` Dan Williams
2023-06-04 23:32 ` [PATCH 05/19] cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTMEM, DEVMEM} Dan Williams
2023-06-06 11:21   ` Jonathan Cameron
2023-06-13 21:03     ` Dan Williams
2023-06-04 23:32 ` [PATCH 06/19] cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEM Dan Williams
2023-06-05  1:14   ` kernel test robot
2023-06-06 20:10     ` Dan Williams
2023-06-06 11:27   ` Jonathan Cameron
2023-06-13 21:23     ` Dan Williams
2023-06-13 22:32     ` Dan Williams
2023-06-14  9:15       ` Jonathan Cameron
2023-06-04 23:32 ` [PATCH 07/19] cxl/region: Manage decoder target_type at decoder-attach time Dan Williams
2023-06-06 12:36   ` Jonathan Cameron
2023-06-13 22:42   ` Dave Jiang
2023-06-04 23:32 ` [PATCH 08/19] cxl/port: Enumerate flit mode capability Dan Williams
2023-06-06 13:04   ` Jonathan Cameron
2023-06-14  1:06     ` Dan Williams
2023-06-04 23:32 ` [PATCH 09/19] cxl/memdev: Formalize endpoint port linkage Dan Williams
2023-06-06 13:26   ` Jonathan Cameron
     [not found]   ` <CGME20230607164756uscas1p2fb025e7f4de5094925cc25fc2ac45212@uscas1p2.samsung.com>
2023-06-07 16:47     ` Fan Ni
2023-06-13 22:59   ` Dave Jiang
2023-06-04 23:32 ` [PATCH 10/19] cxl/memdev: Indicate probe deferral Dan Williams
2023-06-06 13:54   ` Jonathan Cameron
2023-06-04 23:32 ` [PATCH 11/19] cxl/region: Factor out construct_region_{begin, end} and drop_region() for reuse Dan Williams
2023-06-06 14:29   ` Jonathan Cameron
2023-06-13 23:29   ` Dave Jiang
2023-06-04 23:32 ` [PATCH 12/19] cxl/region: Factor out interleave ways setup Dan Williams
2023-06-06 14:31   ` Jonathan Cameron
2023-06-13 23:30   ` Dave Jiang
2023-06-04 23:32 ` [PATCH 13/19] cxl/region: Factor out interleave granularity setup Dan Williams
2023-06-06 14:33   ` Jonathan Cameron
2023-06-13 23:42   ` Dave Jiang
2023-06-04 23:32 ` [PATCH 14/19] cxl/region: Clarify locking requirements of cxl_region_attach() Dan Williams
2023-06-06 14:35   ` Jonathan Cameron
2023-06-13 23:45   ` Dave Jiang
2023-06-04 23:33 ` [PATCH 15/19] cxl/region: Specify host-only vs device memory at region creation time Dan Williams
2023-06-06 14:42   ` Jonathan Cameron
2023-06-04 23:33 ` [PATCH 16/19] cxl/hdm: Define a driver interface for DPA allocation Dan Williams
2023-06-06 14:58   ` Jonathan Cameron
2023-06-13 23:53   ` Dave Jiang
2023-06-04 23:33 ` [PATCH 17/19] cxl/region: Define a driver interface for HPA free space enumeration Dan Williams
2023-06-06 15:23   ` Jonathan Cameron
2023-06-14  0:15   ` Dave Jiang
2023-06-04 23:33 ` [PATCH 18/19] cxl/region: Define a driver interface for region creation Dan Williams
2023-06-06 15:31   ` Jonathan Cameron
2023-06-04 23:33 ` Dan Williams [this message]
2023-06-06 15:34   ` [PATCH 19/19] tools/testing/cxl: Emulate a CXL accelerator with local memory Jonathan Cameron
2023-06-07 21:09   ` Vikram Sethi
2023-06-08 10:47     ` Jonathan Cameron
2023-06-08 14:34       ` Vikram Sethi
2023-06-08 15:22         ` Jonathan Cameron

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