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From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <ira.weiny@intel.com>,
	<navneet.singh@intel.com>
Subject: Re: [PATCH 04/19] cxl/memdev: Make mailbox functionality optional
Date: Tue, 6 Jun 2023 12:15:34 +0100	[thread overview]
Message-ID: <20230606121534.00003870@Huawei.com> (raw)
In-Reply-To: <168592151963.1948938.7831940219025967692.stgit@dwillia2-xfh.jf.intel.com>

On Sun, 04 Jun 2023 16:31:59 -0700
Dan Williams <dan.j.williams@intel.com> wrote:

> In support of the Linux CXL core scaling for a wider set of CXL devices,
> allow for the creation of memdevs with some memory device capabilities
> disabled. Specifically, allow for CXL devices outside of those claiming
> to be compliant with the generic CXL memory device class code, like
> vendor specific Type-2/3 devices that host CXL.mem. This implies, allow
> for the creation of memdevs that only support component-registers, not
> necessarily memory-device-registers (like mailbox registers). A memdev
> derived from a CXL endpoint that does not support generic class code
> expectations is tagged "CXL_DEVTYPE_DEVMEM", while a memdev derived from a
> class-code compliant endpoint is tagged "CXL_DEVTYPE_CLASSMEM".
> 
> The primary assumption of a CXL_DEVTYPE_DEVMEM memdev is that it
> optionally may not host a mailbox. Disable the command passthrough ioctl
> for memdevs that are not CXL_DEVTYPE_CLASSMEM, and return empty strings
> from memdev attributes associated with data retrieved via the
> class-device-standard IDENTIFY command. Note that empty strings were
> chosen over attribute visibility to maintain compatibility with shipping
> versions of cxl-cli that expect those attributes to always be present.
Hmm.  I'm not keen on this, but I guess we've ended up in this corner
so don't have much choice.

> 
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>

Trivial stuff inline.

> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index d3fe73d5ba4d..b8bdf7490d2c 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -254,6 +254,20 @@ struct cxl_poison_state {
>  	struct mutex lock;  /* Protect reads of poison list */
>  };
>  
> +/*
> + * enum cxl_devtype - delineate type-2 from a generic type-3 device
> + * @CXL_DEVTYPE_DEVMEM - Vendor specific CXL Type-2 device implementing HDM-D or

Bit of a naming collision with other uses of DEVMEM but I can't immediately think
of a better name so fair enough...

> + *			 HDM-DB, no expectation that this device implements a
> + *			 mailbox, or other memory-device-standard manageability
> + *			 flows.
no requirement that this device

Expectation is a bit strong the other way to my reading.  These device might well
implement some or all of that + other stuff that means they don't want to use the
class code.

> + * @CXL_DEVTYPE_CLASSMEM - Common class definition of a CXL Type-3 device with
> + *			   HDM-H and class-mandatory memory device registers
> + */
> +enum cxl_devtype {
> +	CXL_DEVTYPE_DEVMEM,
> +	CXL_DEVTYPE_CLASSMEM,
> +};
> +
>  /**
>   * struct cxl_dev_state - The driver device state
>   *
> @@ -273,6 +287,7 @@ struct cxl_poison_state {
>   * @component_reg_phys: register base of component registers
>   * @info: Cached DVSEC information about the device.
>   * @serial: PCIe Device Serial Number
> + * @type: Generic Memory Class device or Vendor Specific Memory device
>   */
>  struct cxl_dev_state {
>  	struct device *dev;
> @@ -286,6 +301,7 @@ struct cxl_dev_state {
>  	struct resource ram_res;
>  	resource_size_t component_reg_phys;
>  	u64 serial;
> +	enum cxl_devtype type;
>  };
>  
>  /**
> @@ -344,6 +360,8 @@ struct cxl_memdev_state {
>  static inline struct cxl_memdev_state *
>  to_cxl_memdev_state(struct cxl_dev_state *cxlds)
>  {
> +	if (cxlds->type != CXL_DEVTYPE_CLASSMEM)
> +		return NULL;
>  	return container_of(cxlds, struct cxl_memdev_state, cxlds);
>  }
>  
> 


  reply	other threads:[~2023-06-06 11:15 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-04 23:31 [PATCH 00/19] cxl: Device memory setup Dan Williams
2023-06-04 23:31 ` [PATCH 01/19] cxl/regs: Clarify when a 'struct cxl_register_map' is input vs output Dan Williams
2023-06-05  8:46   ` Jonathan Cameron
2023-06-13 22:03   ` Dave Jiang
2023-06-04 23:31 ` [PATCH 02/19] tools/testing/cxl: Remove unused @cxlds argument Dan Williams
2023-06-06 10:53   ` Jonathan Cameron
2023-06-13 22:08   ` Dave Jiang
2023-06-04 23:31 ` [PATCH 03/19] cxl/mbox: Move mailbox related driver state to its own data structure Dan Williams
2023-06-06 11:10   ` Jonathan Cameron
2023-06-14  0:45     ` Dan Williams
2023-06-13 22:15   ` Dave Jiang
2023-06-04 23:31 ` [PATCH 04/19] cxl/memdev: Make mailbox functionality optional Dan Williams
2023-06-06 11:15   ` Jonathan Cameron [this message]
2023-06-13 20:53     ` Dan Williams
2023-06-04 23:32 ` [PATCH 05/19] cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTMEM, DEVMEM} Dan Williams
2023-06-06 11:21   ` Jonathan Cameron
2023-06-13 21:03     ` Dan Williams
2023-06-04 23:32 ` [PATCH 06/19] cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEM Dan Williams
2023-06-05  1:14   ` kernel test robot
2023-06-06 20:10     ` Dan Williams
2023-06-06 11:27   ` Jonathan Cameron
2023-06-13 21:23     ` Dan Williams
2023-06-13 22:32     ` Dan Williams
2023-06-14  9:15       ` Jonathan Cameron
2023-06-04 23:32 ` [PATCH 07/19] cxl/region: Manage decoder target_type at decoder-attach time Dan Williams
2023-06-06 12:36   ` Jonathan Cameron
2023-06-13 22:42   ` Dave Jiang
2023-06-04 23:32 ` [PATCH 08/19] cxl/port: Enumerate flit mode capability Dan Williams
2023-06-06 13:04   ` Jonathan Cameron
2023-06-14  1:06     ` Dan Williams
2023-06-04 23:32 ` [PATCH 09/19] cxl/memdev: Formalize endpoint port linkage Dan Williams
2023-06-06 13:26   ` Jonathan Cameron
     [not found]   ` <CGME20230607164756uscas1p2fb025e7f4de5094925cc25fc2ac45212@uscas1p2.samsung.com>
2023-06-07 16:47     ` Fan Ni
2023-06-13 22:59   ` Dave Jiang
2023-06-04 23:32 ` [PATCH 10/19] cxl/memdev: Indicate probe deferral Dan Williams
2023-06-06 13:54   ` Jonathan Cameron
2023-06-04 23:32 ` [PATCH 11/19] cxl/region: Factor out construct_region_{begin, end} and drop_region() for reuse Dan Williams
2023-06-06 14:29   ` Jonathan Cameron
2023-06-13 23:29   ` Dave Jiang
2023-06-04 23:32 ` [PATCH 12/19] cxl/region: Factor out interleave ways setup Dan Williams
2023-06-06 14:31   ` Jonathan Cameron
2023-06-13 23:30   ` Dave Jiang
2023-06-04 23:32 ` [PATCH 13/19] cxl/region: Factor out interleave granularity setup Dan Williams
2023-06-06 14:33   ` Jonathan Cameron
2023-06-13 23:42   ` Dave Jiang
2023-06-04 23:32 ` [PATCH 14/19] cxl/region: Clarify locking requirements of cxl_region_attach() Dan Williams
2023-06-06 14:35   ` Jonathan Cameron
2023-06-13 23:45   ` Dave Jiang
2023-06-04 23:33 ` [PATCH 15/19] cxl/region: Specify host-only vs device memory at region creation time Dan Williams
2023-06-06 14:42   ` Jonathan Cameron
2023-06-04 23:33 ` [PATCH 16/19] cxl/hdm: Define a driver interface for DPA allocation Dan Williams
2023-06-06 14:58   ` Jonathan Cameron
2023-06-13 23:53   ` Dave Jiang
2023-06-04 23:33 ` [PATCH 17/19] cxl/region: Define a driver interface for HPA free space enumeration Dan Williams
2023-06-06 15:23   ` Jonathan Cameron
2023-06-14  0:15   ` Dave Jiang
2023-06-04 23:33 ` [PATCH 18/19] cxl/region: Define a driver interface for region creation Dan Williams
2023-06-06 15:31   ` Jonathan Cameron
2023-06-04 23:33 ` [PATCH 19/19] tools/testing/cxl: Emulate a CXL accelerator with local memory Dan Williams
2023-06-06 15:34   ` Jonathan Cameron
2023-06-07 21:09   ` Vikram Sethi
2023-06-08 10:47     ` Jonathan Cameron
2023-06-08 14:34       ` Vikram Sethi
2023-06-08 15:22         ` Jonathan Cameron

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