All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH] clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
@ 2023-06-14 13:47 ` Alibek Omarov
  0 siblings, 0 replies; 12+ messages in thread
From: Alibek Omarov @ 2023-06-14 13:47 UTC (permalink / raw)
  To: linux-rockchip
  Cc: a1ba.omarov, Michael Turquette, Stephen Boyd, Heiko Stuebner,
	Sascha Hauer, linux-clk, linux-arm-kernel, linux-kernel

PLL rate on RK356x is calculated through the simple formula:
((24000000 / _refdiv) * _fbdiv) / (_postdiv1 * _postdiv2)

The PLL rate setting for 78.75MHz seems to be copied from 96MHz
so this patch fixes it and configures it properly.

Signed-off-by: Alibek Omarov <a1ba.omarov@gmail.com>
Fixes: 842f4cb72639 ("clk: rockchip: Add more PLL rates for rk3568")
---
 drivers/clk/rockchip/clk-rk3568.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 5dae960af4ce..48b8d06c305c 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -82,7 +82,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
 	RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),
 	RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
 	RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
-	RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0),
+	RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),
 	RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
 	{ /* sentinel */ },
 };
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH] clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
@ 2023-06-14 13:47 ` Alibek Omarov
  0 siblings, 0 replies; 12+ messages in thread
From: Alibek Omarov @ 2023-06-14 13:47 UTC (permalink / raw)
  To: linux-rockchip
  Cc: a1ba.omarov, Michael Turquette, Stephen Boyd, Heiko Stuebner,
	Sascha Hauer, linux-clk, linux-arm-kernel, linux-kernel

PLL rate on RK356x is calculated through the simple formula:
((24000000 / _refdiv) * _fbdiv) / (_postdiv1 * _postdiv2)

The PLL rate setting for 78.75MHz seems to be copied from 96MHz
so this patch fixes it and configures it properly.

Signed-off-by: Alibek Omarov <a1ba.omarov@gmail.com>
Fixes: 842f4cb72639 ("clk: rockchip: Add more PLL rates for rk3568")
---
 drivers/clk/rockchip/clk-rk3568.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 5dae960af4ce..48b8d06c305c 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -82,7 +82,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
 	RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),
 	RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
 	RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
-	RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0),
+	RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),
 	RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
 	{ /* sentinel */ },
 };
-- 
2.34.1


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH] clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
@ 2023-06-14 13:47 ` Alibek Omarov
  0 siblings, 0 replies; 12+ messages in thread
From: Alibek Omarov @ 2023-06-14 13:47 UTC (permalink / raw)
  To: linux-rockchip
  Cc: a1ba.omarov, Michael Turquette, Stephen Boyd, Heiko Stuebner,
	Sascha Hauer, linux-clk, linux-arm-kernel, linux-kernel

PLL rate on RK356x is calculated through the simple formula:
((24000000 / _refdiv) * _fbdiv) / (_postdiv1 * _postdiv2)

The PLL rate setting for 78.75MHz seems to be copied from 96MHz
so this patch fixes it and configures it properly.

Signed-off-by: Alibek Omarov <a1ba.omarov@gmail.com>
Fixes: 842f4cb72639 ("clk: rockchip: Add more PLL rates for rk3568")
---
 drivers/clk/rockchip/clk-rk3568.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 5dae960af4ce..48b8d06c305c 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -82,7 +82,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
 	RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),
 	RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
 	RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
-	RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0),
+	RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),
 	RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
 	{ /* sentinel */ },
 };
-- 
2.34.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* Re: [PATCH] clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
  2023-06-14 13:47 ` Alibek Omarov
  (?)
@ 2023-06-20 12:53   ` Alibek Omarov
  -1 siblings, 0 replies; 12+ messages in thread
From: Alibek Omarov @ 2023-06-20 12:53 UTC (permalink / raw)
  To: linux-rockchip
  Cc: Michael Turquette, Stephen Boyd, Heiko Stuebner, Sascha Hauer,
	linux-clk, linux-arm-kernel, linux-kernel

bump

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH] clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
@ 2023-06-20 12:53   ` Alibek Omarov
  0 siblings, 0 replies; 12+ messages in thread
From: Alibek Omarov @ 2023-06-20 12:53 UTC (permalink / raw)
  To: linux-rockchip
  Cc: Michael Turquette, Stephen Boyd, Heiko Stuebner, Sascha Hauer,
	linux-clk, linux-arm-kernel, linux-kernel

bump

_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH] clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
@ 2023-06-20 12:53   ` Alibek Omarov
  0 siblings, 0 replies; 12+ messages in thread
From: Alibek Omarov @ 2023-06-20 12:53 UTC (permalink / raw)
  To: linux-rockchip
  Cc: Michael Turquette, Stephen Boyd, Heiko Stuebner, Sascha Hauer,
	linux-clk, linux-arm-kernel, linux-kernel

bump

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH] clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
  2023-06-14 13:47 ` Alibek Omarov
  (?)
@ 2023-06-26  9:36   ` Sascha Hauer
  -1 siblings, 0 replies; 12+ messages in thread
From: Sascha Hauer @ 2023-06-26  9:36 UTC (permalink / raw)
  To: Alibek Omarov
  Cc: linux-rockchip, Michael Turquette, Stephen Boyd, Heiko Stuebner,
	linux-clk, linux-arm-kernel, linux-kernel

On Wed, Jun 14, 2023 at 04:47:50PM +0300, Alibek Omarov wrote:
> PLL rate on RK356x is calculated through the simple formula:
> ((24000000 / _refdiv) * _fbdiv) / (_postdiv1 * _postdiv2)
> 
> The PLL rate setting for 78.75MHz seems to be copied from 96MHz
> so this patch fixes it and configures it properly.
> 
> Signed-off-by: Alibek Omarov <a1ba.omarov@gmail.com>
> Fixes: 842f4cb72639 ("clk: rockchip: Add more PLL rates for rk3568")

Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>

> ---
>  drivers/clk/rockchip/clk-rk3568.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
> index 5dae960af4ce..48b8d06c305c 100644
> --- a/drivers/clk/rockchip/clk-rk3568.c
> +++ b/drivers/clk/rockchip/clk-rk3568.c
> @@ -82,7 +82,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
>  	RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),
>  	RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
>  	RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
> -	RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0),
> +	RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),

refdiv = 4
fbdiv = 315
postdiv1 = 6
postdiv2 = 4

((24000000 / 4) * 315) / 6 / 4 = 78750000

LGTM

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH] clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
@ 2023-06-26  9:36   ` Sascha Hauer
  0 siblings, 0 replies; 12+ messages in thread
From: Sascha Hauer @ 2023-06-26  9:36 UTC (permalink / raw)
  To: Alibek Omarov
  Cc: linux-rockchip, Michael Turquette, Stephen Boyd, Heiko Stuebner,
	linux-clk, linux-arm-kernel, linux-kernel

On Wed, Jun 14, 2023 at 04:47:50PM +0300, Alibek Omarov wrote:
> PLL rate on RK356x is calculated through the simple formula:
> ((24000000 / _refdiv) * _fbdiv) / (_postdiv1 * _postdiv2)
> 
> The PLL rate setting for 78.75MHz seems to be copied from 96MHz
> so this patch fixes it and configures it properly.
> 
> Signed-off-by: Alibek Omarov <a1ba.omarov@gmail.com>
> Fixes: 842f4cb72639 ("clk: rockchip: Add more PLL rates for rk3568")

Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>

> ---
>  drivers/clk/rockchip/clk-rk3568.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
> index 5dae960af4ce..48b8d06c305c 100644
> --- a/drivers/clk/rockchip/clk-rk3568.c
> +++ b/drivers/clk/rockchip/clk-rk3568.c
> @@ -82,7 +82,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
>  	RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),
>  	RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
>  	RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
> -	RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0),
> +	RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),

refdiv = 4
fbdiv = 315
postdiv1 = 6
postdiv2 = 4

((24000000 / 4) * 315) / 6 / 4 = 78750000

LGTM

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH] clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
@ 2023-06-26  9:36   ` Sascha Hauer
  0 siblings, 0 replies; 12+ messages in thread
From: Sascha Hauer @ 2023-06-26  9:36 UTC (permalink / raw)
  To: Alibek Omarov
  Cc: linux-rockchip, Michael Turquette, Stephen Boyd, Heiko Stuebner,
	linux-clk, linux-arm-kernel, linux-kernel

On Wed, Jun 14, 2023 at 04:47:50PM +0300, Alibek Omarov wrote:
> PLL rate on RK356x is calculated through the simple formula:
> ((24000000 / _refdiv) * _fbdiv) / (_postdiv1 * _postdiv2)
> 
> The PLL rate setting for 78.75MHz seems to be copied from 96MHz
> so this patch fixes it and configures it properly.
> 
> Signed-off-by: Alibek Omarov <a1ba.omarov@gmail.com>
> Fixes: 842f4cb72639 ("clk: rockchip: Add more PLL rates for rk3568")

Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>

> ---
>  drivers/clk/rockchip/clk-rk3568.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
> index 5dae960af4ce..48b8d06c305c 100644
> --- a/drivers/clk/rockchip/clk-rk3568.c
> +++ b/drivers/clk/rockchip/clk-rk3568.c
> @@ -82,7 +82,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
>  	RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),
>  	RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
>  	RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
> -	RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0),
> +	RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),

refdiv = 4
fbdiv = 315
postdiv1 = 6
postdiv2 = 4

((24000000 / 4) * 315) / 6 / 4 = 78750000

LGTM

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH] clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
  2023-06-14 13:47 ` Alibek Omarov
  (?)
@ 2023-06-26 10:57   ` Heiko Stuebner
  -1 siblings, 0 replies; 12+ messages in thread
From: Heiko Stuebner @ 2023-06-26 10:57 UTC (permalink / raw)
  To: linux-rockchip, Alibek Omarov
  Cc: Heiko Stuebner, Sascha Hauer, Michael Turquette, Stephen Boyd,
	linux-kernel, linux-arm-kernel, linux-clk

On Wed, 14 Jun 2023 16:47:50 +0300, Alibek Omarov wrote:
> PLL rate on RK356x is calculated through the simple formula:
> ((24000000 / _refdiv) * _fbdiv) / (_postdiv1 * _postdiv2)
> 
> The PLL rate setting for 78.75MHz seems to be copied from 96MHz
> so this patch fixes it and configures it properly.
> 
> 
> [...]

Applied, thanks!

[1/1] clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
      commit: 17c6d0c5f2a4dd3f48e300d77c93780d5c36a37e

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH] clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
@ 2023-06-26 10:57   ` Heiko Stuebner
  0 siblings, 0 replies; 12+ messages in thread
From: Heiko Stuebner @ 2023-06-26 10:57 UTC (permalink / raw)
  To: linux-rockchip, Alibek Omarov
  Cc: Heiko Stuebner, Sascha Hauer, Michael Turquette, Stephen Boyd,
	linux-kernel, linux-arm-kernel, linux-clk

On Wed, 14 Jun 2023 16:47:50 +0300, Alibek Omarov wrote:
> PLL rate on RK356x is calculated through the simple formula:
> ((24000000 / _refdiv) * _fbdiv) / (_postdiv1 * _postdiv2)
> 
> The PLL rate setting for 78.75MHz seems to be copied from 96MHz
> so this patch fixes it and configures it properly.
> 
> 
> [...]

Applied, thanks!

[1/1] clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
      commit: 17c6d0c5f2a4dd3f48e300d77c93780d5c36a37e

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH] clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
@ 2023-06-26 10:57   ` Heiko Stuebner
  0 siblings, 0 replies; 12+ messages in thread
From: Heiko Stuebner @ 2023-06-26 10:57 UTC (permalink / raw)
  To: linux-rockchip, Alibek Omarov
  Cc: Heiko Stuebner, Sascha Hauer, Michael Turquette, Stephen Boyd,
	linux-kernel, linux-arm-kernel, linux-clk

On Wed, 14 Jun 2023 16:47:50 +0300, Alibek Omarov wrote:
> PLL rate on RK356x is calculated through the simple formula:
> ((24000000 / _refdiv) * _fbdiv) / (_postdiv1 * _postdiv2)
> 
> The PLL rate setting for 78.75MHz seems to be copied from 96MHz
> so this patch fixes it and configures it properly.
> 
> 
> [...]

Applied, thanks!

[1/1] clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
      commit: 17c6d0c5f2a4dd3f48e300d77c93780d5c36a37e

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 12+ messages in thread
end of thread, other threads:[~2023-06-26 10:58 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-06-14 13:47 [PATCH] clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz Alibek Omarov
2023-06-14 13:47 ` Alibek Omarov
2023-06-14 13:47 ` Alibek Omarov
2023-06-20 12:53 ` Alibek Omarov
2023-06-20 12:53   ` Alibek Omarov
2023-06-20 12:53   ` Alibek Omarov
2023-06-26  9:36 ` Sascha Hauer
2023-06-26  9:36   ` Sascha Hauer
2023-06-26  9:36   ` Sascha Hauer
2023-06-26 10:57 ` Heiko Stuebner
2023-06-26 10:57   ` Heiko Stuebner
2023-06-26 10:57   ` Heiko Stuebner

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.