* [Intel-gfx] [PATCH i-g-t 1/2] lib/igt_dummyload: Extract sync spinner API
@ 2023-07-11 16:02 ` Tvrtko Ursulin
0 siblings, 0 replies; 19+ messages in thread
From: Tvrtko Ursulin @ 2023-07-11 16:02 UTC (permalink / raw)
To: igt-dev, Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Sync spinner API is identical and compatible with regular spinners just
that it tries to make sure spinner is actually running on the hardware
before returning from the constructor.
A few tests already use it, one more will, so lets promote it into
common library.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
---
lib/igt_dummyload.c | 105 ++++++++++++++++++++++++++++++++++++++++
lib/igt_dummyload.h | 11 +++++
tests/i915/drm_fdinfo.c | 81 ++++---------------------------
tests/i915/gem_eio.c | 15 ++----
tests/i915/perf_pmu.c | 84 +++++---------------------------
5 files changed, 140 insertions(+), 156 deletions(-)
diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 9f941cef73e6..d3cee91540b6 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -33,6 +33,7 @@
#include "drmtest.h"
#include "i915/gem_create.h"
#include "i915/gem_engine_topology.h"
+#include "i915/gem.h"
#include "i915/gem_mman.h"
#include "i915/gem_submission.h"
#include "igt_aux.h"
@@ -715,6 +716,110 @@ void igt_unshare_spins(void)
IGT_INIT_LIST_HEAD(&spin_list);
}
+/**
+ * __igt_sync_spin_poll:
+ * @i915: open i915 drm file descriptor
+ * @ahnd: allocator handle
+ * @ctx: intel_ctx_t context
+ * @e: engine to execute on
+ *
+ * Starts a recursive batch on an engine.
+ *
+ * Returns a #igt_spin_t which can be used with both standard and igt_sync_spin
+ * API family. Callers should consult @gem_class_can_store_dword to whether
+ * the target platform+engine can reliably support the igt_sync_spin API.
+ */
+igt_spin_t *
+__igt_sync_spin_poll(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e)
+{
+ struct igt_spin_factory opts = {
+ .ahnd = ahnd,
+ .ctx = ctx,
+ .engine = e ? e->flags : 0,
+ };
+
+ if (!e || gem_class_can_store_dword(i915, e->class))
+ opts.flags |= IGT_SPIN_POLL_RUN;
+
+ return __igt_spin_factory(i915, &opts);
+}
+
+/**
+ * __igt_sync_spin_wait:
+ * @i915: open i915 drm file descriptor
+ * @spin: previously create sync spinner
+ *
+ * Waits for a spinner to be running on the hardware.
+ *
+ * Callers should consult @gem_class_can_store_dword to whether the target
+ * platform+engine can reliably support the igt_sync_spin API.
+ */
+unsigned long __igt_sync_spin_wait(int i915, igt_spin_t *spin)
+{
+ struct timespec start = { };
+
+ igt_nsec_elapsed(&start);
+
+ if (igt_spin_has_poll(spin)) {
+ unsigned long timeout = 0;
+
+ while (!igt_spin_has_started(spin)) {
+ unsigned long t = igt_nsec_elapsed(&start);
+
+ igt_assert(gem_bo_busy(i915, spin->handle));
+ if ((t - timeout) > 250e6) {
+ timeout = t;
+ igt_warn("Spinner not running after %.2fms\n",
+ (double)t / 1e6);
+ igt_assert(t < 2e9);
+ }
+ }
+ } else {
+ igt_debug("__spin_wait - usleep mode\n");
+ usleep(500e3); /* Better than nothing! */
+ }
+
+ igt_assert(gem_bo_busy(i915, spin->handle));
+ return igt_nsec_elapsed(&start);
+}
+
+igt_spin_t *
+__igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e)
+{
+ igt_spin_t *spin = __igt_sync_spin_poll(i915, ahnd, ctx, e);
+
+ __igt_sync_spin_wait(i915, spin);
+
+ return spin;
+}
+
+/**
+ * igt_sync_spin:
+ * @i915: open i915 drm file descriptor
+ * @ahnd: allocator handle
+ * @ctx: intel_ctx_t context
+ * @e: engine to execute on
+ *
+ * Starts a recursive batch on an engine.
+ *
+ * Returns a #igt_spin_t and tries to guarantee it to be running at the time of
+ * the return. Otherwise it does a best effort only. Callers should check for
+ * @gem_class_can_store_dword if they want to be sure guarantee can be given.
+ *
+ * Both standard and igt_sync_spin API family can be used on the returned
+ * spinner object.
+ */
+igt_spin_t *
+igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e)
+{
+ igt_require_gem(i915);
+
+ return __igt_sync_spin(i915, ahnd, ctx, e);
+}
+
static uint32_t plug_vgem_handle(struct igt_cork *cork, int fd)
{
struct vgem_bo bo;
diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
index 6eb3f2e696bb..b771011af74f 100644
--- a/lib/igt_dummyload.h
+++ b/lib/igt_dummyload.h
@@ -143,6 +143,17 @@ void igt_terminate_spins(void);
void igt_unshare_spins(void);
void igt_free_spins(int i915);
+struct intel_execution_engine2;
+
+igt_spin_t *__igt_sync_spin_poll(int i915, uint64_t ahnd,
+ const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e);
+unsigned long __igt_sync_spin_wait(int i915, igt_spin_t *spin);
+igt_spin_t *__igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e);
+igt_spin_t *igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e);
+
enum igt_cork_type {
CORK_SYNC_FD = 1,
CORK_VGEM_HANDLE
diff --git a/tests/i915/drm_fdinfo.c b/tests/i915/drm_fdinfo.c
index c0e0ba1905f1..5cafa0e469e2 100644
--- a/tests/i915/drm_fdinfo.c
+++ b/tests/i915/drm_fdinfo.c
@@ -138,68 +138,6 @@ static unsigned int measured_usleep(unsigned int usec)
#define FLAG_HANG (8)
#define TEST_ISOLATION (16)
-static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
- const struct intel_execution_engine2 *e)
-{
- struct igt_spin_factory opts = {
- .ahnd = ahnd,
- .ctx = ctx,
- .engine = e ? e->flags : 0,
- };
-
- if (!e || gem_class_can_store_dword(fd, e->class))
- opts.flags |= IGT_SPIN_POLL_RUN;
-
- return __igt_spin_factory(fd, &opts);
-}
-
-static unsigned long __spin_wait(int fd, igt_spin_t *spin)
-{
- struct timespec start = { };
-
- igt_nsec_elapsed(&start);
-
- if (igt_spin_has_poll(spin)) {
- unsigned long timeout = 0;
-
- while (!igt_spin_has_started(spin)) {
- unsigned long t = igt_nsec_elapsed(&start);
-
- igt_assert(gem_bo_busy(fd, spin->handle));
- if ((t - timeout) > 250e6) {
- timeout = t;
- igt_warn("Spinner not running after %.2fms\n",
- (double)t / 1e6);
- igt_assert(t < 2e9);
- }
- }
- } else {
- igt_debug("__spin_wait - usleep mode\n");
- usleep(500e3); /* Better than nothing! */
- }
-
- igt_assert(gem_bo_busy(fd, spin->handle));
- return igt_nsec_elapsed(&start);
-}
-
-static igt_spin_t *__spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
- const struct intel_execution_engine2 *e)
-{
- igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, e);
-
- __spin_wait(fd, spin);
-
- return spin;
-}
-
-static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
- const struct intel_execution_engine2 *e)
-{
- igt_require_gem(fd);
-
- return __spin_sync(fd, ahnd, ctx, e);
-}
-
static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
{
if (!spin)
@@ -264,7 +202,7 @@ single(int gem_fd, const intel_ctx_t *ctx,
ahnd = get_reloc_ahnd(spin_fd, ctx->id);
if (flags & TEST_BUSY)
- spin = spin_sync(spin_fd, ahnd, ctx, e);
+ spin = igt_sync_spin(spin_fd, ahnd, ctx, e);
else
spin = NULL;
@@ -349,7 +287,7 @@ busy_check_all(int gem_fd, const intel_ctx_t *ctx,
memset(tval, 0, sizeof(tval));
- spin = spin_sync(gem_fd, ahnd, ctx, e);
+ spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
read_busy_all(gem_fd, tval[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -418,14 +356,14 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
__submit_spin(gem_fd, spin, e_, 64);
busy_class[e_->class]++;
} else {
- spin = __spin_poll(gem_fd, ahnd, ctx, e_);
+ spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e_);
busy_class[e_->class]++;
}
}
igt_require(spin); /* at least one busy engine */
/* Small delay to allow engines to start. */
- usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
+ usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
read_busy_all(gem_fd, tval[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -475,12 +413,12 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
if (spin)
__submit_spin(gem_fd, spin, e, 64);
else
- spin = __spin_poll(gem_fd, ahnd, ctx, e);
+ spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e);
busy_class[e->class]++;
}
/* Small delay to allow engines to start. */
- usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
+ usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
read_busy_all(gem_fd, tval[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -624,7 +562,7 @@ virtual(int i915, const intel_ctx_cfg_t *base_cfg, unsigned int flags)
ahnd = get_reloc_ahnd(i915, ctx->id);
if (flags & TEST_BUSY)
- spin = spin_sync(i915, ahnd, ctx, NULL);
+ spin = igt_sync_spin(i915, ahnd, ctx, NULL);
else
spin = NULL;
@@ -732,11 +670,12 @@ virtual_all(int i915, const intel_ctx_cfg_t *base_cfg, unsigned int flags)
if (spin)
__virt_submit_spin(i915, spin, ctx[i], 64);
else
- spin = __spin_poll(i915, ahnd, ctx[i], NULL);
+ spin = __igt_sync_spin_poll(i915, ahnd, ctx[i],
+ NULL);
}
/* Small delay to allow engines to start. */
- usleep(__spin_wait(i915, spin) * count / 1e3);
+ usleep(__igt_sync_spin_wait(i915, spin) * count / 1e3);
val = read_busy(i915, class);
slept = measured_usleep(batch_duration_ns / 1000);
diff --git a/tests/i915/gem_eio.c b/tests/i915/gem_eio.c
index d889d67dcebd..6d4b8f7df909 100644
--- a/tests/i915/gem_eio.c
+++ b/tests/i915/gem_eio.c
@@ -47,6 +47,7 @@
#include "i915/gem_ring.h"
#include "igt.h"
#include "igt_device.h"
+#include "igt_dummyload.h"
#include "igt_fb.h"
#include "igt_kms.h"
#include "igt_stats.h"
@@ -429,22 +430,12 @@ static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
return __igt_spin_factory(fd, &opts);
}
-static void __spin_wait(int fd, igt_spin_t *spin)
-{
- if (igt_spin_has_poll(spin)) {
- igt_spin_busywait_until_started(spin);
- } else {
- igt_debug("__spin_wait - usleep mode\n");
- usleep(500e3); /* Better than nothing! */
- }
-}
-
static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
unsigned long flags)
{
igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, flags);
- __spin_wait(fd, spin);
+ __igt_sync_spin_wait(fd, spin);
return spin;
}
@@ -963,7 +954,7 @@ static void test_inflight_external(int fd)
fence = execbuf.rsvd2 >> 32;
igt_assert(fence != -1);
- __spin_wait(fd, hang);
+ __igt_sync_spin_wait(fd, hang);
manual_hang(fd);
gem_sync(fd, hang->handle); /* wedged, with an unready batch */
diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
index 0806a8e545b5..a888027ad9af 100644
--- a/tests/i915/perf_pmu.c
+++ b/tests/i915/perf_pmu.c
@@ -377,68 +377,6 @@ static unsigned int measured_usleep(unsigned int usec)
#define TEST_OTHER (128)
#define TEST_ALL (256)
-static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
- const struct intel_execution_engine2 *e)
-{
- struct igt_spin_factory opts = {
- .ahnd = ahnd,
- .ctx = ctx,
- .engine = e->flags,
- };
-
- if (gem_class_can_store_dword(fd, e->class))
- opts.flags |= IGT_SPIN_POLL_RUN;
-
- return __igt_spin_factory(fd, &opts);
-}
-
-static unsigned long __spin_wait(int fd, igt_spin_t *spin)
-{
- struct timespec start = { };
-
- igt_nsec_elapsed(&start);
-
- if (igt_spin_has_poll(spin)) {
- unsigned long timeout = 0;
-
- while (!igt_spin_has_started(spin)) {
- unsigned long t = igt_nsec_elapsed(&start);
-
- igt_assert(gem_bo_busy(fd, spin->handle));
- if ((t - timeout) > 250e6) {
- timeout = t;
- igt_warn("Spinner not running after %.2fms\n",
- (double)t / 1e6);
- igt_assert(t < 2e9);
- }
- }
- } else {
- igt_debug("__spin_wait - usleep mode\n");
- usleep(500e3); /* Better than nothing! */
- }
-
- igt_assert(gem_bo_busy(fd, spin->handle));
- return igt_nsec_elapsed(&start);
-}
-
-static igt_spin_t *__spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
- const struct intel_execution_engine2 *e)
-{
- igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, e);
-
- __spin_wait(fd, spin);
-
- return spin;
-}
-
-static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
- const struct intel_execution_engine2 *e)
-{
- igt_require_gem(fd);
-
- return __spin_sync(fd, ahnd, ctx, e);
-}
-
static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
{
if (!spin)
@@ -484,7 +422,7 @@ single(int gem_fd, const intel_ctx_t *ctx,
fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
if (flags & TEST_BUSY)
- spin = spin_sync(gem_fd, ahnd, ctx, e);
+ spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
else
spin = NULL;
@@ -536,7 +474,7 @@ busy_start(int gem_fd, const intel_ctx_t *ctx,
*/
sleep(2);
- spin = __spin_sync(gem_fd, ahnd, ctx, e);
+ spin = __igt_sync_spin(gem_fd, ahnd, ctx, e);
fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
@@ -583,7 +521,7 @@ busy_double_start(int gem_fd, const intel_ctx_t *ctx,
* re-submission in execlists mode. Make sure busyness is correctly
* reported with the engine busy, and after the engine went idle.
*/
- spin[0] = __spin_sync(gem_fd, ahnd, ctx, e);
+ spin[0] = __igt_sync_spin(gem_fd, ahnd, ctx, e);
usleep(500e3);
spin[1] = __igt_spin_new(gem_fd,
.ahnd = ahndN,
@@ -675,7 +613,7 @@ busy_check_all(int gem_fd, const intel_ctx_t *ctx,
igt_assert_eq(i, num_engines);
- spin = spin_sync(gem_fd, ahnd, ctx, e);
+ spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
pmu_read_multi(fd[0], num_engines, tval[0]);
slept = measured_usleep(batch_duration_ns / 1000);
if (flags & TEST_TRAILING_IDLE)
@@ -737,7 +675,7 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
else if (spin)
__submit_spin(gem_fd, spin, e_, 64);
else
- spin = __spin_poll(gem_fd, ahnd, ctx, e_);
+ spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e_);
val[i++] = I915_PMU_ENGINE_BUSY(e_->class, e_->instance);
}
@@ -749,7 +687,7 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
fd[i] = open_group(gem_fd, val[i], fd[0]);
/* Small delay to allow engines to start. */
- usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
+ usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
pmu_read_multi(fd[0], num_engines, tval[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -796,7 +734,7 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
if (spin)
__submit_spin(gem_fd, spin, e, 64);
else
- spin = __spin_poll(gem_fd, ahnd, ctx, e);
+ spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e);
val[i++] = I915_PMU_ENGINE_BUSY(e->class, e->instance);
}
@@ -807,7 +745,7 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
fd[i] = open_group(gem_fd, val[i], fd[0]);
/* Small delay to allow engines to start. */
- usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
+ usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
pmu_read_multi(fd[0], num_engines, tval[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -848,7 +786,7 @@ no_sema(int gem_fd, const intel_ctx_t *ctx,
fd[0]);
if (flags & TEST_BUSY)
- spin = spin_sync(gem_fd, ahnd, ctx, e);
+ spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
else
spin = NULL;
@@ -1406,7 +1344,7 @@ multi_client(int gem_fd, const intel_ctx_t *ctx,
*/
fd[1] = open_pmu(gem_fd, config);
- spin = spin_sync(gem_fd, ahnd, ctx, e);
+ spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
val[0] = val[1] = __pmu_read_single(fd[0], &ts[0]);
slept[1] = measured_usleep(batch_duration_ns / 1000);
@@ -1776,7 +1714,7 @@ static igt_spin_t *spin_sync_gt(int i915, uint64_t ahnd, unsigned int gt,
igt_debug("Using engine %u:%u\n", e.class, e.instance);
- return spin_sync(i915, ahnd, *ctx, &e);
+ return igt_sync_spin(i915, ahnd, *ctx, &e);
}
static void
--
2.39.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [igt-dev] [PATCH i-g-t 1/2] lib/igt_dummyload: Extract sync spinner API
@ 2023-07-11 16:02 ` Tvrtko Ursulin
0 siblings, 0 replies; 19+ messages in thread
From: Tvrtko Ursulin @ 2023-07-11 16:02 UTC (permalink / raw)
To: igt-dev, Intel-gfx; +Cc: Tvrtko Ursulin
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Sync spinner API is identical and compatible with regular spinners just
that it tries to make sure spinner is actually running on the hardware
before returning from the constructor.
A few tests already use it, one more will, so lets promote it into
common library.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
---
lib/igt_dummyload.c | 105 ++++++++++++++++++++++++++++++++++++++++
lib/igt_dummyload.h | 11 +++++
tests/i915/drm_fdinfo.c | 81 ++++---------------------------
tests/i915/gem_eio.c | 15 ++----
tests/i915/perf_pmu.c | 84 +++++---------------------------
5 files changed, 140 insertions(+), 156 deletions(-)
diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
index 9f941cef73e6..d3cee91540b6 100644
--- a/lib/igt_dummyload.c
+++ b/lib/igt_dummyload.c
@@ -33,6 +33,7 @@
#include "drmtest.h"
#include "i915/gem_create.h"
#include "i915/gem_engine_topology.h"
+#include "i915/gem.h"
#include "i915/gem_mman.h"
#include "i915/gem_submission.h"
#include "igt_aux.h"
@@ -715,6 +716,110 @@ void igt_unshare_spins(void)
IGT_INIT_LIST_HEAD(&spin_list);
}
+/**
+ * __igt_sync_spin_poll:
+ * @i915: open i915 drm file descriptor
+ * @ahnd: allocator handle
+ * @ctx: intel_ctx_t context
+ * @e: engine to execute on
+ *
+ * Starts a recursive batch on an engine.
+ *
+ * Returns a #igt_spin_t which can be used with both standard and igt_sync_spin
+ * API family. Callers should consult @gem_class_can_store_dword to whether
+ * the target platform+engine can reliably support the igt_sync_spin API.
+ */
+igt_spin_t *
+__igt_sync_spin_poll(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e)
+{
+ struct igt_spin_factory opts = {
+ .ahnd = ahnd,
+ .ctx = ctx,
+ .engine = e ? e->flags : 0,
+ };
+
+ if (!e || gem_class_can_store_dword(i915, e->class))
+ opts.flags |= IGT_SPIN_POLL_RUN;
+
+ return __igt_spin_factory(i915, &opts);
+}
+
+/**
+ * __igt_sync_spin_wait:
+ * @i915: open i915 drm file descriptor
+ * @spin: previously create sync spinner
+ *
+ * Waits for a spinner to be running on the hardware.
+ *
+ * Callers should consult @gem_class_can_store_dword to whether the target
+ * platform+engine can reliably support the igt_sync_spin API.
+ */
+unsigned long __igt_sync_spin_wait(int i915, igt_spin_t *spin)
+{
+ struct timespec start = { };
+
+ igt_nsec_elapsed(&start);
+
+ if (igt_spin_has_poll(spin)) {
+ unsigned long timeout = 0;
+
+ while (!igt_spin_has_started(spin)) {
+ unsigned long t = igt_nsec_elapsed(&start);
+
+ igt_assert(gem_bo_busy(i915, spin->handle));
+ if ((t - timeout) > 250e6) {
+ timeout = t;
+ igt_warn("Spinner not running after %.2fms\n",
+ (double)t / 1e6);
+ igt_assert(t < 2e9);
+ }
+ }
+ } else {
+ igt_debug("__spin_wait - usleep mode\n");
+ usleep(500e3); /* Better than nothing! */
+ }
+
+ igt_assert(gem_bo_busy(i915, spin->handle));
+ return igt_nsec_elapsed(&start);
+}
+
+igt_spin_t *
+__igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e)
+{
+ igt_spin_t *spin = __igt_sync_spin_poll(i915, ahnd, ctx, e);
+
+ __igt_sync_spin_wait(i915, spin);
+
+ return spin;
+}
+
+/**
+ * igt_sync_spin:
+ * @i915: open i915 drm file descriptor
+ * @ahnd: allocator handle
+ * @ctx: intel_ctx_t context
+ * @e: engine to execute on
+ *
+ * Starts a recursive batch on an engine.
+ *
+ * Returns a #igt_spin_t and tries to guarantee it to be running at the time of
+ * the return. Otherwise it does a best effort only. Callers should check for
+ * @gem_class_can_store_dword if they want to be sure guarantee can be given.
+ *
+ * Both standard and igt_sync_spin API family can be used on the returned
+ * spinner object.
+ */
+igt_spin_t *
+igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e)
+{
+ igt_require_gem(i915);
+
+ return __igt_sync_spin(i915, ahnd, ctx, e);
+}
+
static uint32_t plug_vgem_handle(struct igt_cork *cork, int fd)
{
struct vgem_bo bo;
diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
index 6eb3f2e696bb..b771011af74f 100644
--- a/lib/igt_dummyload.h
+++ b/lib/igt_dummyload.h
@@ -143,6 +143,17 @@ void igt_terminate_spins(void);
void igt_unshare_spins(void);
void igt_free_spins(int i915);
+struct intel_execution_engine2;
+
+igt_spin_t *__igt_sync_spin_poll(int i915, uint64_t ahnd,
+ const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e);
+unsigned long __igt_sync_spin_wait(int i915, igt_spin_t *spin);
+igt_spin_t *__igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e);
+igt_spin_t *igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e);
+
enum igt_cork_type {
CORK_SYNC_FD = 1,
CORK_VGEM_HANDLE
diff --git a/tests/i915/drm_fdinfo.c b/tests/i915/drm_fdinfo.c
index c0e0ba1905f1..5cafa0e469e2 100644
--- a/tests/i915/drm_fdinfo.c
+++ b/tests/i915/drm_fdinfo.c
@@ -138,68 +138,6 @@ static unsigned int measured_usleep(unsigned int usec)
#define FLAG_HANG (8)
#define TEST_ISOLATION (16)
-static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
- const struct intel_execution_engine2 *e)
-{
- struct igt_spin_factory opts = {
- .ahnd = ahnd,
- .ctx = ctx,
- .engine = e ? e->flags : 0,
- };
-
- if (!e || gem_class_can_store_dword(fd, e->class))
- opts.flags |= IGT_SPIN_POLL_RUN;
-
- return __igt_spin_factory(fd, &opts);
-}
-
-static unsigned long __spin_wait(int fd, igt_spin_t *spin)
-{
- struct timespec start = { };
-
- igt_nsec_elapsed(&start);
-
- if (igt_spin_has_poll(spin)) {
- unsigned long timeout = 0;
-
- while (!igt_spin_has_started(spin)) {
- unsigned long t = igt_nsec_elapsed(&start);
-
- igt_assert(gem_bo_busy(fd, spin->handle));
- if ((t - timeout) > 250e6) {
- timeout = t;
- igt_warn("Spinner not running after %.2fms\n",
- (double)t / 1e6);
- igt_assert(t < 2e9);
- }
- }
- } else {
- igt_debug("__spin_wait - usleep mode\n");
- usleep(500e3); /* Better than nothing! */
- }
-
- igt_assert(gem_bo_busy(fd, spin->handle));
- return igt_nsec_elapsed(&start);
-}
-
-static igt_spin_t *__spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
- const struct intel_execution_engine2 *e)
-{
- igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, e);
-
- __spin_wait(fd, spin);
-
- return spin;
-}
-
-static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
- const struct intel_execution_engine2 *e)
-{
- igt_require_gem(fd);
-
- return __spin_sync(fd, ahnd, ctx, e);
-}
-
static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
{
if (!spin)
@@ -264,7 +202,7 @@ single(int gem_fd, const intel_ctx_t *ctx,
ahnd = get_reloc_ahnd(spin_fd, ctx->id);
if (flags & TEST_BUSY)
- spin = spin_sync(spin_fd, ahnd, ctx, e);
+ spin = igt_sync_spin(spin_fd, ahnd, ctx, e);
else
spin = NULL;
@@ -349,7 +287,7 @@ busy_check_all(int gem_fd, const intel_ctx_t *ctx,
memset(tval, 0, sizeof(tval));
- spin = spin_sync(gem_fd, ahnd, ctx, e);
+ spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
read_busy_all(gem_fd, tval[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -418,14 +356,14 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
__submit_spin(gem_fd, spin, e_, 64);
busy_class[e_->class]++;
} else {
- spin = __spin_poll(gem_fd, ahnd, ctx, e_);
+ spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e_);
busy_class[e_->class]++;
}
}
igt_require(spin); /* at least one busy engine */
/* Small delay to allow engines to start. */
- usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
+ usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
read_busy_all(gem_fd, tval[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -475,12 +413,12 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
if (spin)
__submit_spin(gem_fd, spin, e, 64);
else
- spin = __spin_poll(gem_fd, ahnd, ctx, e);
+ spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e);
busy_class[e->class]++;
}
/* Small delay to allow engines to start. */
- usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
+ usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
read_busy_all(gem_fd, tval[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -624,7 +562,7 @@ virtual(int i915, const intel_ctx_cfg_t *base_cfg, unsigned int flags)
ahnd = get_reloc_ahnd(i915, ctx->id);
if (flags & TEST_BUSY)
- spin = spin_sync(i915, ahnd, ctx, NULL);
+ spin = igt_sync_spin(i915, ahnd, ctx, NULL);
else
spin = NULL;
@@ -732,11 +670,12 @@ virtual_all(int i915, const intel_ctx_cfg_t *base_cfg, unsigned int flags)
if (spin)
__virt_submit_spin(i915, spin, ctx[i], 64);
else
- spin = __spin_poll(i915, ahnd, ctx[i], NULL);
+ spin = __igt_sync_spin_poll(i915, ahnd, ctx[i],
+ NULL);
}
/* Small delay to allow engines to start. */
- usleep(__spin_wait(i915, spin) * count / 1e3);
+ usleep(__igt_sync_spin_wait(i915, spin) * count / 1e3);
val = read_busy(i915, class);
slept = measured_usleep(batch_duration_ns / 1000);
diff --git a/tests/i915/gem_eio.c b/tests/i915/gem_eio.c
index d889d67dcebd..6d4b8f7df909 100644
--- a/tests/i915/gem_eio.c
+++ b/tests/i915/gem_eio.c
@@ -47,6 +47,7 @@
#include "i915/gem_ring.h"
#include "igt.h"
#include "igt_device.h"
+#include "igt_dummyload.h"
#include "igt_fb.h"
#include "igt_kms.h"
#include "igt_stats.h"
@@ -429,22 +430,12 @@ static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
return __igt_spin_factory(fd, &opts);
}
-static void __spin_wait(int fd, igt_spin_t *spin)
-{
- if (igt_spin_has_poll(spin)) {
- igt_spin_busywait_until_started(spin);
- } else {
- igt_debug("__spin_wait - usleep mode\n");
- usleep(500e3); /* Better than nothing! */
- }
-}
-
static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
unsigned long flags)
{
igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, flags);
- __spin_wait(fd, spin);
+ __igt_sync_spin_wait(fd, spin);
return spin;
}
@@ -963,7 +954,7 @@ static void test_inflight_external(int fd)
fence = execbuf.rsvd2 >> 32;
igt_assert(fence != -1);
- __spin_wait(fd, hang);
+ __igt_sync_spin_wait(fd, hang);
manual_hang(fd);
gem_sync(fd, hang->handle); /* wedged, with an unready batch */
diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
index 0806a8e545b5..a888027ad9af 100644
--- a/tests/i915/perf_pmu.c
+++ b/tests/i915/perf_pmu.c
@@ -377,68 +377,6 @@ static unsigned int measured_usleep(unsigned int usec)
#define TEST_OTHER (128)
#define TEST_ALL (256)
-static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
- const struct intel_execution_engine2 *e)
-{
- struct igt_spin_factory opts = {
- .ahnd = ahnd,
- .ctx = ctx,
- .engine = e->flags,
- };
-
- if (gem_class_can_store_dword(fd, e->class))
- opts.flags |= IGT_SPIN_POLL_RUN;
-
- return __igt_spin_factory(fd, &opts);
-}
-
-static unsigned long __spin_wait(int fd, igt_spin_t *spin)
-{
- struct timespec start = { };
-
- igt_nsec_elapsed(&start);
-
- if (igt_spin_has_poll(spin)) {
- unsigned long timeout = 0;
-
- while (!igt_spin_has_started(spin)) {
- unsigned long t = igt_nsec_elapsed(&start);
-
- igt_assert(gem_bo_busy(fd, spin->handle));
- if ((t - timeout) > 250e6) {
- timeout = t;
- igt_warn("Spinner not running after %.2fms\n",
- (double)t / 1e6);
- igt_assert(t < 2e9);
- }
- }
- } else {
- igt_debug("__spin_wait - usleep mode\n");
- usleep(500e3); /* Better than nothing! */
- }
-
- igt_assert(gem_bo_busy(fd, spin->handle));
- return igt_nsec_elapsed(&start);
-}
-
-static igt_spin_t *__spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
- const struct intel_execution_engine2 *e)
-{
- igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, e);
-
- __spin_wait(fd, spin);
-
- return spin;
-}
-
-static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
- const struct intel_execution_engine2 *e)
-{
- igt_require_gem(fd);
-
- return __spin_sync(fd, ahnd, ctx, e);
-}
-
static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
{
if (!spin)
@@ -484,7 +422,7 @@ single(int gem_fd, const intel_ctx_t *ctx,
fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
if (flags & TEST_BUSY)
- spin = spin_sync(gem_fd, ahnd, ctx, e);
+ spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
else
spin = NULL;
@@ -536,7 +474,7 @@ busy_start(int gem_fd, const intel_ctx_t *ctx,
*/
sleep(2);
- spin = __spin_sync(gem_fd, ahnd, ctx, e);
+ spin = __igt_sync_spin(gem_fd, ahnd, ctx, e);
fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
@@ -583,7 +521,7 @@ busy_double_start(int gem_fd, const intel_ctx_t *ctx,
* re-submission in execlists mode. Make sure busyness is correctly
* reported with the engine busy, and after the engine went idle.
*/
- spin[0] = __spin_sync(gem_fd, ahnd, ctx, e);
+ spin[0] = __igt_sync_spin(gem_fd, ahnd, ctx, e);
usleep(500e3);
spin[1] = __igt_spin_new(gem_fd,
.ahnd = ahndN,
@@ -675,7 +613,7 @@ busy_check_all(int gem_fd, const intel_ctx_t *ctx,
igt_assert_eq(i, num_engines);
- spin = spin_sync(gem_fd, ahnd, ctx, e);
+ spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
pmu_read_multi(fd[0], num_engines, tval[0]);
slept = measured_usleep(batch_duration_ns / 1000);
if (flags & TEST_TRAILING_IDLE)
@@ -737,7 +675,7 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
else if (spin)
__submit_spin(gem_fd, spin, e_, 64);
else
- spin = __spin_poll(gem_fd, ahnd, ctx, e_);
+ spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e_);
val[i++] = I915_PMU_ENGINE_BUSY(e_->class, e_->instance);
}
@@ -749,7 +687,7 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
fd[i] = open_group(gem_fd, val[i], fd[0]);
/* Small delay to allow engines to start. */
- usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
+ usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
pmu_read_multi(fd[0], num_engines, tval[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -796,7 +734,7 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
if (spin)
__submit_spin(gem_fd, spin, e, 64);
else
- spin = __spin_poll(gem_fd, ahnd, ctx, e);
+ spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e);
val[i++] = I915_PMU_ENGINE_BUSY(e->class, e->instance);
}
@@ -807,7 +745,7 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
fd[i] = open_group(gem_fd, val[i], fd[0]);
/* Small delay to allow engines to start. */
- usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
+ usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
pmu_read_multi(fd[0], num_engines, tval[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -848,7 +786,7 @@ no_sema(int gem_fd, const intel_ctx_t *ctx,
fd[0]);
if (flags & TEST_BUSY)
- spin = spin_sync(gem_fd, ahnd, ctx, e);
+ spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
else
spin = NULL;
@@ -1406,7 +1344,7 @@ multi_client(int gem_fd, const intel_ctx_t *ctx,
*/
fd[1] = open_pmu(gem_fd, config);
- spin = spin_sync(gem_fd, ahnd, ctx, e);
+ spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
val[0] = val[1] = __pmu_read_single(fd[0], &ts[0]);
slept[1] = measured_usleep(batch_duration_ns / 1000);
@@ -1776,7 +1714,7 @@ static igt_spin_t *spin_sync_gt(int i915, uint64_t ahnd, unsigned int gt,
igt_debug("Using engine %u:%u\n", e.class, e.instance);
- return spin_sync(i915, ahnd, *ctx, &e);
+ return igt_sync_spin(i915, ahnd, *ctx, &e);
}
static void
--
2.39.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH i-g-t 2/2] tests/i915_pm_rps: Exercise sysfs thresholds
2023-07-11 16:02 ` [igt-dev] " Tvrtko Ursulin
@ 2023-07-11 16:02 ` Tvrtko Ursulin
-1 siblings, 0 replies; 19+ messages in thread
From: Tvrtko Ursulin @ 2023-07-11 16:02 UTC (permalink / raw)
To: igt-dev, Intel-gfx; +Cc: Rodrigo Vivi
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Exercise a bunch of up and down rps thresholds to verify hardware
is happy with them all.
To limit the overall runtime relies on probability and number of runs
to approach complete coverage.
v2:
* Common sync spinner code now in library.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
tests/i915/i915_pm_rps.c | 194 +++++++++++++++++++++++++++++++++++++++
1 file changed, 194 insertions(+)
diff --git a/tests/i915/i915_pm_rps.c b/tests/i915/i915_pm_rps.c
index 7044fcd81c56..8c370b35c85b 100644
--- a/tests/i915/i915_pm_rps.c
+++ b/tests/i915/i915_pm_rps.c
@@ -39,8 +39,10 @@
#include "i915/gem.h"
#include "i915/gem_create.h"
#include "igt.h"
+#include "igt_aux.h"
#include "igt_dummyload.h"
#include "igt_perf.h"
+#include "igt_rand.h"
#include "igt_sysfs.h"
/**
* TEST: i915 pm rps
@@ -81,6 +83,22 @@
* SUBTEST: waitboost
* Feature: pm_rps
* Run type: FULL
+ *
+ * SUBTEST: thresholds
+ * Feature: pm_rps
+ * Run type: FULL
+ *
+ * SUBTEST: thresholds-idle
+ * Feature: pm_rps
+ * Run type: FULL
+ *
+ * SUBTEST: thresholds-idle-park
+ * Feature: pm_rps
+ * Run type: FULL
+ *
+ * SUBTEST: thresholds-park
+ * Feature: pm_rps
+ * Run type: FULL
*/
IGT_TEST_DESCRIPTION("Render P-States tests - verify GPU frequency changes");
@@ -920,6 +938,146 @@ static void pm_rps_exit_handler(int sig)
drm_close_driver(drm_fd);
}
+static struct i915_engine_class_instance
+find_dword_engine(int i915, const unsigned int gt)
+{
+ struct i915_engine_class_instance *engines, ci = { -1, -1 };
+ unsigned int i, count;
+
+ engines = gem_list_engines(i915, 1u << gt, ~0u, &count);
+ igt_assert(engines);
+
+ for (i = 0; i < count; i++) {
+ if (!gem_class_can_store_dword(i915, engines[i].engine_class))
+ continue;
+
+ ci = engines[i];
+ break;
+ }
+
+ free(engines);
+
+ return ci;
+}
+
+static igt_spin_t *spin_sync_gt(int i915, uint64_t ahnd, unsigned int gt,
+ const intel_ctx_t **ctx)
+{
+ struct i915_engine_class_instance ci = { -1, -1 };
+ struct intel_execution_engine2 e = { };
+
+ ci = find_dword_engine(i915, gt);
+
+ igt_require(ci.engine_class != (uint16_t)I915_ENGINE_CLASS_INVALID);
+
+ if (gem_has_contexts(i915)) {
+ e.class = ci.engine_class;
+ e.instance = ci.engine_instance;
+ e.flags = 0;
+ *ctx = intel_ctx_create_for_engine(i915, e.class, e.instance);
+ } else {
+ igt_require(gt == 0); /* Impossible anyway. */
+ e.class = gem_execbuf_flags_to_engine_class(I915_EXEC_DEFAULT);
+ e.instance = 0;
+ e.flags = I915_EXEC_DEFAULT;
+ *ctx = intel_ctx_0(i915);
+ }
+
+ igt_debug("Using engine %u:%u\n", e.class, e.instance);
+
+ return __igt_sync_spin(i915, ahnd, *ctx, &e);
+}
+
+#define TEST_IDLE 0x1
+#define TEST_PARK 0x2
+static void test_thresholds(int i915, unsigned int gt, unsigned int flags)
+{
+ uint64_t ahnd = get_reloc_ahnd(i915, 0);
+ const unsigned int points = 10;
+ unsigned int def_up, def_down;
+ igt_spin_t *spin = NULL;
+ const intel_ctx_t *ctx;
+ unsigned int *ta, *tb;
+ unsigned int i;
+ int sysfs;
+
+ sysfs = igt_sysfs_gt_open(i915, gt);
+ igt_require(sysfs >= 0);
+
+ /* Feature test */
+ def_up = igt_sysfs_get_u32(sysfs, "rps_up_threshold_pct");
+ def_down = igt_sysfs_get_u32(sysfs, "rps_down_threshold_pct");
+ igt_require(def_up && def_down);
+
+ /* Check invalid percentages are rejected */
+ igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_up_threshold_pct", 101), false);
+ igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_down_threshold_pct", 101), false);
+
+ /*
+ * Invent some random up-down thresholds, but always include 0 and 100
+ * just to have some wild edge cases.
+ */
+ ta = calloc(points, sizeof(unsigned int));
+ tb = calloc(points, sizeof(unsigned int));
+ igt_require(ta && tb);
+
+ ta[0] = tb[0] = 0;
+ ta[1] = tb[1] = 100;
+ hars_petruska_f54_1_random_seed(time(NULL));
+ for (i = 2; i < points; i++) {
+ ta[i] = hars_petruska_f54_1_random_unsafe_max(100);
+ tb[i] = hars_petruska_f54_1_random_unsafe_max(100);
+ }
+ igt_permute_array(ta, points, igt_exchange_int);
+ igt_permute_array(tb, points, igt_exchange_int);
+
+ /* Exercise the thresholds with a GPU load to trigger park/unpark etc */
+ for (i = 0; i < points; i++) {
+ igt_info("Testing thresholds up %u%% and down %u%%...\n", ta[i], tb[i]);
+ igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_up_threshold_pct", ta[i]), true);
+ igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_down_threshold_pct", tb[i]), true);
+
+ if (flags & TEST_IDLE) {
+ gem_quiescent_gpu(i915);
+ } else if (spin) {
+ intel_ctx_destroy(i915, ctx);
+ igt_spin_free(i915, spin);
+ spin = NULL;
+ if (flags & TEST_PARK) {
+ gem_quiescent_gpu(i915);
+ usleep(500000);
+ }
+ }
+ spin = spin_sync_gt(i915, ahnd, gt, &ctx);
+ usleep(1000000);
+ if (flags & TEST_IDLE) {
+ intel_ctx_destroy(i915, ctx);
+ igt_spin_free(i915, spin);
+ if (flags & TEST_PARK) {
+ gem_quiescent_gpu(i915);
+ usleep(500000);
+ }
+ spin = NULL;
+ }
+ }
+
+ if (spin) {
+ intel_ctx_destroy(i915, ctx);
+ igt_spin_free(i915, spin);
+ }
+
+ gem_quiescent_gpu(i915);
+
+ /* Restore defaults */
+ igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_up_threshold_pct", def_up), true);
+ igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_down_threshold_pct", def_down), true);
+
+ free(ta);
+ free(tb);
+ close(sysfs);
+ put_ahnd(ahnd);
+}
+
igt_main
{
igt_fixture {
@@ -1000,6 +1158,42 @@ igt_main
igt_disallow_hang(drm_fd, hang);
}
+ igt_subtest_with_dynamic("thresholds-idle") {
+ int tmp, gt;
+
+ i915_for_each_gt(drm_fd, tmp, gt) {
+ igt_dynamic_f("gt%u", gt)
+ test_thresholds(drm_fd, gt, TEST_IDLE);
+ }
+ }
+
+ igt_subtest_with_dynamic("thresholds") {
+ int tmp, gt;
+
+ i915_for_each_gt(drm_fd, tmp, gt) {
+ igt_dynamic_f("gt%u", gt)
+ test_thresholds(drm_fd, gt, 0);
+ }
+ }
+
+ igt_subtest_with_dynamic("thresholds-park") {
+ int tmp, gt;
+
+ i915_for_each_gt(drm_fd, tmp, gt) {
+ igt_dynamic_f("gt%u", gt)
+ test_thresholds(drm_fd, gt, TEST_PARK);
+ }
+ }
+
+ igt_subtest_with_dynamic("thresholds-idle-park") {
+ int tmp, gt;
+
+ i915_for_each_gt(drm_fd, tmp, gt) {
+ igt_dynamic_f("gt%u", gt)
+ test_thresholds(drm_fd, gt, TEST_IDLE | TEST_PARK);
+ }
+ }
+
igt_fixture
drm_close_driver(drm_fd);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [igt-dev] [PATCH i-g-t 2/2] tests/i915_pm_rps: Exercise sysfs thresholds
@ 2023-07-11 16:02 ` Tvrtko Ursulin
0 siblings, 0 replies; 19+ messages in thread
From: Tvrtko Ursulin @ 2023-07-11 16:02 UTC (permalink / raw)
To: igt-dev, Intel-gfx; +Cc: Rodrigo Vivi, Tvrtko Ursulin
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Exercise a bunch of up and down rps thresholds to verify hardware
is happy with them all.
To limit the overall runtime relies on probability and number of runs
to approach complete coverage.
v2:
* Common sync spinner code now in library.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
tests/i915/i915_pm_rps.c | 194 +++++++++++++++++++++++++++++++++++++++
1 file changed, 194 insertions(+)
diff --git a/tests/i915/i915_pm_rps.c b/tests/i915/i915_pm_rps.c
index 7044fcd81c56..8c370b35c85b 100644
--- a/tests/i915/i915_pm_rps.c
+++ b/tests/i915/i915_pm_rps.c
@@ -39,8 +39,10 @@
#include "i915/gem.h"
#include "i915/gem_create.h"
#include "igt.h"
+#include "igt_aux.h"
#include "igt_dummyload.h"
#include "igt_perf.h"
+#include "igt_rand.h"
#include "igt_sysfs.h"
/**
* TEST: i915 pm rps
@@ -81,6 +83,22 @@
* SUBTEST: waitboost
* Feature: pm_rps
* Run type: FULL
+ *
+ * SUBTEST: thresholds
+ * Feature: pm_rps
+ * Run type: FULL
+ *
+ * SUBTEST: thresholds-idle
+ * Feature: pm_rps
+ * Run type: FULL
+ *
+ * SUBTEST: thresholds-idle-park
+ * Feature: pm_rps
+ * Run type: FULL
+ *
+ * SUBTEST: thresholds-park
+ * Feature: pm_rps
+ * Run type: FULL
*/
IGT_TEST_DESCRIPTION("Render P-States tests - verify GPU frequency changes");
@@ -920,6 +938,146 @@ static void pm_rps_exit_handler(int sig)
drm_close_driver(drm_fd);
}
+static struct i915_engine_class_instance
+find_dword_engine(int i915, const unsigned int gt)
+{
+ struct i915_engine_class_instance *engines, ci = { -1, -1 };
+ unsigned int i, count;
+
+ engines = gem_list_engines(i915, 1u << gt, ~0u, &count);
+ igt_assert(engines);
+
+ for (i = 0; i < count; i++) {
+ if (!gem_class_can_store_dword(i915, engines[i].engine_class))
+ continue;
+
+ ci = engines[i];
+ break;
+ }
+
+ free(engines);
+
+ return ci;
+}
+
+static igt_spin_t *spin_sync_gt(int i915, uint64_t ahnd, unsigned int gt,
+ const intel_ctx_t **ctx)
+{
+ struct i915_engine_class_instance ci = { -1, -1 };
+ struct intel_execution_engine2 e = { };
+
+ ci = find_dword_engine(i915, gt);
+
+ igt_require(ci.engine_class != (uint16_t)I915_ENGINE_CLASS_INVALID);
+
+ if (gem_has_contexts(i915)) {
+ e.class = ci.engine_class;
+ e.instance = ci.engine_instance;
+ e.flags = 0;
+ *ctx = intel_ctx_create_for_engine(i915, e.class, e.instance);
+ } else {
+ igt_require(gt == 0); /* Impossible anyway. */
+ e.class = gem_execbuf_flags_to_engine_class(I915_EXEC_DEFAULT);
+ e.instance = 0;
+ e.flags = I915_EXEC_DEFAULT;
+ *ctx = intel_ctx_0(i915);
+ }
+
+ igt_debug("Using engine %u:%u\n", e.class, e.instance);
+
+ return __igt_sync_spin(i915, ahnd, *ctx, &e);
+}
+
+#define TEST_IDLE 0x1
+#define TEST_PARK 0x2
+static void test_thresholds(int i915, unsigned int gt, unsigned int flags)
+{
+ uint64_t ahnd = get_reloc_ahnd(i915, 0);
+ const unsigned int points = 10;
+ unsigned int def_up, def_down;
+ igt_spin_t *spin = NULL;
+ const intel_ctx_t *ctx;
+ unsigned int *ta, *tb;
+ unsigned int i;
+ int sysfs;
+
+ sysfs = igt_sysfs_gt_open(i915, gt);
+ igt_require(sysfs >= 0);
+
+ /* Feature test */
+ def_up = igt_sysfs_get_u32(sysfs, "rps_up_threshold_pct");
+ def_down = igt_sysfs_get_u32(sysfs, "rps_down_threshold_pct");
+ igt_require(def_up && def_down);
+
+ /* Check invalid percentages are rejected */
+ igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_up_threshold_pct", 101), false);
+ igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_down_threshold_pct", 101), false);
+
+ /*
+ * Invent some random up-down thresholds, but always include 0 and 100
+ * just to have some wild edge cases.
+ */
+ ta = calloc(points, sizeof(unsigned int));
+ tb = calloc(points, sizeof(unsigned int));
+ igt_require(ta && tb);
+
+ ta[0] = tb[0] = 0;
+ ta[1] = tb[1] = 100;
+ hars_petruska_f54_1_random_seed(time(NULL));
+ for (i = 2; i < points; i++) {
+ ta[i] = hars_petruska_f54_1_random_unsafe_max(100);
+ tb[i] = hars_petruska_f54_1_random_unsafe_max(100);
+ }
+ igt_permute_array(ta, points, igt_exchange_int);
+ igt_permute_array(tb, points, igt_exchange_int);
+
+ /* Exercise the thresholds with a GPU load to trigger park/unpark etc */
+ for (i = 0; i < points; i++) {
+ igt_info("Testing thresholds up %u%% and down %u%%...\n", ta[i], tb[i]);
+ igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_up_threshold_pct", ta[i]), true);
+ igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_down_threshold_pct", tb[i]), true);
+
+ if (flags & TEST_IDLE) {
+ gem_quiescent_gpu(i915);
+ } else if (spin) {
+ intel_ctx_destroy(i915, ctx);
+ igt_spin_free(i915, spin);
+ spin = NULL;
+ if (flags & TEST_PARK) {
+ gem_quiescent_gpu(i915);
+ usleep(500000);
+ }
+ }
+ spin = spin_sync_gt(i915, ahnd, gt, &ctx);
+ usleep(1000000);
+ if (flags & TEST_IDLE) {
+ intel_ctx_destroy(i915, ctx);
+ igt_spin_free(i915, spin);
+ if (flags & TEST_PARK) {
+ gem_quiescent_gpu(i915);
+ usleep(500000);
+ }
+ spin = NULL;
+ }
+ }
+
+ if (spin) {
+ intel_ctx_destroy(i915, ctx);
+ igt_spin_free(i915, spin);
+ }
+
+ gem_quiescent_gpu(i915);
+
+ /* Restore defaults */
+ igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_up_threshold_pct", def_up), true);
+ igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_down_threshold_pct", def_down), true);
+
+ free(ta);
+ free(tb);
+ close(sysfs);
+ put_ahnd(ahnd);
+}
+
igt_main
{
igt_fixture {
@@ -1000,6 +1158,42 @@ igt_main
igt_disallow_hang(drm_fd, hang);
}
+ igt_subtest_with_dynamic("thresholds-idle") {
+ int tmp, gt;
+
+ i915_for_each_gt(drm_fd, tmp, gt) {
+ igt_dynamic_f("gt%u", gt)
+ test_thresholds(drm_fd, gt, TEST_IDLE);
+ }
+ }
+
+ igt_subtest_with_dynamic("thresholds") {
+ int tmp, gt;
+
+ i915_for_each_gt(drm_fd, tmp, gt) {
+ igt_dynamic_f("gt%u", gt)
+ test_thresholds(drm_fd, gt, 0);
+ }
+ }
+
+ igt_subtest_with_dynamic("thresholds-park") {
+ int tmp, gt;
+
+ i915_for_each_gt(drm_fd, tmp, gt) {
+ igt_dynamic_f("gt%u", gt)
+ test_thresholds(drm_fd, gt, TEST_PARK);
+ }
+ }
+
+ igt_subtest_with_dynamic("thresholds-idle-park") {
+ int tmp, gt;
+
+ i915_for_each_gt(drm_fd, tmp, gt) {
+ igt_dynamic_f("gt%u", gt)
+ test_thresholds(drm_fd, gt, TEST_IDLE | TEST_PARK);
+ }
+ }
+
igt_fixture
drm_close_driver(drm_fd);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/2] lib/igt_dummyload: Extract sync spinner API
2023-07-11 16:02 ` [igt-dev] " Tvrtko Ursulin
(?)
(?)
@ 2023-07-11 17:13 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2023-07-11 17:13 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 7745 bytes --]
== Series Details ==
Series: series starting with [i-g-t,1/2] lib/igt_dummyload: Extract sync spinner API
URL : https://patchwork.freedesktop.org/series/120556/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13372 -> IGTPW_9387
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/index.html
Participating hosts (41 -> 40)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in IGTPW_9387 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@basic-rte:
- bat-adlp-9: [PASS][1] -> [ABORT][2] ([i915#7977] / [i915#8668])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/bat-adlp-9/igt@i915_pm_rpm@basic-rte.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/bat-adlp-9/igt@i915_pm_rpm@basic-rte.html
- fi-kbl-7567u: [PASS][3] -> [FAIL][4] ([i915#7940])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/fi-kbl-7567u/igt@i915_pm_rpm@basic-rte.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/fi-kbl-7567u/igt@i915_pm_rpm@basic-rte.html
* igt@i915_pm_rpm@module-reload:
- fi-tgl-1115g4: [PASS][5] -> [FAIL][6] ([i915#7940])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/fi-tgl-1115g4/igt@i915_pm_rpm@module-reload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/fi-tgl-1115g4/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: [PASS][7] -> [DMESG-WARN][8] ([i915#6367])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/bat-rpls-2/igt@i915_selftest@live@slpc.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/bat-rpls-2/igt@i915_selftest@live@slpc.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][9] ([i915#1845] / [i915#5354]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
* igt@kms_psr@primary_mmap_gtt:
- bat-rplp-1: NOTRUN -> [ABORT][10] ([i915#8434] / [i915#8442] / [i915#8668])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_psr@primary_page_flip:
- bat-rplp-1: NOTRUN -> [SKIP][11] ([i915#1072]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/bat-rplp-1/igt@kms_psr@primary_page_flip.html
#### Possible fixes ####
* igt@i915_pm_rpm@basic-rte:
- fi-cfl-guc: [FAIL][12] ([i915#7940]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/fi-cfl-guc/igt@i915_pm_rpm@basic-rte.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/fi-cfl-guc/igt@i915_pm_rpm@basic-rte.html
- fi-tgl-1115g4: [FAIL][14] ([i915#7940]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/fi-tgl-1115g4/igt@i915_pm_rpm@basic-rte.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/fi-tgl-1115g4/igt@i915_pm_rpm@basic-rte.html
- fi-skl-guc: [FAIL][16] ([i915#7940]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/fi-skl-guc/igt@i915_pm_rpm@basic-rte.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/fi-skl-guc/igt@i915_pm_rpm@basic-rte.html
- fi-cfl-8700k: [FAIL][18] ([i915#7940]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/fi-cfl-8700k/igt@i915_pm_rpm@basic-rte.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/fi-cfl-8700k/igt@i915_pm_rpm@basic-rte.html
* igt@i915_pm_rpm@module-reload:
- fi-rkl-11600: [FAIL][20] ([i915#7940]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/fi-rkl-11600/igt@i915_pm_rpm@module-reload.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/fi-rkl-11600/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@slpc:
- bat-mtlp-6: [DMESG-WARN][22] ([i915#6367]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/bat-mtlp-6/igt@i915_selftest@live@slpc.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/bat-mtlp-6/igt@i915_selftest@live@slpc.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
- bat-rplp-1: [ABORT][24] ([i915#8442] / [i915#8668]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
#### Warnings ####
* igt@i915_module_load@load:
- bat-adlp-11: [DMESG-WARN][26] ([i915#4423]) -> [ABORT][27] ([i915#4423])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/bat-adlp-11/igt@i915_module_load@load.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/bat-adlp-11/igt@i915_module_load@load.html
* igt@i915_selftest@live@reset:
- bat-rpls-1: [ABORT][28] ([i915#4983] / [i915#7461] / [i915#7981] / [i915#8347] / [i915#8384]) -> [ABORT][29] ([i915#4983] / [i915#7461] / [i915#8347] / [i915#8384])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/bat-rpls-1/igt@i915_selftest@live@reset.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/bat-rpls-1/igt@i915_selftest@live@reset.html
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
[i915#7977]: https://gitlab.freedesktop.org/drm/intel/issues/7977
[i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
[i915#8384]: https://gitlab.freedesktop.org/drm/intel/issues/8384
[i915#8434]: https://gitlab.freedesktop.org/drm/intel/issues/8434
[i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7380 -> IGTPW_9387
CI-20190529: 20190529
CI_DRM_13372: 01c4678ab6c623c621a1dea438133e39711291d4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9387: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/index.html
IGT_7380: 8e65f12de2fd52c05dc48fdbcb8cfe86f6de1a75 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Testlist changes
----------------
+igt@i915_pm_rps@thresholds
+igt@i915_pm_rps@thresholds-idle
+igt@i915_pm_rps@thresholds-idle-park
+igt@i915_pm_rps@thresholds-park
-igt@syncobj_eventfd@binary-wait
-igt@syncobj_eventfd@binary-wait-before-signal
-igt@syncobj_eventfd@binary-wait-signaled
-igt@syncobj_eventfd@invalid-bad-flags
-igt@syncobj_eventfd@invalid-bad-pad
-igt@syncobj_eventfd@invalid-illegal-eventfd
-igt@syncobj_eventfd@invalid-illegal-handle
-igt@syncobj_eventfd@timeline-wait
-igt@syncobj_eventfd@timeline-wait-before-signal
-igt@syncobj_eventfd@timeline-wait-signaled
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/index.html
[-- Attachment #2: Type: text/html, Size: 9754 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* [igt-dev] ○ CI.xeBAT: info for series starting with [i-g-t,1/2] lib/igt_dummyload: Extract sync spinner API
2023-07-11 16:02 ` [igt-dev] " Tvrtko Ursulin
` (2 preceding siblings ...)
(?)
@ 2023-07-11 17:58 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2023-07-11 17:58 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 374 bytes --]
== Series Details ==
Series: series starting with [i-g-t,1/2] lib/igt_dummyload: Extract sync spinner API
URL : https://patchwork.freedesktop.org/series/120556/
State : info
== Summary ==
Participating hosts:
bat-pvc-2
bat-atsm-2
bat-dg2-oem2
bat-adlp-7
Missing hosts results[0]:
Results: [IGTPW_9387](https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9387/index.html)
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^ permalink raw reply [flat|nested] 19+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for series starting with [i-g-t,1/2] lib/igt_dummyload: Extract sync spinner API
2023-07-11 16:02 ` [igt-dev] " Tvrtko Ursulin
` (3 preceding siblings ...)
(?)
@ 2023-07-11 22:17 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2023-07-11 22:17 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: igt-dev
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== Series Details ==
Series: series starting with [i-g-t,1/2] lib/igt_dummyload: Extract sync spinner API
URL : https://patchwork.freedesktop.org/series/120556/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13372_full -> IGTPW_9387_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_9387_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_9387_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/index.html
Participating hosts (10 -> 10)
------------------------------
Additional (1): shard-tglu0
Missing (1): pig-kbl-iris
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_9387_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_eio@reset-stress:
- shard-snb: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-snb6/igt@gem_eio@reset-stress.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-snb7/igt@gem_eio@reset-stress.html
* {igt@i915_pm_rps@thresholds-idle-park@gt0} (NEW):
- shard-tglu: NOTRUN -> [SKIP][3] +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-10/igt@i915_pm_rps@thresholds-idle-park@gt0.html
* {igt@i915_pm_rps@thresholds-idle@gt0} (NEW):
- {shard-dg1}: NOTRUN -> [SKIP][4] +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg1-19/igt@i915_pm_rps@thresholds-idle@gt0.html
* {igt@i915_pm_rps@thresholds-park@gt0} (NEW):
- shard-dg2: NOTRUN -> [SKIP][5] +3 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-1/igt@i915_pm_rps@thresholds-park@gt0.html
- shard-rkl: NOTRUN -> [SKIP][6] +3 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-2/igt@i915_pm_rps@thresholds-park@gt0.html
* {igt@i915_pm_rps@thresholds@gt1} (NEW):
- shard-mtlp: NOTRUN -> [SKIP][7] +7 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-7/igt@i915_pm_rps@thresholds@gt1.html
#### Warnings ####
* igt@gem_eio@unwedge-stress:
- shard-snb: [FAIL][8] ([i915#3354]) -> [FAIL][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-snb4/igt@gem_eio@unwedge-stress.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-snb6/igt@gem_eio@unwedge-stress.html
New tests
---------
New tests have been introduced between CI_DRM_13372_full and IGTPW_9387_full:
### New IGT tests (12) ###
* igt@i915_pm_rps@thresholds:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@thresholds-idle:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@thresholds-idle-park:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@thresholds-idle-park@gt0:
- Statuses : 8 skip(s)
- Exec time: [0.0] s
* igt@i915_pm_rps@thresholds-idle-park@gt1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@i915_pm_rps@thresholds-idle@gt0:
- Statuses : 8 skip(s)
- Exec time: [0.0] s
* igt@i915_pm_rps@thresholds-idle@gt1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@i915_pm_rps@thresholds-park:
- Statuses :
- Exec time: [None] s
* igt@i915_pm_rps@thresholds-park@gt0:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@i915_pm_rps@thresholds-park@gt1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@i915_pm_rps@thresholds@gt0:
- Statuses : 8 skip(s)
- Exec time: [0.0] s
* igt@i915_pm_rps@thresholds@gt1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in IGTPW_9387_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@device_reset@unbind-cold-reset-rebind:
- shard-rkl: NOTRUN -> [SKIP][10] ([i915#7701])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-2/igt@device_reset@unbind-cold-reset-rebind.html
- shard-tglu: NOTRUN -> [SKIP][11] ([i915#7701])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-3/igt@device_reset@unbind-cold-reset-rebind.html
- shard-dg2: NOTRUN -> [SKIP][12] ([i915#7701])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-5/igt@device_reset@unbind-cold-reset-rebind.html
* igt@drm_fdinfo@busy-hang@bcs0:
- shard-dg2: NOTRUN -> [SKIP][13] ([i915#8414]) +11 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-2/igt@drm_fdinfo@busy-hang@bcs0.html
* igt@drm_fdinfo@virtual-busy-all:
- shard-mtlp: NOTRUN -> [SKIP][14] ([i915#8414])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-2/igt@drm_fdinfo@virtual-busy-all.html
* igt@feature_discovery@chamelium:
- shard-dg2: NOTRUN -> [SKIP][15] ([i915#4854])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-10/igt@feature_discovery@chamelium.html
* igt@gem_basic@multigpu-create-close:
- shard-rkl: NOTRUN -> [SKIP][16] ([i915#7697]) +1 similar issue
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-4/igt@gem_basic@multigpu-create-close.html
* igt@gem_ccs@ctrl-surf-copy:
- shard-mtlp: NOTRUN -> [SKIP][17] ([i915#5325])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-7/igt@gem_ccs@ctrl-surf-copy.html
* igt@gem_close_race@multigpu-basic-process:
- shard-tglu: NOTRUN -> [SKIP][18] ([i915#7697]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-7/igt@gem_close_race@multigpu-basic-process.html
- shard-dg2: NOTRUN -> [SKIP][19] ([i915#7697]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-11/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_create@create-ext-cpu-access-big:
- shard-tglu: NOTRUN -> [SKIP][20] ([i915#6335])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-3/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_create@create-ext-set-pat:
- shard-snb: NOTRUN -> [FAIL][21] ([i915#8621])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-snb1/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-rkl: [PASS][22] -> [FAIL][23] ([i915#6268])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-rkl-2/igt@gem_ctx_exec@basic-nohangcheck.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-2/igt@gem_ctx_exec@basic-nohangcheck.html
- shard-tglu: [PASS][24] -> [FAIL][25] ([i915#6268])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-tglu-2/igt@gem_ctx_exec@basic-nohangcheck.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-9/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_param@set-priority-not-supported:
- shard-tglu: NOTRUN -> [SKIP][26] ([fdo#109314])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-4/igt@gem_ctx_param@set-priority-not-supported.html
- shard-dg2: NOTRUN -> [SKIP][27] ([fdo#109314])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-12/igt@gem_ctx_param@set-priority-not-supported.html
- shard-rkl: NOTRUN -> [SKIP][28] ([fdo#109314])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-1/igt@gem_ctx_param@set-priority-not-supported.html
* igt@gem_ctx_persistence@legacy-engines-hostile@vebox:
- shard-mtlp: [PASS][29] -> [FAIL][30] ([i915#2410]) +2 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-mtlp-4/igt@gem_ctx_persistence@legacy-engines-hostile@vebox.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-8/igt@gem_ctx_persistence@legacy-engines-hostile@vebox.html
* igt@gem_ctx_persistence@legacy-engines-mixed:
- shard-snb: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#1099])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-snb2/igt@gem_ctx_persistence@legacy-engines-mixed.html
* igt@gem_exec_balancer@bonded-dual:
- shard-dg2: NOTRUN -> [SKIP][32] ([i915#4771])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-7/igt@gem_exec_balancer@bonded-dual.html
* igt@gem_exec_balancer@bonded-true-hang:
- shard-dg2: NOTRUN -> [SKIP][33] ([i915#4812]) +2 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-11/igt@gem_exec_balancer@bonded-true-hang.html
* igt@gem_exec_capture@pi@vcs0:
- shard-mtlp: [PASS][34] -> [FAIL][35] ([i915#4475])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-mtlp-4/igt@gem_exec_capture@pi@vcs0.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-5/igt@gem_exec_capture@pi@vcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-rkl: [PASS][36] -> [FAIL][37] ([i915#2846])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-rkl-6/igt@gem_exec_fair@basic-deadline.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none:
- shard-mtlp: NOTRUN -> [SKIP][38] ([i915#4473] / [i915#4771])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-6/igt@gem_exec_fair@basic-none.html
- shard-dg2: NOTRUN -> [SKIP][39] ([i915#3539] / [i915#4852])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-3/igt@gem_exec_fair@basic-none.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [PASS][40] -> [FAIL][41] ([i915#2842])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-apl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-apl4/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-rkl: [PASS][42] -> [FAIL][43] ([i915#2842])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-rkl-4/igt@gem_exec_fair@basic-pace@bcs0.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-6/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_params@secure-non-root:
- shard-dg2: NOTRUN -> [SKIP][44] ([fdo#112283])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-3/igt@gem_exec_params@secure-non-root.html
* igt@gem_exec_reloc@basic-gtt-cpu-active:
- shard-mtlp: NOTRUN -> [SKIP][45] ([i915#3281]) +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-5/igt@gem_exec_reloc@basic-gtt-cpu-active.html
* igt@gem_exec_reloc@basic-gtt-wc-active:
- shard-dg2: NOTRUN -> [SKIP][46] ([i915#3281]) +4 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-10/igt@gem_exec_reloc@basic-gtt-wc-active.html
* igt@gem_exec_reloc@basic-write-gtt-active:
- shard-rkl: NOTRUN -> [SKIP][47] ([i915#3281]) +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-4/igt@gem_exec_reloc@basic-write-gtt-active.html
* igt@gem_exec_schedule@deep@vcs0:
- shard-mtlp: [PASS][48] -> [FAIL][49] ([i915#8545])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-mtlp-6/igt@gem_exec_schedule@deep@vcs0.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-3/igt@gem_exec_schedule@deep@vcs0.html
* igt@gem_exec_whisper@basic-forked:
- shard-mtlp: NOTRUN -> [FAIL][50] ([i915#6363])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-1/igt@gem_exec_whisper@basic-forked.html
* igt@gem_exec_whisper@basic-normal:
- shard-mtlp: [PASS][51] -> [FAIL][52] ([i915#6363])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-mtlp-1/igt@gem_exec_whisper@basic-normal.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-2/igt@gem_exec_whisper@basic-normal.html
* igt@gem_fenced_exec_thrash@2-spare-fences:
- shard-dg2: NOTRUN -> [SKIP][53] ([i915#4860])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-12/igt@gem_fenced_exec_thrash@2-spare-fences.html
* igt@gem_lmem_swapping@heavy-verify-multi:
- shard-rkl: NOTRUN -> [SKIP][54] ([i915#4613])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-7/igt@gem_lmem_swapping@heavy-verify-multi.html
* igt@gem_lmem_swapping@heavy-verify-random-ccs:
- shard-tglu: NOTRUN -> [SKIP][55] ([i915#4613]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-4/igt@gem_lmem_swapping@heavy-verify-random-ccs.html
* igt@gem_lmem_swapping@massive:
- shard-apl: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#4613])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-apl1/igt@gem_lmem_swapping@massive.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: [PASS][57] -> [TIMEOUT][58] ([i915#5493])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-dg2-1/igt@gem_lmem_swapping@smem-oom@lmem0.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-2/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_media_vme:
- shard-tglu: NOTRUN -> [SKIP][59] ([i915#284])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-2/igt@gem_media_vme.html
* igt@gem_mmap_gtt@big-bo-tiledx:
- shard-mtlp: NOTRUN -> [SKIP][60] ([i915#4077])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-4/igt@gem_mmap_gtt@big-bo-tiledx.html
* igt@gem_mmap_wc@close:
- shard-dg2: NOTRUN -> [SKIP][61] ([i915#4083]) +5 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-6/igt@gem_mmap_wc@close.html
* igt@gem_mmap_wc@write:
- shard-mtlp: NOTRUN -> [SKIP][62] ([i915#4083]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-4/igt@gem_mmap_wc@write.html
* igt@gem_partial_pwrite_pread@writes-after-reads:
- shard-rkl: NOTRUN -> [SKIP][63] ([i915#3282]) +2 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-4/igt@gem_partial_pwrite_pread@writes-after-reads.html
* igt@gem_pread@snoop:
- shard-dg2: NOTRUN -> [SKIP][64] ([i915#3282]) +4 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-3/igt@gem_pread@snoop.html
* igt@gem_pxp@create-regular-buffer:
- shard-mtlp: NOTRUN -> [SKIP][65] ([i915#4270])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-3/igt@gem_pxp@create-regular-buffer.html
* igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
- shard-dg2: NOTRUN -> [SKIP][66] ([i915#4270]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-7/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html
- shard-rkl: NOTRUN -> [SKIP][67] ([i915#4270])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-2/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html
- shard-tglu: NOTRUN -> [SKIP][68] ([i915#4270])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-9/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html
* igt@gem_readwrite@beyond-eob:
- shard-mtlp: NOTRUN -> [SKIP][69] ([i915#3282])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-2/igt@gem_readwrite@beyond-eob.html
* igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:
- shard-mtlp: NOTRUN -> [SKIP][70] ([i915#8428]) +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-8/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs.html
* igt@gem_tiled_fence_blits@basic:
- shard-dg2: NOTRUN -> [SKIP][71] ([i915#4077]) +3 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-6/igt@gem_tiled_fence_blits@basic.html
* igt@gem_tiled_pread_basic:
- shard-mtlp: NOTRUN -> [SKIP][72] ([i915#4079])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-5/igt@gem_tiled_pread_basic.html
* igt@gem_userptr_blits@invalid-mmap-offset-unsync:
- shard-dg2: NOTRUN -> [SKIP][73] ([i915#3297])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-6/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
- shard-rkl: NOTRUN -> [SKIP][74] ([i915#3297])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-1/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
- shard-tglu: NOTRUN -> [SKIP][75] ([i915#3297])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-2/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-dg2: NOTRUN -> [SKIP][76] ([i915#3297] / [i915#4880])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@nohangcheck:
- shard-mtlp: [PASS][77] -> [FAIL][78] ([i915#7916])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-mtlp-4/igt@gem_userptr_blits@nohangcheck.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-3/igt@gem_userptr_blits@nohangcheck.html
* igt@gen3_render_linear_blits:
- shard-tglu: NOTRUN -> [SKIP][79] ([fdo#109289])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-6/igt@gen3_render_linear_blits.html
* igt@gen7_exec_parse@basic-allowed:
- shard-mtlp: NOTRUN -> [SKIP][80] ([fdo#109289])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-5/igt@gen7_exec_parse@basic-allowed.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][81] -> [ABORT][82] ([i915#5566])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-apl1/igt@gen9_exec_parse@allowed-single.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-apl2/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@bb-large:
- shard-dg2: NOTRUN -> [SKIP][83] ([i915#2856])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-1/igt@gen9_exec_parse@bb-large.html
- shard-rkl: NOTRUN -> [SKIP][84] ([i915#2527])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-6/igt@gen9_exec_parse@bb-large.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-mtlp: NOTRUN -> [SKIP][85] ([i915#2856])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-3/igt@gen9_exec_parse@bb-start-cmd.html
* igt@i915_hangman@engine-engine-error@vcs0:
- shard-mtlp: [PASS][86] -> [FAIL][87] ([i915#7069])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-mtlp-7/igt@i915_hangman@engine-engine-error@vcs0.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-2/igt@i915_hangman@engine-engine-error@vcs0.html
* igt@i915_module_load@load:
- shard-tglu: NOTRUN -> [SKIP][88] ([i915#6227])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-5/igt@i915_module_load@load.html
- shard-dg2: NOTRUN -> [SKIP][89] ([i915#6227])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-3/igt@i915_module_load@load.html
- shard-rkl: NOTRUN -> [SKIP][90] ([i915#6227])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-4/igt@i915_module_load@load.html
* igt@i915_pm_dc@dc5-psr:
- shard-dg2: NOTRUN -> [SKIP][91] ([i915#658]) +2 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-10/igt@i915_pm_dc@dc5-psr.html
* igt@i915_pm_dc@dc9-dpms:
- shard-apl: [PASS][92] -> [SKIP][93] ([fdo#109271])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-apl4/igt@i915_pm_dc@dc9-dpms.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-apl4/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- shard-dg2: NOTRUN -> [SKIP][94] ([i915#1937])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-7/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-mtlp: [PASS][95] -> [SKIP][96] ([fdo#109289] / [i915#8403])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-mtlp-5/igt@i915_pm_rc6_residency@rc6-accuracy.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-6/igt@i915_pm_rc6_residency@rc6-accuracy.html
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-dg2: NOTRUN -> [SKIP][97] ([i915#1397])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-10/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
- shard-tglu: NOTRUN -> [SKIP][98] ([fdo#111644] / [i915#1397])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-3/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp:
- shard-dg2: [PASS][99] -> [SKIP][100] ([i915#1397])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-dg2-12/igt@i915_pm_rpm@modeset-lpsp.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-6/igt@i915_pm_rpm@modeset-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-rkl: [PASS][101] -> [SKIP][102] ([i915#1397]) +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-rkl-7/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-1/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@i915_pm_rps@reset:
- shard-snb: [PASS][103] -> [INCOMPLETE][104] ([i915#7790])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-snb1/igt@i915_pm_rps@reset.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-snb1/igt@i915_pm_rps@reset.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-rkl: [PASS][105] -> [FAIL][106] ([fdo#103375])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-rkl-1/igt@i915_suspend@basic-s3-without-i915.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-6/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- shard-dg2: NOTRUN -> [SKIP][107] ([i915#4215] / [i915#5190])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-11/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@clobberred-modifier:
- shard-dg2: NOTRUN -> [SKIP][108] ([i915#4212])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-3/igt@kms_addfb_basic@clobberred-modifier.html
* igt@kms_async_flips@crc@pipe-b-hdmi-a-1:
- shard-snb: NOTRUN -> [FAIL][109] ([i915#8247]) +1 similar issue
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-snb1/igt@kms_async_flips@crc@pipe-b-hdmi-a-1.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-apl: NOTRUN -> [SKIP][110] ([fdo#109271] / [i915#1769])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-apl7/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][111] ([fdo#111614]) +1 similar issue
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-1/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-tglu: NOTRUN -> [SKIP][112] ([fdo#111615] / [i915#5286]) +1 similar issue
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-rkl: NOTRUN -> [SKIP][113] ([i915#5286]) +1 similar issue
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
- shard-mtlp: [PASS][114] -> [FAIL][115] ([i915#5138]) +1 similar issue
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-mtlp-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-90:
- shard-tglu: NOTRUN -> [SKIP][116] ([fdo#111614])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-5/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html
- shard-rkl: NOTRUN -> [SKIP][117] ([fdo#111614] / [i915#3638])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-4/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-mtlp: [PASS][118] -> [FAIL][119] ([i915#3743])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-mtlp-4/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
- shard-dg2: NOTRUN -> [SKIP][120] ([i915#4538] / [i915#5190]) +3 similar issues
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-12/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][121] ([fdo#110723]) +2 similar issues
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-2/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
- shard-mtlp: NOTRUN -> [SKIP][122] ([fdo#111615])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-3/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-addfb-size-overflow:
- shard-dg2: NOTRUN -> [SKIP][123] ([i915#5190]) +9 similar issues
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-6/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
- shard-mtlp: NOTRUN -> [SKIP][124] ([i915#6187])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-7/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-tglu: NOTRUN -> [SKIP][125] ([fdo#111615]) +2 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-mtlp: NOTRUN -> [SKIP][126] ([i915#3886] / [i915#6095]) +3 similar issues
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-3/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc:
- shard-rkl: NOTRUN -> [SKIP][127] ([i915#5354] / [i915#6095]) +4 similar issues
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-2/igt@kms_ccs@pipe-a-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs:
- shard-rkl: NOTRUN -> [SKIP][128] ([i915#3886] / [i915#5354] / [i915#6095])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-2/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-tglu: NOTRUN -> [SKIP][129] ([i915#3689] / [i915#3886] / [i915#5354] / [i915#6095]) +2 similar issues
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-8/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs:
- shard-rkl: NOTRUN -> [SKIP][130] ([i915#3734] / [i915#5354] / [i915#6095]) +1 similar issue
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-4/igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs.html
- shard-tglu: NOTRUN -> [SKIP][131] ([fdo#111615] / [i915#3689] / [i915#5354] / [i915#6095]) +1 similar issue
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-6/igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_ccs:
- shard-mtlp: NOTRUN -> [SKIP][132] ([i915#6095]) +11 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-5/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-4_tiled_dg2_mc_ccs:
- shard-tglu: NOTRUN -> [SKIP][133] ([i915#3689] / [i915#5354] / [i915#6095]) +6 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-7/igt@kms_ccs@pipe-b-random-ccs-data-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs:
- shard-glk: NOTRUN -> [SKIP][134] ([fdo#109271]) +4 similar issues
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-glk2/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_mtl_mc_ccs:
- shard-dg2: NOTRUN -> [SKIP][135] ([i915#5354]) +24 similar issues
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-6/igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_mtl_mc_ccs.html
- shard-rkl: NOTRUN -> [SKIP][136] ([i915#5354]) +8 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-1/igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_mtl_mc_ccs.html
- shard-tglu: NOTRUN -> [SKIP][137] ([i915#5354] / [i915#6095]) +4 similar issues
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-8/igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_mtl_mc_ccs.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-dg2: NOTRUN -> [SKIP][138] ([i915#3689] / [i915#3886] / [i915#5354]) +5 similar issues
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-1/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][139] ([fdo#109271] / [i915#3886])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-apl7/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs:
- shard-dg2: NOTRUN -> [SKIP][140] ([i915#3689] / [i915#5354]) +14 similar issues
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-6/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs.html
* igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][141] ([i915#4087] / [i915#7213]) +2 similar issues
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-10/igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-1.html
* igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][142] ([i915#7213])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-10/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1.html
* igt@kms_cdclk@plane-scaling@pipe-b-dp-4:
- shard-dg2: NOTRUN -> [SKIP][143] ([i915#4087]) +3 similar issues
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-11/igt@kms_cdclk@plane-scaling@pipe-b-dp-4.html
* igt@kms_chamelium_audio@dp-audio:
- shard-mtlp: NOTRUN -> [SKIP][144] ([i915#7828]) +2 similar issues
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-3/igt@kms_chamelium_audio@dp-audio.html
* igt@kms_chamelium_color@ctm-0-50:
- shard-tglu: NOTRUN -> [SKIP][145] ([fdo#111827])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-5/igt@kms_chamelium_color@ctm-0-50.html
* igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode:
- shard-tglu: NOTRUN -> [SKIP][146] ([i915#7828])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-4/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html
* igt@kms_chamelium_hpd@dp-hpd-storm:
- shard-dg2: NOTRUN -> [SKIP][147] ([i915#7828]) +3 similar issues
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-2/igt@kms_chamelium_hpd@dp-hpd-storm.html
- shard-rkl: NOTRUN -> [SKIP][148] ([i915#7828]) +1 similar issue
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-2/igt@kms_chamelium_hpd@dp-hpd-storm.html
* igt@kms_content_protection@lic:
- shard-dg2: NOTRUN -> [SKIP][149] ([i915#7118])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-3/igt@kms_content_protection@lic.html
* igt@kms_content_protection@mei_interface:
- shard-mtlp: NOTRUN -> [SKIP][150] ([i915#8063])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-5/igt@kms_content_protection@mei_interface.html
* igt@kms_content_protection@uevent:
- shard-rkl: NOTRUN -> [SKIP][151] ([i915#7118])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-7/igt@kms_content_protection@uevent.html
- shard-tglu: NOTRUN -> [SKIP][152] ([i915#6944] / [i915#7116] / [i915#7118])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-5/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-offscreen-512x512:
- shard-dg2: NOTRUN -> [SKIP][153] ([i915#3359]) +3 similar issues
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-11/igt@kms_cursor_crc@cursor-offscreen-512x512.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-rkl: NOTRUN -> [SKIP][154] ([fdo#109279] / [i915#3359])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-6/igt@kms_cursor_crc@cursor-onscreen-512x170.html
- shard-tglu: NOTRUN -> [SKIP][155] ([fdo#109279] / [i915#3359])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-6/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-tglu: NOTRUN -> [SKIP][156] ([i915#3359]) +1 similar issue
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-4/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-rkl: NOTRUN -> [SKIP][157] ([i915#3359]) +1 similar issue
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-2/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-tglu: NOTRUN -> [SKIP][158] ([fdo#109274]) +4 similar issues
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
- shard-dg2: NOTRUN -> [SKIP][159] ([fdo#109274] / [i915#5354]) +2 similar issues
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-12/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html
- shard-rkl: NOTRUN -> [SKIP][160] ([fdo#111825]) +2 similar issues
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-1/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
- shard-dg2: NOTRUN -> [SKIP][161] ([fdo#109274] / [fdo#111767] / [i915#5354])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-12/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
- shard-rkl: NOTRUN -> [SKIP][162] ([fdo#111767] / [fdo#111825])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-7/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
- shard-tglu: NOTRUN -> [SKIP][163] ([fdo#109274] / [fdo#111767])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-4/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [PASS][164] -> [FAIL][165] ([i915#2346])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][166] ([i915#3804])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-1/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html
* igt@kms_dp_aux_dev:
- shard-tglu: NOTRUN -> [SKIP][167] ([i915#1257])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-5/igt@kms_dp_aux_dev.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-dg2: NOTRUN -> [SKIP][168] ([i915#3555] / [i915#3840])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-3/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_fbcon_fbt@psr:
- shard-dg2: NOTRUN -> [SKIP][169] ([i915#3469])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-1/igt@kms_fbcon_fbt@psr.html
- shard-rkl: NOTRUN -> [SKIP][170] ([i915#3955])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-6/igt@kms_fbcon_fbt@psr.html
- shard-tglu: NOTRUN -> [SKIP][171] ([i915#3469])
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-4/igt@kms_fbcon_fbt@psr.html
* igt@kms_fence_pin_leak:
- shard-dg2: NOTRUN -> [SKIP][172] ([i915#4881])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-6/igt@kms_fence_pin_leak.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
- shard-dg2: NOTRUN -> [SKIP][173] ([fdo#109274]) +2 similar issues
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-5/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_flip@2x-nonexisting-fb:
- shard-tglu: NOTRUN -> [SKIP][174] ([fdo#109274] / [i915#3637])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-6/igt@kms_flip@2x-nonexisting-fb.html
* igt@kms_flip@2x-plain-flip-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][175] ([i915#3637])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-3/igt@kms_flip@2x-plain-flip-interruptible.html
* igt@kms_flip@flip-vs-suspend@a-hdmi-a3:
- shard-dg2: [PASS][176] -> [FAIL][177] ([fdo#103375] / [i915#6121]) +3 similar issues
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-dg2-8/igt@kms_flip@flip-vs-suspend@a-hdmi-a3.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-5/igt@kms_flip@flip-vs-suspend@a-hdmi-a3.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][178] ([i915#2672])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode.html
- shard-tglu: NOTRUN -> [SKIP][179] ([i915#2587] / [i915#2672])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-9/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][180] ([i915#2672])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][181] ([i915#2672]) +2 similar issues
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode.html
* igt@kms_force_connector_basic@prune-stale-modes:
- shard-mtlp: NOTRUN -> [SKIP][182] ([i915#5274])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-8/igt@kms_force_connector_basic@prune-stale-modes.html
- shard-dg2: NOTRUN -> [SKIP][183] ([i915#5274])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-3/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][184] ([i915#8708])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite:
- shard-tglu: NOTRUN -> [SKIP][185] ([fdo#109280]) +10 similar issues
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][186] ([i915#3023]) +4 similar issues
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
- shard-dg2: NOTRUN -> [SKIP][187] ([i915#3458]) +6 similar issues
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-12/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render:
- shard-apl: NOTRUN -> [SKIP][188] ([fdo#109271]) +35 similar issues
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-apl4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][189] ([i915#8708]) +10 similar issues
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-10/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
- shard-rkl: NOTRUN -> [SKIP][190] ([fdo#111825] / [i915#1825]) +8 similar issues
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
- shard-snb: NOTRUN -> [SKIP][191] ([fdo#109271]) +104 similar issues
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-snb5/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
- shard-tglu: NOTRUN -> [SKIP][192] ([fdo#110189]) +6 similar issues
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-2/igt@kms_frontbuffer_tracking@fbcpsr-stridechange.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-cpu:
- shard-mtlp: NOTRUN -> [SKIP][193] ([i915#1825]) +6 similar issues
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_hdr@bpc-switch:
- shard-tglu: NOTRUN -> [SKIP][194] ([i915#3555] / [i915#8228])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-6/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@static-swap:
- shard-dg2: NOTRUN -> [SKIP][195] ([i915#3555] / [i915#8228])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-6/igt@kms_hdr@static-swap.html
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-c-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][196] ([i915#5176]) +3 similar issues
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-9/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-c-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [SKIP][197] ([i915#5176]) +7 similar issues
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-11/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-dp-4.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][198] ([i915#5176]) +5 similar issues
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-7/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][199] ([i915#5235]) +23 similar issues
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-2.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][200] ([i915#5235]) +5 similar issues
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-4/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][201] ([i915#5235]) +3 similar issues
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-3/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-1.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-apl: NOTRUN -> [SKIP][202] ([fdo#109271] / [i915#658]) +1 similar issue
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-apl6/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-tglu: NOTRUN -> [SKIP][203] ([fdo#109642] / [fdo#111068] / [i915#658])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-7/igt@kms_psr2_su@frontbuffer-xrgb8888.html
- shard-mtlp: NOTRUN -> [SKIP][204] ([i915#4348])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-8/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@primary_mmap_cpu:
- shard-dg2: NOTRUN -> [SKIP][205] ([i915#1072]) +4 similar issues
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-6/igt@kms_psr@primary_mmap_cpu.html
- shard-rkl: NOTRUN -> [SKIP][206] ([i915#1072]) +2 similar issues
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-1/igt@kms_psr@primary_mmap_cpu.html
* igt@kms_rotation_crc@primary-rotation-270:
- shard-dg2: NOTRUN -> [SKIP][207] ([i915#4235]) +1 similar issue
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-10/igt@kms_rotation_crc@primary-rotation-270.html
* igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
- shard-mtlp: NOTRUN -> [SKIP][208] ([i915#4235])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-1/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
* igt@kms_scaling_modes@scaling-mode-center:
- shard-dg2: NOTRUN -> [SKIP][209] ([i915#3555]) +1 similar issue
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-6/igt@kms_scaling_modes@scaling-mode-center.html
* igt@kms_scaling_modes@scaling-mode-full:
- shard-tglu: NOTRUN -> [SKIP][210] ([i915#3555]) +1 similar issue
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-7/igt@kms_scaling_modes@scaling-mode-full.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-mtlp: NOTRUN -> [SKIP][211] ([i915#8623])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-tglu: [PASS][212] -> [ABORT][213] ([i915#5122])
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-tglu-5/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-10/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-c-query-forked-busy:
- shard-rkl: NOTRUN -> [SKIP][214] ([i915#4070] / [i915#6768])
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-4/igt@kms_vblank@pipe-c-query-forked-busy.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-rkl: NOTRUN -> [SKIP][215] ([i915#4070] / [i915#533] / [i915#6768])
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-6/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-dg2: NOTRUN -> [SKIP][216] ([i915#2437])
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-3/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: [PASS][217] -> [FAIL][218] ([i915#7484])
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-dg2-7/igt@perf@non-zero-reason@0-rcs0.html
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-10/igt@perf@non-zero-reason@0-rcs0.html
* igt@perf_pmu@event-wait@rcs0:
- shard-mtlp: NOTRUN -> [SKIP][219] ([i915#8807])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-3/igt@perf_pmu@event-wait@rcs0.html
* igt@perf_pmu@rc6@other-idle-gt0:
- shard-dg2: NOTRUN -> [SKIP][220] ([i915#8516])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-10/igt@perf_pmu@rc6@other-idle-gt0.html
- shard-tglu: NOTRUN -> [SKIP][221] ([i915#8516])
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-6/igt@perf_pmu@rc6@other-idle-gt0.html
* igt@perf_pmu@render-node-busy-idle@ccs0:
- shard-mtlp: [PASS][222] -> [FAIL][223] ([i915#4349])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-mtlp-4/igt@perf_pmu@render-node-busy-idle@ccs0.html
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-8/igt@perf_pmu@render-node-busy-idle@ccs0.html
* igt@perf_pmu@render-node-busy-idle@vcs1:
- shard-dg2: NOTRUN -> [FAIL][224] ([i915#4349]) +7 similar issues
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-11/igt@perf_pmu@render-node-busy-idle@vcs1.html
* igt@prime_vgem@basic-gtt:
- shard-mtlp: NOTRUN -> [SKIP][225] ([i915#3708] / [i915#4077])
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-5/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@basic-read:
- shard-dg2: NOTRUN -> [SKIP][226] ([i915#3291] / [i915#3708])
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-10/igt@prime_vgem@basic-read.html
* igt@sysfs_heartbeat_interval@nopreempt@bcs0:
- shard-mtlp: [PASS][227] -> [FAIL][228] ([i915#6015])
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-mtlp-1/igt@sysfs_heartbeat_interval@nopreempt@bcs0.html
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-4/igt@sysfs_heartbeat_interval@nopreempt@bcs0.html
* igt@sysfs_preempt_timeout@timeout@vecs0:
- shard-mtlp: [PASS][229] -> [TIMEOUT][230] ([i915#7947])
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-mtlp-6/igt@sysfs_preempt_timeout@timeout@vecs0.html
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-5/igt@sysfs_preempt_timeout@timeout@vecs0.html
* igt@v3d/v3d_submit_cl@bad-multisync-pad:
- shard-mtlp: NOTRUN -> [SKIP][231] ([i915#2575]) +3 similar issues
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-6/igt@v3d/v3d_submit_cl@bad-multisync-pad.html
* igt@v3d/v3d_submit_cl@simple-flush-cache:
- shard-dg2: NOTRUN -> [SKIP][232] ([i915#2575]) +6 similar issues
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-2/igt@v3d/v3d_submit_cl@simple-flush-cache.html
* igt@v3d/v3d_submit_cl@valid-submission:
- shard-tglu: NOTRUN -> [SKIP][233] ([fdo#109315] / [i915#2575]) +3 similar issues
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-3/igt@v3d/v3d_submit_cl@valid-submission.html
* igt@v3d/v3d_submit_csd@bad-multisync-in-sync:
- shard-rkl: NOTRUN -> [SKIP][234] ([fdo#109315]) +2 similar issues
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-6/igt@v3d/v3d_submit_csd@bad-multisync-in-sync.html
* igt@vc4/vc4_mmap@mmap-bo:
- shard-dg2: NOTRUN -> [SKIP][235] ([i915#7711]) +5 similar issues
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-12/igt@vc4/vc4_mmap@mmap-bo.html
- shard-rkl: NOTRUN -> [SKIP][236] ([i915#7711]) +2 similar issues
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-1/igt@vc4/vc4_mmap@mmap-bo.html
* igt@vc4/vc4_purgeable_bo@mark-unpurgeable-purged:
- shard-tglu: NOTRUN -> [SKIP][237] ([i915#2575]) +3 similar issues
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-5/igt@vc4/vc4_purgeable_bo@mark-unpurgeable-purged.html
- shard-mtlp: NOTRUN -> [SKIP][238] ([i915#7711]) +2 similar issues
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-1/igt@vc4/vc4_purgeable_bo@mark-unpurgeable-purged.html
#### Possible fixes ####
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [FAIL][239] ([i915#7742]) -> [PASS][240] +1 similar issue
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-rkl-7/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-2/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@gem_create@create-ext-cpu-access-big:
- shard-dg2: [ABORT][241] ([i915#7461]) -> [PASS][242]
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-dg2-6/igt@gem_create@create-ext-cpu-access-big.html
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-11/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_ctx_persistence@legacy-engines-hang@bsd1:
- shard-mtlp: [FAIL][243] ([i915#2410]) -> [PASS][244]
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-mtlp-3/igt@gem_ctx_persistence@legacy-engines-hang@bsd1.html
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-3/igt@gem_ctx_persistence@legacy-engines-hang@bsd1.html
* igt@gem_eio@hibernate:
- shard-tglu: [ABORT][245] ([i915#7975] / [i915#8213] / [i915#8398]) -> [PASS][246]
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-tglu-10/igt@gem_eio@hibernate.html
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-4/igt@gem_eio@hibernate.html
* igt@gem_eio@kms:
- shard-glk: [FAIL][247] ([i915#8764]) -> [PASS][248]
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-glk1/igt@gem_eio@kms.html
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-glk8/igt@gem_eio@kms.html
* igt@gem_exec_await@wide-contexts:
- shard-dg2: [TIMEOUT][249] ([i915#5892]) -> [PASS][250]
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-dg2-7/igt@gem_exec_await@wide-contexts.html
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-7/igt@gem_exec_await@wide-contexts.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][251] ([i915#2846]) -> [PASS][252]
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-glk1/igt@gem_exec_fair@basic-deadline.html
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-glk1/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][253] ([i915#2842]) -> [PASS][254]
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-apl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][255] ([i915#2842]) -> [PASS][256]
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_schedule@deep@vcs1:
- shard-mtlp: [FAIL][257] ([i915#8606]) -> [PASS][258]
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-mtlp-6/igt@gem_exec_schedule@deep@vcs1.html
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-3/igt@gem_exec_schedule@deep@vcs1.html
* igt@gem_exec_whisper@basic-contexts-forked-all:
- shard-mtlp: [TIMEOUT][259] ([i915#8628]) -> [PASS][260]
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-mtlp-3/igt@gem_exec_whisper@basic-contexts-forked-all.html
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-6/igt@gem_exec_whisper@basic-contexts-forked-all.html
* igt@i915_hangman@engine-engine-hang@vcs0:
- shard-mtlp: [FAIL][261] ([i915#7069]) -> [PASS][262]
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-mtlp-4/igt@i915_hangman@engine-engine-hang@vcs0.html
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-2/igt@i915_hangman@engine-engine-hang@vcs0.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg2: [DMESG-WARN][263] ([i915#7061]) -> [PASS][264]
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-dg2-3/igt@i915_module_load@reload-with-fault-injection.html
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-5/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_dc@dc9-dpms:
- shard-tglu: [SKIP][265] ([i915#4281]) -> [PASS][266]
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-tglu-2/igt@i915_pm_dc@dc9-dpms.html
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-9/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rc6_residency@rc6-idle@rcs0:
- {shard-dg1}: [FAIL][267] ([i915#3591]) -> [PASS][268] +1 similar issue
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- shard-rkl: [SKIP][269] ([i915#1397]) -> [PASS][270]
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-rkl-1/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-7/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
* igt@i915_pm_rpm@gem-execbuf@smem0:
- shard-tglu: [FAIL][271] ([i915#7940]) -> [PASS][272] +1 similar issue
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-tglu-10/igt@i915_pm_rpm@gem-execbuf@smem0.html
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-9/igt@i915_pm_rpm@gem-execbuf@smem0.html
* igt@i915_pm_rpm@i2c:
- shard-dg2: [FAIL][273] ([i915#8717]) -> [PASS][274]
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-dg2-2/igt@i915_pm_rpm@i2c.html
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-10/igt@i915_pm_rpm@i2c.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- {shard-dg1}: [SKIP][275] ([i915#1397]) -> [PASS][276]
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-dg1-19/igt@i915_pm_rpm@modeset-non-lpsp.html
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg1-13/igt@i915_pm_rpm@modeset-non-lpsp.html
* igt@i915_pm_rpm@system-suspend-modeset:
- {shard-dg1}: [FAIL][277] ([i915#7940]) -> [PASS][278] +1 similar issue
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-dg1-16/igt@i915_pm_rpm@system-suspend-modeset.html
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg1-19/igt@i915_pm_rpm@system-suspend-modeset.html
* igt@i915_selftest@perf@request:
- shard-mtlp: [DMESG-FAIL][279] ([i915#8573]) -> [PASS][280]
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-mtlp-1/igt@i915_selftest@perf@request.html
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-2/igt@i915_selftest@perf@request.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
- shard-mtlp: [FAIL][281] ([i915#5138]) -> [PASS][282]
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-mtlp: [FAIL][283] ([i915#3743]) -> [PASS][284]
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-mtlp-8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-mtlp: [FAIL][285] ([i915#79]) -> [PASS][286]
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-mtlp-8/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-6/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-apl: [ABORT][287] ([i915#180]) -> [PASS][288]
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-apl1/igt@kms_flip@flip-vs-suspend@c-dp1.html
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-apl3/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt:
- shard-dg2: [FAIL][289] ([i915#6880]) -> [PASS][290]
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu:
- {shard-dg1}: [DMESG-WARN][291] -> [PASS][292]
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-dg1-19/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu.html
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1:
- shard-tglu: [FAIL][293] ([i915#8292]) -> [PASS][294]
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-tglu-2/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-7/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html
* igt@perf_pmu@most-busy-idle-check-all@rcs0:
- shard-dg2: [FAIL][295] ([i915#5234]) -> [PASS][296]
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-dg2-10/igt@perf_pmu@most-busy-idle-check-all@rcs0.html
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-10/igt@perf_pmu@most-busy-idle-check-all@rcs0.html
- {shard-dg1}: [FAIL][297] ([i915#5234]) -> [PASS][298]
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-dg1-17/igt@perf_pmu@most-busy-idle-check-all@rcs0.html
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg1-15/igt@perf_pmu@most-busy-idle-check-all@rcs0.html
- shard-mtlp: [FAIL][299] ([i915#5234]) -> [PASS][300]
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-mtlp-3/igt@perf_pmu@most-busy-idle-check-all@rcs0.html
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-7/igt@perf_pmu@most-busy-idle-check-all@rcs0.html
* igt@syncobj_timeline@reset-signaled:
- shard-dg2: [TIMEOUT][301] -> [PASS][302]
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-dg2-7/igt@syncobj_timeline@reset-signaled.html
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-11/igt@syncobj_timeline@reset-signaled.html
* igt@sysfs_timeslice_duration@timeout@vecs0:
- shard-mtlp: [ABORT][303] ([i915#8521]) -> [PASS][304]
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-mtlp-5/igt@sysfs_timeslice_duration@timeout@vecs0.html
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-2/igt@sysfs_timeslice_duration@timeout@vecs0.html
#### Warnings ####
* igt@gem_barrier_race@remote-request@rcs0:
- shard-glk: [ABORT][305] ([i915#7461] / [i915#8190]) -> [ABORT][306] ([i915#7461] / [i915#8211])
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-glk9/igt@gem_barrier_race@remote-request@rcs0.html
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-glk1/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_exec_reloc@basic-write-cpu-active:
- shard-dg2: [TIMEOUT][307] -> [SKIP][308] ([i915#3281])
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-dg2-7/igt@gem_exec_reloc@basic-write-cpu-active.html
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-1/igt@gem_exec_reloc@basic-write-cpu-active.html
* igt@gem_workarounds@suspend-resume-context:
- shard-snb: [DMESG-WARN][309] ([i915#8841]) -> [DMESG-FAIL][310] ([fdo#103375])
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-snb5/igt@gem_workarounds@suspend-resume-context.html
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-snb7/igt@gem_workarounds@suspend-resume-context.html
* igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode:
- shard-dg2: [TIMEOUT][311] -> [SKIP][312] ([i915#7828])
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-dg2-7/igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode.html
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-11/igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode.html
* igt@kms_content_protection@content_type_change:
- shard-dg2: [SKIP][313] ([i915#7118]) -> [SKIP][314] ([i915#7118] / [i915#7162])
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-dg2-2/igt@kms_content_protection@content_type_change.html
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-12/igt@kms_content_protection@content_type_change.html
* igt@kms_content_protection@mei_interface:
- shard-rkl: [SKIP][315] ([fdo#109300]) -> [SKIP][316] ([i915#7118])
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-rkl-6/igt@kms_content_protection@mei_interface.html
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-rkl-2/igt@kms_content_protection@mei_interface.html
- shard-tglu: [SKIP][317] ([fdo#109300]) -> [SKIP][318] ([i915#6944] / [i915#7116] / [i915#7118])
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-tglu-7/igt@kms_content_protection@mei_interface.html
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-tglu-6/igt@kms_content_protection@mei_interface.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-mtlp: [FAIL][319] ([i915#2346]) -> [DMESG-FAIL][320] ([i915#2017] / [i915#5954])
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-mtlp-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-mtlp-1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: [INCOMPLETE][321] ([i915#5493]) -> [CRASH][322] ([i915#7331])
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13372/shard-dg2-7/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/shard-dg2-7/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3354]: https://gitlab.freedesktop.org/drm/intel/issues/3354
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4348]: https://gitlab.freedesktop.org/drm/intel/issues/4348
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473
[i915#4475]: https://gitlab.freedesktop.org/drm/intel/issues/4475
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
[i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5234]: https://gitlab.freedesktop.org/drm/intel/issues/5234
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5892]: https://gitlab.freedesktop.org/drm/intel/issues/5892
[i915#5954]: https://gitlab.freedesktop.org/drm/intel/issues/5954
[i915#6015]: https://gitlab.freedesktop.org/drm/intel/issues/6015
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
[i915#6187]: https://gitlab.freedesktop.org/drm/intel/issues/6187
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6363]: https://gitlab.freedesktop.org/drm/intel/issues/6363
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#7061]: https://gitlab.freedesktop.org/drm/intel/issues/7061
[i915#7069]: https://gitlab.freedesktop.org/drm/intel/issues/7069
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
[i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
[i915#7331]: https://gitlab.freedesktop.org/drm/intel/issues/7331
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7484]: https://gitlab.freedesktop.org/drm/intel/issues/7484
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7790]: https://gitlab.freedesktop.org/drm/intel/issues/7790
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7916]: https://gitlab.freedesktop.org/drm/intel/issues/7916
[i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
[i915#7947]: https://gitlab.freedesktop.org/drm/intel/issues/7947
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8063]: https://gitlab.freedesktop.org/drm/intel/issues/8063
[i915#8190]: https://gitlab.freedesktop.org/drm/intel/issues/8190
[i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8398]: https://gitlab.freedesktop.org/drm/intel/issues/8398
[i915#8403]: https://gitlab.freedesktop.org/drm/intel/issues/8403
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
[i915#8516]: https://gitlab.freedesktop.org/drm/intel/issues/8516
[i915#8521]: https://gitlab.freedesktop.org/drm/intel/issues/8521
[i915#8545]: https://gitlab.freedesktop.org/drm/intel/issues/8545
[i915#8573]: https://gitlab.freedesktop.org/drm/intel/issues/8573
[i915#8606]: https://gitlab.freedesktop.org/drm/intel/issues/8606
[i915#8621]: https://gitlab.freedesktop.org/drm/intel/issues/8621
[i915#8623]: https://gitlab.freedesktop.org/drm/intel/issues/8623
[i915#8628]: https://gitlab.freedesktop.org/drm/intel/issues/8628
[i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
[i915#8717]: https://gitlab.freedesktop.org/drm/intel/issues/8717
[i915#8764]: https://gitlab.freedesktop.org/drm/intel/issues/8764
[i915#8807]: https://gitlab.freedesktop.org/drm/intel/issues/8807
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7380 -> IGTPW_9387
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_13372: 01c4678ab6c623c621a1dea438133e39711291d4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9387: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/index.html
IGT_7380: 8e65f12de2fd52c05dc48fdbcb8cfe86f6de1a75 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9387/index.html
[-- Attachment #2: Type: text/html, Size: 99088 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* [igt-dev] ○ CI.xeBAT: info for series starting with [i-g-t,1/2] lib/igt_dummyload: Extract sync spinner API
2023-07-11 16:02 ` [igt-dev] " Tvrtko Ursulin
` (4 preceding siblings ...)
(?)
@ 2023-07-12 7:07 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2023-07-12 7:07 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 374 bytes --]
== Series Details ==
Series: series starting with [i-g-t,1/2] lib/igt_dummyload: Extract sync spinner API
URL : https://patchwork.freedesktop.org/series/120556/
State : info
== Summary ==
Participating hosts:
bat-pvc-2
bat-atsm-2
bat-dg2-oem2
bat-adlp-7
Missing hosts results[0]:
Results: [IGTPW_9387](https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9387/index.html)
[-- Attachment #2: Type: text/html, Size: 890 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* [igt-dev] ○ CI.xeBAT: info for series starting with [i-g-t,1/2] lib/igt_dummyload: Extract sync spinner API
2023-07-11 16:02 ` [igt-dev] " Tvrtko Ursulin
` (5 preceding siblings ...)
(?)
@ 2023-07-12 7:55 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2023-07-12 7:55 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 374 bytes --]
== Series Details ==
Series: series starting with [i-g-t,1/2] lib/igt_dummyload: Extract sync spinner API
URL : https://patchwork.freedesktop.org/series/120556/
State : info
== Summary ==
Participating hosts:
bat-pvc-2
bat-atsm-2
bat-dg2-oem2
bat-adlp-7
Missing hosts results[0]:
Results: [IGTPW_9387](https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9387/index.html)
[-- Attachment #2: Type: text/html, Size: 890 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 1/2] lib/igt_dummyload: Extract sync spinner API
2023-07-11 16:02 ` [igt-dev] " Tvrtko Ursulin
@ 2023-07-14 17:22 ` Rodrigo Vivi
-1 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Vivi @ 2023-07-14 17:22 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: igt-dev, Intel-gfx
On Tue, Jul 11, 2023 at 05:02:13PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Sync spinner API is identical and compatible with regular spinners just
> that it tries to make sure spinner is actually running on the hardware
> before returning from the constructor.
>
> A few tests already use it, one more will, so lets promote it into
> common library.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> ---
> lib/igt_dummyload.c | 105 ++++++++++++++++++++++++++++++++++++++++
> lib/igt_dummyload.h | 11 +++++
> tests/i915/drm_fdinfo.c | 81 ++++---------------------------
> tests/i915/gem_eio.c | 15 ++----
> tests/i915/perf_pmu.c | 84 +++++---------------------------
> 5 files changed, 140 insertions(+), 156 deletions(-)
>
> diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
> index 9f941cef73e6..d3cee91540b6 100644
> --- a/lib/igt_dummyload.c
> +++ b/lib/igt_dummyload.c
why here?
> @@ -33,6 +33,7 @@
> #include "drmtest.h"
> #include "i915/gem_create.h"
> #include "i915/gem_engine_topology.h"
> +#include "i915/gem.h"
> #include "i915/gem_mman.h"
> #include "i915/gem_submission.h"
> #include "igt_aux.h"
> @@ -715,6 +716,110 @@ void igt_unshare_spins(void)
> IGT_INIT_LIST_HEAD(&spin_list);
> }
>
> +/**
> + * __igt_sync_spin_poll:
> + * @i915: open i915 drm file descriptor
anyway to make this not i915 centric?
or maybe move it to or start a lib that is i915 only?
I know that we have many more lib things that are still i915 centric,
but at some point we need to start organizing it...
> + * @ahnd: allocator handle
> + * @ctx: intel_ctx_t context
> + * @e: engine to execute on
> + *
> + * Starts a recursive batch on an engine.
> + *
> + * Returns a #igt_spin_t which can be used with both standard and igt_sync_spin
> + * API family. Callers should consult @gem_class_can_store_dword to whether
> + * the target platform+engine can reliably support the igt_sync_spin API.
> + */
> +igt_spin_t *
> +__igt_sync_spin_poll(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
> + const struct intel_execution_engine2 *e)
> +{
> + struct igt_spin_factory opts = {
> + .ahnd = ahnd,
> + .ctx = ctx,
> + .engine = e ? e->flags : 0,
> + };
> +
> + if (!e || gem_class_can_store_dword(i915, e->class))
> + opts.flags |= IGT_SPIN_POLL_RUN;
> +
> + return __igt_spin_factory(i915, &opts);
> +}
> +
> +/**
> + * __igt_sync_spin_wait:
> + * @i915: open i915 drm file descriptor
> + * @spin: previously create sync spinner
> + *
> + * Waits for a spinner to be running on the hardware.
> + *
> + * Callers should consult @gem_class_can_store_dword to whether the target
> + * platform+engine can reliably support the igt_sync_spin API.
> + */
> +unsigned long __igt_sync_spin_wait(int i915, igt_spin_t *spin)
> +{
> + struct timespec start = { };
> +
> + igt_nsec_elapsed(&start);
> +
> + if (igt_spin_has_poll(spin)) {
> + unsigned long timeout = 0;
> +
> + while (!igt_spin_has_started(spin)) {
> + unsigned long t = igt_nsec_elapsed(&start);
> +
> + igt_assert(gem_bo_busy(i915, spin->handle));
> + if ((t - timeout) > 250e6) {
> + timeout = t;
> + igt_warn("Spinner not running after %.2fms\n",
> + (double)t / 1e6);
> + igt_assert(t < 2e9);
> + }
> + }
> + } else {
> + igt_debug("__spin_wait - usleep mode\n");
> + usleep(500e3); /* Better than nothing! */
> + }
> +
> + igt_assert(gem_bo_busy(i915, spin->handle));
> + return igt_nsec_elapsed(&start);
> +}
> +
> +igt_spin_t *
> +__igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
> + const struct intel_execution_engine2 *e)
> +{
> + igt_spin_t *spin = __igt_sync_spin_poll(i915, ahnd, ctx, e);
> +
> + __igt_sync_spin_wait(i915, spin);
> +
> + return spin;
> +}
> +
> +/**
> + * igt_sync_spin:
> + * @i915: open i915 drm file descriptor
> + * @ahnd: allocator handle
> + * @ctx: intel_ctx_t context
> + * @e: engine to execute on
> + *
> + * Starts a recursive batch on an engine.
> + *
> + * Returns a #igt_spin_t and tries to guarantee it to be running at the time of
> + * the return. Otherwise it does a best effort only. Callers should check for
> + * @gem_class_can_store_dword if they want to be sure guarantee can be given.
> + *
> + * Both standard and igt_sync_spin API family can be used on the returned
> + * spinner object.
> + */
> +igt_spin_t *
> +igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
> + const struct intel_execution_engine2 *e)
> +{
> + igt_require_gem(i915);
> +
> + return __igt_sync_spin(i915, ahnd, ctx, e);
> +}
> +
> static uint32_t plug_vgem_handle(struct igt_cork *cork, int fd)
> {
> struct vgem_bo bo;
> diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
> index 6eb3f2e696bb..b771011af74f 100644
> --- a/lib/igt_dummyload.h
> +++ b/lib/igt_dummyload.h
> @@ -143,6 +143,17 @@ void igt_terminate_spins(void);
> void igt_unshare_spins(void);
> void igt_free_spins(int i915);
>
> +struct intel_execution_engine2;
> +
> +igt_spin_t *__igt_sync_spin_poll(int i915, uint64_t ahnd,
> + const intel_ctx_t *ctx,
> + const struct intel_execution_engine2 *e);
> +unsigned long __igt_sync_spin_wait(int i915, igt_spin_t *spin);
> +igt_spin_t *__igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
> + const struct intel_execution_engine2 *e);
> +igt_spin_t *igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
> + const struct intel_execution_engine2 *e);
> +
> enum igt_cork_type {
> CORK_SYNC_FD = 1,
> CORK_VGEM_HANDLE
> diff --git a/tests/i915/drm_fdinfo.c b/tests/i915/drm_fdinfo.c
> index c0e0ba1905f1..5cafa0e469e2 100644
> --- a/tests/i915/drm_fdinfo.c
> +++ b/tests/i915/drm_fdinfo.c
> @@ -138,68 +138,6 @@ static unsigned int measured_usleep(unsigned int usec)
> #define FLAG_HANG (8)
> #define TEST_ISOLATION (16)
>
> -static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> - const struct intel_execution_engine2 *e)
> -{
> - struct igt_spin_factory opts = {
> - .ahnd = ahnd,
> - .ctx = ctx,
> - .engine = e ? e->flags : 0,
> - };
> -
> - if (!e || gem_class_can_store_dword(fd, e->class))
> - opts.flags |= IGT_SPIN_POLL_RUN;
> -
> - return __igt_spin_factory(fd, &opts);
> -}
> -
> -static unsigned long __spin_wait(int fd, igt_spin_t *spin)
> -{
> - struct timespec start = { };
> -
> - igt_nsec_elapsed(&start);
> -
> - if (igt_spin_has_poll(spin)) {
> - unsigned long timeout = 0;
> -
> - while (!igt_spin_has_started(spin)) {
> - unsigned long t = igt_nsec_elapsed(&start);
> -
> - igt_assert(gem_bo_busy(fd, spin->handle));
> - if ((t - timeout) > 250e6) {
> - timeout = t;
> - igt_warn("Spinner not running after %.2fms\n",
> - (double)t / 1e6);
> - igt_assert(t < 2e9);
> - }
> - }
> - } else {
> - igt_debug("__spin_wait - usleep mode\n");
> - usleep(500e3); /* Better than nothing! */
> - }
> -
> - igt_assert(gem_bo_busy(fd, spin->handle));
> - return igt_nsec_elapsed(&start);
> -}
> -
> -static igt_spin_t *__spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> - const struct intel_execution_engine2 *e)
> -{
> - igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, e);
> -
> - __spin_wait(fd, spin);
> -
> - return spin;
> -}
> -
> -static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> - const struct intel_execution_engine2 *e)
> -{
> - igt_require_gem(fd);
> -
> - return __spin_sync(fd, ahnd, ctx, e);
> -}
> -
> static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
> {
> if (!spin)
> @@ -264,7 +202,7 @@ single(int gem_fd, const intel_ctx_t *ctx,
> ahnd = get_reloc_ahnd(spin_fd, ctx->id);
>
> if (flags & TEST_BUSY)
> - spin = spin_sync(spin_fd, ahnd, ctx, e);
> + spin = igt_sync_spin(spin_fd, ahnd, ctx, e);
> else
> spin = NULL;
>
> @@ -349,7 +287,7 @@ busy_check_all(int gem_fd, const intel_ctx_t *ctx,
>
> memset(tval, 0, sizeof(tval));
>
> - spin = spin_sync(gem_fd, ahnd, ctx, e);
> + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
>
> read_busy_all(gem_fd, tval[0]);
> slept = measured_usleep(batch_duration_ns / 1000);
> @@ -418,14 +356,14 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> __submit_spin(gem_fd, spin, e_, 64);
> busy_class[e_->class]++;
> } else {
> - spin = __spin_poll(gem_fd, ahnd, ctx, e_);
> + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e_);
> busy_class[e_->class]++;
> }
> }
> igt_require(spin); /* at least one busy engine */
>
> /* Small delay to allow engines to start. */
> - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
>
> read_busy_all(gem_fd, tval[0]);
> slept = measured_usleep(batch_duration_ns / 1000);
> @@ -475,12 +413,12 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> if (spin)
> __submit_spin(gem_fd, spin, e, 64);
> else
> - spin = __spin_poll(gem_fd, ahnd, ctx, e);
> + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e);
> busy_class[e->class]++;
> }
>
> /* Small delay to allow engines to start. */
> - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
>
> read_busy_all(gem_fd, tval[0]);
> slept = measured_usleep(batch_duration_ns / 1000);
> @@ -624,7 +562,7 @@ virtual(int i915, const intel_ctx_cfg_t *base_cfg, unsigned int flags)
> ahnd = get_reloc_ahnd(i915, ctx->id);
>
> if (flags & TEST_BUSY)
> - spin = spin_sync(i915, ahnd, ctx, NULL);
> + spin = igt_sync_spin(i915, ahnd, ctx, NULL);
> else
> spin = NULL;
>
> @@ -732,11 +670,12 @@ virtual_all(int i915, const intel_ctx_cfg_t *base_cfg, unsigned int flags)
> if (spin)
> __virt_submit_spin(i915, spin, ctx[i], 64);
> else
> - spin = __spin_poll(i915, ahnd, ctx[i], NULL);
> + spin = __igt_sync_spin_poll(i915, ahnd, ctx[i],
> + NULL);
> }
>
> /* Small delay to allow engines to start. */
> - usleep(__spin_wait(i915, spin) * count / 1e3);
> + usleep(__igt_sync_spin_wait(i915, spin) * count / 1e3);
>
> val = read_busy(i915, class);
> slept = measured_usleep(batch_duration_ns / 1000);
> diff --git a/tests/i915/gem_eio.c b/tests/i915/gem_eio.c
> index d889d67dcebd..6d4b8f7df909 100644
> --- a/tests/i915/gem_eio.c
> +++ b/tests/i915/gem_eio.c
> @@ -47,6 +47,7 @@
> #include "i915/gem_ring.h"
> #include "igt.h"
> #include "igt_device.h"
> +#include "igt_dummyload.h"
> #include "igt_fb.h"
> #include "igt_kms.h"
> #include "igt_stats.h"
> @@ -429,22 +430,12 @@ static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> return __igt_spin_factory(fd, &opts);
> }
>
> -static void __spin_wait(int fd, igt_spin_t *spin)
> -{
> - if (igt_spin_has_poll(spin)) {
> - igt_spin_busywait_until_started(spin);
> - } else {
> - igt_debug("__spin_wait - usleep mode\n");
> - usleep(500e3); /* Better than nothing! */
> - }
> -}
> -
> static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> unsigned long flags)
> {
> igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, flags);
>
> - __spin_wait(fd, spin);
> + __igt_sync_spin_wait(fd, spin);
>
> return spin;
> }
> @@ -963,7 +954,7 @@ static void test_inflight_external(int fd)
> fence = execbuf.rsvd2 >> 32;
> igt_assert(fence != -1);
>
> - __spin_wait(fd, hang);
> + __igt_sync_spin_wait(fd, hang);
> manual_hang(fd);
>
> gem_sync(fd, hang->handle); /* wedged, with an unready batch */
> diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
> index 0806a8e545b5..a888027ad9af 100644
> --- a/tests/i915/perf_pmu.c
> +++ b/tests/i915/perf_pmu.c
> @@ -377,68 +377,6 @@ static unsigned int measured_usleep(unsigned int usec)
> #define TEST_OTHER (128)
> #define TEST_ALL (256)
>
> -static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> - const struct intel_execution_engine2 *e)
> -{
> - struct igt_spin_factory opts = {
> - .ahnd = ahnd,
> - .ctx = ctx,
> - .engine = e->flags,
> - };
> -
> - if (gem_class_can_store_dword(fd, e->class))
> - opts.flags |= IGT_SPIN_POLL_RUN;
> -
> - return __igt_spin_factory(fd, &opts);
> -}
> -
> -static unsigned long __spin_wait(int fd, igt_spin_t *spin)
> -{
> - struct timespec start = { };
> -
> - igt_nsec_elapsed(&start);
> -
> - if (igt_spin_has_poll(spin)) {
> - unsigned long timeout = 0;
> -
> - while (!igt_spin_has_started(spin)) {
> - unsigned long t = igt_nsec_elapsed(&start);
> -
> - igt_assert(gem_bo_busy(fd, spin->handle));
> - if ((t - timeout) > 250e6) {
> - timeout = t;
> - igt_warn("Spinner not running after %.2fms\n",
> - (double)t / 1e6);
> - igt_assert(t < 2e9);
> - }
> - }
> - } else {
> - igt_debug("__spin_wait - usleep mode\n");
> - usleep(500e3); /* Better than nothing! */
> - }
> -
> - igt_assert(gem_bo_busy(fd, spin->handle));
> - return igt_nsec_elapsed(&start);
> -}
> -
> -static igt_spin_t *__spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> - const struct intel_execution_engine2 *e)
> -{
> - igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, e);
> -
> - __spin_wait(fd, spin);
> -
> - return spin;
> -}
> -
> -static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> - const struct intel_execution_engine2 *e)
> -{
> - igt_require_gem(fd);
> -
> - return __spin_sync(fd, ahnd, ctx, e);
> -}
> -
> static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
> {
> if (!spin)
> @@ -484,7 +422,7 @@ single(int gem_fd, const intel_ctx_t *ctx,
> fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> if (flags & TEST_BUSY)
> - spin = spin_sync(gem_fd, ahnd, ctx, e);
> + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
> else
> spin = NULL;
>
> @@ -536,7 +474,7 @@ busy_start(int gem_fd, const intel_ctx_t *ctx,
> */
> sleep(2);
>
> - spin = __spin_sync(gem_fd, ahnd, ctx, e);
> + spin = __igt_sync_spin(gem_fd, ahnd, ctx, e);
>
> fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> @@ -583,7 +521,7 @@ busy_double_start(int gem_fd, const intel_ctx_t *ctx,
> * re-submission in execlists mode. Make sure busyness is correctly
> * reported with the engine busy, and after the engine went idle.
> */
> - spin[0] = __spin_sync(gem_fd, ahnd, ctx, e);
> + spin[0] = __igt_sync_spin(gem_fd, ahnd, ctx, e);
> usleep(500e3);
> spin[1] = __igt_spin_new(gem_fd,
> .ahnd = ahndN,
> @@ -675,7 +613,7 @@ busy_check_all(int gem_fd, const intel_ctx_t *ctx,
>
> igt_assert_eq(i, num_engines);
>
> - spin = spin_sync(gem_fd, ahnd, ctx, e);
> + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
> pmu_read_multi(fd[0], num_engines, tval[0]);
> slept = measured_usleep(batch_duration_ns / 1000);
> if (flags & TEST_TRAILING_IDLE)
> @@ -737,7 +675,7 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> else if (spin)
> __submit_spin(gem_fd, spin, e_, 64);
> else
> - spin = __spin_poll(gem_fd, ahnd, ctx, e_);
> + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e_);
>
> val[i++] = I915_PMU_ENGINE_BUSY(e_->class, e_->instance);
> }
> @@ -749,7 +687,7 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> fd[i] = open_group(gem_fd, val[i], fd[0]);
>
> /* Small delay to allow engines to start. */
> - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
>
> pmu_read_multi(fd[0], num_engines, tval[0]);
> slept = measured_usleep(batch_duration_ns / 1000);
> @@ -796,7 +734,7 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> if (spin)
> __submit_spin(gem_fd, spin, e, 64);
> else
> - spin = __spin_poll(gem_fd, ahnd, ctx, e);
> + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e);
>
> val[i++] = I915_PMU_ENGINE_BUSY(e->class, e->instance);
> }
> @@ -807,7 +745,7 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> fd[i] = open_group(gem_fd, val[i], fd[0]);
>
> /* Small delay to allow engines to start. */
> - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
>
> pmu_read_multi(fd[0], num_engines, tval[0]);
> slept = measured_usleep(batch_duration_ns / 1000);
> @@ -848,7 +786,7 @@ no_sema(int gem_fd, const intel_ctx_t *ctx,
> fd[0]);
>
> if (flags & TEST_BUSY)
> - spin = spin_sync(gem_fd, ahnd, ctx, e);
> + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
> else
> spin = NULL;
>
> @@ -1406,7 +1344,7 @@ multi_client(int gem_fd, const intel_ctx_t *ctx,
> */
> fd[1] = open_pmu(gem_fd, config);
>
> - spin = spin_sync(gem_fd, ahnd, ctx, e);
> + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
>
> val[0] = val[1] = __pmu_read_single(fd[0], &ts[0]);
> slept[1] = measured_usleep(batch_duration_ns / 1000);
> @@ -1776,7 +1714,7 @@ static igt_spin_t *spin_sync_gt(int i915, uint64_t ahnd, unsigned int gt,
>
> igt_debug("Using engine %u:%u\n", e.class, e.instance);
>
> - return spin_sync(i915, ahnd, *ctx, &e);
> + return igt_sync_spin(i915, ahnd, *ctx, &e);
> }
>
> static void
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/2] lib/igt_dummyload: Extract sync spinner API
@ 2023-07-14 17:22 ` Rodrigo Vivi
0 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Vivi @ 2023-07-14 17:22 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: igt-dev, Intel-gfx, Tvrtko Ursulin
On Tue, Jul 11, 2023 at 05:02:13PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Sync spinner API is identical and compatible with regular spinners just
> that it tries to make sure spinner is actually running on the hardware
> before returning from the constructor.
>
> A few tests already use it, one more will, so lets promote it into
> common library.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> ---
> lib/igt_dummyload.c | 105 ++++++++++++++++++++++++++++++++++++++++
> lib/igt_dummyload.h | 11 +++++
> tests/i915/drm_fdinfo.c | 81 ++++---------------------------
> tests/i915/gem_eio.c | 15 ++----
> tests/i915/perf_pmu.c | 84 +++++---------------------------
> 5 files changed, 140 insertions(+), 156 deletions(-)
>
> diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
> index 9f941cef73e6..d3cee91540b6 100644
> --- a/lib/igt_dummyload.c
> +++ b/lib/igt_dummyload.c
why here?
> @@ -33,6 +33,7 @@
> #include "drmtest.h"
> #include "i915/gem_create.h"
> #include "i915/gem_engine_topology.h"
> +#include "i915/gem.h"
> #include "i915/gem_mman.h"
> #include "i915/gem_submission.h"
> #include "igt_aux.h"
> @@ -715,6 +716,110 @@ void igt_unshare_spins(void)
> IGT_INIT_LIST_HEAD(&spin_list);
> }
>
> +/**
> + * __igt_sync_spin_poll:
> + * @i915: open i915 drm file descriptor
anyway to make this not i915 centric?
or maybe move it to or start a lib that is i915 only?
I know that we have many more lib things that are still i915 centric,
but at some point we need to start organizing it...
> + * @ahnd: allocator handle
> + * @ctx: intel_ctx_t context
> + * @e: engine to execute on
> + *
> + * Starts a recursive batch on an engine.
> + *
> + * Returns a #igt_spin_t which can be used with both standard and igt_sync_spin
> + * API family. Callers should consult @gem_class_can_store_dword to whether
> + * the target platform+engine can reliably support the igt_sync_spin API.
> + */
> +igt_spin_t *
> +__igt_sync_spin_poll(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
> + const struct intel_execution_engine2 *e)
> +{
> + struct igt_spin_factory opts = {
> + .ahnd = ahnd,
> + .ctx = ctx,
> + .engine = e ? e->flags : 0,
> + };
> +
> + if (!e || gem_class_can_store_dword(i915, e->class))
> + opts.flags |= IGT_SPIN_POLL_RUN;
> +
> + return __igt_spin_factory(i915, &opts);
> +}
> +
> +/**
> + * __igt_sync_spin_wait:
> + * @i915: open i915 drm file descriptor
> + * @spin: previously create sync spinner
> + *
> + * Waits for a spinner to be running on the hardware.
> + *
> + * Callers should consult @gem_class_can_store_dword to whether the target
> + * platform+engine can reliably support the igt_sync_spin API.
> + */
> +unsigned long __igt_sync_spin_wait(int i915, igt_spin_t *spin)
> +{
> + struct timespec start = { };
> +
> + igt_nsec_elapsed(&start);
> +
> + if (igt_spin_has_poll(spin)) {
> + unsigned long timeout = 0;
> +
> + while (!igt_spin_has_started(spin)) {
> + unsigned long t = igt_nsec_elapsed(&start);
> +
> + igt_assert(gem_bo_busy(i915, spin->handle));
> + if ((t - timeout) > 250e6) {
> + timeout = t;
> + igt_warn("Spinner not running after %.2fms\n",
> + (double)t / 1e6);
> + igt_assert(t < 2e9);
> + }
> + }
> + } else {
> + igt_debug("__spin_wait - usleep mode\n");
> + usleep(500e3); /* Better than nothing! */
> + }
> +
> + igt_assert(gem_bo_busy(i915, spin->handle));
> + return igt_nsec_elapsed(&start);
> +}
> +
> +igt_spin_t *
> +__igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
> + const struct intel_execution_engine2 *e)
> +{
> + igt_spin_t *spin = __igt_sync_spin_poll(i915, ahnd, ctx, e);
> +
> + __igt_sync_spin_wait(i915, spin);
> +
> + return spin;
> +}
> +
> +/**
> + * igt_sync_spin:
> + * @i915: open i915 drm file descriptor
> + * @ahnd: allocator handle
> + * @ctx: intel_ctx_t context
> + * @e: engine to execute on
> + *
> + * Starts a recursive batch on an engine.
> + *
> + * Returns a #igt_spin_t and tries to guarantee it to be running at the time of
> + * the return. Otherwise it does a best effort only. Callers should check for
> + * @gem_class_can_store_dword if they want to be sure guarantee can be given.
> + *
> + * Both standard and igt_sync_spin API family can be used on the returned
> + * spinner object.
> + */
> +igt_spin_t *
> +igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
> + const struct intel_execution_engine2 *e)
> +{
> + igt_require_gem(i915);
> +
> + return __igt_sync_spin(i915, ahnd, ctx, e);
> +}
> +
> static uint32_t plug_vgem_handle(struct igt_cork *cork, int fd)
> {
> struct vgem_bo bo;
> diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
> index 6eb3f2e696bb..b771011af74f 100644
> --- a/lib/igt_dummyload.h
> +++ b/lib/igt_dummyload.h
> @@ -143,6 +143,17 @@ void igt_terminate_spins(void);
> void igt_unshare_spins(void);
> void igt_free_spins(int i915);
>
> +struct intel_execution_engine2;
> +
> +igt_spin_t *__igt_sync_spin_poll(int i915, uint64_t ahnd,
> + const intel_ctx_t *ctx,
> + const struct intel_execution_engine2 *e);
> +unsigned long __igt_sync_spin_wait(int i915, igt_spin_t *spin);
> +igt_spin_t *__igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
> + const struct intel_execution_engine2 *e);
> +igt_spin_t *igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
> + const struct intel_execution_engine2 *e);
> +
> enum igt_cork_type {
> CORK_SYNC_FD = 1,
> CORK_VGEM_HANDLE
> diff --git a/tests/i915/drm_fdinfo.c b/tests/i915/drm_fdinfo.c
> index c0e0ba1905f1..5cafa0e469e2 100644
> --- a/tests/i915/drm_fdinfo.c
> +++ b/tests/i915/drm_fdinfo.c
> @@ -138,68 +138,6 @@ static unsigned int measured_usleep(unsigned int usec)
> #define FLAG_HANG (8)
> #define TEST_ISOLATION (16)
>
> -static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> - const struct intel_execution_engine2 *e)
> -{
> - struct igt_spin_factory opts = {
> - .ahnd = ahnd,
> - .ctx = ctx,
> - .engine = e ? e->flags : 0,
> - };
> -
> - if (!e || gem_class_can_store_dword(fd, e->class))
> - opts.flags |= IGT_SPIN_POLL_RUN;
> -
> - return __igt_spin_factory(fd, &opts);
> -}
> -
> -static unsigned long __spin_wait(int fd, igt_spin_t *spin)
> -{
> - struct timespec start = { };
> -
> - igt_nsec_elapsed(&start);
> -
> - if (igt_spin_has_poll(spin)) {
> - unsigned long timeout = 0;
> -
> - while (!igt_spin_has_started(spin)) {
> - unsigned long t = igt_nsec_elapsed(&start);
> -
> - igt_assert(gem_bo_busy(fd, spin->handle));
> - if ((t - timeout) > 250e6) {
> - timeout = t;
> - igt_warn("Spinner not running after %.2fms\n",
> - (double)t / 1e6);
> - igt_assert(t < 2e9);
> - }
> - }
> - } else {
> - igt_debug("__spin_wait - usleep mode\n");
> - usleep(500e3); /* Better than nothing! */
> - }
> -
> - igt_assert(gem_bo_busy(fd, spin->handle));
> - return igt_nsec_elapsed(&start);
> -}
> -
> -static igt_spin_t *__spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> - const struct intel_execution_engine2 *e)
> -{
> - igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, e);
> -
> - __spin_wait(fd, spin);
> -
> - return spin;
> -}
> -
> -static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> - const struct intel_execution_engine2 *e)
> -{
> - igt_require_gem(fd);
> -
> - return __spin_sync(fd, ahnd, ctx, e);
> -}
> -
> static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
> {
> if (!spin)
> @@ -264,7 +202,7 @@ single(int gem_fd, const intel_ctx_t *ctx,
> ahnd = get_reloc_ahnd(spin_fd, ctx->id);
>
> if (flags & TEST_BUSY)
> - spin = spin_sync(spin_fd, ahnd, ctx, e);
> + spin = igt_sync_spin(spin_fd, ahnd, ctx, e);
> else
> spin = NULL;
>
> @@ -349,7 +287,7 @@ busy_check_all(int gem_fd, const intel_ctx_t *ctx,
>
> memset(tval, 0, sizeof(tval));
>
> - spin = spin_sync(gem_fd, ahnd, ctx, e);
> + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
>
> read_busy_all(gem_fd, tval[0]);
> slept = measured_usleep(batch_duration_ns / 1000);
> @@ -418,14 +356,14 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> __submit_spin(gem_fd, spin, e_, 64);
> busy_class[e_->class]++;
> } else {
> - spin = __spin_poll(gem_fd, ahnd, ctx, e_);
> + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e_);
> busy_class[e_->class]++;
> }
> }
> igt_require(spin); /* at least one busy engine */
>
> /* Small delay to allow engines to start. */
> - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
>
> read_busy_all(gem_fd, tval[0]);
> slept = measured_usleep(batch_duration_ns / 1000);
> @@ -475,12 +413,12 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> if (spin)
> __submit_spin(gem_fd, spin, e, 64);
> else
> - spin = __spin_poll(gem_fd, ahnd, ctx, e);
> + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e);
> busy_class[e->class]++;
> }
>
> /* Small delay to allow engines to start. */
> - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
>
> read_busy_all(gem_fd, tval[0]);
> slept = measured_usleep(batch_duration_ns / 1000);
> @@ -624,7 +562,7 @@ virtual(int i915, const intel_ctx_cfg_t *base_cfg, unsigned int flags)
> ahnd = get_reloc_ahnd(i915, ctx->id);
>
> if (flags & TEST_BUSY)
> - spin = spin_sync(i915, ahnd, ctx, NULL);
> + spin = igt_sync_spin(i915, ahnd, ctx, NULL);
> else
> spin = NULL;
>
> @@ -732,11 +670,12 @@ virtual_all(int i915, const intel_ctx_cfg_t *base_cfg, unsigned int flags)
> if (spin)
> __virt_submit_spin(i915, spin, ctx[i], 64);
> else
> - spin = __spin_poll(i915, ahnd, ctx[i], NULL);
> + spin = __igt_sync_spin_poll(i915, ahnd, ctx[i],
> + NULL);
> }
>
> /* Small delay to allow engines to start. */
> - usleep(__spin_wait(i915, spin) * count / 1e3);
> + usleep(__igt_sync_spin_wait(i915, spin) * count / 1e3);
>
> val = read_busy(i915, class);
> slept = measured_usleep(batch_duration_ns / 1000);
> diff --git a/tests/i915/gem_eio.c b/tests/i915/gem_eio.c
> index d889d67dcebd..6d4b8f7df909 100644
> --- a/tests/i915/gem_eio.c
> +++ b/tests/i915/gem_eio.c
> @@ -47,6 +47,7 @@
> #include "i915/gem_ring.h"
> #include "igt.h"
> #include "igt_device.h"
> +#include "igt_dummyload.h"
> #include "igt_fb.h"
> #include "igt_kms.h"
> #include "igt_stats.h"
> @@ -429,22 +430,12 @@ static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> return __igt_spin_factory(fd, &opts);
> }
>
> -static void __spin_wait(int fd, igt_spin_t *spin)
> -{
> - if (igt_spin_has_poll(spin)) {
> - igt_spin_busywait_until_started(spin);
> - } else {
> - igt_debug("__spin_wait - usleep mode\n");
> - usleep(500e3); /* Better than nothing! */
> - }
> -}
> -
> static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> unsigned long flags)
> {
> igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, flags);
>
> - __spin_wait(fd, spin);
> + __igt_sync_spin_wait(fd, spin);
>
> return spin;
> }
> @@ -963,7 +954,7 @@ static void test_inflight_external(int fd)
> fence = execbuf.rsvd2 >> 32;
> igt_assert(fence != -1);
>
> - __spin_wait(fd, hang);
> + __igt_sync_spin_wait(fd, hang);
> manual_hang(fd);
>
> gem_sync(fd, hang->handle); /* wedged, with an unready batch */
> diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
> index 0806a8e545b5..a888027ad9af 100644
> --- a/tests/i915/perf_pmu.c
> +++ b/tests/i915/perf_pmu.c
> @@ -377,68 +377,6 @@ static unsigned int measured_usleep(unsigned int usec)
> #define TEST_OTHER (128)
> #define TEST_ALL (256)
>
> -static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> - const struct intel_execution_engine2 *e)
> -{
> - struct igt_spin_factory opts = {
> - .ahnd = ahnd,
> - .ctx = ctx,
> - .engine = e->flags,
> - };
> -
> - if (gem_class_can_store_dword(fd, e->class))
> - opts.flags |= IGT_SPIN_POLL_RUN;
> -
> - return __igt_spin_factory(fd, &opts);
> -}
> -
> -static unsigned long __spin_wait(int fd, igt_spin_t *spin)
> -{
> - struct timespec start = { };
> -
> - igt_nsec_elapsed(&start);
> -
> - if (igt_spin_has_poll(spin)) {
> - unsigned long timeout = 0;
> -
> - while (!igt_spin_has_started(spin)) {
> - unsigned long t = igt_nsec_elapsed(&start);
> -
> - igt_assert(gem_bo_busy(fd, spin->handle));
> - if ((t - timeout) > 250e6) {
> - timeout = t;
> - igt_warn("Spinner not running after %.2fms\n",
> - (double)t / 1e6);
> - igt_assert(t < 2e9);
> - }
> - }
> - } else {
> - igt_debug("__spin_wait - usleep mode\n");
> - usleep(500e3); /* Better than nothing! */
> - }
> -
> - igt_assert(gem_bo_busy(fd, spin->handle));
> - return igt_nsec_elapsed(&start);
> -}
> -
> -static igt_spin_t *__spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> - const struct intel_execution_engine2 *e)
> -{
> - igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, e);
> -
> - __spin_wait(fd, spin);
> -
> - return spin;
> -}
> -
> -static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> - const struct intel_execution_engine2 *e)
> -{
> - igt_require_gem(fd);
> -
> - return __spin_sync(fd, ahnd, ctx, e);
> -}
> -
> static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
> {
> if (!spin)
> @@ -484,7 +422,7 @@ single(int gem_fd, const intel_ctx_t *ctx,
> fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> if (flags & TEST_BUSY)
> - spin = spin_sync(gem_fd, ahnd, ctx, e);
> + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
> else
> spin = NULL;
>
> @@ -536,7 +474,7 @@ busy_start(int gem_fd, const intel_ctx_t *ctx,
> */
> sleep(2);
>
> - spin = __spin_sync(gem_fd, ahnd, ctx, e);
> + spin = __igt_sync_spin(gem_fd, ahnd, ctx, e);
>
> fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> @@ -583,7 +521,7 @@ busy_double_start(int gem_fd, const intel_ctx_t *ctx,
> * re-submission in execlists mode. Make sure busyness is correctly
> * reported with the engine busy, and after the engine went idle.
> */
> - spin[0] = __spin_sync(gem_fd, ahnd, ctx, e);
> + spin[0] = __igt_sync_spin(gem_fd, ahnd, ctx, e);
> usleep(500e3);
> spin[1] = __igt_spin_new(gem_fd,
> .ahnd = ahndN,
> @@ -675,7 +613,7 @@ busy_check_all(int gem_fd, const intel_ctx_t *ctx,
>
> igt_assert_eq(i, num_engines);
>
> - spin = spin_sync(gem_fd, ahnd, ctx, e);
> + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
> pmu_read_multi(fd[0], num_engines, tval[0]);
> slept = measured_usleep(batch_duration_ns / 1000);
> if (flags & TEST_TRAILING_IDLE)
> @@ -737,7 +675,7 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> else if (spin)
> __submit_spin(gem_fd, spin, e_, 64);
> else
> - spin = __spin_poll(gem_fd, ahnd, ctx, e_);
> + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e_);
>
> val[i++] = I915_PMU_ENGINE_BUSY(e_->class, e_->instance);
> }
> @@ -749,7 +687,7 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> fd[i] = open_group(gem_fd, val[i], fd[0]);
>
> /* Small delay to allow engines to start. */
> - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
>
> pmu_read_multi(fd[0], num_engines, tval[0]);
> slept = measured_usleep(batch_duration_ns / 1000);
> @@ -796,7 +734,7 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> if (spin)
> __submit_spin(gem_fd, spin, e, 64);
> else
> - spin = __spin_poll(gem_fd, ahnd, ctx, e);
> + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e);
>
> val[i++] = I915_PMU_ENGINE_BUSY(e->class, e->instance);
> }
> @@ -807,7 +745,7 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> fd[i] = open_group(gem_fd, val[i], fd[0]);
>
> /* Small delay to allow engines to start. */
> - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
>
> pmu_read_multi(fd[0], num_engines, tval[0]);
> slept = measured_usleep(batch_duration_ns / 1000);
> @@ -848,7 +786,7 @@ no_sema(int gem_fd, const intel_ctx_t *ctx,
> fd[0]);
>
> if (flags & TEST_BUSY)
> - spin = spin_sync(gem_fd, ahnd, ctx, e);
> + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
> else
> spin = NULL;
>
> @@ -1406,7 +1344,7 @@ multi_client(int gem_fd, const intel_ctx_t *ctx,
> */
> fd[1] = open_pmu(gem_fd, config);
>
> - spin = spin_sync(gem_fd, ahnd, ctx, e);
> + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
>
> val[0] = val[1] = __pmu_read_single(fd[0], &ts[0]);
> slept[1] = measured_usleep(batch_duration_ns / 1000);
> @@ -1776,7 +1714,7 @@ static igt_spin_t *spin_sync_gt(int i915, uint64_t ahnd, unsigned int gt,
>
> igt_debug("Using engine %u:%u\n", e.class, e.instance);
>
> - return spin_sync(i915, ahnd, *ctx, &e);
> + return igt_sync_spin(i915, ahnd, *ctx, &e);
> }
>
> static void
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 2/2] tests/i915_pm_rps: Exercise sysfs thresholds
2023-07-11 16:02 ` [igt-dev] " Tvrtko Ursulin
@ 2023-07-14 17:26 ` Rodrigo Vivi
-1 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Vivi @ 2023-07-14 17:26 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: igt-dev, Intel-gfx
On Tue, Jul 11, 2023 at 05:02:14PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Exercise a bunch of up and down rps thresholds to verify hardware
> is happy with them all.
>
> To limit the overall runtime relies on probability and number of runs
> to approach complete coverage.
>
> v2:
> * Common sync spinner code now in library.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> tests/i915/i915_pm_rps.c | 194 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 194 insertions(+)
>
> diff --git a/tests/i915/i915_pm_rps.c b/tests/i915/i915_pm_rps.c
> index 7044fcd81c56..8c370b35c85b 100644
> --- a/tests/i915/i915_pm_rps.c
> +++ b/tests/i915/i915_pm_rps.c
> @@ -39,8 +39,10 @@
> #include "i915/gem.h"
> #include "i915/gem_create.h"
> #include "igt.h"
> +#include "igt_aux.h"
> #include "igt_dummyload.h"
> #include "igt_perf.h"
> +#include "igt_rand.h"
> #include "igt_sysfs.h"
> /**
> * TEST: i915 pm rps
> @@ -81,6 +83,22 @@
> * SUBTEST: waitboost
> * Feature: pm_rps
> * Run type: FULL
> + *
> + * SUBTEST: thresholds
> + * Feature: pm_rps
> + * Run type: FULL
> + *
> + * SUBTEST: thresholds-idle
> + * Feature: pm_rps
> + * Run type: FULL
> + *
> + * SUBTEST: thresholds-idle-park
> + * Feature: pm_rps
> + * Run type: FULL
> + *
> + * SUBTEST: thresholds-park
> + * Feature: pm_rps
> + * Run type: FULL
> */
>
> IGT_TEST_DESCRIPTION("Render P-States tests - verify GPU frequency changes");
> @@ -920,6 +938,146 @@ static void pm_rps_exit_handler(int sig)
> drm_close_driver(drm_fd);
> }
>
> +static struct i915_engine_class_instance
> +find_dword_engine(int i915, const unsigned int gt)
> +{
> + struct i915_engine_class_instance *engines, ci = { -1, -1 };
> + unsigned int i, count;
> +
> + engines = gem_list_engines(i915, 1u << gt, ~0u, &count);
> + igt_assert(engines);
> +
> + for (i = 0; i < count; i++) {
> + if (!gem_class_can_store_dword(i915, engines[i].engine_class))
> + continue;
> +
> + ci = engines[i];
> + break;
> + }
> +
> + free(engines);
> +
> + return ci;
> +}
> +
> +static igt_spin_t *spin_sync_gt(int i915, uint64_t ahnd, unsigned int gt,
> + const intel_ctx_t **ctx)
> +{
> + struct i915_engine_class_instance ci = { -1, -1 };
> + struct intel_execution_engine2 e = { };
> +
> + ci = find_dword_engine(i915, gt);
> +
> + igt_require(ci.engine_class != (uint16_t)I915_ENGINE_CLASS_INVALID);
> +
> + if (gem_has_contexts(i915)) {
> + e.class = ci.engine_class;
> + e.instance = ci.engine_instance;
> + e.flags = 0;
> + *ctx = intel_ctx_create_for_engine(i915, e.class, e.instance);
> + } else {
> + igt_require(gt == 0); /* Impossible anyway. */
I'm confused by the comment here... if it is impossible why we have code below?!
but why impossible?
anyway, the tests below are great for the sysfs that you are adding. Thanks
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> + e.class = gem_execbuf_flags_to_engine_class(I915_EXEC_DEFAULT);
> + e.instance = 0;
> + e.flags = I915_EXEC_DEFAULT;
> + *ctx = intel_ctx_0(i915);
> + }
> +
> + igt_debug("Using engine %u:%u\n", e.class, e.instance);
> +
> + return __igt_sync_spin(i915, ahnd, *ctx, &e);
> +}
> +
> +#define TEST_IDLE 0x1
> +#define TEST_PARK 0x2
> +static void test_thresholds(int i915, unsigned int gt, unsigned int flags)
> +{
> + uint64_t ahnd = get_reloc_ahnd(i915, 0);
> + const unsigned int points = 10;
> + unsigned int def_up, def_down;
> + igt_spin_t *spin = NULL;
> + const intel_ctx_t *ctx;
> + unsigned int *ta, *tb;
> + unsigned int i;
> + int sysfs;
> +
> + sysfs = igt_sysfs_gt_open(i915, gt);
> + igt_require(sysfs >= 0);
> +
> + /* Feature test */
> + def_up = igt_sysfs_get_u32(sysfs, "rps_up_threshold_pct");
> + def_down = igt_sysfs_get_u32(sysfs, "rps_down_threshold_pct");
> + igt_require(def_up && def_down);
> +
> + /* Check invalid percentages are rejected */
> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_up_threshold_pct", 101), false);
> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_down_threshold_pct", 101), false);
> +
> + /*
> + * Invent some random up-down thresholds, but always include 0 and 100
> + * just to have some wild edge cases.
> + */
> + ta = calloc(points, sizeof(unsigned int));
> + tb = calloc(points, sizeof(unsigned int));
> + igt_require(ta && tb);
> +
> + ta[0] = tb[0] = 0;
> + ta[1] = tb[1] = 100;
> + hars_petruska_f54_1_random_seed(time(NULL));
> + for (i = 2; i < points; i++) {
> + ta[i] = hars_petruska_f54_1_random_unsafe_max(100);
> + tb[i] = hars_petruska_f54_1_random_unsafe_max(100);
> + }
> + igt_permute_array(ta, points, igt_exchange_int);
> + igt_permute_array(tb, points, igt_exchange_int);
> +
> + /* Exercise the thresholds with a GPU load to trigger park/unpark etc */
> + for (i = 0; i < points; i++) {
> + igt_info("Testing thresholds up %u%% and down %u%%...\n", ta[i], tb[i]);
> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_up_threshold_pct", ta[i]), true);
> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_down_threshold_pct", tb[i]), true);
> +
> + if (flags & TEST_IDLE) {
> + gem_quiescent_gpu(i915);
> + } else if (spin) {
> + intel_ctx_destroy(i915, ctx);
> + igt_spin_free(i915, spin);
> + spin = NULL;
> + if (flags & TEST_PARK) {
> + gem_quiescent_gpu(i915);
> + usleep(500000);
> + }
> + }
> + spin = spin_sync_gt(i915, ahnd, gt, &ctx);
> + usleep(1000000);
> + if (flags & TEST_IDLE) {
> + intel_ctx_destroy(i915, ctx);
> + igt_spin_free(i915, spin);
> + if (flags & TEST_PARK) {
> + gem_quiescent_gpu(i915);
> + usleep(500000);
> + }
> + spin = NULL;
> + }
> + }
> +
> + if (spin) {
> + intel_ctx_destroy(i915, ctx);
> + igt_spin_free(i915, spin);
> + }
> +
> + gem_quiescent_gpu(i915);
> +
> + /* Restore defaults */
> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_up_threshold_pct", def_up), true);
> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_down_threshold_pct", def_down), true);
> +
> + free(ta);
> + free(tb);
> + close(sysfs);
> + put_ahnd(ahnd);
> +}
> +
> igt_main
> {
> igt_fixture {
> @@ -1000,6 +1158,42 @@ igt_main
> igt_disallow_hang(drm_fd, hang);
> }
>
> + igt_subtest_with_dynamic("thresholds-idle") {
> + int tmp, gt;
> +
> + i915_for_each_gt(drm_fd, tmp, gt) {
> + igt_dynamic_f("gt%u", gt)
> + test_thresholds(drm_fd, gt, TEST_IDLE);
> + }
> + }
> +
> + igt_subtest_with_dynamic("thresholds") {
> + int tmp, gt;
> +
> + i915_for_each_gt(drm_fd, tmp, gt) {
> + igt_dynamic_f("gt%u", gt)
> + test_thresholds(drm_fd, gt, 0);
> + }
> + }
> +
> + igt_subtest_with_dynamic("thresholds-park") {
> + int tmp, gt;
> +
> + i915_for_each_gt(drm_fd, tmp, gt) {
> + igt_dynamic_f("gt%u", gt)
> + test_thresholds(drm_fd, gt, TEST_PARK);
> + }
> + }
> +
> + igt_subtest_with_dynamic("thresholds-idle-park") {
> + int tmp, gt;
> +
> + i915_for_each_gt(drm_fd, tmp, gt) {
> + igt_dynamic_f("gt%u", gt)
> + test_thresholds(drm_fd, gt, TEST_IDLE | TEST_PARK);
> + }
> + }
> +
> igt_fixture
> drm_close_driver(drm_fd);
> }
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/i915_pm_rps: Exercise sysfs thresholds
@ 2023-07-14 17:26 ` Rodrigo Vivi
0 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Vivi @ 2023-07-14 17:26 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: igt-dev, Intel-gfx, Tvrtko Ursulin
On Tue, Jul 11, 2023 at 05:02:14PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Exercise a bunch of up and down rps thresholds to verify hardware
> is happy with them all.
>
> To limit the overall runtime relies on probability and number of runs
> to approach complete coverage.
>
> v2:
> * Common sync spinner code now in library.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> tests/i915/i915_pm_rps.c | 194 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 194 insertions(+)
>
> diff --git a/tests/i915/i915_pm_rps.c b/tests/i915/i915_pm_rps.c
> index 7044fcd81c56..8c370b35c85b 100644
> --- a/tests/i915/i915_pm_rps.c
> +++ b/tests/i915/i915_pm_rps.c
> @@ -39,8 +39,10 @@
> #include "i915/gem.h"
> #include "i915/gem_create.h"
> #include "igt.h"
> +#include "igt_aux.h"
> #include "igt_dummyload.h"
> #include "igt_perf.h"
> +#include "igt_rand.h"
> #include "igt_sysfs.h"
> /**
> * TEST: i915 pm rps
> @@ -81,6 +83,22 @@
> * SUBTEST: waitboost
> * Feature: pm_rps
> * Run type: FULL
> + *
> + * SUBTEST: thresholds
> + * Feature: pm_rps
> + * Run type: FULL
> + *
> + * SUBTEST: thresholds-idle
> + * Feature: pm_rps
> + * Run type: FULL
> + *
> + * SUBTEST: thresholds-idle-park
> + * Feature: pm_rps
> + * Run type: FULL
> + *
> + * SUBTEST: thresholds-park
> + * Feature: pm_rps
> + * Run type: FULL
> */
>
> IGT_TEST_DESCRIPTION("Render P-States tests - verify GPU frequency changes");
> @@ -920,6 +938,146 @@ static void pm_rps_exit_handler(int sig)
> drm_close_driver(drm_fd);
> }
>
> +static struct i915_engine_class_instance
> +find_dword_engine(int i915, const unsigned int gt)
> +{
> + struct i915_engine_class_instance *engines, ci = { -1, -1 };
> + unsigned int i, count;
> +
> + engines = gem_list_engines(i915, 1u << gt, ~0u, &count);
> + igt_assert(engines);
> +
> + for (i = 0; i < count; i++) {
> + if (!gem_class_can_store_dword(i915, engines[i].engine_class))
> + continue;
> +
> + ci = engines[i];
> + break;
> + }
> +
> + free(engines);
> +
> + return ci;
> +}
> +
> +static igt_spin_t *spin_sync_gt(int i915, uint64_t ahnd, unsigned int gt,
> + const intel_ctx_t **ctx)
> +{
> + struct i915_engine_class_instance ci = { -1, -1 };
> + struct intel_execution_engine2 e = { };
> +
> + ci = find_dword_engine(i915, gt);
> +
> + igt_require(ci.engine_class != (uint16_t)I915_ENGINE_CLASS_INVALID);
> +
> + if (gem_has_contexts(i915)) {
> + e.class = ci.engine_class;
> + e.instance = ci.engine_instance;
> + e.flags = 0;
> + *ctx = intel_ctx_create_for_engine(i915, e.class, e.instance);
> + } else {
> + igt_require(gt == 0); /* Impossible anyway. */
I'm confused by the comment here... if it is impossible why we have code below?!
but why impossible?
anyway, the tests below are great for the sysfs that you are adding. Thanks
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> + e.class = gem_execbuf_flags_to_engine_class(I915_EXEC_DEFAULT);
> + e.instance = 0;
> + e.flags = I915_EXEC_DEFAULT;
> + *ctx = intel_ctx_0(i915);
> + }
> +
> + igt_debug("Using engine %u:%u\n", e.class, e.instance);
> +
> + return __igt_sync_spin(i915, ahnd, *ctx, &e);
> +}
> +
> +#define TEST_IDLE 0x1
> +#define TEST_PARK 0x2
> +static void test_thresholds(int i915, unsigned int gt, unsigned int flags)
> +{
> + uint64_t ahnd = get_reloc_ahnd(i915, 0);
> + const unsigned int points = 10;
> + unsigned int def_up, def_down;
> + igt_spin_t *spin = NULL;
> + const intel_ctx_t *ctx;
> + unsigned int *ta, *tb;
> + unsigned int i;
> + int sysfs;
> +
> + sysfs = igt_sysfs_gt_open(i915, gt);
> + igt_require(sysfs >= 0);
> +
> + /* Feature test */
> + def_up = igt_sysfs_get_u32(sysfs, "rps_up_threshold_pct");
> + def_down = igt_sysfs_get_u32(sysfs, "rps_down_threshold_pct");
> + igt_require(def_up && def_down);
> +
> + /* Check invalid percentages are rejected */
> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_up_threshold_pct", 101), false);
> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_down_threshold_pct", 101), false);
> +
> + /*
> + * Invent some random up-down thresholds, but always include 0 and 100
> + * just to have some wild edge cases.
> + */
> + ta = calloc(points, sizeof(unsigned int));
> + tb = calloc(points, sizeof(unsigned int));
> + igt_require(ta && tb);
> +
> + ta[0] = tb[0] = 0;
> + ta[1] = tb[1] = 100;
> + hars_petruska_f54_1_random_seed(time(NULL));
> + for (i = 2; i < points; i++) {
> + ta[i] = hars_petruska_f54_1_random_unsafe_max(100);
> + tb[i] = hars_petruska_f54_1_random_unsafe_max(100);
> + }
> + igt_permute_array(ta, points, igt_exchange_int);
> + igt_permute_array(tb, points, igt_exchange_int);
> +
> + /* Exercise the thresholds with a GPU load to trigger park/unpark etc */
> + for (i = 0; i < points; i++) {
> + igt_info("Testing thresholds up %u%% and down %u%%...\n", ta[i], tb[i]);
> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_up_threshold_pct", ta[i]), true);
> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_down_threshold_pct", tb[i]), true);
> +
> + if (flags & TEST_IDLE) {
> + gem_quiescent_gpu(i915);
> + } else if (spin) {
> + intel_ctx_destroy(i915, ctx);
> + igt_spin_free(i915, spin);
> + spin = NULL;
> + if (flags & TEST_PARK) {
> + gem_quiescent_gpu(i915);
> + usleep(500000);
> + }
> + }
> + spin = spin_sync_gt(i915, ahnd, gt, &ctx);
> + usleep(1000000);
> + if (flags & TEST_IDLE) {
> + intel_ctx_destroy(i915, ctx);
> + igt_spin_free(i915, spin);
> + if (flags & TEST_PARK) {
> + gem_quiescent_gpu(i915);
> + usleep(500000);
> + }
> + spin = NULL;
> + }
> + }
> +
> + if (spin) {
> + intel_ctx_destroy(i915, ctx);
> + igt_spin_free(i915, spin);
> + }
> +
> + gem_quiescent_gpu(i915);
> +
> + /* Restore defaults */
> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_up_threshold_pct", def_up), true);
> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_down_threshold_pct", def_down), true);
> +
> + free(ta);
> + free(tb);
> + close(sysfs);
> + put_ahnd(ahnd);
> +}
> +
> igt_main
> {
> igt_fixture {
> @@ -1000,6 +1158,42 @@ igt_main
> igt_disallow_hang(drm_fd, hang);
> }
>
> + igt_subtest_with_dynamic("thresholds-idle") {
> + int tmp, gt;
> +
> + i915_for_each_gt(drm_fd, tmp, gt) {
> + igt_dynamic_f("gt%u", gt)
> + test_thresholds(drm_fd, gt, TEST_IDLE);
> + }
> + }
> +
> + igt_subtest_with_dynamic("thresholds") {
> + int tmp, gt;
> +
> + i915_for_each_gt(drm_fd, tmp, gt) {
> + igt_dynamic_f("gt%u", gt)
> + test_thresholds(drm_fd, gt, 0);
> + }
> + }
> +
> + igt_subtest_with_dynamic("thresholds-park") {
> + int tmp, gt;
> +
> + i915_for_each_gt(drm_fd, tmp, gt) {
> + igt_dynamic_f("gt%u", gt)
> + test_thresholds(drm_fd, gt, TEST_PARK);
> + }
> + }
> +
> + igt_subtest_with_dynamic("thresholds-idle-park") {
> + int tmp, gt;
> +
> + i915_for_each_gt(drm_fd, tmp, gt) {
> + igt_dynamic_f("gt%u", gt)
> + test_thresholds(drm_fd, gt, TEST_IDLE | TEST_PARK);
> + }
> + }
> +
> igt_fixture
> drm_close_driver(drm_fd);
> }
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 1/2] lib/igt_dummyload: Extract sync spinner API
2023-07-14 17:22 ` Rodrigo Vivi
@ 2023-07-17 8:34 ` Tvrtko Ursulin
-1 siblings, 0 replies; 19+ messages in thread
From: Tvrtko Ursulin @ 2023-07-17 8:34 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: igt-dev, Intel-gfx
On 14/07/2023 18:22, Rodrigo Vivi wrote:
> On Tue, Jul 11, 2023 at 05:02:13PM +0100, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Sync spinner API is identical and compatible with regular spinners just
>> that it tries to make sure spinner is actually running on the hardware
>> before returning from the constructor.
>>
>> A few tests already use it, one more will, so lets promote it into
>> common library.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>> ---
>> lib/igt_dummyload.c | 105 ++++++++++++++++++++++++++++++++++++++++
>> lib/igt_dummyload.h | 11 +++++
>> tests/i915/drm_fdinfo.c | 81 ++++---------------------------
>> tests/i915/gem_eio.c | 15 ++----
>> tests/i915/perf_pmu.c | 84 +++++---------------------------
>> 5 files changed, 140 insertions(+), 156 deletions(-)
>>
>> diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
>> index 9f941cef73e6..d3cee91540b6 100644
>> --- a/lib/igt_dummyload.c
>> +++ b/lib/igt_dummyload.c
>
> why here?
>
>> @@ -33,6 +33,7 @@
>> #include "drmtest.h"
>> #include "i915/gem_create.h"
>> #include "i915/gem_engine_topology.h"
>> +#include "i915/gem.h"
>> #include "i915/gem_mman.h"
>> #include "i915/gem_submission.h"
>> #include "igt_aux.h"
>> @@ -715,6 +716,110 @@ void igt_unshare_spins(void)
>> IGT_INIT_LIST_HEAD(&spin_list);
>> }
>>
>> +/**
>> + * __igt_sync_spin_poll:
>> + * @i915: open i915 drm file descriptor
>
> anyway to make this not i915 centric?
> or maybe move it to or start a lib that is i915 only?
>
> I know that we have many more lib things that are still i915 centric,
> but at some point we need to start organizing it...
Is igt_dummyload i915/xe agnostic already? I missed that. It would be a
big ask for me to get on top of two uapis and do that.. ugh. :(
So on the "why here?" part. Assuming taking the i915 route.. where would
you suggest to put it?
Regards,
Tvrtko
>> + * @ahnd: allocator handle
>> + * @ctx: intel_ctx_t context
>> + * @e: engine to execute on
>> + *
>> + * Starts a recursive batch on an engine.
>> + *
>> + * Returns a #igt_spin_t which can be used with both standard and igt_sync_spin
>> + * API family. Callers should consult @gem_class_can_store_dword to whether
>> + * the target platform+engine can reliably support the igt_sync_spin API.
>> + */
>> +igt_spin_t *
>> +__igt_sync_spin_poll(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
>> + const struct intel_execution_engine2 *e)
>> +{
>> + struct igt_spin_factory opts = {
>> + .ahnd = ahnd,
>> + .ctx = ctx,
>> + .engine = e ? e->flags : 0,
>> + };
>> +
>> + if (!e || gem_class_can_store_dword(i915, e->class))
>> + opts.flags |= IGT_SPIN_POLL_RUN;
>> +
>> + return __igt_spin_factory(i915, &opts);
>> +}
>> +
>> +/**
>> + * __igt_sync_spin_wait:
>> + * @i915: open i915 drm file descriptor
>> + * @spin: previously create sync spinner
>> + *
>> + * Waits for a spinner to be running on the hardware.
>> + *
>> + * Callers should consult @gem_class_can_store_dword to whether the target
>> + * platform+engine can reliably support the igt_sync_spin API.
>> + */
>> +unsigned long __igt_sync_spin_wait(int i915, igt_spin_t *spin)
>> +{
>> + struct timespec start = { };
>> +
>> + igt_nsec_elapsed(&start);
>> +
>> + if (igt_spin_has_poll(spin)) {
>> + unsigned long timeout = 0;
>> +
>> + while (!igt_spin_has_started(spin)) {
>> + unsigned long t = igt_nsec_elapsed(&start);
>> +
>> + igt_assert(gem_bo_busy(i915, spin->handle));
>> + if ((t - timeout) > 250e6) {
>> + timeout = t;
>> + igt_warn("Spinner not running after %.2fms\n",
>> + (double)t / 1e6);
>> + igt_assert(t < 2e9);
>> + }
>> + }
>> + } else {
>> + igt_debug("__spin_wait - usleep mode\n");
>> + usleep(500e3); /* Better than nothing! */
>> + }
>> +
>> + igt_assert(gem_bo_busy(i915, spin->handle));
>> + return igt_nsec_elapsed(&start);
>> +}
>> +
>> +igt_spin_t *
>> +__igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
>> + const struct intel_execution_engine2 *e)
>> +{
>> + igt_spin_t *spin = __igt_sync_spin_poll(i915, ahnd, ctx, e);
>> +
>> + __igt_sync_spin_wait(i915, spin);
>> +
>> + return spin;
>> +}
>> +
>> +/**
>> + * igt_sync_spin:
>> + * @i915: open i915 drm file descriptor
>> + * @ahnd: allocator handle
>> + * @ctx: intel_ctx_t context
>> + * @e: engine to execute on
>> + *
>> + * Starts a recursive batch on an engine.
>> + *
>> + * Returns a #igt_spin_t and tries to guarantee it to be running at the time of
>> + * the return. Otherwise it does a best effort only. Callers should check for
>> + * @gem_class_can_store_dword if they want to be sure guarantee can be given.
>> + *
>> + * Both standard and igt_sync_spin API family can be used on the returned
>> + * spinner object.
>> + */
>> +igt_spin_t *
>> +igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
>> + const struct intel_execution_engine2 *e)
>> +{
>> + igt_require_gem(i915);
>> +
>> + return __igt_sync_spin(i915, ahnd, ctx, e);
>> +}
>> +
>> static uint32_t plug_vgem_handle(struct igt_cork *cork, int fd)
>> {
>> struct vgem_bo bo;
>> diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
>> index 6eb3f2e696bb..b771011af74f 100644
>> --- a/lib/igt_dummyload.h
>> +++ b/lib/igt_dummyload.h
>> @@ -143,6 +143,17 @@ void igt_terminate_spins(void);
>> void igt_unshare_spins(void);
>> void igt_free_spins(int i915);
>>
>> +struct intel_execution_engine2;
>> +
>> +igt_spin_t *__igt_sync_spin_poll(int i915, uint64_t ahnd,
>> + const intel_ctx_t *ctx,
>> + const struct intel_execution_engine2 *e);
>> +unsigned long __igt_sync_spin_wait(int i915, igt_spin_t *spin);
>> +igt_spin_t *__igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
>> + const struct intel_execution_engine2 *e);
>> +igt_spin_t *igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
>> + const struct intel_execution_engine2 *e);
>> +
>> enum igt_cork_type {
>> CORK_SYNC_FD = 1,
>> CORK_VGEM_HANDLE
>> diff --git a/tests/i915/drm_fdinfo.c b/tests/i915/drm_fdinfo.c
>> index c0e0ba1905f1..5cafa0e469e2 100644
>> --- a/tests/i915/drm_fdinfo.c
>> +++ b/tests/i915/drm_fdinfo.c
>> @@ -138,68 +138,6 @@ static unsigned int measured_usleep(unsigned int usec)
>> #define FLAG_HANG (8)
>> #define TEST_ISOLATION (16)
>>
>> -static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>> - const struct intel_execution_engine2 *e)
>> -{
>> - struct igt_spin_factory opts = {
>> - .ahnd = ahnd,
>> - .ctx = ctx,
>> - .engine = e ? e->flags : 0,
>> - };
>> -
>> - if (!e || gem_class_can_store_dword(fd, e->class))
>> - opts.flags |= IGT_SPIN_POLL_RUN;
>> -
>> - return __igt_spin_factory(fd, &opts);
>> -}
>> -
>> -static unsigned long __spin_wait(int fd, igt_spin_t *spin)
>> -{
>> - struct timespec start = { };
>> -
>> - igt_nsec_elapsed(&start);
>> -
>> - if (igt_spin_has_poll(spin)) {
>> - unsigned long timeout = 0;
>> -
>> - while (!igt_spin_has_started(spin)) {
>> - unsigned long t = igt_nsec_elapsed(&start);
>> -
>> - igt_assert(gem_bo_busy(fd, spin->handle));
>> - if ((t - timeout) > 250e6) {
>> - timeout = t;
>> - igt_warn("Spinner not running after %.2fms\n",
>> - (double)t / 1e6);
>> - igt_assert(t < 2e9);
>> - }
>> - }
>> - } else {
>> - igt_debug("__spin_wait - usleep mode\n");
>> - usleep(500e3); /* Better than nothing! */
>> - }
>> -
>> - igt_assert(gem_bo_busy(fd, spin->handle));
>> - return igt_nsec_elapsed(&start);
>> -}
>> -
>> -static igt_spin_t *__spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>> - const struct intel_execution_engine2 *e)
>> -{
>> - igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, e);
>> -
>> - __spin_wait(fd, spin);
>> -
>> - return spin;
>> -}
>> -
>> -static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>> - const struct intel_execution_engine2 *e)
>> -{
>> - igt_require_gem(fd);
>> -
>> - return __spin_sync(fd, ahnd, ctx, e);
>> -}
>> -
>> static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
>> {
>> if (!spin)
>> @@ -264,7 +202,7 @@ single(int gem_fd, const intel_ctx_t *ctx,
>> ahnd = get_reloc_ahnd(spin_fd, ctx->id);
>>
>> if (flags & TEST_BUSY)
>> - spin = spin_sync(spin_fd, ahnd, ctx, e);
>> + spin = igt_sync_spin(spin_fd, ahnd, ctx, e);
>> else
>> spin = NULL;
>>
>> @@ -349,7 +287,7 @@ busy_check_all(int gem_fd, const intel_ctx_t *ctx,
>>
>> memset(tval, 0, sizeof(tval));
>>
>> - spin = spin_sync(gem_fd, ahnd, ctx, e);
>> + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
>>
>> read_busy_all(gem_fd, tval[0]);
>> slept = measured_usleep(batch_duration_ns / 1000);
>> @@ -418,14 +356,14 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
>> __submit_spin(gem_fd, spin, e_, 64);
>> busy_class[e_->class]++;
>> } else {
>> - spin = __spin_poll(gem_fd, ahnd, ctx, e_);
>> + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e_);
>> busy_class[e_->class]++;
>> }
>> }
>> igt_require(spin); /* at least one busy engine */
>>
>> /* Small delay to allow engines to start. */
>> - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
>> + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
>>
>> read_busy_all(gem_fd, tval[0]);
>> slept = measured_usleep(batch_duration_ns / 1000);
>> @@ -475,12 +413,12 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
>> if (spin)
>> __submit_spin(gem_fd, spin, e, 64);
>> else
>> - spin = __spin_poll(gem_fd, ahnd, ctx, e);
>> + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e);
>> busy_class[e->class]++;
>> }
>>
>> /* Small delay to allow engines to start. */
>> - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
>> + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
>>
>> read_busy_all(gem_fd, tval[0]);
>> slept = measured_usleep(batch_duration_ns / 1000);
>> @@ -624,7 +562,7 @@ virtual(int i915, const intel_ctx_cfg_t *base_cfg, unsigned int flags)
>> ahnd = get_reloc_ahnd(i915, ctx->id);
>>
>> if (flags & TEST_BUSY)
>> - spin = spin_sync(i915, ahnd, ctx, NULL);
>> + spin = igt_sync_spin(i915, ahnd, ctx, NULL);
>> else
>> spin = NULL;
>>
>> @@ -732,11 +670,12 @@ virtual_all(int i915, const intel_ctx_cfg_t *base_cfg, unsigned int flags)
>> if (spin)
>> __virt_submit_spin(i915, spin, ctx[i], 64);
>> else
>> - spin = __spin_poll(i915, ahnd, ctx[i], NULL);
>> + spin = __igt_sync_spin_poll(i915, ahnd, ctx[i],
>> + NULL);
>> }
>>
>> /* Small delay to allow engines to start. */
>> - usleep(__spin_wait(i915, spin) * count / 1e3);
>> + usleep(__igt_sync_spin_wait(i915, spin) * count / 1e3);
>>
>> val = read_busy(i915, class);
>> slept = measured_usleep(batch_duration_ns / 1000);
>> diff --git a/tests/i915/gem_eio.c b/tests/i915/gem_eio.c
>> index d889d67dcebd..6d4b8f7df909 100644
>> --- a/tests/i915/gem_eio.c
>> +++ b/tests/i915/gem_eio.c
>> @@ -47,6 +47,7 @@
>> #include "i915/gem_ring.h"
>> #include "igt.h"
>> #include "igt_device.h"
>> +#include "igt_dummyload.h"
>> #include "igt_fb.h"
>> #include "igt_kms.h"
>> #include "igt_stats.h"
>> @@ -429,22 +430,12 @@ static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>> return __igt_spin_factory(fd, &opts);
>> }
>>
>> -static void __spin_wait(int fd, igt_spin_t *spin)
>> -{
>> - if (igt_spin_has_poll(spin)) {
>> - igt_spin_busywait_until_started(spin);
>> - } else {
>> - igt_debug("__spin_wait - usleep mode\n");
>> - usleep(500e3); /* Better than nothing! */
>> - }
>> -}
>> -
>> static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>> unsigned long flags)
>> {
>> igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, flags);
>>
>> - __spin_wait(fd, spin);
>> + __igt_sync_spin_wait(fd, spin);
>>
>> return spin;
>> }
>> @@ -963,7 +954,7 @@ static void test_inflight_external(int fd)
>> fence = execbuf.rsvd2 >> 32;
>> igt_assert(fence != -1);
>>
>> - __spin_wait(fd, hang);
>> + __igt_sync_spin_wait(fd, hang);
>> manual_hang(fd);
>>
>> gem_sync(fd, hang->handle); /* wedged, with an unready batch */
>> diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
>> index 0806a8e545b5..a888027ad9af 100644
>> --- a/tests/i915/perf_pmu.c
>> +++ b/tests/i915/perf_pmu.c
>> @@ -377,68 +377,6 @@ static unsigned int measured_usleep(unsigned int usec)
>> #define TEST_OTHER (128)
>> #define TEST_ALL (256)
>>
>> -static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>> - const struct intel_execution_engine2 *e)
>> -{
>> - struct igt_spin_factory opts = {
>> - .ahnd = ahnd,
>> - .ctx = ctx,
>> - .engine = e->flags,
>> - };
>> -
>> - if (gem_class_can_store_dword(fd, e->class))
>> - opts.flags |= IGT_SPIN_POLL_RUN;
>> -
>> - return __igt_spin_factory(fd, &opts);
>> -}
>> -
>> -static unsigned long __spin_wait(int fd, igt_spin_t *spin)
>> -{
>> - struct timespec start = { };
>> -
>> - igt_nsec_elapsed(&start);
>> -
>> - if (igt_spin_has_poll(spin)) {
>> - unsigned long timeout = 0;
>> -
>> - while (!igt_spin_has_started(spin)) {
>> - unsigned long t = igt_nsec_elapsed(&start);
>> -
>> - igt_assert(gem_bo_busy(fd, spin->handle));
>> - if ((t - timeout) > 250e6) {
>> - timeout = t;
>> - igt_warn("Spinner not running after %.2fms\n",
>> - (double)t / 1e6);
>> - igt_assert(t < 2e9);
>> - }
>> - }
>> - } else {
>> - igt_debug("__spin_wait - usleep mode\n");
>> - usleep(500e3); /* Better than nothing! */
>> - }
>> -
>> - igt_assert(gem_bo_busy(fd, spin->handle));
>> - return igt_nsec_elapsed(&start);
>> -}
>> -
>> -static igt_spin_t *__spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>> - const struct intel_execution_engine2 *e)
>> -{
>> - igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, e);
>> -
>> - __spin_wait(fd, spin);
>> -
>> - return spin;
>> -}
>> -
>> -static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>> - const struct intel_execution_engine2 *e)
>> -{
>> - igt_require_gem(fd);
>> -
>> - return __spin_sync(fd, ahnd, ctx, e);
>> -}
>> -
>> static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
>> {
>> if (!spin)
>> @@ -484,7 +422,7 @@ single(int gem_fd, const intel_ctx_t *ctx,
>> fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>>
>> if (flags & TEST_BUSY)
>> - spin = spin_sync(gem_fd, ahnd, ctx, e);
>> + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
>> else
>> spin = NULL;
>>
>> @@ -536,7 +474,7 @@ busy_start(int gem_fd, const intel_ctx_t *ctx,
>> */
>> sleep(2);
>>
>> - spin = __spin_sync(gem_fd, ahnd, ctx, e);
>> + spin = __igt_sync_spin(gem_fd, ahnd, ctx, e);
>>
>> fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>>
>> @@ -583,7 +521,7 @@ busy_double_start(int gem_fd, const intel_ctx_t *ctx,
>> * re-submission in execlists mode. Make sure busyness is correctly
>> * reported with the engine busy, and after the engine went idle.
>> */
>> - spin[0] = __spin_sync(gem_fd, ahnd, ctx, e);
>> + spin[0] = __igt_sync_spin(gem_fd, ahnd, ctx, e);
>> usleep(500e3);
>> spin[1] = __igt_spin_new(gem_fd,
>> .ahnd = ahndN,
>> @@ -675,7 +613,7 @@ busy_check_all(int gem_fd, const intel_ctx_t *ctx,
>>
>> igt_assert_eq(i, num_engines);
>>
>> - spin = spin_sync(gem_fd, ahnd, ctx, e);
>> + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
>> pmu_read_multi(fd[0], num_engines, tval[0]);
>> slept = measured_usleep(batch_duration_ns / 1000);
>> if (flags & TEST_TRAILING_IDLE)
>> @@ -737,7 +675,7 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
>> else if (spin)
>> __submit_spin(gem_fd, spin, e_, 64);
>> else
>> - spin = __spin_poll(gem_fd, ahnd, ctx, e_);
>> + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e_);
>>
>> val[i++] = I915_PMU_ENGINE_BUSY(e_->class, e_->instance);
>> }
>> @@ -749,7 +687,7 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
>> fd[i] = open_group(gem_fd, val[i], fd[0]);
>>
>> /* Small delay to allow engines to start. */
>> - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
>> + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
>>
>> pmu_read_multi(fd[0], num_engines, tval[0]);
>> slept = measured_usleep(batch_duration_ns / 1000);
>> @@ -796,7 +734,7 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
>> if (spin)
>> __submit_spin(gem_fd, spin, e, 64);
>> else
>> - spin = __spin_poll(gem_fd, ahnd, ctx, e);
>> + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e);
>>
>> val[i++] = I915_PMU_ENGINE_BUSY(e->class, e->instance);
>> }
>> @@ -807,7 +745,7 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
>> fd[i] = open_group(gem_fd, val[i], fd[0]);
>>
>> /* Small delay to allow engines to start. */
>> - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
>> + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
>>
>> pmu_read_multi(fd[0], num_engines, tval[0]);
>> slept = measured_usleep(batch_duration_ns / 1000);
>> @@ -848,7 +786,7 @@ no_sema(int gem_fd, const intel_ctx_t *ctx,
>> fd[0]);
>>
>> if (flags & TEST_BUSY)
>> - spin = spin_sync(gem_fd, ahnd, ctx, e);
>> + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
>> else
>> spin = NULL;
>>
>> @@ -1406,7 +1344,7 @@ multi_client(int gem_fd, const intel_ctx_t *ctx,
>> */
>> fd[1] = open_pmu(gem_fd, config);
>>
>> - spin = spin_sync(gem_fd, ahnd, ctx, e);
>> + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
>>
>> val[0] = val[1] = __pmu_read_single(fd[0], &ts[0]);
>> slept[1] = measured_usleep(batch_duration_ns / 1000);
>> @@ -1776,7 +1714,7 @@ static igt_spin_t *spin_sync_gt(int i915, uint64_t ahnd, unsigned int gt,
>>
>> igt_debug("Using engine %u:%u\n", e.class, e.instance);
>>
>> - return spin_sync(i915, ahnd, *ctx, &e);
>> + return igt_sync_spin(i915, ahnd, *ctx, &e);
>> }
>>
>> static void
>> --
>> 2.39.2
>>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/2] lib/igt_dummyload: Extract sync spinner API
@ 2023-07-17 8:34 ` Tvrtko Ursulin
0 siblings, 0 replies; 19+ messages in thread
From: Tvrtko Ursulin @ 2023-07-17 8:34 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: igt-dev, Intel-gfx, Tvrtko Ursulin
On 14/07/2023 18:22, Rodrigo Vivi wrote:
> On Tue, Jul 11, 2023 at 05:02:13PM +0100, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Sync spinner API is identical and compatible with regular spinners just
>> that it tries to make sure spinner is actually running on the hardware
>> before returning from the constructor.
>>
>> A few tests already use it, one more will, so lets promote it into
>> common library.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>> ---
>> lib/igt_dummyload.c | 105 ++++++++++++++++++++++++++++++++++++++++
>> lib/igt_dummyload.h | 11 +++++
>> tests/i915/drm_fdinfo.c | 81 ++++---------------------------
>> tests/i915/gem_eio.c | 15 ++----
>> tests/i915/perf_pmu.c | 84 +++++---------------------------
>> 5 files changed, 140 insertions(+), 156 deletions(-)
>>
>> diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
>> index 9f941cef73e6..d3cee91540b6 100644
>> --- a/lib/igt_dummyload.c
>> +++ b/lib/igt_dummyload.c
>
> why here?
>
>> @@ -33,6 +33,7 @@
>> #include "drmtest.h"
>> #include "i915/gem_create.h"
>> #include "i915/gem_engine_topology.h"
>> +#include "i915/gem.h"
>> #include "i915/gem_mman.h"
>> #include "i915/gem_submission.h"
>> #include "igt_aux.h"
>> @@ -715,6 +716,110 @@ void igt_unshare_spins(void)
>> IGT_INIT_LIST_HEAD(&spin_list);
>> }
>>
>> +/**
>> + * __igt_sync_spin_poll:
>> + * @i915: open i915 drm file descriptor
>
> anyway to make this not i915 centric?
> or maybe move it to or start a lib that is i915 only?
>
> I know that we have many more lib things that are still i915 centric,
> but at some point we need to start organizing it...
Is igt_dummyload i915/xe agnostic already? I missed that. It would be a
big ask for me to get on top of two uapis and do that.. ugh. :(
So on the "why here?" part. Assuming taking the i915 route.. where would
you suggest to put it?
Regards,
Tvrtko
>> + * @ahnd: allocator handle
>> + * @ctx: intel_ctx_t context
>> + * @e: engine to execute on
>> + *
>> + * Starts a recursive batch on an engine.
>> + *
>> + * Returns a #igt_spin_t which can be used with both standard and igt_sync_spin
>> + * API family. Callers should consult @gem_class_can_store_dword to whether
>> + * the target platform+engine can reliably support the igt_sync_spin API.
>> + */
>> +igt_spin_t *
>> +__igt_sync_spin_poll(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
>> + const struct intel_execution_engine2 *e)
>> +{
>> + struct igt_spin_factory opts = {
>> + .ahnd = ahnd,
>> + .ctx = ctx,
>> + .engine = e ? e->flags : 0,
>> + };
>> +
>> + if (!e || gem_class_can_store_dword(i915, e->class))
>> + opts.flags |= IGT_SPIN_POLL_RUN;
>> +
>> + return __igt_spin_factory(i915, &opts);
>> +}
>> +
>> +/**
>> + * __igt_sync_spin_wait:
>> + * @i915: open i915 drm file descriptor
>> + * @spin: previously create sync spinner
>> + *
>> + * Waits for a spinner to be running on the hardware.
>> + *
>> + * Callers should consult @gem_class_can_store_dword to whether the target
>> + * platform+engine can reliably support the igt_sync_spin API.
>> + */
>> +unsigned long __igt_sync_spin_wait(int i915, igt_spin_t *spin)
>> +{
>> + struct timespec start = { };
>> +
>> + igt_nsec_elapsed(&start);
>> +
>> + if (igt_spin_has_poll(spin)) {
>> + unsigned long timeout = 0;
>> +
>> + while (!igt_spin_has_started(spin)) {
>> + unsigned long t = igt_nsec_elapsed(&start);
>> +
>> + igt_assert(gem_bo_busy(i915, spin->handle));
>> + if ((t - timeout) > 250e6) {
>> + timeout = t;
>> + igt_warn("Spinner not running after %.2fms\n",
>> + (double)t / 1e6);
>> + igt_assert(t < 2e9);
>> + }
>> + }
>> + } else {
>> + igt_debug("__spin_wait - usleep mode\n");
>> + usleep(500e3); /* Better than nothing! */
>> + }
>> +
>> + igt_assert(gem_bo_busy(i915, spin->handle));
>> + return igt_nsec_elapsed(&start);
>> +}
>> +
>> +igt_spin_t *
>> +__igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
>> + const struct intel_execution_engine2 *e)
>> +{
>> + igt_spin_t *spin = __igt_sync_spin_poll(i915, ahnd, ctx, e);
>> +
>> + __igt_sync_spin_wait(i915, spin);
>> +
>> + return spin;
>> +}
>> +
>> +/**
>> + * igt_sync_spin:
>> + * @i915: open i915 drm file descriptor
>> + * @ahnd: allocator handle
>> + * @ctx: intel_ctx_t context
>> + * @e: engine to execute on
>> + *
>> + * Starts a recursive batch on an engine.
>> + *
>> + * Returns a #igt_spin_t and tries to guarantee it to be running at the time of
>> + * the return. Otherwise it does a best effort only. Callers should check for
>> + * @gem_class_can_store_dword if they want to be sure guarantee can be given.
>> + *
>> + * Both standard and igt_sync_spin API family can be used on the returned
>> + * spinner object.
>> + */
>> +igt_spin_t *
>> +igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
>> + const struct intel_execution_engine2 *e)
>> +{
>> + igt_require_gem(i915);
>> +
>> + return __igt_sync_spin(i915, ahnd, ctx, e);
>> +}
>> +
>> static uint32_t plug_vgem_handle(struct igt_cork *cork, int fd)
>> {
>> struct vgem_bo bo;
>> diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
>> index 6eb3f2e696bb..b771011af74f 100644
>> --- a/lib/igt_dummyload.h
>> +++ b/lib/igt_dummyload.h
>> @@ -143,6 +143,17 @@ void igt_terminate_spins(void);
>> void igt_unshare_spins(void);
>> void igt_free_spins(int i915);
>>
>> +struct intel_execution_engine2;
>> +
>> +igt_spin_t *__igt_sync_spin_poll(int i915, uint64_t ahnd,
>> + const intel_ctx_t *ctx,
>> + const struct intel_execution_engine2 *e);
>> +unsigned long __igt_sync_spin_wait(int i915, igt_spin_t *spin);
>> +igt_spin_t *__igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
>> + const struct intel_execution_engine2 *e);
>> +igt_spin_t *igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
>> + const struct intel_execution_engine2 *e);
>> +
>> enum igt_cork_type {
>> CORK_SYNC_FD = 1,
>> CORK_VGEM_HANDLE
>> diff --git a/tests/i915/drm_fdinfo.c b/tests/i915/drm_fdinfo.c
>> index c0e0ba1905f1..5cafa0e469e2 100644
>> --- a/tests/i915/drm_fdinfo.c
>> +++ b/tests/i915/drm_fdinfo.c
>> @@ -138,68 +138,6 @@ static unsigned int measured_usleep(unsigned int usec)
>> #define FLAG_HANG (8)
>> #define TEST_ISOLATION (16)
>>
>> -static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>> - const struct intel_execution_engine2 *e)
>> -{
>> - struct igt_spin_factory opts = {
>> - .ahnd = ahnd,
>> - .ctx = ctx,
>> - .engine = e ? e->flags : 0,
>> - };
>> -
>> - if (!e || gem_class_can_store_dword(fd, e->class))
>> - opts.flags |= IGT_SPIN_POLL_RUN;
>> -
>> - return __igt_spin_factory(fd, &opts);
>> -}
>> -
>> -static unsigned long __spin_wait(int fd, igt_spin_t *spin)
>> -{
>> - struct timespec start = { };
>> -
>> - igt_nsec_elapsed(&start);
>> -
>> - if (igt_spin_has_poll(spin)) {
>> - unsigned long timeout = 0;
>> -
>> - while (!igt_spin_has_started(spin)) {
>> - unsigned long t = igt_nsec_elapsed(&start);
>> -
>> - igt_assert(gem_bo_busy(fd, spin->handle));
>> - if ((t - timeout) > 250e6) {
>> - timeout = t;
>> - igt_warn("Spinner not running after %.2fms\n",
>> - (double)t / 1e6);
>> - igt_assert(t < 2e9);
>> - }
>> - }
>> - } else {
>> - igt_debug("__spin_wait - usleep mode\n");
>> - usleep(500e3); /* Better than nothing! */
>> - }
>> -
>> - igt_assert(gem_bo_busy(fd, spin->handle));
>> - return igt_nsec_elapsed(&start);
>> -}
>> -
>> -static igt_spin_t *__spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>> - const struct intel_execution_engine2 *e)
>> -{
>> - igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, e);
>> -
>> - __spin_wait(fd, spin);
>> -
>> - return spin;
>> -}
>> -
>> -static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>> - const struct intel_execution_engine2 *e)
>> -{
>> - igt_require_gem(fd);
>> -
>> - return __spin_sync(fd, ahnd, ctx, e);
>> -}
>> -
>> static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
>> {
>> if (!spin)
>> @@ -264,7 +202,7 @@ single(int gem_fd, const intel_ctx_t *ctx,
>> ahnd = get_reloc_ahnd(spin_fd, ctx->id);
>>
>> if (flags & TEST_BUSY)
>> - spin = spin_sync(spin_fd, ahnd, ctx, e);
>> + spin = igt_sync_spin(spin_fd, ahnd, ctx, e);
>> else
>> spin = NULL;
>>
>> @@ -349,7 +287,7 @@ busy_check_all(int gem_fd, const intel_ctx_t *ctx,
>>
>> memset(tval, 0, sizeof(tval));
>>
>> - spin = spin_sync(gem_fd, ahnd, ctx, e);
>> + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
>>
>> read_busy_all(gem_fd, tval[0]);
>> slept = measured_usleep(batch_duration_ns / 1000);
>> @@ -418,14 +356,14 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
>> __submit_spin(gem_fd, spin, e_, 64);
>> busy_class[e_->class]++;
>> } else {
>> - spin = __spin_poll(gem_fd, ahnd, ctx, e_);
>> + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e_);
>> busy_class[e_->class]++;
>> }
>> }
>> igt_require(spin); /* at least one busy engine */
>>
>> /* Small delay to allow engines to start. */
>> - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
>> + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
>>
>> read_busy_all(gem_fd, tval[0]);
>> slept = measured_usleep(batch_duration_ns / 1000);
>> @@ -475,12 +413,12 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
>> if (spin)
>> __submit_spin(gem_fd, spin, e, 64);
>> else
>> - spin = __spin_poll(gem_fd, ahnd, ctx, e);
>> + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e);
>> busy_class[e->class]++;
>> }
>>
>> /* Small delay to allow engines to start. */
>> - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
>> + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
>>
>> read_busy_all(gem_fd, tval[0]);
>> slept = measured_usleep(batch_duration_ns / 1000);
>> @@ -624,7 +562,7 @@ virtual(int i915, const intel_ctx_cfg_t *base_cfg, unsigned int flags)
>> ahnd = get_reloc_ahnd(i915, ctx->id);
>>
>> if (flags & TEST_BUSY)
>> - spin = spin_sync(i915, ahnd, ctx, NULL);
>> + spin = igt_sync_spin(i915, ahnd, ctx, NULL);
>> else
>> spin = NULL;
>>
>> @@ -732,11 +670,12 @@ virtual_all(int i915, const intel_ctx_cfg_t *base_cfg, unsigned int flags)
>> if (spin)
>> __virt_submit_spin(i915, spin, ctx[i], 64);
>> else
>> - spin = __spin_poll(i915, ahnd, ctx[i], NULL);
>> + spin = __igt_sync_spin_poll(i915, ahnd, ctx[i],
>> + NULL);
>> }
>>
>> /* Small delay to allow engines to start. */
>> - usleep(__spin_wait(i915, spin) * count / 1e3);
>> + usleep(__igt_sync_spin_wait(i915, spin) * count / 1e3);
>>
>> val = read_busy(i915, class);
>> slept = measured_usleep(batch_duration_ns / 1000);
>> diff --git a/tests/i915/gem_eio.c b/tests/i915/gem_eio.c
>> index d889d67dcebd..6d4b8f7df909 100644
>> --- a/tests/i915/gem_eio.c
>> +++ b/tests/i915/gem_eio.c
>> @@ -47,6 +47,7 @@
>> #include "i915/gem_ring.h"
>> #include "igt.h"
>> #include "igt_device.h"
>> +#include "igt_dummyload.h"
>> #include "igt_fb.h"
>> #include "igt_kms.h"
>> #include "igt_stats.h"
>> @@ -429,22 +430,12 @@ static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>> return __igt_spin_factory(fd, &opts);
>> }
>>
>> -static void __spin_wait(int fd, igt_spin_t *spin)
>> -{
>> - if (igt_spin_has_poll(spin)) {
>> - igt_spin_busywait_until_started(spin);
>> - } else {
>> - igt_debug("__spin_wait - usleep mode\n");
>> - usleep(500e3); /* Better than nothing! */
>> - }
>> -}
>> -
>> static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>> unsigned long flags)
>> {
>> igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, flags);
>>
>> - __spin_wait(fd, spin);
>> + __igt_sync_spin_wait(fd, spin);
>>
>> return spin;
>> }
>> @@ -963,7 +954,7 @@ static void test_inflight_external(int fd)
>> fence = execbuf.rsvd2 >> 32;
>> igt_assert(fence != -1);
>>
>> - __spin_wait(fd, hang);
>> + __igt_sync_spin_wait(fd, hang);
>> manual_hang(fd);
>>
>> gem_sync(fd, hang->handle); /* wedged, with an unready batch */
>> diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
>> index 0806a8e545b5..a888027ad9af 100644
>> --- a/tests/i915/perf_pmu.c
>> +++ b/tests/i915/perf_pmu.c
>> @@ -377,68 +377,6 @@ static unsigned int measured_usleep(unsigned int usec)
>> #define TEST_OTHER (128)
>> #define TEST_ALL (256)
>>
>> -static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>> - const struct intel_execution_engine2 *e)
>> -{
>> - struct igt_spin_factory opts = {
>> - .ahnd = ahnd,
>> - .ctx = ctx,
>> - .engine = e->flags,
>> - };
>> -
>> - if (gem_class_can_store_dword(fd, e->class))
>> - opts.flags |= IGT_SPIN_POLL_RUN;
>> -
>> - return __igt_spin_factory(fd, &opts);
>> -}
>> -
>> -static unsigned long __spin_wait(int fd, igt_spin_t *spin)
>> -{
>> - struct timespec start = { };
>> -
>> - igt_nsec_elapsed(&start);
>> -
>> - if (igt_spin_has_poll(spin)) {
>> - unsigned long timeout = 0;
>> -
>> - while (!igt_spin_has_started(spin)) {
>> - unsigned long t = igt_nsec_elapsed(&start);
>> -
>> - igt_assert(gem_bo_busy(fd, spin->handle));
>> - if ((t - timeout) > 250e6) {
>> - timeout = t;
>> - igt_warn("Spinner not running after %.2fms\n",
>> - (double)t / 1e6);
>> - igt_assert(t < 2e9);
>> - }
>> - }
>> - } else {
>> - igt_debug("__spin_wait - usleep mode\n");
>> - usleep(500e3); /* Better than nothing! */
>> - }
>> -
>> - igt_assert(gem_bo_busy(fd, spin->handle));
>> - return igt_nsec_elapsed(&start);
>> -}
>> -
>> -static igt_spin_t *__spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>> - const struct intel_execution_engine2 *e)
>> -{
>> - igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, e);
>> -
>> - __spin_wait(fd, spin);
>> -
>> - return spin;
>> -}
>> -
>> -static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>> - const struct intel_execution_engine2 *e)
>> -{
>> - igt_require_gem(fd);
>> -
>> - return __spin_sync(fd, ahnd, ctx, e);
>> -}
>> -
>> static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
>> {
>> if (!spin)
>> @@ -484,7 +422,7 @@ single(int gem_fd, const intel_ctx_t *ctx,
>> fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>>
>> if (flags & TEST_BUSY)
>> - spin = spin_sync(gem_fd, ahnd, ctx, e);
>> + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
>> else
>> spin = NULL;
>>
>> @@ -536,7 +474,7 @@ busy_start(int gem_fd, const intel_ctx_t *ctx,
>> */
>> sleep(2);
>>
>> - spin = __spin_sync(gem_fd, ahnd, ctx, e);
>> + spin = __igt_sync_spin(gem_fd, ahnd, ctx, e);
>>
>> fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>>
>> @@ -583,7 +521,7 @@ busy_double_start(int gem_fd, const intel_ctx_t *ctx,
>> * re-submission in execlists mode. Make sure busyness is correctly
>> * reported with the engine busy, and after the engine went idle.
>> */
>> - spin[0] = __spin_sync(gem_fd, ahnd, ctx, e);
>> + spin[0] = __igt_sync_spin(gem_fd, ahnd, ctx, e);
>> usleep(500e3);
>> spin[1] = __igt_spin_new(gem_fd,
>> .ahnd = ahndN,
>> @@ -675,7 +613,7 @@ busy_check_all(int gem_fd, const intel_ctx_t *ctx,
>>
>> igt_assert_eq(i, num_engines);
>>
>> - spin = spin_sync(gem_fd, ahnd, ctx, e);
>> + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
>> pmu_read_multi(fd[0], num_engines, tval[0]);
>> slept = measured_usleep(batch_duration_ns / 1000);
>> if (flags & TEST_TRAILING_IDLE)
>> @@ -737,7 +675,7 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
>> else if (spin)
>> __submit_spin(gem_fd, spin, e_, 64);
>> else
>> - spin = __spin_poll(gem_fd, ahnd, ctx, e_);
>> + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e_);
>>
>> val[i++] = I915_PMU_ENGINE_BUSY(e_->class, e_->instance);
>> }
>> @@ -749,7 +687,7 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
>> fd[i] = open_group(gem_fd, val[i], fd[0]);
>>
>> /* Small delay to allow engines to start. */
>> - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
>> + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
>>
>> pmu_read_multi(fd[0], num_engines, tval[0]);
>> slept = measured_usleep(batch_duration_ns / 1000);
>> @@ -796,7 +734,7 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
>> if (spin)
>> __submit_spin(gem_fd, spin, e, 64);
>> else
>> - spin = __spin_poll(gem_fd, ahnd, ctx, e);
>> + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e);
>>
>> val[i++] = I915_PMU_ENGINE_BUSY(e->class, e->instance);
>> }
>> @@ -807,7 +745,7 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
>> fd[i] = open_group(gem_fd, val[i], fd[0]);
>>
>> /* Small delay to allow engines to start. */
>> - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
>> + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
>>
>> pmu_read_multi(fd[0], num_engines, tval[0]);
>> slept = measured_usleep(batch_duration_ns / 1000);
>> @@ -848,7 +786,7 @@ no_sema(int gem_fd, const intel_ctx_t *ctx,
>> fd[0]);
>>
>> if (flags & TEST_BUSY)
>> - spin = spin_sync(gem_fd, ahnd, ctx, e);
>> + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
>> else
>> spin = NULL;
>>
>> @@ -1406,7 +1344,7 @@ multi_client(int gem_fd, const intel_ctx_t *ctx,
>> */
>> fd[1] = open_pmu(gem_fd, config);
>>
>> - spin = spin_sync(gem_fd, ahnd, ctx, e);
>> + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
>>
>> val[0] = val[1] = __pmu_read_single(fd[0], &ts[0]);
>> slept[1] = measured_usleep(batch_duration_ns / 1000);
>> @@ -1776,7 +1714,7 @@ static igt_spin_t *spin_sync_gt(int i915, uint64_t ahnd, unsigned int gt,
>>
>> igt_debug("Using engine %u:%u\n", e.class, e.instance);
>>
>> - return spin_sync(i915, ahnd, *ctx, &e);
>> + return igt_sync_spin(i915, ahnd, *ctx, &e);
>> }
>>
>> static void
>> --
>> 2.39.2
>>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 2/2] tests/i915_pm_rps: Exercise sysfs thresholds
2023-07-14 17:26 ` Rodrigo Vivi
@ 2023-07-17 8:37 ` Tvrtko Ursulin
-1 siblings, 0 replies; 19+ messages in thread
From: Tvrtko Ursulin @ 2023-07-17 8:37 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: igt-dev, Intel-gfx
On 14/07/2023 18:26, Rodrigo Vivi wrote:
> On Tue, Jul 11, 2023 at 05:02:14PM +0100, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Exercise a bunch of up and down rps thresholds to verify hardware
>> is happy with them all.
>>
>> To limit the overall runtime relies on probability and number of runs
>> to approach complete coverage.
>>
>> v2:
>> * Common sync spinner code now in library.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>> tests/i915/i915_pm_rps.c | 194 +++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 194 insertions(+)
>>
>> diff --git a/tests/i915/i915_pm_rps.c b/tests/i915/i915_pm_rps.c
>> index 7044fcd81c56..8c370b35c85b 100644
>> --- a/tests/i915/i915_pm_rps.c
>> +++ b/tests/i915/i915_pm_rps.c
>> @@ -39,8 +39,10 @@
>> #include "i915/gem.h"
>> #include "i915/gem_create.h"
>> #include "igt.h"
>> +#include "igt_aux.h"
>> #include "igt_dummyload.h"
>> #include "igt_perf.h"
>> +#include "igt_rand.h"
>> #include "igt_sysfs.h"
>> /**
>> * TEST: i915 pm rps
>> @@ -81,6 +83,22 @@
>> * SUBTEST: waitboost
>> * Feature: pm_rps
>> * Run type: FULL
>> + *
>> + * SUBTEST: thresholds
>> + * Feature: pm_rps
>> + * Run type: FULL
>> + *
>> + * SUBTEST: thresholds-idle
>> + * Feature: pm_rps
>> + * Run type: FULL
>> + *
>> + * SUBTEST: thresholds-idle-park
>> + * Feature: pm_rps
>> + * Run type: FULL
>> + *
>> + * SUBTEST: thresholds-park
>> + * Feature: pm_rps
>> + * Run type: FULL
>> */
>>
>> IGT_TEST_DESCRIPTION("Render P-States tests - verify GPU frequency changes");
>> @@ -920,6 +938,146 @@ static void pm_rps_exit_handler(int sig)
>> drm_close_driver(drm_fd);
>> }
>>
>> +static struct i915_engine_class_instance
>> +find_dword_engine(int i915, const unsigned int gt)
>> +{
>> + struct i915_engine_class_instance *engines, ci = { -1, -1 };
>> + unsigned int i, count;
>> +
>> + engines = gem_list_engines(i915, 1u << gt, ~0u, &count);
>> + igt_assert(engines);
>> +
>> + for (i = 0; i < count; i++) {
>> + if (!gem_class_can_store_dword(i915, engines[i].engine_class))
>> + continue;
>> +
>> + ci = engines[i];
>> + break;
>> + }
>> +
>> + free(engines);
>> +
>> + return ci;
>> +}
>> +
>> +static igt_spin_t *spin_sync_gt(int i915, uint64_t ahnd, unsigned int gt,
>> + const intel_ctx_t **ctx)
>> +{
>> + struct i915_engine_class_instance ci = { -1, -1 };
>> + struct intel_execution_engine2 e = { };
>> +
>> + ci = find_dword_engine(i915, gt);
>> +
>> + igt_require(ci.engine_class != (uint16_t)I915_ENGINE_CLASS_INVALID);
>> +
>> + if (gem_has_contexts(i915)) {
>> + e.class = ci.engine_class;
>> + e.instance = ci.engine_instance;
>> + e.flags = 0;
>> + *ctx = intel_ctx_create_for_engine(i915, e.class, e.instance);
>> + } else {
>> + igt_require(gt == 0); /* Impossible anyway. */
>
> I'm confused by the comment here... if it is impossible why we have code below?!
> but why impossible?
Only the gt != 0 part would be impossible in this !gem_has_context
branch, otherwise the branch runs on old platforms (which are always
single tile). Perhaps a case of too many asserts adding confusion?
>
> anyway, the tests below are great for the sysfs that you are adding. Thanks
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Thanks!
Regards,
Tvrtko
>
>> + e.class = gem_execbuf_flags_to_engine_class(I915_EXEC_DEFAULT);
>> + e.instance = 0;
>> + e.flags = I915_EXEC_DEFAULT;
>> + *ctx = intel_ctx_0(i915);
>> + }
>> +
>> + igt_debug("Using engine %u:%u\n", e.class, e.instance);
>> +
>> + return __igt_sync_spin(i915, ahnd, *ctx, &e);
>> +}
>> +
>> +#define TEST_IDLE 0x1
>> +#define TEST_PARK 0x2
>> +static void test_thresholds(int i915, unsigned int gt, unsigned int flags)
>> +{
>> + uint64_t ahnd = get_reloc_ahnd(i915, 0);
>> + const unsigned int points = 10;
>> + unsigned int def_up, def_down;
>> + igt_spin_t *spin = NULL;
>> + const intel_ctx_t *ctx;
>> + unsigned int *ta, *tb;
>> + unsigned int i;
>> + int sysfs;
>> +
>> + sysfs = igt_sysfs_gt_open(i915, gt);
>> + igt_require(sysfs >= 0);
>> +
>> + /* Feature test */
>> + def_up = igt_sysfs_get_u32(sysfs, "rps_up_threshold_pct");
>> + def_down = igt_sysfs_get_u32(sysfs, "rps_down_threshold_pct");
>> + igt_require(def_up && def_down);
>> +
>> + /* Check invalid percentages are rejected */
>> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_up_threshold_pct", 101), false);
>> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_down_threshold_pct", 101), false);
>> +
>> + /*
>> + * Invent some random up-down thresholds, but always include 0 and 100
>> + * just to have some wild edge cases.
>> + */
>> + ta = calloc(points, sizeof(unsigned int));
>> + tb = calloc(points, sizeof(unsigned int));
>> + igt_require(ta && tb);
>> +
>> + ta[0] = tb[0] = 0;
>> + ta[1] = tb[1] = 100;
>> + hars_petruska_f54_1_random_seed(time(NULL));
>> + for (i = 2; i < points; i++) {
>> + ta[i] = hars_petruska_f54_1_random_unsafe_max(100);
>> + tb[i] = hars_petruska_f54_1_random_unsafe_max(100);
>> + }
>> + igt_permute_array(ta, points, igt_exchange_int);
>> + igt_permute_array(tb, points, igt_exchange_int);
>> +
>> + /* Exercise the thresholds with a GPU load to trigger park/unpark etc */
>> + for (i = 0; i < points; i++) {
>> + igt_info("Testing thresholds up %u%% and down %u%%...\n", ta[i], tb[i]);
>> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_up_threshold_pct", ta[i]), true);
>> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_down_threshold_pct", tb[i]), true);
>> +
>> + if (flags & TEST_IDLE) {
>> + gem_quiescent_gpu(i915);
>> + } else if (spin) {
>> + intel_ctx_destroy(i915, ctx);
>> + igt_spin_free(i915, spin);
>> + spin = NULL;
>> + if (flags & TEST_PARK) {
>> + gem_quiescent_gpu(i915);
>> + usleep(500000);
>> + }
>> + }
>> + spin = spin_sync_gt(i915, ahnd, gt, &ctx);
>> + usleep(1000000);
>> + if (flags & TEST_IDLE) {
>> + intel_ctx_destroy(i915, ctx);
>> + igt_spin_free(i915, spin);
>> + if (flags & TEST_PARK) {
>> + gem_quiescent_gpu(i915);
>> + usleep(500000);
>> + }
>> + spin = NULL;
>> + }
>> + }
>> +
>> + if (spin) {
>> + intel_ctx_destroy(i915, ctx);
>> + igt_spin_free(i915, spin);
>> + }
>> +
>> + gem_quiescent_gpu(i915);
>> +
>> + /* Restore defaults */
>> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_up_threshold_pct", def_up), true);
>> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_down_threshold_pct", def_down), true);
>> +
>> + free(ta);
>> + free(tb);
>> + close(sysfs);
>> + put_ahnd(ahnd);
>> +}
>> +
>> igt_main
>> {
>> igt_fixture {
>> @@ -1000,6 +1158,42 @@ igt_main
>> igt_disallow_hang(drm_fd, hang);
>> }
>>
>> + igt_subtest_with_dynamic("thresholds-idle") {
>> + int tmp, gt;
>> +
>> + i915_for_each_gt(drm_fd, tmp, gt) {
>> + igt_dynamic_f("gt%u", gt)
>> + test_thresholds(drm_fd, gt, TEST_IDLE);
>> + }
>> + }
>> +
>> + igt_subtest_with_dynamic("thresholds") {
>> + int tmp, gt;
>> +
>> + i915_for_each_gt(drm_fd, tmp, gt) {
>> + igt_dynamic_f("gt%u", gt)
>> + test_thresholds(drm_fd, gt, 0);
>> + }
>> + }
>> +
>> + igt_subtest_with_dynamic("thresholds-park") {
>> + int tmp, gt;
>> +
>> + i915_for_each_gt(drm_fd, tmp, gt) {
>> + igt_dynamic_f("gt%u", gt)
>> + test_thresholds(drm_fd, gt, TEST_PARK);
>> + }
>> + }
>> +
>> + igt_subtest_with_dynamic("thresholds-idle-park") {
>> + int tmp, gt;
>> +
>> + i915_for_each_gt(drm_fd, tmp, gt) {
>> + igt_dynamic_f("gt%u", gt)
>> + test_thresholds(drm_fd, gt, TEST_IDLE | TEST_PARK);
>> + }
>> + }
>> +
>> igt_fixture
>> drm_close_driver(drm_fd);
>> }
>> --
>> 2.39.2
>>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] tests/i915_pm_rps: Exercise sysfs thresholds
@ 2023-07-17 8:37 ` Tvrtko Ursulin
0 siblings, 0 replies; 19+ messages in thread
From: Tvrtko Ursulin @ 2023-07-17 8:37 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: igt-dev, Intel-gfx, Tvrtko Ursulin
On 14/07/2023 18:26, Rodrigo Vivi wrote:
> On Tue, Jul 11, 2023 at 05:02:14PM +0100, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Exercise a bunch of up and down rps thresholds to verify hardware
>> is happy with them all.
>>
>> To limit the overall runtime relies on probability and number of runs
>> to approach complete coverage.
>>
>> v2:
>> * Common sync spinner code now in library.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>> tests/i915/i915_pm_rps.c | 194 +++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 194 insertions(+)
>>
>> diff --git a/tests/i915/i915_pm_rps.c b/tests/i915/i915_pm_rps.c
>> index 7044fcd81c56..8c370b35c85b 100644
>> --- a/tests/i915/i915_pm_rps.c
>> +++ b/tests/i915/i915_pm_rps.c
>> @@ -39,8 +39,10 @@
>> #include "i915/gem.h"
>> #include "i915/gem_create.h"
>> #include "igt.h"
>> +#include "igt_aux.h"
>> #include "igt_dummyload.h"
>> #include "igt_perf.h"
>> +#include "igt_rand.h"
>> #include "igt_sysfs.h"
>> /**
>> * TEST: i915 pm rps
>> @@ -81,6 +83,22 @@
>> * SUBTEST: waitboost
>> * Feature: pm_rps
>> * Run type: FULL
>> + *
>> + * SUBTEST: thresholds
>> + * Feature: pm_rps
>> + * Run type: FULL
>> + *
>> + * SUBTEST: thresholds-idle
>> + * Feature: pm_rps
>> + * Run type: FULL
>> + *
>> + * SUBTEST: thresholds-idle-park
>> + * Feature: pm_rps
>> + * Run type: FULL
>> + *
>> + * SUBTEST: thresholds-park
>> + * Feature: pm_rps
>> + * Run type: FULL
>> */
>>
>> IGT_TEST_DESCRIPTION("Render P-States tests - verify GPU frequency changes");
>> @@ -920,6 +938,146 @@ static void pm_rps_exit_handler(int sig)
>> drm_close_driver(drm_fd);
>> }
>>
>> +static struct i915_engine_class_instance
>> +find_dword_engine(int i915, const unsigned int gt)
>> +{
>> + struct i915_engine_class_instance *engines, ci = { -1, -1 };
>> + unsigned int i, count;
>> +
>> + engines = gem_list_engines(i915, 1u << gt, ~0u, &count);
>> + igt_assert(engines);
>> +
>> + for (i = 0; i < count; i++) {
>> + if (!gem_class_can_store_dword(i915, engines[i].engine_class))
>> + continue;
>> +
>> + ci = engines[i];
>> + break;
>> + }
>> +
>> + free(engines);
>> +
>> + return ci;
>> +}
>> +
>> +static igt_spin_t *spin_sync_gt(int i915, uint64_t ahnd, unsigned int gt,
>> + const intel_ctx_t **ctx)
>> +{
>> + struct i915_engine_class_instance ci = { -1, -1 };
>> + struct intel_execution_engine2 e = { };
>> +
>> + ci = find_dword_engine(i915, gt);
>> +
>> + igt_require(ci.engine_class != (uint16_t)I915_ENGINE_CLASS_INVALID);
>> +
>> + if (gem_has_contexts(i915)) {
>> + e.class = ci.engine_class;
>> + e.instance = ci.engine_instance;
>> + e.flags = 0;
>> + *ctx = intel_ctx_create_for_engine(i915, e.class, e.instance);
>> + } else {
>> + igt_require(gt == 0); /* Impossible anyway. */
>
> I'm confused by the comment here... if it is impossible why we have code below?!
> but why impossible?
Only the gt != 0 part would be impossible in this !gem_has_context
branch, otherwise the branch runs on old platforms (which are always
single tile). Perhaps a case of too many asserts adding confusion?
>
> anyway, the tests below are great for the sysfs that you are adding. Thanks
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Thanks!
Regards,
Tvrtko
>
>> + e.class = gem_execbuf_flags_to_engine_class(I915_EXEC_DEFAULT);
>> + e.instance = 0;
>> + e.flags = I915_EXEC_DEFAULT;
>> + *ctx = intel_ctx_0(i915);
>> + }
>> +
>> + igt_debug("Using engine %u:%u\n", e.class, e.instance);
>> +
>> + return __igt_sync_spin(i915, ahnd, *ctx, &e);
>> +}
>> +
>> +#define TEST_IDLE 0x1
>> +#define TEST_PARK 0x2
>> +static void test_thresholds(int i915, unsigned int gt, unsigned int flags)
>> +{
>> + uint64_t ahnd = get_reloc_ahnd(i915, 0);
>> + const unsigned int points = 10;
>> + unsigned int def_up, def_down;
>> + igt_spin_t *spin = NULL;
>> + const intel_ctx_t *ctx;
>> + unsigned int *ta, *tb;
>> + unsigned int i;
>> + int sysfs;
>> +
>> + sysfs = igt_sysfs_gt_open(i915, gt);
>> + igt_require(sysfs >= 0);
>> +
>> + /* Feature test */
>> + def_up = igt_sysfs_get_u32(sysfs, "rps_up_threshold_pct");
>> + def_down = igt_sysfs_get_u32(sysfs, "rps_down_threshold_pct");
>> + igt_require(def_up && def_down);
>> +
>> + /* Check invalid percentages are rejected */
>> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_up_threshold_pct", 101), false);
>> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_down_threshold_pct", 101), false);
>> +
>> + /*
>> + * Invent some random up-down thresholds, but always include 0 and 100
>> + * just to have some wild edge cases.
>> + */
>> + ta = calloc(points, sizeof(unsigned int));
>> + tb = calloc(points, sizeof(unsigned int));
>> + igt_require(ta && tb);
>> +
>> + ta[0] = tb[0] = 0;
>> + ta[1] = tb[1] = 100;
>> + hars_petruska_f54_1_random_seed(time(NULL));
>> + for (i = 2; i < points; i++) {
>> + ta[i] = hars_petruska_f54_1_random_unsafe_max(100);
>> + tb[i] = hars_petruska_f54_1_random_unsafe_max(100);
>> + }
>> + igt_permute_array(ta, points, igt_exchange_int);
>> + igt_permute_array(tb, points, igt_exchange_int);
>> +
>> + /* Exercise the thresholds with a GPU load to trigger park/unpark etc */
>> + for (i = 0; i < points; i++) {
>> + igt_info("Testing thresholds up %u%% and down %u%%...\n", ta[i], tb[i]);
>> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_up_threshold_pct", ta[i]), true);
>> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_down_threshold_pct", tb[i]), true);
>> +
>> + if (flags & TEST_IDLE) {
>> + gem_quiescent_gpu(i915);
>> + } else if (spin) {
>> + intel_ctx_destroy(i915, ctx);
>> + igt_spin_free(i915, spin);
>> + spin = NULL;
>> + if (flags & TEST_PARK) {
>> + gem_quiescent_gpu(i915);
>> + usleep(500000);
>> + }
>> + }
>> + spin = spin_sync_gt(i915, ahnd, gt, &ctx);
>> + usleep(1000000);
>> + if (flags & TEST_IDLE) {
>> + intel_ctx_destroy(i915, ctx);
>> + igt_spin_free(i915, spin);
>> + if (flags & TEST_PARK) {
>> + gem_quiescent_gpu(i915);
>> + usleep(500000);
>> + }
>> + spin = NULL;
>> + }
>> + }
>> +
>> + if (spin) {
>> + intel_ctx_destroy(i915, ctx);
>> + igt_spin_free(i915, spin);
>> + }
>> +
>> + gem_quiescent_gpu(i915);
>> +
>> + /* Restore defaults */
>> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_up_threshold_pct", def_up), true);
>> + igt_assert_eq(igt_sysfs_set_u32(sysfs, "rps_down_threshold_pct", def_down), true);
>> +
>> + free(ta);
>> + free(tb);
>> + close(sysfs);
>> + put_ahnd(ahnd);
>> +}
>> +
>> igt_main
>> {
>> igt_fixture {
>> @@ -1000,6 +1158,42 @@ igt_main
>> igt_disallow_hang(drm_fd, hang);
>> }
>>
>> + igt_subtest_with_dynamic("thresholds-idle") {
>> + int tmp, gt;
>> +
>> + i915_for_each_gt(drm_fd, tmp, gt) {
>> + igt_dynamic_f("gt%u", gt)
>> + test_thresholds(drm_fd, gt, TEST_IDLE);
>> + }
>> + }
>> +
>> + igt_subtest_with_dynamic("thresholds") {
>> + int tmp, gt;
>> +
>> + i915_for_each_gt(drm_fd, tmp, gt) {
>> + igt_dynamic_f("gt%u", gt)
>> + test_thresholds(drm_fd, gt, 0);
>> + }
>> + }
>> +
>> + igt_subtest_with_dynamic("thresholds-park") {
>> + int tmp, gt;
>> +
>> + i915_for_each_gt(drm_fd, tmp, gt) {
>> + igt_dynamic_f("gt%u", gt)
>> + test_thresholds(drm_fd, gt, TEST_PARK);
>> + }
>> + }
>> +
>> + igt_subtest_with_dynamic("thresholds-idle-park") {
>> + int tmp, gt;
>> +
>> + i915_for_each_gt(drm_fd, tmp, gt) {
>> + igt_dynamic_f("gt%u", gt)
>> + test_thresholds(drm_fd, gt, TEST_IDLE | TEST_PARK);
>> + }
>> + }
>> +
>> igt_fixture
>> drm_close_driver(drm_fd);
>> }
>> --
>> 2.39.2
>>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 1/2] lib/igt_dummyload: Extract sync spinner API
2023-07-17 8:34 ` Tvrtko Ursulin
@ 2023-07-17 14:55 ` Rodrigo Vivi
-1 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Vivi @ 2023-07-17 14:55 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: igt-dev, Intel-gfx
On Mon, Jul 17, 2023 at 09:34:36AM +0100, Tvrtko Ursulin wrote:
>
> On 14/07/2023 18:22, Rodrigo Vivi wrote:
> > On Tue, Jul 11, 2023 at 05:02:13PM +0100, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > >
> > > Sync spinner API is identical and compatible with regular spinners just
> > > that it tries to make sure spinner is actually running on the hardware
> > > before returning from the constructor.
> > >
> > > A few tests already use it, one more will, so lets promote it into
> > > common library.
> > >
> > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> > > ---
> > > lib/igt_dummyload.c | 105 ++++++++++++++++++++++++++++++++++++++++
> > > lib/igt_dummyload.h | 11 +++++
> > > tests/i915/drm_fdinfo.c | 81 ++++---------------------------
> > > tests/i915/gem_eio.c | 15 ++----
> > > tests/i915/perf_pmu.c | 84 +++++---------------------------
> > > 5 files changed, 140 insertions(+), 156 deletions(-)
> > >
> > > diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
> > > index 9f941cef73e6..d3cee91540b6 100644
> > > --- a/lib/igt_dummyload.c
> > > +++ b/lib/igt_dummyload.c
> >
> > why here?
> >
> > > @@ -33,6 +33,7 @@
> > > #include "drmtest.h"
> > > #include "i915/gem_create.h"
> > > #include "i915/gem_engine_topology.h"
> > > +#include "i915/gem.h"
> > > #include "i915/gem_mman.h"
> > > #include "i915/gem_submission.h"
> > > #include "igt_aux.h"
> > > @@ -715,6 +716,110 @@ void igt_unshare_spins(void)
> > > IGT_INIT_LIST_HEAD(&spin_list);
> > > }
> > > +/**
> > > + * __igt_sync_spin_poll:
> > > + * @i915: open i915 drm file descriptor
> >
> > anyway to make this not i915 centric?
> > or maybe move it to or start a lib that is i915 only?
> >
> > I know that we have many more lib things that are still i915 centric,
> > but at some point we need to start organizing it...
>
> Is igt_dummyload i915/xe agnostic already? I missed that. It would be a big
> ask for me to get on top of two uapis and do that.. ugh. :(
no, but I also asked above why igt_dummyload to start with?
>
> So on the "why here?" part. Assuming taking the i915 route.. where would you
> suggest to put it?
maybe something new inside ./lib/i915 ?
But, well, I actually don't have a better suggestion here, so let's
not block and any clean-up on i915 vs xe will need to come later anyway.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Regards,
>
> Tvrtko
>
> > > + * @ahnd: allocator handle
> > > + * @ctx: intel_ctx_t context
> > > + * @e: engine to execute on
> > > + *
> > > + * Starts a recursive batch on an engine.
> > > + *
> > > + * Returns a #igt_spin_t which can be used with both standard and igt_sync_spin
> > > + * API family. Callers should consult @gem_class_can_store_dword to whether
> > > + * the target platform+engine can reliably support the igt_sync_spin API.
> > > + */
> > > +igt_spin_t *
> > > +__igt_sync_spin_poll(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
> > > + const struct intel_execution_engine2 *e)
> > > +{
> > > + struct igt_spin_factory opts = {
> > > + .ahnd = ahnd,
> > > + .ctx = ctx,
> > > + .engine = e ? e->flags : 0,
> > > + };
> > > +
> > > + if (!e || gem_class_can_store_dword(i915, e->class))
> > > + opts.flags |= IGT_SPIN_POLL_RUN;
> > > +
> > > + return __igt_spin_factory(i915, &opts);
> > > +}
> > > +
> > > +/**
> > > + * __igt_sync_spin_wait:
> > > + * @i915: open i915 drm file descriptor
> > > + * @spin: previously create sync spinner
> > > + *
> > > + * Waits for a spinner to be running on the hardware.
> > > + *
> > > + * Callers should consult @gem_class_can_store_dword to whether the target
> > > + * platform+engine can reliably support the igt_sync_spin API.
> > > + */
> > > +unsigned long __igt_sync_spin_wait(int i915, igt_spin_t *spin)
> > > +{
> > > + struct timespec start = { };
> > > +
> > > + igt_nsec_elapsed(&start);
> > > +
> > > + if (igt_spin_has_poll(spin)) {
> > > + unsigned long timeout = 0;
> > > +
> > > + while (!igt_spin_has_started(spin)) {
> > > + unsigned long t = igt_nsec_elapsed(&start);
> > > +
> > > + igt_assert(gem_bo_busy(i915, spin->handle));
> > > + if ((t - timeout) > 250e6) {
> > > + timeout = t;
> > > + igt_warn("Spinner not running after %.2fms\n",
> > > + (double)t / 1e6);
> > > + igt_assert(t < 2e9);
> > > + }
> > > + }
> > > + } else {
> > > + igt_debug("__spin_wait - usleep mode\n");
> > > + usleep(500e3); /* Better than nothing! */
> > > + }
> > > +
> > > + igt_assert(gem_bo_busy(i915, spin->handle));
> > > + return igt_nsec_elapsed(&start);
> > > +}
> > > +
> > > +igt_spin_t *
> > > +__igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
> > > + const struct intel_execution_engine2 *e)
> > > +{
> > > + igt_spin_t *spin = __igt_sync_spin_poll(i915, ahnd, ctx, e);
> > > +
> > > + __igt_sync_spin_wait(i915, spin);
> > > +
> > > + return spin;
> > > +}
> > > +
> > > +/**
> > > + * igt_sync_spin:
> > > + * @i915: open i915 drm file descriptor
> > > + * @ahnd: allocator handle
> > > + * @ctx: intel_ctx_t context
> > > + * @e: engine to execute on
> > > + *
> > > + * Starts a recursive batch on an engine.
> > > + *
> > > + * Returns a #igt_spin_t and tries to guarantee it to be running at the time of
> > > + * the return. Otherwise it does a best effort only. Callers should check for
> > > + * @gem_class_can_store_dword if they want to be sure guarantee can be given.
> > > + *
> > > + * Both standard and igt_sync_spin API family can be used on the returned
> > > + * spinner object.
> > > + */
> > > +igt_spin_t *
> > > +igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
> > > + const struct intel_execution_engine2 *e)
> > > +{
> > > + igt_require_gem(i915);
> > > +
> > > + return __igt_sync_spin(i915, ahnd, ctx, e);
> > > +}
> > > +
> > > static uint32_t plug_vgem_handle(struct igt_cork *cork, int fd)
> > > {
> > > struct vgem_bo bo;
> > > diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
> > > index 6eb3f2e696bb..b771011af74f 100644
> > > --- a/lib/igt_dummyload.h
> > > +++ b/lib/igt_dummyload.h
> > > @@ -143,6 +143,17 @@ void igt_terminate_spins(void);
> > > void igt_unshare_spins(void);
> > > void igt_free_spins(int i915);
> > > +struct intel_execution_engine2;
> > > +
> > > +igt_spin_t *__igt_sync_spin_poll(int i915, uint64_t ahnd,
> > > + const intel_ctx_t *ctx,
> > > + const struct intel_execution_engine2 *e);
> > > +unsigned long __igt_sync_spin_wait(int i915, igt_spin_t *spin);
> > > +igt_spin_t *__igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
> > > + const struct intel_execution_engine2 *e);
> > > +igt_spin_t *igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
> > > + const struct intel_execution_engine2 *e);
> > > +
> > > enum igt_cork_type {
> > > CORK_SYNC_FD = 1,
> > > CORK_VGEM_HANDLE
> > > diff --git a/tests/i915/drm_fdinfo.c b/tests/i915/drm_fdinfo.c
> > > index c0e0ba1905f1..5cafa0e469e2 100644
> > > --- a/tests/i915/drm_fdinfo.c
> > > +++ b/tests/i915/drm_fdinfo.c
> > > @@ -138,68 +138,6 @@ static unsigned int measured_usleep(unsigned int usec)
> > > #define FLAG_HANG (8)
> > > #define TEST_ISOLATION (16)
> > > -static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > - const struct intel_execution_engine2 *e)
> > > -{
> > > - struct igt_spin_factory opts = {
> > > - .ahnd = ahnd,
> > > - .ctx = ctx,
> > > - .engine = e ? e->flags : 0,
> > > - };
> > > -
> > > - if (!e || gem_class_can_store_dword(fd, e->class))
> > > - opts.flags |= IGT_SPIN_POLL_RUN;
> > > -
> > > - return __igt_spin_factory(fd, &opts);
> > > -}
> > > -
> > > -static unsigned long __spin_wait(int fd, igt_spin_t *spin)
> > > -{
> > > - struct timespec start = { };
> > > -
> > > - igt_nsec_elapsed(&start);
> > > -
> > > - if (igt_spin_has_poll(spin)) {
> > > - unsigned long timeout = 0;
> > > -
> > > - while (!igt_spin_has_started(spin)) {
> > > - unsigned long t = igt_nsec_elapsed(&start);
> > > -
> > > - igt_assert(gem_bo_busy(fd, spin->handle));
> > > - if ((t - timeout) > 250e6) {
> > > - timeout = t;
> > > - igt_warn("Spinner not running after %.2fms\n",
> > > - (double)t / 1e6);
> > > - igt_assert(t < 2e9);
> > > - }
> > > - }
> > > - } else {
> > > - igt_debug("__spin_wait - usleep mode\n");
> > > - usleep(500e3); /* Better than nothing! */
> > > - }
> > > -
> > > - igt_assert(gem_bo_busy(fd, spin->handle));
> > > - return igt_nsec_elapsed(&start);
> > > -}
> > > -
> > > -static igt_spin_t *__spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > - const struct intel_execution_engine2 *e)
> > > -{
> > > - igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, e);
> > > -
> > > - __spin_wait(fd, spin);
> > > -
> > > - return spin;
> > > -}
> > > -
> > > -static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > - const struct intel_execution_engine2 *e)
> > > -{
> > > - igt_require_gem(fd);
> > > -
> > > - return __spin_sync(fd, ahnd, ctx, e);
> > > -}
> > > -
> > > static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
> > > {
> > > if (!spin)
> > > @@ -264,7 +202,7 @@ single(int gem_fd, const intel_ctx_t *ctx,
> > > ahnd = get_reloc_ahnd(spin_fd, ctx->id);
> > > if (flags & TEST_BUSY)
> > > - spin = spin_sync(spin_fd, ahnd, ctx, e);
> > > + spin = igt_sync_spin(spin_fd, ahnd, ctx, e);
> > > else
> > > spin = NULL;
> > > @@ -349,7 +287,7 @@ busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> > > memset(tval, 0, sizeof(tval));
> > > - spin = spin_sync(gem_fd, ahnd, ctx, e);
> > > + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
> > > read_busy_all(gem_fd, tval[0]);
> > > slept = measured_usleep(batch_duration_ns / 1000);
> > > @@ -418,14 +356,14 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> > > __submit_spin(gem_fd, spin, e_, 64);
> > > busy_class[e_->class]++;
> > > } else {
> > > - spin = __spin_poll(gem_fd, ahnd, ctx, e_);
> > > + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e_);
> > > busy_class[e_->class]++;
> > > }
> > > }
> > > igt_require(spin); /* at least one busy engine */
> > > /* Small delay to allow engines to start. */
> > > - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> > > + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
> > > read_busy_all(gem_fd, tval[0]);
> > > slept = measured_usleep(batch_duration_ns / 1000);
> > > @@ -475,12 +413,12 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> > > if (spin)
> > > __submit_spin(gem_fd, spin, e, 64);
> > > else
> > > - spin = __spin_poll(gem_fd, ahnd, ctx, e);
> > > + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e);
> > > busy_class[e->class]++;
> > > }
> > > /* Small delay to allow engines to start. */
> > > - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> > > + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
> > > read_busy_all(gem_fd, tval[0]);
> > > slept = measured_usleep(batch_duration_ns / 1000);
> > > @@ -624,7 +562,7 @@ virtual(int i915, const intel_ctx_cfg_t *base_cfg, unsigned int flags)
> > > ahnd = get_reloc_ahnd(i915, ctx->id);
> > > if (flags & TEST_BUSY)
> > > - spin = spin_sync(i915, ahnd, ctx, NULL);
> > > + spin = igt_sync_spin(i915, ahnd, ctx, NULL);
> > > else
> > > spin = NULL;
> > > @@ -732,11 +670,12 @@ virtual_all(int i915, const intel_ctx_cfg_t *base_cfg, unsigned int flags)
> > > if (spin)
> > > __virt_submit_spin(i915, spin, ctx[i], 64);
> > > else
> > > - spin = __spin_poll(i915, ahnd, ctx[i], NULL);
> > > + spin = __igt_sync_spin_poll(i915, ahnd, ctx[i],
> > > + NULL);
> > > }
> > > /* Small delay to allow engines to start. */
> > > - usleep(__spin_wait(i915, spin) * count / 1e3);
> > > + usleep(__igt_sync_spin_wait(i915, spin) * count / 1e3);
> > > val = read_busy(i915, class);
> > > slept = measured_usleep(batch_duration_ns / 1000);
> > > diff --git a/tests/i915/gem_eio.c b/tests/i915/gem_eio.c
> > > index d889d67dcebd..6d4b8f7df909 100644
> > > --- a/tests/i915/gem_eio.c
> > > +++ b/tests/i915/gem_eio.c
> > > @@ -47,6 +47,7 @@
> > > #include "i915/gem_ring.h"
> > > #include "igt.h"
> > > #include "igt_device.h"
> > > +#include "igt_dummyload.h"
> > > #include "igt_fb.h"
> > > #include "igt_kms.h"
> > > #include "igt_stats.h"
> > > @@ -429,22 +430,12 @@ static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > return __igt_spin_factory(fd, &opts);
> > > }
> > > -static void __spin_wait(int fd, igt_spin_t *spin)
> > > -{
> > > - if (igt_spin_has_poll(spin)) {
> > > - igt_spin_busywait_until_started(spin);
> > > - } else {
> > > - igt_debug("__spin_wait - usleep mode\n");
> > > - usleep(500e3); /* Better than nothing! */
> > > - }
> > > -}
> > > -
> > > static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > unsigned long flags)
> > > {
> > > igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, flags);
> > > - __spin_wait(fd, spin);
> > > + __igt_sync_spin_wait(fd, spin);
> > > return spin;
> > > }
> > > @@ -963,7 +954,7 @@ static void test_inflight_external(int fd)
> > > fence = execbuf.rsvd2 >> 32;
> > > igt_assert(fence != -1);
> > > - __spin_wait(fd, hang);
> > > + __igt_sync_spin_wait(fd, hang);
> > > manual_hang(fd);
> > > gem_sync(fd, hang->handle); /* wedged, with an unready batch */
> > > diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
> > > index 0806a8e545b5..a888027ad9af 100644
> > > --- a/tests/i915/perf_pmu.c
> > > +++ b/tests/i915/perf_pmu.c
> > > @@ -377,68 +377,6 @@ static unsigned int measured_usleep(unsigned int usec)
> > > #define TEST_OTHER (128)
> > > #define TEST_ALL (256)
> > > -static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > - const struct intel_execution_engine2 *e)
> > > -{
> > > - struct igt_spin_factory opts = {
> > > - .ahnd = ahnd,
> > > - .ctx = ctx,
> > > - .engine = e->flags,
> > > - };
> > > -
> > > - if (gem_class_can_store_dword(fd, e->class))
> > > - opts.flags |= IGT_SPIN_POLL_RUN;
> > > -
> > > - return __igt_spin_factory(fd, &opts);
> > > -}
> > > -
> > > -static unsigned long __spin_wait(int fd, igt_spin_t *spin)
> > > -{
> > > - struct timespec start = { };
> > > -
> > > - igt_nsec_elapsed(&start);
> > > -
> > > - if (igt_spin_has_poll(spin)) {
> > > - unsigned long timeout = 0;
> > > -
> > > - while (!igt_spin_has_started(spin)) {
> > > - unsigned long t = igt_nsec_elapsed(&start);
> > > -
> > > - igt_assert(gem_bo_busy(fd, spin->handle));
> > > - if ((t - timeout) > 250e6) {
> > > - timeout = t;
> > > - igt_warn("Spinner not running after %.2fms\n",
> > > - (double)t / 1e6);
> > > - igt_assert(t < 2e9);
> > > - }
> > > - }
> > > - } else {
> > > - igt_debug("__spin_wait - usleep mode\n");
> > > - usleep(500e3); /* Better than nothing! */
> > > - }
> > > -
> > > - igt_assert(gem_bo_busy(fd, spin->handle));
> > > - return igt_nsec_elapsed(&start);
> > > -}
> > > -
> > > -static igt_spin_t *__spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > - const struct intel_execution_engine2 *e)
> > > -{
> > > - igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, e);
> > > -
> > > - __spin_wait(fd, spin);
> > > -
> > > - return spin;
> > > -}
> > > -
> > > -static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > - const struct intel_execution_engine2 *e)
> > > -{
> > > - igt_require_gem(fd);
> > > -
> > > - return __spin_sync(fd, ahnd, ctx, e);
> > > -}
> > > -
> > > static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
> > > {
> > > if (!spin)
> > > @@ -484,7 +422,7 @@ single(int gem_fd, const intel_ctx_t *ctx,
> > > fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
> > > if (flags & TEST_BUSY)
> > > - spin = spin_sync(gem_fd, ahnd, ctx, e);
> > > + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
> > > else
> > > spin = NULL;
> > > @@ -536,7 +474,7 @@ busy_start(int gem_fd, const intel_ctx_t *ctx,
> > > */
> > > sleep(2);
> > > - spin = __spin_sync(gem_fd, ahnd, ctx, e);
> > > + spin = __igt_sync_spin(gem_fd, ahnd, ctx, e);
> > > fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
> > > @@ -583,7 +521,7 @@ busy_double_start(int gem_fd, const intel_ctx_t *ctx,
> > > * re-submission in execlists mode. Make sure busyness is correctly
> > > * reported with the engine busy, and after the engine went idle.
> > > */
> > > - spin[0] = __spin_sync(gem_fd, ahnd, ctx, e);
> > > + spin[0] = __igt_sync_spin(gem_fd, ahnd, ctx, e);
> > > usleep(500e3);
> > > spin[1] = __igt_spin_new(gem_fd,
> > > .ahnd = ahndN,
> > > @@ -675,7 +613,7 @@ busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> > > igt_assert_eq(i, num_engines);
> > > - spin = spin_sync(gem_fd, ahnd, ctx, e);
> > > + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
> > > pmu_read_multi(fd[0], num_engines, tval[0]);
> > > slept = measured_usleep(batch_duration_ns / 1000);
> > > if (flags & TEST_TRAILING_IDLE)
> > > @@ -737,7 +675,7 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> > > else if (spin)
> > > __submit_spin(gem_fd, spin, e_, 64);
> > > else
> > > - spin = __spin_poll(gem_fd, ahnd, ctx, e_);
> > > + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e_);
> > > val[i++] = I915_PMU_ENGINE_BUSY(e_->class, e_->instance);
> > > }
> > > @@ -749,7 +687,7 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> > > fd[i] = open_group(gem_fd, val[i], fd[0]);
> > > /* Small delay to allow engines to start. */
> > > - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> > > + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
> > > pmu_read_multi(fd[0], num_engines, tval[0]);
> > > slept = measured_usleep(batch_duration_ns / 1000);
> > > @@ -796,7 +734,7 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> > > if (spin)
> > > __submit_spin(gem_fd, spin, e, 64);
> > > else
> > > - spin = __spin_poll(gem_fd, ahnd, ctx, e);
> > > + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e);
> > > val[i++] = I915_PMU_ENGINE_BUSY(e->class, e->instance);
> > > }
> > > @@ -807,7 +745,7 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> > > fd[i] = open_group(gem_fd, val[i], fd[0]);
> > > /* Small delay to allow engines to start. */
> > > - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> > > + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
> > > pmu_read_multi(fd[0], num_engines, tval[0]);
> > > slept = measured_usleep(batch_duration_ns / 1000);
> > > @@ -848,7 +786,7 @@ no_sema(int gem_fd, const intel_ctx_t *ctx,
> > > fd[0]);
> > > if (flags & TEST_BUSY)
> > > - spin = spin_sync(gem_fd, ahnd, ctx, e);
> > > + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
> > > else
> > > spin = NULL;
> > > @@ -1406,7 +1344,7 @@ multi_client(int gem_fd, const intel_ctx_t *ctx,
> > > */
> > > fd[1] = open_pmu(gem_fd, config);
> > > - spin = spin_sync(gem_fd, ahnd, ctx, e);
> > > + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
> > > val[0] = val[1] = __pmu_read_single(fd[0], &ts[0]);
> > > slept[1] = measured_usleep(batch_duration_ns / 1000);
> > > @@ -1776,7 +1714,7 @@ static igt_spin_t *spin_sync_gt(int i915, uint64_t ahnd, unsigned int gt,
> > > igt_debug("Using engine %u:%u\n", e.class, e.instance);
> > > - return spin_sync(i915, ahnd, *ctx, &e);
> > > + return igt_sync_spin(i915, ahnd, *ctx, &e);
> > > }
> > > static void
> > > --
> > > 2.39.2
> > >
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/2] lib/igt_dummyload: Extract sync spinner API
@ 2023-07-17 14:55 ` Rodrigo Vivi
0 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Vivi @ 2023-07-17 14:55 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: igt-dev, Intel-gfx, Tvrtko Ursulin
On Mon, Jul 17, 2023 at 09:34:36AM +0100, Tvrtko Ursulin wrote:
>
> On 14/07/2023 18:22, Rodrigo Vivi wrote:
> > On Tue, Jul 11, 2023 at 05:02:13PM +0100, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > >
> > > Sync spinner API is identical and compatible with regular spinners just
> > > that it tries to make sure spinner is actually running on the hardware
> > > before returning from the constructor.
> > >
> > > A few tests already use it, one more will, so lets promote it into
> > > common library.
> > >
> > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> > > ---
> > > lib/igt_dummyload.c | 105 ++++++++++++++++++++++++++++++++++++++++
> > > lib/igt_dummyload.h | 11 +++++
> > > tests/i915/drm_fdinfo.c | 81 ++++---------------------------
> > > tests/i915/gem_eio.c | 15 ++----
> > > tests/i915/perf_pmu.c | 84 +++++---------------------------
> > > 5 files changed, 140 insertions(+), 156 deletions(-)
> > >
> > > diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
> > > index 9f941cef73e6..d3cee91540b6 100644
> > > --- a/lib/igt_dummyload.c
> > > +++ b/lib/igt_dummyload.c
> >
> > why here?
> >
> > > @@ -33,6 +33,7 @@
> > > #include "drmtest.h"
> > > #include "i915/gem_create.h"
> > > #include "i915/gem_engine_topology.h"
> > > +#include "i915/gem.h"
> > > #include "i915/gem_mman.h"
> > > #include "i915/gem_submission.h"
> > > #include "igt_aux.h"
> > > @@ -715,6 +716,110 @@ void igt_unshare_spins(void)
> > > IGT_INIT_LIST_HEAD(&spin_list);
> > > }
> > > +/**
> > > + * __igt_sync_spin_poll:
> > > + * @i915: open i915 drm file descriptor
> >
> > anyway to make this not i915 centric?
> > or maybe move it to or start a lib that is i915 only?
> >
> > I know that we have many more lib things that are still i915 centric,
> > but at some point we need to start organizing it...
>
> Is igt_dummyload i915/xe agnostic already? I missed that. It would be a big
> ask for me to get on top of two uapis and do that.. ugh. :(
no, but I also asked above why igt_dummyload to start with?
>
> So on the "why here?" part. Assuming taking the i915 route.. where would you
> suggest to put it?
maybe something new inside ./lib/i915 ?
But, well, I actually don't have a better suggestion here, so let's
not block and any clean-up on i915 vs xe will need to come later anyway.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Regards,
>
> Tvrtko
>
> > > + * @ahnd: allocator handle
> > > + * @ctx: intel_ctx_t context
> > > + * @e: engine to execute on
> > > + *
> > > + * Starts a recursive batch on an engine.
> > > + *
> > > + * Returns a #igt_spin_t which can be used with both standard and igt_sync_spin
> > > + * API family. Callers should consult @gem_class_can_store_dword to whether
> > > + * the target platform+engine can reliably support the igt_sync_spin API.
> > > + */
> > > +igt_spin_t *
> > > +__igt_sync_spin_poll(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
> > > + const struct intel_execution_engine2 *e)
> > > +{
> > > + struct igt_spin_factory opts = {
> > > + .ahnd = ahnd,
> > > + .ctx = ctx,
> > > + .engine = e ? e->flags : 0,
> > > + };
> > > +
> > > + if (!e || gem_class_can_store_dword(i915, e->class))
> > > + opts.flags |= IGT_SPIN_POLL_RUN;
> > > +
> > > + return __igt_spin_factory(i915, &opts);
> > > +}
> > > +
> > > +/**
> > > + * __igt_sync_spin_wait:
> > > + * @i915: open i915 drm file descriptor
> > > + * @spin: previously create sync spinner
> > > + *
> > > + * Waits for a spinner to be running on the hardware.
> > > + *
> > > + * Callers should consult @gem_class_can_store_dword to whether the target
> > > + * platform+engine can reliably support the igt_sync_spin API.
> > > + */
> > > +unsigned long __igt_sync_spin_wait(int i915, igt_spin_t *spin)
> > > +{
> > > + struct timespec start = { };
> > > +
> > > + igt_nsec_elapsed(&start);
> > > +
> > > + if (igt_spin_has_poll(spin)) {
> > > + unsigned long timeout = 0;
> > > +
> > > + while (!igt_spin_has_started(spin)) {
> > > + unsigned long t = igt_nsec_elapsed(&start);
> > > +
> > > + igt_assert(gem_bo_busy(i915, spin->handle));
> > > + if ((t - timeout) > 250e6) {
> > > + timeout = t;
> > > + igt_warn("Spinner not running after %.2fms\n",
> > > + (double)t / 1e6);
> > > + igt_assert(t < 2e9);
> > > + }
> > > + }
> > > + } else {
> > > + igt_debug("__spin_wait - usleep mode\n");
> > > + usleep(500e3); /* Better than nothing! */
> > > + }
> > > +
> > > + igt_assert(gem_bo_busy(i915, spin->handle));
> > > + return igt_nsec_elapsed(&start);
> > > +}
> > > +
> > > +igt_spin_t *
> > > +__igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
> > > + const struct intel_execution_engine2 *e)
> > > +{
> > > + igt_spin_t *spin = __igt_sync_spin_poll(i915, ahnd, ctx, e);
> > > +
> > > + __igt_sync_spin_wait(i915, spin);
> > > +
> > > + return spin;
> > > +}
> > > +
> > > +/**
> > > + * igt_sync_spin:
> > > + * @i915: open i915 drm file descriptor
> > > + * @ahnd: allocator handle
> > > + * @ctx: intel_ctx_t context
> > > + * @e: engine to execute on
> > > + *
> > > + * Starts a recursive batch on an engine.
> > > + *
> > > + * Returns a #igt_spin_t and tries to guarantee it to be running at the time of
> > > + * the return. Otherwise it does a best effort only. Callers should check for
> > > + * @gem_class_can_store_dword if they want to be sure guarantee can be given.
> > > + *
> > > + * Both standard and igt_sync_spin API family can be used on the returned
> > > + * spinner object.
> > > + */
> > > +igt_spin_t *
> > > +igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
> > > + const struct intel_execution_engine2 *e)
> > > +{
> > > + igt_require_gem(i915);
> > > +
> > > + return __igt_sync_spin(i915, ahnd, ctx, e);
> > > +}
> > > +
> > > static uint32_t plug_vgem_handle(struct igt_cork *cork, int fd)
> > > {
> > > struct vgem_bo bo;
> > > diff --git a/lib/igt_dummyload.h b/lib/igt_dummyload.h
> > > index 6eb3f2e696bb..b771011af74f 100644
> > > --- a/lib/igt_dummyload.h
> > > +++ b/lib/igt_dummyload.h
> > > @@ -143,6 +143,17 @@ void igt_terminate_spins(void);
> > > void igt_unshare_spins(void);
> > > void igt_free_spins(int i915);
> > > +struct intel_execution_engine2;
> > > +
> > > +igt_spin_t *__igt_sync_spin_poll(int i915, uint64_t ahnd,
> > > + const intel_ctx_t *ctx,
> > > + const struct intel_execution_engine2 *e);
> > > +unsigned long __igt_sync_spin_wait(int i915, igt_spin_t *spin);
> > > +igt_spin_t *__igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
> > > + const struct intel_execution_engine2 *e);
> > > +igt_spin_t *igt_sync_spin(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
> > > + const struct intel_execution_engine2 *e);
> > > +
> > > enum igt_cork_type {
> > > CORK_SYNC_FD = 1,
> > > CORK_VGEM_HANDLE
> > > diff --git a/tests/i915/drm_fdinfo.c b/tests/i915/drm_fdinfo.c
> > > index c0e0ba1905f1..5cafa0e469e2 100644
> > > --- a/tests/i915/drm_fdinfo.c
> > > +++ b/tests/i915/drm_fdinfo.c
> > > @@ -138,68 +138,6 @@ static unsigned int measured_usleep(unsigned int usec)
> > > #define FLAG_HANG (8)
> > > #define TEST_ISOLATION (16)
> > > -static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > - const struct intel_execution_engine2 *e)
> > > -{
> > > - struct igt_spin_factory opts = {
> > > - .ahnd = ahnd,
> > > - .ctx = ctx,
> > > - .engine = e ? e->flags : 0,
> > > - };
> > > -
> > > - if (!e || gem_class_can_store_dword(fd, e->class))
> > > - opts.flags |= IGT_SPIN_POLL_RUN;
> > > -
> > > - return __igt_spin_factory(fd, &opts);
> > > -}
> > > -
> > > -static unsigned long __spin_wait(int fd, igt_spin_t *spin)
> > > -{
> > > - struct timespec start = { };
> > > -
> > > - igt_nsec_elapsed(&start);
> > > -
> > > - if (igt_spin_has_poll(spin)) {
> > > - unsigned long timeout = 0;
> > > -
> > > - while (!igt_spin_has_started(spin)) {
> > > - unsigned long t = igt_nsec_elapsed(&start);
> > > -
> > > - igt_assert(gem_bo_busy(fd, spin->handle));
> > > - if ((t - timeout) > 250e6) {
> > > - timeout = t;
> > > - igt_warn("Spinner not running after %.2fms\n",
> > > - (double)t / 1e6);
> > > - igt_assert(t < 2e9);
> > > - }
> > > - }
> > > - } else {
> > > - igt_debug("__spin_wait - usleep mode\n");
> > > - usleep(500e3); /* Better than nothing! */
> > > - }
> > > -
> > > - igt_assert(gem_bo_busy(fd, spin->handle));
> > > - return igt_nsec_elapsed(&start);
> > > -}
> > > -
> > > -static igt_spin_t *__spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > - const struct intel_execution_engine2 *e)
> > > -{
> > > - igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, e);
> > > -
> > > - __spin_wait(fd, spin);
> > > -
> > > - return spin;
> > > -}
> > > -
> > > -static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > - const struct intel_execution_engine2 *e)
> > > -{
> > > - igt_require_gem(fd);
> > > -
> > > - return __spin_sync(fd, ahnd, ctx, e);
> > > -}
> > > -
> > > static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
> > > {
> > > if (!spin)
> > > @@ -264,7 +202,7 @@ single(int gem_fd, const intel_ctx_t *ctx,
> > > ahnd = get_reloc_ahnd(spin_fd, ctx->id);
> > > if (flags & TEST_BUSY)
> > > - spin = spin_sync(spin_fd, ahnd, ctx, e);
> > > + spin = igt_sync_spin(spin_fd, ahnd, ctx, e);
> > > else
> > > spin = NULL;
> > > @@ -349,7 +287,7 @@ busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> > > memset(tval, 0, sizeof(tval));
> > > - spin = spin_sync(gem_fd, ahnd, ctx, e);
> > > + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
> > > read_busy_all(gem_fd, tval[0]);
> > > slept = measured_usleep(batch_duration_ns / 1000);
> > > @@ -418,14 +356,14 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> > > __submit_spin(gem_fd, spin, e_, 64);
> > > busy_class[e_->class]++;
> > > } else {
> > > - spin = __spin_poll(gem_fd, ahnd, ctx, e_);
> > > + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e_);
> > > busy_class[e_->class]++;
> > > }
> > > }
> > > igt_require(spin); /* at least one busy engine */
> > > /* Small delay to allow engines to start. */
> > > - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> > > + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
> > > read_busy_all(gem_fd, tval[0]);
> > > slept = measured_usleep(batch_duration_ns / 1000);
> > > @@ -475,12 +413,12 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> > > if (spin)
> > > __submit_spin(gem_fd, spin, e, 64);
> > > else
> > > - spin = __spin_poll(gem_fd, ahnd, ctx, e);
> > > + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e);
> > > busy_class[e->class]++;
> > > }
> > > /* Small delay to allow engines to start. */
> > > - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> > > + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
> > > read_busy_all(gem_fd, tval[0]);
> > > slept = measured_usleep(batch_duration_ns / 1000);
> > > @@ -624,7 +562,7 @@ virtual(int i915, const intel_ctx_cfg_t *base_cfg, unsigned int flags)
> > > ahnd = get_reloc_ahnd(i915, ctx->id);
> > > if (flags & TEST_BUSY)
> > > - spin = spin_sync(i915, ahnd, ctx, NULL);
> > > + spin = igt_sync_spin(i915, ahnd, ctx, NULL);
> > > else
> > > spin = NULL;
> > > @@ -732,11 +670,12 @@ virtual_all(int i915, const intel_ctx_cfg_t *base_cfg, unsigned int flags)
> > > if (spin)
> > > __virt_submit_spin(i915, spin, ctx[i], 64);
> > > else
> > > - spin = __spin_poll(i915, ahnd, ctx[i], NULL);
> > > + spin = __igt_sync_spin_poll(i915, ahnd, ctx[i],
> > > + NULL);
> > > }
> > > /* Small delay to allow engines to start. */
> > > - usleep(__spin_wait(i915, spin) * count / 1e3);
> > > + usleep(__igt_sync_spin_wait(i915, spin) * count / 1e3);
> > > val = read_busy(i915, class);
> > > slept = measured_usleep(batch_duration_ns / 1000);
> > > diff --git a/tests/i915/gem_eio.c b/tests/i915/gem_eio.c
> > > index d889d67dcebd..6d4b8f7df909 100644
> > > --- a/tests/i915/gem_eio.c
> > > +++ b/tests/i915/gem_eio.c
> > > @@ -47,6 +47,7 @@
> > > #include "i915/gem_ring.h"
> > > #include "igt.h"
> > > #include "igt_device.h"
> > > +#include "igt_dummyload.h"
> > > #include "igt_fb.h"
> > > #include "igt_kms.h"
> > > #include "igt_stats.h"
> > > @@ -429,22 +430,12 @@ static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > return __igt_spin_factory(fd, &opts);
> > > }
> > > -static void __spin_wait(int fd, igt_spin_t *spin)
> > > -{
> > > - if (igt_spin_has_poll(spin)) {
> > > - igt_spin_busywait_until_started(spin);
> > > - } else {
> > > - igt_debug("__spin_wait - usleep mode\n");
> > > - usleep(500e3); /* Better than nothing! */
> > > - }
> > > -}
> > > -
> > > static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > unsigned long flags)
> > > {
> > > igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, flags);
> > > - __spin_wait(fd, spin);
> > > + __igt_sync_spin_wait(fd, spin);
> > > return spin;
> > > }
> > > @@ -963,7 +954,7 @@ static void test_inflight_external(int fd)
> > > fence = execbuf.rsvd2 >> 32;
> > > igt_assert(fence != -1);
> > > - __spin_wait(fd, hang);
> > > + __igt_sync_spin_wait(fd, hang);
> > > manual_hang(fd);
> > > gem_sync(fd, hang->handle); /* wedged, with an unready batch */
> > > diff --git a/tests/i915/perf_pmu.c b/tests/i915/perf_pmu.c
> > > index 0806a8e545b5..a888027ad9af 100644
> > > --- a/tests/i915/perf_pmu.c
> > > +++ b/tests/i915/perf_pmu.c
> > > @@ -377,68 +377,6 @@ static unsigned int measured_usleep(unsigned int usec)
> > > #define TEST_OTHER (128)
> > > #define TEST_ALL (256)
> > > -static igt_spin_t *__spin_poll(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > - const struct intel_execution_engine2 *e)
> > > -{
> > > - struct igt_spin_factory opts = {
> > > - .ahnd = ahnd,
> > > - .ctx = ctx,
> > > - .engine = e->flags,
> > > - };
> > > -
> > > - if (gem_class_can_store_dword(fd, e->class))
> > > - opts.flags |= IGT_SPIN_POLL_RUN;
> > > -
> > > - return __igt_spin_factory(fd, &opts);
> > > -}
> > > -
> > > -static unsigned long __spin_wait(int fd, igt_spin_t *spin)
> > > -{
> > > - struct timespec start = { };
> > > -
> > > - igt_nsec_elapsed(&start);
> > > -
> > > - if (igt_spin_has_poll(spin)) {
> > > - unsigned long timeout = 0;
> > > -
> > > - while (!igt_spin_has_started(spin)) {
> > > - unsigned long t = igt_nsec_elapsed(&start);
> > > -
> > > - igt_assert(gem_bo_busy(fd, spin->handle));
> > > - if ((t - timeout) > 250e6) {
> > > - timeout = t;
> > > - igt_warn("Spinner not running after %.2fms\n",
> > > - (double)t / 1e6);
> > > - igt_assert(t < 2e9);
> > > - }
> > > - }
> > > - } else {
> > > - igt_debug("__spin_wait - usleep mode\n");
> > > - usleep(500e3); /* Better than nothing! */
> > > - }
> > > -
> > > - igt_assert(gem_bo_busy(fd, spin->handle));
> > > - return igt_nsec_elapsed(&start);
> > > -}
> > > -
> > > -static igt_spin_t *__spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > - const struct intel_execution_engine2 *e)
> > > -{
> > > - igt_spin_t *spin = __spin_poll(fd, ahnd, ctx, e);
> > > -
> > > - __spin_wait(fd, spin);
> > > -
> > > - return spin;
> > > -}
> > > -
> > > -static igt_spin_t *spin_sync(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > - const struct intel_execution_engine2 *e)
> > > -{
> > > - igt_require_gem(fd);
> > > -
> > > - return __spin_sync(fd, ahnd, ctx, e);
> > > -}
> > > -
> > > static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
> > > {
> > > if (!spin)
> > > @@ -484,7 +422,7 @@ single(int gem_fd, const intel_ctx_t *ctx,
> > > fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
> > > if (flags & TEST_BUSY)
> > > - spin = spin_sync(gem_fd, ahnd, ctx, e);
> > > + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
> > > else
> > > spin = NULL;
> > > @@ -536,7 +474,7 @@ busy_start(int gem_fd, const intel_ctx_t *ctx,
> > > */
> > > sleep(2);
> > > - spin = __spin_sync(gem_fd, ahnd, ctx, e);
> > > + spin = __igt_sync_spin(gem_fd, ahnd, ctx, e);
> > > fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
> > > @@ -583,7 +521,7 @@ busy_double_start(int gem_fd, const intel_ctx_t *ctx,
> > > * re-submission in execlists mode. Make sure busyness is correctly
> > > * reported with the engine busy, and after the engine went idle.
> > > */
> > > - spin[0] = __spin_sync(gem_fd, ahnd, ctx, e);
> > > + spin[0] = __igt_sync_spin(gem_fd, ahnd, ctx, e);
> > > usleep(500e3);
> > > spin[1] = __igt_spin_new(gem_fd,
> > > .ahnd = ahndN,
> > > @@ -675,7 +613,7 @@ busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> > > igt_assert_eq(i, num_engines);
> > > - spin = spin_sync(gem_fd, ahnd, ctx, e);
> > > + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
> > > pmu_read_multi(fd[0], num_engines, tval[0]);
> > > slept = measured_usleep(batch_duration_ns / 1000);
> > > if (flags & TEST_TRAILING_IDLE)
> > > @@ -737,7 +675,7 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> > > else if (spin)
> > > __submit_spin(gem_fd, spin, e_, 64);
> > > else
> > > - spin = __spin_poll(gem_fd, ahnd, ctx, e_);
> > > + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e_);
> > > val[i++] = I915_PMU_ENGINE_BUSY(e_->class, e_->instance);
> > > }
> > > @@ -749,7 +687,7 @@ most_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> > > fd[i] = open_group(gem_fd, val[i], fd[0]);
> > > /* Small delay to allow engines to start. */
> > > - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> > > + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
> > > pmu_read_multi(fd[0], num_engines, tval[0]);
> > > slept = measured_usleep(batch_duration_ns / 1000);
> > > @@ -796,7 +734,7 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> > > if (spin)
> > > __submit_spin(gem_fd, spin, e, 64);
> > > else
> > > - spin = __spin_poll(gem_fd, ahnd, ctx, e);
> > > + spin = __igt_sync_spin_poll(gem_fd, ahnd, ctx, e);
> > > val[i++] = I915_PMU_ENGINE_BUSY(e->class, e->instance);
> > > }
> > > @@ -807,7 +745,7 @@ all_busy_check_all(int gem_fd, const intel_ctx_t *ctx,
> > > fd[i] = open_group(gem_fd, val[i], fd[0]);
> > > /* Small delay to allow engines to start. */
> > > - usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> > > + usleep(__igt_sync_spin_wait(gem_fd, spin) * num_engines / 1e3);
> > > pmu_read_multi(fd[0], num_engines, tval[0]);
> > > slept = measured_usleep(batch_duration_ns / 1000);
> > > @@ -848,7 +786,7 @@ no_sema(int gem_fd, const intel_ctx_t *ctx,
> > > fd[0]);
> > > if (flags & TEST_BUSY)
> > > - spin = spin_sync(gem_fd, ahnd, ctx, e);
> > > + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
> > > else
> > > spin = NULL;
> > > @@ -1406,7 +1344,7 @@ multi_client(int gem_fd, const intel_ctx_t *ctx,
> > > */
> > > fd[1] = open_pmu(gem_fd, config);
> > > - spin = spin_sync(gem_fd, ahnd, ctx, e);
> > > + spin = igt_sync_spin(gem_fd, ahnd, ctx, e);
> > > val[0] = val[1] = __pmu_read_single(fd[0], &ts[0]);
> > > slept[1] = measured_usleep(batch_duration_ns / 1000);
> > > @@ -1776,7 +1714,7 @@ static igt_spin_t *spin_sync_gt(int i915, uint64_t ahnd, unsigned int gt,
> > > igt_debug("Using engine %u:%u\n", e.class, e.instance);
> > > - return spin_sync(i915, ahnd, *ctx, &e);
> > > + return igt_sync_spin(i915, ahnd, *ctx, &e);
> > > }
> > > static void
> > > --
> > > 2.39.2
> > >
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2023-07-17 14:55 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-07-11 16:02 [Intel-gfx] [PATCH i-g-t 1/2] lib/igt_dummyload: Extract sync spinner API Tvrtko Ursulin
2023-07-11 16:02 ` [igt-dev] " Tvrtko Ursulin
2023-07-11 16:02 ` [Intel-gfx] [PATCH i-g-t 2/2] tests/i915_pm_rps: Exercise sysfs thresholds Tvrtko Ursulin
2023-07-11 16:02 ` [igt-dev] " Tvrtko Ursulin
2023-07-14 17:26 ` [Intel-gfx] " Rodrigo Vivi
2023-07-14 17:26 ` Rodrigo Vivi
2023-07-17 8:37 ` [Intel-gfx] " Tvrtko Ursulin
2023-07-17 8:37 ` Tvrtko Ursulin
2023-07-11 17:13 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/2] lib/igt_dummyload: Extract sync spinner API Patchwork
2023-07-11 17:58 ` [igt-dev] ○ CI.xeBAT: info " Patchwork
2023-07-11 22:17 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
2023-07-12 7:07 ` [igt-dev] ○ CI.xeBAT: info " Patchwork
2023-07-12 7:55 ` Patchwork
2023-07-14 17:22 ` [Intel-gfx] [igt-dev] [PATCH i-g-t 1/2] " Rodrigo Vivi
2023-07-14 17:22 ` Rodrigo Vivi
2023-07-17 8:34 ` [Intel-gfx] " Tvrtko Ursulin
2023-07-17 8:34 ` Tvrtko Ursulin
2023-07-17 14:55 ` [Intel-gfx] " Rodrigo Vivi
2023-07-17 14:55 ` Rodrigo Vivi
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