* [PATCH v2 0/7] Enable HS-G5 support on SM8550
@ 2023-11-07 4:46 ` Can Guo
0 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-07 4:46 UTC (permalink / raw)
To: quic_cang, bvanassche, mani, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen
Cc: linux-scsi, Can Guo, Matthias Brugger,
AngeloGioacchino Del Regno, open list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support
This series enables HS-G5 support on SM8550.
This series is rebased on below changes from Mani -
https://patchwork.kernel.org/project/linux-scsi/patch/20230908145329.154024-1-manivannan.sadhasivam@linaro.org/
https://patchwork.kernel.org/project/linux-scsi/patch/20230908145329.154024-2-manivannan.sadhasivam@linaro.org/
This series is tested on below HW combinations -
SM8550 MTP + UFS4.0
SM8550 QRD + UFS3.1
SM8450 MTP + UFS3.1 (for regression test)
v1 -> v2:
1. Removed 2 changes which were exposing power info in sysfs
2. Removed 1 change which was moving data structs to phy-qcom-qmp-ufs.h
3. Added one new change (the 1st one) to clean up usage of ufs_dev_params based on comments from Mani
4. Adjusted the logic of UFS device version detection according to comments from Mani:
4.1 For HW version < 0x5, go through dual init
4.2 For HW version >= 0x5
a. If UFS device version is populated, one init is required
b. If UFS device version is not populated, go through dual init
Bao D. Nguyen (1):
scsi: ufs: ufs-qcom: Add support for UFS device version detection
Can Guo (6):
scsi: ufs: host: Rename structure ufs_dev_params to ufs_host_params
scsi: ufs: ufs-qcom: Setup host power mode during init
scsi: ufs: ufs-qcom: Allow the first init start with the maximum
supported gear
scsi: ufs: ufs-qcom: Limit HS-G5 Rate-A to hosts with HW version 5
scsi: ufs: ufs-qcom: Set initial PHY gear to max HS gear for HW ver 5
and newer
phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for
SM8550
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
.../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
drivers/ufs/host/ufs-exynos.c | 7 +-
drivers/ufs/host/ufs-hisi.c | 11 +-
drivers/ufs/host/ufs-mediatek.c | 12 +--
drivers/ufs/host/ufs-qcom.c | 78 ++++++++++----
drivers/ufs/host/ufs-qcom.h | 3 +
drivers/ufs/host/ufshcd-pltfrm.c | 49 +++++----
drivers/ufs/host/ufshcd-pltfrm.h | 10 +-
11 files changed, 217 insertions(+), 81 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH v2 0/7] Enable HS-G5 support on SM8550
@ 2023-11-07 4:46 ` Can Guo
0 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-07 4:46 UTC (permalink / raw)
To: quic_cang, bvanassche, mani, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen
Cc: linux-scsi, Can Guo, Matthias Brugger,
AngeloGioacchino Del Regno, open list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support
This series enables HS-G5 support on SM8550.
This series is rebased on below changes from Mani -
https://patchwork.kernel.org/project/linux-scsi/patch/20230908145329.154024-1-manivannan.sadhasivam@linaro.org/
https://patchwork.kernel.org/project/linux-scsi/patch/20230908145329.154024-2-manivannan.sadhasivam@linaro.org/
This series is tested on below HW combinations -
SM8550 MTP + UFS4.0
SM8550 QRD + UFS3.1
SM8450 MTP + UFS3.1 (for regression test)
v1 -> v2:
1. Removed 2 changes which were exposing power info in sysfs
2. Removed 1 change which was moving data structs to phy-qcom-qmp-ufs.h
3. Added one new change (the 1st one) to clean up usage of ufs_dev_params based on comments from Mani
4. Adjusted the logic of UFS device version detection according to comments from Mani:
4.1 For HW version < 0x5, go through dual init
4.2 For HW version >= 0x5
a. If UFS device version is populated, one init is required
b. If UFS device version is not populated, go through dual init
Bao D. Nguyen (1):
scsi: ufs: ufs-qcom: Add support for UFS device version detection
Can Guo (6):
scsi: ufs: host: Rename structure ufs_dev_params to ufs_host_params
scsi: ufs: ufs-qcom: Setup host power mode during init
scsi: ufs: ufs-qcom: Allow the first init start with the maximum
supported gear
scsi: ufs: ufs-qcom: Limit HS-G5 Rate-A to hosts with HW version 5
scsi: ufs: ufs-qcom: Set initial PHY gear to max HS gear for HW ver 5
and newer
phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for
SM8550
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
.../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
drivers/ufs/host/ufs-exynos.c | 7 +-
drivers/ufs/host/ufs-hisi.c | 11 +-
drivers/ufs/host/ufs-mediatek.c | 12 +--
drivers/ufs/host/ufs-qcom.c | 78 ++++++++++----
drivers/ufs/host/ufs-qcom.h | 3 +
drivers/ufs/host/ufshcd-pltfrm.c | 49 +++++----
drivers/ufs/host/ufshcd-pltfrm.h | 10 +-
11 files changed, 217 insertions(+), 81 deletions(-)
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 86+ messages in thread
* [PATCH v2 1/7] scsi: ufs: host: Rename structure ufs_dev_params to ufs_host_params
2023-11-07 4:46 ` Can Guo
@ 2023-11-07 4:46 ` Can Guo
-1 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-07 4:46 UTC (permalink / raw)
To: quic_cang, bvanassche, mani, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen
Cc: linux-scsi, Alim Akhtar, James E.J. Bottomley,
Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Matthias Brugger, AngeloGioacchino Del Regno,
Uwe Kleine-König, Brian Masney,
moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES,
open list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES,
open list,
moderated list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...,
open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...
From: Can Guo <quic_cang@quicinc.com>
Structure ufs_dev_params is actually used in UFS host vendor drivers to
declare host specific power mode parameters, like ufs_<vendor>_params or
host_cap, which makes the code not very straightforward to read. Rename the
structure ufs_dev_params to ufs_host_params and unify the declarations in
all vendor drivers to host_params.
In addition, rename the two functions ufshcd_init_dev_pwr_param() and
ufshcd_get_dev_pwr_param() which work based on the ufs_host_params to
ufshcd_init_host_param() and ufshcd_negotiate_pwr_param() respectively to
avoid confusions.
This change does not change any functionalities or logic.
Signed-off-by: Can Guo <quic_cang@quicinc.com>
---
drivers/ufs/host/ufs-exynos.c | 7 +++---
drivers/ufs/host/ufs-hisi.c | 11 ++++-----
drivers/ufs/host/ufs-mediatek.c | 12 ++++------
drivers/ufs/host/ufs-qcom.c | 12 ++++------
drivers/ufs/host/ufshcd-pltfrm.c | 49 ++++++++++++++++++++--------------------
drivers/ufs/host/ufshcd-pltfrm.h | 10 ++++----
6 files changed, 47 insertions(+), 54 deletions(-)
diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index 71bd6db..674f2f4 100644
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -765,7 +765,7 @@ static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba,
{
struct exynos_ufs *ufs = ufshcd_get_variant(hba);
struct phy *generic_phy = ufs->phy;
- struct ufs_dev_params ufs_exynos_cap;
+ struct ufs_host_params host_params;
int ret;
if (!dev_req_params) {
@@ -774,10 +774,9 @@ static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba,
goto out;
}
- ufshcd_init_pwr_dev_param(&ufs_exynos_cap);
+ ufshcd_init_host_param(&host_params);
- ret = ufshcd_get_pwr_dev_param(&ufs_exynos_cap,
- dev_max_params, dev_req_params);
+ ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
if (ret) {
pr_err("%s: failed to determine capabilities\n", __func__);
goto out;
diff --git a/drivers/ufs/host/ufs-hisi.c b/drivers/ufs/host/ufs-hisi.c
index 0229ac0..bb0c9a7 100644
--- a/drivers/ufs/host/ufs-hisi.c
+++ b/drivers/ufs/host/ufs-hisi.c
@@ -293,9 +293,9 @@ static int ufs_hisi_link_startup_notify(struct ufs_hba *hba,
return err;
}
-static void ufs_hisi_set_dev_cap(struct ufs_dev_params *hisi_param)
+static void ufs_hisi_set_dev_cap(struct ufs_host_params *host_params)
{
- ufshcd_init_pwr_dev_param(hisi_param);
+ ufshcd_init_host_param(host_params);
}
static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba)
@@ -365,7 +365,7 @@ static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba,
struct ufs_pa_layer_attr *dev_max_params,
struct ufs_pa_layer_attr *dev_req_params)
{
- struct ufs_dev_params ufs_hisi_cap;
+ struct ufs_host_params host_params;
int ret = 0;
if (!dev_req_params) {
@@ -377,9 +377,8 @@ static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba,
switch (status) {
case PRE_CHANGE:
- ufs_hisi_set_dev_cap(&ufs_hisi_cap);
- ret = ufshcd_get_pwr_dev_param(&ufs_hisi_cap,
- dev_max_params, dev_req_params);
+ ufs_hisi_set_dev_cap(&host_params);
+ ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
if (ret) {
dev_err(hba->dev,
"%s: failed to determine capabilities\n", __func__);
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index fc61790..016067d 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -996,16 +996,14 @@ static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba,
struct ufs_pa_layer_attr *dev_req_params)
{
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
- struct ufs_dev_params host_cap;
+ struct ufs_host_params host_params;
int ret;
- ufshcd_init_pwr_dev_param(&host_cap);
- host_cap.hs_rx_gear = UFS_HS_G5;
- host_cap.hs_tx_gear = UFS_HS_G5;
+ ufshcd_init_host_param(&host_params);
+ host_params.hs_rx_gear = UFS_HS_G5;
+ host_params.hs_tx_gear = UFS_HS_G5;
- ret = ufshcd_get_pwr_dev_param(&host_cap,
- dev_max_params,
- dev_req_params);
+ ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
if (ret) {
pr_info("%s: failed to determine capabilities\n",
__func__);
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 96cb8b5..aee66a3 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -898,7 +898,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
struct ufs_pa_layer_attr *dev_req_params)
{
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
- struct ufs_dev_params ufs_qcom_cap;
+ struct ufs_host_params host_params;
int ret = 0;
if (!dev_req_params) {
@@ -908,15 +908,13 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
switch (status) {
case PRE_CHANGE:
- ufshcd_init_pwr_dev_param(&ufs_qcom_cap);
- ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
+ ufshcd_init_host_param(&host_params);
+ host_params.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
/* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
- ufs_qcom_cap.hs_tx_gear = ufs_qcom_cap.hs_rx_gear = ufs_qcom_get_hs_gear(hba);
+ host_params.hs_tx_gear = host_params.hs_rx_gear = ufs_qcom_get_hs_gear(hba);
- ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap,
- dev_max_params,
- dev_req_params);
+ ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
if (ret) {
dev_err(hba->dev, "%s: failed to determine capabilities\n",
__func__);
diff --git a/drivers/ufs/host/ufshcd-pltfrm.c b/drivers/ufs/host/ufshcd-pltfrm.c
index da2558e..6e65b61 100644
--- a/drivers/ufs/host/ufshcd-pltfrm.c
+++ b/drivers/ufs/host/ufshcd-pltfrm.c
@@ -285,17 +285,17 @@ static int ufshcd_parse_operating_points(struct ufs_hba *hba)
}
/**
- * ufshcd_get_pwr_dev_param - get finally agreed attributes for
+ * ufshcd_negotiate_pwr_param - get finally agreed attributes for
* power mode change
- * @pltfrm_param: pointer to platform parameters
+ * @host_param: pointer to platform parameters
* @dev_max: pointer to device attributes
* @agreed_pwr: returned agreed attributes
*
* Return: 0 on success, non-zero value on failure.
*/
-int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
- const struct ufs_pa_layer_attr *dev_max,
- struct ufs_pa_layer_attr *agreed_pwr)
+int ufshcd_negotiate_pwr_param(const struct ufs_host_params *host_param,
+ const struct ufs_pa_layer_attr *dev_max,
+ struct ufs_pa_layer_attr *agreed_pwr)
{
int min_pltfrm_gear;
int min_dev_gear;
@@ -305,19 +305,18 @@ int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
if (dev_max->pwr_rx == FAST_MODE)
is_dev_sup_hs = true;
- if (pltfrm_param->desired_working_mode == UFS_HS_MODE) {
+ if (host_param->desired_working_mode == UFS_HS_MODE) {
is_pltfrm_max_hs = true;
- min_pltfrm_gear = min_t(u32, pltfrm_param->hs_rx_gear,
- pltfrm_param->hs_tx_gear);
+ min_pltfrm_gear = min_t(u32, host_param->hs_rx_gear,
+ host_param->hs_tx_gear);
} else {
- min_pltfrm_gear = min_t(u32, pltfrm_param->pwm_rx_gear,
- pltfrm_param->pwm_tx_gear);
+ min_pltfrm_gear = min_t(u32, host_param->pwm_rx_gear,
+ host_param->pwm_tx_gear);
}
/*
- * device doesn't support HS but
- * pltfrm_param->desired_working_mode is HS,
- * thus device and pltfrm_param don't agree
+ * device doesn't support HS but host_param->desired_working_mode is HS,
+ * thus device and host_param don't agree
*/
if (!is_dev_sup_hs && is_pltfrm_max_hs) {
pr_info("%s: device doesn't support HS\n",
@@ -326,20 +325,20 @@ int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
} else if (is_dev_sup_hs && is_pltfrm_max_hs) {
/*
* since device supports HS, it supports FAST_MODE.
- * since pltfrm_param->desired_working_mode is also HS
+ * since host_param->desired_working_mode is also HS
* then final decision (FAST/FASTAUTO) is done according
* to pltfrm_params as it is the restricting factor
*/
- agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_hs;
+ agreed_pwr->pwr_rx = host_param->rx_pwr_hs;
agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
} else {
/*
- * here pltfrm_param->desired_working_mode is PWM.
+ * here host_param->desired_working_mode is PWM.
* it doesn't matter whether device supports HS or PWM,
- * in both cases pltfrm_param->desired_working_mode will
+ * in both cases host_param->desired_working_mode will
* determine the mode
*/
- agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_pwm;
+ agreed_pwr->pwr_rx = host_param->rx_pwr_pwm;
agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
}
@@ -349,9 +348,9 @@ int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
* the same decision will be made for rx
*/
agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
- pltfrm_param->tx_lanes);
+ host_param->tx_lanes);
agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
- pltfrm_param->rx_lanes);
+ host_param->rx_lanes);
/* device maximum gear is the minimum between device rx and tx gears */
min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
@@ -375,15 +374,15 @@ int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
}
agreed_pwr->gear_tx = agreed_pwr->gear_rx;
- agreed_pwr->hs_rate = pltfrm_param->hs_rate;
+ agreed_pwr->hs_rate = host_param->hs_rate;
return 0;
}
-EXPORT_SYMBOL_GPL(ufshcd_get_pwr_dev_param);
+EXPORT_SYMBOL_GPL(ufshcd_negotiate_pwr_param);
-void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param)
+void ufshcd_init_host_param(struct ufs_host_params *host_param)
{
- *dev_param = (struct ufs_dev_params){
+ *host_param = (struct ufs_host_params){
.tx_lanes = UFS_LANE_2,
.rx_lanes = UFS_LANE_2,
.hs_rx_gear = UFS_HS_G3,
@@ -398,7 +397,7 @@ void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param)
.desired_working_mode = UFS_HS_MODE,
};
}
-EXPORT_SYMBOL_GPL(ufshcd_init_pwr_dev_param);
+EXPORT_SYMBOL_GPL(ufshcd_init_host_param);
/**
* ufshcd_pltfrm_init - probe routine of the driver
diff --git a/drivers/ufs/host/ufshcd-pltfrm.h b/drivers/ufs/host/ufshcd-pltfrm.h
index a86a3ad..2d4d047 100644
--- a/drivers/ufs/host/ufshcd-pltfrm.h
+++ b/drivers/ufs/host/ufshcd-pltfrm.h
@@ -10,7 +10,7 @@
#define UFS_PWM_MODE 1
#define UFS_HS_MODE 2
-struct ufs_dev_params {
+struct ufs_host_params {
u32 pwm_rx_gear; /* pwm rx gear to work in */
u32 pwm_tx_gear; /* pwm tx gear to work in */
u32 hs_rx_gear; /* hs rx gear to work in */
@@ -25,10 +25,10 @@ struct ufs_dev_params {
u32 desired_working_mode;
};
-int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *dev_param,
- const struct ufs_pa_layer_attr *dev_max,
- struct ufs_pa_layer_attr *agreed_pwr);
-void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param);
+int ufshcd_negotiate_pwr_param(const struct ufs_host_params *host_param,
+ const struct ufs_pa_layer_attr *dev_max,
+ struct ufs_pa_layer_attr *agreed_pwr);
+void ufshcd_init_host_param(struct ufs_host_params *host_param);
int ufshcd_pltfrm_init(struct platform_device *pdev,
const struct ufs_hba_variant_ops *vops);
int ufshcd_populate_vreg(struct device *dev, const char *name,
--
2.7.4
^ permalink raw reply related [flat|nested] 86+ messages in thread
* [PATCH v2 1/7] scsi: ufs: host: Rename structure ufs_dev_params to ufs_host_params
@ 2023-11-07 4:46 ` Can Guo
0 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-07 4:46 UTC (permalink / raw)
To: quic_cang, bvanassche, mani, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen
Cc: linux-scsi, Alim Akhtar, James E.J. Bottomley,
Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Matthias Brugger, AngeloGioacchino Del Regno,
Uwe Kleine-König, Brian Masney,
moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES,
open list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES,
open list,
moderated list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...,
open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...
From: Can Guo <quic_cang@quicinc.com>
Structure ufs_dev_params is actually used in UFS host vendor drivers to
declare host specific power mode parameters, like ufs_<vendor>_params or
host_cap, which makes the code not very straightforward to read. Rename the
structure ufs_dev_params to ufs_host_params and unify the declarations in
all vendor drivers to host_params.
In addition, rename the two functions ufshcd_init_dev_pwr_param() and
ufshcd_get_dev_pwr_param() which work based on the ufs_host_params to
ufshcd_init_host_param() and ufshcd_negotiate_pwr_param() respectively to
avoid confusions.
This change does not change any functionalities or logic.
Signed-off-by: Can Guo <quic_cang@quicinc.com>
---
drivers/ufs/host/ufs-exynos.c | 7 +++---
drivers/ufs/host/ufs-hisi.c | 11 ++++-----
drivers/ufs/host/ufs-mediatek.c | 12 ++++------
drivers/ufs/host/ufs-qcom.c | 12 ++++------
drivers/ufs/host/ufshcd-pltfrm.c | 49 ++++++++++++++++++++--------------------
drivers/ufs/host/ufshcd-pltfrm.h | 10 ++++----
6 files changed, 47 insertions(+), 54 deletions(-)
diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index 71bd6db..674f2f4 100644
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -765,7 +765,7 @@ static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba,
{
struct exynos_ufs *ufs = ufshcd_get_variant(hba);
struct phy *generic_phy = ufs->phy;
- struct ufs_dev_params ufs_exynos_cap;
+ struct ufs_host_params host_params;
int ret;
if (!dev_req_params) {
@@ -774,10 +774,9 @@ static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba,
goto out;
}
- ufshcd_init_pwr_dev_param(&ufs_exynos_cap);
+ ufshcd_init_host_param(&host_params);
- ret = ufshcd_get_pwr_dev_param(&ufs_exynos_cap,
- dev_max_params, dev_req_params);
+ ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
if (ret) {
pr_err("%s: failed to determine capabilities\n", __func__);
goto out;
diff --git a/drivers/ufs/host/ufs-hisi.c b/drivers/ufs/host/ufs-hisi.c
index 0229ac0..bb0c9a7 100644
--- a/drivers/ufs/host/ufs-hisi.c
+++ b/drivers/ufs/host/ufs-hisi.c
@@ -293,9 +293,9 @@ static int ufs_hisi_link_startup_notify(struct ufs_hba *hba,
return err;
}
-static void ufs_hisi_set_dev_cap(struct ufs_dev_params *hisi_param)
+static void ufs_hisi_set_dev_cap(struct ufs_host_params *host_params)
{
- ufshcd_init_pwr_dev_param(hisi_param);
+ ufshcd_init_host_param(host_params);
}
static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba)
@@ -365,7 +365,7 @@ static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba,
struct ufs_pa_layer_attr *dev_max_params,
struct ufs_pa_layer_attr *dev_req_params)
{
- struct ufs_dev_params ufs_hisi_cap;
+ struct ufs_host_params host_params;
int ret = 0;
if (!dev_req_params) {
@@ -377,9 +377,8 @@ static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba,
switch (status) {
case PRE_CHANGE:
- ufs_hisi_set_dev_cap(&ufs_hisi_cap);
- ret = ufshcd_get_pwr_dev_param(&ufs_hisi_cap,
- dev_max_params, dev_req_params);
+ ufs_hisi_set_dev_cap(&host_params);
+ ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
if (ret) {
dev_err(hba->dev,
"%s: failed to determine capabilities\n", __func__);
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index fc61790..016067d 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -996,16 +996,14 @@ static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba,
struct ufs_pa_layer_attr *dev_req_params)
{
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
- struct ufs_dev_params host_cap;
+ struct ufs_host_params host_params;
int ret;
- ufshcd_init_pwr_dev_param(&host_cap);
- host_cap.hs_rx_gear = UFS_HS_G5;
- host_cap.hs_tx_gear = UFS_HS_G5;
+ ufshcd_init_host_param(&host_params);
+ host_params.hs_rx_gear = UFS_HS_G5;
+ host_params.hs_tx_gear = UFS_HS_G5;
- ret = ufshcd_get_pwr_dev_param(&host_cap,
- dev_max_params,
- dev_req_params);
+ ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
if (ret) {
pr_info("%s: failed to determine capabilities\n",
__func__);
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 96cb8b5..aee66a3 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -898,7 +898,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
struct ufs_pa_layer_attr *dev_req_params)
{
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
- struct ufs_dev_params ufs_qcom_cap;
+ struct ufs_host_params host_params;
int ret = 0;
if (!dev_req_params) {
@@ -908,15 +908,13 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
switch (status) {
case PRE_CHANGE:
- ufshcd_init_pwr_dev_param(&ufs_qcom_cap);
- ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
+ ufshcd_init_host_param(&host_params);
+ host_params.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
/* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
- ufs_qcom_cap.hs_tx_gear = ufs_qcom_cap.hs_rx_gear = ufs_qcom_get_hs_gear(hba);
+ host_params.hs_tx_gear = host_params.hs_rx_gear = ufs_qcom_get_hs_gear(hba);
- ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap,
- dev_max_params,
- dev_req_params);
+ ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
if (ret) {
dev_err(hba->dev, "%s: failed to determine capabilities\n",
__func__);
diff --git a/drivers/ufs/host/ufshcd-pltfrm.c b/drivers/ufs/host/ufshcd-pltfrm.c
index da2558e..6e65b61 100644
--- a/drivers/ufs/host/ufshcd-pltfrm.c
+++ b/drivers/ufs/host/ufshcd-pltfrm.c
@@ -285,17 +285,17 @@ static int ufshcd_parse_operating_points(struct ufs_hba *hba)
}
/**
- * ufshcd_get_pwr_dev_param - get finally agreed attributes for
+ * ufshcd_negotiate_pwr_param - get finally agreed attributes for
* power mode change
- * @pltfrm_param: pointer to platform parameters
+ * @host_param: pointer to platform parameters
* @dev_max: pointer to device attributes
* @agreed_pwr: returned agreed attributes
*
* Return: 0 on success, non-zero value on failure.
*/
-int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
- const struct ufs_pa_layer_attr *dev_max,
- struct ufs_pa_layer_attr *agreed_pwr)
+int ufshcd_negotiate_pwr_param(const struct ufs_host_params *host_param,
+ const struct ufs_pa_layer_attr *dev_max,
+ struct ufs_pa_layer_attr *agreed_pwr)
{
int min_pltfrm_gear;
int min_dev_gear;
@@ -305,19 +305,18 @@ int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
if (dev_max->pwr_rx == FAST_MODE)
is_dev_sup_hs = true;
- if (pltfrm_param->desired_working_mode == UFS_HS_MODE) {
+ if (host_param->desired_working_mode == UFS_HS_MODE) {
is_pltfrm_max_hs = true;
- min_pltfrm_gear = min_t(u32, pltfrm_param->hs_rx_gear,
- pltfrm_param->hs_tx_gear);
+ min_pltfrm_gear = min_t(u32, host_param->hs_rx_gear,
+ host_param->hs_tx_gear);
} else {
- min_pltfrm_gear = min_t(u32, pltfrm_param->pwm_rx_gear,
- pltfrm_param->pwm_tx_gear);
+ min_pltfrm_gear = min_t(u32, host_param->pwm_rx_gear,
+ host_param->pwm_tx_gear);
}
/*
- * device doesn't support HS but
- * pltfrm_param->desired_working_mode is HS,
- * thus device and pltfrm_param don't agree
+ * device doesn't support HS but host_param->desired_working_mode is HS,
+ * thus device and host_param don't agree
*/
if (!is_dev_sup_hs && is_pltfrm_max_hs) {
pr_info("%s: device doesn't support HS\n",
@@ -326,20 +325,20 @@ int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
} else if (is_dev_sup_hs && is_pltfrm_max_hs) {
/*
* since device supports HS, it supports FAST_MODE.
- * since pltfrm_param->desired_working_mode is also HS
+ * since host_param->desired_working_mode is also HS
* then final decision (FAST/FASTAUTO) is done according
* to pltfrm_params as it is the restricting factor
*/
- agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_hs;
+ agreed_pwr->pwr_rx = host_param->rx_pwr_hs;
agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
} else {
/*
- * here pltfrm_param->desired_working_mode is PWM.
+ * here host_param->desired_working_mode is PWM.
* it doesn't matter whether device supports HS or PWM,
- * in both cases pltfrm_param->desired_working_mode will
+ * in both cases host_param->desired_working_mode will
* determine the mode
*/
- agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_pwm;
+ agreed_pwr->pwr_rx = host_param->rx_pwr_pwm;
agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
}
@@ -349,9 +348,9 @@ int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
* the same decision will be made for rx
*/
agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
- pltfrm_param->tx_lanes);
+ host_param->tx_lanes);
agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
- pltfrm_param->rx_lanes);
+ host_param->rx_lanes);
/* device maximum gear is the minimum between device rx and tx gears */
min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
@@ -375,15 +374,15 @@ int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
}
agreed_pwr->gear_tx = agreed_pwr->gear_rx;
- agreed_pwr->hs_rate = pltfrm_param->hs_rate;
+ agreed_pwr->hs_rate = host_param->hs_rate;
return 0;
}
-EXPORT_SYMBOL_GPL(ufshcd_get_pwr_dev_param);
+EXPORT_SYMBOL_GPL(ufshcd_negotiate_pwr_param);
-void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param)
+void ufshcd_init_host_param(struct ufs_host_params *host_param)
{
- *dev_param = (struct ufs_dev_params){
+ *host_param = (struct ufs_host_params){
.tx_lanes = UFS_LANE_2,
.rx_lanes = UFS_LANE_2,
.hs_rx_gear = UFS_HS_G3,
@@ -398,7 +397,7 @@ void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param)
.desired_working_mode = UFS_HS_MODE,
};
}
-EXPORT_SYMBOL_GPL(ufshcd_init_pwr_dev_param);
+EXPORT_SYMBOL_GPL(ufshcd_init_host_param);
/**
* ufshcd_pltfrm_init - probe routine of the driver
diff --git a/drivers/ufs/host/ufshcd-pltfrm.h b/drivers/ufs/host/ufshcd-pltfrm.h
index a86a3ad..2d4d047 100644
--- a/drivers/ufs/host/ufshcd-pltfrm.h
+++ b/drivers/ufs/host/ufshcd-pltfrm.h
@@ -10,7 +10,7 @@
#define UFS_PWM_MODE 1
#define UFS_HS_MODE 2
-struct ufs_dev_params {
+struct ufs_host_params {
u32 pwm_rx_gear; /* pwm rx gear to work in */
u32 pwm_tx_gear; /* pwm tx gear to work in */
u32 hs_rx_gear; /* hs rx gear to work in */
@@ -25,10 +25,10 @@ struct ufs_dev_params {
u32 desired_working_mode;
};
-int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *dev_param,
- const struct ufs_pa_layer_attr *dev_max,
- struct ufs_pa_layer_attr *agreed_pwr);
-void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param);
+int ufshcd_negotiate_pwr_param(const struct ufs_host_params *host_param,
+ const struct ufs_pa_layer_attr *dev_max,
+ struct ufs_pa_layer_attr *agreed_pwr);
+void ufshcd_init_host_param(struct ufs_host_params *host_param);
int ufshcd_pltfrm_init(struct platform_device *pdev,
const struct ufs_hba_variant_ops *vops);
int ufshcd_populate_vreg(struct device *dev, const char *name,
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 86+ messages in thread
* [PATCH v2 2/7] scsi: ufs: ufs-qcom: Setup host power mode during init
2023-11-07 4:46 ` Can Guo
(?)
(?)
@ 2023-11-07 4:46 ` Can Guo
2023-11-07 20:14 ` Andrew Halaney
2023-11-08 5:07 ` Manivannan Sadhasivam
-1 siblings, 2 replies; 86+ messages in thread
From: Can Guo @ 2023-11-07 4:46 UTC (permalink / raw)
To: quic_cang, bvanassche, mani, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen
Cc: linux-scsi, Bao D . Nguyen, Andy Gross, Bjorn Andersson,
Konrad Dybcio, James E.J. Bottomley,
open list:ARM/QUALCOMM SUPPORT, open list
From: Can Guo <quic_cang@quicinc.com>
Setup host power mode and its limitations during UFS host driver init to
avoid repetitive work during every power mode change.
Co-developed-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
Signed-off-by: Can Guo <quic_cang@quicinc.com>
---
drivers/ufs/host/ufs-qcom.c | 22 ++++++++++++++--------
drivers/ufs/host/ufs-qcom.h | 1 +
2 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index aee66a3..cc0eb37 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -898,7 +898,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
struct ufs_pa_layer_attr *dev_req_params)
{
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
- struct ufs_host_params host_params;
+ struct ufs_host_params *host_params = &host->host_params;
int ret = 0;
if (!dev_req_params) {
@@ -908,13 +908,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
switch (status) {
case PRE_CHANGE:
- ufshcd_init_host_param(&host_params);
- host_params.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
-
- /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
- host_params.hs_tx_gear = host_params.hs_rx_gear = ufs_qcom_get_hs_gear(hba);
-
- ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
+ ret = ufshcd_negotiate_pwr_param(host_params, dev_max_params, dev_req_params);
if (ret) {
dev_err(hba->dev, "%s: failed to determine capabilities\n",
__func__);
@@ -1049,6 +1043,17 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
}
+static void ufs_qcom_set_host_params(struct ufs_hba *hba)
+{
+ struct ufs_qcom_host *host = ufshcd_get_variant(hba);
+ struct ufs_host_params *host_params = &host->host_params;
+
+ ufshcd_init_host_param(host_params);
+
+ /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
+ host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba);
+}
+
static void ufs_qcom_set_caps(struct ufs_hba *hba)
{
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
@@ -1273,6 +1278,7 @@ static int ufs_qcom_init(struct ufs_hba *hba)
ufs_qcom_set_caps(hba);
ufs_qcom_advertise_quirks(hba);
+ ufs_qcom_set_host_params(hba);
err = ufs_qcom_ice_init(host);
if (err)
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index 9950a00..ab94c54 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -240,6 +240,7 @@ struct ufs_qcom_host {
struct gpio_desc *device_reset;
+ struct ufs_host_params host_params;
u32 phy_gear;
bool esi_enabled;
--
2.7.4
^ permalink raw reply related [flat|nested] 86+ messages in thread
* [PATCH v2 3/7] scsi: ufs: ufs-qcom: Allow the first init start with the maximum supported gear
2023-11-07 4:46 ` Can Guo
` (2 preceding siblings ...)
(?)
@ 2023-11-07 4:46 ` Can Guo
2023-11-08 5:23 ` Manivannan Sadhasivam
-1 siblings, 1 reply; 86+ messages in thread
From: Can Guo @ 2023-11-07 4:46 UTC (permalink / raw)
To: quic_cang, bvanassche, mani, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen
Cc: linux-scsi, Andy Gross, Bjorn Andersson, Konrad Dybcio,
James E.J. Bottomley, open list:ARM/QUALCOMM SUPPORT, open list
From: Can Guo <quic_cang@quicinc.com>
During host driver init, the phy_gear is set to the minimum supported gear
(HS_G2). Then, during the first power mode change, the negotiated gear, say
HS-G4, is updated to the phy_gear variable so that in the second init the
updated phy_gear can be used to program the PHY.
But the current code only allows update the phy_gear to a higher value. If
one wants to start the first init with the maximum support gear, say HS-G4,
the phy_gear is not updated to HS-G3 if the device only supports HS-G3.
The original check added there is intend to make sure the phy_gear won't be
updated when gear is scaled down (during clock scaling). Update the check
so that one can start the first init with the maximum support gear without
breaking the original fix by checking the ufshcd_state, that is, allow
update to phy_gear only if power mode change is invoked from
ufshcd_probe_hba().
This change is a preparation patch for the next patches in the same series.
Signed-off-by: Can Guo <quic_cang@quicinc.com>
---
drivers/ufs/host/ufs-qcom.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index cc0eb37..60b35ca 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -916,11 +916,12 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
}
/*
- * Update phy_gear only when the gears are scaled to a higher value. This is
- * because, the PHY gear settings are backwards compatible and we only need to
- * change the PHY gear settings while scaling to higher gears.
+ * During UFS driver probe, always update the PHY gear to match the negotiated
+ * gear, so that, if quirk UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is enabled,
+ * the second init can program the optimal PHY settings. This allows one to start
+ * the first init with either the minimum or the maximum support gear.
*/
- if (dev_req_params->gear_tx > host->phy_gear)
+ if (hba->ufshcd_state == UFSHCD_STATE_RESET)
host->phy_gear = dev_req_params->gear_tx;
/* enable the device ref clock before changing to HS mode */
--
2.7.4
^ permalink raw reply related [flat|nested] 86+ messages in thread
* [PATCH v2 4/7] scsi: ufs: ufs-qcom: Limit HS-G5 Rate-A to hosts with HW version 5
2023-11-07 4:46 ` Can Guo
` (3 preceding siblings ...)
(?)
@ 2023-11-07 4:46 ` Can Guo
2023-11-08 5:25 ` Manivannan Sadhasivam
-1 siblings, 1 reply; 86+ messages in thread
From: Can Guo @ 2023-11-07 4:46 UTC (permalink / raw)
To: quic_cang, bvanassche, mani, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen
Cc: linux-scsi, Andy Gross, Bjorn Andersson, Konrad Dybcio,
James E.J. Bottomley, open list:ARM/QUALCOMM SUPPORT, open list
From: Can Guo <quic_cang@quicinc.com>
Qcom UFS hosts, with HW ver 5, can only support up to HS-G5 Rate-A due to
HW limitations. If the HS-G5 PHY gear is used, update host_params->hs_rate
to Rate-A, so that the subsequent power mode changes shall stick to Rate-A.
Signed-off-by: Can Guo <quic_cang@quicinc.com>
---
drivers/ufs/host/ufs-qcom.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 60b35ca..55ee31d 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -442,9 +442,25 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
{
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
+ struct ufs_host_params *host_params = &host->host_params;
struct phy *phy = host->generic_phy;
+ enum phy_mode mode;
int ret;
+ /*
+ * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations.
+ * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A,
+ * so that the subsequent power mode change shall stick to Rate-A.
+ */
+ if (host->hw_ver.major == 0x5) {
+ if (host->phy_gear == UFS_HS_G5)
+ host_params->hs_rate = PA_HS_MODE_A;
+ else
+ host_params->hs_rate = PA_HS_MODE_B;
+ }
+
+ mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A;
+
/* Reset UFS Host Controller and PHY */
ret = ufs_qcom_host_reset(hba);
if (ret)
@@ -459,7 +475,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
return ret;
}
- phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);
+ phy_set_mode_ext(phy, mode, host->phy_gear);
/* power on phy - start serdes and phy's power and clocks */
ret = phy_power_on(phy);
--
2.7.4
^ permalink raw reply related [flat|nested] 86+ messages in thread
* [PATCH v2 5/7] scsi: ufs: ufs-qcom: Set initial PHY gear to max HS gear for HW ver 5 and newer
2023-11-07 4:46 ` Can Guo
` (4 preceding siblings ...)
(?)
@ 2023-11-07 4:46 ` Can Guo
2023-11-08 5:34 ` Manivannan Sadhasivam
-1 siblings, 1 reply; 86+ messages in thread
From: Can Guo @ 2023-11-07 4:46 UTC (permalink / raw)
To: quic_cang, bvanassche, mani, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen
Cc: linux-scsi, Andy Gross, Bjorn Andersson, Konrad Dybcio,
James E.J. Bottomley,
open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...,
open list
From: Can Guo <quic_cang@quicinc.com>
Set the initial PHY gear to max HS gear for hosts with HW ver 5 and newer.
This patch is not changing any functionalities or logic but only a
preparation patch for the next patch in this series.
Signed-off-by: Can Guo <quic_cang@quicinc.com>
---
drivers/ufs/host/ufs-qcom.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 55ee31d..94d34b5 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -1069,6 +1069,14 @@ static void ufs_qcom_set_host_params(struct ufs_hba *hba)
/* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba);
+ host->phy_gear = host_params->hs_tx_gear;
+
+ /*
+ * Power up the PHY using the minimum supported gear (UFS_HS_G2).
+ * Switching to max gear will be performed during reinit if supported.
+ */
+ if (host->hw_ver.major < 0x5)
+ host->phy_gear = UFS_HS_G2;
}
static void ufs_qcom_set_caps(struct ufs_hba *hba)
@@ -1313,12 +1321,6 @@ static int ufs_qcom_init(struct ufs_hba *hba)
dev_warn(dev, "%s: failed to configure the testbus %d\n",
__func__, err);
- /*
- * Power up the PHY using the minimum supported gear (UFS_HS_G2).
- * Switching to max gear will be performed during reinit if supported.
- */
- host->phy_gear = UFS_HS_G2;
-
return 0;
out_variant_clear:
--
2.7.4
^ permalink raw reply related [flat|nested] 86+ messages in thread
* [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-07 4:46 ` Can Guo
@ 2023-11-07 4:46 ` Can Guo
-1 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-07 4:46 UTC (permalink / raw)
To: quic_cang, bvanassche, mani, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen
Cc: linux-scsi, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
From: Can Guo <quic_cang@quicinc.com>
On SM8550, two sets of UFS PHY settings are provided, one set is to support
HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
settings are programming different values to different registers, mixing
the two sets and/or overwriting one set with another set is definitely not
blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
need to split the two sets into their dedicated tables, and leave only the
common settings in the .tlbs. To have the PHY programmed with the correct
set of PHY settings, the submode passed to PHY driver must be either HS-G4
or HS-G5.
Signed-off-by: Can Guo <quic_cang@quicinc.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
.../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
4 files changed, 115 insertions(+), 13 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
index c23d5e4..e563af5 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
@@ -18,6 +18,7 @@
#define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
#define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
#define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
+#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
#define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
#define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
#define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
@@ -27,5 +28,6 @@
#define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
#define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
#define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
+#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
index f420f8f..ef392ce 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
@@ -56,6 +56,8 @@
#define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
#define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
#define QSERDES_V6_COM_PLL_IVCO 0xf4
+#define QSERDES_V6_COM_CMN_IETRIM 0xfc
+#define QSERDES_V6_COM_CMN_IPTRIM 0x100
#define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
#define QSERDES_V6_COM_RESETSM_CNTRL 0x118
#define QSERDES_V6_COM_LOCK_CMP_EN 0x120
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
index 15bcb4b..48f31c8 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
@@ -10,10 +10,20 @@
#define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
+#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
+#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
+#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
+#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
+#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
+#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
+#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
+#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
+#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
+#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
@@ -25,6 +35,8 @@
#define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
#define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
#define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
+#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
#define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
+#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 3927eba..e0a01497 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
+
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
+
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
};
static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
- QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
};
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
+};
+
static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
- QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
- QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
- QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
@@ -690,14 +709,46 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
};
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
+
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
+};
+
static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
- QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
};
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
+};
+
struct qmp_ufs_offsets {
u16 serdes;
u16 pcs;
@@ -731,6 +782,8 @@ struct qmp_phy_cfg {
const struct qmp_phy_cfg_tbls tbls_hs_b;
/* Additional sequence for HS G4 */
const struct qmp_phy_cfg_tbls tbls_hs_g4;
+ /* Additional sequence for HS G4 */
+ const struct qmp_phy_cfg_tbls tbls_hs_g5;
/* clock ids to be requested */
const char * const *clk_list;
@@ -1157,6 +1210,28 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
.pcs = sm8550_ufsphy_pcs,
.pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
},
+ .tbls_hs_b = {
+ .serdes = sm8550_ufsphy_hs_b_serdes,
+ .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
+ },
+ .tbls_hs_g4 = {
+ .serdes = sm8550_ufsphy_g4_serdes,
+ .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
+ .tx = sm8550_ufsphy_g4_tx,
+ .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
+ .rx = sm8550_ufsphy_g4_rx,
+ .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
+ .pcs = sm8550_ufsphy_g4_pcs,
+ .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
+ },
+ .tbls_hs_g5 = {
+ .serdes = sm8550_ufsphy_g5_serdes,
+ .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
+ .rx = sm8550_ufsphy_g5_rx,
+ .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
+ .pcs = sm8550_ufsphy_g5_pcs,
+ .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -1222,14 +1297,25 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
{
qmp_ufs_serdes_init(qmp, &cfg->tbls);
+ if (qmp->submode == UFS_HS_G4)
+ qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
+ else if (qmp->submode == UFS_HS_G5)
+ qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
+
if (qmp->mode == PHY_MODE_UFS_HS_B)
qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
+
qmp_ufs_lanes_init(qmp, &cfg->tbls);
if (qmp->submode == UFS_HS_G4)
qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4);
+ else if (qmp->submode == UFS_HS_G5)
+ qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g5);
+
qmp_ufs_pcs_init(qmp, &cfg->tbls);
if (qmp->submode == UFS_HS_G4)
qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4);
+ else if (qmp->submode == UFS_HS_G5)
+ qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g5);
}
static int qmp_ufs_com_init(struct qmp_ufs *qmp)
--
2.7.4
^ permalink raw reply related [flat|nested] 86+ messages in thread
* [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-07 4:46 ` Can Guo
0 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-07 4:46 UTC (permalink / raw)
To: quic_cang, bvanassche, mani, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen
Cc: linux-scsi, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
From: Can Guo <quic_cang@quicinc.com>
On SM8550, two sets of UFS PHY settings are provided, one set is to support
HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
settings are programming different values to different registers, mixing
the two sets and/or overwriting one set with another set is definitely not
blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
need to split the two sets into their dedicated tables, and leave only the
common settings in the .tlbs. To have the PHY programmed with the correct
set of PHY settings, the submode passed to PHY driver must be either HS-G4
or HS-G5.
Signed-off-by: Can Guo <quic_cang@quicinc.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
.../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
4 files changed, 115 insertions(+), 13 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
index c23d5e4..e563af5 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
@@ -18,6 +18,7 @@
#define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
#define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
#define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
+#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
#define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
#define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
#define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
@@ -27,5 +28,6 @@
#define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
#define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
#define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
+#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
index f420f8f..ef392ce 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
@@ -56,6 +56,8 @@
#define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
#define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
#define QSERDES_V6_COM_PLL_IVCO 0xf4
+#define QSERDES_V6_COM_CMN_IETRIM 0xfc
+#define QSERDES_V6_COM_CMN_IPTRIM 0x100
#define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
#define QSERDES_V6_COM_RESETSM_CNTRL 0x118
#define QSERDES_V6_COM_LOCK_CMP_EN 0x120
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
index 15bcb4b..48f31c8 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
@@ -10,10 +10,20 @@
#define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
+#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
+#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
+#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
+#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
+#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
+#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
+#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
+#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
+#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
+#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
@@ -25,6 +35,8 @@
#define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
#define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
#define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
+#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
#define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
+#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 3927eba..e0a01497 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
+
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
+
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
};
static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
- QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
};
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
+};
+
static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
- QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
- QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
- QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
@@ -690,14 +709,46 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
};
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
+
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
+};
+
static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
- QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
};
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
+};
+
struct qmp_ufs_offsets {
u16 serdes;
u16 pcs;
@@ -731,6 +782,8 @@ struct qmp_phy_cfg {
const struct qmp_phy_cfg_tbls tbls_hs_b;
/* Additional sequence for HS G4 */
const struct qmp_phy_cfg_tbls tbls_hs_g4;
+ /* Additional sequence for HS G4 */
+ const struct qmp_phy_cfg_tbls tbls_hs_g5;
/* clock ids to be requested */
const char * const *clk_list;
@@ -1157,6 +1210,28 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
.pcs = sm8550_ufsphy_pcs,
.pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
},
+ .tbls_hs_b = {
+ .serdes = sm8550_ufsphy_hs_b_serdes,
+ .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
+ },
+ .tbls_hs_g4 = {
+ .serdes = sm8550_ufsphy_g4_serdes,
+ .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
+ .tx = sm8550_ufsphy_g4_tx,
+ .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
+ .rx = sm8550_ufsphy_g4_rx,
+ .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
+ .pcs = sm8550_ufsphy_g4_pcs,
+ .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
+ },
+ .tbls_hs_g5 = {
+ .serdes = sm8550_ufsphy_g5_serdes,
+ .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
+ .rx = sm8550_ufsphy_g5_rx,
+ .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
+ .pcs = sm8550_ufsphy_g5_pcs,
+ .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -1222,14 +1297,25 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
{
qmp_ufs_serdes_init(qmp, &cfg->tbls);
+ if (qmp->submode == UFS_HS_G4)
+ qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
+ else if (qmp->submode == UFS_HS_G5)
+ qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
+
if (qmp->mode == PHY_MODE_UFS_HS_B)
qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
+
qmp_ufs_lanes_init(qmp, &cfg->tbls);
if (qmp->submode == UFS_HS_G4)
qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4);
+ else if (qmp->submode == UFS_HS_G5)
+ qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g5);
+
qmp_ufs_pcs_init(qmp, &cfg->tbls);
if (qmp->submode == UFS_HS_G4)
qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4);
+ else if (qmp->submode == UFS_HS_G5)
+ qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g5);
}
static int qmp_ufs_com_init(struct qmp_ufs *qmp)
--
2.7.4
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 86+ messages in thread
* [PATCH v2 7/7] scsi: ufs: ufs-qcom: Add support for UFS device version detection
2023-11-07 4:46 ` Can Guo
` (6 preceding siblings ...)
(?)
@ 2023-11-07 4:46 ` Can Guo
-1 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-07 4:46 UTC (permalink / raw)
To: quic_cang, bvanassche, mani, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen
Cc: linux-scsi, Bao D. Nguyen, Andy Gross, Bjorn Andersson,
Konrad Dybcio, James E.J. Bottomley,
open list:ARM/QUALCOMM SUPPORT, open list
From: "Bao D. Nguyen" <quic_nguyenb@quicinc.com>
A spare register in UFS host controller is used to indicate the UFS device
version. The spare register is populated by bootloader for now, but in
future it will be populated by HW automatically during link startup with
its best efforts in any boot stages prior to Linux.
During host driver init, read the spare register, if it is not populated
with a UFS device version, go ahead with the dual init mechanism. If a UFS
device version is in there, use the UFS device version together with host
controller's HW version to decide the proper PHY gear which should be used
to configure the UFS PHY without going through the second init.
Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
Signed-off-by: Can Guo <quic_cang@quicinc.com>
---
drivers/ufs/host/ufs-qcom.c | 23 ++++++++++++++++++-----
drivers/ufs/host/ufs-qcom.h | 2 ++
2 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 94d34b5..b9f726d 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -1064,6 +1064,7 @@ static void ufs_qcom_set_host_params(struct ufs_hba *hba)
{
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
struct ufs_host_params *host_params = &host->host_params;
+ u32 val, dev_major = 0;
ufshcd_init_host_param(host_params);
@@ -1071,12 +1072,24 @@ static void ufs_qcom_set_host_params(struct ufs_hba *hba)
host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba);
host->phy_gear = host_params->hs_tx_gear;
- /*
- * Power up the PHY using the minimum supported gear (UFS_HS_G2).
- * Switching to max gear will be performed during reinit if supported.
- */
- if (host->hw_ver.major < 0x5)
+ if (host->hw_ver.major < 0x5) {
+ /*
+ * Power up the PHY using the minimum supported gear (UFS_HS_G2).
+ * Switching to max gear will be performed during reinit if supported.
+ */
host->phy_gear = UFS_HS_G2;
+ } else {
+ val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG);
+ dev_major = FIELD_GET(GENMASK(7, 4), val);
+
+ /* UFS device version populated, no need to do init twice */
+ if (dev_major != 0)
+ hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
+
+ /* For UFS 3.1 and older, apply HS-G4 PHY gear to save power */
+ if (dev_major < 0x4 && dev_major > 0)
+ host->phy_gear = UFS_HS_G4;
+ }
}
static void ufs_qcom_set_caps(struct ufs_hba *hba)
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index ab94c54..e33c7c1 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -56,6 +56,8 @@ enum {
UFS_AH8_CFG = 0xFC,
REG_UFS_CFG3 = 0x271C,
+
+ REG_UFS_DEBUG_SPARE_CFG = 0x284C,
};
/* QCOM UFS host controller vendor specific debug registers */
--
2.7.4
^ permalink raw reply related [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-07 4:46 ` Can Guo
@ 2023-11-07 13:18 ` Dmitry Baryshkov
-1 siblings, 0 replies; 86+ messages in thread
From: Dmitry Baryshkov @ 2023-11-07 13:18 UTC (permalink / raw)
To: Can Guo
Cc: quic_cang, bvanassche, mani, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, open list:ARM/QUALCOMM SUPPORT,
open list:GENERIC PHY FRAMEWORK, open list
On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
>
> From: Can Guo <quic_cang@quicinc.com>
>
> On SM8550, two sets of UFS PHY settings are provided, one set is to support
> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> settings are programming different values to different registers, mixing
> the two sets and/or overwriting one set with another set is definitely not
> blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> need to split the two sets into their dedicated tables, and leave only the
> common settings in the .tlbs. To have the PHY programmed with the correct
> set of PHY settings, the submode passed to PHY driver must be either HS-G4
> or HS-G5.
>
> Signed-off-by: Can Guo <quic_cang@quicinc.com>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> 4 files changed, 115 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> index c23d5e4..e563af5 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> @@ -18,6 +18,7 @@
> #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> @@ -27,5 +28,6 @@
> #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
>
> #endif
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> index f420f8f..ef392ce 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> @@ -56,6 +56,8 @@
> #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> #define QSERDES_V6_COM_PLL_IVCO 0xf4
> +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> index 15bcb4b..48f31c8 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> @@ -10,10 +10,20 @@
> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
>
> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> @@ -25,6 +35,8 @@
> #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
>
> #endif
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index 3927eba..e0a01497 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> +
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
Aside from moving these registers to the HS_G4 table, you are also
changing these registers. It makes me think that there was an error in
the original programming sequence.
If that is correct, could you please split the patch into two pieces:
- Fix programming sequence (add proper Fixes tags)
- Split G4 and G5 tables.
> +
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
I see all the MODE1 registers being only present in G4 and G5 tables.
Should they be programmed for the modes lower than G4?
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
> };
>
> static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
> - QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
> };
>
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
> +};
> +
> static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
>
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
> @@ -690,14 +709,46 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
> };
>
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
> +
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
> +};
> +
> static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> - QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> };
>
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
> +};
> +
> struct qmp_ufs_offsets {
> u16 serdes;
> u16 pcs;
> @@ -731,6 +782,8 @@ struct qmp_phy_cfg {
> const struct qmp_phy_cfg_tbls tbls_hs_b;
> /* Additional sequence for HS G4 */
> const struct qmp_phy_cfg_tbls tbls_hs_g4;
> + /* Additional sequence for HS G4 */
> + const struct qmp_phy_cfg_tbls tbls_hs_g5;
>
> /* clock ids to be requested */
> const char * const *clk_list;
> @@ -1157,6 +1210,28 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
> .pcs = sm8550_ufsphy_pcs,
> .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
> },
> + .tbls_hs_b = {
> + .serdes = sm8550_ufsphy_hs_b_serdes,
> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
> + },
> + .tbls_hs_g4 = {
> + .serdes = sm8550_ufsphy_g4_serdes,
> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
> + .tx = sm8550_ufsphy_g4_tx,
> + .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
> + .rx = sm8550_ufsphy_g4_rx,
> + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
> + .pcs = sm8550_ufsphy_g4_pcs,
> + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
> + },
> + .tbls_hs_g5 = {
> + .serdes = sm8550_ufsphy_g5_serdes,
> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
> + .rx = sm8550_ufsphy_g5_rx,
> + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
> + .pcs = sm8550_ufsphy_g5_pcs,
> + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
> + },
> .clk_list = sdm845_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> .vreg_list = qmp_phy_vreg_l,
> @@ -1222,14 +1297,25 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
> static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
> {
> qmp_ufs_serdes_init(qmp, &cfg->tbls);
> + if (qmp->submode == UFS_HS_G4)
> + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> + else if (qmp->submode == UFS_HS_G5)
> + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> +
> if (qmp->mode == PHY_MODE_UFS_HS_B)
> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
> +
> qmp_ufs_lanes_init(qmp, &cfg->tbls);
> if (qmp->submode == UFS_HS_G4)
> qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4);
> + else if (qmp->submode == UFS_HS_G5)
> + qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g5);
> +
> qmp_ufs_pcs_init(qmp, &cfg->tbls);
> if (qmp->submode == UFS_HS_G4)
> qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4);
> + else if (qmp->submode == UFS_HS_G5)
> + qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g5);
> }
>
> static int qmp_ufs_com_init(struct qmp_ufs *qmp)
> --
> 2.7.4
>
>
--
With best wishes
Dmitry
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-07 13:18 ` Dmitry Baryshkov
0 siblings, 0 replies; 86+ messages in thread
From: Dmitry Baryshkov @ 2023-11-07 13:18 UTC (permalink / raw)
To: Can Guo
Cc: quic_cang, bvanassche, mani, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, open list:ARM/QUALCOMM SUPPORT,
open list:GENERIC PHY FRAMEWORK, open list
On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
>
> From: Can Guo <quic_cang@quicinc.com>
>
> On SM8550, two sets of UFS PHY settings are provided, one set is to support
> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> settings are programming different values to different registers, mixing
> the two sets and/or overwriting one set with another set is definitely not
> blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> need to split the two sets into their dedicated tables, and leave only the
> common settings in the .tlbs. To have the PHY programmed with the correct
> set of PHY settings, the submode passed to PHY driver must be either HS-G4
> or HS-G5.
>
> Signed-off-by: Can Guo <quic_cang@quicinc.com>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> 4 files changed, 115 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> index c23d5e4..e563af5 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> @@ -18,6 +18,7 @@
> #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> @@ -27,5 +28,6 @@
> #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
>
> #endif
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> index f420f8f..ef392ce 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> @@ -56,6 +56,8 @@
> #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> #define QSERDES_V6_COM_PLL_IVCO 0xf4
> +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> index 15bcb4b..48f31c8 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> @@ -10,10 +10,20 @@
> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
>
> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> @@ -25,6 +35,8 @@
> #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
>
> #endif
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index 3927eba..e0a01497 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> +
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
Aside from moving these registers to the HS_G4 table, you are also
changing these registers. It makes me think that there was an error in
the original programming sequence.
If that is correct, could you please split the patch into two pieces:
- Fix programming sequence (add proper Fixes tags)
- Split G4 and G5 tables.
> +
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
I see all the MODE1 registers being only present in G4 and G5 tables.
Should they be programmed for the modes lower than G4?
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
> };
>
> static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
> - QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
> };
>
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
> +};
> +
> static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
>
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
> @@ -690,14 +709,46 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
> };
>
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
> +
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
> +};
> +
> static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> - QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> };
>
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
> +};
> +
> struct qmp_ufs_offsets {
> u16 serdes;
> u16 pcs;
> @@ -731,6 +782,8 @@ struct qmp_phy_cfg {
> const struct qmp_phy_cfg_tbls tbls_hs_b;
> /* Additional sequence for HS G4 */
> const struct qmp_phy_cfg_tbls tbls_hs_g4;
> + /* Additional sequence for HS G4 */
> + const struct qmp_phy_cfg_tbls tbls_hs_g5;
>
> /* clock ids to be requested */
> const char * const *clk_list;
> @@ -1157,6 +1210,28 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
> .pcs = sm8550_ufsphy_pcs,
> .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
> },
> + .tbls_hs_b = {
> + .serdes = sm8550_ufsphy_hs_b_serdes,
> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
> + },
> + .tbls_hs_g4 = {
> + .serdes = sm8550_ufsphy_g4_serdes,
> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
> + .tx = sm8550_ufsphy_g4_tx,
> + .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
> + .rx = sm8550_ufsphy_g4_rx,
> + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
> + .pcs = sm8550_ufsphy_g4_pcs,
> + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
> + },
> + .tbls_hs_g5 = {
> + .serdes = sm8550_ufsphy_g5_serdes,
> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
> + .rx = sm8550_ufsphy_g5_rx,
> + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
> + .pcs = sm8550_ufsphy_g5_pcs,
> + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
> + },
> .clk_list = sdm845_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> .vreg_list = qmp_phy_vreg_l,
> @@ -1222,14 +1297,25 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
> static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
> {
> qmp_ufs_serdes_init(qmp, &cfg->tbls);
> + if (qmp->submode == UFS_HS_G4)
> + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> + else if (qmp->submode == UFS_HS_G5)
> + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> +
> if (qmp->mode == PHY_MODE_UFS_HS_B)
> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
> +
> qmp_ufs_lanes_init(qmp, &cfg->tbls);
> if (qmp->submode == UFS_HS_G4)
> qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4);
> + else if (qmp->submode == UFS_HS_G5)
> + qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g5);
> +
> qmp_ufs_pcs_init(qmp, &cfg->tbls);
> if (qmp->submode == UFS_HS_G4)
> qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4);
> + else if (qmp->submode == UFS_HS_G5)
> + qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g5);
> }
>
> static int qmp_ufs_com_init(struct qmp_ufs *qmp)
> --
> 2.7.4
>
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 1/7] scsi: ufs: host: Rename structure ufs_dev_params to ufs_host_params
2023-11-07 4:46 ` Can Guo
@ 2023-11-07 19:36 ` Andrew Halaney
-1 siblings, 0 replies; 86+ messages in thread
From: Andrew Halaney @ 2023-11-07 19:36 UTC (permalink / raw)
To: Can Guo
Cc: quic_cang, bvanassche, mani, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Alim Akhtar, James E.J. Bottomley, Krzysztof Kozlowski,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Matthias Brugger,
AngeloGioacchino Del Regno, Uwe Kleine-König, Brian Masney,
moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES,
open list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES,
open list,
moderated list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...,
open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...
On Mon, Nov 06, 2023 at 08:46:07PM -0800, Can Guo wrote:
> From: Can Guo <quic_cang@quicinc.com>
>
> Structure ufs_dev_params is actually used in UFS host vendor drivers to
> declare host specific power mode parameters, like ufs_<vendor>_params or
> host_cap, which makes the code not very straightforward to read. Rename the
> structure ufs_dev_params to ufs_host_params and unify the declarations in
> all vendor drivers to host_params.
>
> In addition, rename the two functions ufshcd_init_dev_pwr_param() and
nit: s/ufshcd_init_dev_pwr_param/ufshcd_init_pwr_dev_param/
> ufshcd_get_dev_pwr_param() which work based on the ufs_host_params to
nit: s/ufshcd_get_dev_pwr_param/ufshcd_get_pwr_dev_param/
> ufshcd_init_host_param() and ufshcd_negotiate_pwr_param() respectively to
> avoid confusions.
>
> This change does not change any functionalities or logic.
>
> Signed-off-by: Can Guo <quic_cang@quicinc.com>
> ---
> drivers/ufs/host/ufs-exynos.c | 7 +++---
> drivers/ufs/host/ufs-hisi.c | 11 ++++-----
> drivers/ufs/host/ufs-mediatek.c | 12 ++++------
> drivers/ufs/host/ufs-qcom.c | 12 ++++------
> drivers/ufs/host/ufshcd-pltfrm.c | 49 ++++++++++++++++++++--------------------
> drivers/ufs/host/ufshcd-pltfrm.h | 10 ++++----
> 6 files changed, 47 insertions(+), 54 deletions(-)
>
<snip>
> diff --git a/drivers/ufs/host/ufshcd-pltfrm.c b/drivers/ufs/host/ufshcd-pltfrm.c
> index da2558e..6e65b61 100644
> --- a/drivers/ufs/host/ufshcd-pltfrm.c
> +++ b/drivers/ufs/host/ufshcd-pltfrm.c
> @@ -285,17 +285,17 @@ static int ufshcd_parse_operating_points(struct ufs_hba *hba)
> }
>
> /**
> - * ufshcd_get_pwr_dev_param - get finally agreed attributes for
> + * ufshcd_negotiate_pwr_param - get finally agreed attributes for
> * power mode change
> - * @pltfrm_param: pointer to platform parameters
> + * @host_param: pointer to platform parameters
> * @dev_max: pointer to device attributes
> * @agreed_pwr: returned agreed attributes
> *
> * Return: 0 on success, non-zero value on failure.
> */
> -int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
> - const struct ufs_pa_layer_attr *dev_max,
> - struct ufs_pa_layer_attr *agreed_pwr)
> +int ufshcd_negotiate_pwr_param(const struct ufs_host_params *host_param,
> + const struct ufs_pa_layer_attr *dev_max,
> + struct ufs_pa_layer_attr *agreed_pwr)
> {
> int min_pltfrm_gear;
If you're going to change pltfrm -> host, maybe do so for
min_pltfrm_gear too? I think this all reads nicer with the functions
changed as is, but the consistency would be nice in my opinion.
Outside of those nits, I think this reads nicer now as well.
Acked-by: Andrew Halaney <ahalaney@redhat.com>
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 1/7] scsi: ufs: host: Rename structure ufs_dev_params to ufs_host_params
@ 2023-11-07 19:36 ` Andrew Halaney
0 siblings, 0 replies; 86+ messages in thread
From: Andrew Halaney @ 2023-11-07 19:36 UTC (permalink / raw)
To: Can Guo
Cc: quic_cang, bvanassche, mani, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Alim Akhtar, James E.J. Bottomley, Krzysztof Kozlowski,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Matthias Brugger,
AngeloGioacchino Del Regno, Uwe Kleine-König, Brian Masney,
moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES,
open list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES,
open list,
moderated list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...,
open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...
On Mon, Nov 06, 2023 at 08:46:07PM -0800, Can Guo wrote:
> From: Can Guo <quic_cang@quicinc.com>
>
> Structure ufs_dev_params is actually used in UFS host vendor drivers to
> declare host specific power mode parameters, like ufs_<vendor>_params or
> host_cap, which makes the code not very straightforward to read. Rename the
> structure ufs_dev_params to ufs_host_params and unify the declarations in
> all vendor drivers to host_params.
>
> In addition, rename the two functions ufshcd_init_dev_pwr_param() and
nit: s/ufshcd_init_dev_pwr_param/ufshcd_init_pwr_dev_param/
> ufshcd_get_dev_pwr_param() which work based on the ufs_host_params to
nit: s/ufshcd_get_dev_pwr_param/ufshcd_get_pwr_dev_param/
> ufshcd_init_host_param() and ufshcd_negotiate_pwr_param() respectively to
> avoid confusions.
>
> This change does not change any functionalities or logic.
>
> Signed-off-by: Can Guo <quic_cang@quicinc.com>
> ---
> drivers/ufs/host/ufs-exynos.c | 7 +++---
> drivers/ufs/host/ufs-hisi.c | 11 ++++-----
> drivers/ufs/host/ufs-mediatek.c | 12 ++++------
> drivers/ufs/host/ufs-qcom.c | 12 ++++------
> drivers/ufs/host/ufshcd-pltfrm.c | 49 ++++++++++++++++++++--------------------
> drivers/ufs/host/ufshcd-pltfrm.h | 10 ++++----
> 6 files changed, 47 insertions(+), 54 deletions(-)
>
<snip>
> diff --git a/drivers/ufs/host/ufshcd-pltfrm.c b/drivers/ufs/host/ufshcd-pltfrm.c
> index da2558e..6e65b61 100644
> --- a/drivers/ufs/host/ufshcd-pltfrm.c
> +++ b/drivers/ufs/host/ufshcd-pltfrm.c
> @@ -285,17 +285,17 @@ static int ufshcd_parse_operating_points(struct ufs_hba *hba)
> }
>
> /**
> - * ufshcd_get_pwr_dev_param - get finally agreed attributes for
> + * ufshcd_negotiate_pwr_param - get finally agreed attributes for
> * power mode change
> - * @pltfrm_param: pointer to platform parameters
> + * @host_param: pointer to platform parameters
> * @dev_max: pointer to device attributes
> * @agreed_pwr: returned agreed attributes
> *
> * Return: 0 on success, non-zero value on failure.
> */
> -int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
> - const struct ufs_pa_layer_attr *dev_max,
> - struct ufs_pa_layer_attr *agreed_pwr)
> +int ufshcd_negotiate_pwr_param(const struct ufs_host_params *host_param,
> + const struct ufs_pa_layer_attr *dev_max,
> + struct ufs_pa_layer_attr *agreed_pwr)
> {
> int min_pltfrm_gear;
If you're going to change pltfrm -> host, maybe do so for
min_pltfrm_gear too? I think this all reads nicer with the functions
changed as is, but the consistency would be nice in my opinion.
Outside of those nits, I think this reads nicer now as well.
Acked-by: Andrew Halaney <ahalaney@redhat.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 2/7] scsi: ufs: ufs-qcom: Setup host power mode during init
2023-11-07 4:46 ` [PATCH v2 2/7] scsi: ufs: ufs-qcom: Setup host power mode during init Can Guo
@ 2023-11-07 20:14 ` Andrew Halaney
2023-11-08 7:47 ` Can Guo
2023-11-08 5:07 ` Manivannan Sadhasivam
1 sibling, 1 reply; 86+ messages in thread
From: Andrew Halaney @ 2023-11-07 20:14 UTC (permalink / raw)
To: Can Guo
Cc: quic_cang, bvanassche, mani, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Bao D . Nguyen, Andy Gross, Bjorn Andersson, Konrad Dybcio,
James E.J. Bottomley, open list:ARM/QUALCOMM SUPPORT, open list
On Mon, Nov 06, 2023 at 08:46:08PM -0800, Can Guo wrote:
> From: Can Guo <quic_cang@quicinc.com>
>
> Setup host power mode and its limitations during UFS host driver init to
> avoid repetitive work during every power mode change.
>
> Co-developed-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
> Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
> Signed-off-by: Can Guo <quic_cang@quicinc.com>
> ---
> drivers/ufs/host/ufs-qcom.c | 22 ++++++++++++++--------
> drivers/ufs/host/ufs-qcom.h | 1 +
> 2 files changed, 15 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index aee66a3..cc0eb37 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -898,7 +898,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
> struct ufs_pa_layer_attr *dev_req_params)
> {
> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> - struct ufs_host_params host_params;
> + struct ufs_host_params *host_params = &host->host_params;
> int ret = 0;
>
> if (!dev_req_params) {
> @@ -908,13 +908,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
>
> switch (status) {
> case PRE_CHANGE:
> - ufshcd_init_host_param(&host_params);
> - host_params.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
You drop the setting of hs_rate in your new function. It seems setting that's
also overkill since UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B. hs_rate is
already set to that in ufshcd_init_host_param(), so removing it makes
sense.
Can you remove it prior in its own patch, and remove the now unused
UFS_QCOM_LIMIT_HS_RATE as well from ufs-qcom.h?
With that in place this seems like a good improvement:
Acked-by: Andrew Halaney <ahalaney@redhat.com>
> -
> - /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
> - host_params.hs_tx_gear = host_params.hs_rx_gear = ufs_qcom_get_hs_gear(hba);
> -
> - ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
> + ret = ufshcd_negotiate_pwr_param(host_params, dev_max_params, dev_req_params);
> if (ret) {
> dev_err(hba->dev, "%s: failed to determine capabilities\n",
> __func__);
> @@ -1049,6 +1043,17 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
> hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
> }
>
> +static void ufs_qcom_set_host_params(struct ufs_hba *hba)
> +{
> + struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> + struct ufs_host_params *host_params = &host->host_params;
> +
> + ufshcd_init_host_param(host_params);
> +
> + /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
> + host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba);
> +}
> +
> static void ufs_qcom_set_caps(struct ufs_hba *hba)
> {
> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> @@ -1273,6 +1278,7 @@ static int ufs_qcom_init(struct ufs_hba *hba)
>
> ufs_qcom_set_caps(hba);
> ufs_qcom_advertise_quirks(hba);
> + ufs_qcom_set_host_params(hba);
>
> err = ufs_qcom_ice_init(host);
> if (err)
> diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
> index 9950a00..ab94c54 100644
> --- a/drivers/ufs/host/ufs-qcom.h
> +++ b/drivers/ufs/host/ufs-qcom.h
> @@ -240,6 +240,7 @@ struct ufs_qcom_host {
>
> struct gpio_desc *device_reset;
>
> + struct ufs_host_params host_params;
> u32 phy_gear;
>
> bool esi_enabled;
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 1/7] scsi: ufs: host: Rename structure ufs_dev_params to ufs_host_params
2023-11-07 4:46 ` Can Guo
@ 2023-11-07 20:56 ` Bart Van Assche
-1 siblings, 0 replies; 86+ messages in thread
From: Bart Van Assche @ 2023-11-07 20:56 UTC (permalink / raw)
To: Can Guo, quic_cang, mani, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen
Cc: linux-scsi, Alim Akhtar, James E.J. Bottomley,
Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Matthias Brugger, AngeloGioacchino Del Regno,
Uwe Kleine-König, Brian Masney,
moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES,
open list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES,
open list,
moderated list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...,
open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...
On 11/6/23 20:46, Can Guo wrote:
> /**
> - * ufshcd_get_pwr_dev_param - get finally agreed attributes for
> + * ufshcd_negotiate_pwr_param - get finally agreed attributes for
> * power mode change
Since you are renaming the function, please also change the description
of the function into something more meaningful, e.g. "find power mode
settings that are supported by both the controller and the device".
> - * @pltfrm_param: pointer to platform parameters
> + * @host_param: pointer to platform parameters
Please make sure that the argument name and argument description are in
sync.
Thanks,
Bart.
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 1/7] scsi: ufs: host: Rename structure ufs_dev_params to ufs_host_params
@ 2023-11-07 20:56 ` Bart Van Assche
0 siblings, 0 replies; 86+ messages in thread
From: Bart Van Assche @ 2023-11-07 20:56 UTC (permalink / raw)
To: Can Guo, quic_cang, mani, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen
Cc: linux-scsi, Alim Akhtar, James E.J. Bottomley,
Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Matthias Brugger, AngeloGioacchino Del Regno,
Uwe Kleine-König, Brian Masney,
moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES,
open list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES,
open list,
moderated list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...,
open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...
On 11/6/23 20:46, Can Guo wrote:
> /**
> - * ufshcd_get_pwr_dev_param - get finally agreed attributes for
> + * ufshcd_negotiate_pwr_param - get finally agreed attributes for
> * power mode change
Since you are renaming the function, please also change the description
of the function into something more meaningful, e.g. "find power mode
settings that are supported by both the controller and the device".
> - * @pltfrm_param: pointer to platform parameters
> + * @host_param: pointer to platform parameters
Please make sure that the argument name and argument description are in
sync.
Thanks,
Bart.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 2/7] scsi: ufs: ufs-qcom: Setup host power mode during init
2023-11-07 4:46 ` [PATCH v2 2/7] scsi: ufs: ufs-qcom: Setup host power mode during init Can Guo
2023-11-07 20:14 ` Andrew Halaney
@ 2023-11-08 5:07 ` Manivannan Sadhasivam
2023-11-08 8:07 ` Can Guo
1 sibling, 1 reply; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-08 5:07 UTC (permalink / raw)
To: Can Guo
Cc: quic_cang, bvanassche, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Bao D . Nguyen, Andy Gross, Bjorn Andersson, Konrad Dybcio,
James E.J. Bottomley, open list:ARM/QUALCOMM SUPPORT, open list
On Mon, Nov 06, 2023 at 08:46:08PM -0800, Can Guo wrote:
> From: Can Guo <quic_cang@quicinc.com>
>
> Setup host power mode and its limitations during UFS host driver init to
> avoid repetitive work during every power mode change.
>
> Co-developed-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
> Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
> Signed-off-by: Can Guo <quic_cang@quicinc.com>
> ---
> drivers/ufs/host/ufs-qcom.c | 22 ++++++++++++++--------
> drivers/ufs/host/ufs-qcom.h | 1 +
> 2 files changed, 15 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index aee66a3..cc0eb37 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -898,7 +898,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
> struct ufs_pa_layer_attr *dev_req_params)
> {
> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> - struct ufs_host_params host_params;
> + struct ufs_host_params *host_params = &host->host_params;
> int ret = 0;
>
> if (!dev_req_params) {
> @@ -908,13 +908,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
>
> switch (status) {
> case PRE_CHANGE:
> - ufshcd_init_host_param(&host_params);
> - host_params.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
As Andrew spotted, this gets removed without explanation. So, I'd also suggest
doing it in a separate patch.
- Mani
> -
> - /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
> - host_params.hs_tx_gear = host_params.hs_rx_gear = ufs_qcom_get_hs_gear(hba);
> -
> - ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
> + ret = ufshcd_negotiate_pwr_param(host_params, dev_max_params, dev_req_params);
> if (ret) {
> dev_err(hba->dev, "%s: failed to determine capabilities\n",
> __func__);
> @@ -1049,6 +1043,17 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
> hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
> }
>
> +static void ufs_qcom_set_host_params(struct ufs_hba *hba)
> +{
> + struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> + struct ufs_host_params *host_params = &host->host_params;
> +
> + ufshcd_init_host_param(host_params);
> +
> + /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
> + host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba);
> +}
> +
> static void ufs_qcom_set_caps(struct ufs_hba *hba)
> {
> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> @@ -1273,6 +1278,7 @@ static int ufs_qcom_init(struct ufs_hba *hba)
>
> ufs_qcom_set_caps(hba);
> ufs_qcom_advertise_quirks(hba);
> + ufs_qcom_set_host_params(hba);
>
> err = ufs_qcom_ice_init(host);
> if (err)
> diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
> index 9950a00..ab94c54 100644
> --- a/drivers/ufs/host/ufs-qcom.h
> +++ b/drivers/ufs/host/ufs-qcom.h
> @@ -240,6 +240,7 @@ struct ufs_qcom_host {
>
> struct gpio_desc *device_reset;
>
> + struct ufs_host_params host_params;
> u32 phy_gear;
>
> bool esi_enabled;
> --
> 2.7.4
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 0/7] Enable HS-G5 support on SM8550
2023-11-07 4:46 ` Can Guo
@ 2023-11-08 5:11 ` Manivannan Sadhasivam
-1 siblings, 0 replies; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-08 5:11 UTC (permalink / raw)
To: Can Guo
Cc: quic_cang, bvanassche, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Matthias Brugger, AngeloGioacchino Del Regno,
open list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support
On Mon, Nov 06, 2023 at 08:46:06PM -0800, Can Guo wrote:
> This series enables HS-G5 support on SM8550.
>
> This series is rebased on below changes from Mani -
> https://patchwork.kernel.org/project/linux-scsi/patch/20230908145329.154024-1-manivannan.sadhasivam@linaro.org/
> https://patchwork.kernel.org/project/linux-scsi/patch/20230908145329.154024-2-manivannan.sadhasivam@linaro.org/
>
> This series is tested on below HW combinations -
> SM8550 MTP + UFS4.0
> SM8550 QRD + UFS3.1
> SM8450 MTP + UFS3.1 (for regression test)
>
You are sending the patches from QTI email and that's not supposed to happen I
believe.
- Mani
> v1 -> v2:
> 1. Removed 2 changes which were exposing power info in sysfs
> 2. Removed 1 change which was moving data structs to phy-qcom-qmp-ufs.h
> 3. Added one new change (the 1st one) to clean up usage of ufs_dev_params based on comments from Mani
> 4. Adjusted the logic of UFS device version detection according to comments from Mani:
> 4.1 For HW version < 0x5, go through dual init
> 4.2 For HW version >= 0x5
> a. If UFS device version is populated, one init is required
> b. If UFS device version is not populated, go through dual init
>
> Bao D. Nguyen (1):
> scsi: ufs: ufs-qcom: Add support for UFS device version detection
>
> Can Guo (6):
> scsi: ufs: host: Rename structure ufs_dev_params to ufs_host_params
> scsi: ufs: ufs-qcom: Setup host power mode during init
> scsi: ufs: ufs-qcom: Allow the first init start with the maximum
> supported gear
> scsi: ufs: ufs-qcom: Limit HS-G5 Rate-A to hosts with HW version 5
> scsi: ufs: ufs-qcom: Set initial PHY gear to max HS gear for HW ver 5
> and newer
> phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for
> SM8550
>
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> drivers/ufs/host/ufs-exynos.c | 7 +-
> drivers/ufs/host/ufs-hisi.c | 11 +-
> drivers/ufs/host/ufs-mediatek.c | 12 +--
> drivers/ufs/host/ufs-qcom.c | 78 ++++++++++----
> drivers/ufs/host/ufs-qcom.h | 3 +
> drivers/ufs/host/ufshcd-pltfrm.c | 49 +++++----
> drivers/ufs/host/ufshcd-pltfrm.h | 10 +-
> 11 files changed, 217 insertions(+), 81 deletions(-)
>
> --
> 2.7.4
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 0/7] Enable HS-G5 support on SM8550
@ 2023-11-08 5:11 ` Manivannan Sadhasivam
0 siblings, 0 replies; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-08 5:11 UTC (permalink / raw)
To: Can Guo
Cc: quic_cang, bvanassche, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Matthias Brugger, AngeloGioacchino Del Regno,
open list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support
On Mon, Nov 06, 2023 at 08:46:06PM -0800, Can Guo wrote:
> This series enables HS-G5 support on SM8550.
>
> This series is rebased on below changes from Mani -
> https://patchwork.kernel.org/project/linux-scsi/patch/20230908145329.154024-1-manivannan.sadhasivam@linaro.org/
> https://patchwork.kernel.org/project/linux-scsi/patch/20230908145329.154024-2-manivannan.sadhasivam@linaro.org/
>
> This series is tested on below HW combinations -
> SM8550 MTP + UFS4.0
> SM8550 QRD + UFS3.1
> SM8450 MTP + UFS3.1 (for regression test)
>
You are sending the patches from QTI email and that's not supposed to happen I
believe.
- Mani
> v1 -> v2:
> 1. Removed 2 changes which were exposing power info in sysfs
> 2. Removed 1 change which was moving data structs to phy-qcom-qmp-ufs.h
> 3. Added one new change (the 1st one) to clean up usage of ufs_dev_params based on comments from Mani
> 4. Adjusted the logic of UFS device version detection according to comments from Mani:
> 4.1 For HW version < 0x5, go through dual init
> 4.2 For HW version >= 0x5
> a. If UFS device version is populated, one init is required
> b. If UFS device version is not populated, go through dual init
>
> Bao D. Nguyen (1):
> scsi: ufs: ufs-qcom: Add support for UFS device version detection
>
> Can Guo (6):
> scsi: ufs: host: Rename structure ufs_dev_params to ufs_host_params
> scsi: ufs: ufs-qcom: Setup host power mode during init
> scsi: ufs: ufs-qcom: Allow the first init start with the maximum
> supported gear
> scsi: ufs: ufs-qcom: Limit HS-G5 Rate-A to hosts with HW version 5
> scsi: ufs: ufs-qcom: Set initial PHY gear to max HS gear for HW ver 5
> and newer
> phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for
> SM8550
>
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> drivers/ufs/host/ufs-exynos.c | 7 +-
> drivers/ufs/host/ufs-hisi.c | 11 +-
> drivers/ufs/host/ufs-mediatek.c | 12 +--
> drivers/ufs/host/ufs-qcom.c | 78 ++++++++++----
> drivers/ufs/host/ufs-qcom.h | 3 +
> drivers/ufs/host/ufshcd-pltfrm.c | 49 +++++----
> drivers/ufs/host/ufshcd-pltfrm.h | 10 +-
> 11 files changed, 217 insertions(+), 81 deletions(-)
>
> --
> 2.7.4
>
--
மணிவண்ணன் சதாசிவம்
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 3/7] scsi: ufs: ufs-qcom: Allow the first init start with the maximum supported gear
2023-11-07 4:46 ` [PATCH v2 3/7] scsi: ufs: ufs-qcom: Allow the first init start with the maximum supported gear Can Guo
@ 2023-11-08 5:23 ` Manivannan Sadhasivam
2023-11-08 8:21 ` Can Guo
0 siblings, 1 reply; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-08 5:23 UTC (permalink / raw)
To: Can Guo
Cc: quic_cang, bvanassche, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, James E.J. Bottomley,
open list:ARM/QUALCOMM SUPPORT, open list
On Mon, Nov 06, 2023 at 08:46:09PM -0800, Can Guo wrote:
> From: Can Guo <quic_cang@quicinc.com>
>
> During host driver init, the phy_gear is set to the minimum supported gear
> (HS_G2). Then, during the first power mode change, the negotiated gear, say
> HS-G4, is updated to the phy_gear variable so that in the second init the
> updated phy_gear can be used to program the PHY.
>
> But the current code only allows update the phy_gear to a higher value. If
> one wants to start the first init with the maximum support gear, say HS-G4,
> the phy_gear is not updated to HS-G3 if the device only supports HS-G3.
>
Can you elaborate when this can happen? AFAICS, there are 3 possibilities of
initial phy gear with this series:
1. If ufshc is < 5.0, then G2 will be used.
2. If ufshc is >= 5.0 and if the version is populated in register, then that
gear will be used. Most likely that gear can be G4/G5 depending on the device
connected.
3. If ufshc is >=5.0 and version is not populated, then G4 will be used.
In all the above cases, I do not see any necessity to switch the phy gear
setting to lower one while scaling. Since the gears are backwards compatible,
we always use one phy gear sequence. Moreover, we only have 2 init sequences.
Please correct me if I'm missing anything.
- Mani
> The original check added there is intend to make sure the phy_gear won't be
> updated when gear is scaled down (during clock scaling). Update the check
> so that one can start the first init with the maximum support gear without
> breaking the original fix by checking the ufshcd_state, that is, allow
> update to phy_gear only if power mode change is invoked from
> ufshcd_probe_hba().
>
> This change is a preparation patch for the next patches in the same series.
>
> Signed-off-by: Can Guo <quic_cang@quicinc.com>
> ---
> drivers/ufs/host/ufs-qcom.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index cc0eb37..60b35ca 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -916,11 +916,12 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
> }
>
> /*
> - * Update phy_gear only when the gears are scaled to a higher value. This is
> - * because, the PHY gear settings are backwards compatible and we only need to
> - * change the PHY gear settings while scaling to higher gears.
> + * During UFS driver probe, always update the PHY gear to match the negotiated
> + * gear, so that, if quirk UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is enabled,
> + * the second init can program the optimal PHY settings. This allows one to start
> + * the first init with either the minimum or the maximum support gear.
> */
> - if (dev_req_params->gear_tx > host->phy_gear)
> + if (hba->ufshcd_state == UFSHCD_STATE_RESET)
> host->phy_gear = dev_req_params->gear_tx;
>
> /* enable the device ref clock before changing to HS mode */
> --
> 2.7.4
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 4/7] scsi: ufs: ufs-qcom: Limit HS-G5 Rate-A to hosts with HW version 5
2023-11-07 4:46 ` [PATCH v2 4/7] scsi: ufs: ufs-qcom: Limit HS-G5 Rate-A to hosts with HW version 5 Can Guo
@ 2023-11-08 5:25 ` Manivannan Sadhasivam
2023-11-08 8:42 ` Can Guo
0 siblings, 1 reply; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-08 5:25 UTC (permalink / raw)
To: Can Guo
Cc: quic_cang, bvanassche, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, James E.J. Bottomley,
open list:ARM/QUALCOMM SUPPORT, open list
On Mon, Nov 06, 2023 at 08:46:10PM -0800, Can Guo wrote:
> From: Can Guo <quic_cang@quicinc.com>
>
> Qcom UFS hosts, with HW ver 5, can only support up to HS-G5 Rate-A due to
> HW limitations. If the HS-G5 PHY gear is used, update host_params->hs_rate
> to Rate-A, so that the subsequent power mode changes shall stick to Rate-A.
>
> Signed-off-by: Can Guo <quic_cang@quicinc.com>
> ---
> drivers/ufs/host/ufs-qcom.c | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index 60b35ca..55ee31d 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -442,9 +442,25 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
> static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> {
> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> + struct ufs_host_params *host_params = &host->host_params;
> struct phy *phy = host->generic_phy;
> + enum phy_mode mode;
> int ret;
>
> + /*
> + * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations.
Does this limitation apply to future targets as well or just to SM8550? If
it's the latter, then we need to use a flag.
- Mani
> + * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A,
> + * so that the subsequent power mode change shall stick to Rate-A.
> + */
> + if (host->hw_ver.major == 0x5) {
> + if (host->phy_gear == UFS_HS_G5)
> + host_params->hs_rate = PA_HS_MODE_A;
> + else
> + host_params->hs_rate = PA_HS_MODE_B;
> + }
> +
> + mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A;
> +
> /* Reset UFS Host Controller and PHY */
> ret = ufs_qcom_host_reset(hba);
> if (ret)
> @@ -459,7 +475,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> return ret;
> }
>
> - phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);
> + phy_set_mode_ext(phy, mode, host->phy_gear);
>
> /* power on phy - start serdes and phy's power and clocks */
> ret = phy_power_on(phy);
> --
> 2.7.4
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 5/7] scsi: ufs: ufs-qcom: Set initial PHY gear to max HS gear for HW ver 5 and newer
2023-11-07 4:46 ` [PATCH v2 5/7] scsi: ufs: ufs-qcom: Set initial PHY gear to max HS gear for HW ver 5 and newer Can Guo
@ 2023-11-08 5:34 ` Manivannan Sadhasivam
2023-11-08 8:46 ` Can Guo
0 siblings, 1 reply; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-08 5:34 UTC (permalink / raw)
To: Can Guo
Cc: quic_cang, bvanassche, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, James E.J. Bottomley,
open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...,
open list
On Mon, Nov 06, 2023 at 08:46:11PM -0800, Can Guo wrote:
> From: Can Guo <quic_cang@quicinc.com>
>
> Set the initial PHY gear to max HS gear for hosts with HW ver 5 and newer.
>
How about,
"For UFSHC >= 5.0, set the initial PHY gear based on the gear value returned by
ufs_qcom_get_hs_gear(). For the rest, use the existing default value of G2."
> This patch is not changing any functionalities or logic but only a
> preparation patch for the next patch in this series.
>
You are also moving the default phy_gear code to ufs_qcom_set_host_params(). So
it should be mentioned in the commit message.
> Signed-off-by: Can Guo <quic_cang@quicinc.com>
> ---
> drivers/ufs/host/ufs-qcom.c | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index 55ee31d..94d34b5 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -1069,6 +1069,14 @@ static void ufs_qcom_set_host_params(struct ufs_hba *hba)
>
> /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
> host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba);
> + host->phy_gear = host_params->hs_tx_gear;
> +
> + /*
> + * Power up the PHY using the minimum supported gear (UFS_HS_G2).
> + * Switching to max gear will be performed during reinit if supported.
> + */
This comment should be moved inside the "if" condition here as done in the next
patch.
- Mani
> + if (host->hw_ver.major < 0x5)
> + host->phy_gear = UFS_HS_G2;
> }
>
> static void ufs_qcom_set_caps(struct ufs_hba *hba)
> @@ -1313,12 +1321,6 @@ static int ufs_qcom_init(struct ufs_hba *hba)
> dev_warn(dev, "%s: failed to configure the testbus %d\n",
> __func__, err);
>
> - /*
> - * Power up the PHY using the minimum supported gear (UFS_HS_G2).
> - * Switching to max gear will be performed during reinit if supported.
> - */
> - host->phy_gear = UFS_HS_G2;
> -
> return 0;
>
> out_variant_clear:
> --
> 2.7.4
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-07 13:18 ` Dmitry Baryshkov
@ 2023-11-08 5:49 ` Manivannan Sadhasivam
-1 siblings, 0 replies; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-08 5:49 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Can Guo, quic_cang, bvanassche, stanley.chu, adrian.hunter,
beanhuo, avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, open list:ARM/QUALCOMM SUPPORT,
open list:GENERIC PHY FRAMEWORK, open list
On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> >
> > From: Can Guo <quic_cang@quicinc.com>
> >
> > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > settings are programming different values to different registers, mixing
> > the two sets and/or overwriting one set with another set is definitely not
> > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > need to split the two sets into their dedicated tables, and leave only the
> > common settings in the .tlbs. To have the PHY programmed with the correct
> > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > or HS-G5.
> >
You should also mention that this issue is also present in G4 supported targets.
And a note that it will get fixed later.
> > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > ---
> > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > 4 files changed, 115 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > index c23d5e4..e563af5 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > @@ -18,6 +18,7 @@
> > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > @@ -27,5 +28,6 @@
> > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> >
> > #endif
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > index f420f8f..ef392ce 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > @@ -56,6 +56,8 @@
> > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > index 15bcb4b..48f31c8 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > @@ -10,10 +10,20 @@
> > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> >
> > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > @@ -25,6 +35,8 @@
> > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> >
> > #endif
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > index 3927eba..e0a01497 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > +
> > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
>
> Aside from moving these registers to the HS_G4 table, you are also
> changing these registers. It makes me think that there was an error in
> the original programming sequence.
> If that is correct, could you please split the patch into two pieces:
> - Fix programming sequence (add proper Fixes tags)
> - Split G4 and G5 tables.
Ack
>
> > +
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
>
> I see all the MODE1 registers being only present in G4 and G5 tables.
> Should they be programmed for the modes lower than G4?
>
We use G4 table for all the modes <= G4.
> > +};
> > +
> > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
> > +
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
> > };
> >
> > static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
> > - QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
> > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
> > };
> >
> > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
> > +};
> > +
> > static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
> > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
> > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
> >
> > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
> > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
> > @@ -690,14 +709,46 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
> > };
> >
> > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
> > +
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
> > +};
> > +
> > static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
> > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
> > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
> > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> > - QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> > };
> >
> > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
> > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
> > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
> > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
> > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
> > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
> > +};
> > +
> > struct qmp_ufs_offsets {
> > u16 serdes;
> > u16 pcs;
> > @@ -731,6 +782,8 @@ struct qmp_phy_cfg {
> > const struct qmp_phy_cfg_tbls tbls_hs_b;
> > /* Additional sequence for HS G4 */
> > const struct qmp_phy_cfg_tbls tbls_hs_g4;
> > + /* Additional sequence for HS G4 */
HS G5
> > + const struct qmp_phy_cfg_tbls tbls_hs_g5;
> >
> > /* clock ids to be requested */
> > const char * const *clk_list;
> > @@ -1157,6 +1210,28 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
> > .pcs = sm8550_ufsphy_pcs,
> > .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
> > },
> > + .tbls_hs_b = {
> > + .serdes = sm8550_ufsphy_hs_b_serdes,
> > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
> > + },
> > + .tbls_hs_g4 = {
> > + .serdes = sm8550_ufsphy_g4_serdes,
> > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
> > + .tx = sm8550_ufsphy_g4_tx,
> > + .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
> > + .rx = sm8550_ufsphy_g4_rx,
> > + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
> > + .pcs = sm8550_ufsphy_g4_pcs,
> > + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
> > + },
> > + .tbls_hs_g5 = {
> > + .serdes = sm8550_ufsphy_g5_serdes,
> > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
> > + .rx = sm8550_ufsphy_g5_rx,
> > + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
> > + .pcs = sm8550_ufsphy_g5_pcs,
> > + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
> > + },
> > .clk_list = sdm845_ufs_phy_clk_l,
> > .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> > .vreg_list = qmp_phy_vreg_l,
> > @@ -1222,14 +1297,25 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
> > static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
> > {
> > qmp_ufs_serdes_init(qmp, &cfg->tbls);
> > + if (qmp->submode == UFS_HS_G4)
> > + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > + else if (qmp->submode == UFS_HS_G5)
> > + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> > +
Should we program submode sequence after HS_B?
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-08 5:49 ` Manivannan Sadhasivam
0 siblings, 0 replies; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-08 5:49 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Can Guo, quic_cang, bvanassche, stanley.chu, adrian.hunter,
beanhuo, avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, open list:ARM/QUALCOMM SUPPORT,
open list:GENERIC PHY FRAMEWORK, open list
On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> >
> > From: Can Guo <quic_cang@quicinc.com>
> >
> > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > settings are programming different values to different registers, mixing
> > the two sets and/or overwriting one set with another set is definitely not
> > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > need to split the two sets into their dedicated tables, and leave only the
> > common settings in the .tlbs. To have the PHY programmed with the correct
> > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > or HS-G5.
> >
You should also mention that this issue is also present in G4 supported targets.
And a note that it will get fixed later.
> > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > ---
> > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > 4 files changed, 115 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > index c23d5e4..e563af5 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > @@ -18,6 +18,7 @@
> > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > @@ -27,5 +28,6 @@
> > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> >
> > #endif
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > index f420f8f..ef392ce 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > @@ -56,6 +56,8 @@
> > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > index 15bcb4b..48f31c8 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > @@ -10,10 +10,20 @@
> > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> >
> > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > @@ -25,6 +35,8 @@
> > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> >
> > #endif
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > index 3927eba..e0a01497 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > +
> > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
>
> Aside from moving these registers to the HS_G4 table, you are also
> changing these registers. It makes me think that there was an error in
> the original programming sequence.
> If that is correct, could you please split the patch into two pieces:
> - Fix programming sequence (add proper Fixes tags)
> - Split G4 and G5 tables.
Ack
>
> > +
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
>
> I see all the MODE1 registers being only present in G4 and G5 tables.
> Should they be programmed for the modes lower than G4?
>
We use G4 table for all the modes <= G4.
> > +};
> > +
> > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
> > +
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
> > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
> > };
> >
> > static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
> > - QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
> > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
> > };
> >
> > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
> > +};
> > +
> > static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
> > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
> > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
> >
> > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
> > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
> > @@ -690,14 +709,46 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
> > };
> >
> > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
> > +
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
> > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
> > +};
> > +
> > static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
> > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
> > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
> > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> > - QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> > };
> >
> > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
> > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
> > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
> > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
> > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
> > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
> > +};
> > +
> > struct qmp_ufs_offsets {
> > u16 serdes;
> > u16 pcs;
> > @@ -731,6 +782,8 @@ struct qmp_phy_cfg {
> > const struct qmp_phy_cfg_tbls tbls_hs_b;
> > /* Additional sequence for HS G4 */
> > const struct qmp_phy_cfg_tbls tbls_hs_g4;
> > + /* Additional sequence for HS G4 */
HS G5
> > + const struct qmp_phy_cfg_tbls tbls_hs_g5;
> >
> > /* clock ids to be requested */
> > const char * const *clk_list;
> > @@ -1157,6 +1210,28 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
> > .pcs = sm8550_ufsphy_pcs,
> > .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
> > },
> > + .tbls_hs_b = {
> > + .serdes = sm8550_ufsphy_hs_b_serdes,
> > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
> > + },
> > + .tbls_hs_g4 = {
> > + .serdes = sm8550_ufsphy_g4_serdes,
> > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
> > + .tx = sm8550_ufsphy_g4_tx,
> > + .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
> > + .rx = sm8550_ufsphy_g4_rx,
> > + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
> > + .pcs = sm8550_ufsphy_g4_pcs,
> > + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
> > + },
> > + .tbls_hs_g5 = {
> > + .serdes = sm8550_ufsphy_g5_serdes,
> > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
> > + .rx = sm8550_ufsphy_g5_rx,
> > + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
> > + .pcs = sm8550_ufsphy_g5_pcs,
> > + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
> > + },
> > .clk_list = sdm845_ufs_phy_clk_l,
> > .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> > .vreg_list = qmp_phy_vreg_l,
> > @@ -1222,14 +1297,25 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
> > static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
> > {
> > qmp_ufs_serdes_init(qmp, &cfg->tbls);
> > + if (qmp->submode == UFS_HS_G4)
> > + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > + else if (qmp->submode == UFS_HS_G5)
> > + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> > +
Should we program submode sequence after HS_B?
- Mani
--
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^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-08 5:49 ` Manivannan Sadhasivam
@ 2023-11-08 6:56 ` Dmitry Baryshkov
-1 siblings, 0 replies; 86+ messages in thread
From: Dmitry Baryshkov @ 2023-11-08 6:56 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Can Guo, quic_cang, bvanassche, stanley.chu, adrian.hunter,
beanhuo, avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, open list:ARM/QUALCOMM SUPPORT,
open list:GENERIC PHY FRAMEWORK, open list
On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
>
> On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> > On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> > >
> > > From: Can Guo <quic_cang@quicinc.com>
> > >
> > > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > > settings are programming different values to different registers, mixing
> > > the two sets and/or overwriting one set with another set is definitely not
> > > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > > need to split the two sets into their dedicated tables, and leave only the
> > > common settings in the .tlbs. To have the PHY programmed with the correct
> > > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > > or HS-G5.
> > >
>
> You should also mention that this issue is also present in G4 supported targets.
> And a note that it will get fixed later.
>
> > > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > > ---
> > > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > > 4 files changed, 115 insertions(+), 13 deletions(-)
> > >
> > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > index c23d5e4..e563af5 100644
> > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > @@ -18,6 +18,7 @@
> > > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > > @@ -27,5 +28,6 @@
> > > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> > >
> > > #endif
> > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > index f420f8f..ef392ce 100644
> > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > @@ -56,6 +56,8 @@
> > > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > index 15bcb4b..48f31c8 100644
> > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > @@ -10,10 +10,20 @@
> > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> > >
> > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > > @@ -25,6 +35,8 @@
> > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> > >
> > > #endif
> > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > index 3927eba..e0a01497 100644
> > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > +
> > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > > +};
> > > +
> > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > > +};
> > > +
> > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> >
> > Aside from moving these registers to the HS_G4 table, you are also
> > changing these registers. It makes me think that there was an error in
> > the original programming sequence.
> > If that is correct, could you please split the patch into two pieces:
> > - Fix programming sequence (add proper Fixes tags)
> > - Split G4 and G5 tables.
>
> Ack
>
> >
> > > +
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> >
> > I see all the MODE1 registers being only present in G4 and G5 tables.
> > Should they be programmed for the modes lower than G4?
> >
>
> We use G4 table for all the modes <= G4.
Could you please point me how it's handled?
In the patch I see just:
if (qmp->submode == UFS_HS_G4)
qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
else if (qmp->submode == UFS_HS_G5)
qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
Which looks like two special cases (HS_G4 and HS_G5) and nothing for
anything else.
>
> > > +};
> > > +
> > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
> > > +
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
> > > };
> > >
> > > static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
> > > - QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
> > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
> > > };
> > >
> > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
> > > +};
> > > +
> > > static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> > > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
> > > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
> > > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
> > >
> > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
> > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
> > > @@ -690,14 +709,46 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
> > > };
> > >
> > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> > > +};
> > > +
> > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
> > > +
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
> > > +};
> > > +
> > > static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
> > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
> > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
> > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> > > - QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> > > };
> > >
> > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
> > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
> > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
> > > +};
> > > +
> > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
> > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
> > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
> > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
> > > +};
> > > +
> > > struct qmp_ufs_offsets {
> > > u16 serdes;
> > > u16 pcs;
> > > @@ -731,6 +782,8 @@ struct qmp_phy_cfg {
> > > const struct qmp_phy_cfg_tbls tbls_hs_b;
> > > /* Additional sequence for HS G4 */
> > > const struct qmp_phy_cfg_tbls tbls_hs_g4;
> > > + /* Additional sequence for HS G4 */
>
> HS G5
>
> > > + const struct qmp_phy_cfg_tbls tbls_hs_g5;
> > >
> > > /* clock ids to be requested */
> > > const char * const *clk_list;
> > > @@ -1157,6 +1210,28 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
> > > .pcs = sm8550_ufsphy_pcs,
> > > .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
> > > },
> > > + .tbls_hs_b = {
> > > + .serdes = sm8550_ufsphy_hs_b_serdes,
> > > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
> > > + },
> > > + .tbls_hs_g4 = {
> > > + .serdes = sm8550_ufsphy_g4_serdes,
> > > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
> > > + .tx = sm8550_ufsphy_g4_tx,
> > > + .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
> > > + .rx = sm8550_ufsphy_g4_rx,
> > > + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
> > > + .pcs = sm8550_ufsphy_g4_pcs,
> > > + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
> > > + },
> > > + .tbls_hs_g5 = {
> > > + .serdes = sm8550_ufsphy_g5_serdes,
> > > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
> > > + .rx = sm8550_ufsphy_g5_rx,
> > > + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
> > > + .pcs = sm8550_ufsphy_g5_pcs,
> > > + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
> > > + },
> > > .clk_list = sdm845_ufs_phy_clk_l,
> > > .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> > > .vreg_list = qmp_phy_vreg_l,
> > > @@ -1222,14 +1297,25 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
> > > static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
> > > {
> > > qmp_ufs_serdes_init(qmp, &cfg->tbls);
> > > + if (qmp->submode == UFS_HS_G4)
> > > + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > > + else if (qmp->submode == UFS_HS_G5)
> > > + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> > > +
>
> Should we program submode sequence after HS_B?
>
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-08 6:56 ` Dmitry Baryshkov
0 siblings, 0 replies; 86+ messages in thread
From: Dmitry Baryshkov @ 2023-11-08 6:56 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Can Guo, quic_cang, bvanassche, stanley.chu, adrian.hunter,
beanhuo, avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, open list:ARM/QUALCOMM SUPPORT,
open list:GENERIC PHY FRAMEWORK, open list
On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
>
> On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> > On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> > >
> > > From: Can Guo <quic_cang@quicinc.com>
> > >
> > > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > > settings are programming different values to different registers, mixing
> > > the two sets and/or overwriting one set with another set is definitely not
> > > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > > need to split the two sets into their dedicated tables, and leave only the
> > > common settings in the .tlbs. To have the PHY programmed with the correct
> > > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > > or HS-G5.
> > >
>
> You should also mention that this issue is also present in G4 supported targets.
> And a note that it will get fixed later.
>
> > > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > > ---
> > > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > > 4 files changed, 115 insertions(+), 13 deletions(-)
> > >
> > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > index c23d5e4..e563af5 100644
> > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > @@ -18,6 +18,7 @@
> > > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > > @@ -27,5 +28,6 @@
> > > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> > >
> > > #endif
> > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > index f420f8f..ef392ce 100644
> > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > @@ -56,6 +56,8 @@
> > > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > index 15bcb4b..48f31c8 100644
> > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > @@ -10,10 +10,20 @@
> > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> > >
> > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > > @@ -25,6 +35,8 @@
> > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> > >
> > > #endif
> > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > index 3927eba..e0a01497 100644
> > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > +
> > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > > +};
> > > +
> > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > > +};
> > > +
> > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> >
> > Aside from moving these registers to the HS_G4 table, you are also
> > changing these registers. It makes me think that there was an error in
> > the original programming sequence.
> > If that is correct, could you please split the patch into two pieces:
> > - Fix programming sequence (add proper Fixes tags)
> > - Split G4 and G5 tables.
>
> Ack
>
> >
> > > +
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> >
> > I see all the MODE1 registers being only present in G4 and G5 tables.
> > Should they be programmed for the modes lower than G4?
> >
>
> We use G4 table for all the modes <= G4.
Could you please point me how it's handled?
In the patch I see just:
if (qmp->submode == UFS_HS_G4)
qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
else if (qmp->submode == UFS_HS_G5)
qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
Which looks like two special cases (HS_G4 and HS_G5) and nothing for
anything else.
>
> > > +};
> > > +
> > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
> > > +
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
> > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
> > > };
> > >
> > > static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
> > > - QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
> > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
> > > };
> > >
> > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
> > > +};
> > > +
> > > static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> > > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
> > > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
> > > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
> > >
> > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
> > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
> > > @@ -690,14 +709,46 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
> > > };
> > >
> > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> > > +};
> > > +
> > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
> > > +
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
> > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
> > > +};
> > > +
> > > static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
> > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
> > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
> > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> > > - QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> > > };
> > >
> > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
> > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
> > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
> > > +};
> > > +
> > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
> > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
> > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
> > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
> > > +};
> > > +
> > > struct qmp_ufs_offsets {
> > > u16 serdes;
> > > u16 pcs;
> > > @@ -731,6 +782,8 @@ struct qmp_phy_cfg {
> > > const struct qmp_phy_cfg_tbls tbls_hs_b;
> > > /* Additional sequence for HS G4 */
> > > const struct qmp_phy_cfg_tbls tbls_hs_g4;
> > > + /* Additional sequence for HS G4 */
>
> HS G5
>
> > > + const struct qmp_phy_cfg_tbls tbls_hs_g5;
> > >
> > > /* clock ids to be requested */
> > > const char * const *clk_list;
> > > @@ -1157,6 +1210,28 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
> > > .pcs = sm8550_ufsphy_pcs,
> > > .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
> > > },
> > > + .tbls_hs_b = {
> > > + .serdes = sm8550_ufsphy_hs_b_serdes,
> > > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
> > > + },
> > > + .tbls_hs_g4 = {
> > > + .serdes = sm8550_ufsphy_g4_serdes,
> > > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
> > > + .tx = sm8550_ufsphy_g4_tx,
> > > + .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
> > > + .rx = sm8550_ufsphy_g4_rx,
> > > + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
> > > + .pcs = sm8550_ufsphy_g4_pcs,
> > > + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
> > > + },
> > > + .tbls_hs_g5 = {
> > > + .serdes = sm8550_ufsphy_g5_serdes,
> > > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
> > > + .rx = sm8550_ufsphy_g5_rx,
> > > + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
> > > + .pcs = sm8550_ufsphy_g5_pcs,
> > > + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
> > > + },
> > > .clk_list = sdm845_ufs_phy_clk_l,
> > > .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> > > .vreg_list = qmp_phy_vreg_l,
> > > @@ -1222,14 +1297,25 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
> > > static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
> > > {
> > > qmp_ufs_serdes_init(qmp, &cfg->tbls);
> > > + if (qmp->submode == UFS_HS_G4)
> > > + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > > + else if (qmp->submode == UFS_HS_G5)
> > > + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> > > +
>
> Should we program submode sequence after HS_B?
>
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்
--
With best wishes
Dmitry
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 1/7] scsi: ufs: host: Rename structure ufs_dev_params to ufs_host_params
2023-11-07 19:36 ` Andrew Halaney
@ 2023-11-08 7:44 ` Can Guo
-1 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-08 7:44 UTC (permalink / raw)
To: Andrew Halaney, Can Guo
Cc: bvanassche, mani, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Alim Akhtar, James E.J. Bottomley, Krzysztof Kozlowski,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Matthias Brugger,
AngeloGioacchino Del Regno, Uwe Kleine-König, Brian Masney,
moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES,
open list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES,
open list,
moderated list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...,
open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...
Hi Andrew,
On 11/8/2023 3:36 AM, Andrew Halaney wrote:
> On Mon, Nov 06, 2023 at 08:46:07PM -0800, Can Guo wrote:
>> From: Can Guo <quic_cang@quicinc.com>
>>
>> Structure ufs_dev_params is actually used in UFS host vendor drivers to
>> declare host specific power mode parameters, like ufs_<vendor>_params or
>> host_cap, which makes the code not very straightforward to read. Rename the
>> structure ufs_dev_params to ufs_host_params and unify the declarations in
>> all vendor drivers to host_params.
>>
>> In addition, rename the two functions ufshcd_init_dev_pwr_param() and
> nit: s/ufshcd_init_dev_pwr_param/ufshcd_init_pwr_dev_param/
sure
>
>> ufshcd_get_dev_pwr_param() which work based on the ufs_host_params to
> nit: s/ufshcd_get_dev_pwr_param/ufshcd_get_pwr_dev_param/
sure
>
>> ufshcd_init_host_param() and ufshcd_negotiate_pwr_param() respectively to
>> avoid confusions.
>>
>> This change does not change any functionalities or logic.
>>
>> Signed-off-by: Can Guo <quic_cang@quicinc.com>
>> ---
>> drivers/ufs/host/ufs-exynos.c | 7 +++---
>> drivers/ufs/host/ufs-hisi.c | 11 ++++-----
>> drivers/ufs/host/ufs-mediatek.c | 12 ++++------
>> drivers/ufs/host/ufs-qcom.c | 12 ++++------
>> drivers/ufs/host/ufshcd-pltfrm.c | 49 ++++++++++++++++++++--------------------
>> drivers/ufs/host/ufshcd-pltfrm.h | 10 ++++----
>> 6 files changed, 47 insertions(+), 54 deletions(-)
>>
> <snip>
>
>> diff --git a/drivers/ufs/host/ufshcd-pltfrm.c b/drivers/ufs/host/ufshcd-pltfrm.c
>> index da2558e..6e65b61 100644
>> --- a/drivers/ufs/host/ufshcd-pltfrm.c
>> +++ b/drivers/ufs/host/ufshcd-pltfrm.c
>> @@ -285,17 +285,17 @@ static int ufshcd_parse_operating_points(struct ufs_hba *hba)
>> }
>>
>> /**
>> - * ufshcd_get_pwr_dev_param - get finally agreed attributes for
>> + * ufshcd_negotiate_pwr_param - get finally agreed attributes for
>> * power mode change
>> - * @pltfrm_param: pointer to platform parameters
>> + * @host_param: pointer to platform parameters
>> * @dev_max: pointer to device attributes
>> * @agreed_pwr: returned agreed attributes
>> *
>> * Return: 0 on success, non-zero value on failure.
>> */
>> -int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
>> - const struct ufs_pa_layer_attr *dev_max,
>> - struct ufs_pa_layer_attr *agreed_pwr)
>> +int ufshcd_negotiate_pwr_param(const struct ufs_host_params *host_param,
>> + const struct ufs_pa_layer_attr *dev_max,
>> + struct ufs_pa_layer_attr *agreed_pwr)
>> {
>> int min_pltfrm_gear;
> If you're going to change pltfrm -> host, maybe do so for
> min_pltfrm_gear too? I think this all reads nicer with the functions
> changed as is, but the consistency would be nice in my opinion.
Sure, will address in next version.
>
> Outside of those nits, I think this reads nicer now as well.
>
> Acked-by: Andrew Halaney <ahalaney@redhat.com>
Thanks,
Can Guo
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 1/7] scsi: ufs: host: Rename structure ufs_dev_params to ufs_host_params
@ 2023-11-08 7:44 ` Can Guo
0 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-08 7:44 UTC (permalink / raw)
To: Andrew Halaney, Can Guo
Cc: bvanassche, mani, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Alim Akhtar, James E.J. Bottomley, Krzysztof Kozlowski,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Matthias Brugger,
AngeloGioacchino Del Regno, Uwe Kleine-König, Brian Masney,
moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES,
open list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES,
open list,
moderated list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...,
open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...
Hi Andrew,
On 11/8/2023 3:36 AM, Andrew Halaney wrote:
> On Mon, Nov 06, 2023 at 08:46:07PM -0800, Can Guo wrote:
>> From: Can Guo <quic_cang@quicinc.com>
>>
>> Structure ufs_dev_params is actually used in UFS host vendor drivers to
>> declare host specific power mode parameters, like ufs_<vendor>_params or
>> host_cap, which makes the code not very straightforward to read. Rename the
>> structure ufs_dev_params to ufs_host_params and unify the declarations in
>> all vendor drivers to host_params.
>>
>> In addition, rename the two functions ufshcd_init_dev_pwr_param() and
> nit: s/ufshcd_init_dev_pwr_param/ufshcd_init_pwr_dev_param/
sure
>
>> ufshcd_get_dev_pwr_param() which work based on the ufs_host_params to
> nit: s/ufshcd_get_dev_pwr_param/ufshcd_get_pwr_dev_param/
sure
>
>> ufshcd_init_host_param() and ufshcd_negotiate_pwr_param() respectively to
>> avoid confusions.
>>
>> This change does not change any functionalities or logic.
>>
>> Signed-off-by: Can Guo <quic_cang@quicinc.com>
>> ---
>> drivers/ufs/host/ufs-exynos.c | 7 +++---
>> drivers/ufs/host/ufs-hisi.c | 11 ++++-----
>> drivers/ufs/host/ufs-mediatek.c | 12 ++++------
>> drivers/ufs/host/ufs-qcom.c | 12 ++++------
>> drivers/ufs/host/ufshcd-pltfrm.c | 49 ++++++++++++++++++++--------------------
>> drivers/ufs/host/ufshcd-pltfrm.h | 10 ++++----
>> 6 files changed, 47 insertions(+), 54 deletions(-)
>>
> <snip>
>
>> diff --git a/drivers/ufs/host/ufshcd-pltfrm.c b/drivers/ufs/host/ufshcd-pltfrm.c
>> index da2558e..6e65b61 100644
>> --- a/drivers/ufs/host/ufshcd-pltfrm.c
>> +++ b/drivers/ufs/host/ufshcd-pltfrm.c
>> @@ -285,17 +285,17 @@ static int ufshcd_parse_operating_points(struct ufs_hba *hba)
>> }
>>
>> /**
>> - * ufshcd_get_pwr_dev_param - get finally agreed attributes for
>> + * ufshcd_negotiate_pwr_param - get finally agreed attributes for
>> * power mode change
>> - * @pltfrm_param: pointer to platform parameters
>> + * @host_param: pointer to platform parameters
>> * @dev_max: pointer to device attributes
>> * @agreed_pwr: returned agreed attributes
>> *
>> * Return: 0 on success, non-zero value on failure.
>> */
>> -int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
>> - const struct ufs_pa_layer_attr *dev_max,
>> - struct ufs_pa_layer_attr *agreed_pwr)
>> +int ufshcd_negotiate_pwr_param(const struct ufs_host_params *host_param,
>> + const struct ufs_pa_layer_attr *dev_max,
>> + struct ufs_pa_layer_attr *agreed_pwr)
>> {
>> int min_pltfrm_gear;
> If you're going to change pltfrm -> host, maybe do so for
> min_pltfrm_gear too? I think this all reads nicer with the functions
> changed as is, but the consistency would be nice in my opinion.
Sure, will address in next version.
>
> Outside of those nits, I think this reads nicer now as well.
>
> Acked-by: Andrew Halaney <ahalaney@redhat.com>
Thanks,
Can Guo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 2/7] scsi: ufs: ufs-qcom: Setup host power mode during init
2023-11-07 20:14 ` Andrew Halaney
@ 2023-11-08 7:47 ` Can Guo
0 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-08 7:47 UTC (permalink / raw)
To: Andrew Halaney, Can Guo
Cc: bvanassche, mani, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Bao D . Nguyen, Andy Gross, Bjorn Andersson, Konrad Dybcio,
James E.J. Bottomley, open list:ARM/QUALCOMM SUPPORT, open list
Hi Andrew,
On 11/8/2023 4:14 AM, Andrew Halaney wrote:
> On Mon, Nov 06, 2023 at 08:46:08PM -0800, Can Guo wrote:
>> From: Can Guo <quic_cang@quicinc.com>
>>
>> Setup host power mode and its limitations during UFS host driver init to
>> avoid repetitive work during every power mode change.
>>
>> Co-developed-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
>> Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
>> Signed-off-by: Can Guo <quic_cang@quicinc.com>
>> ---
>> drivers/ufs/host/ufs-qcom.c | 22 ++++++++++++++--------
>> drivers/ufs/host/ufs-qcom.h | 1 +
>> 2 files changed, 15 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
>> index aee66a3..cc0eb37 100644
>> --- a/drivers/ufs/host/ufs-qcom.c
>> +++ b/drivers/ufs/host/ufs-qcom.c
>> @@ -898,7 +898,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
>> struct ufs_pa_layer_attr *dev_req_params)
>> {
>> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
>> - struct ufs_host_params host_params;
>> + struct ufs_host_params *host_params = &host->host_params;
>> int ret = 0;
>>
>> if (!dev_req_params) {
>> @@ -908,13 +908,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
>>
>> switch (status) {
>> case PRE_CHANGE:
>> - ufshcd_init_host_param(&host_params);
>> - host_params.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
> You drop the setting of hs_rate in your new function. It seems setting that's
> also overkill since UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B. hs_rate is
> already set to that in ufshcd_init_host_param(), so removing it makes
> sense.
>
> Can you remove it prior in its own patch, and remove the now unused
> UFS_QCOM_LIMIT_HS_RATE as well from ufs-qcom.h?
Sure, will address this in next version.
>
> With that in place this seems like a good improvement:
>
> Acked-by: Andrew Halaney <ahalaney@redhat.com>
Thanks,
Can Guo.
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 1/7] scsi: ufs: host: Rename structure ufs_dev_params to ufs_host_params
2023-11-07 20:56 ` Bart Van Assche
@ 2023-11-08 7:48 ` Can Guo
-1 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-08 7:48 UTC (permalink / raw)
To: Bart Van Assche, Can Guo, mani, stanley.chu, adrian.hunter,
beanhuo, avri.altman, junwoo80.lee, martin.petersen
Cc: linux-scsi, Alim Akhtar, James E.J. Bottomley,
Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Matthias Brugger, AngeloGioacchino Del Regno,
Uwe Kleine-König, Brian Masney,
moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES,
open list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES,
open list,
moderated list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...,
open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...
Hi Bart,
On 11/8/2023 4:56 AM, Bart Van Assche wrote:
> On 11/6/23 20:46, Can Guo wrote:
>> /**
>> - * ufshcd_get_pwr_dev_param - get finally agreed attributes for
>> + * ufshcd_negotiate_pwr_param - get finally agreed attributes for
>> * power mode change
>
> Since you are renaming the function, please also change the description
> of the function into something more meaningful, e.g. "find power mode
> settings that are supported by both the controller and the device".
Sure, will do.
>
>> - * @pltfrm_param: pointer to platform parameters
>> + * @host_param: pointer to platform parameters
>
> Please make sure that the argument name and argument description are in
> sync.
Sure.
>
> Thanks,
>
> Bart.
Thanks,
Can Guo.
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 1/7] scsi: ufs: host: Rename structure ufs_dev_params to ufs_host_params
@ 2023-11-08 7:48 ` Can Guo
0 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-08 7:48 UTC (permalink / raw)
To: Bart Van Assche, Can Guo, mani, stanley.chu, adrian.hunter,
beanhuo, avri.altman, junwoo80.lee, martin.petersen
Cc: linux-scsi, Alim Akhtar, James E.J. Bottomley,
Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Matthias Brugger, AngeloGioacchino Del Regno,
Uwe Kleine-König, Brian Masney,
moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES,
open list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES,
open list,
moderated list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...,
open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...
Hi Bart,
On 11/8/2023 4:56 AM, Bart Van Assche wrote:
> On 11/6/23 20:46, Can Guo wrote:
>> /**
>> - * ufshcd_get_pwr_dev_param - get finally agreed attributes for
>> + * ufshcd_negotiate_pwr_param - get finally agreed attributes for
>> * power mode change
>
> Since you are renaming the function, please also change the description
> of the function into something more meaningful, e.g. "find power mode
> settings that are supported by both the controller and the device".
Sure, will do.
>
>> - * @pltfrm_param: pointer to platform parameters
>> + * @host_param: pointer to platform parameters
>
> Please make sure that the argument name and argument description are in
> sync.
Sure.
>
> Thanks,
>
> Bart.
Thanks,
Can Guo.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 2/7] scsi: ufs: ufs-qcom: Setup host power mode during init
2023-11-08 5:07 ` Manivannan Sadhasivam
@ 2023-11-08 8:07 ` Can Guo
0 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-08 8:07 UTC (permalink / raw)
To: Manivannan Sadhasivam, Can Guo
Cc: bvanassche, stanley.chu, adrian.hunter, beanhuo, avri.altman,
junwoo80.lee, martin.petersen, linux-scsi, Bao D . Nguyen,
Andy Gross, Bjorn Andersson, Konrad Dybcio, James E.J. Bottomley,
open list:ARM/QUALCOMM SUPPORT, open list
Hi Mani,
On 11/8/2023 1:07 PM, Manivannan Sadhasivam wrote:
> On Mon, Nov 06, 2023 at 08:46:08PM -0800, Can Guo wrote:
>> From: Can Guo <quic_cang@quicinc.com>
>>
>> Setup host power mode and its limitations during UFS host driver init to
>> avoid repetitive work during every power mode change.
>>
>> Co-developed-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
>> Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
>> Signed-off-by: Can Guo <quic_cang@quicinc.com>
>> ---
>> drivers/ufs/host/ufs-qcom.c | 22 ++++++++++++++--------
>> drivers/ufs/host/ufs-qcom.h | 1 +
>> 2 files changed, 15 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
>> index aee66a3..cc0eb37 100644
>> --- a/drivers/ufs/host/ufs-qcom.c
>> +++ b/drivers/ufs/host/ufs-qcom.c
>> @@ -898,7 +898,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
>> struct ufs_pa_layer_attr *dev_req_params)
>> {
>> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
>> - struct ufs_host_params host_params;
>> + struct ufs_host_params *host_params = &host->host_params;
>> int ret = 0;
>>
>> if (!dev_req_params) {
>> @@ -908,13 +908,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
>>
>> switch (status) {
>> case PRE_CHANGE:
>> - ufshcd_init_host_param(&host_params);
>> - host_params.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
>
> As Andrew spotted, this gets removed without explanation. So, I'd also suggest
> doing it in a separate patch.
>
> - Mani
Sure, will do
Thanks,
Can Guo.
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 0/7] Enable HS-G5 support on SM8550
2023-11-08 5:11 ` Manivannan Sadhasivam
@ 2023-11-08 8:09 ` Can Guo
-1 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-08 8:09 UTC (permalink / raw)
To: Manivannan Sadhasivam, Can Guo
Cc: bvanassche, stanley.chu, adrian.hunter, beanhuo, avri.altman,
junwoo80.lee, martin.petersen, linux-scsi, Matthias Brugger,
AngeloGioacchino Del Regno, open list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support
Hi Mani,
On 11/8/2023 1:11 PM, Manivannan Sadhasivam wrote:
> On Mon, Nov 06, 2023 at 08:46:06PM -0800, Can Guo wrote:
>> This series enables HS-G5 support on SM8550.
>>
>> This series is rebased on below changes from Mani -
>> https://patchwork.kernel.org/project/linux-scsi/patch/20230908145329.154024-1-manivannan.sadhasivam@linaro.org/
>> https://patchwork.kernel.org/project/linux-scsi/patch/20230908145329.154024-2-manivannan.sadhasivam@linaro.org/
>>
>> This series is tested on below HW combinations -
>> SM8550 MTP + UFS4.0
>> SM8550 QRD + UFS3.1
>> SM8450 MTP + UFS3.1 (for regression test)
>>
>
> You are sending the patches from QTI email and that's not supposed to happen I
> believe.
>
> - Mani
You are right, not sure what went wrong with my config. Will change back
to quicinc mail next time.
Thanks,
Can Guo.
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 0/7] Enable HS-G5 support on SM8550
@ 2023-11-08 8:09 ` Can Guo
0 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-08 8:09 UTC (permalink / raw)
To: Manivannan Sadhasivam, Can Guo
Cc: bvanassche, stanley.chu, adrian.hunter, beanhuo, avri.altman,
junwoo80.lee, martin.petersen, linux-scsi, Matthias Brugger,
AngeloGioacchino Del Regno, open list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support,
moderated list:ARM/Mediatek SoC support
Hi Mani,
On 11/8/2023 1:11 PM, Manivannan Sadhasivam wrote:
> On Mon, Nov 06, 2023 at 08:46:06PM -0800, Can Guo wrote:
>> This series enables HS-G5 support on SM8550.
>>
>> This series is rebased on below changes from Mani -
>> https://patchwork.kernel.org/project/linux-scsi/patch/20230908145329.154024-1-manivannan.sadhasivam@linaro.org/
>> https://patchwork.kernel.org/project/linux-scsi/patch/20230908145329.154024-2-manivannan.sadhasivam@linaro.org/
>>
>> This series is tested on below HW combinations -
>> SM8550 MTP + UFS4.0
>> SM8550 QRD + UFS3.1
>> SM8450 MTP + UFS3.1 (for regression test)
>>
>
> You are sending the patches from QTI email and that's not supposed to happen I
> believe.
>
> - Mani
You are right, not sure what went wrong with my config. Will change back
to quicinc mail next time.
Thanks,
Can Guo.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 3/7] scsi: ufs: ufs-qcom: Allow the first init start with the maximum supported gear
2023-11-08 5:23 ` Manivannan Sadhasivam
@ 2023-11-08 8:21 ` Can Guo
2023-11-08 8:23 ` Can Guo
2023-11-09 3:47 ` Manivannan Sadhasivam
0 siblings, 2 replies; 86+ messages in thread
From: Can Guo @ 2023-11-08 8:21 UTC (permalink / raw)
To: Manivannan Sadhasivam, Can Guo
Cc: bvanassche, stanley.chu, adrian.hunter, beanhuo, avri.altman,
junwoo80.lee, martin.petersen, linux-scsi, Andy Gross,
Bjorn Andersson, Konrad Dybcio, James E.J. Bottomley,
open list:ARM/QUALCOMM SUPPORT, open list
Hi Mani,
On 11/8/2023 1:23 PM, Manivannan Sadhasivam wrote:
> On Mon, Nov 06, 2023 at 08:46:09PM -0800, Can Guo wrote:
>> From: Can Guo <quic_cang@quicinc.com>
>>
>> During host driver init, the phy_gear is set to the minimum supported gear
>> (HS_G2). Then, during the first power mode change, the negotiated gear, say
>> HS-G4, is updated to the phy_gear variable so that in the second init the
>> updated phy_gear can be used to program the PHY.
>>
>> But the current code only allows update the phy_gear to a higher value. If
>> one wants to start the first init with the maximum support gear, say HS-G4,
>> the phy_gear is not updated to HS-G3 if the device only supports HS-G3.
>>
>
> Can you elaborate when this can happen? AFAICS, there are 3 possibilities of
> initial phy gear with this series:
>
> 1. If ufshc is < 5.0, then G2 will be used.
> 2. If ufshc is >= 5.0 and if the version is populated in register, then that
> gear will be used. Most likely that gear can be G4/G5 depending on the device
> connected.
> 3. If ufshc is >=5.0 and version is not populated, then G4 will be used.
>
> In all the above cases, I do not see any necessity to switch the phy gear
> setting to lower one while scaling. Since the gears are backwards compatible,
> we always use one phy gear sequence. Moreover, we only have 2 init sequences.
>
> Please correct me if I'm missing anything.
>
> - Mani
In the next patch, I am setting the initial PHY gear to max HS gear read
from UFS host cap register, so that we don't need to keep updating the
initial value for host->phy_gear for different HW versions in future.
FYI, for HW ver 5 and 6, it is HS-G5. In future, the max gear might
become HS-G6 or higher on newer HW verions.
I the case #3, if HS-G5 is set to host->phy_gear, the first init uses
HS-G5, then after negotiation if the agreed gear is HS-G4, we need to
update host->phy_gear to HS-G4 (a lower value) such that we use a power
saving PHY gear settings during the 2nd init.
If the commit message is making you confused, I can update it in next
version. Please let me if I made any mistakes here.
Thanks,
Can Guo.
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 3/7] scsi: ufs: ufs-qcom: Allow the first init start with the maximum supported gear
2023-11-08 8:21 ` Can Guo
@ 2023-11-08 8:23 ` Can Guo
2023-11-09 3:47 ` Manivannan Sadhasivam
1 sibling, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-08 8:23 UTC (permalink / raw)
To: Manivannan Sadhasivam, Can Guo
Cc: bvanassche, stanley.chu, adrian.hunter, beanhuo, avri.altman,
junwoo80.lee, martin.petersen, linux-scsi, Andy Gross,
Bjorn Andersson, Konrad Dybcio, James E.J. Bottomley,
open list:ARM/QUALCOMM SUPPORT, open list
Hi Mani,
On 11/8/2023 4:21 PM, Can Guo wrote:
> Hi Mani,
>
> On 11/8/2023 1:23 PM, Manivannan Sadhasivam wrote:
>> On Mon, Nov 06, 2023 at 08:46:09PM -0800, Can Guo wrote:
>>> From: Can Guo <quic_cang@quicinc.com>
>>>
>>> During host driver init, the phy_gear is set to the minimum supported
>>> gear
>>> (HS_G2). Then, during the first power mode change, the negotiated
>>> gear, say
>>> HS-G4, is updated to the phy_gear variable so that in the second init
>>> the
>>> updated phy_gear can be used to program the PHY.
>>>
>>> But the current code only allows update the phy_gear to a higher
>>> value. If
>>> one wants to start the first init with the maximum support gear, say
>>> HS-G4,
>>> the phy_gear is not updated to HS-G3 if the device only supports HS-G3.
>>>
>>
>> Can you elaborate when this can happen? AFAICS, there are 3
>> possibilities of
>> initial phy gear with this series:
>>
>> 1. If ufshc is < 5.0, then G2 will be used.
>> 2. If ufshc is >= 5.0 and if the version is populated in register,
>> then that
>> gear will be used. Most likely that gear can be G4/G5 depending on the
>> device
>> connected.
>> 3. If ufshc is >=5.0 and version is not populated, then G4 will be used.
I think this made you confused, in case #3, HS-G5 is used as initial PHY
gear, not G4 (in the last patch in this series).
Thanks,
Can Guo.
>>
>> In all the above cases, I do not see any necessity to switch the phy gear
>> setting to lower one while scaling. Since the gears are backwards
>> compatible,
>> we always use one phy gear sequence. Moreover, we only have 2 init
>> sequences.
>>
>> Please correct me if I'm missing anything.
>>
>> - Mani
> In the next patch, I am setting the initial PHY gear to max HS gear read
> from UFS host cap register, so that we don't need to keep updating the
> initial value for host->phy_gear for different HW versions in future.
> FYI, for HW ver 5 and 6, it is HS-G5. In future, the max gear might
> become HS-G6 or higher on newer HW verions.
>
> I the case #3, if HS-G5 is set to host->phy_gear, the first init uses
> HS-G5, then after negotiation if the agreed gear is HS-G4, we need to
> update host->phy_gear to HS-G4 (a lower value) such that we use a power
> saving PHY gear settings during the 2nd init.
>
> If the commit message is making you confused, I can update it in next
> version. Please let me if I made any mistakes here.
>
> Thanks,
> Can Guo.
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 4/7] scsi: ufs: ufs-qcom: Limit HS-G5 Rate-A to hosts with HW version 5
2023-11-08 5:25 ` Manivannan Sadhasivam
@ 2023-11-08 8:42 ` Can Guo
2023-11-09 3:27 ` Manivannan Sadhasivam
0 siblings, 1 reply; 86+ messages in thread
From: Can Guo @ 2023-11-08 8:42 UTC (permalink / raw)
To: Manivannan Sadhasivam, Can Guo
Cc: bvanassche, stanley.chu, adrian.hunter, beanhuo, avri.altman,
junwoo80.lee, martin.petersen, linux-scsi, Andy Gross,
Bjorn Andersson, Konrad Dybcio, James E.J. Bottomley,
open list:ARM/QUALCOMM SUPPORT, open list
Hi Mani,
On 11/8/2023 1:25 PM, Manivannan Sadhasivam wrote:
> On Mon, Nov 06, 2023 at 08:46:10PM -0800, Can Guo wrote:
>> From: Can Guo <quic_cang@quicinc.com>
>>
>> Qcom UFS hosts, with HW ver 5, can only support up to HS-G5 Rate-A due to
>> HW limitations. If the HS-G5 PHY gear is used, update host_params->hs_rate
>> to Rate-A, so that the subsequent power mode changes shall stick to Rate-A.
>>
>> Signed-off-by: Can Guo <quic_cang@quicinc.com>
>> ---
>> drivers/ufs/host/ufs-qcom.c | 18 +++++++++++++++++-
>> 1 file changed, 17 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
>> index 60b35ca..55ee31d 100644
>> --- a/drivers/ufs/host/ufs-qcom.c
>> +++ b/drivers/ufs/host/ufs-qcom.c
>> @@ -442,9 +442,25 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
>> static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
>> {
>> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
>> + struct ufs_host_params *host_params = &host->host_params;
>> struct phy *phy = host->generic_phy;
>> + enum phy_mode mode;
>> int ret;
>>
>> + /*
>> + * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations.
>
> Does this limitation apply to future targets as well or just to SM8550? If
> it's the latter, then we need to use a flag.
>
> - ManiUFS host controller HW ver (major) 5 IPs (they may have different
minor/step verions) can be used by many QCOM chipsets, so it applies to
several available targets and future targets which are going to have HW
ver 5 UFS host controller. This limitation goes away since HW ver 6.
Thanks,
Can Guo.
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 5/7] scsi: ufs: ufs-qcom: Set initial PHY gear to max HS gear for HW ver 5 and newer
2023-11-08 5:34 ` Manivannan Sadhasivam
@ 2023-11-08 8:46 ` Can Guo
0 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-08 8:46 UTC (permalink / raw)
To: Manivannan Sadhasivam, Can Guo
Cc: bvanassche, stanley.chu, adrian.hunter, beanhuo, avri.altman,
junwoo80.lee, martin.petersen, linux-scsi, Andy Gross,
Bjorn Andersson, Konrad Dybcio, James E.J. Bottomley,
open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...,
open list
Hi Mani,
On 11/8/2023 1:34 PM, Manivannan Sadhasivam wrote:
> On Mon, Nov 06, 2023 at 08:46:11PM -0800, Can Guo wrote:
>> From: Can Guo <quic_cang@quicinc.com>
>>
>> Set the initial PHY gear to max HS gear for hosts with HW ver 5 and newer.
>>
>
> How about,
>
> "For UFSHC >= 5.0, set the initial PHY gear based on the gear value returned by
> ufs_qcom_get_hs_gear(). For the rest, use the existing default value of G2."
>
It is much better, will improve in next version.
>> This patch is not changing any functionalities or logic but only a
>> preparation patch for the next patch in this series.
>>
>
> You are also moving the default phy_gear code to ufs_qcom_set_host_params(). So
> it should be mentioned in the commit message.
>
Sure.
Thanks,
Can Guo.
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-07 13:18 ` Dmitry Baryshkov
@ 2023-11-08 9:02 ` Can Guo
-1 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-08 9:02 UTC (permalink / raw)
To: Dmitry Baryshkov, Can Guo
Cc: bvanassche, mani, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, open list:ARM/QUALCOMM SUPPORT,
open list:GENERIC PHY FRAMEWORK, open list
Hi Dmitry,
On 11/7/2023 9:18 PM, Dmitry Baryshkov wrote:
> On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
>>
>> From: Can Guo <quic_cang@quicinc.com>
>>
>> On SM8550, two sets of UFS PHY settings are provided, one set is to support
>> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
>> settings are programming different values to different registers, mixing
>> the two sets and/or overwriting one set with another set is definitely not
>> blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
>> need to split the two sets into their dedicated tables, and leave only the
>> common settings in the .tlbs. To have the PHY programmed with the correct
>> set of PHY settings, the submode passed to PHY driver must be either HS-G4
>> or HS-G5.
>>
>> Signed-off-by: Can Guo <quic_cang@quicinc.com>
>> ---
>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
>> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
>> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
>> 4 files changed, 115 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>> index c23d5e4..e563af5 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>> @@ -18,6 +18,7 @@
>> #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
>> #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
>> #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
>> +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
>> #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
>> #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
>> #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
>> @@ -27,5 +28,6 @@
>> #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
>> #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
>> #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
>> +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
>>
>> #endif
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>> index f420f8f..ef392ce 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>> @@ -56,6 +56,8 @@
>> #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
>> #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
>> #define QSERDES_V6_COM_PLL_IVCO 0xf4
>> +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
>> +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
>> #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
>> #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
>> #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>> index 15bcb4b..48f31c8 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>> @@ -10,10 +10,20 @@
>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
>> +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
>> +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
>>
>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
>> +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
>> +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
>> #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
>> +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
>> +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
>> @@ -25,6 +35,8 @@
>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
>> +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
>> +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
>>
>> #endif
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> index 3927eba..e0a01497 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
>> +
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
>> +};
>> +
>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
>> +};
>> +
>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
>
> Aside from moving these registers to the HS_G4 table, you are also
> changing these registers. It makes me think that there was an error in
> the original programming sequence.
> If that is correct, could you please split the patch into two pieces:
> - Fix programming sequence (add proper Fixes tags)
> - Split G4 and G5 tables.
You are correct, I don't know where the original values are from, but
they look like a mixing of HS-G4 settings and HS-G5 settings to me,
because I see some values are only supposed to be there for HS-G5,
whereas the same MODE0 registers are programmed twice, I guess they
should be MODE1 registers which are only required for HS-G4.
>
>> +
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
>
> I see all the MODE1 registers being only present in G4 and G5 tables.
> Should they be programmed for the modes lower than G4?
>
As mentioned in the commit msg, on SM8550, only two sets of UFS PHY
settings are provided, one set is to support HS-G5, another set is to
support HS-G4.
Although HS-G5 set of PHY settings is backward comptiable and able to
support all lower gears, UFS driver should make sure HS-G5 set of PHY
settings are only used when UFS device really supports HS-G5.
For UFS devices which can only support HS-G4 or lower gears, UFS driver
would use the HS-G4 set of PHY settings, in order to save power.
Thanks,
Can Guo.
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-08 9:02 ` Can Guo
0 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-08 9:02 UTC (permalink / raw)
To: Dmitry Baryshkov, Can Guo
Cc: bvanassche, mani, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, open list:ARM/QUALCOMM SUPPORT,
open list:GENERIC PHY FRAMEWORK, open list
Hi Dmitry,
On 11/7/2023 9:18 PM, Dmitry Baryshkov wrote:
> On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
>>
>> From: Can Guo <quic_cang@quicinc.com>
>>
>> On SM8550, two sets of UFS PHY settings are provided, one set is to support
>> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
>> settings are programming different values to different registers, mixing
>> the two sets and/or overwriting one set with another set is definitely not
>> blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
>> need to split the two sets into their dedicated tables, and leave only the
>> common settings in the .tlbs. To have the PHY programmed with the correct
>> set of PHY settings, the submode passed to PHY driver must be either HS-G4
>> or HS-G5.
>>
>> Signed-off-by: Can Guo <quic_cang@quicinc.com>
>> ---
>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
>> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
>> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
>> 4 files changed, 115 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>> index c23d5e4..e563af5 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>> @@ -18,6 +18,7 @@
>> #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
>> #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
>> #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
>> +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
>> #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
>> #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
>> #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
>> @@ -27,5 +28,6 @@
>> #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
>> #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
>> #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
>> +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
>>
>> #endif
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>> index f420f8f..ef392ce 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>> @@ -56,6 +56,8 @@
>> #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
>> #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
>> #define QSERDES_V6_COM_PLL_IVCO 0xf4
>> +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
>> +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
>> #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
>> #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
>> #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>> index 15bcb4b..48f31c8 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>> @@ -10,10 +10,20 @@
>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
>> +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
>> +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
>>
>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
>> +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
>> +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
>> #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
>> +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
>> +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
>> @@ -25,6 +35,8 @@
>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
>> +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
>> +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
>>
>> #endif
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> index 3927eba..e0a01497 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
>> +
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
>> +};
>> +
>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
>> +};
>> +
>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
>
> Aside from moving these registers to the HS_G4 table, you are also
> changing these registers. It makes me think that there was an error in
> the original programming sequence.
> If that is correct, could you please split the patch into two pieces:
> - Fix programming sequence (add proper Fixes tags)
> - Split G4 and G5 tables.
You are correct, I don't know where the original values are from, but
they look like a mixing of HS-G4 settings and HS-G5 settings to me,
because I see some values are only supposed to be there for HS-G5,
whereas the same MODE0 registers are programmed twice, I guess they
should be MODE1 registers which are only required for HS-G4.
>
>> +
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
>
> I see all the MODE1 registers being only present in G4 and G5 tables.
> Should they be programmed for the modes lower than G4?
>
As mentioned in the commit msg, on SM8550, only two sets of UFS PHY
settings are provided, one set is to support HS-G5, another set is to
support HS-G4.
Although HS-G5 set of PHY settings is backward comptiable and able to
support all lower gears, UFS driver should make sure HS-G5 set of PHY
settings are only used when UFS device really supports HS-G5.
For UFS devices which can only support HS-G4 or lower gears, UFS driver
would use the HS-G4 set of PHY settings, in order to save power.
Thanks,
Can Guo.
--
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linux-phy@lists.infradead.org
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^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-08 5:49 ` Manivannan Sadhasivam
@ 2023-11-08 9:19 ` Can Guo
-1 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-08 9:19 UTC (permalink / raw)
To: Manivannan Sadhasivam, Dmitry Baryshkov
Cc: Can Guo, bvanassche, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, open list:ARM/QUALCOMM SUPPORT,
open list:GENERIC PHY FRAMEWORK, open list
Hi Mani,
On 11/8/2023 1:49 PM, Manivannan Sadhasivam wrote:
> On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
>> On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
>>>
>>> From: Can Guo <quic_cang@quicinc.com>
>>>
>>> On SM8550, two sets of UFS PHY settings are provided, one set is to support
>>> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
>>> settings are programming different values to different registers, mixing
>>> the two sets and/or overwriting one set with another set is definitely not
>>> blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
>>> need to split the two sets into their dedicated tables, and leave only the
>>> common settings in the .tlbs. To have the PHY programmed with the correct
>>> set of PHY settings, the submode passed to PHY driver must be either HS-G4
>>> or HS-G5.
>>>
>
> You should also mention that this issue is also present in G4 supported targets.
> And a note that it will get fixed later.
Will this info upset more people? How about I mention this in the cover
letter?
>
>>> Signed-off-by: Can Guo <quic_cang@quicinc.com>
>>> ---
>>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
>>> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
>>> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
>>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
>>> 4 files changed, 115 insertions(+), 13 deletions(-)
>>>
>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>> index c23d5e4..e563af5 100644
>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>> @@ -18,6 +18,7 @@
>>> #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
>>> #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
>>> #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
>>> +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
>>> #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
>>> #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
>>> #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
>>> @@ -27,5 +28,6 @@
>>> #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
>>> #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
>>> #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
>>> +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
>>>
>>> #endif
>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>> index f420f8f..ef392ce 100644
>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>> @@ -56,6 +56,8 @@
>>> #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
>>> #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
>>> #define QSERDES_V6_COM_PLL_IVCO 0xf4
>>> +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
>>> +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
>>> #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
>>> #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
>>> #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>> index 15bcb4b..48f31c8 100644
>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>> @@ -10,10 +10,20 @@
>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
>>> +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
>>> +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
>>>
>>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
>>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
>>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
>>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
>>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
>>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
>>> +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
>>> +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
>>> #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
>>> +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
>>> +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
>>> @@ -25,6 +35,8 @@
>>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
>>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
>>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
>>> +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
>>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
>>> +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
>>>
>>> #endif
>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>> index 3927eba..e0a01497 100644
>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>> @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
>>> +
>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
>>> +};
>>> +
>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
>>> +};
>>> +
>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
>>
>> Aside from moving these registers to the HS_G4 table, you are also
>> changing these registers. It makes me think that there was an error in
>> the original programming sequence.
>> If that is correct, could you please split the patch into two pieces:
>> - Fix programming sequence (add proper Fixes tags)
>> - Split G4 and G5 tables.
>
> Ack
>
>>
>>> +
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
>>
>> I see all the MODE1 registers being only present in G4 and G5 tables.
>> Should they be programmed for the modes lower than G4?
>>
>
> We use G4 table for all the modes <= G4.
>
>>> +};
>>> +
>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
>>> +
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
>>> };
>>>
>>> static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
>>> - QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
>>> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
>>> };
>>>
>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
>>> +};
>>> +
>>> static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
>>> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
>>> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
>>> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
>>>
>>> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
>>> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
>>> @@ -690,14 +709,46 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
>>> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
>>> };
>>>
>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
>>> +};
>>> +
>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
>>> +
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
>>> +};
>>> +
>>> static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
>>> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
>>> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
>>> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
>>> - QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
>>> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
>>> };
>>>
>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
>>> +};
>>> +
>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
>>> +};
>>> +
>>> struct qmp_ufs_offsets {
>>> u16 serdes;
>>> u16 pcs;
>>> @@ -731,6 +782,8 @@ struct qmp_phy_cfg {
>>> const struct qmp_phy_cfg_tbls tbls_hs_b;
>>> /* Additional sequence for HS G4 */
>>> const struct qmp_phy_cfg_tbls tbls_hs_g4;
>>> + /* Additional sequence for HS G4 */
>
> HS G5
Sure
>
>>> + const struct qmp_phy_cfg_tbls tbls_hs_g5;
>>>
>>> /* clock ids to be requested */
>>> const char * const *clk_list;
>>> @@ -1157,6 +1210,28 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
>>> .pcs = sm8550_ufsphy_pcs,
>>> .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
>>> },
>>> + .tbls_hs_b = {
>>> + .serdes = sm8550_ufsphy_hs_b_serdes,
>>> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
>>> + },
>>> + .tbls_hs_g4 = {
>>> + .serdes = sm8550_ufsphy_g4_serdes,
>>> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
>>> + .tx = sm8550_ufsphy_g4_tx,
>>> + .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
>>> + .rx = sm8550_ufsphy_g4_rx,
>>> + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
>>> + .pcs = sm8550_ufsphy_g4_pcs,
>>> + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
>>> + },
>>> + .tbls_hs_g5 = {
>>> + .serdes = sm8550_ufsphy_g5_serdes,
>>> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
>>> + .rx = sm8550_ufsphy_g5_rx,
>>> + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
>>> + .pcs = sm8550_ufsphy_g5_pcs,
>>> + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
>>> + },
>>> .clk_list = sdm845_ufs_phy_clk_l,
>>> .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
>>> .vreg_list = qmp_phy_vreg_l,
>>> @@ -1222,14 +1297,25 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
>>> static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
>>> {
>>> qmp_ufs_serdes_init(qmp, &cfg->tbls);
>>> + if (qmp->submode == UFS_HS_G4)
>>> + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
>>> + else if (qmp->submode == UFS_HS_G5)
>>> + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
>>> +
>
> Should we program submode sequence after HS_B?
>
> - Mani
>
As the UFS PHY HW programming doc mentions, order of these writes is not
important, so long as they are programmed correctly before release S/W
reset, then it is fine.
Thanks,
Can Guo.
--
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linux-phy@lists.infradead.org
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^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-08 9:19 ` Can Guo
0 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-08 9:19 UTC (permalink / raw)
To: Manivannan Sadhasivam, Dmitry Baryshkov
Cc: Can Guo, bvanassche, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, open list:ARM/QUALCOMM SUPPORT,
open list:GENERIC PHY FRAMEWORK, open list
Hi Mani,
On 11/8/2023 1:49 PM, Manivannan Sadhasivam wrote:
> On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
>> On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
>>>
>>> From: Can Guo <quic_cang@quicinc.com>
>>>
>>> On SM8550, two sets of UFS PHY settings are provided, one set is to support
>>> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
>>> settings are programming different values to different registers, mixing
>>> the two sets and/or overwriting one set with another set is definitely not
>>> blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
>>> need to split the two sets into their dedicated tables, and leave only the
>>> common settings in the .tlbs. To have the PHY programmed with the correct
>>> set of PHY settings, the submode passed to PHY driver must be either HS-G4
>>> or HS-G5.
>>>
>
> You should also mention that this issue is also present in G4 supported targets.
> And a note that it will get fixed later.
Will this info upset more people? How about I mention this in the cover
letter?
>
>>> Signed-off-by: Can Guo <quic_cang@quicinc.com>
>>> ---
>>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
>>> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
>>> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
>>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
>>> 4 files changed, 115 insertions(+), 13 deletions(-)
>>>
>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>> index c23d5e4..e563af5 100644
>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>> @@ -18,6 +18,7 @@
>>> #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
>>> #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
>>> #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
>>> +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
>>> #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
>>> #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
>>> #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
>>> @@ -27,5 +28,6 @@
>>> #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
>>> #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
>>> #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
>>> +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
>>>
>>> #endif
>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>> index f420f8f..ef392ce 100644
>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>> @@ -56,6 +56,8 @@
>>> #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
>>> #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
>>> #define QSERDES_V6_COM_PLL_IVCO 0xf4
>>> +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
>>> +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
>>> #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
>>> #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
>>> #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>> index 15bcb4b..48f31c8 100644
>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>> @@ -10,10 +10,20 @@
>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
>>> +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
>>> +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
>>>
>>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
>>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
>>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
>>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
>>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
>>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
>>> +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
>>> +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
>>> #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
>>> +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
>>> +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
>>> @@ -25,6 +35,8 @@
>>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
>>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
>>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
>>> +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
>>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
>>> +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
>>>
>>> #endif
>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>> index 3927eba..e0a01497 100644
>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>> @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
>>> +
>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
>>> +};
>>> +
>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
>>> +};
>>> +
>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
>>
>> Aside from moving these registers to the HS_G4 table, you are also
>> changing these registers. It makes me think that there was an error in
>> the original programming sequence.
>> If that is correct, could you please split the patch into two pieces:
>> - Fix programming sequence (add proper Fixes tags)
>> - Split G4 and G5 tables.
>
> Ack
>
>>
>>> +
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
>>
>> I see all the MODE1 registers being only present in G4 and G5 tables.
>> Should they be programmed for the modes lower than G4?
>>
>
> We use G4 table for all the modes <= G4.
>
>>> +};
>>> +
>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
>>> +
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
>>> };
>>>
>>> static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
>>> - QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
>>> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
>>> };
>>>
>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
>>> +};
>>> +
>>> static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
>>> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
>>> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
>>> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
>>>
>>> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
>>> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
>>> @@ -690,14 +709,46 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
>>> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
>>> };
>>>
>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
>>> +};
>>> +
>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
>>> +
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
>>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
>>> +};
>>> +
>>> static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
>>> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
>>> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
>>> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
>>> - QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
>>> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
>>> };
>>>
>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
>>> +};
>>> +
>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
>>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
>>> +};
>>> +
>>> struct qmp_ufs_offsets {
>>> u16 serdes;
>>> u16 pcs;
>>> @@ -731,6 +782,8 @@ struct qmp_phy_cfg {
>>> const struct qmp_phy_cfg_tbls tbls_hs_b;
>>> /* Additional sequence for HS G4 */
>>> const struct qmp_phy_cfg_tbls tbls_hs_g4;
>>> + /* Additional sequence for HS G4 */
>
> HS G5
Sure
>
>>> + const struct qmp_phy_cfg_tbls tbls_hs_g5;
>>>
>>> /* clock ids to be requested */
>>> const char * const *clk_list;
>>> @@ -1157,6 +1210,28 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
>>> .pcs = sm8550_ufsphy_pcs,
>>> .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
>>> },
>>> + .tbls_hs_b = {
>>> + .serdes = sm8550_ufsphy_hs_b_serdes,
>>> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
>>> + },
>>> + .tbls_hs_g4 = {
>>> + .serdes = sm8550_ufsphy_g4_serdes,
>>> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
>>> + .tx = sm8550_ufsphy_g4_tx,
>>> + .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
>>> + .rx = sm8550_ufsphy_g4_rx,
>>> + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
>>> + .pcs = sm8550_ufsphy_g4_pcs,
>>> + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
>>> + },
>>> + .tbls_hs_g5 = {
>>> + .serdes = sm8550_ufsphy_g5_serdes,
>>> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
>>> + .rx = sm8550_ufsphy_g5_rx,
>>> + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
>>> + .pcs = sm8550_ufsphy_g5_pcs,
>>> + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
>>> + },
>>> .clk_list = sdm845_ufs_phy_clk_l,
>>> .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
>>> .vreg_list = qmp_phy_vreg_l,
>>> @@ -1222,14 +1297,25 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
>>> static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
>>> {
>>> qmp_ufs_serdes_init(qmp, &cfg->tbls);
>>> + if (qmp->submode == UFS_HS_G4)
>>> + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
>>> + else if (qmp->submode == UFS_HS_G5)
>>> + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
>>> +
>
> Should we program submode sequence after HS_B?
>
> - Mani
>
As the UFS PHY HW programming doc mentions, order of these writes is not
important, so long as they are programmed correctly before release S/W
reset, then it is fine.
Thanks,
Can Guo.
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-08 6:56 ` Dmitry Baryshkov
@ 2023-11-09 3:24 ` Manivannan Sadhasivam
-1 siblings, 0 replies; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-09 3:24 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Manivannan Sadhasivam, Can Guo, quic_cang, bvanassche,
stanley.chu, adrian.hunter, beanhuo, avri.altman, junwoo80.lee,
martin.petersen, linux-scsi, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
> On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
> >
> > On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> > > On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> > > >
> > > > From: Can Guo <quic_cang@quicinc.com>
> > > >
> > > > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > > > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > > > settings are programming different values to different registers, mixing
> > > > the two sets and/or overwriting one set with another set is definitely not
> > > > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > > > need to split the two sets into their dedicated tables, and leave only the
> > > > common settings in the .tlbs. To have the PHY programmed with the correct
> > > > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > > > or HS-G5.
> > > >
> >
> > You should also mention that this issue is also present in G4 supported targets.
> > And a note that it will get fixed later.
> >
> > > > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > > > ---
> > > > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > > > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > > > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > > > 4 files changed, 115 insertions(+), 13 deletions(-)
> > > >
> > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > index c23d5e4..e563af5 100644
> > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > @@ -18,6 +18,7 @@
> > > > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > > > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > > > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > > > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > > > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > > > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > > > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > > > @@ -27,5 +28,6 @@
> > > > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > > > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > > > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > > > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> > > >
> > > > #endif
> > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > index f420f8f..ef392ce 100644
> > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > @@ -56,6 +56,8 @@
> > > > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > > > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > > > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > > > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > > > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > > > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > > > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > > > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > index 15bcb4b..48f31c8 100644
> > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > @@ -10,10 +10,20 @@
> > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > > > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > > > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> > > >
> > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > > > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > > > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > > > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > > > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > > > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > > > @@ -25,6 +35,8 @@
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > > > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > > > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> > > >
> > > > #endif
> > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > index 3927eba..e0a01497 100644
> > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > +
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > > > +};
> > > > +
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > > > +};
> > > > +
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> > >
> > > Aside from moving these registers to the HS_G4 table, you are also
> > > changing these registers. It makes me think that there was an error in
> > > the original programming sequence.
> > > If that is correct, could you please split the patch into two pieces:
> > > - Fix programming sequence (add proper Fixes tags)
> > > - Split G4 and G5 tables.
> >
> > Ack
> >
> > >
> > > > +
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> > >
> > > I see all the MODE1 registers being only present in G4 and G5 tables.
> > > Should they be programmed for the modes lower than G4?
> > >
> >
> > We use G4 table for all the modes <= G4.
>
> Could you please point me how it's handled?
> In the patch I see just:
>
> if (qmp->submode == UFS_HS_G4)
> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> else if (qmp->submode == UFS_HS_G5)
> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
>
> Which looks like two special cases (HS_G4 and HS_G5) and nothing for
> anything else.
>
Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
sequence will be used and for G5, G5 sequence will be used.
- Mani
> >
> > > > +};
> > > > +
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
> > > > +
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
> > > > };
> > > >
> > > > static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
> > > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
> > > > };
> > > >
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
> > > > +};
> > > > +
> > > > static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> > > > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
> > > > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
> > > > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
> > > >
> > > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
> > > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
> > > > @@ -690,14 +709,46 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> > > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
> > > > };
> > > >
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> > > > +};
> > > > +
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
> > > > +
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
> > > > +};
> > > > +
> > > > static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
> > > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
> > > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
> > > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> > > > - QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> > > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> > > > };
> > > >
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
> > > > +};
> > > > +
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
> > > > +};
> > > > +
> > > > struct qmp_ufs_offsets {
> > > > u16 serdes;
> > > > u16 pcs;
> > > > @@ -731,6 +782,8 @@ struct qmp_phy_cfg {
> > > > const struct qmp_phy_cfg_tbls tbls_hs_b;
> > > > /* Additional sequence for HS G4 */
> > > > const struct qmp_phy_cfg_tbls tbls_hs_g4;
> > > > + /* Additional sequence for HS G4 */
> >
> > HS G5
> >
> > > > + const struct qmp_phy_cfg_tbls tbls_hs_g5;
> > > >
> > > > /* clock ids to be requested */
> > > > const char * const *clk_list;
> > > > @@ -1157,6 +1210,28 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
> > > > .pcs = sm8550_ufsphy_pcs,
> > > > .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
> > > > },
> > > > + .tbls_hs_b = {
> > > > + .serdes = sm8550_ufsphy_hs_b_serdes,
> > > > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
> > > > + },
> > > > + .tbls_hs_g4 = {
> > > > + .serdes = sm8550_ufsphy_g4_serdes,
> > > > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
> > > > + .tx = sm8550_ufsphy_g4_tx,
> > > > + .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
> > > > + .rx = sm8550_ufsphy_g4_rx,
> > > > + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
> > > > + .pcs = sm8550_ufsphy_g4_pcs,
> > > > + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
> > > > + },
> > > > + .tbls_hs_g5 = {
> > > > + .serdes = sm8550_ufsphy_g5_serdes,
> > > > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
> > > > + .rx = sm8550_ufsphy_g5_rx,
> > > > + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
> > > > + .pcs = sm8550_ufsphy_g5_pcs,
> > > > + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
> > > > + },
> > > > .clk_list = sdm845_ufs_phy_clk_l,
> > > > .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> > > > .vreg_list = qmp_phy_vreg_l,
> > > > @@ -1222,14 +1297,25 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
> > > > static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
> > > > {
> > > > qmp_ufs_serdes_init(qmp, &cfg->tbls);
> > > > + if (qmp->submode == UFS_HS_G4)
> > > > + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > > > + else if (qmp->submode == UFS_HS_G5)
> > > > + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> > > > +
> >
> > Should we program submode sequence after HS_B?
> >
> > - Mani
> >
> > --
> > மணிவண்ணன் சதாசிவம்
>
>
>
> --
> With best wishes
> Dmitry
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-09 3:24 ` Manivannan Sadhasivam
0 siblings, 0 replies; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-09 3:24 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Manivannan Sadhasivam, Can Guo, quic_cang, bvanassche,
stanley.chu, adrian.hunter, beanhuo, avri.altman, junwoo80.lee,
martin.petersen, linux-scsi, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
> On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
> >
> > On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> > > On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> > > >
> > > > From: Can Guo <quic_cang@quicinc.com>
> > > >
> > > > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > > > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > > > settings are programming different values to different registers, mixing
> > > > the two sets and/or overwriting one set with another set is definitely not
> > > > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > > > need to split the two sets into their dedicated tables, and leave only the
> > > > common settings in the .tlbs. To have the PHY programmed with the correct
> > > > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > > > or HS-G5.
> > > >
> >
> > You should also mention that this issue is also present in G4 supported targets.
> > And a note that it will get fixed later.
> >
> > > > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > > > ---
> > > > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > > > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > > > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > > > 4 files changed, 115 insertions(+), 13 deletions(-)
> > > >
> > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > index c23d5e4..e563af5 100644
> > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > @@ -18,6 +18,7 @@
> > > > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > > > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > > > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > > > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > > > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > > > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > > > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > > > @@ -27,5 +28,6 @@
> > > > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > > > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > > > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > > > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> > > >
> > > > #endif
> > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > index f420f8f..ef392ce 100644
> > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > @@ -56,6 +56,8 @@
> > > > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > > > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > > > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > > > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > > > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > > > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > > > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > > > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > index 15bcb4b..48f31c8 100644
> > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > @@ -10,10 +10,20 @@
> > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > > > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > > > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> > > >
> > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > > > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > > > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > > > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > > > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > > > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > > > @@ -25,6 +35,8 @@
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > > > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > > > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> > > >
> > > > #endif
> > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > index 3927eba..e0a01497 100644
> > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > +
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > > > +};
> > > > +
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > > > +};
> > > > +
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> > >
> > > Aside from moving these registers to the HS_G4 table, you are also
> > > changing these registers. It makes me think that there was an error in
> > > the original programming sequence.
> > > If that is correct, could you please split the patch into two pieces:
> > > - Fix programming sequence (add proper Fixes tags)
> > > - Split G4 and G5 tables.
> >
> > Ack
> >
> > >
> > > > +
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> > >
> > > I see all the MODE1 registers being only present in G4 and G5 tables.
> > > Should they be programmed for the modes lower than G4?
> > >
> >
> > We use G4 table for all the modes <= G4.
>
> Could you please point me how it's handled?
> In the patch I see just:
>
> if (qmp->submode == UFS_HS_G4)
> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> else if (qmp->submode == UFS_HS_G5)
> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
>
> Which looks like two special cases (HS_G4 and HS_G5) and nothing for
> anything else.
>
Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
sequence will be used and for G5, G5 sequence will be used.
- Mani
> >
> > > > +};
> > > > +
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
> > > > +
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
> > > > };
> > > >
> > > > static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
> > > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
> > > > };
> > > >
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
> > > > +};
> > > > +
> > > > static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> > > > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
> > > > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
> > > > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
> > > >
> > > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
> > > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
> > > > @@ -690,14 +709,46 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> > > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
> > > > };
> > > >
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> > > > +};
> > > > +
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
> > > > +
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
> > > > +};
> > > > +
> > > > static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
> > > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
> > > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
> > > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> > > > - QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> > > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> > > > };
> > > >
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
> > > > +};
> > > > +
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
> > > > +};
> > > > +
> > > > struct qmp_ufs_offsets {
> > > > u16 serdes;
> > > > u16 pcs;
> > > > @@ -731,6 +782,8 @@ struct qmp_phy_cfg {
> > > > const struct qmp_phy_cfg_tbls tbls_hs_b;
> > > > /* Additional sequence for HS G4 */
> > > > const struct qmp_phy_cfg_tbls tbls_hs_g4;
> > > > + /* Additional sequence for HS G4 */
> >
> > HS G5
> >
> > > > + const struct qmp_phy_cfg_tbls tbls_hs_g5;
> > > >
> > > > /* clock ids to be requested */
> > > > const char * const *clk_list;
> > > > @@ -1157,6 +1210,28 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
> > > > .pcs = sm8550_ufsphy_pcs,
> > > > .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
> > > > },
> > > > + .tbls_hs_b = {
> > > > + .serdes = sm8550_ufsphy_hs_b_serdes,
> > > > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
> > > > + },
> > > > + .tbls_hs_g4 = {
> > > > + .serdes = sm8550_ufsphy_g4_serdes,
> > > > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
> > > > + .tx = sm8550_ufsphy_g4_tx,
> > > > + .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
> > > > + .rx = sm8550_ufsphy_g4_rx,
> > > > + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
> > > > + .pcs = sm8550_ufsphy_g4_pcs,
> > > > + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
> > > > + },
> > > > + .tbls_hs_g5 = {
> > > > + .serdes = sm8550_ufsphy_g5_serdes,
> > > > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
> > > > + .rx = sm8550_ufsphy_g5_rx,
> > > > + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
> > > > + .pcs = sm8550_ufsphy_g5_pcs,
> > > > + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
> > > > + },
> > > > .clk_list = sdm845_ufs_phy_clk_l,
> > > > .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> > > > .vreg_list = qmp_phy_vreg_l,
> > > > @@ -1222,14 +1297,25 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
> > > > static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
> > > > {
> > > > qmp_ufs_serdes_init(qmp, &cfg->tbls);
> > > > + if (qmp->submode == UFS_HS_G4)
> > > > + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > > > + else if (qmp->submode == UFS_HS_G5)
> > > > + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> > > > +
> >
> > Should we program submode sequence after HS_B?
> >
> > - Mani
> >
> > --
> > மணிவண்ணன் சதாசிவம்
>
>
>
> --
> With best wishes
> Dmitry
--
மணிவண்ணன் சதாசிவம்
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-08 9:19 ` Can Guo
@ 2023-11-09 3:26 ` Manivannan Sadhasivam
-1 siblings, 0 replies; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-09 3:26 UTC (permalink / raw)
To: Can Guo
Cc: Dmitry Baryshkov, Can Guo, bvanassche, stanley.chu,
adrian.hunter, beanhuo, avri.altman, junwoo80.lee,
martin.petersen, linux-scsi, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
On Wed, Nov 08, 2023 at 05:19:43PM +0800, Can Guo wrote:
> Hi Mani,
>
> On 11/8/2023 1:49 PM, Manivannan Sadhasivam wrote:
> > On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> > > On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> > > >
> > > > From: Can Guo <quic_cang@quicinc.com>
> > > >
> > > > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > > > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > > > settings are programming different values to different registers, mixing
> > > > the two sets and/or overwriting one set with another set is definitely not
> > > > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > > > need to split the two sets into their dedicated tables, and leave only the
> > > > common settings in the .tlbs. To have the PHY programmed with the correct
> > > > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > > > or HS-G5.
> > > >
> >
> > You should also mention that this issue is also present in G4 supported targets.
> > And a note that it will get fixed later.
>
> Will this info upset more people? How about I mention this in the cover
> letter?
>
It is working fine for now and we just want to make sure the sequence is aligned
with HPG. So I don't think it can upset anyone. But yeah, you can just mention
it in the cover letter.
- Mani
> >
> > > > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > > > ---
> > > > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > > > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > > > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > > > 4 files changed, 115 insertions(+), 13 deletions(-)
> > > >
> > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > index c23d5e4..e563af5 100644
> > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > @@ -18,6 +18,7 @@
> > > > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > > > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > > > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > > > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > > > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > > > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > > > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > > > @@ -27,5 +28,6 @@
> > > > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > > > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > > > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > > > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> > > >
> > > > #endif
> > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > index f420f8f..ef392ce 100644
> > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > @@ -56,6 +56,8 @@
> > > > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > > > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > > > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > > > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > > > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > > > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > > > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > > > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > index 15bcb4b..48f31c8 100644
> > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > @@ -10,10 +10,20 @@
> > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > > > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > > > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> > > >
> > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > > > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > > > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > > > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > > > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > > > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > > > @@ -25,6 +35,8 @@
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > > > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > > > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> > > >
> > > > #endif
> > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > index 3927eba..e0a01497 100644
> > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > +
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > > > +};
> > > > +
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > > > +};
> > > > +
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> > >
> > > Aside from moving these registers to the HS_G4 table, you are also
> > > changing these registers. It makes me think that there was an error in
> > > the original programming sequence.
> > > If that is correct, could you please split the patch into two pieces:
> > > - Fix programming sequence (add proper Fixes tags)
> > > - Split G4 and G5 tables.
> >
> > Ack
> >
> > >
> > > > +
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> > >
> > > I see all the MODE1 registers being only present in G4 and G5 tables.
> > > Should they be programmed for the modes lower than G4?
> > >
> >
> > We use G4 table for all the modes <= G4.
> >
> > > > +};
> > > > +
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
> > > > +
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
> > > > };
> > > >
> > > > static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
> > > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
> > > > };
> > > >
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
> > > > +};
> > > > +
> > > > static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> > > > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
> > > > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
> > > > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
> > > >
> > > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
> > > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
> > > > @@ -690,14 +709,46 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> > > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
> > > > };
> > > >
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> > > > +};
> > > > +
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
> > > > +
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
> > > > +};
> > > > +
> > > > static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
> > > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
> > > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
> > > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> > > > - QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> > > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> > > > };
> > > >
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
> > > > +};
> > > > +
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
> > > > +};
> > > > +
> > > > struct qmp_ufs_offsets {
> > > > u16 serdes;
> > > > u16 pcs;
> > > > @@ -731,6 +782,8 @@ struct qmp_phy_cfg {
> > > > const struct qmp_phy_cfg_tbls tbls_hs_b;
> > > > /* Additional sequence for HS G4 */
> > > > const struct qmp_phy_cfg_tbls tbls_hs_g4;
> > > > + /* Additional sequence for HS G4 */
> >
> > HS G5
>
> Sure
>
> >
> > > > + const struct qmp_phy_cfg_tbls tbls_hs_g5;
> > > >
> > > > /* clock ids to be requested */
> > > > const char * const *clk_list;
> > > > @@ -1157,6 +1210,28 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
> > > > .pcs = sm8550_ufsphy_pcs,
> > > > .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
> > > > },
> > > > + .tbls_hs_b = {
> > > > + .serdes = sm8550_ufsphy_hs_b_serdes,
> > > > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
> > > > + },
> > > > + .tbls_hs_g4 = {
> > > > + .serdes = sm8550_ufsphy_g4_serdes,
> > > > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
> > > > + .tx = sm8550_ufsphy_g4_tx,
> > > > + .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
> > > > + .rx = sm8550_ufsphy_g4_rx,
> > > > + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
> > > > + .pcs = sm8550_ufsphy_g4_pcs,
> > > > + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
> > > > + },
> > > > + .tbls_hs_g5 = {
> > > > + .serdes = sm8550_ufsphy_g5_serdes,
> > > > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
> > > > + .rx = sm8550_ufsphy_g5_rx,
> > > > + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
> > > > + .pcs = sm8550_ufsphy_g5_pcs,
> > > > + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
> > > > + },
> > > > .clk_list = sdm845_ufs_phy_clk_l,
> > > > .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> > > > .vreg_list = qmp_phy_vreg_l,
> > > > @@ -1222,14 +1297,25 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
> > > > static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
> > > > {
> > > > qmp_ufs_serdes_init(qmp, &cfg->tbls);
> > > > + if (qmp->submode == UFS_HS_G4)
> > > > + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > > > + else if (qmp->submode == UFS_HS_G5)
> > > > + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> > > > +
> >
> > Should we program submode sequence after HS_B?
> >
> > - Mani
> >
> As the UFS PHY HW programming doc mentions, order of these writes is not
> important, so long as they are programmed correctly before release S/W
> reset, then it is fine.
>
> Thanks,
> Can Guo.
>
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-09 3:26 ` Manivannan Sadhasivam
0 siblings, 0 replies; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-09 3:26 UTC (permalink / raw)
To: Can Guo
Cc: Dmitry Baryshkov, Can Guo, bvanassche, stanley.chu,
adrian.hunter, beanhuo, avri.altman, junwoo80.lee,
martin.petersen, linux-scsi, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
On Wed, Nov 08, 2023 at 05:19:43PM +0800, Can Guo wrote:
> Hi Mani,
>
> On 11/8/2023 1:49 PM, Manivannan Sadhasivam wrote:
> > On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> > > On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> > > >
> > > > From: Can Guo <quic_cang@quicinc.com>
> > > >
> > > > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > > > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > > > settings are programming different values to different registers, mixing
> > > > the two sets and/or overwriting one set with another set is definitely not
> > > > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > > > need to split the two sets into their dedicated tables, and leave only the
> > > > common settings in the .tlbs. To have the PHY programmed with the correct
> > > > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > > > or HS-G5.
> > > >
> >
> > You should also mention that this issue is also present in G4 supported targets.
> > And a note that it will get fixed later.
>
> Will this info upset more people? How about I mention this in the cover
> letter?
>
It is working fine for now and we just want to make sure the sequence is aligned
with HPG. So I don't think it can upset anyone. But yeah, you can just mention
it in the cover letter.
- Mani
> >
> > > > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > > > ---
> > > > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > > > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > > > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > > > 4 files changed, 115 insertions(+), 13 deletions(-)
> > > >
> > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > index c23d5e4..e563af5 100644
> > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > @@ -18,6 +18,7 @@
> > > > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > > > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > > > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > > > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > > > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > > > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > > > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > > > @@ -27,5 +28,6 @@
> > > > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > > > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > > > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > > > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> > > >
> > > > #endif
> > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > index f420f8f..ef392ce 100644
> > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > @@ -56,6 +56,8 @@
> > > > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > > > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > > > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > > > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > > > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > > > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > > > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > > > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > index 15bcb4b..48f31c8 100644
> > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > @@ -10,10 +10,20 @@
> > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > > > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > > > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> > > >
> > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > > > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > > > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > > > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > > > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > > > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > > > @@ -25,6 +35,8 @@
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > > > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > > > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> > > >
> > > > #endif
> > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > index 3927eba..e0a01497 100644
> > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > +
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > > > +};
> > > > +
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > > > +};
> > > > +
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> > >
> > > Aside from moving these registers to the HS_G4 table, you are also
> > > changing these registers. It makes me think that there was an error in
> > > the original programming sequence.
> > > If that is correct, could you please split the patch into two pieces:
> > > - Fix programming sequence (add proper Fixes tags)
> > > - Split G4 and G5 tables.
> >
> > Ack
> >
> > >
> > > > +
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> > >
> > > I see all the MODE1 registers being only present in G4 and G5 tables.
> > > Should they be programmed for the modes lower than G4?
> > >
> >
> > We use G4 table for all the modes <= G4.
> >
> > > > +};
> > > > +
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
> > > > +
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
> > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
> > > > };
> > > >
> > > > static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
> > > > - QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
> > > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
> > > > };
> > > >
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
> > > > +};
> > > > +
> > > > static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> > > > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
> > > > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
> > > > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
> > > >
> > > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
> > > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
> > > > @@ -690,14 +709,46 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> > > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
> > > > };
> > > >
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> > > > +};
> > > > +
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
> > > > +
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
> > > > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
> > > > +};
> > > > +
> > > > static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
> > > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
> > > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
> > > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> > > > - QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> > > > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> > > > };
> > > >
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
> > > > +};
> > > > +
> > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
> > > > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
> > > > +};
> > > > +
> > > > struct qmp_ufs_offsets {
> > > > u16 serdes;
> > > > u16 pcs;
> > > > @@ -731,6 +782,8 @@ struct qmp_phy_cfg {
> > > > const struct qmp_phy_cfg_tbls tbls_hs_b;
> > > > /* Additional sequence for HS G4 */
> > > > const struct qmp_phy_cfg_tbls tbls_hs_g4;
> > > > + /* Additional sequence for HS G4 */
> >
> > HS G5
>
> Sure
>
> >
> > > > + const struct qmp_phy_cfg_tbls tbls_hs_g5;
> > > >
> > > > /* clock ids to be requested */
> > > > const char * const *clk_list;
> > > > @@ -1157,6 +1210,28 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
> > > > .pcs = sm8550_ufsphy_pcs,
> > > > .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
> > > > },
> > > > + .tbls_hs_b = {
> > > > + .serdes = sm8550_ufsphy_hs_b_serdes,
> > > > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
> > > > + },
> > > > + .tbls_hs_g4 = {
> > > > + .serdes = sm8550_ufsphy_g4_serdes,
> > > > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
> > > > + .tx = sm8550_ufsphy_g4_tx,
> > > > + .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
> > > > + .rx = sm8550_ufsphy_g4_rx,
> > > > + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
> > > > + .pcs = sm8550_ufsphy_g4_pcs,
> > > > + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
> > > > + },
> > > > + .tbls_hs_g5 = {
> > > > + .serdes = sm8550_ufsphy_g5_serdes,
> > > > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
> > > > + .rx = sm8550_ufsphy_g5_rx,
> > > > + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
> > > > + .pcs = sm8550_ufsphy_g5_pcs,
> > > > + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
> > > > + },
> > > > .clk_list = sdm845_ufs_phy_clk_l,
> > > > .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> > > > .vreg_list = qmp_phy_vreg_l,
> > > > @@ -1222,14 +1297,25 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
> > > > static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
> > > > {
> > > > qmp_ufs_serdes_init(qmp, &cfg->tbls);
> > > > + if (qmp->submode == UFS_HS_G4)
> > > > + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > > > + else if (qmp->submode == UFS_HS_G5)
> > > > + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> > > > +
> >
> > Should we program submode sequence after HS_B?
> >
> > - Mani
> >
> As the UFS PHY HW programming doc mentions, order of these writes is not
> important, so long as they are programmed correctly before release S/W
> reset, then it is fine.
>
> Thanks,
> Can Guo.
>
>
--
மணிவண்ணன் சதாசிவம்
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 4/7] scsi: ufs: ufs-qcom: Limit HS-G5 Rate-A to hosts with HW version 5
2023-11-08 8:42 ` Can Guo
@ 2023-11-09 3:27 ` Manivannan Sadhasivam
0 siblings, 0 replies; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-09 3:27 UTC (permalink / raw)
To: Can Guo
Cc: Can Guo, bvanassche, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, James E.J. Bottomley,
open list:ARM/QUALCOMM SUPPORT, open list
On Wed, Nov 08, 2023 at 04:42:42PM +0800, Can Guo wrote:
> Hi Mani,
>
> On 11/8/2023 1:25 PM, Manivannan Sadhasivam wrote:
> > On Mon, Nov 06, 2023 at 08:46:10PM -0800, Can Guo wrote:
> > > From: Can Guo <quic_cang@quicinc.com>
> > >
> > > Qcom UFS hosts, with HW ver 5, can only support up to HS-G5 Rate-A due to
> > > HW limitations. If the HS-G5 PHY gear is used, update host_params->hs_rate
> > > to Rate-A, so that the subsequent power mode changes shall stick to Rate-A.
> > >
> > > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > > ---
> > > drivers/ufs/host/ufs-qcom.c | 18 +++++++++++++++++-
> > > 1 file changed, 17 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> > > index 60b35ca..55ee31d 100644
> > > --- a/drivers/ufs/host/ufs-qcom.c
> > > +++ b/drivers/ufs/host/ufs-qcom.c
> > > @@ -442,9 +442,25 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
> > > static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> > > {
> > > struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> > > + struct ufs_host_params *host_params = &host->host_params;
> > > struct phy *phy = host->generic_phy;
> > > + enum phy_mode mode;
> > > int ret;
> > > + /*
> > > + * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations.
> >
> > Does this limitation apply to future targets as well or just to SM8550? If
> > it's the latter, then we need to use a flag.
> >
> > - ManiUFS host controller HW ver (major) 5 IPs (they may have different
> minor/step verions) can be used by many QCOM chipsets, so it applies to
> several available targets and future targets which are going to have HW ver
> 5 UFS host controller. This limitation goes away since HW ver 6.
>
Okay, thanks for clarifying.
- Mani
> Thanks,
> Can Guo.
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 3/7] scsi: ufs: ufs-qcom: Allow the first init start with the maximum supported gear
2023-11-08 8:21 ` Can Guo
2023-11-08 8:23 ` Can Guo
@ 2023-11-09 3:47 ` Manivannan Sadhasivam
2023-11-09 4:07 ` Can Guo
1 sibling, 1 reply; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-09 3:47 UTC (permalink / raw)
To: Can Guo
Cc: Can Guo, bvanassche, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, James E.J. Bottomley,
open list:ARM/QUALCOMM SUPPORT, open list
On Wed, Nov 08, 2023 at 04:21:52PM +0800, Can Guo wrote:
> Hi Mani,
>
> On 11/8/2023 1:23 PM, Manivannan Sadhasivam wrote:
> > On Mon, Nov 06, 2023 at 08:46:09PM -0800, Can Guo wrote:
> > > From: Can Guo <quic_cang@quicinc.com>
> > >
> > > During host driver init, the phy_gear is set to the minimum supported gear
> > > (HS_G2). Then, during the first power mode change, the negotiated gear, say
> > > HS-G4, is updated to the phy_gear variable so that in the second init the
> > > updated phy_gear can be used to program the PHY.
> > >
> > > But the current code only allows update the phy_gear to a higher value. If
> > > one wants to start the first init with the maximum support gear, say HS-G4,
> > > the phy_gear is not updated to HS-G3 if the device only supports HS-G3.
> > >
> >
> > Can you elaborate when this can happen? AFAICS, there are 3 possibilities of
> > initial phy gear with this series:
> >
> > 1. If ufshc is < 5.0, then G2 will be used.
> > 2. If ufshc is >= 5.0 and if the version is populated in register, then that
> > gear will be used. Most likely that gear can be G4/G5 depending on the device
> > connected.
> > 3. If ufshc is >=5.0 and version is not populated, then G4 will be used.
> >
> > In all the above cases, I do not see any necessity to switch the phy gear
> > setting to lower one while scaling. Since the gears are backwards compatible,
> > we always use one phy gear sequence. Moreover, we only have 2 init sequences.
> >
> > Please correct me if I'm missing anything.
> >
> > - Mani
> In the next patch, I am setting the initial PHY gear to max HS gear read
> from UFS host cap register, so that we don't need to keep updating the
> initial value for host->phy_gear for different HW versions in future. FYI,
> for HW ver 5 and 6, it is HS-G5. In future, the max gear might become HS-G6
> or higher on newer HW verions.
>
> I the case #3, if HS-G5 is set to host->phy_gear, the first init uses HS-G5,
> then after negotiation if the agreed gear is HS-G4, we need to update
> host->phy_gear to HS-G4 (a lower value) such that we use a power saving PHY
> gear settings during the 2nd init.
>
> If the commit message is making you confused, I can update it in next
> version. Please let me if I made any mistakes here.
>
I see redundancy while setting the phy_gear and it is leading to confusion.
In ufs_qcom_set_host_params(), first you are setting phy_gear based on
ufs_qcom_get_hs_gear(), then changing it again with the version check for v5.
I don't see a necessity for "host->phy_gear = host_params->hs_tx_gear", since in
the later check, you are covering both version <5 and >=5.
Btw, it would be better to move this logic to a separate function like
ufs_qcom_get_phy_gear() to align with ufs_qcom_get_hs_gear().
- Mani
> Thanks,
> Can Guo.
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 3/7] scsi: ufs: ufs-qcom: Allow the first init start with the maximum supported gear
2023-11-09 3:47 ` Manivannan Sadhasivam
@ 2023-11-09 4:07 ` Can Guo
2023-11-09 7:47 ` Manivannan Sadhasivam
0 siblings, 1 reply; 86+ messages in thread
From: Can Guo @ 2023-11-09 4:07 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Can Guo, bvanassche, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, James E.J. Bottomley,
open list:ARM/QUALCOMM SUPPORT, open list
Hi Mani,
On 11/9/2023 11:47 AM, Manivannan Sadhasivam wrote:
> On Wed, Nov 08, 2023 at 04:21:52PM +0800, Can Guo wrote:
>> Hi Mani,
>>
>> On 11/8/2023 1:23 PM, Manivannan Sadhasivam wrote:
>>> On Mon, Nov 06, 2023 at 08:46:09PM -0800, Can Guo wrote:
>>>> From: Can Guo <quic_cang@quicinc.com>
>>>>
>>>> During host driver init, the phy_gear is set to the minimum supported gear
>>>> (HS_G2). Then, during the first power mode change, the negotiated gear, say
>>>> HS-G4, is updated to the phy_gear variable so that in the second init the
>>>> updated phy_gear can be used to program the PHY.
>>>>
>>>> But the current code only allows update the phy_gear to a higher value. If
>>>> one wants to start the first init with the maximum support gear, say HS-G4,
>>>> the phy_gear is not updated to HS-G3 if the device only supports HS-G3.
>>>>
>>>
>>> Can you elaborate when this can happen? AFAICS, there are 3 possibilities of
>>> initial phy gear with this series:
>>>
>>> 1. If ufshc is < 5.0, then G2 will be used.
>>> 2. If ufshc is >= 5.0 and if the version is populated in register, then that
>>> gear will be used. Most likely that gear can be G4/G5 depending on the device
>>> connected.
>>> 3. If ufshc is >=5.0 and version is not populated, then G4 will be used.
>>>
>>> In all the above cases, I do not see any necessity to switch the phy gear
>>> setting to lower one while scaling. Since the gears are backwards compatible,
>>> we always use one phy gear sequence. Moreover, we only have 2 init sequences.
>>>
>>> Please correct me if I'm missing anything.
>>>
>>> - Mani
>> In the next patch, I am setting the initial PHY gear to max HS gear read
>> from UFS host cap register, so that we don't need to keep updating the
>> initial value for host->phy_gear for different HW versions in future. FYI,
>> for HW ver 5 and 6, it is HS-G5. In future, the max gear might become HS-G6
>> or higher on newer HW verions.
>>
>> I the case #3, if HS-G5 is set to host->phy_gear, the first init uses HS-G5,
>> then after negotiation if the agreed gear is HS-G4, we need to update
>> host->phy_gear to HS-G4 (a lower value) such that we use a power saving PHY
>> gear settings during the 2nd init.
>>
>> If the commit message is making you confused, I can update it in next
>> version. Please let me if I made any mistakes here.
>>
>
> I see redundancy while setting the phy_gear and it is leading to confusion.
> In ufs_qcom_set_host_params(), first you are setting phy_gear based on
> ufs_qcom_get_hs_gear(), then changing it again with the version check for v5.
>
> I don't see a necessity for "host->phy_gear = host_params->hs_tx_gear", since in
> the later check, you are covering both version <5 and >=5.
In the case of HW version >= 5, we are only overwriting the PHY gear
only if the UFS device cannot support HS-G5. Hence, we need to give
host->phy_gear an initial value.
>
> Btw, it would be better to move this logic to a separate function like
> ufs_qcom_get_phy_gear() to align with ufs_qcom_get_hs_gear().
>
OK, will do in next version.
Thanks,
Can Guo.
> - Mani
>
>> Thanks,
>> Can Guo.
>
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 3/7] scsi: ufs: ufs-qcom: Allow the first init start with the maximum supported gear
2023-11-09 4:07 ` Can Guo
@ 2023-11-09 7:47 ` Manivannan Sadhasivam
0 siblings, 0 replies; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-09 7:47 UTC (permalink / raw)
To: Can Guo
Cc: Can Guo, bvanassche, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, James E.J. Bottomley,
open list:ARM/QUALCOMM SUPPORT, open list
On Thu, Nov 09, 2023 at 12:07:37PM +0800, Can Guo wrote:
> Hi Mani,
>
> On 11/9/2023 11:47 AM, Manivannan Sadhasivam wrote:
> > On Wed, Nov 08, 2023 at 04:21:52PM +0800, Can Guo wrote:
> > > Hi Mani,
> > >
> > > On 11/8/2023 1:23 PM, Manivannan Sadhasivam wrote:
> > > > On Mon, Nov 06, 2023 at 08:46:09PM -0800, Can Guo wrote:
> > > > > From: Can Guo <quic_cang@quicinc.com>
> > > > >
> > > > > During host driver init, the phy_gear is set to the minimum supported gear
> > > > > (HS_G2). Then, during the first power mode change, the negotiated gear, say
> > > > > HS-G4, is updated to the phy_gear variable so that in the second init the
> > > > > updated phy_gear can be used to program the PHY.
> > > > >
> > > > > But the current code only allows update the phy_gear to a higher value. If
> > > > > one wants to start the first init with the maximum support gear, say HS-G4,
> > > > > the phy_gear is not updated to HS-G3 if the device only supports HS-G3.
> > > > >
> > > >
> > > > Can you elaborate when this can happen? AFAICS, there are 3 possibilities of
> > > > initial phy gear with this series:
> > > >
> > > > 1. If ufshc is < 5.0, then G2 will be used.
> > > > 2. If ufshc is >= 5.0 and if the version is populated in register, then that
> > > > gear will be used. Most likely that gear can be G4/G5 depending on the device
> > > > connected.
> > > > 3. If ufshc is >=5.0 and version is not populated, then G4 will be used.
> > > >
> > > > In all the above cases, I do not see any necessity to switch the phy gear
> > > > setting to lower one while scaling. Since the gears are backwards compatible,
> > > > we always use one phy gear sequence. Moreover, we only have 2 init sequences.
> > > >
> > > > Please correct me if I'm missing anything.
> > > >
> > > > - Mani
> > > In the next patch, I am setting the initial PHY gear to max HS gear read
> > > from UFS host cap register, so that we don't need to keep updating the
> > > initial value for host->phy_gear for different HW versions in future. FYI,
> > > for HW ver 5 and 6, it is HS-G5. In future, the max gear might become HS-G6
> > > or higher on newer HW verions.
> > >
> > > I the case #3, if HS-G5 is set to host->phy_gear, the first init uses HS-G5,
> > > then after negotiation if the agreed gear is HS-G4, we need to update
> > > host->phy_gear to HS-G4 (a lower value) such that we use a power saving PHY
> > > gear settings during the 2nd init.
> > >
> > > If the commit message is making you confused, I can update it in next
> > > version. Please let me if I made any mistakes here.
> > >
> >
> > I see redundancy while setting the phy_gear and it is leading to confusion.
> > In ufs_qcom_set_host_params(), first you are setting phy_gear based on
> > ufs_qcom_get_hs_gear(), then changing it again with the version check for v5.
> >
> > I don't see a necessity for "host->phy_gear = host_params->hs_tx_gear", since in
> > the later check, you are covering both version <5 and >=5.
> In the case of HW version >= 5, we are only overwriting the PHY gear only if
> the UFS device cannot support HS-G5. Hence, we need to give host->phy_gear
> an initial value.
>
Okay, I overlooked that part, thanks for clarifying. I think if we move the
logic to ufs_qcom_get_phy_gear(), it will be clear.
- Mani
> >
> > Btw, it would be better to move this logic to a separate function like
> > ufs_qcom_get_phy_gear() to align with ufs_qcom_get_hs_gear().
> >
> OK, will do in next version.
>
> Thanks,
> Can Guo.
> > - Mani
> >
> > > Thanks,
> > > Can Guo.
> >
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-09 3:24 ` Manivannan Sadhasivam
@ 2023-11-09 9:40 ` Dmitry Baryshkov
-1 siblings, 0 replies; 86+ messages in thread
From: Dmitry Baryshkov @ 2023-11-09 9:40 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Can Guo, quic_cang, bvanassche, stanley.chu, adrian.hunter,
beanhuo, avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, open list:ARM/QUALCOMM SUPPORT,
open list:GENERIC PHY FRAMEWORK, open list
On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
>
> On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
> > On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > >
> > > On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> > > > On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> > > > >
> > > > > From: Can Guo <quic_cang@quicinc.com>
> > > > >
> > > > > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > > > > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > > > > settings are programming different values to different registers, mixing
> > > > > the two sets and/or overwriting one set with another set is definitely not
> > > > > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > > > > need to split the two sets into their dedicated tables, and leave only the
> > > > > common settings in the .tlbs. To have the PHY programmed with the correct
> > > > > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > > > > or HS-G5.
> > > > >
> > >
> > > You should also mention that this issue is also present in G4 supported targets.
> > > And a note that it will get fixed later.
> > >
> > > > > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > > > > ---
> > > > > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > > > > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > > > > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > > > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > > > > 4 files changed, 115 insertions(+), 13 deletions(-)
> > > > >
> > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > index c23d5e4..e563af5 100644
> > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > @@ -18,6 +18,7 @@
> > > > > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > > > > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > > > > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > > > > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > > > > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > > > > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > > > > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > > > > @@ -27,5 +28,6 @@
> > > > > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > > > > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > > > > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > > > > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> > > > >
> > > > > #endif
> > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > index f420f8f..ef392ce 100644
> > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > @@ -56,6 +56,8 @@
> > > > > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > > > > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > > > > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > > > > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > > > > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > > > > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > > > > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > > > > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > index 15bcb4b..48f31c8 100644
> > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > @@ -10,10 +10,20 @@
> > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > > > > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > > > > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> > > > >
> > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > > > > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > > > > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > > > > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > > > > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > > > > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > > > > @@ -25,6 +35,8 @@
> > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > > > > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > > > > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> > > > >
> > > > > #endif
> > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > index 3927eba..e0a01497 100644
> > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > +
> > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > > > > +};
> > > > > +
> > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > > > > +};
> > > > > +
> > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> > > >
> > > > Aside from moving these registers to the HS_G4 table, you are also
> > > > changing these registers. It makes me think that there was an error in
> > > > the original programming sequence.
> > > > If that is correct, could you please split the patch into two pieces:
> > > > - Fix programming sequence (add proper Fixes tags)
> > > > - Split G4 and G5 tables.
> > >
> > > Ack
> > >
> > > >
> > > > > +
> > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> > > >
> > > > I see all the MODE1 registers being only present in G4 and G5 tables.
> > > > Should they be programmed for the modes lower than G4?
> > > >
> > >
> > > We use G4 table for all the modes <= G4.
> >
> > Could you please point me how it's handled?
> > In the patch I see just:
> >
> > if (qmp->submode == UFS_HS_G4)
> > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > else if (qmp->submode == UFS_HS_G5)
> > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> >
> > Which looks like two special cases (HS_G4 and HS_G5) and nothing for
> > anything else.
> >
>
> Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
> sequence will be used and for G5, G5 sequence will be used.
>
That's what I could not find in the UFS driver. I see a call to
`phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
host->phy_gear is initialised to UFS_HS_G2.
Maybe we should change the condition here (in the PHY driver) to:
if (qmp->submode <= UFS_HS_G4)
?
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-09 9:40 ` Dmitry Baryshkov
0 siblings, 0 replies; 86+ messages in thread
From: Dmitry Baryshkov @ 2023-11-09 9:40 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Can Guo, quic_cang, bvanassche, stanley.chu, adrian.hunter,
beanhuo, avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, open list:ARM/QUALCOMM SUPPORT,
open list:GENERIC PHY FRAMEWORK, open list
On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
>
> On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
> > On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > >
> > > On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> > > > On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> > > > >
> > > > > From: Can Guo <quic_cang@quicinc.com>
> > > > >
> > > > > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > > > > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > > > > settings are programming different values to different registers, mixing
> > > > > the two sets and/or overwriting one set with another set is definitely not
> > > > > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > > > > need to split the two sets into their dedicated tables, and leave only the
> > > > > common settings in the .tlbs. To have the PHY programmed with the correct
> > > > > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > > > > or HS-G5.
> > > > >
> > >
> > > You should also mention that this issue is also present in G4 supported targets.
> > > And a note that it will get fixed later.
> > >
> > > > > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > > > > ---
> > > > > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > > > > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > > > > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > > > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > > > > 4 files changed, 115 insertions(+), 13 deletions(-)
> > > > >
> > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > index c23d5e4..e563af5 100644
> > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > @@ -18,6 +18,7 @@
> > > > > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > > > > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > > > > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > > > > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > > > > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > > > > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > > > > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > > > > @@ -27,5 +28,6 @@
> > > > > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > > > > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > > > > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > > > > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> > > > >
> > > > > #endif
> > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > index f420f8f..ef392ce 100644
> > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > @@ -56,6 +56,8 @@
> > > > > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > > > > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > > > > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > > > > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > > > > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > > > > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > > > > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > > > > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > index 15bcb4b..48f31c8 100644
> > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > @@ -10,10 +10,20 @@
> > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > > > > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > > > > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> > > > >
> > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > > > > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > > > > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > > > > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > > > > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > > > > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > > > > @@ -25,6 +35,8 @@
> > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > > > > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > > > > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> > > > >
> > > > > #endif
> > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > index 3927eba..e0a01497 100644
> > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > +
> > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > > > > +};
> > > > > +
> > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > > > > +};
> > > > > +
> > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> > > >
> > > > Aside from moving these registers to the HS_G4 table, you are also
> > > > changing these registers. It makes me think that there was an error in
> > > > the original programming sequence.
> > > > If that is correct, could you please split the patch into two pieces:
> > > > - Fix programming sequence (add proper Fixes tags)
> > > > - Split G4 and G5 tables.
> > >
> > > Ack
> > >
> > > >
> > > > > +
> > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> > > >
> > > > I see all the MODE1 registers being only present in G4 and G5 tables.
> > > > Should they be programmed for the modes lower than G4?
> > > >
> > >
> > > We use G4 table for all the modes <= G4.
> >
> > Could you please point me how it's handled?
> > In the patch I see just:
> >
> > if (qmp->submode == UFS_HS_G4)
> > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > else if (qmp->submode == UFS_HS_G5)
> > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> >
> > Which looks like two special cases (HS_G4 and HS_G5) and nothing for
> > anything else.
> >
>
> Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
> sequence will be used and for G5, G5 sequence will be used.
>
That's what I could not find in the UFS driver. I see a call to
`phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
host->phy_gear is initialised to UFS_HS_G2.
Maybe we should change the condition here (in the PHY driver) to:
if (qmp->submode <= UFS_HS_G4)
?
--
With best wishes
Dmitry
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-09 9:40 ` Dmitry Baryshkov
@ 2023-11-09 10:42 ` Manivannan Sadhasivam
-1 siblings, 0 replies; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-09 10:42 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Can Guo, quic_cang, bvanassche, stanley.chu, adrian.hunter,
beanhuo, avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, open list:ARM/QUALCOMM SUPPORT,
open list:GENERIC PHY FRAMEWORK, open list
On Thu, Nov 09, 2023 at 11:40:51AM +0200, Dmitry Baryshkov wrote:
> On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
> >
> > On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
> > > On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > >
> > > > On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> > > > > On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> > > > > >
> > > > > > From: Can Guo <quic_cang@quicinc.com>
> > > > > >
> > > > > > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > > > > > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > > > > > settings are programming different values to different registers, mixing
> > > > > > the two sets and/or overwriting one set with another set is definitely not
> > > > > > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > > > > > need to split the two sets into their dedicated tables, and leave only the
> > > > > > common settings in the .tlbs. To have the PHY programmed with the correct
> > > > > > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > > > > > or HS-G5.
> > > > > >
> > > >
> > > > You should also mention that this issue is also present in G4 supported targets.
> > > > And a note that it will get fixed later.
> > > >
> > > > > > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > > > > > ---
> > > > > > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > > > > > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > > > > > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > > > > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > > > > > 4 files changed, 115 insertions(+), 13 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > index c23d5e4..e563af5 100644
> > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > @@ -18,6 +18,7 @@
> > > > > > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > > > > > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > > > > > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > > > > > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > > > > > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > > > > > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > > > > > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > > > > > @@ -27,5 +28,6 @@
> > > > > > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > > > > > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > > > > > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > > > > > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> > > > > >
> > > > > > #endif
> > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > index f420f8f..ef392ce 100644
> > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > @@ -56,6 +56,8 @@
> > > > > > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > > > > > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > > > > > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > > > > > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > > > > > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > > > > > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > > > > > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > > > > > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > index 15bcb4b..48f31c8 100644
> > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > @@ -10,10 +10,20 @@
> > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > > > > > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > > > > > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> > > > > >
> > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > > > > > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > > > > > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > > > > > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > > > > > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > > > > > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > > > > > @@ -25,6 +35,8 @@
> > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > > > > > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > > > > > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> > > > > >
> > > > > > #endif
> > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > index 3927eba..e0a01497 100644
> > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > +
> > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > > > > > +};
> > > > > > +
> > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > > > > > +};
> > > > > > +
> > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> > > > >
> > > > > Aside from moving these registers to the HS_G4 table, you are also
> > > > > changing these registers. It makes me think that there was an error in
> > > > > the original programming sequence.
> > > > > If that is correct, could you please split the patch into two pieces:
> > > > > - Fix programming sequence (add proper Fixes tags)
> > > > > - Split G4 and G5 tables.
> > > >
> > > > Ack
> > > >
> > > > >
> > > > > > +
> > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> > > > >
> > > > > I see all the MODE1 registers being only present in G4 and G5 tables.
> > > > > Should they be programmed for the modes lower than G4?
> > > > >
> > > >
> > > > We use G4 table for all the modes <= G4.
> > >
> > > Could you please point me how it's handled?
> > > In the patch I see just:
> > >
> > > if (qmp->submode == UFS_HS_G4)
> > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > > else if (qmp->submode == UFS_HS_G5)
> > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> > >
> > > Which looks like two special cases (HS_G4 and HS_G5) and nothing for
> > > anything else.
> > >
> >
> > Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
> > sequence will be used and for G5, G5 sequence will be used.
> >
>
> That's what I could not find in the UFS driver. I see a call to
> `phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
> host->phy_gear is initialised to UFS_HS_G2.
>
You need to check the UFS driver changes in this series to get the complete
picture as the logic is getting changed.
It is common to get confused because of the way the UFS driver (qcom mostly)
handles the PHY init sequence programming. We used to have only one init
sequence for older targets and life was easy. But when I wanted to add G4
support for SM8250, I learned that there are 2 separate init sequences. One for
non-G4 and other for G4. So I used the phy_sub_mode property to pass the
relevant mode from the UFS driver to the PHY driver and programmed the sequence
accordingly. This got extended to non-G5 and G5 now.
Now, the UFS driver will start probing from a low gear for older targets (G2)
and G4/G5 for newer ones then scale up based on the device and host capability.
For older targets, the common table (tbls) will be used if the submode doesn't
match G4/G5. But for newer targets, the UFS driver will _only_ pass G4 or G5 as
the phy_gear, so those specific sequence will only be used.
Hope I'm clear.
- Mani
> Maybe we should change the condition here (in the PHY driver) to:
>
> if (qmp->submode <= UFS_HS_G4)
>
> ?
> --
> With best wishes
> Dmitry
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-09 10:42 ` Manivannan Sadhasivam
0 siblings, 0 replies; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-09 10:42 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Can Guo, quic_cang, bvanassche, stanley.chu, adrian.hunter,
beanhuo, avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, open list:ARM/QUALCOMM SUPPORT,
open list:GENERIC PHY FRAMEWORK, open list
On Thu, Nov 09, 2023 at 11:40:51AM +0200, Dmitry Baryshkov wrote:
> On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
> >
> > On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
> > > On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > >
> > > > On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> > > > > On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> > > > > >
> > > > > > From: Can Guo <quic_cang@quicinc.com>
> > > > > >
> > > > > > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > > > > > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > > > > > settings are programming different values to different registers, mixing
> > > > > > the two sets and/or overwriting one set with another set is definitely not
> > > > > > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > > > > > need to split the two sets into their dedicated tables, and leave only the
> > > > > > common settings in the .tlbs. To have the PHY programmed with the correct
> > > > > > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > > > > > or HS-G5.
> > > > > >
> > > >
> > > > You should also mention that this issue is also present in G4 supported targets.
> > > > And a note that it will get fixed later.
> > > >
> > > > > > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > > > > > ---
> > > > > > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > > > > > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > > > > > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > > > > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > > > > > 4 files changed, 115 insertions(+), 13 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > index c23d5e4..e563af5 100644
> > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > @@ -18,6 +18,7 @@
> > > > > > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > > > > > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > > > > > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > > > > > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > > > > > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > > > > > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > > > > > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > > > > > @@ -27,5 +28,6 @@
> > > > > > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > > > > > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > > > > > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > > > > > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> > > > > >
> > > > > > #endif
> > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > index f420f8f..ef392ce 100644
> > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > @@ -56,6 +56,8 @@
> > > > > > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > > > > > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > > > > > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > > > > > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > > > > > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > > > > > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > > > > > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > > > > > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > index 15bcb4b..48f31c8 100644
> > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > @@ -10,10 +10,20 @@
> > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > > > > > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > > > > > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> > > > > >
> > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > > > > > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > > > > > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > > > > > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > > > > > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > > > > > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > > > > > @@ -25,6 +35,8 @@
> > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > > > > > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > > > > > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> > > > > >
> > > > > > #endif
> > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > index 3927eba..e0a01497 100644
> > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > +
> > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > > > > > +};
> > > > > > +
> > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > > > > > +};
> > > > > > +
> > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> > > > >
> > > > > Aside from moving these registers to the HS_G4 table, you are also
> > > > > changing these registers. It makes me think that there was an error in
> > > > > the original programming sequence.
> > > > > If that is correct, could you please split the patch into two pieces:
> > > > > - Fix programming sequence (add proper Fixes tags)
> > > > > - Split G4 and G5 tables.
> > > >
> > > > Ack
> > > >
> > > > >
> > > > > > +
> > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> > > > >
> > > > > I see all the MODE1 registers being only present in G4 and G5 tables.
> > > > > Should they be programmed for the modes lower than G4?
> > > > >
> > > >
> > > > We use G4 table for all the modes <= G4.
> > >
> > > Could you please point me how it's handled?
> > > In the patch I see just:
> > >
> > > if (qmp->submode == UFS_HS_G4)
> > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > > else if (qmp->submode == UFS_HS_G5)
> > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> > >
> > > Which looks like two special cases (HS_G4 and HS_G5) and nothing for
> > > anything else.
> > >
> >
> > Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
> > sequence will be used and for G5, G5 sequence will be used.
> >
>
> That's what I could not find in the UFS driver. I see a call to
> `phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
> host->phy_gear is initialised to UFS_HS_G2.
>
You need to check the UFS driver changes in this series to get the complete
picture as the logic is getting changed.
It is common to get confused because of the way the UFS driver (qcom mostly)
handles the PHY init sequence programming. We used to have only one init
sequence for older targets and life was easy. But when I wanted to add G4
support for SM8250, I learned that there are 2 separate init sequences. One for
non-G4 and other for G4. So I used the phy_sub_mode property to pass the
relevant mode from the UFS driver to the PHY driver and programmed the sequence
accordingly. This got extended to non-G5 and G5 now.
Now, the UFS driver will start probing from a low gear for older targets (G2)
and G4/G5 for newer ones then scale up based on the device and host capability.
For older targets, the common table (tbls) will be used if the submode doesn't
match G4/G5. But for newer targets, the UFS driver will _only_ pass G4 or G5 as
the phy_gear, so those specific sequence will only be used.
Hope I'm clear.
- Mani
> Maybe we should change the condition here (in the PHY driver) to:
>
> if (qmp->submode <= UFS_HS_G4)
>
> ?
> --
> With best wishes
> Dmitry
--
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^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-09 10:42 ` Manivannan Sadhasivam
@ 2023-11-09 11:00 ` Dmitry Baryshkov
-1 siblings, 0 replies; 86+ messages in thread
From: Dmitry Baryshkov @ 2023-11-09 11:00 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Can Guo, quic_cang, bvanassche, stanley.chu, adrian.hunter,
beanhuo, avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, open list:ARM/QUALCOMM SUPPORT,
open list:GENERIC PHY FRAMEWORK, open list
On Thu, 9 Nov 2023 at 12:43, Manivannan Sadhasivam <mani@kernel.org> wrote:
>
> On Thu, Nov 09, 2023 at 11:40:51AM +0200, Dmitry Baryshkov wrote:
> > On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > >
> > > On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
> > > > On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > >
> > > > > On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> > > > > > On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> > > > > > >
> > > > > > > From: Can Guo <quic_cang@quicinc.com>
> > > > > > >
> > > > > > > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > > > > > > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > > > > > > settings are programming different values to different registers, mixing
> > > > > > > the two sets and/or overwriting one set with another set is definitely not
> > > > > > > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > > > > > > need to split the two sets into their dedicated tables, and leave only the
> > > > > > > common settings in the .tlbs. To have the PHY programmed with the correct
> > > > > > > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > > > > > > or HS-G5.
> > > > > > >
> > > > >
> > > > > You should also mention that this issue is also present in G4 supported targets.
> > > > > And a note that it will get fixed later.
> > > > >
> > > > > > > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > > > > > > ---
> > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > > > > > > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > > > > > > 4 files changed, 115 insertions(+), 13 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > index c23d5e4..e563af5 100644
> > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > @@ -18,6 +18,7 @@
> > > > > > > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > > > > > > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > > > > > > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > > > > > > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > > > > > > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > > > > > > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > > > > > > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > > > > > > @@ -27,5 +28,6 @@
> > > > > > > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > > > > > > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > > > > > > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > > > > > > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> > > > > > >
> > > > > > > #endif
> > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > index f420f8f..ef392ce 100644
> > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > @@ -56,6 +56,8 @@
> > > > > > > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > > > > > > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > > > > > > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > > > > > > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > > > > > > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > > > > > > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > > > > > > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > > > > > > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > index 15bcb4b..48f31c8 100644
> > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > @@ -10,10 +10,20 @@
> > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > > > > > > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > > > > > > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> > > > > > >
> > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > > > > > > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > > > > > > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > > > > > > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > > > > > > @@ -25,6 +35,8 @@
> > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > > > > > > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > > > > > > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> > > > > > >
> > > > > > > #endif
> > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > index 3927eba..e0a01497 100644
> > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > +
> > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > > > > > > +};
> > > > > > > +
> > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > > > > > > +};
> > > > > > > +
> > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> > > > > >
> > > > > > Aside from moving these registers to the HS_G4 table, you are also
> > > > > > changing these registers. It makes me think that there was an error in
> > > > > > the original programming sequence.
> > > > > > If that is correct, could you please split the patch into two pieces:
> > > > > > - Fix programming sequence (add proper Fixes tags)
> > > > > > - Split G4 and G5 tables.
> > > > >
> > > > > Ack
> > > > >
> > > > > >
> > > > > > > +
> > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> > > > > >
> > > > > > I see all the MODE1 registers being only present in G4 and G5 tables.
> > > > > > Should they be programmed for the modes lower than G4?
> > > > > >
> > > > >
> > > > > We use G4 table for all the modes <= G4.
> > > >
> > > > Could you please point me how it's handled?
> > > > In the patch I see just:
> > > >
> > > > if (qmp->submode == UFS_HS_G4)
> > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > > > else if (qmp->submode == UFS_HS_G5)
> > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> > > >
> > > > Which looks like two special cases (HS_G4 and HS_G5) and nothing for
> > > > anything else.
> > > >
> > >
> > > Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
> > > sequence will be used and for G5, G5 sequence will be used.
> > >
> >
> > That's what I could not find in the UFS driver. I see a call to
> > `phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
> > host->phy_gear is initialised to UFS_HS_G2.
> >
>
> You need to check the UFS driver changes in this series to get the complete
> picture as the logic is getting changed.
>
> It is common to get confused because of the way the UFS driver (qcom mostly)
> handles the PHY init sequence programming. We used to have only one init
> sequence for older targets and life was easy. But when I wanted to add G4
> support for SM8250, I learned that there are 2 separate init sequences. One for
> non-G4 and other for G4. So I used the phy_sub_mode property to pass the
> relevant mode from the UFS driver to the PHY driver and programmed the sequence
> accordingly. This got extended to non-G5 and G5 now.
>
> Now, the UFS driver will start probing from a low gear for older targets (G2)
> and G4/G5 for newer ones then scale up based on the device and host capability.
> For older targets, the common table (tbls) will be used if the submode doesn't
> match G4/G5. But for newer targets, the UFS driver will _only_ pass G4 or G5 as
> the phy_gear, so those specific sequence will only be used.
>
> Hope I'm clear.
Yes, it is now clear, thank you!
Would it be possible / feasible / logical to maintain this idea even
for newer platforms (leaving the HS_A / HS_B aside)?
tbls - works for HS_G2
tbls + tbls_g4 - works for HS_G4
tbls + tbls_g5 - works for HS_G5
I mean here that the PHY driver should not depend on the knowledge
that the UFS driver will not be setting HS_G2 for some particular
platform and ideally it should continue working if at some point we
change the UFS driver to set HS_G2.
>
> - Mani
>
> > Maybe we should change the condition here (in the PHY driver) to:
> >
> > if (qmp->submode <= UFS_HS_G4)
> >
> > ?
> > --
> > With best wishes
> > Dmitry
>
> --
> மணிவண்ணன் சதாசிவம்
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-09 11:00 ` Dmitry Baryshkov
0 siblings, 0 replies; 86+ messages in thread
From: Dmitry Baryshkov @ 2023-11-09 11:00 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Can Guo, quic_cang, bvanassche, stanley.chu, adrian.hunter,
beanhuo, avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, open list:ARM/QUALCOMM SUPPORT,
open list:GENERIC PHY FRAMEWORK, open list
On Thu, 9 Nov 2023 at 12:43, Manivannan Sadhasivam <mani@kernel.org> wrote:
>
> On Thu, Nov 09, 2023 at 11:40:51AM +0200, Dmitry Baryshkov wrote:
> > On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > >
> > > On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
> > > > On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > >
> > > > > On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> > > > > > On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> > > > > > >
> > > > > > > From: Can Guo <quic_cang@quicinc.com>
> > > > > > >
> > > > > > > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > > > > > > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > > > > > > settings are programming different values to different registers, mixing
> > > > > > > the two sets and/or overwriting one set with another set is definitely not
> > > > > > > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > > > > > > need to split the two sets into their dedicated tables, and leave only the
> > > > > > > common settings in the .tlbs. To have the PHY programmed with the correct
> > > > > > > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > > > > > > or HS-G5.
> > > > > > >
> > > > >
> > > > > You should also mention that this issue is also present in G4 supported targets.
> > > > > And a note that it will get fixed later.
> > > > >
> > > > > > > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > > > > > > ---
> > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > > > > > > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > > > > > > 4 files changed, 115 insertions(+), 13 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > index c23d5e4..e563af5 100644
> > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > @@ -18,6 +18,7 @@
> > > > > > > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > > > > > > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > > > > > > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > > > > > > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > > > > > > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > > > > > > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > > > > > > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > > > > > > @@ -27,5 +28,6 @@
> > > > > > > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > > > > > > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > > > > > > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > > > > > > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> > > > > > >
> > > > > > > #endif
> > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > index f420f8f..ef392ce 100644
> > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > @@ -56,6 +56,8 @@
> > > > > > > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > > > > > > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > > > > > > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > > > > > > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > > > > > > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > > > > > > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > > > > > > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > > > > > > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > index 15bcb4b..48f31c8 100644
> > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > @@ -10,10 +10,20 @@
> > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > > > > > > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > > > > > > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> > > > > > >
> > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > > > > > > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > > > > > > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > > > > > > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > > > > > > @@ -25,6 +35,8 @@
> > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > > > > > > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > > > > > > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> > > > > > >
> > > > > > > #endif
> > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > index 3927eba..e0a01497 100644
> > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > +
> > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > > > > > > +};
> > > > > > > +
> > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > > > > > > +};
> > > > > > > +
> > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> > > > > >
> > > > > > Aside from moving these registers to the HS_G4 table, you are also
> > > > > > changing these registers. It makes me think that there was an error in
> > > > > > the original programming sequence.
> > > > > > If that is correct, could you please split the patch into two pieces:
> > > > > > - Fix programming sequence (add proper Fixes tags)
> > > > > > - Split G4 and G5 tables.
> > > > >
> > > > > Ack
> > > > >
> > > > > >
> > > > > > > +
> > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> > > > > >
> > > > > > I see all the MODE1 registers being only present in G4 and G5 tables.
> > > > > > Should they be programmed for the modes lower than G4?
> > > > > >
> > > > >
> > > > > We use G4 table for all the modes <= G4.
> > > >
> > > > Could you please point me how it's handled?
> > > > In the patch I see just:
> > > >
> > > > if (qmp->submode == UFS_HS_G4)
> > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > > > else if (qmp->submode == UFS_HS_G5)
> > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> > > >
> > > > Which looks like two special cases (HS_G4 and HS_G5) and nothing for
> > > > anything else.
> > > >
> > >
> > > Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
> > > sequence will be used and for G5, G5 sequence will be used.
> > >
> >
> > That's what I could not find in the UFS driver. I see a call to
> > `phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
> > host->phy_gear is initialised to UFS_HS_G2.
> >
>
> You need to check the UFS driver changes in this series to get the complete
> picture as the logic is getting changed.
>
> It is common to get confused because of the way the UFS driver (qcom mostly)
> handles the PHY init sequence programming. We used to have only one init
> sequence for older targets and life was easy. But when I wanted to add G4
> support for SM8250, I learned that there are 2 separate init sequences. One for
> non-G4 and other for G4. So I used the phy_sub_mode property to pass the
> relevant mode from the UFS driver to the PHY driver and programmed the sequence
> accordingly. This got extended to non-G5 and G5 now.
>
> Now, the UFS driver will start probing from a low gear for older targets (G2)
> and G4/G5 for newer ones then scale up based on the device and host capability.
> For older targets, the common table (tbls) will be used if the submode doesn't
> match G4/G5. But for newer targets, the UFS driver will _only_ pass G4 or G5 as
> the phy_gear, so those specific sequence will only be used.
>
> Hope I'm clear.
Yes, it is now clear, thank you!
Would it be possible / feasible / logical to maintain this idea even
for newer platforms (leaving the HS_A / HS_B aside)?
tbls - works for HS_G2
tbls + tbls_g4 - works for HS_G4
tbls + tbls_g5 - works for HS_G5
I mean here that the PHY driver should not depend on the knowledge
that the UFS driver will not be setting HS_G2 for some particular
platform and ideally it should continue working if at some point we
change the UFS driver to set HS_G2.
>
> - Mani
>
> > Maybe we should change the condition here (in the PHY driver) to:
> >
> > if (qmp->submode <= UFS_HS_G4)
> >
> > ?
> > --
> > With best wishes
> > Dmitry
>
> --
> மணிவண்ணன் சதாசிவம்
--
With best wishes
Dmitry
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-09 11:00 ` Dmitry Baryshkov
@ 2023-11-09 16:04 ` Manivannan Sadhasivam
-1 siblings, 0 replies; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-09 16:04 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Can Guo, quic_cang, bvanassche, stanley.chu, adrian.hunter,
beanhuo, avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, open list:ARM/QUALCOMM SUPPORT,
open list:GENERIC PHY FRAMEWORK, open list
On Thu, Nov 09, 2023 at 01:00:51PM +0200, Dmitry Baryshkov wrote:
> On Thu, 9 Nov 2023 at 12:43, Manivannan Sadhasivam <mani@kernel.org> wrote:
> >
> > On Thu, Nov 09, 2023 at 11:40:51AM +0200, Dmitry Baryshkov wrote:
> > > On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > >
> > > > On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
> > > > > On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > >
> > > > > > On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> > > > > > > On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> > > > > > > >
> > > > > > > > From: Can Guo <quic_cang@quicinc.com>
> > > > > > > >
> > > > > > > > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > > > > > > > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > > > > > > > settings are programming different values to different registers, mixing
> > > > > > > > the two sets and/or overwriting one set with another set is definitely not
> > > > > > > > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > > > > > > > need to split the two sets into their dedicated tables, and leave only the
> > > > > > > > common settings in the .tlbs. To have the PHY programmed with the correct
> > > > > > > > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > > > > > > > or HS-G5.
> > > > > > > >
> > > > > >
> > > > > > You should also mention that this issue is also present in G4 supported targets.
> > > > > > And a note that it will get fixed later.
> > > > > >
> > > > > > > > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > > > > > > > ---
> > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > > > > > > > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > > > > > > > 4 files changed, 115 insertions(+), 13 deletions(-)
> > > > > > > >
> > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > index c23d5e4..e563af5 100644
> > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > @@ -18,6 +18,7 @@
> > > > > > > > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > > > > > > > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > > > > > > > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > > > > > > > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > > > > > > > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > > > > > > > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > > > > > > > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > > > > > > > @@ -27,5 +28,6 @@
> > > > > > > > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > > > > > > > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > > > > > > > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > > > > > > > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> > > > > > > >
> > > > > > > > #endif
> > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > index f420f8f..ef392ce 100644
> > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > @@ -56,6 +56,8 @@
> > > > > > > > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > > > > > > > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > > > > > > > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > > > > > > > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > > > > > > > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > > > > > > > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > > > > > > > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > > > > > > > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > index 15bcb4b..48f31c8 100644
> > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > @@ -10,10 +10,20 @@
> > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > > > > > > > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > > > > > > > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> > > > > > > >
> > > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > > > > > > > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > > > > > > > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > > > > > > > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > > > > > > > @@ -25,6 +35,8 @@
> > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > > > > > > > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > > > > > > > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> > > > > > > >
> > > > > > > > #endif
> > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > index 3927eba..e0a01497 100644
> > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > > +
> > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > > > > > > > +};
> > > > > > > > +
> > > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > > > > > > > +};
> > > > > > > > +
> > > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> > > > > > >
> > > > > > > Aside from moving these registers to the HS_G4 table, you are also
> > > > > > > changing these registers. It makes me think that there was an error in
> > > > > > > the original programming sequence.
> > > > > > > If that is correct, could you please split the patch into two pieces:
> > > > > > > - Fix programming sequence (add proper Fixes tags)
> > > > > > > - Split G4 and G5 tables.
> > > > > >
> > > > > > Ack
> > > > > >
> > > > > > >
> > > > > > > > +
> > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> > > > > > >
> > > > > > > I see all the MODE1 registers being only present in G4 and G5 tables.
> > > > > > > Should they be programmed for the modes lower than G4?
> > > > > > >
> > > > > >
> > > > > > We use G4 table for all the modes <= G4.
> > > > >
> > > > > Could you please point me how it's handled?
> > > > > In the patch I see just:
> > > > >
> > > > > if (qmp->submode == UFS_HS_G4)
> > > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > > > > else if (qmp->submode == UFS_HS_G5)
> > > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> > > > >
> > > > > Which looks like two special cases (HS_G4 and HS_G5) and nothing for
> > > > > anything else.
> > > > >
> > > >
> > > > Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
> > > > sequence will be used and for G5, G5 sequence will be used.
> > > >
> > >
> > > That's what I could not find in the UFS driver. I see a call to
> > > `phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
> > > host->phy_gear is initialised to UFS_HS_G2.
> > >
> >
> > You need to check the UFS driver changes in this series to get the complete
> > picture as the logic is getting changed.
> >
> > It is common to get confused because of the way the UFS driver (qcom mostly)
> > handles the PHY init sequence programming. We used to have only one init
> > sequence for older targets and life was easy. But when I wanted to add G4
> > support for SM8250, I learned that there are 2 separate init sequences. One for
> > non-G4 and other for G4. So I used the phy_sub_mode property to pass the
> > relevant mode from the UFS driver to the PHY driver and programmed the sequence
> > accordingly. This got extended to non-G5 and G5 now.
> >
> > Now, the UFS driver will start probing from a low gear for older targets (G2)
> > and G4/G5 for newer ones then scale up based on the device and host capability.
> > For older targets, the common table (tbls) will be used if the submode doesn't
> > match G4/G5. But for newer targets, the UFS driver will _only_ pass G4 or G5 as
> > the phy_gear, so those specific sequence will only be used.
> >
> > Hope I'm clear.
>
> Yes, it is now clear, thank you!
>
> Would it be possible / feasible / logical to maintain this idea even
> for newer platforms (leaving the HS_A / HS_B aside)?
>
> tbls - works for HS_G2
> tbls + tbls_g4 - works for HS_G4
> tbls + tbls_g5 - works for HS_G5
>
No. The PHY team only gives 2 init sequences for any SoC now.
- Mani
> I mean here that the PHY driver should not depend on the knowledge
> that the UFS driver will not be setting HS_G2 for some particular
> platform and ideally it should continue working if at some point we
> change the UFS driver to set HS_G2.
>
>
> >
> > - Mani
> >
> > > Maybe we should change the condition here (in the PHY driver) to:
> > >
> > > if (qmp->submode <= UFS_HS_G4)
> > >
> > > ?
> > > --
> > > With best wishes
> > > Dmitry
> >
> > --
> > மணிவண்ணன் சதாசிவம்
>
>
>
> --
> With best wishes
> Dmitry
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-09 16:04 ` Manivannan Sadhasivam
0 siblings, 0 replies; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-09 16:04 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Can Guo, quic_cang, bvanassche, stanley.chu, adrian.hunter,
beanhuo, avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, open list:ARM/QUALCOMM SUPPORT,
open list:GENERIC PHY FRAMEWORK, open list
On Thu, Nov 09, 2023 at 01:00:51PM +0200, Dmitry Baryshkov wrote:
> On Thu, 9 Nov 2023 at 12:43, Manivannan Sadhasivam <mani@kernel.org> wrote:
> >
> > On Thu, Nov 09, 2023 at 11:40:51AM +0200, Dmitry Baryshkov wrote:
> > > On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > >
> > > > On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
> > > > > On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > >
> > > > > > On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> > > > > > > On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> > > > > > > >
> > > > > > > > From: Can Guo <quic_cang@quicinc.com>
> > > > > > > >
> > > > > > > > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > > > > > > > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > > > > > > > settings are programming different values to different registers, mixing
> > > > > > > > the two sets and/or overwriting one set with another set is definitely not
> > > > > > > > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > > > > > > > need to split the two sets into their dedicated tables, and leave only the
> > > > > > > > common settings in the .tlbs. To have the PHY programmed with the correct
> > > > > > > > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > > > > > > > or HS-G5.
> > > > > > > >
> > > > > >
> > > > > > You should also mention that this issue is also present in G4 supported targets.
> > > > > > And a note that it will get fixed later.
> > > > > >
> > > > > > > > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > > > > > > > ---
> > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > > > > > > > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > > > > > > > 4 files changed, 115 insertions(+), 13 deletions(-)
> > > > > > > >
> > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > index c23d5e4..e563af5 100644
> > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > @@ -18,6 +18,7 @@
> > > > > > > > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > > > > > > > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > > > > > > > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > > > > > > > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > > > > > > > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > > > > > > > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > > > > > > > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > > > > > > > @@ -27,5 +28,6 @@
> > > > > > > > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > > > > > > > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > > > > > > > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > > > > > > > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> > > > > > > >
> > > > > > > > #endif
> > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > index f420f8f..ef392ce 100644
> > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > @@ -56,6 +56,8 @@
> > > > > > > > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > > > > > > > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > > > > > > > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > > > > > > > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > > > > > > > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > > > > > > > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > > > > > > > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > > > > > > > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > index 15bcb4b..48f31c8 100644
> > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > @@ -10,10 +10,20 @@
> > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > > > > > > > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > > > > > > > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> > > > > > > >
> > > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > > > > > > > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > > > > > > > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > > > > > > > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > > > > > > > @@ -25,6 +35,8 @@
> > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > > > > > > > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > > > > > > > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> > > > > > > >
> > > > > > > > #endif
> > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > index 3927eba..e0a01497 100644
> > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > > +
> > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > > > > > > > +};
> > > > > > > > +
> > > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > > > > > > > +};
> > > > > > > > +
> > > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> > > > > > >
> > > > > > > Aside from moving these registers to the HS_G4 table, you are also
> > > > > > > changing these registers. It makes me think that there was an error in
> > > > > > > the original programming sequence.
> > > > > > > If that is correct, could you please split the patch into two pieces:
> > > > > > > - Fix programming sequence (add proper Fixes tags)
> > > > > > > - Split G4 and G5 tables.
> > > > > >
> > > > > > Ack
> > > > > >
> > > > > > >
> > > > > > > > +
> > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> > > > > > >
> > > > > > > I see all the MODE1 registers being only present in G4 and G5 tables.
> > > > > > > Should they be programmed for the modes lower than G4?
> > > > > > >
> > > > > >
> > > > > > We use G4 table for all the modes <= G4.
> > > > >
> > > > > Could you please point me how it's handled?
> > > > > In the patch I see just:
> > > > >
> > > > > if (qmp->submode == UFS_HS_G4)
> > > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > > > > else if (qmp->submode == UFS_HS_G5)
> > > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> > > > >
> > > > > Which looks like two special cases (HS_G4 and HS_G5) and nothing for
> > > > > anything else.
> > > > >
> > > >
> > > > Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
> > > > sequence will be used and for G5, G5 sequence will be used.
> > > >
> > >
> > > That's what I could not find in the UFS driver. I see a call to
> > > `phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
> > > host->phy_gear is initialised to UFS_HS_G2.
> > >
> >
> > You need to check the UFS driver changes in this series to get the complete
> > picture as the logic is getting changed.
> >
> > It is common to get confused because of the way the UFS driver (qcom mostly)
> > handles the PHY init sequence programming. We used to have only one init
> > sequence for older targets and life was easy. But when I wanted to add G4
> > support for SM8250, I learned that there are 2 separate init sequences. One for
> > non-G4 and other for G4. So I used the phy_sub_mode property to pass the
> > relevant mode from the UFS driver to the PHY driver and programmed the sequence
> > accordingly. This got extended to non-G5 and G5 now.
> >
> > Now, the UFS driver will start probing from a low gear for older targets (G2)
> > and G4/G5 for newer ones then scale up based on the device and host capability.
> > For older targets, the common table (tbls) will be used if the submode doesn't
> > match G4/G5. But for newer targets, the UFS driver will _only_ pass G4 or G5 as
> > the phy_gear, so those specific sequence will only be used.
> >
> > Hope I'm clear.
>
> Yes, it is now clear, thank you!
>
> Would it be possible / feasible / logical to maintain this idea even
> for newer platforms (leaving the HS_A / HS_B aside)?
>
> tbls - works for HS_G2
> tbls + tbls_g4 - works for HS_G4
> tbls + tbls_g5 - works for HS_G5
>
No. The PHY team only gives 2 init sequences for any SoC now.
- Mani
> I mean here that the PHY driver should not depend on the knowledge
> that the UFS driver will not be setting HS_G2 for some particular
> platform and ideally it should continue working if at some point we
> change the UFS driver to set HS_G2.
>
>
> >
> > - Mani
> >
> > > Maybe we should change the condition here (in the PHY driver) to:
> > >
> > > if (qmp->submode <= UFS_HS_G4)
> > >
> > > ?
> > > --
> > > With best wishes
> > > Dmitry
> >
> > --
> > மணிவண்ணன் சதாசிவம்
>
>
>
> --
> With best wishes
> Dmitry
--
மணிவண்ணன் சதாசிவம்
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-09 16:04 ` Manivannan Sadhasivam
@ 2023-11-09 22:11 ` Dmitry Baryshkov
-1 siblings, 0 replies; 86+ messages in thread
From: Dmitry Baryshkov @ 2023-11-09 22:11 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Can Guo, quic_cang, bvanassche, stanley.chu, adrian.hunter,
beanhuo, avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, open list:ARM/QUALCOMM SUPPORT,
open list:GENERIC PHY FRAMEWORK, open list
On Thu, 9 Nov 2023 at 18:04, Manivannan Sadhasivam <mani@kernel.org> wrote:
>
> On Thu, Nov 09, 2023 at 01:00:51PM +0200, Dmitry Baryshkov wrote:
> > On Thu, 9 Nov 2023 at 12:43, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > >
> > > On Thu, Nov 09, 2023 at 11:40:51AM +0200, Dmitry Baryshkov wrote:
> > > > On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > >
> > > > > On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
> > > > > > On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > > >
> > > > > > > On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> > > > > > > > On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> > > > > > > > >
> > > > > > > > > From: Can Guo <quic_cang@quicinc.com>
> > > > > > > > >
> > > > > > > > > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > > > > > > > > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > > > > > > > > settings are programming different values to different registers, mixing
> > > > > > > > > the two sets and/or overwriting one set with another set is definitely not
> > > > > > > > > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > > > > > > > > need to split the two sets into their dedicated tables, and leave only the
> > > > > > > > > common settings in the .tlbs. To have the PHY programmed with the correct
> > > > > > > > > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > > > > > > > > or HS-G5.
> > > > > > > > >
> > > > > > >
> > > > > > > You should also mention that this issue is also present in G4 supported targets.
> > > > > > > And a note that it will get fixed later.
> > > > > > >
> > > > > > > > > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > > > > > > > > ---
> > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > > > > > > > > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > > > > > > > > 4 files changed, 115 insertions(+), 13 deletions(-)
> > > > > > > > >
> > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > index c23d5e4..e563af5 100644
> > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > @@ -18,6 +18,7 @@
> > > > > > > > > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > > > > > > > > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > > > > > > > > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > > > > > > > > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > > > > > > > > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > > > > > > > > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > > > > > > > > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > > > > > > > > @@ -27,5 +28,6 @@
> > > > > > > > > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > > > > > > > > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > > > > > > > > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > > > > > > > > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> > > > > > > > >
> > > > > > > > > #endif
> > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > index f420f8f..ef392ce 100644
> > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > @@ -56,6 +56,8 @@
> > > > > > > > > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > > > > > > > > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > > > > > > > > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > > > > > > > > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > > > > > > > > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > > > > > > > > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > > > > > > > > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > > > > > > > > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > index 15bcb4b..48f31c8 100644
> > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > @@ -10,10 +10,20 @@
> > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > > > > > > > > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > > > > > > > > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> > > > > > > > >
> > > > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > > > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > > > > > > > > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > > > > > > > > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > > > > > > > > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > > > > > > > > @@ -25,6 +35,8 @@
> > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > > > > > > > > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > > > > > > > > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> > > > > > > > >
> > > > > > > > > #endif
> > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > index 3927eba..e0a01497 100644
> > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > > > +
> > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > > > > > > > > +};
> > > > > > > > > +
> > > > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > > > > > > > > +};
> > > > > > > > > +
> > > > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> > > > > > > >
> > > > > > > > Aside from moving these registers to the HS_G4 table, you are also
> > > > > > > > changing these registers. It makes me think that there was an error in
> > > > > > > > the original programming sequence.
> > > > > > > > If that is correct, could you please split the patch into two pieces:
> > > > > > > > - Fix programming sequence (add proper Fixes tags)
> > > > > > > > - Split G4 and G5 tables.
> > > > > > >
> > > > > > > Ack
> > > > > > >
> > > > > > > >
> > > > > > > > > +
> > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> > > > > > > >
> > > > > > > > I see all the MODE1 registers being only present in G4 and G5 tables.
> > > > > > > > Should they be programmed for the modes lower than G4?
> > > > > > > >
> > > > > > >
> > > > > > > We use G4 table for all the modes <= G4.
> > > > > >
> > > > > > Could you please point me how it's handled?
> > > > > > In the patch I see just:
> > > > > >
> > > > > > if (qmp->submode == UFS_HS_G4)
> > > > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > > > > > else if (qmp->submode == UFS_HS_G5)
> > > > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> > > > > >
> > > > > > Which looks like two special cases (HS_G4 and HS_G5) and nothing for
> > > > > > anything else.
> > > > > >
> > > > >
> > > > > Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
> > > > > sequence will be used and for G5, G5 sequence will be used.
> > > > >
> > > >
> > > > That's what I could not find in the UFS driver. I see a call to
> > > > `phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
> > > > host->phy_gear is initialised to UFS_HS_G2.
> > > >
> > >
> > > You need to check the UFS driver changes in this series to get the complete
> > > picture as the logic is getting changed.
> > >
> > > It is common to get confused because of the way the UFS driver (qcom mostly)
> > > handles the PHY init sequence programming. We used to have only one init
> > > sequence for older targets and life was easy. But when I wanted to add G4
> > > support for SM8250, I learned that there are 2 separate init sequences. One for
> > > non-G4 and other for G4. So I used the phy_sub_mode property to pass the
> > > relevant mode from the UFS driver to the PHY driver and programmed the sequence
> > > accordingly. This got extended to non-G5 and G5 now.
> > >
> > > Now, the UFS driver will start probing from a low gear for older targets (G2)
> > > and G4/G5 for newer ones then scale up based on the device and host capability.
> > > For older targets, the common table (tbls) will be used if the submode doesn't
> > > match G4/G5. But for newer targets, the UFS driver will _only_ pass G4 or G5 as
> > > the phy_gear, so those specific sequence will only be used.
> > >
> > > Hope I'm clear.
> >
> > Yes, it is now clear, thank you!
> >
> > Would it be possible / feasible / logical to maintain this idea even
> > for newer platforms (leaving the HS_A / HS_B aside)?
> >
> > tbls - works for HS_G2
> > tbls + tbls_g4 - works for HS_G4
> > tbls + tbls_g5 - works for HS_G5
> >
>
> No. The PHY team only gives 2 init sequences for any SoC now.
Ack. Then the code should become
if (HS_G5)
program(tbls_hs_g5)
else
program(tbls_hs_g4);
>
> - Mani
>
> > I mean here that the PHY driver should not depend on the knowledge
> > that the UFS driver will not be setting HS_G2 for some particular
> > platform and ideally it should continue working if at some point we
> > change the UFS driver to set HS_G2.
> >
> >
> > >
> > > - Mani
> > >
> > > > Maybe we should change the condition here (in the PHY driver) to:
> > > >
> > > > if (qmp->submode <= UFS_HS_G4)
> > > >
> > > > ?
> > > > --
> > > > With best wishes
> > > > Dmitry
> > >
> > > --
> > > மணிவண்ணன் சதாசிவம்
> >
> >
> >
> > --
> > With best wishes
> > Dmitry
>
> --
> மணிவண்ணன் சதாசிவம்
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-09 22:11 ` Dmitry Baryshkov
0 siblings, 0 replies; 86+ messages in thread
From: Dmitry Baryshkov @ 2023-11-09 22:11 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Can Guo, quic_cang, bvanassche, stanley.chu, adrian.hunter,
beanhuo, avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, open list:ARM/QUALCOMM SUPPORT,
open list:GENERIC PHY FRAMEWORK, open list
On Thu, 9 Nov 2023 at 18:04, Manivannan Sadhasivam <mani@kernel.org> wrote:
>
> On Thu, Nov 09, 2023 at 01:00:51PM +0200, Dmitry Baryshkov wrote:
> > On Thu, 9 Nov 2023 at 12:43, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > >
> > > On Thu, Nov 09, 2023 at 11:40:51AM +0200, Dmitry Baryshkov wrote:
> > > > On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > >
> > > > > On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
> > > > > > On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > > >
> > > > > > > On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> > > > > > > > On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> > > > > > > > >
> > > > > > > > > From: Can Guo <quic_cang@quicinc.com>
> > > > > > > > >
> > > > > > > > > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > > > > > > > > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > > > > > > > > settings are programming different values to different registers, mixing
> > > > > > > > > the two sets and/or overwriting one set with another set is definitely not
> > > > > > > > > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > > > > > > > > need to split the two sets into their dedicated tables, and leave only the
> > > > > > > > > common settings in the .tlbs. To have the PHY programmed with the correct
> > > > > > > > > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > > > > > > > > or HS-G5.
> > > > > > > > >
> > > > > > >
> > > > > > > You should also mention that this issue is also present in G4 supported targets.
> > > > > > > And a note that it will get fixed later.
> > > > > > >
> > > > > > > > > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > > > > > > > > ---
> > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > > > > > > > > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > > > > > > > > 4 files changed, 115 insertions(+), 13 deletions(-)
> > > > > > > > >
> > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > index c23d5e4..e563af5 100644
> > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > @@ -18,6 +18,7 @@
> > > > > > > > > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > > > > > > > > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > > > > > > > > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > > > > > > > > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > > > > > > > > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > > > > > > > > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > > > > > > > > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > > > > > > > > @@ -27,5 +28,6 @@
> > > > > > > > > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > > > > > > > > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > > > > > > > > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > > > > > > > > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> > > > > > > > >
> > > > > > > > > #endif
> > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > index f420f8f..ef392ce 100644
> > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > @@ -56,6 +56,8 @@
> > > > > > > > > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > > > > > > > > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > > > > > > > > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > > > > > > > > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > > > > > > > > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > > > > > > > > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > > > > > > > > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > > > > > > > > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > index 15bcb4b..48f31c8 100644
> > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > @@ -10,10 +10,20 @@
> > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > > > > > > > > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > > > > > > > > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> > > > > > > > >
> > > > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > > > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > > > > > > > > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > > > > > > > > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > > > > > > > > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > > > > > > > > @@ -25,6 +35,8 @@
> > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > > > > > > > > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > > > > > > > > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> > > > > > > > >
> > > > > > > > > #endif
> > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > index 3927eba..e0a01497 100644
> > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > > > +
> > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > > > > > > > > +};
> > > > > > > > > +
> > > > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > > > > > > > > +};
> > > > > > > > > +
> > > > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> > > > > > > >
> > > > > > > > Aside from moving these registers to the HS_G4 table, you are also
> > > > > > > > changing these registers. It makes me think that there was an error in
> > > > > > > > the original programming sequence.
> > > > > > > > If that is correct, could you please split the patch into two pieces:
> > > > > > > > - Fix programming sequence (add proper Fixes tags)
> > > > > > > > - Split G4 and G5 tables.
> > > > > > >
> > > > > > > Ack
> > > > > > >
> > > > > > > >
> > > > > > > > > +
> > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> > > > > > > >
> > > > > > > > I see all the MODE1 registers being only present in G4 and G5 tables.
> > > > > > > > Should they be programmed for the modes lower than G4?
> > > > > > > >
> > > > > > >
> > > > > > > We use G4 table for all the modes <= G4.
> > > > > >
> > > > > > Could you please point me how it's handled?
> > > > > > In the patch I see just:
> > > > > >
> > > > > > if (qmp->submode == UFS_HS_G4)
> > > > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > > > > > else if (qmp->submode == UFS_HS_G5)
> > > > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> > > > > >
> > > > > > Which looks like two special cases (HS_G4 and HS_G5) and nothing for
> > > > > > anything else.
> > > > > >
> > > > >
> > > > > Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
> > > > > sequence will be used and for G5, G5 sequence will be used.
> > > > >
> > > >
> > > > That's what I could not find in the UFS driver. I see a call to
> > > > `phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
> > > > host->phy_gear is initialised to UFS_HS_G2.
> > > >
> > >
> > > You need to check the UFS driver changes in this series to get the complete
> > > picture as the logic is getting changed.
> > >
> > > It is common to get confused because of the way the UFS driver (qcom mostly)
> > > handles the PHY init sequence programming. We used to have only one init
> > > sequence for older targets and life was easy. But when I wanted to add G4
> > > support for SM8250, I learned that there are 2 separate init sequences. One for
> > > non-G4 and other for G4. So I used the phy_sub_mode property to pass the
> > > relevant mode from the UFS driver to the PHY driver and programmed the sequence
> > > accordingly. This got extended to non-G5 and G5 now.
> > >
> > > Now, the UFS driver will start probing from a low gear for older targets (G2)
> > > and G4/G5 for newer ones then scale up based on the device and host capability.
> > > For older targets, the common table (tbls) will be used if the submode doesn't
> > > match G4/G5. But for newer targets, the UFS driver will _only_ pass G4 or G5 as
> > > the phy_gear, so those specific sequence will only be used.
> > >
> > > Hope I'm clear.
> >
> > Yes, it is now clear, thank you!
> >
> > Would it be possible / feasible / logical to maintain this idea even
> > for newer platforms (leaving the HS_A / HS_B aside)?
> >
> > tbls - works for HS_G2
> > tbls + tbls_g4 - works for HS_G4
> > tbls + tbls_g5 - works for HS_G5
> >
>
> No. The PHY team only gives 2 init sequences for any SoC now.
Ack. Then the code should become
if (HS_G5)
program(tbls_hs_g5)
else
program(tbls_hs_g4);
>
> - Mani
>
> > I mean here that the PHY driver should not depend on the knowledge
> > that the UFS driver will not be setting HS_G2 for some particular
> > platform and ideally it should continue working if at some point we
> > change the UFS driver to set HS_G2.
> >
> >
> > >
> > > - Mani
> > >
> > > > Maybe we should change the condition here (in the PHY driver) to:
> > > >
> > > > if (qmp->submode <= UFS_HS_G4)
> > > >
> > > > ?
> > > > --
> > > > With best wishes
> > > > Dmitry
> > >
> > > --
> > > மணிவண்ணன் சதாசிவம்
> >
> >
> >
> > --
> > With best wishes
> > Dmitry
>
> --
> மணிவண்ணன் சதாசிவம்
--
With best wishes
Dmitry
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-07 4:46 ` Can Guo
@ 2023-11-10 8:47 ` neil.armstrong
-1 siblings, 0 replies; 86+ messages in thread
From: neil.armstrong @ 2023-11-10 8:47 UTC (permalink / raw)
To: Can Guo, quic_cang, bvanassche, mani, stanley.chu, adrian.hunter,
beanhuo, avri.altman, junwoo80.lee, martin.petersen
Cc: linux-scsi, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
Hi,
On 07/11/2023 05:46, Can Guo wrote:
> From: Can Guo <quic_cang@quicinc.com>
>
> On SM8550, two sets of UFS PHY settings are provided, one set is to support
> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> settings are programming different values to different registers, mixing
> the two sets and/or overwriting one set with another set is definitely not
> blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> need to split the two sets into their dedicated tables, and leave only the
> common settings in the .tlbs. To have the PHY programmed with the correct
> set of PHY settings, the submode passed to PHY driver must be either HS-G4
> or HS-G5.
I guess I'll need to rebase my SM8650 UFS PHY driver to support both G4 and G5 modes
at some point ?
Neil
>
> Signed-off-by: Can Guo <quic_cang@quicinc.com>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> 4 files changed, 115 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> index c23d5e4..e563af5 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> @@ -18,6 +18,7 @@
> #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> @@ -27,5 +28,6 @@
> #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
>
> #endif
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> index f420f8f..ef392ce 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> @@ -56,6 +56,8 @@
> #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> #define QSERDES_V6_COM_PLL_IVCO 0xf4
> +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> index 15bcb4b..48f31c8 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> @@ -10,10 +10,20 @@
> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
>
> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> @@ -25,6 +35,8 @@
> #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
>
> #endif
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index 3927eba..e0a01497 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> +
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
> };
>
> static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
> - QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
> };
>
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
> +};
> +
> static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
>
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
> @@ -690,14 +709,46 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
> };
>
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
> +
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
> +};
> +
> static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> - QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> };
>
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
> +};
> +
> struct qmp_ufs_offsets {
> u16 serdes;
> u16 pcs;
> @@ -731,6 +782,8 @@ struct qmp_phy_cfg {
> const struct qmp_phy_cfg_tbls tbls_hs_b;
> /* Additional sequence for HS G4 */
> const struct qmp_phy_cfg_tbls tbls_hs_g4;
> + /* Additional sequence for HS G4 */
> + const struct qmp_phy_cfg_tbls tbls_hs_g5;
>
> /* clock ids to be requested */
> const char * const *clk_list;
> @@ -1157,6 +1210,28 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
> .pcs = sm8550_ufsphy_pcs,
> .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
> },
> + .tbls_hs_b = {
> + .serdes = sm8550_ufsphy_hs_b_serdes,
> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
> + },
> + .tbls_hs_g4 = {
> + .serdes = sm8550_ufsphy_g4_serdes,
> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
> + .tx = sm8550_ufsphy_g4_tx,
> + .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
> + .rx = sm8550_ufsphy_g4_rx,
> + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
> + .pcs = sm8550_ufsphy_g4_pcs,
> + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
> + },
> + .tbls_hs_g5 = {
> + .serdes = sm8550_ufsphy_g5_serdes,
> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
> + .rx = sm8550_ufsphy_g5_rx,
> + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
> + .pcs = sm8550_ufsphy_g5_pcs,
> + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
> + },
> .clk_list = sdm845_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> .vreg_list = qmp_phy_vreg_l,
> @@ -1222,14 +1297,25 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
> static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
> {
> qmp_ufs_serdes_init(qmp, &cfg->tbls);
> + if (qmp->submode == UFS_HS_G4)
> + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> + else if (qmp->submode == UFS_HS_G5)
> + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> +
> if (qmp->mode == PHY_MODE_UFS_HS_B)
> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
> +
> qmp_ufs_lanes_init(qmp, &cfg->tbls);
> if (qmp->submode == UFS_HS_G4)
> qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4);
> + else if (qmp->submode == UFS_HS_G5)
> + qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g5);
> +
> qmp_ufs_pcs_init(qmp, &cfg->tbls);
> if (qmp->submode == UFS_HS_G4)
> qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4);
> + else if (qmp->submode == UFS_HS_G5)
> + qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g5);
> }
>
> static int qmp_ufs_com_init(struct qmp_ufs *qmp)
--
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^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-10 8:47 ` neil.armstrong
0 siblings, 0 replies; 86+ messages in thread
From: neil.armstrong @ 2023-11-10 8:47 UTC (permalink / raw)
To: Can Guo, quic_cang, bvanassche, mani, stanley.chu, adrian.hunter,
beanhuo, avri.altman, junwoo80.lee, martin.petersen
Cc: linux-scsi, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
Hi,
On 07/11/2023 05:46, Can Guo wrote:
> From: Can Guo <quic_cang@quicinc.com>
>
> On SM8550, two sets of UFS PHY settings are provided, one set is to support
> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> settings are programming different values to different registers, mixing
> the two sets and/or overwriting one set with another set is definitely not
> blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> need to split the two sets into their dedicated tables, and leave only the
> common settings in the .tlbs. To have the PHY programmed with the correct
> set of PHY settings, the submode passed to PHY driver must be either HS-G4
> or HS-G5.
I guess I'll need to rebase my SM8650 UFS PHY driver to support both G4 and G5 modes
at some point ?
Neil
>
> Signed-off-by: Can Guo <quic_cang@quicinc.com>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> 4 files changed, 115 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> index c23d5e4..e563af5 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> @@ -18,6 +18,7 @@
> #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> @@ -27,5 +28,6 @@
> #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
>
> #endif
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> index f420f8f..ef392ce 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> @@ -56,6 +56,8 @@
> #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> #define QSERDES_V6_COM_PLL_IVCO 0xf4
> +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> index 15bcb4b..48f31c8 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> @@ -10,10 +10,20 @@
> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
>
> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> @@ -25,6 +35,8 @@
> #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
>
> #endif
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index 3927eba..e0a01497 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> +
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
> +
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
> };
>
> static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
> - QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
> };
>
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
> +};
> +
> static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
>
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
> @@ -690,14 +709,46 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
> };
>
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
> +
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
> +};
> +
> static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> - QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> };
>
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
> +};
> +
> struct qmp_ufs_offsets {
> u16 serdes;
> u16 pcs;
> @@ -731,6 +782,8 @@ struct qmp_phy_cfg {
> const struct qmp_phy_cfg_tbls tbls_hs_b;
> /* Additional sequence for HS G4 */
> const struct qmp_phy_cfg_tbls tbls_hs_g4;
> + /* Additional sequence for HS G4 */
> + const struct qmp_phy_cfg_tbls tbls_hs_g5;
>
> /* clock ids to be requested */
> const char * const *clk_list;
> @@ -1157,6 +1210,28 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
> .pcs = sm8550_ufsphy_pcs,
> .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
> },
> + .tbls_hs_b = {
> + .serdes = sm8550_ufsphy_hs_b_serdes,
> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
> + },
> + .tbls_hs_g4 = {
> + .serdes = sm8550_ufsphy_g4_serdes,
> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
> + .tx = sm8550_ufsphy_g4_tx,
> + .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
> + .rx = sm8550_ufsphy_g4_rx,
> + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
> + .pcs = sm8550_ufsphy_g4_pcs,
> + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
> + },
> + .tbls_hs_g5 = {
> + .serdes = sm8550_ufsphy_g5_serdes,
> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
> + .rx = sm8550_ufsphy_g5_rx,
> + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
> + .pcs = sm8550_ufsphy_g5_pcs,
> + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
> + },
> .clk_list = sdm845_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> .vreg_list = qmp_phy_vreg_l,
> @@ -1222,14 +1297,25 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
> static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
> {
> qmp_ufs_serdes_init(qmp, &cfg->tbls);
> + if (qmp->submode == UFS_HS_G4)
> + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> + else if (qmp->submode == UFS_HS_G5)
> + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> +
> if (qmp->mode == PHY_MODE_UFS_HS_B)
> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
> +
> qmp_ufs_lanes_init(qmp, &cfg->tbls);
> if (qmp->submode == UFS_HS_G4)
> qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4);
> + else if (qmp->submode == UFS_HS_G5)
> + qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g5);
> +
> qmp_ufs_pcs_init(qmp, &cfg->tbls);
> if (qmp->submode == UFS_HS_G4)
> qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4);
> + else if (qmp->submode == UFS_HS_G5)
> + qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g5);
> }
>
> static int qmp_ufs_com_init(struct qmp_ufs *qmp)
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-10 8:47 ` neil.armstrong
@ 2023-11-10 9:03 ` Can Guo
-1 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-10 9:03 UTC (permalink / raw)
To: neil.armstrong, Can Guo, bvanassche, mani, stanley.chu,
adrian.hunter, beanhuo, avri.altman, junwoo80.lee,
martin.petersen
Cc: linux-scsi, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
Hi Neil,
On 11/10/2023 4:47 PM, neil.armstrong@linaro.org wrote:
> Hi,
>
> On 07/11/2023 05:46, Can Guo wrote:
>> From: Can Guo <quic_cang@quicinc.com>
>>
>> On SM8550, two sets of UFS PHY settings are provided, one set is to
>> support
>> HS-G5, another set is to support HS-G4 and lower gears. The two sets
>> of PHY
>> settings are programming different values to different registers, mixing
>> the two sets and/or overwriting one set with another set is definitely
>> not
>> blessed by UFS PHY designers. In order to add HS-G5 support for
>> SM8550, we
>> need to split the two sets into their dedicated tables, and leave only
>> the
>> common settings in the .tlbs. To have the PHY programmed with the correct
>> set of PHY settings, the submode passed to PHY driver must be either
>> HS-G4
>> or HS-G5.
>
> I guess I'll need to rebase my SM8650 UFS PHY driver to support both G4
> and G5 modes
> at some point ?
Thank for reaching out. Yes, please.
I can help review the PHY settings.
BTW, are you enabling MCQ (by adding MCQ related DT) at the same time?
Thanks,
Can Guo.
>
> Neil
>
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-10 9:03 ` Can Guo
0 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-10 9:03 UTC (permalink / raw)
To: neil.armstrong, Can Guo, bvanassche, mani, stanley.chu,
adrian.hunter, beanhuo, avri.altman, junwoo80.lee,
martin.petersen
Cc: linux-scsi, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
Hi Neil,
On 11/10/2023 4:47 PM, neil.armstrong@linaro.org wrote:
> Hi,
>
> On 07/11/2023 05:46, Can Guo wrote:
>> From: Can Guo <quic_cang@quicinc.com>
>>
>> On SM8550, two sets of UFS PHY settings are provided, one set is to
>> support
>> HS-G5, another set is to support HS-G4 and lower gears. The two sets
>> of PHY
>> settings are programming different values to different registers, mixing
>> the two sets and/or overwriting one set with another set is definitely
>> not
>> blessed by UFS PHY designers. In order to add HS-G5 support for
>> SM8550, we
>> need to split the two sets into their dedicated tables, and leave only
>> the
>> common settings in the .tlbs. To have the PHY programmed with the correct
>> set of PHY settings, the submode passed to PHY driver must be either
>> HS-G4
>> or HS-G5.
>
> I guess I'll need to rebase my SM8650 UFS PHY driver to support both G4
> and G5 modes
> at some point ?
Thank for reaching out. Yes, please.
I can help review the PHY settings.
BTW, are you enabling MCQ (by adding MCQ related DT) at the same time?
Thanks,
Can Guo.
>
> Neil
>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-10 9:03 ` Can Guo
@ 2023-11-10 9:17 ` neil.armstrong
-1 siblings, 0 replies; 86+ messages in thread
From: neil.armstrong @ 2023-11-10 9:17 UTC (permalink / raw)
To: Can Guo, Can Guo, bvanassche, mani, stanley.chu, adrian.hunter,
beanhuo, avri.altman, junwoo80.lee, martin.petersen
Cc: linux-scsi, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
Hi,
On 10/11/2023 10:03, Can Guo wrote:
> Hi Neil,
>
> On 11/10/2023 4:47 PM, neil.armstrong@linaro.org wrote:
>> Hi,
>>
>> On 07/11/2023 05:46, Can Guo wrote:
>>> From: Can Guo <quic_cang@quicinc.com>
>>>
>>> On SM8550, two sets of UFS PHY settings are provided, one set is to support
>>> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
>>> settings are programming different values to different registers, mixing
>>> the two sets and/or overwriting one set with another set is definitely not
>>> blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
>>> need to split the two sets into their dedicated tables, and leave only the
>>> common settings in the .tlbs. To have the PHY programmed with the correct
>>> set of PHY settings, the submode passed to PHY driver must be either HS-G4
>>> or HS-G5.
>>
>> I guess I'll need to rebase my SM8650 UFS PHY driver to support both G4 and G5 modes
>> at some point ?
>
>
> Thank for reaching out. Yes, please.
>
> I can help review the PHY settings.
Ok I'll try rebasing on this serie and add G5 support.
>
> BTW, are you enabling MCQ (by adding MCQ related DT) at the same time?
I tested MCQ but it triggers the same issues we have with suspend/resume on SM8550 & SM8650,
and the bindings are not present of the UFS qcom node.
Neil
>
> Thanks,
> Can Guo.
>
>>
>> Neil
>>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-10 9:17 ` neil.armstrong
0 siblings, 0 replies; 86+ messages in thread
From: neil.armstrong @ 2023-11-10 9:17 UTC (permalink / raw)
To: Can Guo, Can Guo, bvanassche, mani, stanley.chu, adrian.hunter,
beanhuo, avri.altman, junwoo80.lee, martin.petersen
Cc: linux-scsi, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
Hi,
On 10/11/2023 10:03, Can Guo wrote:
> Hi Neil,
>
> On 11/10/2023 4:47 PM, neil.armstrong@linaro.org wrote:
>> Hi,
>>
>> On 07/11/2023 05:46, Can Guo wrote:
>>> From: Can Guo <quic_cang@quicinc.com>
>>>
>>> On SM8550, two sets of UFS PHY settings are provided, one set is to support
>>> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
>>> settings are programming different values to different registers, mixing
>>> the two sets and/or overwriting one set with another set is definitely not
>>> blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
>>> need to split the two sets into their dedicated tables, and leave only the
>>> common settings in the .tlbs. To have the PHY programmed with the correct
>>> set of PHY settings, the submode passed to PHY driver must be either HS-G4
>>> or HS-G5.
>>
>> I guess I'll need to rebase my SM8650 UFS PHY driver to support both G4 and G5 modes
>> at some point ?
>
>
> Thank for reaching out. Yes, please.
>
> I can help review the PHY settings.
Ok I'll try rebasing on this serie and add G5 support.
>
> BTW, are you enabling MCQ (by adding MCQ related DT) at the same time?
I tested MCQ but it triggers the same issues we have with suspend/resume on SM8550 & SM8650,
and the bindings are not present of the UFS qcom node.
Neil
>
> Thanks,
> Can Guo.
>
>>
>> Neil
>>
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-10 9:17 ` neil.armstrong
@ 2023-11-10 9:32 ` Can Guo
-1 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-10 9:32 UTC (permalink / raw)
To: neil.armstrong, Can Guo, bvanassche, mani, stanley.chu,
adrian.hunter, beanhuo, avri.altman, junwoo80.lee,
martin.petersen
Cc: linux-scsi, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
Hi Neil,
On 11/10/2023 5:17 PM, neil.armstrong@linaro.org wrote:
> Hi,
>
> On 10/11/2023 10:03, Can Guo wrote:
>> Hi Neil,
>>
>> On 11/10/2023 4:47 PM, neil.armstrong@linaro.org wrote:
>>> Hi,
>>>
>>> On 07/11/2023 05:46, Can Guo wrote:
>>>> From: Can Guo <quic_cang@quicinc.com>
>>>>
>>>> On SM8550, two sets of UFS PHY settings are provided, one set is to
>>>> support
>>>> HS-G5, another set is to support HS-G4 and lower gears. The two sets
>>>> of PHY
>>>> settings are programming different values to different registers,
>>>> mixing
>>>> the two sets and/or overwriting one set with another set is
>>>> definitely not
>>>> blessed by UFS PHY designers. In order to add HS-G5 support for
>>>> SM8550, we
>>>> need to split the two sets into their dedicated tables, and leave
>>>> only the
>>>> common settings in the .tlbs. To have the PHY programmed with the
>>>> correct
>>>> set of PHY settings, the submode passed to PHY driver must be either
>>>> HS-G4
>>>> or HS-G5.
>>>
>>> I guess I'll need to rebase my SM8650 UFS PHY driver to support both
>>> G4 and G5 modes
>>> at some point ?
>>
>>
>> Thank for reaching out. Yes, please.
>>
>> I can help review the PHY settings.
>
> Ok I'll try rebasing on this serie and add G5 support.
>
>>
>> BTW, are you enabling MCQ (by adding MCQ related DT) at the same time?
>
> I tested MCQ but it triggers the same issues we have with suspend/resume
> on SM8550 & SM8650,
> and the bindings are not present of the UFS qcom node.
Are you talking about suspend/resume fail with rpm/spm_lvl == 5? If yes,
then Nitin and Naveen are working on fixing it.
If you have plan to enable UFS MCQ on SM8650 later, please let me know,
I have some BUG fixes for it, we can co-work.
Thanks,
Can Guo
>
> Neil
>
>>
>> Thanks,
>> Can Guo.
>>
>>>
>>> Neil
>>>
>
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-10 9:32 ` Can Guo
0 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-10 9:32 UTC (permalink / raw)
To: neil.armstrong, Can Guo, bvanassche, mani, stanley.chu,
adrian.hunter, beanhuo, avri.altman, junwoo80.lee,
martin.petersen
Cc: linux-scsi, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
Hi Neil,
On 11/10/2023 5:17 PM, neil.armstrong@linaro.org wrote:
> Hi,
>
> On 10/11/2023 10:03, Can Guo wrote:
>> Hi Neil,
>>
>> On 11/10/2023 4:47 PM, neil.armstrong@linaro.org wrote:
>>> Hi,
>>>
>>> On 07/11/2023 05:46, Can Guo wrote:
>>>> From: Can Guo <quic_cang@quicinc.com>
>>>>
>>>> On SM8550, two sets of UFS PHY settings are provided, one set is to
>>>> support
>>>> HS-G5, another set is to support HS-G4 and lower gears. The two sets
>>>> of PHY
>>>> settings are programming different values to different registers,
>>>> mixing
>>>> the two sets and/or overwriting one set with another set is
>>>> definitely not
>>>> blessed by UFS PHY designers. In order to add HS-G5 support for
>>>> SM8550, we
>>>> need to split the two sets into their dedicated tables, and leave
>>>> only the
>>>> common settings in the .tlbs. To have the PHY programmed with the
>>>> correct
>>>> set of PHY settings, the submode passed to PHY driver must be either
>>>> HS-G4
>>>> or HS-G5.
>>>
>>> I guess I'll need to rebase my SM8650 UFS PHY driver to support both
>>> G4 and G5 modes
>>> at some point ?
>>
>>
>> Thank for reaching out. Yes, please.
>>
>> I can help review the PHY settings.
>
> Ok I'll try rebasing on this serie and add G5 support.
>
>>
>> BTW, are you enabling MCQ (by adding MCQ related DT) at the same time?
>
> I tested MCQ but it triggers the same issues we have with suspend/resume
> on SM8550 & SM8650,
> and the bindings are not present of the UFS qcom node.
Are you talking about suspend/resume fail with rpm/spm_lvl == 5? If yes,
then Nitin and Naveen are working on fixing it.
If you have plan to enable UFS MCQ on SM8650 later, please let me know,
I have some BUG fixes for it, we can co-work.
Thanks,
Can Guo
>
> Neil
>
>>
>> Thanks,
>> Can Guo.
>>
>>>
>>> Neil
>>>
>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-10 9:32 ` Can Guo
@ 2023-11-10 9:35 ` neil.armstrong
-1 siblings, 0 replies; 86+ messages in thread
From: neil.armstrong @ 2023-11-10 9:35 UTC (permalink / raw)
To: Can Guo, Can Guo, bvanassche, mani, stanley.chu, adrian.hunter,
beanhuo, avri.altman, junwoo80.lee, martin.petersen
Cc: linux-scsi, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
On 10/11/2023 10:32, Can Guo wrote:
> Hi Neil,
>
> On 11/10/2023 5:17 PM, neil.armstrong@linaro.org wrote:
>> Hi,
>>
>> On 10/11/2023 10:03, Can Guo wrote:
>>> Hi Neil,
>>>
>>> On 11/10/2023 4:47 PM, neil.armstrong@linaro.org wrote:
>>>> Hi,
>>>>
>>>> On 07/11/2023 05:46, Can Guo wrote:
>>>>> From: Can Guo <quic_cang@quicinc.com>
>>>>>
>>>>> On SM8550, two sets of UFS PHY settings are provided, one set is to support
>>>>> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
>>>>> settings are programming different values to different registers, mixing
>>>>> the two sets and/or overwriting one set with another set is definitely not
>>>>> blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
>>>>> need to split the two sets into their dedicated tables, and leave only the
>>>>> common settings in the .tlbs. To have the PHY programmed with the correct
>>>>> set of PHY settings, the submode passed to PHY driver must be either HS-G4
>>>>> or HS-G5.
>>>>
>>>> I guess I'll need to rebase my SM8650 UFS PHY driver to support both G4 and G5 modes
>>>> at some point ?
>>>
>>>
>>> Thank for reaching out. Yes, please.
>>>
>>> I can help review the PHY settings.
>>
>> Ok I'll try rebasing on this serie and add G5 support.
>>
>>>
>>> BTW, are you enabling MCQ (by adding MCQ related DT) at the same time?
>>
>> I tested MCQ but it triggers the same issues we have with suspend/resume on SM8550 & SM8650,
>> and the bindings are not present of the UFS qcom node.
>
> Are you talking about suspend/resume fail with rpm/spm_lvl == 5? If yes, then Nitin and Naveen are working on fixing it.
Exact, if you have some changes for me to test, I'll be happy to have a run on 8550 and 8650.
>
> If you have plan to enable UFS MCQ on SM8650 later, please let me know, I have some BUG fixes for it, we can co-work.
Yes I plan to when basic SM8650 support gets merged, same I'm able to test some changes if needed.
Neil
>
> Thanks,
> Can Guo
>
>>
>> Neil
>>
>>>
>>> Thanks,
>>> Can Guo.
>>>
>>>>
>>>> Neil
>>>>
>>
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-10 9:35 ` neil.armstrong
0 siblings, 0 replies; 86+ messages in thread
From: neil.armstrong @ 2023-11-10 9:35 UTC (permalink / raw)
To: Can Guo, Can Guo, bvanassche, mani, stanley.chu, adrian.hunter,
beanhuo, avri.altman, junwoo80.lee, martin.petersen
Cc: linux-scsi, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
On 10/11/2023 10:32, Can Guo wrote:
> Hi Neil,
>
> On 11/10/2023 5:17 PM, neil.armstrong@linaro.org wrote:
>> Hi,
>>
>> On 10/11/2023 10:03, Can Guo wrote:
>>> Hi Neil,
>>>
>>> On 11/10/2023 4:47 PM, neil.armstrong@linaro.org wrote:
>>>> Hi,
>>>>
>>>> On 07/11/2023 05:46, Can Guo wrote:
>>>>> From: Can Guo <quic_cang@quicinc.com>
>>>>>
>>>>> On SM8550, two sets of UFS PHY settings are provided, one set is to support
>>>>> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
>>>>> settings are programming different values to different registers, mixing
>>>>> the two sets and/or overwriting one set with another set is definitely not
>>>>> blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
>>>>> need to split the two sets into their dedicated tables, and leave only the
>>>>> common settings in the .tlbs. To have the PHY programmed with the correct
>>>>> set of PHY settings, the submode passed to PHY driver must be either HS-G4
>>>>> or HS-G5.
>>>>
>>>> I guess I'll need to rebase my SM8650 UFS PHY driver to support both G4 and G5 modes
>>>> at some point ?
>>>
>>>
>>> Thank for reaching out. Yes, please.
>>>
>>> I can help review the PHY settings.
>>
>> Ok I'll try rebasing on this serie and add G5 support.
>>
>>>
>>> BTW, are you enabling MCQ (by adding MCQ related DT) at the same time?
>>
>> I tested MCQ but it triggers the same issues we have with suspend/resume on SM8550 & SM8650,
>> and the bindings are not present of the UFS qcom node.
>
> Are you talking about suspend/resume fail with rpm/spm_lvl == 5? If yes, then Nitin and Naveen are working on fixing it.
Exact, if you have some changes for me to test, I'll be happy to have a run on 8550 and 8650.
>
> If you have plan to enable UFS MCQ on SM8650 later, please let me know, I have some BUG fixes for it, we can co-work.
Yes I plan to when basic SM8650 support gets merged, same I'm able to test some changes if needed.
Neil
>
> Thanks,
> Can Guo
>
>>
>> Neil
>>
>>>
>>> Thanks,
>>> Can Guo.
>>>
>>>>
>>>> Neil
>>>>
>>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-09 22:11 ` Dmitry Baryshkov
@ 2023-11-10 13:18 ` Manivannan Sadhasivam
-1 siblings, 0 replies; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-10 13:18 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Manivannan Sadhasivam, Can Guo, quic_cang, bvanassche,
stanley.chu, adrian.hunter, beanhuo, avri.altman, junwoo80.lee,
martin.petersen, linux-scsi, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
On Fri, Nov 10, 2023 at 12:11:46AM +0200, Dmitry Baryshkov wrote:
> On Thu, 9 Nov 2023 at 18:04, Manivannan Sadhasivam <mani@kernel.org> wrote:
> >
> > On Thu, Nov 09, 2023 at 01:00:51PM +0200, Dmitry Baryshkov wrote:
> > > On Thu, 9 Nov 2023 at 12:43, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > >
> > > > On Thu, Nov 09, 2023 at 11:40:51AM +0200, Dmitry Baryshkov wrote:
> > > > > On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > >
> > > > > > On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
> > > > > > > On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > > > >
> > > > > > > > On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> > > > > > > > > On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> > > > > > > > > >
> > > > > > > > > > From: Can Guo <quic_cang@quicinc.com>
> > > > > > > > > >
> > > > > > > > > > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > > > > > > > > > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > > > > > > > > > settings are programming different values to different registers, mixing
> > > > > > > > > > the two sets and/or overwriting one set with another set is definitely not
> > > > > > > > > > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > > > > > > > > > need to split the two sets into their dedicated tables, and leave only the
> > > > > > > > > > common settings in the .tlbs. To have the PHY programmed with the correct
> > > > > > > > > > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > > > > > > > > > or HS-G5.
> > > > > > > > > >
> > > > > > > >
> > > > > > > > You should also mention that this issue is also present in G4 supported targets.
> > > > > > > > And a note that it will get fixed later.
> > > > > > > >
> > > > > > > > > > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > > > > > > > > > ---
> > > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > > > > > > > > > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > > > > > > > > > 4 files changed, 115 insertions(+), 13 deletions(-)
> > > > > > > > > >
> > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > > index c23d5e4..e563af5 100644
> > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > > @@ -18,6 +18,7 @@
> > > > > > > > > > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > > > > > > > > > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > > > > > > > > > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > > > > > > > > > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > > > > > > > > > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > > > > > > > > > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > > > > > > > > > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > > > > > > > > > @@ -27,5 +28,6 @@
> > > > > > > > > > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > > > > > > > > > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > > > > > > > > > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > > > > > > > > > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> > > > > > > > > >
> > > > > > > > > > #endif
> > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > > index f420f8f..ef392ce 100644
> > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > > @@ -56,6 +56,8 @@
> > > > > > > > > > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > > > > > > > > > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > > > > > > > > > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > > > > > > > > > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > > > > > > > > > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > > > > > > > > > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > > > > > > > > > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > > > > > > > > > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > > index 15bcb4b..48f31c8 100644
> > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > > @@ -10,10 +10,20 @@
> > > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > > > > > > > > > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > > > > > > > > > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> > > > > > > > > >
> > > > > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > > > > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > > > > > > > > > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > > > > > > > > > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > > > > > > > > > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > > > > > > > > > @@ -25,6 +35,8 @@
> > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > > > > > > > > > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > > > > > > > > > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> > > > > > > > > >
> > > > > > > > > > #endif
> > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > > index 3927eba..e0a01497 100644
> > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > > > > +
> > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > > > > > > > > > +};
> > > > > > > > > > +
> > > > > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > > > > > > > > > +};
> > > > > > > > > > +
> > > > > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> > > > > > > > >
> > > > > > > > > Aside from moving these registers to the HS_G4 table, you are also
> > > > > > > > > changing these registers. It makes me think that there was an error in
> > > > > > > > > the original programming sequence.
> > > > > > > > > If that is correct, could you please split the patch into two pieces:
> > > > > > > > > - Fix programming sequence (add proper Fixes tags)
> > > > > > > > > - Split G4 and G5 tables.
> > > > > > > >
> > > > > > > > Ack
> > > > > > > >
> > > > > > > > >
> > > > > > > > > > +
> > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> > > > > > > > >
> > > > > > > > > I see all the MODE1 registers being only present in G4 and G5 tables.
> > > > > > > > > Should they be programmed for the modes lower than G4?
> > > > > > > > >
> > > > > > > >
> > > > > > > > We use G4 table for all the modes <= G4.
> > > > > > >
> > > > > > > Could you please point me how it's handled?
> > > > > > > In the patch I see just:
> > > > > > >
> > > > > > > if (qmp->submode == UFS_HS_G4)
> > > > > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > > > > > > else if (qmp->submode == UFS_HS_G5)
> > > > > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> > > > > > >
> > > > > > > Which looks like two special cases (HS_G4 and HS_G5) and nothing for
> > > > > > > anything else.
> > > > > > >
> > > > > >
> > > > > > Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
> > > > > > sequence will be used and for G5, G5 sequence will be used.
> > > > > >
> > > > >
> > > > > That's what I could not find in the UFS driver. I see a call to
> > > > > `phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
> > > > > host->phy_gear is initialised to UFS_HS_G2.
> > > > >
> > > >
> > > > You need to check the UFS driver changes in this series to get the complete
> > > > picture as the logic is getting changed.
> > > >
> > > > It is common to get confused because of the way the UFS driver (qcom mostly)
> > > > handles the PHY init sequence programming. We used to have only one init
> > > > sequence for older targets and life was easy. But when I wanted to add G4
> > > > support for SM8250, I learned that there are 2 separate init sequences. One for
> > > > non-G4 and other for G4. So I used the phy_sub_mode property to pass the
> > > > relevant mode from the UFS driver to the PHY driver and programmed the sequence
> > > > accordingly. This got extended to non-G5 and G5 now.
> > > >
> > > > Now, the UFS driver will start probing from a low gear for older targets (G2)
> > > > and G4/G5 for newer ones then scale up based on the device and host capability.
> > > > For older targets, the common table (tbls) will be used if the submode doesn't
> > > > match G4/G5. But for newer targets, the UFS driver will _only_ pass G4 or G5 as
> > > > the phy_gear, so those specific sequence will only be used.
> > > >
> > > > Hope I'm clear.
> > >
> > > Yes, it is now clear, thank you!
> > >
> > > Would it be possible / feasible / logical to maintain this idea even
> > > for newer platforms (leaving the HS_A / HS_B aside)?
> > >
> > > tbls - works for HS_G2
> > > tbls + tbls_g4 - works for HS_G4
> > > tbls + tbls_g5 - works for HS_G5
> > >
> >
> > No. The PHY team only gives 2 init sequences for any SoC now.
>
> Ack. Then the code should become
> if (HS_G5)
> program(tbls_hs_g5)
> else
> program(tbls_hs_g4);
>
This should work. Even if we have to accomodate G6 in the future, we can use
"else if" for that and keep G4 as the "else" condition. This logic can also be
optimized in the future.
- Mani
> >
> > - Mani
> >
> > > I mean here that the PHY driver should not depend on the knowledge
> > > that the UFS driver will not be setting HS_G2 for some particular
> > > platform and ideally it should continue working if at some point we
> > > change the UFS driver to set HS_G2.
> > >
> > >
> > > >
> > > > - Mani
> > > >
> > > > > Maybe we should change the condition here (in the PHY driver) to:
> > > > >
> > > > > if (qmp->submode <= UFS_HS_G4)
> > > > >
> > > > > ?
> > > > > --
> > > > > With best wishes
> > > > > Dmitry
> > > >
> > > > --
> > > > மணிவண்ணன் சதாசிவம்
> > >
> > >
> > >
> > > --
> > > With best wishes
> > > Dmitry
> >
> > --
> > மணிவண்ணன் சதாசிவம்
>
>
>
> --
> With best wishes
> Dmitry
--
மணிவண்ணன் சதாசிவம்
--
linux-phy mailing list
linux-phy@lists.infradead.org
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^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-10 13:18 ` Manivannan Sadhasivam
0 siblings, 0 replies; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-10 13:18 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Manivannan Sadhasivam, Can Guo, quic_cang, bvanassche,
stanley.chu, adrian.hunter, beanhuo, avri.altman, junwoo80.lee,
martin.petersen, linux-scsi, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
On Fri, Nov 10, 2023 at 12:11:46AM +0200, Dmitry Baryshkov wrote:
> On Thu, 9 Nov 2023 at 18:04, Manivannan Sadhasivam <mani@kernel.org> wrote:
> >
> > On Thu, Nov 09, 2023 at 01:00:51PM +0200, Dmitry Baryshkov wrote:
> > > On Thu, 9 Nov 2023 at 12:43, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > >
> > > > On Thu, Nov 09, 2023 at 11:40:51AM +0200, Dmitry Baryshkov wrote:
> > > > > On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > >
> > > > > > On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
> > > > > > > On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > > > >
> > > > > > > > On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> > > > > > > > > On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> > > > > > > > > >
> > > > > > > > > > From: Can Guo <quic_cang@quicinc.com>
> > > > > > > > > >
> > > > > > > > > > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > > > > > > > > > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > > > > > > > > > settings are programming different values to different registers, mixing
> > > > > > > > > > the two sets and/or overwriting one set with another set is definitely not
> > > > > > > > > > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > > > > > > > > > need to split the two sets into their dedicated tables, and leave only the
> > > > > > > > > > common settings in the .tlbs. To have the PHY programmed with the correct
> > > > > > > > > > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > > > > > > > > > or HS-G5.
> > > > > > > > > >
> > > > > > > >
> > > > > > > > You should also mention that this issue is also present in G4 supported targets.
> > > > > > > > And a note that it will get fixed later.
> > > > > > > >
> > > > > > > > > > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > > > > > > > > > ---
> > > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > > > > > > > > > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > > > > > > > > > 4 files changed, 115 insertions(+), 13 deletions(-)
> > > > > > > > > >
> > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > > index c23d5e4..e563af5 100644
> > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > > @@ -18,6 +18,7 @@
> > > > > > > > > > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > > > > > > > > > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > > > > > > > > > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > > > > > > > > > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > > > > > > > > > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > > > > > > > > > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > > > > > > > > > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > > > > > > > > > @@ -27,5 +28,6 @@
> > > > > > > > > > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > > > > > > > > > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > > > > > > > > > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > > > > > > > > > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> > > > > > > > > >
> > > > > > > > > > #endif
> > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > > index f420f8f..ef392ce 100644
> > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > > @@ -56,6 +56,8 @@
> > > > > > > > > > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > > > > > > > > > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > > > > > > > > > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > > > > > > > > > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > > > > > > > > > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > > > > > > > > > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > > > > > > > > > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > > > > > > > > > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > > index 15bcb4b..48f31c8 100644
> > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > > @@ -10,10 +10,20 @@
> > > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > > > > > > > > > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > > > > > > > > > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> > > > > > > > > >
> > > > > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > > > > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > > > > > > > > > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > > > > > > > > > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > > > > > > > > > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > > > > > > > > > @@ -25,6 +35,8 @@
> > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > > > > > > > > > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > > > > > > > > > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> > > > > > > > > >
> > > > > > > > > > #endif
> > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > > index 3927eba..e0a01497 100644
> > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > > > > +
> > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > > > > > > > > > +};
> > > > > > > > > > +
> > > > > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > > > > > > > > > +};
> > > > > > > > > > +
> > > > > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> > > > > > > > >
> > > > > > > > > Aside from moving these registers to the HS_G4 table, you are also
> > > > > > > > > changing these registers. It makes me think that there was an error in
> > > > > > > > > the original programming sequence.
> > > > > > > > > If that is correct, could you please split the patch into two pieces:
> > > > > > > > > - Fix programming sequence (add proper Fixes tags)
> > > > > > > > > - Split G4 and G5 tables.
> > > > > > > >
> > > > > > > > Ack
> > > > > > > >
> > > > > > > > >
> > > > > > > > > > +
> > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> > > > > > > > >
> > > > > > > > > I see all the MODE1 registers being only present in G4 and G5 tables.
> > > > > > > > > Should they be programmed for the modes lower than G4?
> > > > > > > > >
> > > > > > > >
> > > > > > > > We use G4 table for all the modes <= G4.
> > > > > > >
> > > > > > > Could you please point me how it's handled?
> > > > > > > In the patch I see just:
> > > > > > >
> > > > > > > if (qmp->submode == UFS_HS_G4)
> > > > > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > > > > > > else if (qmp->submode == UFS_HS_G5)
> > > > > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> > > > > > >
> > > > > > > Which looks like two special cases (HS_G4 and HS_G5) and nothing for
> > > > > > > anything else.
> > > > > > >
> > > > > >
> > > > > > Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
> > > > > > sequence will be used and for G5, G5 sequence will be used.
> > > > > >
> > > > >
> > > > > That's what I could not find in the UFS driver. I see a call to
> > > > > `phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
> > > > > host->phy_gear is initialised to UFS_HS_G2.
> > > > >
> > > >
> > > > You need to check the UFS driver changes in this series to get the complete
> > > > picture as the logic is getting changed.
> > > >
> > > > It is common to get confused because of the way the UFS driver (qcom mostly)
> > > > handles the PHY init sequence programming. We used to have only one init
> > > > sequence for older targets and life was easy. But when I wanted to add G4
> > > > support for SM8250, I learned that there are 2 separate init sequences. One for
> > > > non-G4 and other for G4. So I used the phy_sub_mode property to pass the
> > > > relevant mode from the UFS driver to the PHY driver and programmed the sequence
> > > > accordingly. This got extended to non-G5 and G5 now.
> > > >
> > > > Now, the UFS driver will start probing from a low gear for older targets (G2)
> > > > and G4/G5 for newer ones then scale up based on the device and host capability.
> > > > For older targets, the common table (tbls) will be used if the submode doesn't
> > > > match G4/G5. But for newer targets, the UFS driver will _only_ pass G4 or G5 as
> > > > the phy_gear, so those specific sequence will only be used.
> > > >
> > > > Hope I'm clear.
> > >
> > > Yes, it is now clear, thank you!
> > >
> > > Would it be possible / feasible / logical to maintain this idea even
> > > for newer platforms (leaving the HS_A / HS_B aside)?
> > >
> > > tbls - works for HS_G2
> > > tbls + tbls_g4 - works for HS_G4
> > > tbls + tbls_g5 - works for HS_G5
> > >
> >
> > No. The PHY team only gives 2 init sequences for any SoC now.
>
> Ack. Then the code should become
> if (HS_G5)
> program(tbls_hs_g5)
> else
> program(tbls_hs_g4);
>
This should work. Even if we have to accomodate G6 in the future, we can use
"else if" for that and keep G4 as the "else" condition. This logic can also be
optimized in the future.
- Mani
> >
> > - Mani
> >
> > > I mean here that the PHY driver should not depend on the knowledge
> > > that the UFS driver will not be setting HS_G2 for some particular
> > > platform and ideally it should continue working if at some point we
> > > change the UFS driver to set HS_G2.
> > >
> > >
> > > >
> > > > - Mani
> > > >
> > > > > Maybe we should change the condition here (in the PHY driver) to:
> > > > >
> > > > > if (qmp->submode <= UFS_HS_G4)
> > > > >
> > > > > ?
> > > > > --
> > > > > With best wishes
> > > > > Dmitry
> > > >
> > > > --
> > > > மணிவண்ணன் சதாசிவம்
> > >
> > >
> > >
> > > --
> > > With best wishes
> > > Dmitry
> >
> > --
> > மணிவண்ணன் சதாசிவம்
>
>
>
> --
> With best wishes
> Dmitry
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-10 13:18 ` Manivannan Sadhasivam
@ 2023-11-10 14:40 ` Can Guo
-1 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-10 14:40 UTC (permalink / raw)
To: Manivannan Sadhasivam, Dmitry Baryshkov
Cc: Can Guo, bvanassche, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, open list:ARM/QUALCOMM SUPPORT,
open list:GENERIC PHY FRAMEWORK, open list
On 11/10/2023 9:18 PM, Manivannan Sadhasivam wrote:
> On Fri, Nov 10, 2023 at 12:11:46AM +0200, Dmitry Baryshkov wrote:
>> On Thu, 9 Nov 2023 at 18:04, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>
>>> On Thu, Nov 09, 2023 at 01:00:51PM +0200, Dmitry Baryshkov wrote:
>>>> On Thu, 9 Nov 2023 at 12:43, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>>>
>>>>> On Thu, Nov 09, 2023 at 11:40:51AM +0200, Dmitry Baryshkov wrote:
>>>>>> On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>>>>>
>>>>>>> On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
>>>>>>>> On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>>>>>>>
>>>>>>>>> On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
>>>>>>>>>> On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
>>>>>>>>>>>
>>>>>>>>>>> From: Can Guo <quic_cang@quicinc.com>
>>>>>>>>>>>
>>>>>>>>>>> On SM8550, two sets of UFS PHY settings are provided, one set is to support
>>>>>>>>>>> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
>>>>>>>>>>> settings are programming different values to different registers, mixing
>>>>>>>>>>> the two sets and/or overwriting one set with another set is definitely not
>>>>>>>>>>> blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
>>>>>>>>>>> need to split the two sets into their dedicated tables, and leave only the
>>>>>>>>>>> common settings in the .tlbs. To have the PHY programmed with the correct
>>>>>>>>>>> set of PHY settings, the submode passed to PHY driver must be either HS-G4
>>>>>>>>>>> or HS-G5.
>>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> You should also mention that this issue is also present in G4 supported targets.
>>>>>>>>> And a note that it will get fixed later.
>>>>>>>>>
>>>>>>>>>>> Signed-off-by: Can Guo <quic_cang@quicinc.com>
>>>>>>>>>>> ---
>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
>>>>>>>>>>> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
>>>>>>>>>>> 4 files changed, 115 insertions(+), 13 deletions(-)
>>>>>>>>>>>
>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>>>>>>>>>> index c23d5e4..e563af5 100644
>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>>>>>>>>>> @@ -18,6 +18,7 @@
>>>>>>>>>>> #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
>>>>>>>>>>> #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
>>>>>>>>>>> #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
>>>>>>>>>>> +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
>>>>>>>>>>> #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
>>>>>>>>>>> #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
>>>>>>>>>>> #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
>>>>>>>>>>> @@ -27,5 +28,6 @@
>>>>>>>>>>> #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
>>>>>>>>>>> #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
>>>>>>>>>>> #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
>>>>>>>>>>> +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
>>>>>>>>>>>
>>>>>>>>>>> #endif
>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>>>>>>>>> index f420f8f..ef392ce 100644
>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>>>>>>>>> @@ -56,6 +56,8 @@
>>>>>>>>>>> #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
>>>>>>>>>>> #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
>>>>>>>>>>> #define QSERDES_V6_COM_PLL_IVCO 0xf4
>>>>>>>>>>> +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
>>>>>>>>>>> +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
>>>>>>>>>>> #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
>>>>>>>>>>> #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
>>>>>>>>>>> #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>>>>>>>>>> index 15bcb4b..48f31c8 100644
>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>>>>>>>>>> @@ -10,10 +10,20 @@
>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
>>>>>>>>>>> +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
>>>>>>>>>>> +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
>>>>>>>>>>>
>>>>>>>>>>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
>>>>>>>>>>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
>>>>>>>>>>> #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
>>>>>>>>>>> @@ -25,6 +35,8 @@
>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
>>>>>>>>>>>
>>>>>>>>>>> #endif
>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>>>>>>>> index 3927eba..e0a01497 100644
>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>>>>>>>> @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
>>>>>>>>>>> +
>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
>>>>>>>>>>> +};
>>>>>>>>>>> +
>>>>>>>>>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
>>>>>>>>>>> +};
>>>>>>>>>>> +
>>>>>>>>>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
>>>>>>>>>>
>>>>>>>>>> Aside from moving these registers to the HS_G4 table, you are also
>>>>>>>>>> changing these registers. It makes me think that there was an error in
>>>>>>>>>> the original programming sequence.
>>>>>>>>>> If that is correct, could you please split the patch into two pieces:
>>>>>>>>>> - Fix programming sequence (add proper Fixes tags)
>>>>>>>>>> - Split G4 and G5 tables.
>>>>>>>>>
>>>>>>>>> Ack
>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>> +
>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
>>>>>>>>>>
>>>>>>>>>> I see all the MODE1 registers being only present in G4 and G5 tables.
>>>>>>>>>> Should they be programmed for the modes lower than G4?
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> We use G4 table for all the modes <= G4.
>>>>>>>>
>>>>>>>> Could you please point me how it's handled?
>>>>>>>> In the patch I see just:
>>>>>>>>
>>>>>>>> if (qmp->submode == UFS_HS_G4)
>>>>>>>> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
>>>>>>>> else if (qmp->submode == UFS_HS_G5)
>>>>>>>> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
>>>>>>>>
>>>>>>>> Which looks like two special cases (HS_G4 and HS_G5) and nothing for
>>>>>>>> anything else.
>>>>>>>>
>>>>>>>
>>>>>>> Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
>>>>>>> sequence will be used and for G5, G5 sequence will be used.
>>>>>>>
>>>>>>
>>>>>> That's what I could not find in the UFS driver. I see a call to
>>>>>> `phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
>>>>>> host->phy_gear is initialised to UFS_HS_G2.
>>>>>>
>>>>>
>>>>> You need to check the UFS driver changes in this series to get the complete
>>>>> picture as the logic is getting changed.
>>>>>
>>>>> It is common to get confused because of the way the UFS driver (qcom mostly)
>>>>> handles the PHY init sequence programming. We used to have only one init
>>>>> sequence for older targets and life was easy. But when I wanted to add G4
>>>>> support for SM8250, I learned that there are 2 separate init sequences. One for
>>>>> non-G4 and other for G4. So I used the phy_sub_mode property to pass the
>>>>> relevant mode from the UFS driver to the PHY driver and programmed the sequence
>>>>> accordingly. This got extended to non-G5 and G5 now.
>>>>>
>>>>> Now, the UFS driver will start probing from a low gear for older targets (G2)
>>>>> and G4/G5 for newer ones then scale up based on the device and host capability.
>>>>> For older targets, the common table (tbls) will be used if the submode doesn't
>>>>> match G4/G5. But for newer targets, the UFS driver will _only_ pass G4 or G5 as
>>>>> the phy_gear, so those specific sequence will only be used.
>>>>>
>>>>> Hope I'm clear.
>>>>
>>>> Yes, it is now clear, thank you!
>>>>
>>>> Would it be possible / feasible / logical to maintain this idea even
>>>> for newer platforms (leaving the HS_A / HS_B aside)?
>>>>
>>>> tbls - works for HS_G2
>>>> tbls + tbls_g4 - works for HS_G4
>>>> tbls + tbls_g5 - works for HS_G5
>>>>
>>>
>>> No. The PHY team only gives 2 init sequences for any SoC now.
>>
>> Ack. Then the code should become
>> if (HS_G5)
>> program(tbls_hs_g5)
>> else
>> program(tbls_hs_g4);
>>
>
> This should work. Even if we have to accomodate G6 in the future, we can use
> "else if" for that and keep G4 as the "else" condition. This logic can also be
> optimized in the future.
That would make dual init meaningless for old targets. Say on SM8450,
the initial PHY gear is G2, with the "else" condition, during the first
init, G4 table would be programmed, then gear negotiation happens btw
host and device and the negotiated gear is G3 (assume a UFS2.x is
connected). During the 2nd init, the "else" condition would __again__
program the G4 table - it is not programming the non-G4 table for power
saving. The dual init is supposed to find the optimal PHY settings, but
the "else" condition is programming G4 table unconditinally.
With the original code change in this patch, the dual init works as it
is for old targets. say SM8450, the initial PHY gear is G2, during the
2nd init, it is programming the non-G4 table (assume a UFS2.x is
connected), but not the G4 table.
Thanks,
Can Guo.
>
> - Mani
>
>>>
>>> - Mani
>>>
>>>> I mean here that the PHY driver should not depend on the knowledge
>>>> that the UFS driver will not be setting HS_G2 for some particular
>>>> platform and ideally it should continue working if at some point we
>>>> change the UFS driver to set HS_G2.
>>>>
>>>>
>>>>>
>>>>> - Mani
>>>>>
>>>>>> Maybe we should change the condition here (in the PHY driver) to:
>>>>>>
>>>>>> if (qmp->submode <= UFS_HS_G4)
>>>>>>
>>>>>> ?
>>>>>> --
>>>>>> With best wishes
>>>>>> Dmitry
>>>>>
>>>>> --
>>>>> மணிவண்ணன் சதாசிவம்
>>>>
>>>>
>>>>
>>>> --
>>>> With best wishes
>>>> Dmitry
>>>
>>> --
>>> மணிவண்ணன் சதாசிவம்
>>
>>
>>
>> --
>> With best wishes
>> Dmitry
>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-10 14:40 ` Can Guo
0 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-10 14:40 UTC (permalink / raw)
To: Manivannan Sadhasivam, Dmitry Baryshkov
Cc: Can Guo, bvanassche, stanley.chu, adrian.hunter, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, linux-scsi,
Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, open list:ARM/QUALCOMM SUPPORT,
open list:GENERIC PHY FRAMEWORK, open list
On 11/10/2023 9:18 PM, Manivannan Sadhasivam wrote:
> On Fri, Nov 10, 2023 at 12:11:46AM +0200, Dmitry Baryshkov wrote:
>> On Thu, 9 Nov 2023 at 18:04, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>
>>> On Thu, Nov 09, 2023 at 01:00:51PM +0200, Dmitry Baryshkov wrote:
>>>> On Thu, 9 Nov 2023 at 12:43, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>>>
>>>>> On Thu, Nov 09, 2023 at 11:40:51AM +0200, Dmitry Baryshkov wrote:
>>>>>> On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>>>>>
>>>>>>> On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
>>>>>>>> On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>>>>>>>
>>>>>>>>> On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
>>>>>>>>>> On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
>>>>>>>>>>>
>>>>>>>>>>> From: Can Guo <quic_cang@quicinc.com>
>>>>>>>>>>>
>>>>>>>>>>> On SM8550, two sets of UFS PHY settings are provided, one set is to support
>>>>>>>>>>> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
>>>>>>>>>>> settings are programming different values to different registers, mixing
>>>>>>>>>>> the two sets and/or overwriting one set with another set is definitely not
>>>>>>>>>>> blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
>>>>>>>>>>> need to split the two sets into their dedicated tables, and leave only the
>>>>>>>>>>> common settings in the .tlbs. To have the PHY programmed with the correct
>>>>>>>>>>> set of PHY settings, the submode passed to PHY driver must be either HS-G4
>>>>>>>>>>> or HS-G5.
>>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> You should also mention that this issue is also present in G4 supported targets.
>>>>>>>>> And a note that it will get fixed later.
>>>>>>>>>
>>>>>>>>>>> Signed-off-by: Can Guo <quic_cang@quicinc.com>
>>>>>>>>>>> ---
>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
>>>>>>>>>>> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
>>>>>>>>>>> 4 files changed, 115 insertions(+), 13 deletions(-)
>>>>>>>>>>>
>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>>>>>>>>>> index c23d5e4..e563af5 100644
>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>>>>>>>>>> @@ -18,6 +18,7 @@
>>>>>>>>>>> #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
>>>>>>>>>>> #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
>>>>>>>>>>> #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
>>>>>>>>>>> +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
>>>>>>>>>>> #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
>>>>>>>>>>> #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
>>>>>>>>>>> #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
>>>>>>>>>>> @@ -27,5 +28,6 @@
>>>>>>>>>>> #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
>>>>>>>>>>> #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
>>>>>>>>>>> #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
>>>>>>>>>>> +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
>>>>>>>>>>>
>>>>>>>>>>> #endif
>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>>>>>>>>> index f420f8f..ef392ce 100644
>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>>>>>>>>> @@ -56,6 +56,8 @@
>>>>>>>>>>> #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
>>>>>>>>>>> #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
>>>>>>>>>>> #define QSERDES_V6_COM_PLL_IVCO 0xf4
>>>>>>>>>>> +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
>>>>>>>>>>> +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
>>>>>>>>>>> #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
>>>>>>>>>>> #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
>>>>>>>>>>> #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>>>>>>>>>> index 15bcb4b..48f31c8 100644
>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>>>>>>>>>> @@ -10,10 +10,20 @@
>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
>>>>>>>>>>> +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
>>>>>>>>>>> +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
>>>>>>>>>>>
>>>>>>>>>>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
>>>>>>>>>>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
>>>>>>>>>>> #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
>>>>>>>>>>> @@ -25,6 +35,8 @@
>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
>>>>>>>>>>>
>>>>>>>>>>> #endif
>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>>>>>>>> index 3927eba..e0a01497 100644
>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>>>>>>>> @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
>>>>>>>>>>> +
>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
>>>>>>>>>>> +};
>>>>>>>>>>> +
>>>>>>>>>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
>>>>>>>>>>> +};
>>>>>>>>>>> +
>>>>>>>>>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
>>>>>>>>>>
>>>>>>>>>> Aside from moving these registers to the HS_G4 table, you are also
>>>>>>>>>> changing these registers. It makes me think that there was an error in
>>>>>>>>>> the original programming sequence.
>>>>>>>>>> If that is correct, could you please split the patch into two pieces:
>>>>>>>>>> - Fix programming sequence (add proper Fixes tags)
>>>>>>>>>> - Split G4 and G5 tables.
>>>>>>>>>
>>>>>>>>> Ack
>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>> +
>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
>>>>>>>>>>
>>>>>>>>>> I see all the MODE1 registers being only present in G4 and G5 tables.
>>>>>>>>>> Should they be programmed for the modes lower than G4?
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> We use G4 table for all the modes <= G4.
>>>>>>>>
>>>>>>>> Could you please point me how it's handled?
>>>>>>>> In the patch I see just:
>>>>>>>>
>>>>>>>> if (qmp->submode == UFS_HS_G4)
>>>>>>>> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
>>>>>>>> else if (qmp->submode == UFS_HS_G5)
>>>>>>>> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
>>>>>>>>
>>>>>>>> Which looks like two special cases (HS_G4 and HS_G5) and nothing for
>>>>>>>> anything else.
>>>>>>>>
>>>>>>>
>>>>>>> Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
>>>>>>> sequence will be used and for G5, G5 sequence will be used.
>>>>>>>
>>>>>>
>>>>>> That's what I could not find in the UFS driver. I see a call to
>>>>>> `phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
>>>>>> host->phy_gear is initialised to UFS_HS_G2.
>>>>>>
>>>>>
>>>>> You need to check the UFS driver changes in this series to get the complete
>>>>> picture as the logic is getting changed.
>>>>>
>>>>> It is common to get confused because of the way the UFS driver (qcom mostly)
>>>>> handles the PHY init sequence programming. We used to have only one init
>>>>> sequence for older targets and life was easy. But when I wanted to add G4
>>>>> support for SM8250, I learned that there are 2 separate init sequences. One for
>>>>> non-G4 and other for G4. So I used the phy_sub_mode property to pass the
>>>>> relevant mode from the UFS driver to the PHY driver and programmed the sequence
>>>>> accordingly. This got extended to non-G5 and G5 now.
>>>>>
>>>>> Now, the UFS driver will start probing from a low gear for older targets (G2)
>>>>> and G4/G5 for newer ones then scale up based on the device and host capability.
>>>>> For older targets, the common table (tbls) will be used if the submode doesn't
>>>>> match G4/G5. But for newer targets, the UFS driver will _only_ pass G4 or G5 as
>>>>> the phy_gear, so those specific sequence will only be used.
>>>>>
>>>>> Hope I'm clear.
>>>>
>>>> Yes, it is now clear, thank you!
>>>>
>>>> Would it be possible / feasible / logical to maintain this idea even
>>>> for newer platforms (leaving the HS_A / HS_B aside)?
>>>>
>>>> tbls - works for HS_G2
>>>> tbls + tbls_g4 - works for HS_G4
>>>> tbls + tbls_g5 - works for HS_G5
>>>>
>>>
>>> No. The PHY team only gives 2 init sequences for any SoC now.
>>
>> Ack. Then the code should become
>> if (HS_G5)
>> program(tbls_hs_g5)
>> else
>> program(tbls_hs_g4);
>>
>
> This should work. Even if we have to accomodate G6 in the future, we can use
> "else if" for that and keep G4 as the "else" condition. This logic can also be
> optimized in the future.
That would make dual init meaningless for old targets. Say on SM8450,
the initial PHY gear is G2, with the "else" condition, during the first
init, G4 table would be programmed, then gear negotiation happens btw
host and device and the negotiated gear is G3 (assume a UFS2.x is
connected). During the 2nd init, the "else" condition would __again__
program the G4 table - it is not programming the non-G4 table for power
saving. The dual init is supposed to find the optimal PHY settings, but
the "else" condition is programming G4 table unconditinally.
With the original code change in this patch, the dual init works as it
is for old targets. say SM8450, the initial PHY gear is G2, during the
2nd init, it is programming the non-G4 table (assume a UFS2.x is
connected), but not the G4 table.
Thanks,
Can Guo.
>
> - Mani
>
>>>
>>> - Mani
>>>
>>>> I mean here that the PHY driver should not depend on the knowledge
>>>> that the UFS driver will not be setting HS_G2 for some particular
>>>> platform and ideally it should continue working if at some point we
>>>> change the UFS driver to set HS_G2.
>>>>
>>>>
>>>>>
>>>>> - Mani
>>>>>
>>>>>> Maybe we should change the condition here (in the PHY driver) to:
>>>>>>
>>>>>> if (qmp->submode <= UFS_HS_G4)
>>>>>>
>>>>>> ?
>>>>>> --
>>>>>> With best wishes
>>>>>> Dmitry
>>>>>
>>>>> --
>>>>> மணிவண்ணன் சதாசிவம்
>>>>
>>>>
>>>>
>>>> --
>>>> With best wishes
>>>> Dmitry
>>>
>>> --
>>> மணிவண்ணன் சதாசிவம்
>>
>>
>>
>> --
>> With best wishes
>> Dmitry
>
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-10 14:40 ` Can Guo
@ 2023-11-11 4:12 ` Manivannan Sadhasivam
-1 siblings, 0 replies; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-11 4:12 UTC (permalink / raw)
To: Can Guo
Cc: Manivannan Sadhasivam, Dmitry Baryshkov, Can Guo, bvanassche,
stanley.chu, adrian.hunter, beanhuo, avri.altman, junwoo80.lee,
martin.petersen, linux-scsi, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
On Fri, Nov 10, 2023 at 10:40:53PM +0800, Can Guo wrote:
>
>
> On 11/10/2023 9:18 PM, Manivannan Sadhasivam wrote:
> > On Fri, Nov 10, 2023 at 12:11:46AM +0200, Dmitry Baryshkov wrote:
> > > On Thu, 9 Nov 2023 at 18:04, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > >
> > > > On Thu, Nov 09, 2023 at 01:00:51PM +0200, Dmitry Baryshkov wrote:
> > > > > On Thu, 9 Nov 2023 at 12:43, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > >
> > > > > > On Thu, Nov 09, 2023 at 11:40:51AM +0200, Dmitry Baryshkov wrote:
> > > > > > > On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > > > >
> > > > > > > > On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
> > > > > > > > > On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > > > > > >
> > > > > > > > > > On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> > > > > > > > > > > On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> > > > > > > > > > > >
> > > > > > > > > > > > From: Can Guo <quic_cang@quicinc.com>
> > > > > > > > > > > >
> > > > > > > > > > > > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > > > > > > > > > > > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > > > > > > > > > > > settings are programming different values to different registers, mixing
> > > > > > > > > > > > the two sets and/or overwriting one set with another set is definitely not
> > > > > > > > > > > > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > > > > > > > > > > > need to split the two sets into their dedicated tables, and leave only the
> > > > > > > > > > > > common settings in the .tlbs. To have the PHY programmed with the correct
> > > > > > > > > > > > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > > > > > > > > > > > or HS-G5.
> > > > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > You should also mention that this issue is also present in G4 supported targets.
> > > > > > > > > > And a note that it will get fixed later.
> > > > > > > > > >
> > > > > > > > > > > > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > > > > > > > > > > > ---
> > > > > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > > > > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > > > > > > > > > > > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > > > > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > > > > > > > > > > > 4 files changed, 115 insertions(+), 13 deletions(-)
> > > > > > > > > > > >
> > > > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > > > > index c23d5e4..e563af5 100644
> > > > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > > > > @@ -18,6 +18,7 @@
> > > > > > > > > > > > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > > > > > > > > > > > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > > > > > > > > > > > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > > > > > > > > > > > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > > > > > > > > > > > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > > > > > > > > > > > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > > > > > > > > > > > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > > > > > > > > > > > @@ -27,5 +28,6 @@
> > > > > > > > > > > > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > > > > > > > > > > > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > > > > > > > > > > > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > > > > > > > > > > > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> > > > > > > > > > > >
> > > > > > > > > > > > #endif
> > > > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > > > > index f420f8f..ef392ce 100644
> > > > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > > > > @@ -56,6 +56,8 @@
> > > > > > > > > > > > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > > > > > > > > > > > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > > > > > > > > > > > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > > > > > > > > > > > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > > > > > > > > > > > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > > > > > > > > > > > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > > > > > > > > > > > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > > > > > > > > > > > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > > > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > > > > index 15bcb4b..48f31c8 100644
> > > > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > > > > @@ -10,10 +10,20 @@
> > > > > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > > > > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > > > > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > > > > > > > > > > > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > > > > > > > > > > > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> > > > > > > > > > > >
> > > > > > > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > > > > > > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > > > > > > > > > > > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > > > > > > > > > > > @@ -25,6 +35,8 @@
> > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> > > > > > > > > > > >
> > > > > > > > > > > > #endif
> > > > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > > > > index 3927eba..e0a01497 100644
> > > > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > > > > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > > > > > > +
> > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > > > > > > > > > > > +};
> > > > > > > > > > > > +
> > > > > > > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > > > > > > > > > > > +};
> > > > > > > > > > > > +
> > > > > > > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> > > > > > > > > > >
> > > > > > > > > > > Aside from moving these registers to the HS_G4 table, you are also
> > > > > > > > > > > changing these registers. It makes me think that there was an error in
> > > > > > > > > > > the original programming sequence.
> > > > > > > > > > > If that is correct, could you please split the patch into two pieces:
> > > > > > > > > > > - Fix programming sequence (add proper Fixes tags)
> > > > > > > > > > > - Split G4 and G5 tables.
> > > > > > > > > >
> > > > > > > > > > Ack
> > > > > > > > > >
> > > > > > > > > > >
> > > > > > > > > > > > +
> > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> > > > > > > > > > >
> > > > > > > > > > > I see all the MODE1 registers being only present in G4 and G5 tables.
> > > > > > > > > > > Should they be programmed for the modes lower than G4?
> > > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > We use G4 table for all the modes <= G4.
> > > > > > > > >
> > > > > > > > > Could you please point me how it's handled?
> > > > > > > > > In the patch I see just:
> > > > > > > > >
> > > > > > > > > if (qmp->submode == UFS_HS_G4)
> > > > > > > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > > > > > > > > else if (qmp->submode == UFS_HS_G5)
> > > > > > > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> > > > > > > > >
> > > > > > > > > Which looks like two special cases (HS_G4 and HS_G5) and nothing for
> > > > > > > > > anything else.
> > > > > > > > >
> > > > > > > >
> > > > > > > > Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
> > > > > > > > sequence will be used and for G5, G5 sequence will be used.
> > > > > > > >
> > > > > > >
> > > > > > > That's what I could not find in the UFS driver. I see a call to
> > > > > > > `phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
> > > > > > > host->phy_gear is initialised to UFS_HS_G2.
> > > > > > >
> > > > > >
> > > > > > You need to check the UFS driver changes in this series to get the complete
> > > > > > picture as the logic is getting changed.
> > > > > >
> > > > > > It is common to get confused because of the way the UFS driver (qcom mostly)
> > > > > > handles the PHY init sequence programming. We used to have only one init
> > > > > > sequence for older targets and life was easy. But when I wanted to add G4
> > > > > > support for SM8250, I learned that there are 2 separate init sequences. One for
> > > > > > non-G4 and other for G4. So I used the phy_sub_mode property to pass the
> > > > > > relevant mode from the UFS driver to the PHY driver and programmed the sequence
> > > > > > accordingly. This got extended to non-G5 and G5 now.
> > > > > >
> > > > > > Now, the UFS driver will start probing from a low gear for older targets (G2)
> > > > > > and G4/G5 for newer ones then scale up based on the device and host capability.
> > > > > > For older targets, the common table (tbls) will be used if the submode doesn't
> > > > > > match G4/G5. But for newer targets, the UFS driver will _only_ pass G4 or G5 as
> > > > > > the phy_gear, so those specific sequence will only be used.
> > > > > >
> > > > > > Hope I'm clear.
> > > > >
> > > > > Yes, it is now clear, thank you!
> > > > >
> > > > > Would it be possible / feasible / logical to maintain this idea even
> > > > > for newer platforms (leaving the HS_A / HS_B aside)?
> > > > >
> > > > > tbls - works for HS_G2
> > > > > tbls + tbls_g4 - works for HS_G4
> > > > > tbls + tbls_g5 - works for HS_G5
> > > > >
> > > >
> > > > No. The PHY team only gives 2 init sequences for any SoC now.
> > >
> > > Ack. Then the code should become
> > > if (HS_G5)
> > > program(tbls_hs_g5)
> > > else
> > > program(tbls_hs_g4);
> > >
> >
> > This should work. Even if we have to accomodate G6 in the future, we can use
> > "else if" for that and keep G4 as the "else" condition. This logic can also be
> > optimized in the future.
>
> That would make dual init meaningless for old targets. Say on SM8450, the
> initial PHY gear is G2, with the "else" condition, during the first init, G4
> table would be programmed, then gear negotiation happens btw host and device
> and the negotiated gear is G3 (assume a UFS2.x is connected). During the 2nd
> init, the "else" condition would __again__ program the G4 table - it is not
> programming the non-G4 table for power saving. The dual init is supposed to
> find the optimal PHY settings, but the "else" condition is programming G4
> table unconditinally.
>
> With the original code change in this patch, the dual init works as it is
> for old targets. say SM8450, the initial PHY gear is G2, during the 2nd
> init, it is programming the non-G4 table (assume a UFS2.x is connected), but
> not the G4 table.
>
You are right. I completely overlooked the compatibility for old targets. But
still we can move the common table to the "else" condition. This makes it clear
that one of the 3 will be programmed at a time. But with the current logic, I
get the impression that common table is overridden by G4/G5 tables.
So this is what I'm suggesting:
if (HS_G5)
program(tbls_hs_g5)
else if (HS_G4)
program(tbls_hs_g4);
else
program(tbls_hs_common);
- Mani
> Thanks,
> Can Guo.
> >
> > - Mani
> >
> > > >
> > > > - Mani
> > > >
> > > > > I mean here that the PHY driver should not depend on the knowledge
> > > > > that the UFS driver will not be setting HS_G2 for some particular
> > > > > platform and ideally it should continue working if at some point we
> > > > > change the UFS driver to set HS_G2.
> > > > >
> > > > >
> > > > > >
> > > > > > - Mani
> > > > > >
> > > > > > > Maybe we should change the condition here (in the PHY driver) to:
> > > > > > >
> > > > > > > if (qmp->submode <= UFS_HS_G4)
> > > > > > >
> > > > > > > ?
> > > > > > > --
> > > > > > > With best wishes
> > > > > > > Dmitry
> > > > > >
> > > > > > --
> > > > > > மணிவண்ணன் சதாசிவம்
> > > > >
> > > > >
> > > > >
> > > > > --
> > > > > With best wishes
> > > > > Dmitry
> > > >
> > > > --
> > > > மணிவண்ணன் சதாசிவம்
> > >
> > >
> > >
> > > --
> > > With best wishes
> > > Dmitry
> >
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-11 4:12 ` Manivannan Sadhasivam
0 siblings, 0 replies; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-11 4:12 UTC (permalink / raw)
To: Can Guo
Cc: Manivannan Sadhasivam, Dmitry Baryshkov, Can Guo, bvanassche,
stanley.chu, adrian.hunter, beanhuo, avri.altman, junwoo80.lee,
martin.petersen, linux-scsi, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
On Fri, Nov 10, 2023 at 10:40:53PM +0800, Can Guo wrote:
>
>
> On 11/10/2023 9:18 PM, Manivannan Sadhasivam wrote:
> > On Fri, Nov 10, 2023 at 12:11:46AM +0200, Dmitry Baryshkov wrote:
> > > On Thu, 9 Nov 2023 at 18:04, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > >
> > > > On Thu, Nov 09, 2023 at 01:00:51PM +0200, Dmitry Baryshkov wrote:
> > > > > On Thu, 9 Nov 2023 at 12:43, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > >
> > > > > > On Thu, Nov 09, 2023 at 11:40:51AM +0200, Dmitry Baryshkov wrote:
> > > > > > > On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > > > >
> > > > > > > > On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
> > > > > > > > > On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > > > > > >
> > > > > > > > > > On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> > > > > > > > > > > On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> > > > > > > > > > > >
> > > > > > > > > > > > From: Can Guo <quic_cang@quicinc.com>
> > > > > > > > > > > >
> > > > > > > > > > > > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > > > > > > > > > > > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > > > > > > > > > > > settings are programming different values to different registers, mixing
> > > > > > > > > > > > the two sets and/or overwriting one set with another set is definitely not
> > > > > > > > > > > > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > > > > > > > > > > > need to split the two sets into their dedicated tables, and leave only the
> > > > > > > > > > > > common settings in the .tlbs. To have the PHY programmed with the correct
> > > > > > > > > > > > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > > > > > > > > > > > or HS-G5.
> > > > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > You should also mention that this issue is also present in G4 supported targets.
> > > > > > > > > > And a note that it will get fixed later.
> > > > > > > > > >
> > > > > > > > > > > > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > > > > > > > > > > > ---
> > > > > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > > > > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > > > > > > > > > > > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > > > > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > > > > > > > > > > > 4 files changed, 115 insertions(+), 13 deletions(-)
> > > > > > > > > > > >
> > > > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > > > > index c23d5e4..e563af5 100644
> > > > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > > > > @@ -18,6 +18,7 @@
> > > > > > > > > > > > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > > > > > > > > > > > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > > > > > > > > > > > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > > > > > > > > > > > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > > > > > > > > > > > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > > > > > > > > > > > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > > > > > > > > > > > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > > > > > > > > > > > @@ -27,5 +28,6 @@
> > > > > > > > > > > > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > > > > > > > > > > > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > > > > > > > > > > > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > > > > > > > > > > > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> > > > > > > > > > > >
> > > > > > > > > > > > #endif
> > > > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > > > > index f420f8f..ef392ce 100644
> > > > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > > > > @@ -56,6 +56,8 @@
> > > > > > > > > > > > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > > > > > > > > > > > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > > > > > > > > > > > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > > > > > > > > > > > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > > > > > > > > > > > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > > > > > > > > > > > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > > > > > > > > > > > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > > > > > > > > > > > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > > > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > > > > index 15bcb4b..48f31c8 100644
> > > > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > > > > @@ -10,10 +10,20 @@
> > > > > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > > > > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > > > > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > > > > > > > > > > > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > > > > > > > > > > > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> > > > > > > > > > > >
> > > > > > > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > > > > > > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > > > > > > > > > > > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > > > > > > > > > > > @@ -25,6 +35,8 @@
> > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> > > > > > > > > > > >
> > > > > > > > > > > > #endif
> > > > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > > > > index 3927eba..e0a01497 100644
> > > > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > > > > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > > > > > > +
> > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > > > > > > > > > > > +};
> > > > > > > > > > > > +
> > > > > > > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > > > > > > > > > > > +};
> > > > > > > > > > > > +
> > > > > > > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> > > > > > > > > > >
> > > > > > > > > > > Aside from moving these registers to the HS_G4 table, you are also
> > > > > > > > > > > changing these registers. It makes me think that there was an error in
> > > > > > > > > > > the original programming sequence.
> > > > > > > > > > > If that is correct, could you please split the patch into two pieces:
> > > > > > > > > > > - Fix programming sequence (add proper Fixes tags)
> > > > > > > > > > > - Split G4 and G5 tables.
> > > > > > > > > >
> > > > > > > > > > Ack
> > > > > > > > > >
> > > > > > > > > > >
> > > > > > > > > > > > +
> > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> > > > > > > > > > >
> > > > > > > > > > > I see all the MODE1 registers being only present in G4 and G5 tables.
> > > > > > > > > > > Should they be programmed for the modes lower than G4?
> > > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > We use G4 table for all the modes <= G4.
> > > > > > > > >
> > > > > > > > > Could you please point me how it's handled?
> > > > > > > > > In the patch I see just:
> > > > > > > > >
> > > > > > > > > if (qmp->submode == UFS_HS_G4)
> > > > > > > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > > > > > > > > else if (qmp->submode == UFS_HS_G5)
> > > > > > > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> > > > > > > > >
> > > > > > > > > Which looks like two special cases (HS_G4 and HS_G5) and nothing for
> > > > > > > > > anything else.
> > > > > > > > >
> > > > > > > >
> > > > > > > > Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
> > > > > > > > sequence will be used and for G5, G5 sequence will be used.
> > > > > > > >
> > > > > > >
> > > > > > > That's what I could not find in the UFS driver. I see a call to
> > > > > > > `phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
> > > > > > > host->phy_gear is initialised to UFS_HS_G2.
> > > > > > >
> > > > > >
> > > > > > You need to check the UFS driver changes in this series to get the complete
> > > > > > picture as the logic is getting changed.
> > > > > >
> > > > > > It is common to get confused because of the way the UFS driver (qcom mostly)
> > > > > > handles the PHY init sequence programming. We used to have only one init
> > > > > > sequence for older targets and life was easy. But when I wanted to add G4
> > > > > > support for SM8250, I learned that there are 2 separate init sequences. One for
> > > > > > non-G4 and other for G4. So I used the phy_sub_mode property to pass the
> > > > > > relevant mode from the UFS driver to the PHY driver and programmed the sequence
> > > > > > accordingly. This got extended to non-G5 and G5 now.
> > > > > >
> > > > > > Now, the UFS driver will start probing from a low gear for older targets (G2)
> > > > > > and G4/G5 for newer ones then scale up based on the device and host capability.
> > > > > > For older targets, the common table (tbls) will be used if the submode doesn't
> > > > > > match G4/G5. But for newer targets, the UFS driver will _only_ pass G4 or G5 as
> > > > > > the phy_gear, so those specific sequence will only be used.
> > > > > >
> > > > > > Hope I'm clear.
> > > > >
> > > > > Yes, it is now clear, thank you!
> > > > >
> > > > > Would it be possible / feasible / logical to maintain this idea even
> > > > > for newer platforms (leaving the HS_A / HS_B aside)?
> > > > >
> > > > > tbls - works for HS_G2
> > > > > tbls + tbls_g4 - works for HS_G4
> > > > > tbls + tbls_g5 - works for HS_G5
> > > > >
> > > >
> > > > No. The PHY team only gives 2 init sequences for any SoC now.
> > >
> > > Ack. Then the code should become
> > > if (HS_G5)
> > > program(tbls_hs_g5)
> > > else
> > > program(tbls_hs_g4);
> > >
> >
> > This should work. Even if we have to accomodate G6 in the future, we can use
> > "else if" for that and keep G4 as the "else" condition. This logic can also be
> > optimized in the future.
>
> That would make dual init meaningless for old targets. Say on SM8450, the
> initial PHY gear is G2, with the "else" condition, during the first init, G4
> table would be programmed, then gear negotiation happens btw host and device
> and the negotiated gear is G3 (assume a UFS2.x is connected). During the 2nd
> init, the "else" condition would __again__ program the G4 table - it is not
> programming the non-G4 table for power saving. The dual init is supposed to
> find the optimal PHY settings, but the "else" condition is programming G4
> table unconditinally.
>
> With the original code change in this patch, the dual init works as it is
> for old targets. say SM8450, the initial PHY gear is G2, during the 2nd
> init, it is programming the non-G4 table (assume a UFS2.x is connected), but
> not the G4 table.
>
You are right. I completely overlooked the compatibility for old targets. But
still we can move the common table to the "else" condition. This makes it clear
that one of the 3 will be programmed at a time. But with the current logic, I
get the impression that common table is overridden by G4/G5 tables.
So this is what I'm suggesting:
if (HS_G5)
program(tbls_hs_g5)
else if (HS_G4)
program(tbls_hs_g4);
else
program(tbls_hs_common);
- Mani
> Thanks,
> Can Guo.
> >
> > - Mani
> >
> > > >
> > > > - Mani
> > > >
> > > > > I mean here that the PHY driver should not depend on the knowledge
> > > > > that the UFS driver will not be setting HS_G2 for some particular
> > > > > platform and ideally it should continue working if at some point we
> > > > > change the UFS driver to set HS_G2.
> > > > >
> > > > >
> > > > > >
> > > > > > - Mani
> > > > > >
> > > > > > > Maybe we should change the condition here (in the PHY driver) to:
> > > > > > >
> > > > > > > if (qmp->submode <= UFS_HS_G4)
> > > > > > >
> > > > > > > ?
> > > > > > > --
> > > > > > > With best wishes
> > > > > > > Dmitry
> > > > > >
> > > > > > --
> > > > > > மணிவண்ணன் சதாசிவம்
> > > > >
> > > > >
> > > > >
> > > > > --
> > > > > With best wishes
> > > > > Dmitry
> > > >
> > > > --
> > > > மணிவண்ணன் சதாசிவம்
> > >
> > >
> > >
> > > --
> > > With best wishes
> > > Dmitry
> >
--
மணிவண்ணன் சதாசிவம்
--
linux-phy mailing list
linux-phy@lists.infradead.org
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^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-11 4:12 ` Manivannan Sadhasivam
@ 2023-11-12 5:13 ` Can Guo
-1 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-12 5:13 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Dmitry Baryshkov, Can Guo, bvanassche, stanley.chu,
adrian.hunter, beanhuo, avri.altman, junwoo80.lee,
martin.petersen, linux-scsi, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
Hi Mani,
On 11/11/2023 12:12 PM, Manivannan Sadhasivam wrote:
> On Fri, Nov 10, 2023 at 10:40:53PM +0800, Can Guo wrote:
>>
>>
>> On 11/10/2023 9:18 PM, Manivannan Sadhasivam wrote:
>>> On Fri, Nov 10, 2023 at 12:11:46AM +0200, Dmitry Baryshkov wrote:
>>>> On Thu, 9 Nov 2023 at 18:04, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>>>
>>>>> On Thu, Nov 09, 2023 at 01:00:51PM +0200, Dmitry Baryshkov wrote:
>>>>>> On Thu, 9 Nov 2023 at 12:43, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>>>>>
>>>>>>> On Thu, Nov 09, 2023 at 11:40:51AM +0200, Dmitry Baryshkov wrote:
>>>>>>>> On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>>>>>>>
>>>>>>>>> On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
>>>>>>>>>> On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>>>>>>>>>
>>>>>>>>>>> On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
>>>>>>>>>>>> On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
>>>>>>>>>>>>>
>>>>>>>>>>>>> From: Can Guo <quic_cang@quicinc.com>
>>>>>>>>>>>>>
>>>>>>>>>>>>> On SM8550, two sets of UFS PHY settings are provided, one set is to support
>>>>>>>>>>>>> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
>>>>>>>>>>>>> settings are programming different values to different registers, mixing
>>>>>>>>>>>>> the two sets and/or overwriting one set with another set is definitely not
>>>>>>>>>>>>> blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
>>>>>>>>>>>>> need to split the two sets into their dedicated tables, and leave only the
>>>>>>>>>>>>> common settings in the .tlbs. To have the PHY programmed with the correct
>>>>>>>>>>>>> set of PHY settings, the submode passed to PHY driver must be either HS-G4
>>>>>>>>>>>>> or HS-G5.
>>>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> You should also mention that this issue is also present in G4 supported targets.
>>>>>>>>>>> And a note that it will get fixed later.
>>>>>>>>>>>
>>>>>>>>>>>>> Signed-off-by: Can Guo <quic_cang@quicinc.com>
>>>>>>>>>>>>> ---
>>>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
>>>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
>>>>>>>>>>>>> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
>>>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
>>>>>>>>>>>>> 4 files changed, 115 insertions(+), 13 deletions(-)
>>>>>>>>>>>>>
>>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>>>>>>>>>>>> index c23d5e4..e563af5 100644
>>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>>>>>>>>>>>> @@ -18,6 +18,7 @@
>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
>>>>>>>>>>>>> +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
>>>>>>>>>>>>> @@ -27,5 +28,6 @@
>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
>>>>>>>>>>>>> +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
>>>>>>>>>>>>>
>>>>>>>>>>>>> #endif
>>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>>>>>>>>>>> index f420f8f..ef392ce 100644
>>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>>>>>>>>>>> @@ -56,6 +56,8 @@
>>>>>>>>>>>>> #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
>>>>>>>>>>>>> #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
>>>>>>>>>>>>> #define QSERDES_V6_COM_PLL_IVCO 0xf4
>>>>>>>>>>>>> +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
>>>>>>>>>>>>> +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
>>>>>>>>>>>>> #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
>>>>>>>>>>>>> #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
>>>>>>>>>>>>> #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
>>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>>>>>>>>>>>> index 15bcb4b..48f31c8 100644
>>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>>>>>>>>>>>> @@ -10,10 +10,20 @@
>>>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
>>>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
>>>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
>>>>>>>>>>>>>
>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
>>>>>>>>>>>>> @@ -25,6 +35,8 @@
>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
>>>>>>>>>>>>>
>>>>>>>>>>>>> #endif
>>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>>>>>>>>>> index 3927eba..e0a01497 100644
>>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>>>>>>>>>> @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
>>>>>>>>>>>>> +
>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
>>>>>>>>>>>>> +};
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
>>>>>>>>>>>>> +};
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
>>>>>>>>>>>>
>>>>>>>>>>>> Aside from moving these registers to the HS_G4 table, you are also
>>>>>>>>>>>> changing these registers. It makes me think that there was an error in
>>>>>>>>>>>> the original programming sequence.
>>>>>>>>>>>> If that is correct, could you please split the patch into two pieces:
>>>>>>>>>>>> - Fix programming sequence (add proper Fixes tags)
>>>>>>>>>>>> - Split G4 and G5 tables.
>>>>>>>>>>>
>>>>>>>>>>> Ack
>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>>> +
>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
>>>>>>>>>>>>
>>>>>>>>>>>> I see all the MODE1 registers being only present in G4 and G5 tables.
>>>>>>>>>>>> Should they be programmed for the modes lower than G4?
>>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> We use G4 table for all the modes <= G4.
>>>>>>>>>>
>>>>>>>>>> Could you please point me how it's handled?
>>>>>>>>>> In the patch I see just:
>>>>>>>>>>
>>>>>>>>>> if (qmp->submode == UFS_HS_G4)
>>>>>>>>>> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
>>>>>>>>>> else if (qmp->submode == UFS_HS_G5)
>>>>>>>>>> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
>>>>>>>>>>
>>>>>>>>>> Which looks like two special cases (HS_G4 and HS_G5) and nothing for
>>>>>>>>>> anything else.
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
>>>>>>>>> sequence will be used and for G5, G5 sequence will be used.
>>>>>>>>>
>>>>>>>>
>>>>>>>> That's what I could not find in the UFS driver. I see a call to
>>>>>>>> `phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
>>>>>>>> host->phy_gear is initialised to UFS_HS_G2.
>>>>>>>>
>>>>>>>
>>>>>>> You need to check the UFS driver changes in this series to get the complete
>>>>>>> picture as the logic is getting changed.
>>>>>>>
>>>>>>> It is common to get confused because of the way the UFS driver (qcom mostly)
>>>>>>> handles the PHY init sequence programming. We used to have only one init
>>>>>>> sequence for older targets and life was easy. But when I wanted to add G4
>>>>>>> support for SM8250, I learned that there are 2 separate init sequences. One for
>>>>>>> non-G4 and other for G4. So I used the phy_sub_mode property to pass the
>>>>>>> relevant mode from the UFS driver to the PHY driver and programmed the sequence
>>>>>>> accordingly. This got extended to non-G5 and G5 now.
>>>>>>>
>>>>>>> Now, the UFS driver will start probing from a low gear for older targets (G2)
>>>>>>> and G4/G5 for newer ones then scale up based on the device and host capability.
>>>>>>> For older targets, the common table (tbls) will be used if the submode doesn't
>>>>>>> match G4/G5. But for newer targets, the UFS driver will _only_ pass G4 or G5 as
>>>>>>> the phy_gear, so those specific sequence will only be used.
>>>>>>>
>>>>>>> Hope I'm clear.
>>>>>>
>>>>>> Yes, it is now clear, thank you!
>>>>>>
>>>>>> Would it be possible / feasible / logical to maintain this idea even
>>>>>> for newer platforms (leaving the HS_A / HS_B aside)?
>>>>>>
>>>>>> tbls - works for HS_G2
>>>>>> tbls + tbls_g4 - works for HS_G4
>>>>>> tbls + tbls_g5 - works for HS_G5
>>>>>>
>>>>>
>>>>> No. The PHY team only gives 2 init sequences for any SoC now.
>>>>
>>>> Ack. Then the code should become
>>>> if (HS_G5)
>>>> program(tbls_hs_g5)
>>>> else
>>>> program(tbls_hs_g4);
>>>>
>>>
>>> This should work. Even if we have to accomodate G6 in the future, we can use
>>> "else if" for that and keep G4 as the "else" condition. This logic can also be
>>> optimized in the future.
>>
>> That would make dual init meaningless for old targets. Say on SM8450, the
>> initial PHY gear is G2, with the "else" condition, during the first init, G4
>> table would be programmed, then gear negotiation happens btw host and device
>> and the negotiated gear is G3 (assume a UFS2.x is connected). During the 2nd
>> init, the "else" condition would __again__ program the G4 table - it is not
>> programming the non-G4 table for power saving. The dual init is supposed to
>> find the optimal PHY settings, but the "else" condition is programming G4
>> table unconditinally.
>>
>> With the original code change in this patch, the dual init works as it is
>> for old targets. say SM8450, the initial PHY gear is G2, during the 2nd
>> init, it is programming the non-G4 table (assume a UFS2.x is connected), but
>> not the G4 table.
>>
>
> You are right. I completely overlooked the compatibility for old targets. But
> still we can move the common table to the "else" condition. This makes it clear
> that one of the 3 will be programmed at a time. But with the current logic, I
> get the impression that common table is overridden by G4/G5 tables.
>
> So this is what I'm suggesting:
>
> if (HS_G5)
> program(tbls_hs_g5)
> else if (HS_G4)
> program(tbls_hs_g4);
> else
> program(tbls_hs_common);
>
Common table is needed regardlessly, we cannot put it in "else",
otherwise it would break all targets -
On old targets (no G5 supported):
Common table - supports non-G4 (G3 and lower)
Common table + G4 table - supports G4
On new targets (G5 supported):
Common table - supports nothing, as it is just common parts of G4
table and G5 table.
Common table + G4 table - support non-G5 (G4 and lower)
Common table + G5 table - support G5
Thanks,
Can Guo.
> - Mani
>
>> Thanks,
>> Can Guo.
>>>
>>> - Mani
>>>
>>>>>
>>>>> - Mani
>>>>>
>>>>>> I mean here that the PHY driver should not depend on the knowledge
>>>>>> that the UFS driver will not be setting HS_G2 for some particular
>>>>>> platform and ideally it should continue working if at some point we
>>>>>> change the UFS driver to set HS_G2.
>>>>>>
>>>>>>
>>>>>>>
>>>>>>> - Mani
>>>>>>>
>>>>>>>> Maybe we should change the condition here (in the PHY driver) to:
>>>>>>>>
>>>>>>>> if (qmp->submode <= UFS_HS_G4)
>>>>>>>>
>>>>>>>> ?
>>>>>>>> --
>>>>>>>> With best wishes
>>>>>>>> Dmitry
>>>>>>>
>>>>>>> --
>>>>>>> மணிவண்ணன் சதாசிவம்
>>>>>>
>>>>>>
>>>>>>
>>>>>> --
>>>>>> With best wishes
>>>>>> Dmitry
>>>>>
>>>>> --
>>>>> மணிவண்ணன் சதாசிவம்
>>>>
>>>>
>>>>
>>>> --
>>>> With best wishes
>>>> Dmitry
>>>
>
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-12 5:13 ` Can Guo
0 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-12 5:13 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Dmitry Baryshkov, Can Guo, bvanassche, stanley.chu,
adrian.hunter, beanhuo, avri.altman, junwoo80.lee,
martin.petersen, linux-scsi, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
Hi Mani,
On 11/11/2023 12:12 PM, Manivannan Sadhasivam wrote:
> On Fri, Nov 10, 2023 at 10:40:53PM +0800, Can Guo wrote:
>>
>>
>> On 11/10/2023 9:18 PM, Manivannan Sadhasivam wrote:
>>> On Fri, Nov 10, 2023 at 12:11:46AM +0200, Dmitry Baryshkov wrote:
>>>> On Thu, 9 Nov 2023 at 18:04, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>>>
>>>>> On Thu, Nov 09, 2023 at 01:00:51PM +0200, Dmitry Baryshkov wrote:
>>>>>> On Thu, 9 Nov 2023 at 12:43, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>>>>>
>>>>>>> On Thu, Nov 09, 2023 at 11:40:51AM +0200, Dmitry Baryshkov wrote:
>>>>>>>> On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>>>>>>>
>>>>>>>>> On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
>>>>>>>>>> On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>>>>>>>>>
>>>>>>>>>>> On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
>>>>>>>>>>>> On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
>>>>>>>>>>>>>
>>>>>>>>>>>>> From: Can Guo <quic_cang@quicinc.com>
>>>>>>>>>>>>>
>>>>>>>>>>>>> On SM8550, two sets of UFS PHY settings are provided, one set is to support
>>>>>>>>>>>>> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
>>>>>>>>>>>>> settings are programming different values to different registers, mixing
>>>>>>>>>>>>> the two sets and/or overwriting one set with another set is definitely not
>>>>>>>>>>>>> blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
>>>>>>>>>>>>> need to split the two sets into their dedicated tables, and leave only the
>>>>>>>>>>>>> common settings in the .tlbs. To have the PHY programmed with the correct
>>>>>>>>>>>>> set of PHY settings, the submode passed to PHY driver must be either HS-G4
>>>>>>>>>>>>> or HS-G5.
>>>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> You should also mention that this issue is also present in G4 supported targets.
>>>>>>>>>>> And a note that it will get fixed later.
>>>>>>>>>>>
>>>>>>>>>>>>> Signed-off-by: Can Guo <quic_cang@quicinc.com>
>>>>>>>>>>>>> ---
>>>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
>>>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
>>>>>>>>>>>>> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
>>>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
>>>>>>>>>>>>> 4 files changed, 115 insertions(+), 13 deletions(-)
>>>>>>>>>>>>>
>>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>>>>>>>>>>>> index c23d5e4..e563af5 100644
>>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>>>>>>>>>>>> @@ -18,6 +18,7 @@
>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
>>>>>>>>>>>>> +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
>>>>>>>>>>>>> @@ -27,5 +28,6 @@
>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
>>>>>>>>>>>>> +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
>>>>>>>>>>>>>
>>>>>>>>>>>>> #endif
>>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>>>>>>>>>>> index f420f8f..ef392ce 100644
>>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>>>>>>>>>>> @@ -56,6 +56,8 @@
>>>>>>>>>>>>> #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
>>>>>>>>>>>>> #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
>>>>>>>>>>>>> #define QSERDES_V6_COM_PLL_IVCO 0xf4
>>>>>>>>>>>>> +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
>>>>>>>>>>>>> +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
>>>>>>>>>>>>> #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
>>>>>>>>>>>>> #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
>>>>>>>>>>>>> #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
>>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>>>>>>>>>>>> index 15bcb4b..48f31c8 100644
>>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>>>>>>>>>>>> @@ -10,10 +10,20 @@
>>>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
>>>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
>>>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
>>>>>>>>>>>>>
>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
>>>>>>>>>>>>> @@ -25,6 +35,8 @@
>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
>>>>>>>>>>>>>
>>>>>>>>>>>>> #endif
>>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>>>>>>>>>> index 3927eba..e0a01497 100644
>>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>>>>>>>>>> @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
>>>>>>>>>>>>> +
>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
>>>>>>>>>>>>> +};
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
>>>>>>>>>>>>> +};
>>>>>>>>>>>>> +
>>>>>>>>>>>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
>>>>>>>>>>>>
>>>>>>>>>>>> Aside from moving these registers to the HS_G4 table, you are also
>>>>>>>>>>>> changing these registers. It makes me think that there was an error in
>>>>>>>>>>>> the original programming sequence.
>>>>>>>>>>>> If that is correct, could you please split the patch into two pieces:
>>>>>>>>>>>> - Fix programming sequence (add proper Fixes tags)
>>>>>>>>>>>> - Split G4 and G5 tables.
>>>>>>>>>>>
>>>>>>>>>>> Ack
>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>>> +
>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
>>>>>>>>>>>>
>>>>>>>>>>>> I see all the MODE1 registers being only present in G4 and G5 tables.
>>>>>>>>>>>> Should they be programmed for the modes lower than G4?
>>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> We use G4 table for all the modes <= G4.
>>>>>>>>>>
>>>>>>>>>> Could you please point me how it's handled?
>>>>>>>>>> In the patch I see just:
>>>>>>>>>>
>>>>>>>>>> if (qmp->submode == UFS_HS_G4)
>>>>>>>>>> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
>>>>>>>>>> else if (qmp->submode == UFS_HS_G5)
>>>>>>>>>> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
>>>>>>>>>>
>>>>>>>>>> Which looks like two special cases (HS_G4 and HS_G5) and nothing for
>>>>>>>>>> anything else.
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
>>>>>>>>> sequence will be used and for G5, G5 sequence will be used.
>>>>>>>>>
>>>>>>>>
>>>>>>>> That's what I could not find in the UFS driver. I see a call to
>>>>>>>> `phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
>>>>>>>> host->phy_gear is initialised to UFS_HS_G2.
>>>>>>>>
>>>>>>>
>>>>>>> You need to check the UFS driver changes in this series to get the complete
>>>>>>> picture as the logic is getting changed.
>>>>>>>
>>>>>>> It is common to get confused because of the way the UFS driver (qcom mostly)
>>>>>>> handles the PHY init sequence programming. We used to have only one init
>>>>>>> sequence for older targets and life was easy. But when I wanted to add G4
>>>>>>> support for SM8250, I learned that there are 2 separate init sequences. One for
>>>>>>> non-G4 and other for G4. So I used the phy_sub_mode property to pass the
>>>>>>> relevant mode from the UFS driver to the PHY driver and programmed the sequence
>>>>>>> accordingly. This got extended to non-G5 and G5 now.
>>>>>>>
>>>>>>> Now, the UFS driver will start probing from a low gear for older targets (G2)
>>>>>>> and G4/G5 for newer ones then scale up based on the device and host capability.
>>>>>>> For older targets, the common table (tbls) will be used if the submode doesn't
>>>>>>> match G4/G5. But for newer targets, the UFS driver will _only_ pass G4 or G5 as
>>>>>>> the phy_gear, so those specific sequence will only be used.
>>>>>>>
>>>>>>> Hope I'm clear.
>>>>>>
>>>>>> Yes, it is now clear, thank you!
>>>>>>
>>>>>> Would it be possible / feasible / logical to maintain this idea even
>>>>>> for newer platforms (leaving the HS_A / HS_B aside)?
>>>>>>
>>>>>> tbls - works for HS_G2
>>>>>> tbls + tbls_g4 - works for HS_G4
>>>>>> tbls + tbls_g5 - works for HS_G5
>>>>>>
>>>>>
>>>>> No. The PHY team only gives 2 init sequences for any SoC now.
>>>>
>>>> Ack. Then the code should become
>>>> if (HS_G5)
>>>> program(tbls_hs_g5)
>>>> else
>>>> program(tbls_hs_g4);
>>>>
>>>
>>> This should work. Even if we have to accomodate G6 in the future, we can use
>>> "else if" for that and keep G4 as the "else" condition. This logic can also be
>>> optimized in the future.
>>
>> That would make dual init meaningless for old targets. Say on SM8450, the
>> initial PHY gear is G2, with the "else" condition, during the first init, G4
>> table would be programmed, then gear negotiation happens btw host and device
>> and the negotiated gear is G3 (assume a UFS2.x is connected). During the 2nd
>> init, the "else" condition would __again__ program the G4 table - it is not
>> programming the non-G4 table for power saving. The dual init is supposed to
>> find the optimal PHY settings, but the "else" condition is programming G4
>> table unconditinally.
>>
>> With the original code change in this patch, the dual init works as it is
>> for old targets. say SM8450, the initial PHY gear is G2, during the 2nd
>> init, it is programming the non-G4 table (assume a UFS2.x is connected), but
>> not the G4 table.
>>
>
> You are right. I completely overlooked the compatibility for old targets. But
> still we can move the common table to the "else" condition. This makes it clear
> that one of the 3 will be programmed at a time. But with the current logic, I
> get the impression that common table is overridden by G4/G5 tables.
>
> So this is what I'm suggesting:
>
> if (HS_G5)
> program(tbls_hs_g5)
> else if (HS_G4)
> program(tbls_hs_g4);
> else
> program(tbls_hs_common);
>
Common table is needed regardlessly, we cannot put it in "else",
otherwise it would break all targets -
On old targets (no G5 supported):
Common table - supports non-G4 (G3 and lower)
Common table + G4 table - supports G4
On new targets (G5 supported):
Common table - supports nothing, as it is just common parts of G4
table and G5 table.
Common table + G4 table - support non-G5 (G4 and lower)
Common table + G5 table - support G5
Thanks,
Can Guo.
> - Mani
>
>> Thanks,
>> Can Guo.
>>>
>>> - Mani
>>>
>>>>>
>>>>> - Mani
>>>>>
>>>>>> I mean here that the PHY driver should not depend on the knowledge
>>>>>> that the UFS driver will not be setting HS_G2 for some particular
>>>>>> platform and ideally it should continue working if at some point we
>>>>>> change the UFS driver to set HS_G2.
>>>>>>
>>>>>>
>>>>>>>
>>>>>>> - Mani
>>>>>>>
>>>>>>>> Maybe we should change the condition here (in the PHY driver) to:
>>>>>>>>
>>>>>>>> if (qmp->submode <= UFS_HS_G4)
>>>>>>>>
>>>>>>>> ?
>>>>>>>> --
>>>>>>>> With best wishes
>>>>>>>> Dmitry
>>>>>>>
>>>>>>> --
>>>>>>> மணிவண்ணன் சதாசிவம்
>>>>>>
>>>>>>
>>>>>>
>>>>>> --
>>>>>> With best wishes
>>>>>> Dmitry
>>>>>
>>>>> --
>>>>> மணிவண்ணன் சதாசிவம்
>>>>
>>>>
>>>>
>>>> --
>>>> With best wishes
>>>> Dmitry
>>>
>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-12 5:13 ` Can Guo
@ 2023-11-14 6:12 ` Manivannan Sadhasivam
-1 siblings, 0 replies; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-14 6:12 UTC (permalink / raw)
To: Can Guo
Cc: Manivannan Sadhasivam, Dmitry Baryshkov, Can Guo, bvanassche,
stanley.chu, adrian.hunter, beanhuo, avri.altman, junwoo80.lee,
martin.petersen, linux-scsi, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
On Sun, Nov 12, 2023 at 01:13:30PM +0800, Can Guo wrote:
> Hi Mani,
>
> On 11/11/2023 12:12 PM, Manivannan Sadhasivam wrote:
> > On Fri, Nov 10, 2023 at 10:40:53PM +0800, Can Guo wrote:
> > >
> > >
> > > On 11/10/2023 9:18 PM, Manivannan Sadhasivam wrote:
> > > > On Fri, Nov 10, 2023 at 12:11:46AM +0200, Dmitry Baryshkov wrote:
> > > > > On Thu, 9 Nov 2023 at 18:04, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > >
> > > > > > On Thu, Nov 09, 2023 at 01:00:51PM +0200, Dmitry Baryshkov wrote:
> > > > > > > On Thu, 9 Nov 2023 at 12:43, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > > > >
> > > > > > > > On Thu, Nov 09, 2023 at 11:40:51AM +0200, Dmitry Baryshkov wrote:
> > > > > > > > > On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > > > > > >
> > > > > > > > > > On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
> > > > > > > > > > > On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > > > > > > > >
> > > > > > > > > > > > On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> > > > > > > > > > > > > On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > From: Can Guo <quic_cang@quicinc.com>
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > > > > > > > > > > > > > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > > > > > > > > > > > > > settings are programming different values to different registers, mixing
> > > > > > > > > > > > > > the two sets and/or overwriting one set with another set is definitely not
> > > > > > > > > > > > > > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > > > > > > > > > > > > > need to split the two sets into their dedicated tables, and leave only the
> > > > > > > > > > > > > > common settings in the .tlbs. To have the PHY programmed with the correct
> > > > > > > > > > > > > > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > > > > > > > > > > > > > or HS-G5.
> > > > > > > > > > > > > >
> > > > > > > > > > > >
> > > > > > > > > > > > You should also mention that this issue is also present in G4 supported targets.
> > > > > > > > > > > > And a note that it will get fixed later.
> > > > > > > > > > > >
> > > > > > > > > > > > > > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > > > > > > > > > > > > > ---
> > > > > > > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > > > > > > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > > > > > > > > > > > > > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > > > > > > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > > > > > > > > > > > > > 4 files changed, 115 insertions(+), 13 deletions(-)
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > > > > > > index c23d5e4..e563af5 100644
> > > > > > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > > > > > > @@ -18,6 +18,7 @@
> > > > > > > > > > > > > > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > > > > > > > > > > > > > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > > > > > > > > > > > > > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > > > > > > > > > > > > > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > > > > > > > > > > > > > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > > > > > > > > > > > > > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > > > > > > > > > > > > > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > > > > > > > > > > > > > @@ -27,5 +28,6 @@
> > > > > > > > > > > > > > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > > > > > > > > > > > > > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > > > > > > > > > > > > > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > > > > > > > > > > > > > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > #endif
> > > > > > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > > > > > > index f420f8f..ef392ce 100644
> > > > > > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > > > > > > @@ -56,6 +56,8 @@
> > > > > > > > > > > > > > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > > > > > > > > > > > > > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > > > > > > > > > > > > > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > > > > > > > > > > > > > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > > > > > > > > > > > > > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > > > > > > > > > > > > > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > > > > > > > > > > > > > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > > > > > > > > > > > > > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > > > > > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > > > > > > index 15bcb4b..48f31c8 100644
> > > > > > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > > > > > > @@ -10,10 +10,20 @@
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > > > > > > > > > > > > > @@ -25,6 +35,8 @@
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > #endif
> > > > > > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > > > > > > index 3927eba..e0a01497 100644
> > > > > > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > > > > > > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > > > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > > > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > > > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > > > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > > > > > > > > +
> > > > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > > > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > > > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > > > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > > > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > > > > > > > > > > > > > +};
> > > > > > > > > > > > > > +
> > > > > > > > > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > > > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > > > > > > > > > > > > > +};
> > > > > > > > > > > > > > +
> > > > > > > > > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > > > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > > > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> > > > > > > > > > > > >
> > > > > > > > > > > > > Aside from moving these registers to the HS_G4 table, you are also
> > > > > > > > > > > > > changing these registers. It makes me think that there was an error in
> > > > > > > > > > > > > the original programming sequence.
> > > > > > > > > > > > > If that is correct, could you please split the patch into two pieces:
> > > > > > > > > > > > > - Fix programming sequence (add proper Fixes tags)
> > > > > > > > > > > > > - Split G4 and G5 tables.
> > > > > > > > > > > >
> > > > > > > > > > > > Ack
> > > > > > > > > > > >
> > > > > > > > > > > > >
> > > > > > > > > > > > > > +
> > > > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > > > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > > > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > > > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > > > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > > > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> > > > > > > > > > > > >
> > > > > > > > > > > > > I see all the MODE1 registers being only present in G4 and G5 tables.
> > > > > > > > > > > > > Should they be programmed for the modes lower than G4?
> > > > > > > > > > > > >
> > > > > > > > > > > >
> > > > > > > > > > > > We use G4 table for all the modes <= G4.
> > > > > > > > > > >
> > > > > > > > > > > Could you please point me how it's handled?
> > > > > > > > > > > In the patch I see just:
> > > > > > > > > > >
> > > > > > > > > > > if (qmp->submode == UFS_HS_G4)
> > > > > > > > > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > > > > > > > > > > else if (qmp->submode == UFS_HS_G5)
> > > > > > > > > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> > > > > > > > > > >
> > > > > > > > > > > Which looks like two special cases (HS_G4 and HS_G5) and nothing for
> > > > > > > > > > > anything else.
> > > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
> > > > > > > > > > sequence will be used and for G5, G5 sequence will be used.
> > > > > > > > > >
> > > > > > > > >
> > > > > > > > > That's what I could not find in the UFS driver. I see a call to
> > > > > > > > > `phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
> > > > > > > > > host->phy_gear is initialised to UFS_HS_G2.
> > > > > > > > >
> > > > > > > >
> > > > > > > > You need to check the UFS driver changes in this series to get the complete
> > > > > > > > picture as the logic is getting changed.
> > > > > > > >
> > > > > > > > It is common to get confused because of the way the UFS driver (qcom mostly)
> > > > > > > > handles the PHY init sequence programming. We used to have only one init
> > > > > > > > sequence for older targets and life was easy. But when I wanted to add G4
> > > > > > > > support for SM8250, I learned that there are 2 separate init sequences. One for
> > > > > > > > non-G4 and other for G4. So I used the phy_sub_mode property to pass the
> > > > > > > > relevant mode from the UFS driver to the PHY driver and programmed the sequence
> > > > > > > > accordingly. This got extended to non-G5 and G5 now.
> > > > > > > >
> > > > > > > > Now, the UFS driver will start probing from a low gear for older targets (G2)
> > > > > > > > and G4/G5 for newer ones then scale up based on the device and host capability.
> > > > > > > > For older targets, the common table (tbls) will be used if the submode doesn't
> > > > > > > > match G4/G5. But for newer targets, the UFS driver will _only_ pass G4 or G5 as
> > > > > > > > the phy_gear, so those specific sequence will only be used.
> > > > > > > >
> > > > > > > > Hope I'm clear.
> > > > > > >
> > > > > > > Yes, it is now clear, thank you!
> > > > > > >
> > > > > > > Would it be possible / feasible / logical to maintain this idea even
> > > > > > > for newer platforms (leaving the HS_A / HS_B aside)?
> > > > > > >
> > > > > > > tbls - works for HS_G2
> > > > > > > tbls + tbls_g4 - works for HS_G4
> > > > > > > tbls + tbls_g5 - works for HS_G5
> > > > > > >
> > > > > >
> > > > > > No. The PHY team only gives 2 init sequences for any SoC now.
> > > > >
> > > > > Ack. Then the code should become
> > > > > if (HS_G5)
> > > > > program(tbls_hs_g5)
> > > > > else
> > > > > program(tbls_hs_g4);
> > > > >
> > > >
> > > > This should work. Even if we have to accomodate G6 in the future, we can use
> > > > "else if" for that and keep G4 as the "else" condition. This logic can also be
> > > > optimized in the future.
> > >
> > > That would make dual init meaningless for old targets. Say on SM8450, the
> > > initial PHY gear is G2, with the "else" condition, during the first init, G4
> > > table would be programmed, then gear negotiation happens btw host and device
> > > and the negotiated gear is G3 (assume a UFS2.x is connected). During the 2nd
> > > init, the "else" condition would __again__ program the G4 table - it is not
> > > programming the non-G4 table for power saving. The dual init is supposed to
> > > find the optimal PHY settings, but the "else" condition is programming G4
> > > table unconditinally.
> > >
> > > With the original code change in this patch, the dual init works as it is
> > > for old targets. say SM8450, the initial PHY gear is G2, during the 2nd
> > > init, it is programming the non-G4 table (assume a UFS2.x is connected), but
> > > not the G4 table.
> > >
> >
> > You are right. I completely overlooked the compatibility for old targets. But
> > still we can move the common table to the "else" condition. This makes it clear
> > that one of the 3 will be programmed at a time. But with the current logic, I
> > get the impression that common table is overridden by G4/G5 tables.
> >
> > So this is what I'm suggesting:
> >
> > if (HS_G5)
> > program(tbls_hs_g5)
> > else if (HS_G4)
> > program(tbls_hs_g4);
> > else
> > program(tbls_hs_common);
> >
>
> Common table is needed regardlessly, we cannot put it in "else", otherwise
> it would break all targets -
>
> On old targets (no G5 supported):
> Common table - supports non-G4 (G3 and lower)
> Common table + G4 table - supports G4
>
> On new targets (G5 supported):
> Common table - supports nothing, as it is just common parts of G4 table
> and G5 table.
> Common table + G4 table - support non-G5 (G4 and lower)
> Common table + G5 table - support G5
>
Doh! I missed the fact that common table is not a standalone table. Sorry for
the confusion. Let's keep it as you proposed for now. I still don't like the if
conditions as it would just keep growing with future gears, but we can get to it
later.
- Mani
> Thanks,
> Can Guo.
>
> > - Mani
> >
> > > Thanks,
> > > Can Guo.
> > > >
> > > > - Mani
> > > >
> > > > > >
> > > > > > - Mani
> > > > > >
> > > > > > > I mean here that the PHY driver should not depend on the knowledge
> > > > > > > that the UFS driver will not be setting HS_G2 for some particular
> > > > > > > platform and ideally it should continue working if at some point we
> > > > > > > change the UFS driver to set HS_G2.
> > > > > > >
> > > > > > >
> > > > > > > >
> > > > > > > > - Mani
> > > > > > > >
> > > > > > > > > Maybe we should change the condition here (in the PHY driver) to:
> > > > > > > > >
> > > > > > > > > if (qmp->submode <= UFS_HS_G4)
> > > > > > > > >
> > > > > > > > > ?
> > > > > > > > > --
> > > > > > > > > With best wishes
> > > > > > > > > Dmitry
> > > > > > > >
> > > > > > > > --
> > > > > > > > மணிவண்ணன் சதாசிவம்
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > > --
> > > > > > > With best wishes
> > > > > > > Dmitry
> > > > > >
> > > > > > --
> > > > > > மணிவண்ணன் சதாசிவம்
> > > > >
> > > > >
> > > > >
> > > > > --
> > > > > With best wishes
> > > > > Dmitry
> > > >
> >
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-14 6:12 ` Manivannan Sadhasivam
0 siblings, 0 replies; 86+ messages in thread
From: Manivannan Sadhasivam @ 2023-11-14 6:12 UTC (permalink / raw)
To: Can Guo
Cc: Manivannan Sadhasivam, Dmitry Baryshkov, Can Guo, bvanassche,
stanley.chu, adrian.hunter, beanhuo, avri.altman, junwoo80.lee,
martin.petersen, linux-scsi, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
On Sun, Nov 12, 2023 at 01:13:30PM +0800, Can Guo wrote:
> Hi Mani,
>
> On 11/11/2023 12:12 PM, Manivannan Sadhasivam wrote:
> > On Fri, Nov 10, 2023 at 10:40:53PM +0800, Can Guo wrote:
> > >
> > >
> > > On 11/10/2023 9:18 PM, Manivannan Sadhasivam wrote:
> > > > On Fri, Nov 10, 2023 at 12:11:46AM +0200, Dmitry Baryshkov wrote:
> > > > > On Thu, 9 Nov 2023 at 18:04, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > >
> > > > > > On Thu, Nov 09, 2023 at 01:00:51PM +0200, Dmitry Baryshkov wrote:
> > > > > > > On Thu, 9 Nov 2023 at 12:43, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > > > >
> > > > > > > > On Thu, Nov 09, 2023 at 11:40:51AM +0200, Dmitry Baryshkov wrote:
> > > > > > > > > On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > > > > > >
> > > > > > > > > > On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
> > > > > > > > > > > On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > > > > > > > >
> > > > > > > > > > > > On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> > > > > > > > > > > > > On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > From: Can Guo <quic_cang@quicinc.com>
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > On SM8550, two sets of UFS PHY settings are provided, one set is to support
> > > > > > > > > > > > > > HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> > > > > > > > > > > > > > settings are programming different values to different registers, mixing
> > > > > > > > > > > > > > the two sets and/or overwriting one set with another set is definitely not
> > > > > > > > > > > > > > blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> > > > > > > > > > > > > > need to split the two sets into their dedicated tables, and leave only the
> > > > > > > > > > > > > > common settings in the .tlbs. To have the PHY programmed with the correct
> > > > > > > > > > > > > > set of PHY settings, the submode passed to PHY driver must be either HS-G4
> > > > > > > > > > > > > > or HS-G5.
> > > > > > > > > > > > > >
> > > > > > > > > > > >
> > > > > > > > > > > > You should also mention that this issue is also present in G4 supported targets.
> > > > > > > > > > > > And a note that it will get fixed later.
> > > > > > > > > > > >
> > > > > > > > > > > > > > Signed-off-by: Can Guo <quic_cang@quicinc.com>
> > > > > > > > > > > > > > ---
> > > > > > > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> > > > > > > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> > > > > > > > > > > > > > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> > > > > > > > > > > > > > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> > > > > > > > > > > > > > 4 files changed, 115 insertions(+), 13 deletions(-)
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > > > > > > index c23d5e4..e563af5 100644
> > > > > > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> > > > > > > > > > > > > > @@ -18,6 +18,7 @@
> > > > > > > > > > > > > > #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> > > > > > > > > > > > > > #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> > > > > > > > > > > > > > #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> > > > > > > > > > > > > > +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> > > > > > > > > > > > > > #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> > > > > > > > > > > > > > #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> > > > > > > > > > > > > > #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> > > > > > > > > > > > > > @@ -27,5 +28,6 @@
> > > > > > > > > > > > > > #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> > > > > > > > > > > > > > #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> > > > > > > > > > > > > > #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> > > > > > > > > > > > > > +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > #endif
> > > > > > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > > > > > > index f420f8f..ef392ce 100644
> > > > > > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> > > > > > > > > > > > > > @@ -56,6 +56,8 @@
> > > > > > > > > > > > > > #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> > > > > > > > > > > > > > #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> > > > > > > > > > > > > > #define QSERDES_V6_COM_PLL_IVCO 0xf4
> > > > > > > > > > > > > > +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> > > > > > > > > > > > > > +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> > > > > > > > > > > > > > #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> > > > > > > > > > > > > > #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> > > > > > > > > > > > > > #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> > > > > > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > > > > > > index 15bcb4b..48f31c8 100644
> > > > > > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> > > > > > > > > > > > > > @@ -10,10 +10,20 @@
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> > > > > > > > > > > > > > @@ -25,6 +35,8 @@
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> > > > > > > > > > > > > > #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> > > > > > > > > > > > > > +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > #endif
> > > > > > > > > > > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > > > > > > index 3927eba..e0a01497 100644
> > > > > > > > > > > > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > > > > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> > > > > > > > > > > > > > @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> > > > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> > > > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> > > > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> > > > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > > > > > > > > +
> > > > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> > > > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> > > > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> > > > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> > > > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> > > > > > > > > > > > > > +};
> > > > > > > > > > > > > > +
> > > > > > > > > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> > > > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> > > > > > > > > > > > > > +};
> > > > > > > > > > > > > > +
> > > > > > > > > > > > > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> > > > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> > > > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> > > > > > > > > > > > > > QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> > > > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> > > > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> > > > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> > > > > > > > > > > > > > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> > > > > > > > > > > > >
> > > > > > > > > > > > > Aside from moving these registers to the HS_G4 table, you are also
> > > > > > > > > > > > > changing these registers. It makes me think that there was an error in
> > > > > > > > > > > > > the original programming sequence.
> > > > > > > > > > > > > If that is correct, could you please split the patch into two pieces:
> > > > > > > > > > > > > - Fix programming sequence (add proper Fixes tags)
> > > > > > > > > > > > > - Split G4 and G5 tables.
> > > > > > > > > > > >
> > > > > > > > > > > > Ack
> > > > > > > > > > > >
> > > > > > > > > > > > >
> > > > > > > > > > > > > > +
> > > > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> > > > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> > > > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> > > > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> > > > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> > > > > > > > > > > > > > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> > > > > > > > > > > > >
> > > > > > > > > > > > > I see all the MODE1 registers being only present in G4 and G5 tables.
> > > > > > > > > > > > > Should they be programmed for the modes lower than G4?
> > > > > > > > > > > > >
> > > > > > > > > > > >
> > > > > > > > > > > > We use G4 table for all the modes <= G4.
> > > > > > > > > > >
> > > > > > > > > > > Could you please point me how it's handled?
> > > > > > > > > > > In the patch I see just:
> > > > > > > > > > >
> > > > > > > > > > > if (qmp->submode == UFS_HS_G4)
> > > > > > > > > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> > > > > > > > > > > else if (qmp->submode == UFS_HS_G5)
> > > > > > > > > > > qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> > > > > > > > > > >
> > > > > > > > > > > Which looks like two special cases (HS_G4 and HS_G5) and nothing for
> > > > > > > > > > > anything else.
> > > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
> > > > > > > > > > sequence will be used and for G5, G5 sequence will be used.
> > > > > > > > > >
> > > > > > > > >
> > > > > > > > > That's what I could not find in the UFS driver. I see a call to
> > > > > > > > > `phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
> > > > > > > > > host->phy_gear is initialised to UFS_HS_G2.
> > > > > > > > >
> > > > > > > >
> > > > > > > > You need to check the UFS driver changes in this series to get the complete
> > > > > > > > picture as the logic is getting changed.
> > > > > > > >
> > > > > > > > It is common to get confused because of the way the UFS driver (qcom mostly)
> > > > > > > > handles the PHY init sequence programming. We used to have only one init
> > > > > > > > sequence for older targets and life was easy. But when I wanted to add G4
> > > > > > > > support for SM8250, I learned that there are 2 separate init sequences. One for
> > > > > > > > non-G4 and other for G4. So I used the phy_sub_mode property to pass the
> > > > > > > > relevant mode from the UFS driver to the PHY driver and programmed the sequence
> > > > > > > > accordingly. This got extended to non-G5 and G5 now.
> > > > > > > >
> > > > > > > > Now, the UFS driver will start probing from a low gear for older targets (G2)
> > > > > > > > and G4/G5 for newer ones then scale up based on the device and host capability.
> > > > > > > > For older targets, the common table (tbls) will be used if the submode doesn't
> > > > > > > > match G4/G5. But for newer targets, the UFS driver will _only_ pass G4 or G5 as
> > > > > > > > the phy_gear, so those specific sequence will only be used.
> > > > > > > >
> > > > > > > > Hope I'm clear.
> > > > > > >
> > > > > > > Yes, it is now clear, thank you!
> > > > > > >
> > > > > > > Would it be possible / feasible / logical to maintain this idea even
> > > > > > > for newer platforms (leaving the HS_A / HS_B aside)?
> > > > > > >
> > > > > > > tbls - works for HS_G2
> > > > > > > tbls + tbls_g4 - works for HS_G4
> > > > > > > tbls + tbls_g5 - works for HS_G5
> > > > > > >
> > > > > >
> > > > > > No. The PHY team only gives 2 init sequences for any SoC now.
> > > > >
> > > > > Ack. Then the code should become
> > > > > if (HS_G5)
> > > > > program(tbls_hs_g5)
> > > > > else
> > > > > program(tbls_hs_g4);
> > > > >
> > > >
> > > > This should work. Even if we have to accomodate G6 in the future, we can use
> > > > "else if" for that and keep G4 as the "else" condition. This logic can also be
> > > > optimized in the future.
> > >
> > > That would make dual init meaningless for old targets. Say on SM8450, the
> > > initial PHY gear is G2, with the "else" condition, during the first init, G4
> > > table would be programmed, then gear negotiation happens btw host and device
> > > and the negotiated gear is G3 (assume a UFS2.x is connected). During the 2nd
> > > init, the "else" condition would __again__ program the G4 table - it is not
> > > programming the non-G4 table for power saving. The dual init is supposed to
> > > find the optimal PHY settings, but the "else" condition is programming G4
> > > table unconditinally.
> > >
> > > With the original code change in this patch, the dual init works as it is
> > > for old targets. say SM8450, the initial PHY gear is G2, during the 2nd
> > > init, it is programming the non-G4 table (assume a UFS2.x is connected), but
> > > not the G4 table.
> > >
> >
> > You are right. I completely overlooked the compatibility for old targets. But
> > still we can move the common table to the "else" condition. This makes it clear
> > that one of the 3 will be programmed at a time. But with the current logic, I
> > get the impression that common table is overridden by G4/G5 tables.
> >
> > So this is what I'm suggesting:
> >
> > if (HS_G5)
> > program(tbls_hs_g5)
> > else if (HS_G4)
> > program(tbls_hs_g4);
> > else
> > program(tbls_hs_common);
> >
>
> Common table is needed regardlessly, we cannot put it in "else", otherwise
> it would break all targets -
>
> On old targets (no G5 supported):
> Common table - supports non-G4 (G3 and lower)
> Common table + G4 table - supports G4
>
> On new targets (G5 supported):
> Common table - supports nothing, as it is just common parts of G4 table
> and G5 table.
> Common table + G4 table - support non-G5 (G4 and lower)
> Common table + G5 table - support G5
>
Doh! I missed the fact that common table is not a standalone table. Sorry for
the confusion. Let's keep it as you proposed for now. I still don't like the if
conditions as it would just keep growing with future gears, but we can get to it
later.
- Mani
> Thanks,
> Can Guo.
>
> > - Mani
> >
> > > Thanks,
> > > Can Guo.
> > > >
> > > > - Mani
> > > >
> > > > > >
> > > > > > - Mani
> > > > > >
> > > > > > > I mean here that the PHY driver should not depend on the knowledge
> > > > > > > that the UFS driver will not be setting HS_G2 for some particular
> > > > > > > platform and ideally it should continue working if at some point we
> > > > > > > change the UFS driver to set HS_G2.
> > > > > > >
> > > > > > >
> > > > > > > >
> > > > > > > > - Mani
> > > > > > > >
> > > > > > > > > Maybe we should change the condition here (in the PHY driver) to:
> > > > > > > > >
> > > > > > > > > if (qmp->submode <= UFS_HS_G4)
> > > > > > > > >
> > > > > > > > > ?
> > > > > > > > > --
> > > > > > > > > With best wishes
> > > > > > > > > Dmitry
> > > > > > > >
> > > > > > > > --
> > > > > > > > மணிவண்ணன் சதாசிவம்
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > > --
> > > > > > > With best wishes
> > > > > > > Dmitry
> > > > > >
> > > > > > --
> > > > > > மணிவண்ணன் சதாசிவம்
> > > > >
> > > > >
> > > > >
> > > > > --
> > > > > With best wishes
> > > > > Dmitry
> > > >
> >
--
மணிவண்ணன் சதாசிவம்
--
linux-phy mailing list
linux-phy@lists.infradead.org
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^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-12 5:13 ` Can Guo
@ 2023-11-14 9:15 ` Dmitry Baryshkov
-1 siblings, 0 replies; 86+ messages in thread
From: Dmitry Baryshkov @ 2023-11-14 9:15 UTC (permalink / raw)
To: Can Guo
Cc: Manivannan Sadhasivam, Can Guo, bvanassche, stanley.chu,
adrian.hunter, beanhuo, avri.altman, junwoo80.lee,
martin.petersen, linux-scsi, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
On Sun, 12 Nov 2023 at 07:13, Can Guo <quic_cang@quicinc.com> wrote:
>
> Hi Mani,
>
> On 11/11/2023 12:12 PM, Manivannan Sadhasivam wrote:
> > On Fri, Nov 10, 2023 at 10:40:53PM +0800, Can Guo wrote:
> >>
> >>
> >> On 11/10/2023 9:18 PM, Manivannan Sadhasivam wrote:
> >>> On Fri, Nov 10, 2023 at 12:11:46AM +0200, Dmitry Baryshkov wrote:
> >>>> On Thu, 9 Nov 2023 at 18:04, Manivannan Sadhasivam <mani@kernel.org> wrote:
> >>>>>
> >>>>> On Thu, Nov 09, 2023 at 01:00:51PM +0200, Dmitry Baryshkov wrote:
> >>>>>> On Thu, 9 Nov 2023 at 12:43, Manivannan Sadhasivam <mani@kernel.org> wrote:
> >>>>>>>
> >>>>>>> On Thu, Nov 09, 2023 at 11:40:51AM +0200, Dmitry Baryshkov wrote:
> >>>>>>>> On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
> >>>>>>>>>
> >>>>>>>>> On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
> >>>>>>>>>> On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
> >>>>>>>>>>>
> >>>>>>>>>>> On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> >>>>>>>>>>>> On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> From: Can Guo <quic_cang@quicinc.com>
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> On SM8550, two sets of UFS PHY settings are provided, one set is to support
> >>>>>>>>>>>>> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> >>>>>>>>>>>>> settings are programming different values to different registers, mixing
> >>>>>>>>>>>>> the two sets and/or overwriting one set with another set is definitely not
> >>>>>>>>>>>>> blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> >>>>>>>>>>>>> need to split the two sets into their dedicated tables, and leave only the
> >>>>>>>>>>>>> common settings in the .tlbs. To have the PHY programmed with the correct
> >>>>>>>>>>>>> set of PHY settings, the submode passed to PHY driver must be either HS-G4
> >>>>>>>>>>>>> or HS-G5.
> >>>>>>>>>>>>>
> >>>>>>>>>>>
> >>>>>>>>>>> You should also mention that this issue is also present in G4 supported targets.
> >>>>>>>>>>> And a note that it will get fixed later.
> >>>>>>>>>>>
> >>>>>>>>>>>>> Signed-off-by: Can Guo <quic_cang@quicinc.com>
> >>>>>>>>>>>>> ---
> >>>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> >>>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> >>>>>>>>>>>>> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> >>>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> >>>>>>>>>>>>> 4 files changed, 115 insertions(+), 13 deletions(-)
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> >>>>>>>>>>>>> index c23d5e4..e563af5 100644
> >>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> >>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> >>>>>>>>>>>>> @@ -18,6 +18,7 @@
> >>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> >>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> >>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> >>>>>>>>>>>>> +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> >>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> >>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> >>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> >>>>>>>>>>>>> @@ -27,5 +28,6 @@
> >>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> >>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> >>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> >>>>>>>>>>>>> +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> #endif
> >>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> >>>>>>>>>>>>> index f420f8f..ef392ce 100644
> >>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> >>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> >>>>>>>>>>>>> @@ -56,6 +56,8 @@
> >>>>>>>>>>>>> #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> >>>>>>>>>>>>> #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> >>>>>>>>>>>>> #define QSERDES_V6_COM_PLL_IVCO 0xf4
> >>>>>>>>>>>>> +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> >>>>>>>>>>>>> +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> >>>>>>>>>>>>> #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> >>>>>>>>>>>>> #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> >>>>>>>>>>>>> #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> >>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> >>>>>>>>>>>>> index 15bcb4b..48f31c8 100644
> >>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> >>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> >>>>>>>>>>>>> @@ -10,10 +10,20 @@
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> >>>>>>>>>>>>> @@ -25,6 +35,8 @@
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> #endif
> >>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >>>>>>>>>>>>> index 3927eba..e0a01497 100644
> >>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >>>>>>>>>>>>> @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> >>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> >>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> >>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> >>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> >>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> >>>>>>>>>>>>> +
> >>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> >>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> >>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> >>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> >>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> >>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> >>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> >>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> >>>>>>>>>>>>> +};
> >>>>>>>>>>>>> +
> >>>>>>>>>>>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> >>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> >>>>>>>>>>>>> +};
> >>>>>>>>>>>>> +
> >>>>>>>>>>>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> >>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> >>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> >>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> >>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> >>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> >>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> >>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> >>>>>>>>>>>>
> >>>>>>>>>>>> Aside from moving these registers to the HS_G4 table, you are also
> >>>>>>>>>>>> changing these registers. It makes me think that there was an error in
> >>>>>>>>>>>> the original programming sequence.
> >>>>>>>>>>>> If that is correct, could you please split the patch into two pieces:
> >>>>>>>>>>>> - Fix programming sequence (add proper Fixes tags)
> >>>>>>>>>>>> - Split G4 and G5 tables.
> >>>>>>>>>>>
> >>>>>>>>>>> Ack
> >>>>>>>>>>>
> >>>>>>>>>>>>
> >>>>>>>>>>>>> +
> >>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> >>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> >>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> >>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> >>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> >>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> >>>>>>>>>>>>
> >>>>>>>>>>>> I see all the MODE1 registers being only present in G4 and G5 tables.
> >>>>>>>>>>>> Should they be programmed for the modes lower than G4?
> >>>>>>>>>>>>
> >>>>>>>>>>>
> >>>>>>>>>>> We use G4 table for all the modes <= G4.
> >>>>>>>>>>
> >>>>>>>>>> Could you please point me how it's handled?
> >>>>>>>>>> In the patch I see just:
> >>>>>>>>>>
> >>>>>>>>>> if (qmp->submode == UFS_HS_G4)
> >>>>>>>>>> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> >>>>>>>>>> else if (qmp->submode == UFS_HS_G5)
> >>>>>>>>>> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> >>>>>>>>>>
> >>>>>>>>>> Which looks like two special cases (HS_G4 and HS_G5) and nothing for
> >>>>>>>>>> anything else.
> >>>>>>>>>>
> >>>>>>>>>
> >>>>>>>>> Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
> >>>>>>>>> sequence will be used and for G5, G5 sequence will be used.
> >>>>>>>>>
> >>>>>>>>
> >>>>>>>> That's what I could not find in the UFS driver. I see a call to
> >>>>>>>> `phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
> >>>>>>>> host->phy_gear is initialised to UFS_HS_G2.
> >>>>>>>>
> >>>>>>>
> >>>>>>> You need to check the UFS driver changes in this series to get the complete
> >>>>>>> picture as the logic is getting changed.
> >>>>>>>
> >>>>>>> It is common to get confused because of the way the UFS driver (qcom mostly)
> >>>>>>> handles the PHY init sequence programming. We used to have only one init
> >>>>>>> sequence for older targets and life was easy. But when I wanted to add G4
> >>>>>>> support for SM8250, I learned that there are 2 separate init sequences. One for
> >>>>>>> non-G4 and other for G4. So I used the phy_sub_mode property to pass the
> >>>>>>> relevant mode from the UFS driver to the PHY driver and programmed the sequence
> >>>>>>> accordingly. This got extended to non-G5 and G5 now.
> >>>>>>>
> >>>>>>> Now, the UFS driver will start probing from a low gear for older targets (G2)
> >>>>>>> and G4/G5 for newer ones then scale up based on the device and host capability.
> >>>>>>> For older targets, the common table (tbls) will be used if the submode doesn't
> >>>>>>> match G4/G5. But for newer targets, the UFS driver will _only_ pass G4 or G5 as
> >>>>>>> the phy_gear, so those specific sequence will only be used.
> >>>>>>>
> >>>>>>> Hope I'm clear.
> >>>>>>
> >>>>>> Yes, it is now clear, thank you!
> >>>>>>
> >>>>>> Would it be possible / feasible / logical to maintain this idea even
> >>>>>> for newer platforms (leaving the HS_A / HS_B aside)?
> >>>>>>
> >>>>>> tbls - works for HS_G2
> >>>>>> tbls + tbls_g4 - works for HS_G4
> >>>>>> tbls + tbls_g5 - works for HS_G5
> >>>>>>
> >>>>>
> >>>>> No. The PHY team only gives 2 init sequences for any SoC now.
> >>>>
> >>>> Ack. Then the code should become
> >>>> if (HS_G5)
> >>>> program(tbls_hs_g5)
> >>>> else
> >>>> program(tbls_hs_g4);
> >>>>
> >>>
> >>> This should work. Even if we have to accomodate G6 in the future, we can use
> >>> "else if" for that and keep G4 as the "else" condition. This logic can also be
> >>> optimized in the future.
> >>
> >> That would make dual init meaningless for old targets. Say on SM8450, the
> >> initial PHY gear is G2, with the "else" condition, during the first init, G4
> >> table would be programmed, then gear negotiation happens btw host and device
> >> and the negotiated gear is G3 (assume a UFS2.x is connected). During the 2nd
> >> init, the "else" condition would __again__ program the G4 table - it is not
> >> programming the non-G4 table for power saving. The dual init is supposed to
> >> find the optimal PHY settings, but the "else" condition is programming G4
> >> table unconditinally.
> >>
> >> With the original code change in this patch, the dual init works as it is
> >> for old targets. say SM8450, the initial PHY gear is G2, during the 2nd
> >> init, it is programming the non-G4 table (assume a UFS2.x is connected), but
> >> not the G4 table.
> >>
> >
> > You are right. I completely overlooked the compatibility for old targets. But
> > still we can move the common table to the "else" condition. This makes it clear
> > that one of the 3 will be programmed at a time. But with the current logic, I
> > get the impression that common table is overridden by G4/G5 tables.
> >
> > So this is what I'm suggesting:
> >
> > if (HS_G5)
> > program(tbls_hs_g5)
> > else if (HS_G4)
> > program(tbls_hs_g4);
> > else
> > program(tbls_hs_common);
> >
>
> Common table is needed regardlessly, we cannot put it in "else",
> otherwise it would break all targets -
>
> On old targets (no G5 supported):
> Common table - supports non-G4 (G3 and lower)
> Common table + G4 table - supports G4
>
> On new targets (G5 supported):
> Common table - supports nothing, as it is just common parts of G4
> table and G5 table.
> Common table + G4 table - support non-G5 (G4 and lower)
> Common table + G5 table - support G5
There is one issue with this approach, which you might be able to fix.
For the older PHYs we have two cases: pre-G4 and G4. The host driver
can set any mode of its choice.
For the newer targets we only support G4 and G5 modes, don't we?
However the knowledge that there will be no modes lower than G4 is
hidden inside the host driver.
Could you please add a flag / condition to the PHY driver to error out
if the host tries to set e.g. G2 for the newer PHYs?
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-14 9:15 ` Dmitry Baryshkov
0 siblings, 0 replies; 86+ messages in thread
From: Dmitry Baryshkov @ 2023-11-14 9:15 UTC (permalink / raw)
To: Can Guo
Cc: Manivannan Sadhasivam, Can Guo, bvanassche, stanley.chu,
adrian.hunter, beanhuo, avri.altman, junwoo80.lee,
martin.petersen, linux-scsi, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
On Sun, 12 Nov 2023 at 07:13, Can Guo <quic_cang@quicinc.com> wrote:
>
> Hi Mani,
>
> On 11/11/2023 12:12 PM, Manivannan Sadhasivam wrote:
> > On Fri, Nov 10, 2023 at 10:40:53PM +0800, Can Guo wrote:
> >>
> >>
> >> On 11/10/2023 9:18 PM, Manivannan Sadhasivam wrote:
> >>> On Fri, Nov 10, 2023 at 12:11:46AM +0200, Dmitry Baryshkov wrote:
> >>>> On Thu, 9 Nov 2023 at 18:04, Manivannan Sadhasivam <mani@kernel.org> wrote:
> >>>>>
> >>>>> On Thu, Nov 09, 2023 at 01:00:51PM +0200, Dmitry Baryshkov wrote:
> >>>>>> On Thu, 9 Nov 2023 at 12:43, Manivannan Sadhasivam <mani@kernel.org> wrote:
> >>>>>>>
> >>>>>>> On Thu, Nov 09, 2023 at 11:40:51AM +0200, Dmitry Baryshkov wrote:
> >>>>>>>> On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
> >>>>>>>>>
> >>>>>>>>> On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
> >>>>>>>>>> On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
> >>>>>>>>>>>
> >>>>>>>>>>> On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
> >>>>>>>>>>>> On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> From: Can Guo <quic_cang@quicinc.com>
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> On SM8550, two sets of UFS PHY settings are provided, one set is to support
> >>>>>>>>>>>>> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> >>>>>>>>>>>>> settings are programming different values to different registers, mixing
> >>>>>>>>>>>>> the two sets and/or overwriting one set with another set is definitely not
> >>>>>>>>>>>>> blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
> >>>>>>>>>>>>> need to split the two sets into their dedicated tables, and leave only the
> >>>>>>>>>>>>> common settings in the .tlbs. To have the PHY programmed with the correct
> >>>>>>>>>>>>> set of PHY settings, the submode passed to PHY driver must be either HS-G4
> >>>>>>>>>>>>> or HS-G5.
> >>>>>>>>>>>>>
> >>>>>>>>>>>
> >>>>>>>>>>> You should also mention that this issue is also present in G4 supported targets.
> >>>>>>>>>>> And a note that it will get fixed later.
> >>>>>>>>>>>
> >>>>>>>>>>>>> Signed-off-by: Can Guo <quic_cang@quicinc.com>
> >>>>>>>>>>>>> ---
> >>>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> >>>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> >>>>>>>>>>>>> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
> >>>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
> >>>>>>>>>>>>> 4 files changed, 115 insertions(+), 13 deletions(-)
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> >>>>>>>>>>>>> index c23d5e4..e563af5 100644
> >>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> >>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> >>>>>>>>>>>>> @@ -18,6 +18,7 @@
> >>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> >>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> >>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> >>>>>>>>>>>>> +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> >>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> >>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> >>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> >>>>>>>>>>>>> @@ -27,5 +28,6 @@
> >>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> >>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> >>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> >>>>>>>>>>>>> +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> #endif
> >>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> >>>>>>>>>>>>> index f420f8f..ef392ce 100644
> >>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> >>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> >>>>>>>>>>>>> @@ -56,6 +56,8 @@
> >>>>>>>>>>>>> #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> >>>>>>>>>>>>> #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> >>>>>>>>>>>>> #define QSERDES_V6_COM_PLL_IVCO 0xf4
> >>>>>>>>>>>>> +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> >>>>>>>>>>>>> +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> >>>>>>>>>>>>> #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> >>>>>>>>>>>>> #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> >>>>>>>>>>>>> #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> >>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> >>>>>>>>>>>>> index 15bcb4b..48f31c8 100644
> >>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> >>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> >>>>>>>>>>>>> @@ -10,10 +10,20 @@
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> >>>>>>>>>>>>> @@ -25,6 +35,8 @@
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> >>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> >>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> #endif
> >>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >>>>>>>>>>>>> index 3927eba..e0a01497 100644
> >>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >>>>>>>>>>>>> @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> >>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> >>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> >>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> >>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> >>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> >>>>>>>>>>>>> +
> >>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> >>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> >>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> >>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> >>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> >>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> >>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> >>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> >>>>>>>>>>>>> +};
> >>>>>>>>>>>>> +
> >>>>>>>>>>>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> >>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> >>>>>>>>>>>>> +};
> >>>>>>>>>>>>> +
> >>>>>>>>>>>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> >>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> >>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> >>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> >>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> >>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> >>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> >>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> >>>>>>>>>>>>
> >>>>>>>>>>>> Aside from moving these registers to the HS_G4 table, you are also
> >>>>>>>>>>>> changing these registers. It makes me think that there was an error in
> >>>>>>>>>>>> the original programming sequence.
> >>>>>>>>>>>> If that is correct, could you please split the patch into two pieces:
> >>>>>>>>>>>> - Fix programming sequence (add proper Fixes tags)
> >>>>>>>>>>>> - Split G4 and G5 tables.
> >>>>>>>>>>>
> >>>>>>>>>>> Ack
> >>>>>>>>>>>
> >>>>>>>>>>>>
> >>>>>>>>>>>>> +
> >>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> >>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> >>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> >>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> >>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> >>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> >>>>>>>>>>>>
> >>>>>>>>>>>> I see all the MODE1 registers being only present in G4 and G5 tables.
> >>>>>>>>>>>> Should they be programmed for the modes lower than G4?
> >>>>>>>>>>>>
> >>>>>>>>>>>
> >>>>>>>>>>> We use G4 table for all the modes <= G4.
> >>>>>>>>>>
> >>>>>>>>>> Could you please point me how it's handled?
> >>>>>>>>>> In the patch I see just:
> >>>>>>>>>>
> >>>>>>>>>> if (qmp->submode == UFS_HS_G4)
> >>>>>>>>>> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
> >>>>>>>>>> else if (qmp->submode == UFS_HS_G5)
> >>>>>>>>>> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
> >>>>>>>>>>
> >>>>>>>>>> Which looks like two special cases (HS_G4 and HS_G5) and nothing for
> >>>>>>>>>> anything else.
> >>>>>>>>>>
> >>>>>>>>>
> >>>>>>>>> Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
> >>>>>>>>> sequence will be used and for G5, G5 sequence will be used.
> >>>>>>>>>
> >>>>>>>>
> >>>>>>>> That's what I could not find in the UFS driver. I see a call to
> >>>>>>>> `phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
> >>>>>>>> host->phy_gear is initialised to UFS_HS_G2.
> >>>>>>>>
> >>>>>>>
> >>>>>>> You need to check the UFS driver changes in this series to get the complete
> >>>>>>> picture as the logic is getting changed.
> >>>>>>>
> >>>>>>> It is common to get confused because of the way the UFS driver (qcom mostly)
> >>>>>>> handles the PHY init sequence programming. We used to have only one init
> >>>>>>> sequence for older targets and life was easy. But when I wanted to add G4
> >>>>>>> support for SM8250, I learned that there are 2 separate init sequences. One for
> >>>>>>> non-G4 and other for G4. So I used the phy_sub_mode property to pass the
> >>>>>>> relevant mode from the UFS driver to the PHY driver and programmed the sequence
> >>>>>>> accordingly. This got extended to non-G5 and G5 now.
> >>>>>>>
> >>>>>>> Now, the UFS driver will start probing from a low gear for older targets (G2)
> >>>>>>> and G4/G5 for newer ones then scale up based on the device and host capability.
> >>>>>>> For older targets, the common table (tbls) will be used if the submode doesn't
> >>>>>>> match G4/G5. But for newer targets, the UFS driver will _only_ pass G4 or G5 as
> >>>>>>> the phy_gear, so those specific sequence will only be used.
> >>>>>>>
> >>>>>>> Hope I'm clear.
> >>>>>>
> >>>>>> Yes, it is now clear, thank you!
> >>>>>>
> >>>>>> Would it be possible / feasible / logical to maintain this idea even
> >>>>>> for newer platforms (leaving the HS_A / HS_B aside)?
> >>>>>>
> >>>>>> tbls - works for HS_G2
> >>>>>> tbls + tbls_g4 - works for HS_G4
> >>>>>> tbls + tbls_g5 - works for HS_G5
> >>>>>>
> >>>>>
> >>>>> No. The PHY team only gives 2 init sequences for any SoC now.
> >>>>
> >>>> Ack. Then the code should become
> >>>> if (HS_G5)
> >>>> program(tbls_hs_g5)
> >>>> else
> >>>> program(tbls_hs_g4);
> >>>>
> >>>
> >>> This should work. Even if we have to accomodate G6 in the future, we can use
> >>> "else if" for that and keep G4 as the "else" condition. This logic can also be
> >>> optimized in the future.
> >>
> >> That would make dual init meaningless for old targets. Say on SM8450, the
> >> initial PHY gear is G2, with the "else" condition, during the first init, G4
> >> table would be programmed, then gear negotiation happens btw host and device
> >> and the negotiated gear is G3 (assume a UFS2.x is connected). During the 2nd
> >> init, the "else" condition would __again__ program the G4 table - it is not
> >> programming the non-G4 table for power saving. The dual init is supposed to
> >> find the optimal PHY settings, but the "else" condition is programming G4
> >> table unconditinally.
> >>
> >> With the original code change in this patch, the dual init works as it is
> >> for old targets. say SM8450, the initial PHY gear is G2, during the 2nd
> >> init, it is programming the non-G4 table (assume a UFS2.x is connected), but
> >> not the G4 table.
> >>
> >
> > You are right. I completely overlooked the compatibility for old targets. But
> > still we can move the common table to the "else" condition. This makes it clear
> > that one of the 3 will be programmed at a time. But with the current logic, I
> > get the impression that common table is overridden by G4/G5 tables.
> >
> > So this is what I'm suggesting:
> >
> > if (HS_G5)
> > program(tbls_hs_g5)
> > else if (HS_G4)
> > program(tbls_hs_g4);
> > else
> > program(tbls_hs_common);
> >
>
> Common table is needed regardlessly, we cannot put it in "else",
> otherwise it would break all targets -
>
> On old targets (no G5 supported):
> Common table - supports non-G4 (G3 and lower)
> Common table + G4 table - supports G4
>
> On new targets (G5 supported):
> Common table - supports nothing, as it is just common parts of G4
> table and G5 table.
> Common table + G4 table - support non-G5 (G4 and lower)
> Common table + G5 table - support G5
There is one issue with this approach, which you might be able to fix.
For the older PHYs we have two cases: pre-G4 and G4. The host driver
can set any mode of its choice.
For the newer targets we only support G4 and G5 modes, don't we?
However the knowledge that there will be no modes lower than G4 is
hidden inside the host driver.
Could you please add a flag / condition to the PHY driver to error out
if the host tries to set e.g. G2 for the newer PHYs?
--
With best wishes
Dmitry
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
2023-11-14 9:15 ` Dmitry Baryshkov
@ 2023-11-15 7:51 ` Can Guo
-1 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-15 7:51 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Manivannan Sadhasivam, Can Guo, bvanassche, stanley.chu,
adrian.hunter, beanhuo, avri.altman, junwoo80.lee,
martin.petersen, linux-scsi, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
On 11/14/2023 5:15 PM, Dmitry Baryshkov wrote:
> On Sun, 12 Nov 2023 at 07:13, Can Guo <quic_cang@quicinc.com> wrote:
>>
>> Hi Mani,
>>
>> On 11/11/2023 12:12 PM, Manivannan Sadhasivam wrote:
>>> On Fri, Nov 10, 2023 at 10:40:53PM +0800, Can Guo wrote:
>>>>
>>>>
>>>> On 11/10/2023 9:18 PM, Manivannan Sadhasivam wrote:
>>>>> On Fri, Nov 10, 2023 at 12:11:46AM +0200, Dmitry Baryshkov wrote:
>>>>>> On Thu, 9 Nov 2023 at 18:04, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>>>>>
>>>>>>> On Thu, Nov 09, 2023 at 01:00:51PM +0200, Dmitry Baryshkov wrote:
>>>>>>>> On Thu, 9 Nov 2023 at 12:43, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>>>>>>>
>>>>>>>>> On Thu, Nov 09, 2023 at 11:40:51AM +0200, Dmitry Baryshkov wrote:
>>>>>>>>>> On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>>>>>>>>>
>>>>>>>>>>> On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
>>>>>>>>>>>> On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>>>>>>>>>>>
>>>>>>>>>>>>> On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
>>>>>>>>>>>>>> On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> From: Can Guo <quic_cang@quicinc.com>
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> On SM8550, two sets of UFS PHY settings are provided, one set is to support
>>>>>>>>>>>>>>> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
>>>>>>>>>>>>>>> settings are programming different values to different registers, mixing
>>>>>>>>>>>>>>> the two sets and/or overwriting one set with another set is definitely not
>>>>>>>>>>>>>>> blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
>>>>>>>>>>>>>>> need to split the two sets into their dedicated tables, and leave only the
>>>>>>>>>>>>>>> common settings in the .tlbs. To have the PHY programmed with the correct
>>>>>>>>>>>>>>> set of PHY settings, the submode passed to PHY driver must be either HS-G4
>>>>>>>>>>>>>>> or HS-G5.
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>> You should also mention that this issue is also present in G4 supported targets.
>>>>>>>>>>>>> And a note that it will get fixed later.
>>>>>>>>>>>>>
>>>>>>>>>>>>>>> Signed-off-by: Can Guo <quic_cang@quicinc.com>
>>>>>>>>>>>>>>> ---
>>>>>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
>>>>>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
>>>>>>>>>>>>>>> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
>>>>>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
>>>>>>>>>>>>>>> 4 files changed, 115 insertions(+), 13 deletions(-)
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>>>>>>>>>>>>>> index c23d5e4..e563af5 100644
>>>>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>>>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>>>>>>>>>>>>>> @@ -18,6 +18,7 @@
>>>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
>>>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
>>>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
>>>>>>>>>>>>>>> +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
>>>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
>>>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
>>>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
>>>>>>>>>>>>>>> @@ -27,5 +28,6 @@
>>>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
>>>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
>>>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
>>>>>>>>>>>>>>> +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> #endif
>>>>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>>>>>>>>>>>>> index f420f8f..ef392ce 100644
>>>>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>>>>>>>>>>>>> @@ -56,6 +56,8 @@
>>>>>>>>>>>>>>> #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
>>>>>>>>>>>>>>> #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
>>>>>>>>>>>>>>> #define QSERDES_V6_COM_PLL_IVCO 0xf4
>>>>>>>>>>>>>>> +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
>>>>>>>>>>>>>>> +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
>>>>>>>>>>>>>>> #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
>>>>>>>>>>>>>>> #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
>>>>>>>>>>>>>>> #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
>>>>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>>>>>>>>>>>>>> index 15bcb4b..48f31c8 100644
>>>>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>>>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>>>>>>>>>>>>>> @@ -10,10 +10,20 @@
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
>>>>>>>>>>>>>>> @@ -25,6 +35,8 @@
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> #endif
>>>>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>>>>>>>>>>>> index 3927eba..e0a01497 100644
>>>>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>>>>>>>>>>>> @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
>>>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
>>>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
>>>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
>>>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
>>>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
>>>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
>>>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
>>>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>>>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>>>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
>>>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
>>>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
>>>>>>>>>>>>>>> +};
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
>>>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
>>>>>>>>>>>>>>> +};
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
>>>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
>>>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
>>>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
>>>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>>>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>>>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
>>>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Aside from moving these registers to the HS_G4 table, you are also
>>>>>>>>>>>>>> changing these registers. It makes me think that there was an error in
>>>>>>>>>>>>>> the original programming sequence.
>>>>>>>>>>>>>> If that is correct, could you please split the patch into two pieces:
>>>>>>>>>>>>>> - Fix programming sequence (add proper Fixes tags)
>>>>>>>>>>>>>> - Split G4 and G5 tables.
>>>>>>>>>>>>>
>>>>>>>>>>>>> Ack
>>>>>>>>>>>>>
>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
>>>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
>>>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
>>>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
>>>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
>>>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> I see all the MODE1 registers being only present in G4 and G5 tables.
>>>>>>>>>>>>>> Should they be programmed for the modes lower than G4?
>>>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>> We use G4 table for all the modes <= G4.
>>>>>>>>>>>>
>>>>>>>>>>>> Could you please point me how it's handled?
>>>>>>>>>>>> In the patch I see just:
>>>>>>>>>>>>
>>>>>>>>>>>> if (qmp->submode == UFS_HS_G4)
>>>>>>>>>>>> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
>>>>>>>>>>>> else if (qmp->submode == UFS_HS_G5)
>>>>>>>>>>>> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
>>>>>>>>>>>>
>>>>>>>>>>>> Which looks like two special cases (HS_G4 and HS_G5) and nothing for
>>>>>>>>>>>> anything else.
>>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
>>>>>>>>>>> sequence will be used and for G5, G5 sequence will be used.
>>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> That's what I could not find in the UFS driver. I see a call to
>>>>>>>>>> `phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
>>>>>>>>>> host->phy_gear is initialised to UFS_HS_G2.
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> You need to check the UFS driver changes in this series to get the complete
>>>>>>>>> picture as the logic is getting changed.
>>>>>>>>>
>>>>>>>>> It is common to get confused because of the way the UFS driver (qcom mostly)
>>>>>>>>> handles the PHY init sequence programming. We used to have only one init
>>>>>>>>> sequence for older targets and life was easy. But when I wanted to add G4
>>>>>>>>> support for SM8250, I learned that there are 2 separate init sequences. One for
>>>>>>>>> non-G4 and other for G4. So I used the phy_sub_mode property to pass the
>>>>>>>>> relevant mode from the UFS driver to the PHY driver and programmed the sequence
>>>>>>>>> accordingly. This got extended to non-G5 and G5 now.
>>>>>>>>>
>>>>>>>>> Now, the UFS driver will start probing from a low gear for older targets (G2)
>>>>>>>>> and G4/G5 for newer ones then scale up based on the device and host capability.
>>>>>>>>> For older targets, the common table (tbls) will be used if the submode doesn't
>>>>>>>>> match G4/G5. But for newer targets, the UFS driver will _only_ pass G4 or G5 as
>>>>>>>>> the phy_gear, so those specific sequence will only be used.
>>>>>>>>>
>>>>>>>>> Hope I'm clear.
>>>>>>>>
>>>>>>>> Yes, it is now clear, thank you!
>>>>>>>>
>>>>>>>> Would it be possible / feasible / logical to maintain this idea even
>>>>>>>> for newer platforms (leaving the HS_A / HS_B aside)?
>>>>>>>>
>>>>>>>> tbls - works for HS_G2
>>>>>>>> tbls + tbls_g4 - works for HS_G4
>>>>>>>> tbls + tbls_g5 - works for HS_G5
>>>>>>>>
>>>>>>>
>>>>>>> No. The PHY team only gives 2 init sequences for any SoC now.
>>>>>>
>>>>>> Ack. Then the code should become
>>>>>> if (HS_G5)
>>>>>> program(tbls_hs_g5)
>>>>>> else
>>>>>> program(tbls_hs_g4);
>>>>>>
>>>>>
>>>>> This should work. Even if we have to accomodate G6 in the future, we can use
>>>>> "else if" for that and keep G4 as the "else" condition. This logic can also be
>>>>> optimized in the future.
>>>>
>>>> That would make dual init meaningless for old targets. Say on SM8450, the
>>>> initial PHY gear is G2, with the "else" condition, during the first init, G4
>>>> table would be programmed, then gear negotiation happens btw host and device
>>>> and the negotiated gear is G3 (assume a UFS2.x is connected). During the 2nd
>>>> init, the "else" condition would __again__ program the G4 table - it is not
>>>> programming the non-G4 table for power saving. The dual init is supposed to
>>>> find the optimal PHY settings, but the "else" condition is programming G4
>>>> table unconditinally.
>>>>
>>>> With the original code change in this patch, the dual init works as it is
>>>> for old targets. say SM8450, the initial PHY gear is G2, during the 2nd
>>>> init, it is programming the non-G4 table (assume a UFS2.x is connected), but
>>>> not the G4 table.
>>>>
>>>
>>> You are right. I completely overlooked the compatibility for old targets. But
>>> still we can move the common table to the "else" condition. This makes it clear
>>> that one of the 3 will be programmed at a time. But with the current logic, I
>>> get the impression that common table is overridden by G4/G5 tables.
>>>
>>> So this is what I'm suggesting:
>>>
>>> if (HS_G5)
>>> program(tbls_hs_g5)
>>> else if (HS_G4)
>>> program(tbls_hs_g4);
>>> else
>>> program(tbls_hs_common);
>>>
>>
>> Common table is needed regardlessly, we cannot put it in "else",
>> otherwise it would break all targets -
>>
>> On old targets (no G5 supported):
>> Common table - supports non-G4 (G3 and lower)
>> Common table + G4 table - supports G4
>>
>> On new targets (G5 supported):
>> Common table - supports nothing, as it is just common parts of G4
>> table and G5 table.
>> Common table + G4 table - support non-G5 (G4 and lower)
>> Common table + G5 table - support G5
>
> There is one issue with this approach, which you might be able to fix.
> For the older PHYs we have two cases: pre-G4 and G4. The host driver
> can set any mode of its choice.
> For the newer targets we only support G4 and G5 modes, don't we?
> However the knowledge that there will be no modes lower than G4 is
> hidden inside the host driver.
> Could you please add a flag / condition to the PHY driver to error out
> if the host tries to set e.g. G2 for the newer PHYs?
>
I will propose a fix for this once for all in next version.
Thanks,
Can Guo.
^ permalink raw reply [flat|nested] 86+ messages in thread
* Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
@ 2023-11-15 7:51 ` Can Guo
0 siblings, 0 replies; 86+ messages in thread
From: Can Guo @ 2023-11-15 7:51 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Manivannan Sadhasivam, Can Guo, bvanassche, stanley.chu,
adrian.hunter, beanhuo, avri.altman, junwoo80.lee,
martin.petersen, linux-scsi, Andy Gross, Bjorn Andersson,
Konrad Dybcio, Vinod Koul, Kishon Vijay Abraham I,
open list:ARM/QUALCOMM SUPPORT, open list:GENERIC PHY FRAMEWORK,
open list
On 11/14/2023 5:15 PM, Dmitry Baryshkov wrote:
> On Sun, 12 Nov 2023 at 07:13, Can Guo <quic_cang@quicinc.com> wrote:
>>
>> Hi Mani,
>>
>> On 11/11/2023 12:12 PM, Manivannan Sadhasivam wrote:
>>> On Fri, Nov 10, 2023 at 10:40:53PM +0800, Can Guo wrote:
>>>>
>>>>
>>>> On 11/10/2023 9:18 PM, Manivannan Sadhasivam wrote:
>>>>> On Fri, Nov 10, 2023 at 12:11:46AM +0200, Dmitry Baryshkov wrote:
>>>>>> On Thu, 9 Nov 2023 at 18:04, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>>>>>
>>>>>>> On Thu, Nov 09, 2023 at 01:00:51PM +0200, Dmitry Baryshkov wrote:
>>>>>>>> On Thu, 9 Nov 2023 at 12:43, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>>>>>>>
>>>>>>>>> On Thu, Nov 09, 2023 at 11:40:51AM +0200, Dmitry Baryshkov wrote:
>>>>>>>>>> On Thu, 9 Nov 2023 at 05:24, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>>>>>>>>>
>>>>>>>>>>> On Wed, Nov 08, 2023 at 08:56:16AM +0200, Dmitry Baryshkov wrote:
>>>>>>>>>>>> On Wed, 8 Nov 2023 at 07:49, Manivannan Sadhasivam <mani@kernel.org> wrote:
>>>>>>>>>>>>>
>>>>>>>>>>>>> On Tue, Nov 07, 2023 at 03:18:09PM +0200, Dmitry Baryshkov wrote:
>>>>>>>>>>>>>> On Tue, 7 Nov 2023 at 06:47, Can Guo <cang@qti.qualcomm.com> wrote:
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> From: Can Guo <quic_cang@quicinc.com>
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> On SM8550, two sets of UFS PHY settings are provided, one set is to support
>>>>>>>>>>>>>>> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
>>>>>>>>>>>>>>> settings are programming different values to different registers, mixing
>>>>>>>>>>>>>>> the two sets and/or overwriting one set with another set is definitely not
>>>>>>>>>>>>>>> blessed by UFS PHY designers. In order to add HS-G5 support for SM8550, we
>>>>>>>>>>>>>>> need to split the two sets into their dedicated tables, and leave only the
>>>>>>>>>>>>>>> common settings in the .tlbs. To have the PHY programmed with the correct
>>>>>>>>>>>>>>> set of PHY settings, the submode passed to PHY driver must be either HS-G4
>>>>>>>>>>>>>>> or HS-G5.
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>> You should also mention that this issue is also present in G4 supported targets.
>>>>>>>>>>>>> And a note that it will get fixed later.
>>>>>>>>>>>>>
>>>>>>>>>>>>>>> Signed-off-by: Can Guo <quic_cang@quicinc.com>
>>>>>>>>>>>>>>> ---
>>>>>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
>>>>>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
>>>>>>>>>>>>>>> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 +++
>>>>>>>>>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 112 ++++++++++++++++++---
>>>>>>>>>>>>>>> 4 files changed, 115 insertions(+), 13 deletions(-)
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>>>>>>>>>>>>>> index c23d5e4..e563af5 100644
>>>>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>>>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
>>>>>>>>>>>>>>> @@ -18,6 +18,7 @@
>>>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
>>>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
>>>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
>>>>>>>>>>>>>>> +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
>>>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
>>>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
>>>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
>>>>>>>>>>>>>>> @@ -27,5 +28,6 @@
>>>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
>>>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
>>>>>>>>>>>>>>> #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
>>>>>>>>>>>>>>> +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> #endif
>>>>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>>>>>>>>>>>>> index f420f8f..ef392ce 100644
>>>>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
>>>>>>>>>>>>>>> @@ -56,6 +56,8 @@
>>>>>>>>>>>>>>> #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
>>>>>>>>>>>>>>> #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
>>>>>>>>>>>>>>> #define QSERDES_V6_COM_PLL_IVCO 0xf4
>>>>>>>>>>>>>>> +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
>>>>>>>>>>>>>>> +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
>>>>>>>>>>>>>>> #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
>>>>>>>>>>>>>>> #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
>>>>>>>>>>>>>>> #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
>>>>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>>>>>>>>>>>>>> index 15bcb4b..48f31c8 100644
>>>>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>>>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>>>>>>>>>>>>>>> @@ -10,10 +10,20 @@
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
>>>>>>>>>>>>>>> @@ -25,6 +35,8 @@
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
>>>>>>>>>>>>>>> #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
>>>>>>>>>>>>>>> +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> #endif
>>>>>>>>>>>>>>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>>>>>>>>>>>> index 3927eba..e0a01497 100644
>>>>>>>>>>>>>>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>>>>>>>>>>>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>>>>>>>>>>>>>>> @@ -649,32 +649,51 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
>>>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
>>>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
>>>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
>>>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
>>>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
>>>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
>>>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
>>>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>>>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>>>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
>>>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
>>>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
>>>>>>>>>>>>>>> +};
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
>>>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
>>>>>>>>>>>>>>> +};
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
>>>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
>>>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
>>>>>>>>>>>>>>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
>>>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>>>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>>>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
>>>>>>>>>>>>>>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Aside from moving these registers to the HS_G4 table, you are also
>>>>>>>>>>>>>> changing these registers. It makes me think that there was an error in
>>>>>>>>>>>>>> the original programming sequence.
>>>>>>>>>>>>>> If that is correct, could you please split the patch into two pieces:
>>>>>>>>>>>>>> - Fix programming sequence (add proper Fixes tags)
>>>>>>>>>>>>>> - Split G4 and G5 tables.
>>>>>>>>>>>>>
>>>>>>>>>>>>> Ack
>>>>>>>>>>>>>
>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> +
>>>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
>>>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
>>>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
>>>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
>>>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
>>>>>>>>>>>>>>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> I see all the MODE1 registers being only present in G4 and G5 tables.
>>>>>>>>>>>>>> Should they be programmed for the modes lower than G4?
>>>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>> We use G4 table for all the modes <= G4.
>>>>>>>>>>>>
>>>>>>>>>>>> Could you please point me how it's handled?
>>>>>>>>>>>> In the patch I see just:
>>>>>>>>>>>>
>>>>>>>>>>>> if (qmp->submode == UFS_HS_G4)
>>>>>>>>>>>> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g4);
>>>>>>>>>>>> else if (qmp->submode == UFS_HS_G5)
>>>>>>>>>>>> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_g5);
>>>>>>>>>>>>
>>>>>>>>>>>> Which looks like two special cases (HS_G4 and HS_G5) and nothing for
>>>>>>>>>>>> anything else.
>>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> Yes, and the UFS driver passes only G4/G5. For all the gears <=G4, G4 init
>>>>>>>>>>> sequence will be used and for G5, G5 sequence will be used.
>>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> That's what I could not find in the UFS driver. I see a call to
>>>>>>>>>> `phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);` and
>>>>>>>>>> host->phy_gear is initialised to UFS_HS_G2.
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> You need to check the UFS driver changes in this series to get the complete
>>>>>>>>> picture as the logic is getting changed.
>>>>>>>>>
>>>>>>>>> It is common to get confused because of the way the UFS driver (qcom mostly)
>>>>>>>>> handles the PHY init sequence programming. We used to have only one init
>>>>>>>>> sequence for older targets and life was easy. But when I wanted to add G4
>>>>>>>>> support for SM8250, I learned that there are 2 separate init sequences. One for
>>>>>>>>> non-G4 and other for G4. So I used the phy_sub_mode property to pass the
>>>>>>>>> relevant mode from the UFS driver to the PHY driver and programmed the sequence
>>>>>>>>> accordingly. This got extended to non-G5 and G5 now.
>>>>>>>>>
>>>>>>>>> Now, the UFS driver will start probing from a low gear for older targets (G2)
>>>>>>>>> and G4/G5 for newer ones then scale up based on the device and host capability.
>>>>>>>>> For older targets, the common table (tbls) will be used if the submode doesn't
>>>>>>>>> match G4/G5. But for newer targets, the UFS driver will _only_ pass G4 or G5 as
>>>>>>>>> the phy_gear, so those specific sequence will only be used.
>>>>>>>>>
>>>>>>>>> Hope I'm clear.
>>>>>>>>
>>>>>>>> Yes, it is now clear, thank you!
>>>>>>>>
>>>>>>>> Would it be possible / feasible / logical to maintain this idea even
>>>>>>>> for newer platforms (leaving the HS_A / HS_B aside)?
>>>>>>>>
>>>>>>>> tbls - works for HS_G2
>>>>>>>> tbls + tbls_g4 - works for HS_G4
>>>>>>>> tbls + tbls_g5 - works for HS_G5
>>>>>>>>
>>>>>>>
>>>>>>> No. The PHY team only gives 2 init sequences for any SoC now.
>>>>>>
>>>>>> Ack. Then the code should become
>>>>>> if (HS_G5)
>>>>>> program(tbls_hs_g5)
>>>>>> else
>>>>>> program(tbls_hs_g4);
>>>>>>
>>>>>
>>>>> This should work. Even if we have to accomodate G6 in the future, we can use
>>>>> "else if" for that and keep G4 as the "else" condition. This logic can also be
>>>>> optimized in the future.
>>>>
>>>> That would make dual init meaningless for old targets. Say on SM8450, the
>>>> initial PHY gear is G2, with the "else" condition, during the first init, G4
>>>> table would be programmed, then gear negotiation happens btw host and device
>>>> and the negotiated gear is G3 (assume a UFS2.x is connected). During the 2nd
>>>> init, the "else" condition would __again__ program the G4 table - it is not
>>>> programming the non-G4 table for power saving. The dual init is supposed to
>>>> find the optimal PHY settings, but the "else" condition is programming G4
>>>> table unconditinally.
>>>>
>>>> With the original code change in this patch, the dual init works as it is
>>>> for old targets. say SM8450, the initial PHY gear is G2, during the 2nd
>>>> init, it is programming the non-G4 table (assume a UFS2.x is connected), but
>>>> not the G4 table.
>>>>
>>>
>>> You are right. I completely overlooked the compatibility for old targets. But
>>> still we can move the common table to the "else" condition. This makes it clear
>>> that one of the 3 will be programmed at a time. But with the current logic, I
>>> get the impression that common table is overridden by G4/G5 tables.
>>>
>>> So this is what I'm suggesting:
>>>
>>> if (HS_G5)
>>> program(tbls_hs_g5)
>>> else if (HS_G4)
>>> program(tbls_hs_g4);
>>> else
>>> program(tbls_hs_common);
>>>
>>
>> Common table is needed regardlessly, we cannot put it in "else",
>> otherwise it would break all targets -
>>
>> On old targets (no G5 supported):
>> Common table - supports non-G4 (G3 and lower)
>> Common table + G4 table - supports G4
>>
>> On new targets (G5 supported):
>> Common table - supports nothing, as it is just common parts of G4
>> table and G5 table.
>> Common table + G4 table - support non-G5 (G4 and lower)
>> Common table + G5 table - support G5
>
> There is one issue with this approach, which you might be able to fix.
> For the older PHYs we have two cases: pre-G4 and G4. The host driver
> can set any mode of its choice.
> For the newer targets we only support G4 and G5 modes, don't we?
> However the knowledge that there will be no modes lower than G4 is
> hidden inside the host driver.
> Could you please add a flag / condition to the PHY driver to error out
> if the host tries to set e.g. G2 for the newer PHYs?
>
I will propose a fix for this once for all in next version.
Thanks,
Can Guo.
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^ permalink raw reply [flat|nested] 86+ messages in thread
end of thread, other threads:[~2023-11-15 7:52 UTC | newest]
Thread overview: 86+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-11-07 4:46 [PATCH v2 0/7] Enable HS-G5 support on SM8550 Can Guo
2023-11-07 4:46 ` Can Guo
2023-11-07 4:46 ` [PATCH v2 1/7] scsi: ufs: host: Rename structure ufs_dev_params to ufs_host_params Can Guo
2023-11-07 4:46 ` Can Guo
2023-11-07 19:36 ` Andrew Halaney
2023-11-07 19:36 ` Andrew Halaney
2023-11-08 7:44 ` Can Guo
2023-11-08 7:44 ` Can Guo
2023-11-07 20:56 ` Bart Van Assche
2023-11-07 20:56 ` Bart Van Assche
2023-11-08 7:48 ` Can Guo
2023-11-08 7:48 ` Can Guo
2023-11-07 4:46 ` [PATCH v2 2/7] scsi: ufs: ufs-qcom: Setup host power mode during init Can Guo
2023-11-07 20:14 ` Andrew Halaney
2023-11-08 7:47 ` Can Guo
2023-11-08 5:07 ` Manivannan Sadhasivam
2023-11-08 8:07 ` Can Guo
2023-11-07 4:46 ` [PATCH v2 3/7] scsi: ufs: ufs-qcom: Allow the first init start with the maximum supported gear Can Guo
2023-11-08 5:23 ` Manivannan Sadhasivam
2023-11-08 8:21 ` Can Guo
2023-11-08 8:23 ` Can Guo
2023-11-09 3:47 ` Manivannan Sadhasivam
2023-11-09 4:07 ` Can Guo
2023-11-09 7:47 ` Manivannan Sadhasivam
2023-11-07 4:46 ` [PATCH v2 4/7] scsi: ufs: ufs-qcom: Limit HS-G5 Rate-A to hosts with HW version 5 Can Guo
2023-11-08 5:25 ` Manivannan Sadhasivam
2023-11-08 8:42 ` Can Guo
2023-11-09 3:27 ` Manivannan Sadhasivam
2023-11-07 4:46 ` [PATCH v2 5/7] scsi: ufs: ufs-qcom: Set initial PHY gear to max HS gear for HW ver 5 and newer Can Guo
2023-11-08 5:34 ` Manivannan Sadhasivam
2023-11-08 8:46 ` Can Guo
2023-11-07 4:46 ` [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550 Can Guo
2023-11-07 4:46 ` Can Guo
2023-11-07 13:18 ` Dmitry Baryshkov
2023-11-07 13:18 ` Dmitry Baryshkov
2023-11-08 5:49 ` Manivannan Sadhasivam
2023-11-08 5:49 ` Manivannan Sadhasivam
2023-11-08 6:56 ` Dmitry Baryshkov
2023-11-08 6:56 ` Dmitry Baryshkov
2023-11-09 3:24 ` Manivannan Sadhasivam
2023-11-09 3:24 ` Manivannan Sadhasivam
2023-11-09 9:40 ` Dmitry Baryshkov
2023-11-09 9:40 ` Dmitry Baryshkov
2023-11-09 10:42 ` Manivannan Sadhasivam
2023-11-09 10:42 ` Manivannan Sadhasivam
2023-11-09 11:00 ` Dmitry Baryshkov
2023-11-09 11:00 ` Dmitry Baryshkov
2023-11-09 16:04 ` Manivannan Sadhasivam
2023-11-09 16:04 ` Manivannan Sadhasivam
2023-11-09 22:11 ` Dmitry Baryshkov
2023-11-09 22:11 ` Dmitry Baryshkov
2023-11-10 13:18 ` Manivannan Sadhasivam
2023-11-10 13:18 ` Manivannan Sadhasivam
2023-11-10 14:40 ` Can Guo
2023-11-10 14:40 ` Can Guo
2023-11-11 4:12 ` Manivannan Sadhasivam
2023-11-11 4:12 ` Manivannan Sadhasivam
2023-11-12 5:13 ` Can Guo
2023-11-12 5:13 ` Can Guo
2023-11-14 6:12 ` Manivannan Sadhasivam
2023-11-14 6:12 ` Manivannan Sadhasivam
2023-11-14 9:15 ` Dmitry Baryshkov
2023-11-14 9:15 ` Dmitry Baryshkov
2023-11-15 7:51 ` Can Guo
2023-11-15 7:51 ` Can Guo
2023-11-08 9:19 ` Can Guo
2023-11-08 9:19 ` Can Guo
2023-11-09 3:26 ` Manivannan Sadhasivam
2023-11-09 3:26 ` Manivannan Sadhasivam
2023-11-08 9:02 ` Can Guo
2023-11-08 9:02 ` Can Guo
2023-11-10 8:47 ` neil.armstrong
2023-11-10 8:47 ` neil.armstrong
2023-11-10 9:03 ` Can Guo
2023-11-10 9:03 ` Can Guo
2023-11-10 9:17 ` neil.armstrong
2023-11-10 9:17 ` neil.armstrong
2023-11-10 9:32 ` Can Guo
2023-11-10 9:32 ` Can Guo
2023-11-10 9:35 ` neil.armstrong
2023-11-10 9:35 ` neil.armstrong
2023-11-07 4:46 ` [PATCH v2 7/7] scsi: ufs: ufs-qcom: Add support for UFS device version detection Can Guo
2023-11-08 5:11 ` [PATCH v2 0/7] Enable HS-G5 support on SM8550 Manivannan Sadhasivam
2023-11-08 5:11 ` Manivannan Sadhasivam
2023-11-08 8:09 ` Can Guo
2023-11-08 8:09 ` Can Guo
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