From: Nick Kossifidis <mick@ics.forth.gr>
To: Nick Kossifidis <mick@ics.forth.gr>
Cc: "Anup Patel" <anup@brainfault.org>, "Guo Ren" <guoren@kernel.org>,
"Anup Patel" <anup.patel@wdc.com>,
"Atish Patra" <atish.patra@wdc.com>,
"Palmer Dabbelt" <palmerdabbelt@google.com>,
"Christoph Müllner" <christoph.muellner@vrull.eu>,
"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
"Christoph Hellwig" <hch@lst.de>, liush <liush@allwinnertech.com>,
wefu@redhat.com, "Wei Wu (吴伟)" <lazyparser@gmail.com>,
"Drew Fustini" <drew@beagleboard.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>,
taiten.peng@canonical.com, aniket.ponkshe@canonical.com,
"Heinrich Schuchardt" <heinrich.schuchardt@canonical.com>,
gordan.markus@canonical.com, "Guo Ren" <guoren@linux.alibaba.com>,
"Arnd Bergmann" <arnd@arndb.de>, "Chen-Yu Tsai" <wens@csie.org>,
"Maxime Ripard" <maxime@cerno.tech>,
"Daniel Lustig" <dlustig@nvidia.com>,
"Greg Favor" <gfavor@ventanamicro.com>,
"Andrea Mondelli" <andrea.mondelli@huawei.com>,
"Jonathan Behrens" <behrensj@mit.edu>,
Xinhaoqu <xinhaoqu@huawei.com>,
"Bill Huffman" <huffman@cadence.com>,
"Allen Baum" <allen.baum@esperantotech.com>,
"Josh Scheid" <jscheid@ventanamicro.com>,
"Richard Trauben" <rtrauben@gmail.com>
Subject: Re: [PATCH] riscv: Add RISC-V svpbmt extension
Date: Thu, 23 Sep 2021 12:48:13 +0300 [thread overview]
Message-ID: <16de95480d279b086cf0c612461e4235@mailhost.ics.forth.gr> (raw)
In-Reply-To: <0861cc74d3886e685e9aa5d13ddcd781@mailhost.ics.forth.gr>
Στις 2021-09-23 12:42, Nick Kossifidis έγραψε:
> Στις 2021-09-23 12:37, Anup Patel έγραψε:
>> On Thu, Sep 23, 2021 at 2:55 PM Nick Kossifidis <mick@ics.forth.gr>
>> wrote:
>>>
>>> Hello Guo,
>>>
>>> Στις 2021-09-23 10:27, guoren@kernel.org έγραψε:
>>> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml
>>> b/Documentation/devicetree/bindings/riscv/cpus.yaml
>>> index e534f6a7cfa1..1825cd8db0de 100644
>>> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
>>> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
>>> @@ -56,7 +56,9 @@ properties:
>>> enum:
>>> - riscv,sv32
>>> - riscv,sv39
>>> + - riscv,sv39,svpbmt
>>> - riscv,sv48
>>> + - riscv,sv48,svpbmt
>>> - riscv,none
>>>
>>> Isn't svpbmt orthogonal to the mmu type ? It's a functionality that
>>> can
>>> be present on either sv39/48/57 so why not have another "svpbmt"
>>> property directly on the cpu node ?
>>
>> Actually, "mmu-type" would be a good place because it's page based
>> memory attribute and paging can't exist without mmu translation mode.
>>
>> Also, "svpmbt" is indeed a CPU property so has to be feature
>> individual
>> CPU node. Hypothetically, a heterogeneous system is possible where
>> some CPUs have "svpmbt" and some CPUs don't have "svpmbt". For
>> example, a future FUxxx SoC might have a E-core and few S-cores
>> where S-cores have Svpmbt whereas E-core does not have Svpmbt
>> because it's an embedded core.
>>
>
> I should say cpuX node, not the root /cpu node. We can have an svpbmt
> property in the same way we have an mmu-type property.
>
I'm also thinking of future mmu-related extensions, e.g. what about
svnapot ? Should we have mmu-type be riscv,sv39,svnapot and e.g.
riscv.sv39,svpbmt,svnapot ? It'll become messy.
Regards,
Nick
WARNING: multiple messages have this Message-ID (diff)
From: Nick Kossifidis <mick@ics.forth.gr>
To: Nick Kossifidis <mick@ics.forth.gr>
Cc: "Anup Patel" <anup@brainfault.org>, "Guo Ren" <guoren@kernel.org>,
"Anup Patel" <anup.patel@wdc.com>,
"Atish Patra" <atish.patra@wdc.com>,
"Palmer Dabbelt" <palmerdabbelt@google.com>,
"Christoph Müllner" <christoph.muellner@vrull.eu>,
"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
"Christoph Hellwig" <hch@lst.de>, liush <liush@allwinnertech.com>,
wefu@redhat.com, "Wei Wu (吴伟)" <lazyparser@gmail.com>,
"Drew Fustini" <drew@beagleboard.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>,
taiten.peng@canonical.com, aniket.ponkshe@canonical.com,
"Heinrich Schuchardt" <heinrich.schuchardt@canonical.com>,
gordan.markus@canonical.com, "Guo Ren" <guoren@linux.alibaba.com>,
"Arnd Bergmann" <arnd@arndb.de>, "Chen-Yu Tsai" <wens@csie.org>,
"Maxime Ripard" <maxime@cerno.tech>,
"Daniel Lustig" <dlustig@nvidia.com>,
"Greg Favor" <gfavor@ventanamicro.com>,
"Andrea Mondelli" <andrea.mondelli@huawei.com>,
"Jonathan Behrens" <behrensj@mit.edu>,
Xinhaoqu <xinhaoqu@huawei.com>,
"Bill Huffman" <huffman@cadence.com>,
"Allen Baum" <allen.baum@esperantotech.com>,
"Josh Scheid" <jscheid@ventanamicro.com>,
"Richard Trauben" <rtrauben@gmail.com>
Subject: Re: [PATCH] riscv: Add RISC-V svpbmt extension
Date: Thu, 23 Sep 2021 12:48:13 +0300 [thread overview]
Message-ID: <16de95480d279b086cf0c612461e4235@mailhost.ics.forth.gr> (raw)
In-Reply-To: <0861cc74d3886e685e9aa5d13ddcd781@mailhost.ics.forth.gr>
Στις 2021-09-23 12:42, Nick Kossifidis έγραψε:
> Στις 2021-09-23 12:37, Anup Patel έγραψε:
>> On Thu, Sep 23, 2021 at 2:55 PM Nick Kossifidis <mick@ics.forth.gr>
>> wrote:
>>>
>>> Hello Guo,
>>>
>>> Στις 2021-09-23 10:27, guoren@kernel.org έγραψε:
>>> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml
>>> b/Documentation/devicetree/bindings/riscv/cpus.yaml
>>> index e534f6a7cfa1..1825cd8db0de 100644
>>> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
>>> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
>>> @@ -56,7 +56,9 @@ properties:
>>> enum:
>>> - riscv,sv32
>>> - riscv,sv39
>>> + - riscv,sv39,svpbmt
>>> - riscv,sv48
>>> + - riscv,sv48,svpbmt
>>> - riscv,none
>>>
>>> Isn't svpbmt orthogonal to the mmu type ? It's a functionality that
>>> can
>>> be present on either sv39/48/57 so why not have another "svpbmt"
>>> property directly on the cpu node ?
>>
>> Actually, "mmu-type" would be a good place because it's page based
>> memory attribute and paging can't exist without mmu translation mode.
>>
>> Also, "svpmbt" is indeed a CPU property so has to be feature
>> individual
>> CPU node. Hypothetically, a heterogeneous system is possible where
>> some CPUs have "svpmbt" and some CPUs don't have "svpmbt". For
>> example, a future FUxxx SoC might have a E-core and few S-cores
>> where S-cores have Svpmbt whereas E-core does not have Svpmbt
>> because it's an embedded core.
>>
>
> I should say cpuX node, not the root /cpu node. We can have an svpbmt
> property in the same way we have an mmu-type property.
>
I'm also thinking of future mmu-related extensions, e.g. what about
svnapot ? Should we have mmu-type be riscv,sv39,svnapot and e.g.
riscv.sv39,svpbmt,svnapot ? It'll become messy.
Regards,
Nick
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-09-23 9:48 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-23 7:27 [PATCH] riscv: Add RISC-V svpbmt extension guoren
2021-09-23 7:27 ` guoren
2021-09-23 9:13 ` Anup Patel
2021-09-23 9:13 ` Anup Patel
2021-09-23 11:53 ` Guo Ren
2021-09-23 11:53 ` Guo Ren
2021-09-23 9:24 ` Nick Kossifidis
2021-09-23 9:24 ` Nick Kossifidis
2021-09-23 9:37 ` Anup Patel
2021-09-23 9:37 ` Anup Patel
2021-09-23 9:42 ` Nick Kossifidis
2021-09-23 9:42 ` Nick Kossifidis
2021-09-23 9:48 ` Nick Kossifidis [this message]
2021-09-23 9:48 ` Nick Kossifidis
2021-09-23 9:57 ` Anup Patel
2021-09-23 9:57 ` Anup Patel
2021-09-23 10:07 ` Philipp Tomsich
2021-09-23 10:07 ` Philipp Tomsich
2021-09-23 10:36 ` Anup Patel
2021-09-23 10:36 ` Anup Patel
[not found] ` <CAAeLtUDu0yaDBcuC06nX1WUQC9k4eNuWjvAFrpkP_h0nf5BZAw@mail.gmail.com>
2021-09-23 10:09 ` Nick Kossifidis
2021-09-23 10:09 ` Nick Kossifidis
2021-09-23 11:50 ` Alexandre Ghiti
2021-09-23 11:50 ` Alexandre Ghiti
2021-09-23 12:05 ` Anup Patel
2021-09-23 12:05 ` Anup Patel
2021-09-23 12:05 ` Guo Ren
2021-09-23 12:05 ` Guo Ren
2021-09-23 12:04 ` Guo Ren
2021-09-23 12:04 ` Guo Ren
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