* [Intel-gfx] [PATCH] drm/i915/cdclk: Remove divider field from tables
@ 2023-11-24 20:55 Gustavo Sousa
2023-11-24 21:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 14+ messages in thread
From: Gustavo Sousa @ 2023-11-24 20:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Matt Roper
The cdclk tables were introduced with commit 736da8112fee ("drm/i915:
Use literal representation of cdclk tables"). It has been almost 4 years
and the divider field was not really used yet. Let's remove it.
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 269 ++++++++++-----------
1 file changed, 134 insertions(+), 135 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index b93d1ad7936d..7f85a216ff5c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1227,183 +1227,182 @@ struct intel_cdclk_vals {
u32 cdclk;
u16 refclk;
u16 waveform;
- u8 divider; /* CD2X divider * 2 */
u8 ratio;
};
static const struct intel_cdclk_vals bxt_cdclk_table[] = {
- { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
- { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
- { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
- { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
- { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
+ { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
+ { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
+ { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
+ { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
+ { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
{}
};
static const struct intel_cdclk_vals glk_cdclk_table[] = {
- { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
- { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
- { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
+ { .refclk = 19200, .cdclk = 79200, .ratio = 33 },
+ { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
+ { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
{}
};
static const struct intel_cdclk_vals icl_cdclk_table[] = {
- { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
- { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
- { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
- { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
- { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
- { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
-
- { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
- { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
- { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
- { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
- { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
- { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
-
- { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
- { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
- { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
- { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
- { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
- { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
+ { .refclk = 19200, .cdclk = 172800, .ratio = 18 },
+ { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
+ { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
+ { .refclk = 19200, .cdclk = 326400, .ratio = 68 },
+ { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
+ { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
+
+ { .refclk = 24000, .cdclk = 180000, .ratio = 15 },
+ { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
+ { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
+ { .refclk = 24000, .cdclk = 324000, .ratio = 54 },
+ { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
+ { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
+
+ { .refclk = 38400, .cdclk = 172800, .ratio = 9 },
+ { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
+ { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
+ { .refclk = 38400, .cdclk = 326400, .ratio = 34 },
+ { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
+ { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
{}
};
static const struct intel_cdclk_vals rkl_cdclk_table[] = {
- { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 },
- { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 },
- { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 },
- { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
- { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
- { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },
-
- { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 },
- { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 },
- { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 },
- { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
- { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 },
- { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },
-
- { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
- { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
- { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
- { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
- { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
- { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
+ { .refclk = 19200, .cdclk = 172800, .ratio = 36 },
+ { .refclk = 19200, .cdclk = 192000, .ratio = 40 },
+ { .refclk = 19200, .cdclk = 307200, .ratio = 64 },
+ { .refclk = 19200, .cdclk = 326400, .ratio = 136 },
+ { .refclk = 19200, .cdclk = 556800, .ratio = 116 },
+ { .refclk = 19200, .cdclk = 652800, .ratio = 136 },
+
+ { .refclk = 24000, .cdclk = 180000, .ratio = 30 },
+ { .refclk = 24000, .cdclk = 192000, .ratio = 32 },
+ { .refclk = 24000, .cdclk = 312000, .ratio = 52 },
+ { .refclk = 24000, .cdclk = 324000, .ratio = 108 },
+ { .refclk = 24000, .cdclk = 552000, .ratio = 92 },
+ { .refclk = 24000, .cdclk = 648000, .ratio = 108 },
+
+ { .refclk = 38400, .cdclk = 172800, .ratio = 18 },
+ { .refclk = 38400, .cdclk = 192000, .ratio = 20 },
+ { .refclk = 38400, .cdclk = 307200, .ratio = 32 },
+ { .refclk = 38400, .cdclk = 326400, .ratio = 68 },
+ { .refclk = 38400, .cdclk = 556800, .ratio = 58 },
+ { .refclk = 38400, .cdclk = 652800, .ratio = 68 },
{}
};
static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
- { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
- { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
- { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
+ { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
+ { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
+ { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
- { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
- { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
- { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
+ { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
+ { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
+ { .refclk = 24400, .cdclk = 648000, .ratio = 54 },
- { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
- { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
- { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
+ { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
+ { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
+ { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
{}
};
static const struct intel_cdclk_vals adlp_cdclk_table[] = {
- { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
- { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
- { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
- { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
- { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
-
- { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
- { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
- { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
- { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
- { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
-
- { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
- { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
- { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
- { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
- { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
+ { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
+ { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
+ { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
+ { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
+ { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
+
+ { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
+ { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
+ { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
+ { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
+ { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
+
+ { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
+ { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
+ { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
+ { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
+ { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
{}
};
static const struct intel_cdclk_vals rplu_cdclk_table[] = {
- { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
- { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
- { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
- { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
- { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
- { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
-
- { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
- { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
- { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
- { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
- { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
- { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
-
- { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
- { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
- { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
- { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
- { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
- { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
+ { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
+ { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
+ { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
+ { .refclk = 19200, .cdclk = 480000, .ratio = 50 },
+ { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
+ { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
+
+ { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
+ { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
+ { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
+ { .refclk = 24000, .cdclk = 480000, .ratio = 40 },
+ { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
+ { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
+
+ { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
+ { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
+ { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
+ { .refclk = 38400, .cdclk = 480000, .ratio = 25 },
+ { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
+ { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
{}
};
static const struct intel_cdclk_vals dg2_cdclk_table[] = {
- { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
- { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
- { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 },
- { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a },
- { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa },
- { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a },
- { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 },
- { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 },
- { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee },
- { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de },
- { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
- { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
- { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
+ { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
+ { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
+ { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
+ { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
+ { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
+ { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
+ { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
+ { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
+ { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
+ { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
{}
};
static const struct intel_cdclk_vals mtl_cdclk_table[] = {
- { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
- { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
- { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
- { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
- { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
- { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
+ { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
{}
};
static const struct intel_cdclk_vals lnl_cdclk_table[] = {
- { .refclk = 38400, .cdclk = 153600, .divider = 2, .ratio = 16, .waveform = 0xaaaa },
- { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
- { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
- { .refclk = 38400, .cdclk = 211200, .divider = 2, .ratio = 16, .waveform = 0xdbb6 },
- { .refclk = 38400, .cdclk = 230400, .divider = 2, .ratio = 16, .waveform = 0xeeee },
- { .refclk = 38400, .cdclk = 249600, .divider = 2, .ratio = 16, .waveform = 0xf7de },
- { .refclk = 38400, .cdclk = 268800, .divider = 2, .ratio = 16, .waveform = 0xfefe },
- { .refclk = 38400, .cdclk = 288000, .divider = 2, .ratio = 16, .waveform = 0xfffe },
- { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0xffff },
- { .refclk = 38400, .cdclk = 330000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 },
- { .refclk = 38400, .cdclk = 360000, .divider = 2, .ratio = 25, .waveform = 0xeeee },
- { .refclk = 38400, .cdclk = 390000, .divider = 2, .ratio = 25, .waveform = 0xf7de },
- { .refclk = 38400, .cdclk = 420000, .divider = 2, .ratio = 25, .waveform = 0xfefe },
- { .refclk = 38400, .cdclk = 450000, .divider = 2, .ratio = 25, .waveform = 0xfffe },
- { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0xffff },
- { .refclk = 38400, .cdclk = 487200, .divider = 2, .ratio = 29, .waveform = 0xfefe },
- { .refclk = 38400, .cdclk = 522000, .divider = 2, .ratio = 29, .waveform = 0xfffe },
- { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0xffff },
- { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
- { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
- { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
+ { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
+ { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
+ { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
+ { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
+ { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
+ { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
+ { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
+ { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
+ { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
+ { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
+ { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
+ { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
+ { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
+ { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
+ { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
{}
};
--
2.42.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cdclk: Remove divider field from tables
2023-11-24 20:55 [Intel-gfx] [PATCH] drm/i915/cdclk: Remove divider field from tables Gustavo Sousa
@ 2023-11-24 21:57 ` Patchwork
2023-11-26 4:12 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-11-27 16:21 ` [Intel-gfx] [PATCH] " Matt Roper
2 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2023-11-24 21:57 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 15878 bytes --]
== Series Details ==
Series: drm/i915/cdclk: Remove divider field from tables
URL : https://patchwork.freedesktop.org/series/126883/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13921 -> Patchwork_126883v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/index.html
Participating hosts (37 -> 36)
------------------------------
Additional (3): bat-dg2-8 bat-dg2-9 bat-mtlp-8
Missing (4): bat-rpls-1 bat-adlp-11 fi-snb-2520m fi-pnv-d510
Known issues
------------
Here are the changes found in Patchwork_126883v1 that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- fi-bsw-n3050: [FAIL][1] ([i915#8293]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/fi-bsw-n3050/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/fi-bsw-n3050/boot.html
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-mtlp-8: NOTRUN -> [SKIP][3] ([i915#9318])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-mtlp-8/igt@debugfs_test@basic-hwmon.html
* igt@gem_lmem_swapping@random-engines:
- fi-bsw-n3050: NOTRUN -> [SKIP][4] ([fdo#109271]) +14 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/fi-bsw-n3050/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@verify-random:
- bat-mtlp-8: NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-mtlp-8/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap@basic:
- bat-dg2-9: NOTRUN -> [SKIP][6] ([i915#4083])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-9/igt@gem_mmap@basic.html
- bat-mtlp-8: NOTRUN -> [SKIP][7] ([i915#4083])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-mtlp-8/igt@gem_mmap@basic.html
- bat-dg2-8: NOTRUN -> [SKIP][8] ([i915#4083])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-8/igt@gem_mmap@basic.html
* igt@gem_mmap_gtt@basic:
- bat-dg2-9: NOTRUN -> [SKIP][9] ([i915#4077]) +2 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-9/igt@gem_mmap_gtt@basic.html
- bat-mtlp-8: NOTRUN -> [SKIP][10] ([i915#4077]) +2 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-mtlp-8/igt@gem_mmap_gtt@basic.html
- bat-dg2-8: NOTRUN -> [SKIP][11] ([i915#4077]) +2 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-8/igt@gem_mmap_gtt@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-dg2-9: NOTRUN -> [SKIP][12] ([i915#4079]) +1 other test skip
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-9/igt@gem_render_tiled_blits@basic.html
- bat-mtlp-8: NOTRUN -> [SKIP][13] ([i915#4079]) +1 other test skip
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-mtlp-8/igt@gem_render_tiled_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg2-8: NOTRUN -> [SKIP][14] ([i915#4079]) +1 other test skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-8/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rps@basic-api:
- bat-dg2-9: NOTRUN -> [SKIP][15] ([i915#6621])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-9/igt@i915_pm_rps@basic-api.html
- bat-mtlp-8: NOTRUN -> [SKIP][16] ([i915#6621])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-mtlp-8/igt@i915_pm_rps@basic-api.html
- bat-dg2-8: NOTRUN -> [SKIP][17] ([i915#6621])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-8/igt@i915_pm_rps@basic-api.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-mtlp-8: NOTRUN -> [SKIP][18] ([i915#6645])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-mtlp-8/igt@i915_suspend@basic-s3-without-i915.html
- bat-dg2-8: NOTRUN -> [SKIP][19] ([i915#6645])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-8/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-9: NOTRUN -> [SKIP][20] ([i915#5190])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-9/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
- bat-mtlp-8: NOTRUN -> [SKIP][21] ([i915#5190])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-mtlp-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
- bat-dg2-8: NOTRUN -> [SKIP][22] ([i915#5190])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-9: NOTRUN -> [SKIP][23] ([i915#4215] / [i915#5190])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-9/igt@kms_addfb_basic@basic-y-tiled-legacy.html
- bat-mtlp-8: NOTRUN -> [SKIP][24] ([i915#4212]) +8 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-mtlp-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
- bat-dg2-8: NOTRUN -> [SKIP][25] ([i915#4215] / [i915#5190])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-9: NOTRUN -> [SKIP][26] ([i915#4212]) +6 other tests skip
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-9/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
- bat-dg2-8: NOTRUN -> [SKIP][27] ([i915#4212]) +6 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-8/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg2-9: NOTRUN -> [SKIP][28] ([i915#4212] / [i915#5608])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-9/igt@kms_addfb_basic@tile-pitch-mismatch.html
- bat-dg2-8: NOTRUN -> [SKIP][29] ([i915#4212] / [i915#5608])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-8/igt@kms_addfb_basic@tile-pitch-mismatch.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-9: NOTRUN -> [SKIP][30] ([i915#4103] / [i915#4213] / [i915#5608]) +1 other test skip
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-9/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-mtlp-8: NOTRUN -> [SKIP][31] ([i915#4213]) +1 other test skip
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-mtlp-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-dg2-8: NOTRUN -> [SKIP][32] ([i915#4103] / [i915#4213] / [i915#5608]) +1 other test skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-mtlp-8: NOTRUN -> [SKIP][33] ([i915#3555] / [i915#3840] / [i915#4098] / [i915#9159])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-mtlp-8/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-9: NOTRUN -> [SKIP][34] ([fdo#109285])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-9/igt@kms_force_connector_basic@force-load-detect.html
- bat-mtlp-8: NOTRUN -> [SKIP][35] ([fdo#109285])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-mtlp-8/igt@kms_force_connector_basic@force-load-detect.html
- bat-dg2-8: NOTRUN -> [SKIP][36] ([fdo#109285])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-8/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-9: NOTRUN -> [SKIP][37] ([i915#5274])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-9/igt@kms_force_connector_basic@prune-stale-modes.html
- bat-mtlp-8: NOTRUN -> [SKIP][38] ([i915#5274])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-mtlp-8/igt@kms_force_connector_basic@prune-stale-modes.html
- bat-dg2-8: NOTRUN -> [SKIP][39] ([i915#5274])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-8/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [PASS][40] -> [FAIL][41] ([IGT#3])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
- fi-bsw-n3050: NOTRUN -> [FAIL][42] ([IGT#152])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/fi-bsw-n3050/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-dg2-9: NOTRUN -> [SKIP][43] ([i915#3555] / [i915#4098])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-9/igt@kms_setmode@basic-clone-single-crtc.html
- bat-mtlp-8: NOTRUN -> [SKIP][44] ([i915#3555] / [i915#8809])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-mtlp-8/igt@kms_setmode@basic-clone-single-crtc.html
- bat-dg2-8: NOTRUN -> [SKIP][45] ([i915#3555] / [i915#4098])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-8/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-dg2-9: NOTRUN -> [SKIP][46] ([i915#3708])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-9/igt@prime_vgem@basic-fence-flip.html
- bat-dg2-8: NOTRUN -> [SKIP][47] ([i915#3708])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-8/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-dg2-8: NOTRUN -> [SKIP][48] ([i915#3708] / [i915#4077]) +1 other test skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-8/igt@prime_vgem@basic-fence-mmap.html
- bat-dg2-9: NOTRUN -> [SKIP][49] ([i915#3708] / [i915#4077]) +1 other test skip
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-9/igt@prime_vgem@basic-fence-mmap.html
- bat-mtlp-8: NOTRUN -> [SKIP][50] ([i915#3708] / [i915#4077]) +1 other test skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-mtlp-8/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- bat-mtlp-8: NOTRUN -> [SKIP][51] ([i915#3708]) +2 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-mtlp-8/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-write:
- bat-dg2-9: NOTRUN -> [SKIP][52] ([i915#3291] / [i915#3708]) +2 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-9/igt@prime_vgem@basic-write.html
- bat-dg2-8: NOTRUN -> [SKIP][53] ([i915#3291] / [i915#3708]) +2 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-dg2-8/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-7567u: [DMESG-FAIL][54] ([i915#5334] / [i915#7872]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/fi-kbl-7567u/igt@i915_selftest@live@gt_heartbeat.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/fi-kbl-7567u/igt@i915_selftest@live@gt_heartbeat.html
- fi-apl-guc: [DMESG-FAIL][56] ([i915#5334]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
- bat-rplp-1: [ABORT][58] ([i915#8668]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#152]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/152
[IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
[i915#9159]: https://gitlab.freedesktop.org/drm/intel/issues/9159
[i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
[i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
Build changes
-------------
* Linux: CI_DRM_13921 -> Patchwork_126883v1
CI-20190529: 20190529
CI_DRM_13921: 002e96d8067fa253ee53af2fa191717f4f5b782b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7603: 2ddd8cac90d4333943cd017319514949b047821b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_126883v1: 002e96d8067fa253ee53af2fa191717f4f5b782b @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
bffa647638c7 drm/i915/cdclk: Remove divider field from tables
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/index.html
[-- Attachment #2: Type: text/html, Size: 20496 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/cdclk: Remove divider field from tables
2023-11-24 20:55 [Intel-gfx] [PATCH] drm/i915/cdclk: Remove divider field from tables Gustavo Sousa
2023-11-24 21:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
@ 2023-11-26 4:12 ` Patchwork
2023-11-27 16:21 ` [Intel-gfx] [PATCH] " Matt Roper
2 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2023-11-26 4:12 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 64988 bytes --]
== Series Details ==
Series: drm/i915/cdclk: Remove divider field from tables
URL : https://patchwork.freedesktop.org/series/126883/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13921_full -> Patchwork_126883v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_126883v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_126883v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_126883v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_eio@unwedge-stress:
- shard-mtlp: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-mtlp-7/igt@gem_eio@unwedge-stress.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-4/igt@gem_eio@unwedge-stress.html
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-glk: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk7/igt@gem_ppgtt@blt-vs-render-ctx0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk8/igt@gem_ppgtt@blt-vs-render-ctx0.html
* igt@kms_flip@plain-flip-fb-recreate@a-hdmi-a1:
- shard-snb: NOTRUN -> [INCOMPLETE][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-snb1/igt@kms_flip@plain-flip-fb-recreate@a-hdmi-a1.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_psr@psr2_dpms@edp-1}:
- shard-mtlp: NOTRUN -> [FAIL][6]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-6/igt@kms_psr@psr2_dpms@edp-1.html
Known issues
------------
Here are the changes found in Patchwork_126883v1_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-glk: ([FAIL][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31]) ([i915#8293]) -> ([PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk1/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk1/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk1/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk2/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk2/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk2/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk3/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk3/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk3/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk4/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk4/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk4/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk5/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk5/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk5/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk6/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk6/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk6/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk7/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk7/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk7/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk8/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk8/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk9/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk9/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk1/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk1/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk1/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk2/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk2/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk2/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk3/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk3/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk3/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk4/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk4/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk4/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk5/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk5/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk5/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk6/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk6/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk6/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk7/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk8/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk8/boot.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk8/boot.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk9/boot.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk9/boot.html
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-keep-cache:
- shard-mtlp: NOTRUN -> [SKIP][56] ([i915#8411])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-7/igt@api_intel_bb@blit-reloc-keep-cache.html
* igt@api_intel_bb@object-noreloc-keep-cache-simple:
- shard-snb: NOTRUN -> [SKIP][57] ([fdo#109271]) +63 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-snb4/igt@api_intel_bb@object-noreloc-keep-cache-simple.html
* igt@drm_fdinfo@all-busy-idle-check-all:
- shard-mtlp: NOTRUN -> [SKIP][58] ([i915#8414]) +1 other test skip
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-5/igt@drm_fdinfo@all-busy-idle-check-all.html
* igt@drm_fdinfo@most-busy-check-all@bcs0:
- shard-dg2: NOTRUN -> [SKIP][59] ([i915#8414]) +31 other tests skip
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@drm_fdinfo@most-busy-check-all@bcs0.html
* igt@gem_barrier_race@remote-request@rcs0:
- shard-glk: [PASS][60] -> [ABORT][61] ([i915#8190])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk7/igt@gem_barrier_race@remote-request@rcs0.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk3/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_ccs@block-copy-compressed:
- shard-mtlp: NOTRUN -> [SKIP][62] ([i915#3555])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-7/igt@gem_ccs@block-copy-compressed.html
* igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0:
- shard-dg2: [PASS][63] -> [INCOMPLETE][64] ([i915#7297])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-dg2-2/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-2/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html
* igt@gem_close_race@multigpu-basic-process:
- shard-tglu: NOTRUN -> [SKIP][65] ([i915#7697])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-3/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_create@create-ext-cpu-access-sanity-check:
- shard-mtlp: NOTRUN -> [SKIP][66] ([i915#6335])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-7/igt@gem_create@create-ext-cpu-access-sanity-check.html
* igt@gem_create@create-ext-set-pat:
- shard-dg2: NOTRUN -> [SKIP][67] ([i915#8562])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-6/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_persistence@engines-hostile:
- shard-snb: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#1099]) +1 other test skip
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-snb4/igt@gem_ctx_persistence@engines-hostile.html
* igt@gem_ctx_persistence@heartbeat-hang:
- shard-dg2: NOTRUN -> [SKIP][69] ([i915#8555]) +1 other test skip
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@gem_ctx_persistence@heartbeat-hang.html
* igt@gem_ctx_persistence@heartbeat-stop:
- shard-mtlp: NOTRUN -> [SKIP][70] ([i915#8555])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-7/igt@gem_ctx_persistence@heartbeat-stop.html
* igt@gem_eio@context-create:
- shard-mtlp: [PASS][71] -> [ABORT][72] ([i915#9414])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-mtlp-5/igt@gem_eio@context-create.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-4/igt@gem_eio@context-create.html
* igt@gem_eio@hibernate:
- shard-dg2: NOTRUN -> [ABORT][73] ([i915#7975] / [i915#8213])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-10/igt@gem_eio@hibernate.html
* igt@gem_eio@reset-stress:
- shard-dg2: NOTRUN -> [FAIL][74] ([i915#5784])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@bonded-false-hang:
- shard-mtlp: NOTRUN -> [SKIP][75] ([i915#4812]) +1 other test skip
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-7/igt@gem_exec_balancer@bonded-false-hang.html
* igt@gem_exec_balancer@bonded-pair:
- shard-dg2: NOTRUN -> [SKIP][76] ([i915#4771])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@gem_exec_balancer@bonded-pair.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [PASS][77] -> [FAIL][78] ([i915#2842])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk4/igt@gem_exec_fair@basic-none-share@rcs0.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk3/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-tglu: NOTRUN -> [FAIL][79] ([i915#2842]) +1 other test fail
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-7/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace:
- shard-mtlp: NOTRUN -> [SKIP][80] ([i915#4473] / [i915#4771]) +1 other test skip
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-6/igt@gem_exec_fair@basic-pace.html
* igt@gem_exec_fair@basic-pace-solo:
- shard-dg2: NOTRUN -> [SKIP][81] ([i915#3539])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-10/igt@gem_exec_fair@basic-pace-solo.html
* igt@gem_exec_fence@submit:
- shard-dg2: NOTRUN -> [SKIP][82] ([i915#4812]) +1 other test skip
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@gem_exec_fence@submit.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-dg2: NOTRUN -> [SKIP][83] ([i915#3539] / [i915#4852]) +2 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_gttfill@multigpu-basic:
- shard-dg2: NOTRUN -> [SKIP][84] ([i915#7697]) +1 other test skip
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@gem_exec_gttfill@multigpu-basic.html
* igt@gem_exec_params@rsvd2-dirt:
- shard-dg2: NOTRUN -> [SKIP][85] ([fdo#109283] / [i915#5107])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-6/igt@gem_exec_params@rsvd2-dirt.html
* igt@gem_exec_reloc@basic-gtt-cpu-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][86] ([i915#3281]) +5 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-8/igt@gem_exec_reloc@basic-gtt-cpu-noreloc.html
* igt@gem_exec_reloc@basic-gtt-wc:
- shard-dg2: NOTRUN -> [SKIP][87] ([i915#3281]) +5 other tests skip
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-6/igt@gem_exec_reloc@basic-gtt-wc.html
* igt@gem_exec_schedule@preempt-queue-chain:
- shard-dg2: NOTRUN -> [SKIP][88] ([i915#4537] / [i915#4812])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@gem_exec_schedule@preempt-queue-chain.html
* igt@gem_exec_schedule@preempt-queue-contexts:
- shard-mtlp: NOTRUN -> [SKIP][89] ([i915#4537] / [i915#4812])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-5/igt@gem_exec_schedule@preempt-queue-contexts.html
* igt@gem_fence_thrash@bo-copy:
- shard-dg2: NOTRUN -> [SKIP][90] ([i915#4860]) +3 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@gem_fence_thrash@bo-copy.html
* igt@gem_fenced_exec_thrash@no-spare-fences-busy:
- shard-mtlp: NOTRUN -> [SKIP][91] ([i915#4860])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-7/igt@gem_fenced_exec_thrash@no-spare-fences-busy.html
* igt@gem_lmem_swapping@heavy-multi:
- shard-glk: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#4613])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk1/igt@gem_lmem_swapping@heavy-multi.html
- shard-mtlp: NOTRUN -> [SKIP][93] ([i915#4613])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-7/igt@gem_lmem_swapping@heavy-multi.html
* igt@gem_lmem_swapping@smem-oom:
- shard-tglu: NOTRUN -> [SKIP][94] ([i915#4613])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-3/igt@gem_lmem_swapping@smem-oom.html
* igt@gem_media_vme:
- shard-dg2: NOTRUN -> [SKIP][95] ([i915#284])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-6/igt@gem_media_vme.html
* igt@gem_mmap@short-mmap:
- shard-dg2: NOTRUN -> [SKIP][96] ([i915#4083]) +6 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@gem_mmap@short-mmap.html
* igt@gem_mmap_gtt@close-race:
- shard-mtlp: NOTRUN -> [SKIP][97] ([i915#4077]) +2 other tests skip
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-7/igt@gem_mmap_gtt@close-race.html
* igt@gem_mmap_gtt@zero-extend:
- shard-dg2: NOTRUN -> [SKIP][98] ([i915#4077]) +9 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-6/igt@gem_mmap_gtt@zero-extend.html
* igt@gem_mmap_wc@write:
- shard-mtlp: NOTRUN -> [SKIP][99] ([i915#4083]) +2 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-7/igt@gem_mmap_wc@write.html
* igt@gem_pread@exhaustion:
- shard-snb: NOTRUN -> [WARN][100] ([i915#2658])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-snb4/igt@gem_pread@exhaustion.html
- shard-tglu: NOTRUN -> [WARN][101] ([i915#2658])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-7/igt@gem_pread@exhaustion.html
* igt@gem_pread@snoop:
- shard-mtlp: NOTRUN -> [SKIP][102] ([i915#3282]) +1 other test skip
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-6/igt@gem_pread@snoop.html
* igt@gem_pwrite@basic-random:
- shard-dg2: NOTRUN -> [SKIP][103] ([i915#3282]) +5 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-2/igt@gem_pwrite@basic-random.html
* igt@gem_pxp@reject-modify-context-protection-off-2:
- shard-tglu: NOTRUN -> [SKIP][104] ([i915#4270])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-3/igt@gem_pxp@reject-modify-context-protection-off-2.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-dg2: NOTRUN -> [SKIP][105] ([i915#4270]) +4 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-2/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
- shard-mtlp: NOTRUN -> [SKIP][106] ([i915#4270])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-7/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
* igt@gem_render_copy@linear-to-vebox-y-tiled:
- shard-mtlp: NOTRUN -> [SKIP][107] ([i915#8428]) +5 other tests skip
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-8/igt@gem_render_copy@linear-to-vebox-y-tiled.html
* igt@gem_userptr_blits@access-control:
- shard-mtlp: NOTRUN -> [SKIP][108] ([i915#3297]) +1 other test skip
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-6/igt@gem_userptr_blits@access-control.html
* igt@gem_userptr_blits@coherency-sync:
- shard-tglu: NOTRUN -> [SKIP][109] ([fdo#110542])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-7/igt@gem_userptr_blits@coherency-sync.html
* igt@gem_userptr_blits@invalid-mmap-offset-unsync:
- shard-tglu: NOTRUN -> [SKIP][110] ([i915#3297])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-3/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate:
- shard-dg2: NOTRUN -> [SKIP][111] ([i915#3297] / [i915#4880])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-2/igt@gem_userptr_blits@map-fixed-invalidate.html
* igt@gem_userptr_blits@sd-probe:
- shard-dg2: NOTRUN -> [SKIP][112] ([i915#3297] / [i915#4958])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@gem_userptr_blits@sd-probe.html
* igt@gen3_render_tiledy_blits:
- shard-mtlp: NOTRUN -> [SKIP][113] ([fdo#109289]) +3 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-7/igt@gen3_render_tiledy_blits.html
* igt@gen7_exec_parse@cmd-crossing-page:
- shard-dg2: NOTRUN -> [SKIP][114] ([fdo#109289])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-6/igt@gen7_exec_parse@cmd-crossing-page.html
* igt@gen9_exec_parse@basic-rejected:
- shard-tglu: NOTRUN -> [SKIP][115] ([i915#2527] / [i915#2856]) +1 other test skip
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-7/igt@gen9_exec_parse@basic-rejected.html
* igt@gen9_exec_parse@cmd-crossing-page:
- shard-mtlp: NOTRUN -> [SKIP][116] ([i915#2856]) +2 other tests skip
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-5/igt@gen9_exec_parse@cmd-crossing-page.html
* igt@gen9_exec_parse@secure-batches:
- shard-dg2: NOTRUN -> [SKIP][117] ([i915#2856]) +3 other tests skip
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-2/igt@gen9_exec_parse@secure-batches.html
* igt@i915_module_load@load:
- shard-dg2: NOTRUN -> [SKIP][118] ([i915#6227])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-6/igt@i915_module_load@load.html
* igt@i915_query@query-topology-known-pci-ids:
- shard-mtlp: NOTRUN -> [SKIP][119] ([fdo#109303])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-6/igt@i915_query@query-topology-known-pci-ids.html
* igt@i915_selftest@live@workarounds:
- shard-dg1: [PASS][120] -> [ABORT][121] ([i915#9413])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-dg1-18/igt@i915_selftest@live@workarounds.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg1-12/igt@i915_selftest@live@workarounds.html
* igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- shard-mtlp: NOTRUN -> [SKIP][122] ([i915#4212])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-7/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- shard-dg2: NOTRUN -> [SKIP][123] ([i915#4212]) +1 other test skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@kms_addfb_basic@basic-x-tiled-legacy.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-dg2: NOTRUN -> [SKIP][124] ([i915#1769] / [i915#3555])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-10/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
- shard-tglu: NOTRUN -> [SKIP][125] ([i915#1769] / [i915#3555])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-180:
- shard-tglu: NOTRUN -> [SKIP][126] ([fdo#111615] / [i915#5286]) +1 other test skip
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-7/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][127] ([fdo#111614]) +2 other tests skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-addfb:
- shard-tglu: NOTRUN -> [SKIP][128] ([i915#5286])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-3/igt@kms_big_fb@4-tiled-addfb.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-90:
- shard-mtlp: NOTRUN -> [SKIP][129] ([fdo#111614]) +6 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-6/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-tglu: NOTRUN -> [FAIL][130] ([i915#3743])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-7/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-180:
- shard-dg2: NOTRUN -> [SKIP][131] ([i915#5190]) +9 other tests skip
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-tglu: [PASS][132] -> [FAIL][133] ([i915#3743])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-tglu-8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
- shard-tglu: NOTRUN -> [SKIP][134] ([fdo#111615]) +1 other test skip
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-7/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][135] ([i915#4538] / [i915#5190]) +4 other tests skip
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-6/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-mtlp: NOTRUN -> [SKIP][136] ([i915#6187])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-7/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180:
- shard-mtlp: NOTRUN -> [SKIP][137] ([fdo#111615]) +4 other tests skip
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
* igt@kms_big_joiner@basic:
- shard-tglu: NOTRUN -> [SKIP][138] ([i915#2705])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-7/igt@kms_big_joiner@basic.html
* igt@kms_big_joiner@invalid-modeset:
- shard-dg2: NOTRUN -> [SKIP][139] ([i915#2705]) +1 other test skip
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-6/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_cdclk@mode-transition@pipe-d-dp-4:
- shard-dg2: NOTRUN -> [SKIP][140] ([i915#4087] / [i915#7213]) +3 other tests skip
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-11/igt@kms_cdclk@mode-transition@pipe-d-dp-4.html
* igt@kms_cdclk@plane-scaling:
- shard-tglu: NOTRUN -> [SKIP][141] ([i915#3742])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-3/igt@kms_cdclk@plane-scaling.html
* igt@kms_chamelium_color@ctm-0-25:
- shard-tglu: NOTRUN -> [SKIP][142] ([fdo#111827])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-7/igt@kms_chamelium_color@ctm-0-25.html
* igt@kms_chamelium_color@ctm-max:
- shard-glk: NOTRUN -> [SKIP][143] ([fdo#109271]) +41 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk1/igt@kms_chamelium_color@ctm-max.html
- shard-mtlp: NOTRUN -> [SKIP][144] ([fdo#111827])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-7/igt@kms_chamelium_color@ctm-max.html
* igt@kms_chamelium_color@degamma:
- shard-dg2: NOTRUN -> [SKIP][145] ([fdo#111827]) +2 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@kms_chamelium_color@degamma.html
* igt@kms_chamelium_frames@hdmi-crc-multiple:
- shard-dg2: NOTRUN -> [SKIP][146] ([i915#7828]) +4 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@kms_chamelium_frames@hdmi-crc-multiple.html
* igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats:
- shard-tglu: NOTRUN -> [SKIP][147] ([i915#7828]) +3 other tests skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-7/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html
* igt@kms_chamelium_hpd@dp-hpd-for-each-pipe:
- shard-mtlp: NOTRUN -> [SKIP][148] ([i915#7828]) +5 other tests skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-6/igt@kms_chamelium_hpd@dp-hpd-for-each-pipe.html
* igt@kms_content_protection@legacy:
- shard-mtlp: NOTRUN -> [SKIP][149] ([i915#6944])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-6/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@srm:
- shard-dg2: NOTRUN -> [SKIP][150] ([i915#7118]) +2 other tests skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-6/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@cursor-onscreen-32x10:
- shard-mtlp: NOTRUN -> [SKIP][151] ([i915#3555] / [i915#8814]) +3 other tests skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-6/igt@kms_cursor_crc@cursor-onscreen-32x10.html
* igt@kms_cursor_crc@cursor-onscreen-32x32:
- shard-tglu: NOTRUN -> [SKIP][152] ([i915#3555]) +3 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-7/igt@kms_cursor_crc@cursor-onscreen-32x32.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-dg2: NOTRUN -> [SKIP][153] ([i915#3359]) +4 other tests skip
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-2/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-tglu: NOTRUN -> [SKIP][154] ([fdo#109274])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-3/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-dg2: NOTRUN -> [SKIP][155] ([fdo#109274] / [i915#5354]) +3 other tests skip
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- shard-dg2: NOTRUN -> [SKIP][156] ([i915#4103] / [i915#4213] / [i915#5608])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic:
- shard-mtlp: NOTRUN -> [SKIP][157] ([i915#3546])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-6/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][158] -> [FAIL][159] ([i915#2346])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@forked-bo@all-pipes:
- shard-mtlp: [PASS][160] -> [DMESG-WARN][161] ([i915#2017])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-mtlp-5/igt@kms_cursor_legacy@forked-bo@all-pipes.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-4/igt@kms_cursor_legacy@forked-bo@all-pipes.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-tglu: NOTRUN -> [SKIP][162] ([i915#4103])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-3/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_dither@fb-8bpc-vs-panel-8bpc:
- shard-dg2: NOTRUN -> [SKIP][163] ([i915#3555]) +4 other tests skip
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-10/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
* igt@kms_dsc@dsc-basic:
- shard-dg2: NOTRUN -> [SKIP][164] ([i915#3555] / [i915#3840] / [i915#4098])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-2/igt@kms_dsc@dsc-basic.html
* igt@kms_dsc@dsc-with-formats:
- shard-mtlp: NOTRUN -> [SKIP][165] ([i915#3555] / [i915#3840] / [i915#4098])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-7/igt@kms_dsc@dsc-with-formats.html
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][166] ([i915#3637]) +5 other tests skip
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-7/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-dg2: NOTRUN -> [SKIP][167] ([fdo#109274] / [fdo#111767])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-modeset-vs-hang:
- shard-dg2: NOTRUN -> [SKIP][168] ([fdo#109274]) +1 other test skip
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html
* igt@kms_flip@2x-flip-vs-panning-vs-hang:
- shard-tglu: NOTRUN -> [SKIP][169] ([fdo#109274] / [i915#3637]) +3 other tests skip
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-7/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
* igt@kms_flip@2x-flip-vs-rmfb-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][170] ([fdo#111767] / [i915#3637])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-5/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html
* igt@kms_flip@flip-vs-fences-interruptible:
- shard-dg2: NOTRUN -> [SKIP][171] ([i915#8381])
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-6/igt@kms_flip@flip-vs-fences-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][172] ([i915#8810])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][173] ([i915#2672])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-7/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][174] ([i915#2672] / [i915#3555])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][175] ([i915#2672])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][176] ([i915#2587] / [i915#2672])
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-mtlp: NOTRUN -> [SKIP][177] ([i915#1825]) +18 other tests skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-dg2: NOTRUN -> [SKIP][178] ([i915#3458]) +15 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render:
- shard-dg2: NOTRUN -> [SKIP][179] ([i915#5354]) +25 other tests skip
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-10/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
- shard-tglu: NOTRUN -> [SKIP][180] ([fdo#110189]) +9 other tests skip
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-7/igt@kms_frontbuffer_tracking@fbcpsr-stridechange.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
- shard-tglu: NOTRUN -> [SKIP][181] ([fdo#109280]) +15 other tests skip
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][182] ([i915#8708]) +21 other tests skip
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][183] ([i915#8708]) +5 other tests skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-8/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch:
- shard-dg2: NOTRUN -> [SKIP][184] ([i915#3555] / [i915#8228])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-6/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@static-toggle-dpms:
- shard-mtlp: NOTRUN -> [SKIP][185] ([i915#3555] / [i915#8228])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-8/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_hdr@static-toggle-suspend:
- shard-tglu: NOTRUN -> [SKIP][186] ([i915#3555] / [i915#8228])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-7/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_panel_fitting@legacy:
- shard-dg2: NOTRUN -> [SKIP][187] ([i915#6301])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@kms_panel_fitting@legacy.html
* igt@kms_plane_lowres@tiling-4@pipe-c-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][188] ([i915#3582]) +3 other tests skip
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-6/igt@kms_plane_lowres@tiling-4@pipe-c-edp-1.html
* igt@kms_plane_lowres@tiling-yf:
- shard-dg2: NOTRUN -> [SKIP][189] ([i915#3555] / [i915#8821])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-2/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-dg2: NOTRUN -> [SKIP][190] ([i915#6953])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-10/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][191] ([i915#5176]) +1 other test skip
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-6/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][192] ([i915#5176] / [i915#9423]) +3 other tests skip
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg1-17/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-hdmi-a-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-c-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][193] ([i915#5235]) +7 other tests skip
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-3/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-c-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-dp-4:
- shard-dg2: NOTRUN -> [SKIP][194] ([i915#5235]) +11 other tests skip
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-11/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-dp-4.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][195] ([i915#5235]) +3 other tests skip
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-7/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d-edp-1.html
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-tglu: NOTRUN -> [SKIP][196] ([fdo#111068] / [i915#9683])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-7/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-dg2: NOTRUN -> [SKIP][197] ([i915#9683]) +1 other test skip
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-tglu: NOTRUN -> [SKIP][198] ([fdo#109642] / [fdo#111068] / [i915#9683])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-3/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-dg2: NOTRUN -> [SKIP][199] ([i915#9681]) +2 other tests skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-tglu: NOTRUN -> [SKIP][200] ([i915#9673]) +1 other test skip
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-3/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_rotation_crc@primary-rotation-270:
- shard-dg2: NOTRUN -> [SKIP][201] ([i915#4235]) +1 other test skip
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-10/igt@kms_rotation_crc@primary-rotation-270.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-tglu: NOTRUN -> [SKIP][202] ([fdo#111615] / [i915#5289])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-7/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-mtlp: NOTRUN -> [SKIP][203] ([i915#4235]) +1 other test skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_setmode@basic-clone-single-crtc:
- shard-mtlp: NOTRUN -> [SKIP][204] ([i915#3555] / [i915#8809])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-7/igt@kms_setmode@basic-clone-single-crtc.html
* igt@kms_setmode@invalid-clone-exclusive-crtc:
- shard-dg2: NOTRUN -> [SKIP][205] ([i915#3555] / [i915#4098])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-2/igt@kms_setmode@invalid-clone-exclusive-crtc.html
* igt@kms_sysfs_edid_timing:
- shard-dg2: NOTRUN -> [FAIL][206] ([IGT#2])
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@kms_sysfs_edid_timing.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-tglu: NOTRUN -> [SKIP][207] ([i915#8623])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-3/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-mtlp: NOTRUN -> [SKIP][208] ([i915#8623])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-7/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-edp-1:
- shard-mtlp: [PASS][209] -> [FAIL][210] ([i915#9196])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-mtlp-5/igt@kms_universal_plane@cursor-fb-leak@pipe-b-edp-1.html
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-2/igt@kms_universal_plane@cursor-fb-leak@pipe-b-edp-1.html
* igt@kms_writeback@writeback-check-output:
- shard-mtlp: NOTRUN -> [SKIP][211] ([i915#2437])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-8/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-dg2: NOTRUN -> [SKIP][212] ([i915#2437])
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-2/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf@global-sseu-config:
- shard-dg2: NOTRUN -> [SKIP][213] ([i915#7387])
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-2/igt@perf@global-sseu-config.html
* igt@perf@per-context-mode-unprivileged:
- shard-tglu: NOTRUN -> [SKIP][214] ([fdo#109289]) +2 other tests skip
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-3/igt@perf@per-context-mode-unprivileged.html
* igt@perf_pmu@busy-double-start@rcs0:
- shard-mtlp: [PASS][215] -> [FAIL][216] ([i915#4349])
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-mtlp-8/igt@perf_pmu@busy-double-start@rcs0.html
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-8/igt@perf_pmu@busy-double-start@rcs0.html
* igt@perf_pmu@busy-double-start@vecs1:
- shard-dg2: [PASS][217] -> [FAIL][218] ([i915#4349]) +3 other tests fail
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-dg2-11/igt@perf_pmu@busy-double-start@vecs1.html
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-10/igt@perf_pmu@busy-double-start@vecs1.html
* igt@perf_pmu@cpu-hotplug:
- shard-mtlp: NOTRUN -> [SKIP][219] ([i915#8850])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-5/igt@perf_pmu@cpu-hotplug.html
* igt@perf_pmu@module-unload:
- shard-dg2: NOTRUN -> [FAIL][220] ([i915#5793])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-2/igt@perf_pmu@module-unload.html
* igt@perf_pmu@rc6-all-gts:
- shard-dg2: NOTRUN -> [SKIP][221] ([i915#5608] / [i915#8516])
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@perf_pmu@rc6-all-gts.html
* igt@perf_pmu@rc6@other-idle-gt0:
- shard-tglu: NOTRUN -> [SKIP][222] ([i915#8516])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-7/igt@perf_pmu@rc6@other-idle-gt0.html
* igt@prime_vgem@coherency-gtt:
- shard-dg2: NOTRUN -> [SKIP][223] ([i915#3708] / [i915#4077]) +2 other tests skip
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@prime_vgem@coherency-gtt.html
* igt@prime_vgem@fence-read-hang:
- shard-dg2: NOTRUN -> [SKIP][224] ([i915#3708])
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-5/igt@prime_vgem@fence-read-hang.html
* igt@v3d/v3d_job_submission@array-job-submission:
- shard-dg2: NOTRUN -> [SKIP][225] ([i915#2575]) +13 other tests skip
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-2/igt@v3d/v3d_job_submission@array-job-submission.html
* igt@v3d/v3d_mmap@mmap-bo:
- shard-mtlp: NOTRUN -> [SKIP][226] ([i915#2575]) +6 other tests skip
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-7/igt@v3d/v3d_mmap@mmap-bo.html
* igt@v3d/v3d_submit_cl@valid-submission:
- shard-tglu: NOTRUN -> [SKIP][227] ([fdo#109315] / [i915#2575]) +4 other tests skip
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-3/igt@v3d/v3d_submit_cl@valid-submission.html
* igt@vc4/vc4_mmap@mmap-bo:
- shard-dg2: NOTRUN -> [SKIP][228] ([i915#7711]) +8 other tests skip
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-6/igt@vc4/vc4_mmap@mmap-bo.html
* igt@vc4/vc4_perfmon@create-single-perfmon:
- shard-mtlp: NOTRUN -> [SKIP][229] ([i915#7711]) +3 other tests skip
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-6/igt@vc4/vc4_perfmon@create-single-perfmon.html
* igt@vc4/vc4_tiling@set-get:
- shard-tglu: NOTRUN -> [SKIP][230] ([i915#2575]) +2 other tests skip
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-7/igt@vc4/vc4_tiling@set-get.html
#### Possible fixes ####
* igt@debugfs_test@read_all_entries_display_off:
- shard-mtlp: [ABORT][231] ([i915#9414]) -> [PASS][232] +1 other test pass
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-mtlp-8/igt@debugfs_test@read_all_entries_display_off.html
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-8/igt@debugfs_test@read_all_entries_display_off.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglu: [FAIL][233] ([i915#2842]) -> [PASS][234]
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-tglu-8/igt@gem_exec_fair@basic-pace-share@rcs0.html
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-3/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [FAIL][235] ([i915#2842]) -> [PASS][236]
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-glk6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-glk2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@i915_pm_freq_api@freq-suspend@gt0:
- shard-dg2: [INCOMPLETE][237] ([i915#9407]) -> [PASS][238]
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-dg2-2/igt@i915_pm_freq_api@freq-suspend@gt0.html
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-2/igt@i915_pm_freq_api@freq-suspend@gt0.html
* igt@i915_pm_rpm@system-suspend:
- shard-dg1: [FAIL][239] ([fdo#103375]) -> [PASS][240] +2 other tests pass
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-dg1-18/igt@i915_pm_rpm@system-suspend.html
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg1-12/igt@i915_pm_rpm@system-suspend.html
* igt@i915_pm_rps@reset:
- shard-snb: [INCOMPLETE][241] ([i915#7790]) -> [PASS][242]
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-snb5/igt@i915_pm_rps@reset.html
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-snb4/igt@i915_pm_rps@reset.html
- shard-tglu: [INCOMPLETE][243] -> [PASS][244]
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-tglu-6/igt@i915_pm_rps@reset.html
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-7/igt@i915_pm_rps@reset.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-mtlp: [FAIL][245] ([i915#5138]) -> [PASS][246]
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
- shard-dg2: [FAIL][247] ([i915#6880]) -> [PASS][248]
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite.html
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite.html
* {igt@kms_pm_rpm@dpms-non-lpsp}:
- shard-dg2: [SKIP][249] ([i915#9519]) -> [PASS][250]
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-dg2-10/igt@kms_pm_rpm@dpms-non-lpsp.html
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-dg2-2/igt@kms_pm_rpm@dpms-non-lpsp.html
* igt@perf_pmu@busy-double-start@ccs0:
- shard-mtlp: [FAIL][251] ([i915#4349]) -> [PASS][252]
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-mtlp-8/igt@perf_pmu@busy-double-start@ccs0.html
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-8/igt@perf_pmu@busy-double-start@ccs0.html
#### Warnings ####
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglu: [FAIL][253] ([i915#2842]) -> [FAIL][254] ([i915#2876])
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-tglu-7/igt@gem_exec_fair@basic-pace@rcs0.html
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-tglu-9/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@kms_async_flips@crc@pipe-d-edp-1:
- shard-mtlp: [FAIL][255] ([i915#8247]) -> [DMESG-FAIL][256] ([i915#8561]) +1 other test dmesg-fail
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13921/shard-mtlp-7/igt@kms_async_flips@crc@pipe-d-edp-1.html
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/shard-mtlp-6/igt@kms_async_flips@crc@pipe-d-edp-1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2876]: https://gitlab.freedesktop.org/drm/intel/issues/2876
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3582]: https://gitlab.freedesktop.org/drm/intel/issues/3582
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473
[i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958
[i915#5107]: https://gitlab.freedesktop.org/drm/intel/issues/5107
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5793]: https://gitlab.freedesktop.org/drm/intel/issues/5793
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6187]: https://gitlab.freedesktop.org/drm/intel/issues/6187
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
[i915#7297]: https://gitlab.freedesktop.org/drm/intel/issues/7297
[i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7790]: https://gitlab.freedesktop.org/drm/intel/issues/7790
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8190]: https://gitlab.freedesktop.org/drm/intel/issues/8190
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
[i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8516]: https://gitlab.freedesktop.org/drm/intel/issues/8516
[i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
[i915#8561]: https://gitlab.freedesktop.org/drm/intel/issues/8561
[i915#8562]: https://gitlab.freedesktop.org/drm/intel/issues/8562
[i915#8623]: https://gitlab.freedesktop.org/drm/intel/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
[i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
[i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810
[i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
[i915#8821]: https://gitlab.freedesktop.org/drm/intel/issues/8821
[i915#8850]: https://gitlab.freedesktop.org/drm/intel/issues/8850
[i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196
[i915#9310]: https://gitlab.freedesktop.org/drm/intel/issues/9310
[i915#9340]: https://gitlab.freedesktop.org/drm/intel/issues/9340
[i915#9407]: https://gitlab.freedesktop.org/drm/intel/issues/9407
[i915#9412]: https://gitlab.freedesktop.org/drm/intel/issues/9412
[i915#9413]: https://gitlab.freedesktop.org/drm/intel/issues/9413
[i915#9414]: https://gitlab.freedesktop.org/drm/intel/issues/9414
[i915#9423]: https://gitlab.freedesktop.org/drm/intel/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/intel/issues/9424
[i915#9433]: https://gitlab.freedesktop.org/drm/intel/issues/9433
[i915#9519]: https://gitlab.freedesktop.org/drm/intel/issues/9519
[i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
[i915#9681]: https://gitlab.freedesktop.org/drm/intel/issues/9681
[i915#9683]: https://gitlab.freedesktop.org/drm/intel/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/intel/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/intel/issues/9688
Build changes
-------------
* Linux: CI_DRM_13921 -> Patchwork_126883v1
CI-20190529: 20190529
CI_DRM_13921: 002e96d8067fa253ee53af2fa191717f4f5b782b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7603: 2ddd8cac90d4333943cd017319514949b047821b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_126883v1: 002e96d8067fa253ee53af2fa191717f4f5b782b @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126883v1/index.html
[-- Attachment #2: Type: text/html, Size: 76855 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/cdclk: Remove divider field from tables
2023-11-24 20:55 [Intel-gfx] [PATCH] drm/i915/cdclk: Remove divider field from tables Gustavo Sousa
2023-11-24 21:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2023-11-26 4:12 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2023-11-27 16:21 ` Matt Roper
2023-11-28 8:43 ` Ville Syrjälä
2 siblings, 1 reply; 14+ messages in thread
From: Matt Roper @ 2023-11-27 16:21 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-gfx
On Fri, Nov 24, 2023 at 05:55:23PM -0300, Gustavo Sousa wrote:
> The cdclk tables were introduced with commit 736da8112fee ("drm/i915:
> Use literal representation of cdclk tables"). It has been almost 4 years
> and the divider field was not really used yet. Let's remove it.
I think we need to go the other way and actually start using it instead
of (incorrectly) trying to re-derive it from cdclk->vco. The logic the
driver is using today doesn't account for the potential use of
squashing, which means we program the wrong divider value into CDCLK_CTL
in some cases. I pointed that out during the LNL code reviews a couple
months ago, and I believe Stan is working on fixing that.
I wonder if the misprogramming we're doing today is what requires the
"HACK" at the bottom of intel_crtc_compute_min_cdclk for DG2?
Matt
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 269 ++++++++++-----------
> 1 file changed, 134 insertions(+), 135 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index b93d1ad7936d..7f85a216ff5c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1227,183 +1227,182 @@ struct intel_cdclk_vals {
> u32 cdclk;
> u16 refclk;
> u16 waveform;
> - u8 divider; /* CD2X divider * 2 */
> u8 ratio;
> };
>
> static const struct intel_cdclk_vals bxt_cdclk_table[] = {
> - { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
> - { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
> - { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
> - { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
> - { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
> + { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
> + { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
> + { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
> + { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
> + { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
> {}
> };
>
> static const struct intel_cdclk_vals glk_cdclk_table[] = {
> - { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
> - { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
> - { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
> + { .refclk = 19200, .cdclk = 79200, .ratio = 33 },
> + { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
> + { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
> {}
> };
>
> static const struct intel_cdclk_vals icl_cdclk_table[] = {
> - { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
> - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> - { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
> - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> -
> - { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
> - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> - { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
> - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> -
> - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
> - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> - { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
> - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> + { .refclk = 19200, .cdclk = 172800, .ratio = 18 },
> + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> + { .refclk = 19200, .cdclk = 326400, .ratio = 68 },
> + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> +
> + { .refclk = 24000, .cdclk = 180000, .ratio = 15 },
> + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> + { .refclk = 24000, .cdclk = 324000, .ratio = 54 },
> + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> +
> + { .refclk = 38400, .cdclk = 172800, .ratio = 9 },
> + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> + { .refclk = 38400, .cdclk = 326400, .ratio = 34 },
> + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> {}
> };
>
> static const struct intel_cdclk_vals rkl_cdclk_table[] = {
> - { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 },
> - { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 },
> - { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 },
> - { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
> - { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
> - { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },
> -
> - { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 },
> - { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 },
> - { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 },
> - { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
> - { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 },
> - { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },
> -
> - { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
> - { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
> - { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
> - { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
> - { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
> - { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
> + { .refclk = 19200, .cdclk = 172800, .ratio = 36 },
> + { .refclk = 19200, .cdclk = 192000, .ratio = 40 },
> + { .refclk = 19200, .cdclk = 307200, .ratio = 64 },
> + { .refclk = 19200, .cdclk = 326400, .ratio = 136 },
> + { .refclk = 19200, .cdclk = 556800, .ratio = 116 },
> + { .refclk = 19200, .cdclk = 652800, .ratio = 136 },
> +
> + { .refclk = 24000, .cdclk = 180000, .ratio = 30 },
> + { .refclk = 24000, .cdclk = 192000, .ratio = 32 },
> + { .refclk = 24000, .cdclk = 312000, .ratio = 52 },
> + { .refclk = 24000, .cdclk = 324000, .ratio = 108 },
> + { .refclk = 24000, .cdclk = 552000, .ratio = 92 },
> + { .refclk = 24000, .cdclk = 648000, .ratio = 108 },
> +
> + { .refclk = 38400, .cdclk = 172800, .ratio = 18 },
> + { .refclk = 38400, .cdclk = 192000, .ratio = 20 },
> + { .refclk = 38400, .cdclk = 307200, .ratio = 32 },
> + { .refclk = 38400, .cdclk = 326400, .ratio = 68 },
> + { .refclk = 38400, .cdclk = 556800, .ratio = 58 },
> + { .refclk = 38400, .cdclk = 652800, .ratio = 68 },
> {}
> };
>
> static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
> - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
>
> - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> - { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
> + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> + { .refclk = 24400, .cdclk = 648000, .ratio = 54 },
>
> - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> {}
> };
>
> static const struct intel_cdclk_vals adlp_cdclk_table[] = {
> - { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> -
> - { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> -
> - { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> + { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
> + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> +
> + { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
> + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> +
> + { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
> + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> {}
> };
>
> static const struct intel_cdclk_vals rplu_cdclk_table[] = {
> - { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> - { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
> - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> -
> - { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> - { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
> - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> -
> - { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
> - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> + { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
> + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> + { .refclk = 19200, .cdclk = 480000, .ratio = 50 },
> + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> +
> + { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
> + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> + { .refclk = 24000, .cdclk = 480000, .ratio = 40 },
> + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> +
> + { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
> + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> + { .refclk = 38400, .cdclk = 480000, .ratio = 25 },
> + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> {}
> };
>
> static const struct intel_cdclk_vals dg2_cdclk_table[] = {
> - { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
> - { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
> - { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 },
> - { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a },
> - { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa },
> - { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a },
> - { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 },
> - { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 },
> - { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee },
> - { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de },
> - { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
> - { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
> - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
> + { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
> + { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
> + { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
> + { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
> + { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
> + { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
> + { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
> + { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
> + { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
> + { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
> + { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
> + { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
> + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
> {}
> };
>
> static const struct intel_cdclk_vals mtl_cdclk_table[] = {
> - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
> - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
> - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
> - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
> + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
> + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
> + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
> + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
> + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
> + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
> {}
> };
>
> static const struct intel_cdclk_vals lnl_cdclk_table[] = {
> - { .refclk = 38400, .cdclk = 153600, .divider = 2, .ratio = 16, .waveform = 0xaaaa },
> - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> - { .refclk = 38400, .cdclk = 211200, .divider = 2, .ratio = 16, .waveform = 0xdbb6 },
> - { .refclk = 38400, .cdclk = 230400, .divider = 2, .ratio = 16, .waveform = 0xeeee },
> - { .refclk = 38400, .cdclk = 249600, .divider = 2, .ratio = 16, .waveform = 0xf7de },
> - { .refclk = 38400, .cdclk = 268800, .divider = 2, .ratio = 16, .waveform = 0xfefe },
> - { .refclk = 38400, .cdclk = 288000, .divider = 2, .ratio = 16, .waveform = 0xfffe },
> - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0xffff },
> - { .refclk = 38400, .cdclk = 330000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 },
> - { .refclk = 38400, .cdclk = 360000, .divider = 2, .ratio = 25, .waveform = 0xeeee },
> - { .refclk = 38400, .cdclk = 390000, .divider = 2, .ratio = 25, .waveform = 0xf7de },
> - { .refclk = 38400, .cdclk = 420000, .divider = 2, .ratio = 25, .waveform = 0xfefe },
> - { .refclk = 38400, .cdclk = 450000, .divider = 2, .ratio = 25, .waveform = 0xfffe },
> - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0xffff },
> - { .refclk = 38400, .cdclk = 487200, .divider = 2, .ratio = 29, .waveform = 0xfefe },
> - { .refclk = 38400, .cdclk = 522000, .divider = 2, .ratio = 29, .waveform = 0xfffe },
> - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0xffff },
> - { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
> - { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
> - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
> + { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
> + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
> + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
> + { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
> + { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
> + { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
> + { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
> + { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
> + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
> + { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
> + { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
> + { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
> + { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
> + { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
> + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
> + { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
> + { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
> + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
> + { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
> + { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
> + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
> {}
> };
>
> --
> 2.42.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/cdclk: Remove divider field from tables
2023-11-27 16:21 ` [Intel-gfx] [PATCH] " Matt Roper
@ 2023-11-28 8:43 ` Ville Syrjälä
2023-11-28 8:53 ` Lisovskiy, Stanislav
` (2 more replies)
0 siblings, 3 replies; 14+ messages in thread
From: Ville Syrjälä @ 2023-11-28 8:43 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Mon, Nov 27, 2023 at 08:21:46AM -0800, Matt Roper wrote:
> On Fri, Nov 24, 2023 at 05:55:23PM -0300, Gustavo Sousa wrote:
> > The cdclk tables were introduced with commit 736da8112fee ("drm/i915:
> > Use literal representation of cdclk tables"). It has been almost 4 years
> > and the divider field was not really used yet. Let's remove it.
>
> I think we need to go the other way and actually start using it instead
> of (incorrectly) trying to re-derive it from cdclk->vco. The logic the
> driver is using today doesn't account for the potential use of
> squashing, which means we program the wrong divider value into CDCLK_CTL
> in some cases. I pointed that out during the LNL code reviews a couple
> months ago, and I believe Stan is working on fixing that.
The code should be correct as is, but it does assume that the cd2x
divider is 2 when squashing is used. If that no longer holds then we
have to change something.
>
> I wonder if the misprogramming we're doing today is what requires the
> "HACK" at the bottom of intel_crtc_compute_min_cdclk for DG2?
>
>
> Matt
>
> >
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 269 ++++++++++-----------
> > 1 file changed, 134 insertions(+), 135 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index b93d1ad7936d..7f85a216ff5c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1227,183 +1227,182 @@ struct intel_cdclk_vals {
> > u32 cdclk;
> > u16 refclk;
> > u16 waveform;
> > - u8 divider; /* CD2X divider * 2 */
> > u8 ratio;
> > };
> >
> > static const struct intel_cdclk_vals bxt_cdclk_table[] = {
> > - { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
> > - { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
> > - { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
> > - { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
> > - { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
> > + { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
> > + { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
> > + { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
> > + { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
> > + { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
> > {}
> > };
> >
> > static const struct intel_cdclk_vals glk_cdclk_table[] = {
> > - { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
> > - { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
> > - { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
> > + { .refclk = 19200, .cdclk = 79200, .ratio = 33 },
> > + { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
> > + { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
> > {}
> > };
> >
> > static const struct intel_cdclk_vals icl_cdclk_table[] = {
> > - { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
> > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > - { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
> > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > -
> > - { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
> > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > - { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
> > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > -
> > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
> > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > - { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
> > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > + { .refclk = 19200, .cdclk = 172800, .ratio = 18 },
> > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > + { .refclk = 19200, .cdclk = 326400, .ratio = 68 },
> > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > +
> > + { .refclk = 24000, .cdclk = 180000, .ratio = 15 },
> > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > + { .refclk = 24000, .cdclk = 324000, .ratio = 54 },
> > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> > +
> > + { .refclk = 38400, .cdclk = 172800, .ratio = 9 },
> > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > + { .refclk = 38400, .cdclk = 326400, .ratio = 34 },
> > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > {}
> > };
> >
> > static const struct intel_cdclk_vals rkl_cdclk_table[] = {
> > - { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 },
> > - { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 },
> > - { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 },
> > - { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
> > - { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
> > - { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },
> > -
> > - { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 },
> > - { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 },
> > - { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 },
> > - { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
> > - { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 },
> > - { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },
> > -
> > - { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
> > - { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
> > - { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
> > - { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
> > - { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
> > - { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
> > + { .refclk = 19200, .cdclk = 172800, .ratio = 36 },
> > + { .refclk = 19200, .cdclk = 192000, .ratio = 40 },
> > + { .refclk = 19200, .cdclk = 307200, .ratio = 64 },
> > + { .refclk = 19200, .cdclk = 326400, .ratio = 136 },
> > + { .refclk = 19200, .cdclk = 556800, .ratio = 116 },
> > + { .refclk = 19200, .cdclk = 652800, .ratio = 136 },
> > +
> > + { .refclk = 24000, .cdclk = 180000, .ratio = 30 },
> > + { .refclk = 24000, .cdclk = 192000, .ratio = 32 },
> > + { .refclk = 24000, .cdclk = 312000, .ratio = 52 },
> > + { .refclk = 24000, .cdclk = 324000, .ratio = 108 },
> > + { .refclk = 24000, .cdclk = 552000, .ratio = 92 },
> > + { .refclk = 24000, .cdclk = 648000, .ratio = 108 },
> > +
> > + { .refclk = 38400, .cdclk = 172800, .ratio = 18 },
> > + { .refclk = 38400, .cdclk = 192000, .ratio = 20 },
> > + { .refclk = 38400, .cdclk = 307200, .ratio = 32 },
> > + { .refclk = 38400, .cdclk = 326400, .ratio = 68 },
> > + { .refclk = 38400, .cdclk = 556800, .ratio = 58 },
> > + { .refclk = 38400, .cdclk = 652800, .ratio = 68 },
> > {}
> > };
> >
> > static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
> > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> >
> > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > - { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > + { .refclk = 24400, .cdclk = 648000, .ratio = 54 },
> >
> > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > {}
> > };
> >
> > static const struct intel_cdclk_vals adlp_cdclk_table[] = {
> > - { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > -
> > - { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > -
> > - { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > + { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
> > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > +
> > + { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
> > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> > +
> > + { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
> > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > {}
> > };
> >
> > static const struct intel_cdclk_vals rplu_cdclk_table[] = {
> > - { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > - { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
> > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > -
> > - { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > - { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
> > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > -
> > - { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
> > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > + { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
> > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > + { .refclk = 19200, .cdclk = 480000, .ratio = 50 },
> > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > +
> > + { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
> > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > + { .refclk = 24000, .cdclk = 480000, .ratio = 40 },
> > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> > +
> > + { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
> > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > + { .refclk = 38400, .cdclk = 480000, .ratio = 25 },
> > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > {}
> > };
> >
> > static const struct intel_cdclk_vals dg2_cdclk_table[] = {
> > - { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
> > - { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
> > - { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 },
> > - { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a },
> > - { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa },
> > - { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a },
> > - { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 },
> > - { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 },
> > - { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee },
> > - { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de },
> > - { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
> > - { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
> > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
> > + { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
> > + { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
> > + { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
> > + { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
> > + { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
> > + { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
> > + { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
> > + { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
> > + { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
> > + { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
> > + { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
> > + { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
> > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
> > {}
> > };
> >
> > static const struct intel_cdclk_vals mtl_cdclk_table[] = {
> > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
> > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
> > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
> > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
> > + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
> > + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
> > + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
> > + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
> > + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
> > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
> > {}
> > };
> >
> > static const struct intel_cdclk_vals lnl_cdclk_table[] = {
> > - { .refclk = 38400, .cdclk = 153600, .divider = 2, .ratio = 16, .waveform = 0xaaaa },
> > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> > - { .refclk = 38400, .cdclk = 211200, .divider = 2, .ratio = 16, .waveform = 0xdbb6 },
> > - { .refclk = 38400, .cdclk = 230400, .divider = 2, .ratio = 16, .waveform = 0xeeee },
> > - { .refclk = 38400, .cdclk = 249600, .divider = 2, .ratio = 16, .waveform = 0xf7de },
> > - { .refclk = 38400, .cdclk = 268800, .divider = 2, .ratio = 16, .waveform = 0xfefe },
> > - { .refclk = 38400, .cdclk = 288000, .divider = 2, .ratio = 16, .waveform = 0xfffe },
> > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0xffff },
> > - { .refclk = 38400, .cdclk = 330000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 },
> > - { .refclk = 38400, .cdclk = 360000, .divider = 2, .ratio = 25, .waveform = 0xeeee },
> > - { .refclk = 38400, .cdclk = 390000, .divider = 2, .ratio = 25, .waveform = 0xf7de },
> > - { .refclk = 38400, .cdclk = 420000, .divider = 2, .ratio = 25, .waveform = 0xfefe },
> > - { .refclk = 38400, .cdclk = 450000, .divider = 2, .ratio = 25, .waveform = 0xfffe },
> > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0xffff },
> > - { .refclk = 38400, .cdclk = 487200, .divider = 2, .ratio = 29, .waveform = 0xfefe },
> > - { .refclk = 38400, .cdclk = 522000, .divider = 2, .ratio = 29, .waveform = 0xfffe },
> > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0xffff },
> > - { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
> > - { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
> > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
> > + { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
> > + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
> > + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
> > + { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
> > + { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
> > + { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
> > + { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
> > + { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
> > + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
> > + { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
> > + { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
> > + { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
> > + { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
> > + { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
> > + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
> > + { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
> > + { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
> > + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
> > + { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
> > + { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
> > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
> > {}
> > };
> >
> > --
> > 2.42.1
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/cdclk: Remove divider field from tables
2023-11-28 8:43 ` Ville Syrjälä
@ 2023-11-28 8:53 ` Lisovskiy, Stanislav
2023-11-28 9:01 ` Ville Syrjälä
2023-11-28 9:51 ` Ville Syrjälä
2 siblings, 0 replies; 14+ messages in thread
From: Lisovskiy, Stanislav @ 2023-11-28 8:53 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Matt Roper
On Tue, Nov 28, 2023 at 10:43:36AM +0200, Ville Syrjälä wrote:
> On Mon, Nov 27, 2023 at 08:21:46AM -0800, Matt Roper wrote:
> > On Fri, Nov 24, 2023 at 05:55:23PM -0300, Gustavo Sousa wrote:
> > > The cdclk tables were introduced with commit 736da8112fee ("drm/i915:
> > > Use literal representation of cdclk tables"). It has been almost 4 years
> > > and the divider field was not really used yet. Let's remove it.
> >
> > I think we need to go the other way and actually start using it instead
> > of (incorrectly) trying to re-derive it from cdclk->vco. The logic the
> > driver is using today doesn't account for the potential use of
> > squashing, which means we program the wrong divider value into CDCLK_CTL
> > in some cases. I pointed that out during the LNL code reviews a couple
> > months ago, and I believe Stan is working on fixing that.
>
> The code should be correct as is, but it does assume that the cd2x
> divider is 2 when squashing is used. If that no longer holds then we
> have to change something.
So we need to have some kind of a consensus/agreement here, whether are we modify the
calculation function and remove divider from the table, or do we just
use the value from the table.
So which approach is better?
Stan
>
> >
> > I wonder if the misprogramming we're doing today is what requires the
> > "HACK" at the bottom of intel_crtc_compute_min_cdclk for DG2?
> >
> >
> > Matt
> >
> > >
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_cdclk.c | 269 ++++++++++-----------
> > > 1 file changed, 134 insertions(+), 135 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > index b93d1ad7936d..7f85a216ff5c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > @@ -1227,183 +1227,182 @@ struct intel_cdclk_vals {
> > > u32 cdclk;
> > > u16 refclk;
> > > u16 waveform;
> > > - u8 divider; /* CD2X divider * 2 */
> > > u8 ratio;
> > > };
> > >
> > > static const struct intel_cdclk_vals bxt_cdclk_table[] = {
> > > - { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
> > > - { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
> > > - { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
> > > - { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
> > > - { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
> > > + { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
> > > + { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
> > > + { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
> > > + { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
> > > + { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals glk_cdclk_table[] = {
> > > - { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
> > > - { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
> > > - { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
> > > + { .refclk = 19200, .cdclk = 79200, .ratio = 33 },
> > > + { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
> > > + { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals icl_cdclk_table[] = {
> > > - { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
> > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > > - { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
> > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > > -
> > > - { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
> > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > > - { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
> > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > > -
> > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
> > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > > - { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
> > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > > + { .refclk = 19200, .cdclk = 172800, .ratio = 18 },
> > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > > + { .refclk = 19200, .cdclk = 326400, .ratio = 68 },
> > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > > +
> > > + { .refclk = 24000, .cdclk = 180000, .ratio = 15 },
> > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > > + { .refclk = 24000, .cdclk = 324000, .ratio = 54 },
> > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> > > +
> > > + { .refclk = 38400, .cdclk = 172800, .ratio = 9 },
> > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > > + { .refclk = 38400, .cdclk = 326400, .ratio = 34 },
> > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals rkl_cdclk_table[] = {
> > > - { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 },
> > > - { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 },
> > > - { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 },
> > > - { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
> > > - { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
> > > - { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },
> > > -
> > > - { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 },
> > > - { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 },
> > > - { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 },
> > > - { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
> > > - { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 },
> > > - { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },
> > > -
> > > - { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
> > > - { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
> > > - { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
> > > - { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
> > > - { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
> > > + { .refclk = 19200, .cdclk = 172800, .ratio = 36 },
> > > + { .refclk = 19200, .cdclk = 192000, .ratio = 40 },
> > > + { .refclk = 19200, .cdclk = 307200, .ratio = 64 },
> > > + { .refclk = 19200, .cdclk = 326400, .ratio = 136 },
> > > + { .refclk = 19200, .cdclk = 556800, .ratio = 116 },
> > > + { .refclk = 19200, .cdclk = 652800, .ratio = 136 },
> > > +
> > > + { .refclk = 24000, .cdclk = 180000, .ratio = 30 },
> > > + { .refclk = 24000, .cdclk = 192000, .ratio = 32 },
> > > + { .refclk = 24000, .cdclk = 312000, .ratio = 52 },
> > > + { .refclk = 24000, .cdclk = 324000, .ratio = 108 },
> > > + { .refclk = 24000, .cdclk = 552000, .ratio = 92 },
> > > + { .refclk = 24000, .cdclk = 648000, .ratio = 108 },
> > > +
> > > + { .refclk = 38400, .cdclk = 172800, .ratio = 18 },
> > > + { .refclk = 38400, .cdclk = 192000, .ratio = 20 },
> > > + { .refclk = 38400, .cdclk = 307200, .ratio = 32 },
> > > + { .refclk = 38400, .cdclk = 326400, .ratio = 68 },
> > > + { .refclk = 38400, .cdclk = 556800, .ratio = 58 },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 68 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
> > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > >
> > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > > - { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > > + { .refclk = 24400, .cdclk = 648000, .ratio = 54 },
> > >
> > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals adlp_cdclk_table[] = {
> > > - { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > > -
> > > - { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > > -
> > > - { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > > + { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
> > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > > +
> > > + { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
> > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> > > +
> > > + { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
> > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals rplu_cdclk_table[] = {
> > > - { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > > - { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
> > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > > -
> > > - { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > > - { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
> > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > > -
> > > - { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
> > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > > + { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
> > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > > + { .refclk = 19200, .cdclk = 480000, .ratio = 50 },
> > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > > +
> > > + { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
> > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > > + { .refclk = 24000, .cdclk = 480000, .ratio = 40 },
> > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> > > +
> > > + { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
> > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25 },
> > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals dg2_cdclk_table[] = {
> > > - { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
> > > - { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
> > > - { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 },
> > > - { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a },
> > > - { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa },
> > > - { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a },
> > > - { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 },
> > > - { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 },
> > > - { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee },
> > > - { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de },
> > > - { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
> > > - { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
> > > + { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
> > > + { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
> > > + { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
> > > + { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
> > > + { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
> > > + { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
> > > + { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
> > > + { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
> > > + { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
> > > + { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
> > > + { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
> > > + { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals mtl_cdclk_table[] = {
> > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
> > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
> > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
> > > + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
> > > + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
> > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
> > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
> > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals lnl_cdclk_table[] = {
> > > - { .refclk = 38400, .cdclk = 153600, .divider = 2, .ratio = 16, .waveform = 0xaaaa },
> > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> > > - { .refclk = 38400, .cdclk = 211200, .divider = 2, .ratio = 16, .waveform = 0xdbb6 },
> > > - { .refclk = 38400, .cdclk = 230400, .divider = 2, .ratio = 16, .waveform = 0xeeee },
> > > - { .refclk = 38400, .cdclk = 249600, .divider = 2, .ratio = 16, .waveform = 0xf7de },
> > > - { .refclk = 38400, .cdclk = 268800, .divider = 2, .ratio = 16, .waveform = 0xfefe },
> > > - { .refclk = 38400, .cdclk = 288000, .divider = 2, .ratio = 16, .waveform = 0xfffe },
> > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0xffff },
> > > - { .refclk = 38400, .cdclk = 330000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 },
> > > - { .refclk = 38400, .cdclk = 360000, .divider = 2, .ratio = 25, .waveform = 0xeeee },
> > > - { .refclk = 38400, .cdclk = 390000, .divider = 2, .ratio = 25, .waveform = 0xf7de },
> > > - { .refclk = 38400, .cdclk = 420000, .divider = 2, .ratio = 25, .waveform = 0xfefe },
> > > - { .refclk = 38400, .cdclk = 450000, .divider = 2, .ratio = 25, .waveform = 0xfffe },
> > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0xffff },
> > > - { .refclk = 38400, .cdclk = 487200, .divider = 2, .ratio = 29, .waveform = 0xfefe },
> > > - { .refclk = 38400, .cdclk = 522000, .divider = 2, .ratio = 29, .waveform = 0xfffe },
> > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0xffff },
> > > - { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
> > > - { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
> > > + { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
> > > + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
> > > + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
> > > + { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
> > > + { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
> > > + { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
> > > + { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
> > > + { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
> > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
> > > + { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
> > > + { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
> > > + { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
> > > + { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
> > > + { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
> > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
> > > + { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
> > > + { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
> > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
> > > + { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
> > > + { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
> > > {}
> > > };
> > >
> > > --
> > > 2.42.1
> > >
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/cdclk: Remove divider field from tables
2023-11-28 8:43 ` Ville Syrjälä
2023-11-28 8:53 ` Lisovskiy, Stanislav
@ 2023-11-28 9:01 ` Ville Syrjälä
2023-11-28 9:51 ` Ville Syrjälä
2 siblings, 0 replies; 14+ messages in thread
From: Ville Syrjälä @ 2023-11-28 9:01 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Tue, Nov 28, 2023 at 10:43:36AM +0200, Ville Syrjälä wrote:
> On Mon, Nov 27, 2023 at 08:21:46AM -0800, Matt Roper wrote:
> > On Fri, Nov 24, 2023 at 05:55:23PM -0300, Gustavo Sousa wrote:
> > > The cdclk tables were introduced with commit 736da8112fee ("drm/i915:
> > > Use literal representation of cdclk tables"). It has been almost 4 years
> > > and the divider field was not really used yet. Let's remove it.
> >
> > I think we need to go the other way and actually start using it instead
> > of (incorrectly) trying to re-derive it from cdclk->vco. The logic the
> > driver is using today doesn't account for the potential use of
> > squashing, which means we program the wrong divider value into CDCLK_CTL
> > in some cases. I pointed that out during the LNL code reviews a couple
> > months ago, and I believe Stan is working on fixing that.
>
> The code should be correct as is, but it does assume that the cd2x
> divider is 2 when squashing is used. If that no longer holds then we
> have to change something.
BTW long ago I wrote some patches to cross check all the values in the
table (since there is redundancy in what we store there), but I was
too annoyed at having to do that cross check at runtime that I didn't
send the patches out. I was slightly hopeful that C23 constexpr could
save us, but apparently constexpr for functions didn't end up in in
the spec, so likely not really useful :(
>
> >
> > I wonder if the misprogramming we're doing today is what requires the
> > "HACK" at the bottom of intel_crtc_compute_min_cdclk for DG2?
> >
> >
> > Matt
> >
> > >
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_cdclk.c | 269 ++++++++++-----------
> > > 1 file changed, 134 insertions(+), 135 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > index b93d1ad7936d..7f85a216ff5c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > @@ -1227,183 +1227,182 @@ struct intel_cdclk_vals {
> > > u32 cdclk;
> > > u16 refclk;
> > > u16 waveform;
> > > - u8 divider; /* CD2X divider * 2 */
> > > u8 ratio;
> > > };
> > >
> > > static const struct intel_cdclk_vals bxt_cdclk_table[] = {
> > > - { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
> > > - { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
> > > - { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
> > > - { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
> > > - { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
> > > + { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
> > > + { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
> > > + { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
> > > + { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
> > > + { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals glk_cdclk_table[] = {
> > > - { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
> > > - { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
> > > - { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
> > > + { .refclk = 19200, .cdclk = 79200, .ratio = 33 },
> > > + { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
> > > + { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals icl_cdclk_table[] = {
> > > - { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
> > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > > - { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
> > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > > -
> > > - { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
> > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > > - { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
> > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > > -
> > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
> > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > > - { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
> > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > > + { .refclk = 19200, .cdclk = 172800, .ratio = 18 },
> > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > > + { .refclk = 19200, .cdclk = 326400, .ratio = 68 },
> > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > > +
> > > + { .refclk = 24000, .cdclk = 180000, .ratio = 15 },
> > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > > + { .refclk = 24000, .cdclk = 324000, .ratio = 54 },
> > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> > > +
> > > + { .refclk = 38400, .cdclk = 172800, .ratio = 9 },
> > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > > + { .refclk = 38400, .cdclk = 326400, .ratio = 34 },
> > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals rkl_cdclk_table[] = {
> > > - { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 },
> > > - { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 },
> > > - { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 },
> > > - { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
> > > - { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
> > > - { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },
> > > -
> > > - { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 },
> > > - { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 },
> > > - { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 },
> > > - { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
> > > - { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 },
> > > - { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },
> > > -
> > > - { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
> > > - { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
> > > - { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
> > > - { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
> > > - { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
> > > + { .refclk = 19200, .cdclk = 172800, .ratio = 36 },
> > > + { .refclk = 19200, .cdclk = 192000, .ratio = 40 },
> > > + { .refclk = 19200, .cdclk = 307200, .ratio = 64 },
> > > + { .refclk = 19200, .cdclk = 326400, .ratio = 136 },
> > > + { .refclk = 19200, .cdclk = 556800, .ratio = 116 },
> > > + { .refclk = 19200, .cdclk = 652800, .ratio = 136 },
> > > +
> > > + { .refclk = 24000, .cdclk = 180000, .ratio = 30 },
> > > + { .refclk = 24000, .cdclk = 192000, .ratio = 32 },
> > > + { .refclk = 24000, .cdclk = 312000, .ratio = 52 },
> > > + { .refclk = 24000, .cdclk = 324000, .ratio = 108 },
> > > + { .refclk = 24000, .cdclk = 552000, .ratio = 92 },
> > > + { .refclk = 24000, .cdclk = 648000, .ratio = 108 },
> > > +
> > > + { .refclk = 38400, .cdclk = 172800, .ratio = 18 },
> > > + { .refclk = 38400, .cdclk = 192000, .ratio = 20 },
> > > + { .refclk = 38400, .cdclk = 307200, .ratio = 32 },
> > > + { .refclk = 38400, .cdclk = 326400, .ratio = 68 },
> > > + { .refclk = 38400, .cdclk = 556800, .ratio = 58 },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 68 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
> > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > >
> > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > > - { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > > + { .refclk = 24400, .cdclk = 648000, .ratio = 54 },
> > >
> > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals adlp_cdclk_table[] = {
> > > - { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > > -
> > > - { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > > -
> > > - { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > > + { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
> > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > > +
> > > + { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
> > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> > > +
> > > + { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
> > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals rplu_cdclk_table[] = {
> > > - { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > > - { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
> > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > > -
> > > - { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > > - { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
> > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > > -
> > > - { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
> > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > > + { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
> > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > > + { .refclk = 19200, .cdclk = 480000, .ratio = 50 },
> > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > > +
> > > + { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
> > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > > + { .refclk = 24000, .cdclk = 480000, .ratio = 40 },
> > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> > > +
> > > + { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
> > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25 },
> > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals dg2_cdclk_table[] = {
> > > - { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
> > > - { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
> > > - { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 },
> > > - { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a },
> > > - { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa },
> > > - { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a },
> > > - { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 },
> > > - { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 },
> > > - { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee },
> > > - { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de },
> > > - { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
> > > - { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
> > > + { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
> > > + { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
> > > + { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
> > > + { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
> > > + { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
> > > + { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
> > > + { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
> > > + { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
> > > + { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
> > > + { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
> > > + { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
> > > + { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals mtl_cdclk_table[] = {
> > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
> > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
> > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
> > > + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
> > > + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
> > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
> > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
> > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals lnl_cdclk_table[] = {
> > > - { .refclk = 38400, .cdclk = 153600, .divider = 2, .ratio = 16, .waveform = 0xaaaa },
> > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> > > - { .refclk = 38400, .cdclk = 211200, .divider = 2, .ratio = 16, .waveform = 0xdbb6 },
> > > - { .refclk = 38400, .cdclk = 230400, .divider = 2, .ratio = 16, .waveform = 0xeeee },
> > > - { .refclk = 38400, .cdclk = 249600, .divider = 2, .ratio = 16, .waveform = 0xf7de },
> > > - { .refclk = 38400, .cdclk = 268800, .divider = 2, .ratio = 16, .waveform = 0xfefe },
> > > - { .refclk = 38400, .cdclk = 288000, .divider = 2, .ratio = 16, .waveform = 0xfffe },
> > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0xffff },
> > > - { .refclk = 38400, .cdclk = 330000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 },
> > > - { .refclk = 38400, .cdclk = 360000, .divider = 2, .ratio = 25, .waveform = 0xeeee },
> > > - { .refclk = 38400, .cdclk = 390000, .divider = 2, .ratio = 25, .waveform = 0xf7de },
> > > - { .refclk = 38400, .cdclk = 420000, .divider = 2, .ratio = 25, .waveform = 0xfefe },
> > > - { .refclk = 38400, .cdclk = 450000, .divider = 2, .ratio = 25, .waveform = 0xfffe },
> > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0xffff },
> > > - { .refclk = 38400, .cdclk = 487200, .divider = 2, .ratio = 29, .waveform = 0xfefe },
> > > - { .refclk = 38400, .cdclk = 522000, .divider = 2, .ratio = 29, .waveform = 0xfffe },
> > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0xffff },
> > > - { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
> > > - { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
> > > + { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
> > > + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
> > > + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
> > > + { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
> > > + { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
> > > + { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
> > > + { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
> > > + { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
> > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
> > > + { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
> > > + { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
> > > + { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
> > > + { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
> > > + { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
> > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
> > > + { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
> > > + { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
> > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
> > > + { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
> > > + { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
> > > {}
> > > };
> > >
> > > --
> > > 2.42.1
> > >
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation
>
> --
> Ville Syrjälä
> Intel
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/cdclk: Remove divider field from tables
2023-11-28 8:43 ` Ville Syrjälä
2023-11-28 8:53 ` Lisovskiy, Stanislav
2023-11-28 9:01 ` Ville Syrjälä
@ 2023-11-28 9:51 ` Ville Syrjälä
2023-11-28 11:52 ` Ville Syrjälä
2023-12-01 23:07 ` Matt Roper
2 siblings, 2 replies; 14+ messages in thread
From: Ville Syrjälä @ 2023-11-28 9:51 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Tue, Nov 28, 2023 at 10:43:36AM +0200, Ville Syrjälä wrote:
> On Mon, Nov 27, 2023 at 08:21:46AM -0800, Matt Roper wrote:
> > On Fri, Nov 24, 2023 at 05:55:23PM -0300, Gustavo Sousa wrote:
> > > The cdclk tables were introduced with commit 736da8112fee ("drm/i915:
> > > Use literal representation of cdclk tables"). It has been almost 4 years
> > > and the divider field was not really used yet. Let's remove it.
> >
> > I think we need to go the other way and actually start using it instead
> > of (incorrectly) trying to re-derive it from cdclk->vco. The logic the
> > driver is using today doesn't account for the potential use of
> > squashing, which means we program the wrong divider value into CDCLK_CTL
> > in some cases. I pointed that out during the LNL code reviews a couple
> > months ago, and I believe Stan is working on fixing that.
>
> The code should be correct as is, but it does assume that the cd2x
> divider is 2 when squashing is used. If that no longer holds then we
> have to change something.
Something like this should be sufficient to eliminate that
assumption.
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 8bb6bab7c8cd..58567d42e725 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1897,10 +1897,7 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
waveform = cdclk_squash_waveform(dev_priv, cdclk);
- if (waveform)
- clock = vco / 2;
- else
- clock = cdclk;
+ clock = DIV_ROUND_CLOSEST(cdclk * 16, cdclk_squash_divider(waveform));
if (HAS_CDCLK_SQUASH(dev_priv))
dg2_cdclk_squash_program(dev_priv, waveform);
>
> >
> > I wonder if the misprogramming we're doing today is what requires the
> > "HACK" at the bottom of intel_crtc_compute_min_cdclk for DG2?
> >
> >
> > Matt
> >
> > >
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_cdclk.c | 269 ++++++++++-----------
> > > 1 file changed, 134 insertions(+), 135 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > index b93d1ad7936d..7f85a216ff5c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > @@ -1227,183 +1227,182 @@ struct intel_cdclk_vals {
> > > u32 cdclk;
> > > u16 refclk;
> > > u16 waveform;
> > > - u8 divider; /* CD2X divider * 2 */
> > > u8 ratio;
> > > };
> > >
> > > static const struct intel_cdclk_vals bxt_cdclk_table[] = {
> > > - { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
> > > - { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
> > > - { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
> > > - { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
> > > - { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
> > > + { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
> > > + { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
> > > + { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
> > > + { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
> > > + { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals glk_cdclk_table[] = {
> > > - { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
> > > - { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
> > > - { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
> > > + { .refclk = 19200, .cdclk = 79200, .ratio = 33 },
> > > + { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
> > > + { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals icl_cdclk_table[] = {
> > > - { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
> > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > > - { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
> > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > > -
> > > - { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
> > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > > - { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
> > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > > -
> > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
> > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > > - { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
> > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > > + { .refclk = 19200, .cdclk = 172800, .ratio = 18 },
> > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > > + { .refclk = 19200, .cdclk = 326400, .ratio = 68 },
> > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > > +
> > > + { .refclk = 24000, .cdclk = 180000, .ratio = 15 },
> > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > > + { .refclk = 24000, .cdclk = 324000, .ratio = 54 },
> > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> > > +
> > > + { .refclk = 38400, .cdclk = 172800, .ratio = 9 },
> > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > > + { .refclk = 38400, .cdclk = 326400, .ratio = 34 },
> > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals rkl_cdclk_table[] = {
> > > - { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 },
> > > - { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 },
> > > - { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 },
> > > - { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
> > > - { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
> > > - { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },
> > > -
> > > - { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 },
> > > - { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 },
> > > - { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 },
> > > - { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
> > > - { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 },
> > > - { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },
> > > -
> > > - { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
> > > - { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
> > > - { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
> > > - { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
> > > - { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
> > > + { .refclk = 19200, .cdclk = 172800, .ratio = 36 },
> > > + { .refclk = 19200, .cdclk = 192000, .ratio = 40 },
> > > + { .refclk = 19200, .cdclk = 307200, .ratio = 64 },
> > > + { .refclk = 19200, .cdclk = 326400, .ratio = 136 },
> > > + { .refclk = 19200, .cdclk = 556800, .ratio = 116 },
> > > + { .refclk = 19200, .cdclk = 652800, .ratio = 136 },
> > > +
> > > + { .refclk = 24000, .cdclk = 180000, .ratio = 30 },
> > > + { .refclk = 24000, .cdclk = 192000, .ratio = 32 },
> > > + { .refclk = 24000, .cdclk = 312000, .ratio = 52 },
> > > + { .refclk = 24000, .cdclk = 324000, .ratio = 108 },
> > > + { .refclk = 24000, .cdclk = 552000, .ratio = 92 },
> > > + { .refclk = 24000, .cdclk = 648000, .ratio = 108 },
> > > +
> > > + { .refclk = 38400, .cdclk = 172800, .ratio = 18 },
> > > + { .refclk = 38400, .cdclk = 192000, .ratio = 20 },
> > > + { .refclk = 38400, .cdclk = 307200, .ratio = 32 },
> > > + { .refclk = 38400, .cdclk = 326400, .ratio = 68 },
> > > + { .refclk = 38400, .cdclk = 556800, .ratio = 58 },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 68 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
> > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > >
> > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > > - { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > > + { .refclk = 24400, .cdclk = 648000, .ratio = 54 },
> > >
> > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals adlp_cdclk_table[] = {
> > > - { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > > -
> > > - { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > > -
> > > - { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > > + { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
> > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > > +
> > > + { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
> > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> > > +
> > > + { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
> > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals rplu_cdclk_table[] = {
> > > - { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > > - { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
> > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > > -
> > > - { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > > - { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
> > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > > -
> > > - { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
> > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > > + { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
> > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > > + { .refclk = 19200, .cdclk = 480000, .ratio = 50 },
> > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > > +
> > > + { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
> > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > > + { .refclk = 24000, .cdclk = 480000, .ratio = 40 },
> > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> > > +
> > > + { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
> > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25 },
> > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals dg2_cdclk_table[] = {
> > > - { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
> > > - { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
> > > - { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 },
> > > - { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a },
> > > - { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa },
> > > - { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a },
> > > - { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 },
> > > - { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 },
> > > - { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee },
> > > - { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de },
> > > - { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
> > > - { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
> > > + { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
> > > + { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
> > > + { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
> > > + { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
> > > + { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
> > > + { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
> > > + { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
> > > + { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
> > > + { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
> > > + { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
> > > + { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
> > > + { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals mtl_cdclk_table[] = {
> > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
> > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
> > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
> > > + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
> > > + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
> > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
> > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
> > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
> > > {}
> > > };
> > >
> > > static const struct intel_cdclk_vals lnl_cdclk_table[] = {
> > > - { .refclk = 38400, .cdclk = 153600, .divider = 2, .ratio = 16, .waveform = 0xaaaa },
> > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> > > - { .refclk = 38400, .cdclk = 211200, .divider = 2, .ratio = 16, .waveform = 0xdbb6 },
> > > - { .refclk = 38400, .cdclk = 230400, .divider = 2, .ratio = 16, .waveform = 0xeeee },
> > > - { .refclk = 38400, .cdclk = 249600, .divider = 2, .ratio = 16, .waveform = 0xf7de },
> > > - { .refclk = 38400, .cdclk = 268800, .divider = 2, .ratio = 16, .waveform = 0xfefe },
> > > - { .refclk = 38400, .cdclk = 288000, .divider = 2, .ratio = 16, .waveform = 0xfffe },
> > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0xffff },
> > > - { .refclk = 38400, .cdclk = 330000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 },
> > > - { .refclk = 38400, .cdclk = 360000, .divider = 2, .ratio = 25, .waveform = 0xeeee },
> > > - { .refclk = 38400, .cdclk = 390000, .divider = 2, .ratio = 25, .waveform = 0xf7de },
> > > - { .refclk = 38400, .cdclk = 420000, .divider = 2, .ratio = 25, .waveform = 0xfefe },
> > > - { .refclk = 38400, .cdclk = 450000, .divider = 2, .ratio = 25, .waveform = 0xfffe },
> > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0xffff },
> > > - { .refclk = 38400, .cdclk = 487200, .divider = 2, .ratio = 29, .waveform = 0xfefe },
> > > - { .refclk = 38400, .cdclk = 522000, .divider = 2, .ratio = 29, .waveform = 0xfffe },
> > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0xffff },
> > > - { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
> > > - { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
> > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
> > > + { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
> > > + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
> > > + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
> > > + { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
> > > + { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
> > > + { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
> > > + { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
> > > + { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
> > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
> > > + { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
> > > + { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
> > > + { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
> > > + { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
> > > + { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
> > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
> > > + { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
> > > + { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
> > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
> > > + { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
> > > + { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
> > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
> > > {}
> > > };
> > >
> > > --
> > > 2.42.1
> > >
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation
>
> --
> Ville Syrjälä
> Intel
--
Ville Syrjälä
Intel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/cdclk: Remove divider field from tables
2023-11-28 9:51 ` Ville Syrjälä
@ 2023-11-28 11:52 ` Ville Syrjälä
2023-12-01 23:07 ` Matt Roper
1 sibling, 0 replies; 14+ messages in thread
From: Ville Syrjälä @ 2023-11-28 11:52 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Tue, Nov 28, 2023 at 11:51:43AM +0200, Ville Syrjälä wrote:
> On Tue, Nov 28, 2023 at 10:43:36AM +0200, Ville Syrjälä wrote:
> > On Mon, Nov 27, 2023 at 08:21:46AM -0800, Matt Roper wrote:
> > > On Fri, Nov 24, 2023 at 05:55:23PM -0300, Gustavo Sousa wrote:
> > > > The cdclk tables were introduced with commit 736da8112fee ("drm/i915:
> > > > Use literal representation of cdclk tables"). It has been almost 4 years
> > > > and the divider field was not really used yet. Let's remove it.
> > >
> > > I think we need to go the other way and actually start using it instead
> > > of (incorrectly) trying to re-derive it from cdclk->vco. The logic the
> > > driver is using today doesn't account for the potential use of
> > > squashing, which means we program the wrong divider value into CDCLK_CTL
> > > in some cases. I pointed that out during the LNL code reviews a couple
> > > months ago, and I believe Stan is working on fixing that.
> >
> > The code should be correct as is, but it does assume that the cd2x
> > divider is 2 when squashing is used. If that no longer holds then we
> > have to change something.
>
> Something like this should be sufficient to eliminate that
> assumption.
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 8bb6bab7c8cd..58567d42e725 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1897,10 +1897,7 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
>
> waveform = cdclk_squash_waveform(dev_priv, cdclk);
>
> - if (waveform)
> - clock = vco / 2;
> - else
> - clock = cdclk;
> + clock = DIV_ROUND_CLOSEST(cdclk * 16, cdclk_squash_divider(waveform));
>
> if (HAS_CDCLK_SQUASH(dev_priv))
> dg2_cdclk_squash_program(dev_priv, waveform);
Sent that, and a bunch of other cdclk stuff as a proper series to the
list.
>
> >
> > >
> > > I wonder if the misprogramming we're doing today is what requires the
> > > "HACK" at the bottom of intel_crtc_compute_min_cdclk for DG2?
> > >
> > >
> > > Matt
> > >
> > > >
> > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_cdclk.c | 269 ++++++++++-----------
> > > > 1 file changed, 134 insertions(+), 135 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > > index b93d1ad7936d..7f85a216ff5c 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > > @@ -1227,183 +1227,182 @@ struct intel_cdclk_vals {
> > > > u32 cdclk;
> > > > u16 refclk;
> > > > u16 waveform;
> > > > - u8 divider; /* CD2X divider * 2 */
> > > > u8 ratio;
> > > > };
> > > >
> > > > static const struct intel_cdclk_vals bxt_cdclk_table[] = {
> > > > - { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
> > > > - { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
> > > > - { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
> > > > - { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
> > > > - { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
> > > > + { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
> > > > + { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
> > > > + { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
> > > > + { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
> > > > + { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
> > > > {}
> > > > };
> > > >
> > > > static const struct intel_cdclk_vals glk_cdclk_table[] = {
> > > > - { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
> > > > - { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
> > > > - { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
> > > > + { .refclk = 19200, .cdclk = 79200, .ratio = 33 },
> > > > + { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
> > > > + { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
> > > > {}
> > > > };
> > > >
> > > > static const struct intel_cdclk_vals icl_cdclk_table[] = {
> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > > > - { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > > > -
> > > > - { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > > > - { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > > > -
> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > > > - { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 18 },
> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > > > + { .refclk = 19200, .cdclk = 326400, .ratio = 68 },
> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > > > +
> > > > + { .refclk = 24000, .cdclk = 180000, .ratio = 15 },
> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > > > + { .refclk = 24000, .cdclk = 324000, .ratio = 54 },
> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> > > > +
> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 9 },
> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > > > + { .refclk = 38400, .cdclk = 326400, .ratio = 34 },
> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > > > {}
> > > > };
> > > >
> > > > static const struct intel_cdclk_vals rkl_cdclk_table[] = {
> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 },
> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 },
> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 },
> > > > - { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },
> > > > -
> > > > - { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 },
> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 },
> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 },
> > > > - { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 },
> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },
> > > > -
> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
> > > > - { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 36 },
> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 40 },
> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 64 },
> > > > + { .refclk = 19200, .cdclk = 326400, .ratio = 136 },
> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 116 },
> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 136 },
> > > > +
> > > > + { .refclk = 24000, .cdclk = 180000, .ratio = 30 },
> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 32 },
> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 52 },
> > > > + { .refclk = 24000, .cdclk = 324000, .ratio = 108 },
> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 92 },
> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 108 },
> > > > +
> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 18 },
> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 20 },
> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 32 },
> > > > + { .refclk = 38400, .cdclk = 326400, .ratio = 68 },
> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 58 },
> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 68 },
> > > > {}
> > > > };
> > > >
> > > > static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > > >
> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > > > - { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > > > + { .refclk = 24400, .cdclk = 648000, .ratio = 54 },
> > > >
> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > > > {}
> > > > };
> > > >
> > > > static const struct intel_cdclk_vals adlp_cdclk_table[] = {
> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > > > -
> > > > - { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > > > -
> > > > - { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > > > +
> > > > + { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> > > > +
> > > > + { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > > > {}
> > > > };
> > > >
> > > > static const struct intel_cdclk_vals rplu_cdclk_table[] = {
> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > > > - { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > > > -
> > > > - { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > > > - { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > > > -
> > > > - { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > > > + { .refclk = 19200, .cdclk = 480000, .ratio = 50 },
> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > > > +
> > > > + { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > > > + { .refclk = 24000, .cdclk = 480000, .ratio = 40 },
> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> > > > +
> > > > + { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25 },
> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > > > {}
> > > > };
> > > >
> > > > static const struct intel_cdclk_vals dg2_cdclk_table[] = {
> > > > - { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
> > > > - { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
> > > > - { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 },
> > > > - { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a },
> > > > - { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa },
> > > > - { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a },
> > > > - { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 },
> > > > - { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 },
> > > > - { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee },
> > > > - { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de },
> > > > - { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
> > > > - { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
> > > > + { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
> > > > + { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
> > > > + { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
> > > > + { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
> > > > + { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
> > > > + { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
> > > > + { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
> > > > + { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
> > > > + { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
> > > > + { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
> > > > + { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
> > > > + { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
> > > > {}
> > > > };
> > > >
> > > > static const struct intel_cdclk_vals mtl_cdclk_table[] = {
> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
> > > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
> > > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
> > > > {}
> > > > };
> > > >
> > > > static const struct intel_cdclk_vals lnl_cdclk_table[] = {
> > > > - { .refclk = 38400, .cdclk = 153600, .divider = 2, .ratio = 16, .waveform = 0xaaaa },
> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> > > > - { .refclk = 38400, .cdclk = 211200, .divider = 2, .ratio = 16, .waveform = 0xdbb6 },
> > > > - { .refclk = 38400, .cdclk = 230400, .divider = 2, .ratio = 16, .waveform = 0xeeee },
> > > > - { .refclk = 38400, .cdclk = 249600, .divider = 2, .ratio = 16, .waveform = 0xf7de },
> > > > - { .refclk = 38400, .cdclk = 268800, .divider = 2, .ratio = 16, .waveform = 0xfefe },
> > > > - { .refclk = 38400, .cdclk = 288000, .divider = 2, .ratio = 16, .waveform = 0xfffe },
> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0xffff },
> > > > - { .refclk = 38400, .cdclk = 330000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 },
> > > > - { .refclk = 38400, .cdclk = 360000, .divider = 2, .ratio = 25, .waveform = 0xeeee },
> > > > - { .refclk = 38400, .cdclk = 390000, .divider = 2, .ratio = 25, .waveform = 0xf7de },
> > > > - { .refclk = 38400, .cdclk = 420000, .divider = 2, .ratio = 25, .waveform = 0xfefe },
> > > > - { .refclk = 38400, .cdclk = 450000, .divider = 2, .ratio = 25, .waveform = 0xfffe },
> > > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0xffff },
> > > > - { .refclk = 38400, .cdclk = 487200, .divider = 2, .ratio = 29, .waveform = 0xfefe },
> > > > - { .refclk = 38400, .cdclk = 522000, .divider = 2, .ratio = 29, .waveform = 0xfffe },
> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0xffff },
> > > > - { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
> > > > - { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
> > > > + { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
> > > > + { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
> > > > + { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
> > > > + { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
> > > > + { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
> > > > + { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
> > > > + { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
> > > > + { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
> > > > + { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
> > > > + { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
> > > > + { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
> > > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
> > > > + { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
> > > > + { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
> > > > + { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
> > > > + { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
> > > > {}
> > > > };
> > > >
> > > > --
> > > > 2.42.1
> > > >
> > >
> > > --
> > > Matt Roper
> > > Graphics Software Engineer
> > > Linux GPU Platform Enablement
> > > Intel Corporation
> >
> > --
> > Ville Syrjälä
> > Intel
>
> --
> Ville Syrjälä
> Intel
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/cdclk: Remove divider field from tables
2023-11-28 9:51 ` Ville Syrjälä
2023-11-28 11:52 ` Ville Syrjälä
@ 2023-12-01 23:07 ` Matt Roper
2023-12-04 14:04 ` Gustavo Sousa
1 sibling, 1 reply; 14+ messages in thread
From: Matt Roper @ 2023-12-01 23:07 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, Nov 28, 2023 at 11:51:43AM +0200, Ville Syrjälä wrote:
> On Tue, Nov 28, 2023 at 10:43:36AM +0200, Ville Syrjälä wrote:
> > On Mon, Nov 27, 2023 at 08:21:46AM -0800, Matt Roper wrote:
> > > On Fri, Nov 24, 2023 at 05:55:23PM -0300, Gustavo Sousa wrote:
> > > > The cdclk tables were introduced with commit 736da8112fee ("drm/i915:
> > > > Use literal representation of cdclk tables"). It has been almost 4 years
> > > > and the divider field was not really used yet. Let's remove it.
> > >
> > > I think we need to go the other way and actually start using it instead
> > > of (incorrectly) trying to re-derive it from cdclk->vco. The logic the
> > > driver is using today doesn't account for the potential use of
> > > squashing, which means we program the wrong divider value into CDCLK_CTL
> > > in some cases. I pointed that out during the LNL code reviews a couple
> > > months ago, and I believe Stan is working on fixing that.
> >
> > The code should be correct as is, but it does assume that the cd2x
> > divider is 2 when squashing is used. If that no longer holds then we
> > have to change something.
>
> Something like this should be sufficient to eliminate that
> assumption.
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 8bb6bab7c8cd..58567d42e725 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1897,10 +1897,7 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
>
> waveform = cdclk_squash_waveform(dev_priv, cdclk);
>
> - if (waveform)
> - clock = vco / 2;
> - else
> - clock = cdclk;
> + clock = DIV_ROUND_CLOSEST(cdclk * 16, cdclk_squash_divider(waveform));
>
I haven't had time to come back and revisit this (or check your new
series yet), but when I was reviewing the cdclk stuff a couple months
ago, my concern was around bxt_cdclk_cd2x_div_sel() which is deriving
the CD2X divider from the vco and cdclk value. On a platform like DG2,
we use squashing instead of changes to PLL ratio to hit different cdclk
values, so the calculation there doesn't seem valid anymore. Am I
overlooking something?
Matt
> if (HAS_CDCLK_SQUASH(dev_priv))
> dg2_cdclk_squash_program(dev_priv, waveform);
>
> >
> > >
> > > I wonder if the misprogramming we're doing today is what requires the
> > > "HACK" at the bottom of intel_crtc_compute_min_cdclk for DG2?
> > >
> > >
> > > Matt
> > >
> > > >
> > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_cdclk.c | 269 ++++++++++-----------
> > > > 1 file changed, 134 insertions(+), 135 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > > index b93d1ad7936d..7f85a216ff5c 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > > @@ -1227,183 +1227,182 @@ struct intel_cdclk_vals {
> > > > u32 cdclk;
> > > > u16 refclk;
> > > > u16 waveform;
> > > > - u8 divider; /* CD2X divider * 2 */
> > > > u8 ratio;
> > > > };
> > > >
> > > > static const struct intel_cdclk_vals bxt_cdclk_table[] = {
> > > > - { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
> > > > - { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
> > > > - { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
> > > > - { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
> > > > - { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
> > > > + { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
> > > > + { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
> > > > + { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
> > > > + { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
> > > > + { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
> > > > {}
> > > > };
> > > >
> > > > static const struct intel_cdclk_vals glk_cdclk_table[] = {
> > > > - { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
> > > > - { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
> > > > - { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
> > > > + { .refclk = 19200, .cdclk = 79200, .ratio = 33 },
> > > > + { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
> > > > + { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
> > > > {}
> > > > };
> > > >
> > > > static const struct intel_cdclk_vals icl_cdclk_table[] = {
> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > > > - { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > > > -
> > > > - { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > > > - { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > > > -
> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > > > - { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 18 },
> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > > > + { .refclk = 19200, .cdclk = 326400, .ratio = 68 },
> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > > > +
> > > > + { .refclk = 24000, .cdclk = 180000, .ratio = 15 },
> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > > > + { .refclk = 24000, .cdclk = 324000, .ratio = 54 },
> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> > > > +
> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 9 },
> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > > > + { .refclk = 38400, .cdclk = 326400, .ratio = 34 },
> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > > > {}
> > > > };
> > > >
> > > > static const struct intel_cdclk_vals rkl_cdclk_table[] = {
> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 },
> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 },
> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 },
> > > > - { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },
> > > > -
> > > > - { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 },
> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 },
> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 },
> > > > - { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 },
> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },
> > > > -
> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
> > > > - { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 36 },
> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 40 },
> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 64 },
> > > > + { .refclk = 19200, .cdclk = 326400, .ratio = 136 },
> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 116 },
> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 136 },
> > > > +
> > > > + { .refclk = 24000, .cdclk = 180000, .ratio = 30 },
> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 32 },
> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 52 },
> > > > + { .refclk = 24000, .cdclk = 324000, .ratio = 108 },
> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 92 },
> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 108 },
> > > > +
> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 18 },
> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 20 },
> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 32 },
> > > > + { .refclk = 38400, .cdclk = 326400, .ratio = 68 },
> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 58 },
> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 68 },
> > > > {}
> > > > };
> > > >
> > > > static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > > >
> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > > > - { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > > > + { .refclk = 24400, .cdclk = 648000, .ratio = 54 },
> > > >
> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > > > {}
> > > > };
> > > >
> > > > static const struct intel_cdclk_vals adlp_cdclk_table[] = {
> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > > > -
> > > > - { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > > > -
> > > > - { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > > > +
> > > > + { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> > > > +
> > > > + { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > > > {}
> > > > };
> > > >
> > > > static const struct intel_cdclk_vals rplu_cdclk_table[] = {
> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > > > - { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > > > -
> > > > - { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > > > - { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > > > -
> > > > - { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > > > + { .refclk = 19200, .cdclk = 480000, .ratio = 50 },
> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > > > +
> > > > + { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > > > + { .refclk = 24000, .cdclk = 480000, .ratio = 40 },
> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> > > > +
> > > > + { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25 },
> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > > > {}
> > > > };
> > > >
> > > > static const struct intel_cdclk_vals dg2_cdclk_table[] = {
> > > > - { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
> > > > - { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
> > > > - { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 },
> > > > - { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a },
> > > > - { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa },
> > > > - { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a },
> > > > - { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 },
> > > > - { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 },
> > > > - { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee },
> > > > - { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de },
> > > > - { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
> > > > - { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
> > > > + { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
> > > > + { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
> > > > + { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
> > > > + { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
> > > > + { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
> > > > + { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
> > > > + { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
> > > > + { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
> > > > + { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
> > > > + { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
> > > > + { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
> > > > + { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
> > > > {}
> > > > };
> > > >
> > > > static const struct intel_cdclk_vals mtl_cdclk_table[] = {
> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
> > > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
> > > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
> > > > {}
> > > > };
> > > >
> > > > static const struct intel_cdclk_vals lnl_cdclk_table[] = {
> > > > - { .refclk = 38400, .cdclk = 153600, .divider = 2, .ratio = 16, .waveform = 0xaaaa },
> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> > > > - { .refclk = 38400, .cdclk = 211200, .divider = 2, .ratio = 16, .waveform = 0xdbb6 },
> > > > - { .refclk = 38400, .cdclk = 230400, .divider = 2, .ratio = 16, .waveform = 0xeeee },
> > > > - { .refclk = 38400, .cdclk = 249600, .divider = 2, .ratio = 16, .waveform = 0xf7de },
> > > > - { .refclk = 38400, .cdclk = 268800, .divider = 2, .ratio = 16, .waveform = 0xfefe },
> > > > - { .refclk = 38400, .cdclk = 288000, .divider = 2, .ratio = 16, .waveform = 0xfffe },
> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0xffff },
> > > > - { .refclk = 38400, .cdclk = 330000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 },
> > > > - { .refclk = 38400, .cdclk = 360000, .divider = 2, .ratio = 25, .waveform = 0xeeee },
> > > > - { .refclk = 38400, .cdclk = 390000, .divider = 2, .ratio = 25, .waveform = 0xf7de },
> > > > - { .refclk = 38400, .cdclk = 420000, .divider = 2, .ratio = 25, .waveform = 0xfefe },
> > > > - { .refclk = 38400, .cdclk = 450000, .divider = 2, .ratio = 25, .waveform = 0xfffe },
> > > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0xffff },
> > > > - { .refclk = 38400, .cdclk = 487200, .divider = 2, .ratio = 29, .waveform = 0xfefe },
> > > > - { .refclk = 38400, .cdclk = 522000, .divider = 2, .ratio = 29, .waveform = 0xfffe },
> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0xffff },
> > > > - { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
> > > > - { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
> > > > + { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
> > > > + { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
> > > > + { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
> > > > + { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
> > > > + { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
> > > > + { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
> > > > + { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
> > > > + { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
> > > > + { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
> > > > + { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
> > > > + { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
> > > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
> > > > + { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
> > > > + { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
> > > > + { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
> > > > + { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
> > > > {}
> > > > };
> > > >
> > > > --
> > > > 2.42.1
> > > >
> > >
> > > --
> > > Matt Roper
> > > Graphics Software Engineer
> > > Linux GPU Platform Enablement
> > > Intel Corporation
> >
> > --
> > Ville Syrjälä
> > Intel
>
> --
> Ville Syrjälä
> Intel
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/cdclk: Remove divider field from tables
2023-12-01 23:07 ` Matt Roper
@ 2023-12-04 14:04 ` Gustavo Sousa
2023-12-04 14:13 ` Gustavo Sousa
0 siblings, 1 reply; 14+ messages in thread
From: Gustavo Sousa @ 2023-12-04 14:04 UTC (permalink / raw)
To: Matt Roper, Ville Syrjälä; +Cc: intel-gfx
Quoting Matt Roper (2023-12-01 20:07:48-03:00)
>On Tue, Nov 28, 2023 at 11:51:43AM +0200, Ville Syrjälä wrote:
>> On Tue, Nov 28, 2023 at 10:43:36AM +0200, Ville Syrjälä wrote:
>> > On Mon, Nov 27, 2023 at 08:21:46AM -0800, Matt Roper wrote:
>> > > On Fri, Nov 24, 2023 at 05:55:23PM -0300, Gustavo Sousa wrote:
>> > > > The cdclk tables were introduced with commit 736da8112fee ("drm/i915:
>> > > > Use literal representation of cdclk tables"). It has been almost 4 years
>> > > > and the divider field was not really used yet. Let's remove it.
>> > >
>> > > I think we need to go the other way and actually start using it instead
>> > > of (incorrectly) trying to re-derive it from cdclk->vco. The logic the
>> > > driver is using today doesn't account for the potential use of
>> > > squashing, which means we program the wrong divider value into CDCLK_CTL
>> > > in some cases. I pointed that out during the LNL code reviews a couple
>> > > months ago, and I believe Stan is working on fixing that.
>> >
>> > The code should be correct as is, but it does assume that the cd2x
>> > divider is 2 when squashing is used. If that no longer holds then we
>> > have to change something.
>>
>> Something like this should be sufficient to eliminate that
>> assumption.
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index 8bb6bab7c8cd..58567d42e725 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -1897,10 +1897,7 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
>>
>> waveform = cdclk_squash_waveform(dev_priv, cdclk);
>>
>> - if (waveform)
>> - clock = vco / 2;
>> - else
>> - clock = cdclk;
>> + clock = DIV_ROUND_CLOSEST(cdclk * 16, cdclk_squash_divider(waveform));
>>
>
>I haven't had time to come back and revisit this (or check your new
>series yet), but when I was reviewing the cdclk stuff a couple months
>ago, my concern was around bxt_cdclk_cd2x_div_sel() which is deriving
>the CD2X divider from the vco and cdclk value. On a platform like DG2,
>we use squashing instead of changes to PLL ratio to hit different cdclk
>values, so the calculation there doesn't seem valid anymore. Am I
>overlooking something?
I looked at Ville's patches and they seem correct to me - althought I'm
not that experienced and might be missing something as well... Here goes
my rationale:
Looking at how cdclk works with our hardware, I would say that the
cdclock is defined by:
cdclk = vco / div / sq_div / 2
, with: vco being the output of the CD2X PLL; "div", the CD2X divider;
"sq_div", the divider that is derived from the squash wave (16 / "sqash
wave 1's count"); and 2, the final division that is done at the end.
The DIV_ROUND_CLOSEST() operation suggested above is equivalent to
doing:
x = cdclk * sq_div = vco / div / 2
Meaning that x is the "unsquashed cdclk". From this point, what
bxt_cdclk_cd2x_div_sel() is doing is:
y = vco / x / 2
(the last "2" divisor comes from the switch-case statement).
That resolves to:
y = vco / (vco / div / 2) / 2 = div
--
Gustavo Sousa
>
>
>Matt
>
>> if (HAS_CDCLK_SQUASH(dev_priv))
>> dg2_cdclk_squash_program(dev_priv, waveform);
>>
>> >
>> > >
>> > > I wonder if the misprogramming we're doing today is what requires the
>> > > "HACK" at the bottom of intel_crtc_compute_min_cdclk for DG2?
>> > >
>> > >
>> > > Matt
>> > >
>> > > >
>> > > > Cc: Matt Roper <matthew.d.roper@intel.com>
>> > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> > > > ---
>> > > > drivers/gpu/drm/i915/display/intel_cdclk.c | 269 ++++++++++-----------
>> > > > 1 file changed, 134 insertions(+), 135 deletions(-)
>> > > >
>> > > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> > > > index b93d1ad7936d..7f85a216ff5c 100644
>> > > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> > > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> > > > @@ -1227,183 +1227,182 @@ struct intel_cdclk_vals {
>> > > > u32 cdclk;
>> > > > u16 refclk;
>> > > > u16 waveform;
>> > > > - u8 divider; /* CD2X divider * 2 */
>> > > > u8 ratio;
>> > > > };
>> > > >
>> > > > static const struct intel_cdclk_vals bxt_cdclk_table[] = {
>> > > > - { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
>> > > > - { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
>> > > > - { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
>> > > > - { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
>> > > > - { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
>> > > > + { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
>> > > > + { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
>> > > > + { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
>> > > > + { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
>> > > > + { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
>> > > > {}
>> > > > };
>> > > >
>> > > > static const struct intel_cdclk_vals glk_cdclk_table[] = {
>> > > > - { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
>> > > > - { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
>> > > > - { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
>> > > > + { .refclk = 19200, .cdclk = 79200, .ratio = 33 },
>> > > > + { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
>> > > > + { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
>> > > > {}
>> > > > };
>> > > >
>> > > > static const struct intel_cdclk_vals icl_cdclk_table[] = {
>> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
>> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
>> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
>> > > > - { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
>> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
>> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
>> > > > -
>> > > > - { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
>> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
>> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
>> > > > - { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
>> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
>> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
>> > > > -
>> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
>> > > > - { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
>> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 18 },
>> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
>> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
>> > > > + { .refclk = 19200, .cdclk = 326400, .ratio = 68 },
>> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
>> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
>> > > > +
>> > > > + { .refclk = 24000, .cdclk = 180000, .ratio = 15 },
>> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
>> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
>> > > > + { .refclk = 24000, .cdclk = 324000, .ratio = 54 },
>> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
>> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
>> > > > +
>> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 9 },
>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
>> > > > + { .refclk = 38400, .cdclk = 326400, .ratio = 34 },
>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
>> > > > {}
>> > > > };
>> > > >
>> > > > static const struct intel_cdclk_vals rkl_cdclk_table[] = {
>> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 },
>> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 },
>> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 },
>> > > > - { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
>> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
>> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },
>> > > > -
>> > > > - { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 },
>> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 },
>> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 },
>> > > > - { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
>> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 },
>> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },
>> > > > -
>> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
>> > > > - { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
>> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 36 },
>> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 40 },
>> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 64 },
>> > > > + { .refclk = 19200, .cdclk = 326400, .ratio = 136 },
>> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 116 },
>> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 136 },
>> > > > +
>> > > > + { .refclk = 24000, .cdclk = 180000, .ratio = 30 },
>> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 32 },
>> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 52 },
>> > > > + { .refclk = 24000, .cdclk = 324000, .ratio = 108 },
>> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 92 },
>> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 108 },
>> > > > +
>> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 18 },
>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 20 },
>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 32 },
>> > > > + { .refclk = 38400, .cdclk = 326400, .ratio = 68 },
>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 58 },
>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 68 },
>> > > > {}
>> > > > };
>> > > >
>> > > > static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
>> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
>> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
>> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
>> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
>> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
>> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
>> > > >
>> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
>> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
>> > > > - { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
>> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
>> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
>> > > > + { .refclk = 24400, .cdclk = 648000, .ratio = 54 },
>> > > >
>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
>> > > > {}
>> > > > };
>> > > >
>> > > > static const struct intel_cdclk_vals adlp_cdclk_table[] = {
>> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
>> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
>> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
>> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
>> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
>> > > > -
>> > > > - { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
>> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
>> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
>> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
>> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
>> > > > -
>> > > > - { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
>> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
>> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
>> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
>> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
>> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
>> > > > +
>> > > > + { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
>> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
>> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
>> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
>> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
>> > > > +
>> > > > + { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
>> > > > {}
>> > > > };
>> > > >
>> > > > static const struct intel_cdclk_vals rplu_cdclk_table[] = {
>> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
>> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
>> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
>> > > > - { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
>> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
>> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
>> > > > -
>> > > > - { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
>> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
>> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
>> > > > - { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
>> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
>> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
>> > > > -
>> > > > - { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
>> > > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
>> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
>> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
>> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
>> > > > + { .refclk = 19200, .cdclk = 480000, .ratio = 50 },
>> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
>> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
>> > > > +
>> > > > + { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
>> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
>> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
>> > > > + { .refclk = 24000, .cdclk = 480000, .ratio = 40 },
>> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
>> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
>> > > > +
>> > > > + { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
>> > > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25 },
>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
>> > > > {}
>> > > > };
>> > > >
>> > > > static const struct intel_cdclk_vals dg2_cdclk_table[] = {
>> > > > - { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
>> > > > - { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
>> > > > - { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 },
>> > > > - { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a },
>> > > > - { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa },
>> > > > - { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a },
>> > > > - { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 },
>> > > > - { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 },
>> > > > - { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee },
>> > > > - { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de },
>> > > > - { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
>> > > > - { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
>> > > > + { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
>> > > > + { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
>> > > > + { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
>> > > > + { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
>> > > > + { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
>> > > > + { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
>> > > > + { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
>> > > > + { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
>> > > > + { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
>> > > > + { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
>> > > > + { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
>> > > > + { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
>> > > > {}
>> > > > };
>> > > >
>> > > > static const struct intel_cdclk_vals mtl_cdclk_table[] = {
>> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
>> > > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
>> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
>> > > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
>> > > > {}
>> > > > };
>> > > >
>> > > > static const struct intel_cdclk_vals lnl_cdclk_table[] = {
>> > > > - { .refclk = 38400, .cdclk = 153600, .divider = 2, .ratio = 16, .waveform = 0xaaaa },
>> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
>> > > > - { .refclk = 38400, .cdclk = 211200, .divider = 2, .ratio = 16, .waveform = 0xdbb6 },
>> > > > - { .refclk = 38400, .cdclk = 230400, .divider = 2, .ratio = 16, .waveform = 0xeeee },
>> > > > - { .refclk = 38400, .cdclk = 249600, .divider = 2, .ratio = 16, .waveform = 0xf7de },
>> > > > - { .refclk = 38400, .cdclk = 268800, .divider = 2, .ratio = 16, .waveform = 0xfefe },
>> > > > - { .refclk = 38400, .cdclk = 288000, .divider = 2, .ratio = 16, .waveform = 0xfffe },
>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0xffff },
>> > > > - { .refclk = 38400, .cdclk = 330000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 },
>> > > > - { .refclk = 38400, .cdclk = 360000, .divider = 2, .ratio = 25, .waveform = 0xeeee },
>> > > > - { .refclk = 38400, .cdclk = 390000, .divider = 2, .ratio = 25, .waveform = 0xf7de },
>> > > > - { .refclk = 38400, .cdclk = 420000, .divider = 2, .ratio = 25, .waveform = 0xfefe },
>> > > > - { .refclk = 38400, .cdclk = 450000, .divider = 2, .ratio = 25, .waveform = 0xfffe },
>> > > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0xffff },
>> > > > - { .refclk = 38400, .cdclk = 487200, .divider = 2, .ratio = 29, .waveform = 0xfefe },
>> > > > - { .refclk = 38400, .cdclk = 522000, .divider = 2, .ratio = 29, .waveform = 0xfffe },
>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0xffff },
>> > > > - { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
>> > > > - { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
>> > > > + { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
>> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
>> > > > + { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
>> > > > + { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
>> > > > + { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
>> > > > + { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
>> > > > + { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
>> > > > + { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
>> > > > + { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
>> > > > + { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
>> > > > + { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
>> > > > + { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
>> > > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
>> > > > + { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
>> > > > + { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
>> > > > + { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
>> > > > + { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
>> > > > {}
>> > > > };
>> > > >
>> > > > --
>> > > > 2.42.1
>> > > >
>> > >
>> > > --
>> > > Matt Roper
>> > > Graphics Software Engineer
>> > > Linux GPU Platform Enablement
>> > > Intel Corporation
>> >
>> > --
>> > Ville Syrjälä
>> > Intel
>>
>> --
>> Ville Syrjälä
>> Intel
>
>--
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/cdclk: Remove divider field from tables
2023-12-04 14:04 ` Gustavo Sousa
@ 2023-12-04 14:13 ` Gustavo Sousa
2023-12-14 0:07 ` Matt Roper
0 siblings, 1 reply; 14+ messages in thread
From: Gustavo Sousa @ 2023-12-04 14:13 UTC (permalink / raw)
To: Matt Roper, Ville Syrjälä; +Cc: intel-gfx
Quoting Gustavo Sousa (2023-12-04 11:04:20-03:00)
>Quoting Matt Roper (2023-12-01 20:07:48-03:00)
>>On Tue, Nov 28, 2023 at 11:51:43AM +0200, Ville Syrjälä wrote:
>>> On Tue, Nov 28, 2023 at 10:43:36AM +0200, Ville Syrjälä wrote:
>>> > On Mon, Nov 27, 2023 at 08:21:46AM -0800, Matt Roper wrote:
>>> > > On Fri, Nov 24, 2023 at 05:55:23PM -0300, Gustavo Sousa wrote:
>>> > > > The cdclk tables were introduced with commit 736da8112fee ("drm/i915:
>>> > > > Use literal representation of cdclk tables"). It has been almost 4 years
>>> > > > and the divider field was not really used yet. Let's remove it.
>>> > >
>>> > > I think we need to go the other way and actually start using it instead
>>> > > of (incorrectly) trying to re-derive it from cdclk->vco. The logic the
>>> > > driver is using today doesn't account for the potential use of
>>> > > squashing, which means we program the wrong divider value into CDCLK_CTL
>>> > > in some cases. I pointed that out during the LNL code reviews a couple
>>> > > months ago, and I believe Stan is working on fixing that.
>>> >
>>> > The code should be correct as is, but it does assume that the cd2x
>>> > divider is 2 when squashing is used. If that no longer holds then we
>>> > have to change something.
>>>
>>> Something like this should be sufficient to eliminate that
>>> assumption.
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>>> index 8bb6bab7c8cd..58567d42e725 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>>> @@ -1897,10 +1897,7 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
>>>
>>> waveform = cdclk_squash_waveform(dev_priv, cdclk);
>>>
>>> - if (waveform)
>>> - clock = vco / 2;
Ah, one thing I did not mention in my previous message is that, this
assignment here means that we were always assuming that the divisor was
always 1:
x' = vco / 2
, meaning that bxt_cdclk_cd2x_div_sel() would do:
y' = vco / x' / 2 = 1
--
Gustavo Sousa
>>> - else
>>> - clock = cdclk;
>>> + clock = DIV_ROUND_CLOSEST(cdclk * 16, cdclk_squash_divider(waveform));
>>>
>>
>>I haven't had time to come back and revisit this (or check your new
>>series yet), but when I was reviewing the cdclk stuff a couple months
>>ago, my concern was around bxt_cdclk_cd2x_div_sel() which is deriving
>>the CD2X divider from the vco and cdclk value. On a platform like DG2,
>>we use squashing instead of changes to PLL ratio to hit different cdclk
>>values, so the calculation there doesn't seem valid anymore. Am I
>>overlooking something?
>
>I looked at Ville's patches and they seem correct to me - althought I'm
>not that experienced and might be missing something as well... Here goes
>my rationale:
>
>Looking at how cdclk works with our hardware, I would say that the
>cdclock is defined by:
>
> cdclk = vco / div / sq_div / 2
>
>, with: vco being the output of the CD2X PLL; "div", the CD2X divider;
>"sq_div", the divider that is derived from the squash wave (16 / "sqash
>wave 1's count"); and 2, the final division that is done at the end.
>
>The DIV_ROUND_CLOSEST() operation suggested above is equivalent to
>doing:
>
> x = cdclk * sq_div = vco / div / 2
>
>Meaning that x is the "unsquashed cdclk". From this point, what
>bxt_cdclk_cd2x_div_sel() is doing is:
>
> y = vco / x / 2
>
>(the last "2" divisor comes from the switch-case statement).
>
>That resolves to:
>
> y = vco / (vco / div / 2) / 2 = div
>
>--
>Gustavo Sousa
>
>>
>>
>>Matt
>>
>>> if (HAS_CDCLK_SQUASH(dev_priv))
>>> dg2_cdclk_squash_program(dev_priv, waveform);
>>>
>>> >
>>> > >
>>> > > I wonder if the misprogramming we're doing today is what requires the
>>> > > "HACK" at the bottom of intel_crtc_compute_min_cdclk for DG2?
>>> > >
>>> > >
>>> > > Matt
>>> > >
>>> > > >
>>> > > > Cc: Matt Roper <matthew.d.roper@intel.com>
>>> > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> > > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>>> > > > ---
>>> > > > drivers/gpu/drm/i915/display/intel_cdclk.c | 269 ++++++++++-----------
>>> > > > 1 file changed, 134 insertions(+), 135 deletions(-)
>>> > > >
>>> > > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>>> > > > index b93d1ad7936d..7f85a216ff5c 100644
>>> > > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>>> > > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>>> > > > @@ -1227,183 +1227,182 @@ struct intel_cdclk_vals {
>>> > > > u32 cdclk;
>>> > > > u16 refclk;
>>> > > > u16 waveform;
>>> > > > - u8 divider; /* CD2X divider * 2 */
>>> > > > u8 ratio;
>>> > > > };
>>> > > >
>>> > > > static const struct intel_cdclk_vals bxt_cdclk_table[] = {
>>> > > > - { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
>>> > > > - { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
>>> > > > - { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
>>> > > > - { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
>>> > > > - { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
>>> > > > + { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
>>> > > > + { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
>>> > > > + { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
>>> > > > + { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
>>> > > > + { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
>>> > > > {}
>>> > > > };
>>> > > >
>>> > > > static const struct intel_cdclk_vals glk_cdclk_table[] = {
>>> > > > - { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
>>> > > > - { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
>>> > > > - { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
>>> > > > + { .refclk = 19200, .cdclk = 79200, .ratio = 33 },
>>> > > > + { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
>>> > > > + { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
>>> > > > {}
>>> > > > };
>>> > > >
>>> > > > static const struct intel_cdclk_vals icl_cdclk_table[] = {
>>> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
>>> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
>>> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
>>> > > > - { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
>>> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
>>> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
>>> > > > -
>>> > > > - { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
>>> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
>>> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
>>> > > > - { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
>>> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
>>> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
>>> > > > -
>>> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
>>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
>>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
>>> > > > - { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
>>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
>>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
>>> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 18 },
>>> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
>>> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
>>> > > > + { .refclk = 19200, .cdclk = 326400, .ratio = 68 },
>>> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
>>> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
>>> > > > +
>>> > > > + { .refclk = 24000, .cdclk = 180000, .ratio = 15 },
>>> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
>>> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
>>> > > > + { .refclk = 24000, .cdclk = 324000, .ratio = 54 },
>>> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
>>> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
>>> > > > +
>>> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 9 },
>>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
>>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
>>> > > > + { .refclk = 38400, .cdclk = 326400, .ratio = 34 },
>>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
>>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
>>> > > > {}
>>> > > > };
>>> > > >
>>> > > > static const struct intel_cdclk_vals rkl_cdclk_table[] = {
>>> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 },
>>> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 },
>>> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 },
>>> > > > - { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
>>> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
>>> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },
>>> > > > -
>>> > > > - { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 },
>>> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 },
>>> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 },
>>> > > > - { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
>>> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 },
>>> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },
>>> > > > -
>>> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
>>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
>>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
>>> > > > - { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
>>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
>>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
>>> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 36 },
>>> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 40 },
>>> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 64 },
>>> > > > + { .refclk = 19200, .cdclk = 326400, .ratio = 136 },
>>> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 116 },
>>> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 136 },
>>> > > > +
>>> > > > + { .refclk = 24000, .cdclk = 180000, .ratio = 30 },
>>> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 32 },
>>> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 52 },
>>> > > > + { .refclk = 24000, .cdclk = 324000, .ratio = 108 },
>>> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 92 },
>>> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 108 },
>>> > > > +
>>> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 18 },
>>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 20 },
>>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 32 },
>>> > > > + { .refclk = 38400, .cdclk = 326400, .ratio = 68 },
>>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 58 },
>>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 68 },
>>> > > > {}
>>> > > > };
>>> > > >
>>> > > > static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
>>> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
>>> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
>>> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
>>> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
>>> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
>>> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
>>> > > >
>>> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
>>> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
>>> > > > - { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
>>> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
>>> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
>>> > > > + { .refclk = 24400, .cdclk = 648000, .ratio = 54 },
>>> > > >
>>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
>>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
>>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
>>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
>>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
>>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
>>> > > > {}
>>> > > > };
>>> > > >
>>> > > > static const struct intel_cdclk_vals adlp_cdclk_table[] = {
>>> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
>>> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
>>> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
>>> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
>>> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
>>> > > > -
>>> > > > - { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
>>> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
>>> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
>>> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
>>> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
>>> > > > -
>>> > > > - { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
>>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
>>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
>>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
>>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
>>> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
>>> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
>>> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
>>> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
>>> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
>>> > > > +
>>> > > > + { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
>>> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
>>> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
>>> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
>>> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
>>> > > > +
>>> > > > + { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
>>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
>>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
>>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
>>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
>>> > > > {}
>>> > > > };
>>> > > >
>>> > > > static const struct intel_cdclk_vals rplu_cdclk_table[] = {
>>> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
>>> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
>>> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
>>> > > > - { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
>>> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
>>> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
>>> > > > -
>>> > > > - { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
>>> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
>>> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
>>> > > > - { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
>>> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
>>> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
>>> > > > -
>>> > > > - { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
>>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
>>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
>>> > > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
>>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
>>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
>>> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
>>> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
>>> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
>>> > > > + { .refclk = 19200, .cdclk = 480000, .ratio = 50 },
>>> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
>>> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
>>> > > > +
>>> > > > + { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
>>> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
>>> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
>>> > > > + { .refclk = 24000, .cdclk = 480000, .ratio = 40 },
>>> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
>>> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
>>> > > > +
>>> > > > + { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
>>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
>>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
>>> > > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25 },
>>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
>>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
>>> > > > {}
>>> > > > };
>>> > > >
>>> > > > static const struct intel_cdclk_vals dg2_cdclk_table[] = {
>>> > > > - { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
>>> > > > - { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
>>> > > > - { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 },
>>> > > > - { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a },
>>> > > > - { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa },
>>> > > > - { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a },
>>> > > > - { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 },
>>> > > > - { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 },
>>> > > > - { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee },
>>> > > > - { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de },
>>> > > > - { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
>>> > > > - { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
>>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
>>> > > > + { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
>>> > > > + { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
>>> > > > + { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
>>> > > > + { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
>>> > > > + { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
>>> > > > + { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
>>> > > > + { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
>>> > > > + { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
>>> > > > + { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
>>> > > > + { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
>>> > > > + { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
>>> > > > + { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
>>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
>>> > > > {}
>>> > > > };
>>> > > >
>>> > > > static const struct intel_cdclk_vals mtl_cdclk_table[] = {
>>> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
>>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
>>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
>>> > > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
>>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
>>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
>>> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
>>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
>>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
>>> > > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
>>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
>>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
>>> > > > {}
>>> > > > };
>>> > > >
>>> > > > static const struct intel_cdclk_vals lnl_cdclk_table[] = {
>>> > > > - { .refclk = 38400, .cdclk = 153600, .divider = 2, .ratio = 16, .waveform = 0xaaaa },
>>> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
>>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
>>> > > > - { .refclk = 38400, .cdclk = 211200, .divider = 2, .ratio = 16, .waveform = 0xdbb6 },
>>> > > > - { .refclk = 38400, .cdclk = 230400, .divider = 2, .ratio = 16, .waveform = 0xeeee },
>>> > > > - { .refclk = 38400, .cdclk = 249600, .divider = 2, .ratio = 16, .waveform = 0xf7de },
>>> > > > - { .refclk = 38400, .cdclk = 268800, .divider = 2, .ratio = 16, .waveform = 0xfefe },
>>> > > > - { .refclk = 38400, .cdclk = 288000, .divider = 2, .ratio = 16, .waveform = 0xfffe },
>>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0xffff },
>>> > > > - { .refclk = 38400, .cdclk = 330000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 },
>>> > > > - { .refclk = 38400, .cdclk = 360000, .divider = 2, .ratio = 25, .waveform = 0xeeee },
>>> > > > - { .refclk = 38400, .cdclk = 390000, .divider = 2, .ratio = 25, .waveform = 0xf7de },
>>> > > > - { .refclk = 38400, .cdclk = 420000, .divider = 2, .ratio = 25, .waveform = 0xfefe },
>>> > > > - { .refclk = 38400, .cdclk = 450000, .divider = 2, .ratio = 25, .waveform = 0xfffe },
>>> > > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0xffff },
>>> > > > - { .refclk = 38400, .cdclk = 487200, .divider = 2, .ratio = 29, .waveform = 0xfefe },
>>> > > > - { .refclk = 38400, .cdclk = 522000, .divider = 2, .ratio = 29, .waveform = 0xfffe },
>>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0xffff },
>>> > > > - { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
>>> > > > - { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
>>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
>>> > > > + { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
>>> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
>>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
>>> > > > + { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
>>> > > > + { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
>>> > > > + { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
>>> > > > + { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
>>> > > > + { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
>>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
>>> > > > + { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
>>> > > > + { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
>>> > > > + { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
>>> > > > + { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
>>> > > > + { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
>>> > > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
>>> > > > + { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
>>> > > > + { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
>>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
>>> > > > + { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
>>> > > > + { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
>>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
>>> > > > {}
>>> > > > };
>>> > > >
>>> > > > --
>>> > > > 2.42.1
>>> > > >
>>> > >
>>> > > --
>>> > > Matt Roper
>>> > > Graphics Software Engineer
>>> > > Linux GPU Platform Enablement
>>> > > Intel Corporation
>>> >
>>> > --
>>> > Ville Syrjälä
>>> > Intel
>>>
>>> --
>>> Ville Syrjälä
>>> Intel
>>
>>--
>>Matt Roper
>>Graphics Software Engineer
>>Linux GPU Platform Enablement
>>Intel Corporation
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/cdclk: Remove divider field from tables
2023-12-04 14:13 ` Gustavo Sousa
@ 2023-12-14 0:07 ` Matt Roper
2023-12-20 21:13 ` Matt Roper
0 siblings, 1 reply; 14+ messages in thread
From: Matt Roper @ 2023-12-14 0:07 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-gfx
On Mon, Dec 04, 2023 at 11:13:52AM -0300, Gustavo Sousa wrote:
> Quoting Gustavo Sousa (2023-12-04 11:04:20-03:00)
> >Quoting Matt Roper (2023-12-01 20:07:48-03:00)
> >>On Tue, Nov 28, 2023 at 11:51:43AM +0200, Ville Syrjälä wrote:
> >>> On Tue, Nov 28, 2023 at 10:43:36AM +0200, Ville Syrjälä wrote:
> >>> > On Mon, Nov 27, 2023 at 08:21:46AM -0800, Matt Roper wrote:
> >>> > > On Fri, Nov 24, 2023 at 05:55:23PM -0300, Gustavo Sousa wrote:
> >>> > > > The cdclk tables were introduced with commit 736da8112fee ("drm/i915:
> >>> > > > Use literal representation of cdclk tables"). It has been almost 4 years
> >>> > > > and the divider field was not really used yet. Let's remove it.
> >>> > >
> >>> > > I think we need to go the other way and actually start using it instead
> >>> > > of (incorrectly) trying to re-derive it from cdclk->vco. The logic the
> >>> > > driver is using today doesn't account for the potential use of
> >>> > > squashing, which means we program the wrong divider value into CDCLK_CTL
> >>> > > in some cases. I pointed that out during the LNL code reviews a couple
> >>> > > months ago, and I believe Stan is working on fixing that.
> >>> >
> >>> > The code should be correct as is, but it does assume that the cd2x
> >>> > divider is 2 when squashing is used. If that no longer holds then we
> >>> > have to change something.
> >>>
> >>> Something like this should be sufficient to eliminate that
> >>> assumption.
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >>> index 8bb6bab7c8cd..58567d42e725 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> >>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >>> @@ -1897,10 +1897,7 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
> >>>
> >>> waveform = cdclk_squash_waveform(dev_priv, cdclk);
> >>>
> >>> - if (waveform)
> >>> - clock = vco / 2;
>
> Ah, one thing I did not mention in my previous message is that, this
> assignment here means that we were always assuming that the divisor was
> always 1:
>
> x' = vco / 2
>
> , meaning that bxt_cdclk_cd2x_div_sel() would do:
>
> y' = vco / x' / 2 = 1
>
I finally got back to looking at this. With Ville's cleanups it's a lot
clearer and I agree we should be safe to drop the dividers from the
table.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Sorry for the delay getting back to this.
Matt
> --
> Gustavo Sousa
>
> >>> - else
> >>> - clock = cdclk;
> >>> + clock = DIV_ROUND_CLOSEST(cdclk * 16, cdclk_squash_divider(waveform));
> >>>
> >>
> >>I haven't had time to come back and revisit this (or check your new
> >>series yet), but when I was reviewing the cdclk stuff a couple months
> >>ago, my concern was around bxt_cdclk_cd2x_div_sel() which is deriving
> >>the CD2X divider from the vco and cdclk value. On a platform like DG2,
> >>we use squashing instead of changes to PLL ratio to hit different cdclk
> >>values, so the calculation there doesn't seem valid anymore. Am I
> >>overlooking something?
> >
> >I looked at Ville's patches and they seem correct to me - althought I'm
> >not that experienced and might be missing something as well... Here goes
> >my rationale:
> >
> >Looking at how cdclk works with our hardware, I would say that the
> >cdclock is defined by:
> >
> > cdclk = vco / div / sq_div / 2
> >
> >, with: vco being the output of the CD2X PLL; "div", the CD2X divider;
> >"sq_div", the divider that is derived from the squash wave (16 / "sqash
> >wave 1's count"); and 2, the final division that is done at the end.
> >
> >The DIV_ROUND_CLOSEST() operation suggested above is equivalent to
> >doing:
> >
> > x = cdclk * sq_div = vco / div / 2
> >
> >Meaning that x is the "unsquashed cdclk". From this point, what
> >bxt_cdclk_cd2x_div_sel() is doing is:
> >
> > y = vco / x / 2
> >
> >(the last "2" divisor comes from the switch-case statement).
> >
> >That resolves to:
> >
> > y = vco / (vco / div / 2) / 2 = div
> >
> >--
> >Gustavo Sousa
> >
> >>
> >>
> >>Matt
> >>
> >>> if (HAS_CDCLK_SQUASH(dev_priv))
> >>> dg2_cdclk_squash_program(dev_priv, waveform);
> >>>
> >>> >
> >>> > >
> >>> > > I wonder if the misprogramming we're doing today is what requires the
> >>> > > "HACK" at the bottom of intel_crtc_compute_min_cdclk for DG2?
> >>> > >
> >>> > >
> >>> > > Matt
> >>> > >
> >>> > > >
> >>> > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> >>> > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>> > > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> >>> > > > ---
> >>> > > > drivers/gpu/drm/i915/display/intel_cdclk.c | 269 ++++++++++-----------
> >>> > > > 1 file changed, 134 insertions(+), 135 deletions(-)
> >>> > > >
> >>> > > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >>> > > > index b93d1ad7936d..7f85a216ff5c 100644
> >>> > > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> >>> > > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >>> > > > @@ -1227,183 +1227,182 @@ struct intel_cdclk_vals {
> >>> > > > u32 cdclk;
> >>> > > > u16 refclk;
> >>> > > > u16 waveform;
> >>> > > > - u8 divider; /* CD2X divider * 2 */
> >>> > > > u8 ratio;
> >>> > > > };
> >>> > > >
> >>> > > > static const struct intel_cdclk_vals bxt_cdclk_table[] = {
> >>> > > > - { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
> >>> > > > - { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
> >>> > > > - { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
> >>> > > > - { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
> >>> > > > - { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
> >>> > > > + { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
> >>> > > > + { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
> >>> > > > + { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
> >>> > > > + { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
> >>> > > > + { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
> >>> > > > {}
> >>> > > > };
> >>> > > >
> >>> > > > static const struct intel_cdclk_vals glk_cdclk_table[] = {
> >>> > > > - { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
> >>> > > > - { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
> >>> > > > - { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
> >>> > > > + { .refclk = 19200, .cdclk = 79200, .ratio = 33 },
> >>> > > > + { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
> >>> > > > + { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
> >>> > > > {}
> >>> > > > };
> >>> > > >
> >>> > > > static const struct intel_cdclk_vals icl_cdclk_table[] = {
> >>> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
> >>> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> >>> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> >>> > > > - { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
> >>> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> >>> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> >>> > > > -
> >>> > > > - { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
> >>> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> >>> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> >>> > > > - { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
> >>> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> >>> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> >>> > > > -
> >>> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
> >>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> >>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> >>> > > > - { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
> >>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> >>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> >>> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 18 },
> >>> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> >>> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> >>> > > > + { .refclk = 19200, .cdclk = 326400, .ratio = 68 },
> >>> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> >>> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> >>> > > > +
> >>> > > > + { .refclk = 24000, .cdclk = 180000, .ratio = 15 },
> >>> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> >>> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> >>> > > > + { .refclk = 24000, .cdclk = 324000, .ratio = 54 },
> >>> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> >>> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> >>> > > > +
> >>> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 9 },
> >>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> >>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> >>> > > > + { .refclk = 38400, .cdclk = 326400, .ratio = 34 },
> >>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> >>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> >>> > > > {}
> >>> > > > };
> >>> > > >
> >>> > > > static const struct intel_cdclk_vals rkl_cdclk_table[] = {
> >>> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 },
> >>> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 },
> >>> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 },
> >>> > > > - { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
> >>> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
> >>> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },
> >>> > > > -
> >>> > > > - { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 },
> >>> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 },
> >>> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 },
> >>> > > > - { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
> >>> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 },
> >>> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },
> >>> > > > -
> >>> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
> >>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
> >>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
> >>> > > > - { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
> >>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
> >>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
> >>> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 36 },
> >>> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 40 },
> >>> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 64 },
> >>> > > > + { .refclk = 19200, .cdclk = 326400, .ratio = 136 },
> >>> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 116 },
> >>> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 136 },
> >>> > > > +
> >>> > > > + { .refclk = 24000, .cdclk = 180000, .ratio = 30 },
> >>> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 32 },
> >>> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 52 },
> >>> > > > + { .refclk = 24000, .cdclk = 324000, .ratio = 108 },
> >>> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 92 },
> >>> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 108 },
> >>> > > > +
> >>> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 18 },
> >>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 20 },
> >>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 32 },
> >>> > > > + { .refclk = 38400, .cdclk = 326400, .ratio = 68 },
> >>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 58 },
> >>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 68 },
> >>> > > > {}
> >>> > > > };
> >>> > > >
> >>> > > > static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
> >>> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> >>> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> >>> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> >>> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> >>> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> >>> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> >>> > > >
> >>> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> >>> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> >>> > > > - { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
> >>> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> >>> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> >>> > > > + { .refclk = 24400, .cdclk = 648000, .ratio = 54 },
> >>> > > >
> >>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> >>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> >>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> >>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> >>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> >>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> >>> > > > {}
> >>> > > > };
> >>> > > >
> >>> > > > static const struct intel_cdclk_vals adlp_cdclk_table[] = {
> >>> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> >>> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> >>> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> >>> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> >>> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> >>> > > > -
> >>> > > > - { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> >>> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> >>> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> >>> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> >>> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> >>> > > > -
> >>> > > > - { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> >>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> >>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> >>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> >>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> >>> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
> >>> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> >>> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> >>> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> >>> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> >>> > > > +
> >>> > > > + { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
> >>> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> >>> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> >>> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> >>> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> >>> > > > +
> >>> > > > + { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
> >>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> >>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> >>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> >>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> >>> > > > {}
> >>> > > > };
> >>> > > >
> >>> > > > static const struct intel_cdclk_vals rplu_cdclk_table[] = {
> >>> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> >>> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> >>> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> >>> > > > - { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
> >>> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> >>> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> >>> > > > -
> >>> > > > - { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> >>> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> >>> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> >>> > > > - { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
> >>> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> >>> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> >>> > > > -
> >>> > > > - { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> >>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> >>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> >>> > > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
> >>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> >>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> >>> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
> >>> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> >>> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> >>> > > > + { .refclk = 19200, .cdclk = 480000, .ratio = 50 },
> >>> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> >>> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> >>> > > > +
> >>> > > > + { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
> >>> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> >>> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> >>> > > > + { .refclk = 24000, .cdclk = 480000, .ratio = 40 },
> >>> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> >>> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> >>> > > > +
> >>> > > > + { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
> >>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> >>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> >>> > > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25 },
> >>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> >>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> >>> > > > {}
> >>> > > > };
> >>> > > >
> >>> > > > static const struct intel_cdclk_vals dg2_cdclk_table[] = {
> >>> > > > - { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
> >>> > > > - { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
> >>> > > > - { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 },
> >>> > > > - { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a },
> >>> > > > - { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa },
> >>> > > > - { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a },
> >>> > > > - { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 },
> >>> > > > - { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 },
> >>> > > > - { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee },
> >>> > > > - { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de },
> >>> > > > - { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
> >>> > > > - { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
> >>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
> >>> > > > + { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
> >>> > > > + { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
> >>> > > > + { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
> >>> > > > + { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
> >>> > > > + { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
> >>> > > > + { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
> >>> > > > + { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
> >>> > > > + { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
> >>> > > > + { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
> >>> > > > + { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
> >>> > > > + { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
> >>> > > > + { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
> >>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
> >>> > > > {}
> >>> > > > };
> >>> > > >
> >>> > > > static const struct intel_cdclk_vals mtl_cdclk_table[] = {
> >>> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> >>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> >>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
> >>> > > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
> >>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
> >>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
> >>> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
> >>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
> >>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
> >>> > > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
> >>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
> >>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
> >>> > > > {}
> >>> > > > };
> >>> > > >
> >>> > > > static const struct intel_cdclk_vals lnl_cdclk_table[] = {
> >>> > > > - { .refclk = 38400, .cdclk = 153600, .divider = 2, .ratio = 16, .waveform = 0xaaaa },
> >>> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> >>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> >>> > > > - { .refclk = 38400, .cdclk = 211200, .divider = 2, .ratio = 16, .waveform = 0xdbb6 },
> >>> > > > - { .refclk = 38400, .cdclk = 230400, .divider = 2, .ratio = 16, .waveform = 0xeeee },
> >>> > > > - { .refclk = 38400, .cdclk = 249600, .divider = 2, .ratio = 16, .waveform = 0xf7de },
> >>> > > > - { .refclk = 38400, .cdclk = 268800, .divider = 2, .ratio = 16, .waveform = 0xfefe },
> >>> > > > - { .refclk = 38400, .cdclk = 288000, .divider = 2, .ratio = 16, .waveform = 0xfffe },
> >>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0xffff },
> >>> > > > - { .refclk = 38400, .cdclk = 330000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 },
> >>> > > > - { .refclk = 38400, .cdclk = 360000, .divider = 2, .ratio = 25, .waveform = 0xeeee },
> >>> > > > - { .refclk = 38400, .cdclk = 390000, .divider = 2, .ratio = 25, .waveform = 0xf7de },
> >>> > > > - { .refclk = 38400, .cdclk = 420000, .divider = 2, .ratio = 25, .waveform = 0xfefe },
> >>> > > > - { .refclk = 38400, .cdclk = 450000, .divider = 2, .ratio = 25, .waveform = 0xfffe },
> >>> > > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0xffff },
> >>> > > > - { .refclk = 38400, .cdclk = 487200, .divider = 2, .ratio = 29, .waveform = 0xfefe },
> >>> > > > - { .refclk = 38400, .cdclk = 522000, .divider = 2, .ratio = 29, .waveform = 0xfffe },
> >>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0xffff },
> >>> > > > - { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
> >>> > > > - { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
> >>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
> >>> > > > + { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
> >>> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
> >>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
> >>> > > > + { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
> >>> > > > + { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
> >>> > > > + { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
> >>> > > > + { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
> >>> > > > + { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
> >>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
> >>> > > > + { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
> >>> > > > + { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
> >>> > > > + { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
> >>> > > > + { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
> >>> > > > + { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
> >>> > > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
> >>> > > > + { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
> >>> > > > + { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
> >>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
> >>> > > > + { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
> >>> > > > + { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
> >>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
> >>> > > > {}
> >>> > > > };
> >>> > > >
> >>> > > > --
> >>> > > > 2.42.1
> >>> > > >
> >>> > >
> >>> > > --
> >>> > > Matt Roper
> >>> > > Graphics Software Engineer
> >>> > > Linux GPU Platform Enablement
> >>> > > Intel Corporation
> >>> >
> >>> > --
> >>> > Ville Syrjälä
> >>> > Intel
> >>>
> >>> --
> >>> Ville Syrjälä
> >>> Intel
> >>
> >>--
> >>Matt Roper
> >>Graphics Software Engineer
> >>Linux GPU Platform Enablement
> >>Intel Corporation
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/cdclk: Remove divider field from tables
2023-12-14 0:07 ` Matt Roper
@ 2023-12-20 21:13 ` Matt Roper
0 siblings, 0 replies; 14+ messages in thread
From: Matt Roper @ 2023-12-20 21:13 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-gfx
On Wed, Dec 13, 2023 at 04:07:26PM -0800, Matt Roper wrote:
> On Mon, Dec 04, 2023 at 11:13:52AM -0300, Gustavo Sousa wrote:
> > Quoting Gustavo Sousa (2023-12-04 11:04:20-03:00)
> > >Quoting Matt Roper (2023-12-01 20:07:48-03:00)
> > >>On Tue, Nov 28, 2023 at 11:51:43AM +0200, Ville Syrjälä wrote:
> > >>> On Tue, Nov 28, 2023 at 10:43:36AM +0200, Ville Syrjälä wrote:
> > >>> > On Mon, Nov 27, 2023 at 08:21:46AM -0800, Matt Roper wrote:
> > >>> > > On Fri, Nov 24, 2023 at 05:55:23PM -0300, Gustavo Sousa wrote:
> > >>> > > > The cdclk tables were introduced with commit 736da8112fee ("drm/i915:
> > >>> > > > Use literal representation of cdclk tables"). It has been almost 4 years
> > >>> > > > and the divider field was not really used yet. Let's remove it.
> > >>> > >
> > >>> > > I think we need to go the other way and actually start using it instead
> > >>> > > of (incorrectly) trying to re-derive it from cdclk->vco. The logic the
> > >>> > > driver is using today doesn't account for the potential use of
> > >>> > > squashing, which means we program the wrong divider value into CDCLK_CTL
> > >>> > > in some cases. I pointed that out during the LNL code reviews a couple
> > >>> > > months ago, and I believe Stan is working on fixing that.
> > >>> >
> > >>> > The code should be correct as is, but it does assume that the cd2x
> > >>> > divider is 2 when squashing is used. If that no longer holds then we
> > >>> > have to change something.
> > >>>
> > >>> Something like this should be sufficient to eliminate that
> > >>> assumption.
> > >>>
> > >>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > >>> index 8bb6bab7c8cd..58567d42e725 100644
> > >>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > >>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > >>> @@ -1897,10 +1897,7 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
> > >>>
> > >>> waveform = cdclk_squash_waveform(dev_priv, cdclk);
> > >>>
> > >>> - if (waveform)
> > >>> - clock = vco / 2;
> >
> > Ah, one thing I did not mention in my previous message is that, this
> > assignment here means that we were always assuming that the divisor was
> > always 1:
> >
> > x' = vco / 2
> >
> > , meaning that bxt_cdclk_cd2x_div_sel() would do:
> >
> > y' = vco / x' / 2 = 1
> >
>
> I finally got back to looking at this. With Ville's cleanups it's a lot
> clearer and I agree we should be safe to drop the dividers from the
> table.
>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
> Sorry for the delay getting back to this.
And applied to drm-intel-next. Thanks for the patch.
Matt
>
>
> Matt
>
> > --
> > Gustavo Sousa
> >
> > >>> - else
> > >>> - clock = cdclk;
> > >>> + clock = DIV_ROUND_CLOSEST(cdclk * 16, cdclk_squash_divider(waveform));
> > >>>
> > >>
> > >>I haven't had time to come back and revisit this (or check your new
> > >>series yet), but when I was reviewing the cdclk stuff a couple months
> > >>ago, my concern was around bxt_cdclk_cd2x_div_sel() which is deriving
> > >>the CD2X divider from the vco and cdclk value. On a platform like DG2,
> > >>we use squashing instead of changes to PLL ratio to hit different cdclk
> > >>values, so the calculation there doesn't seem valid anymore. Am I
> > >>overlooking something?
> > >
> > >I looked at Ville's patches and they seem correct to me - althought I'm
> > >not that experienced and might be missing something as well... Here goes
> > >my rationale:
> > >
> > >Looking at how cdclk works with our hardware, I would say that the
> > >cdclock is defined by:
> > >
> > > cdclk = vco / div / sq_div / 2
> > >
> > >, with: vco being the output of the CD2X PLL; "div", the CD2X divider;
> > >"sq_div", the divider that is derived from the squash wave (16 / "sqash
> > >wave 1's count"); and 2, the final division that is done at the end.
> > >
> > >The DIV_ROUND_CLOSEST() operation suggested above is equivalent to
> > >doing:
> > >
> > > x = cdclk * sq_div = vco / div / 2
> > >
> > >Meaning that x is the "unsquashed cdclk". From this point, what
> > >bxt_cdclk_cd2x_div_sel() is doing is:
> > >
> > > y = vco / x / 2
> > >
> > >(the last "2" divisor comes from the switch-case statement).
> > >
> > >That resolves to:
> > >
> > > y = vco / (vco / div / 2) / 2 = div
> > >
> > >--
> > >Gustavo Sousa
> > >
> > >>
> > >>
> > >>Matt
> > >>
> > >>> if (HAS_CDCLK_SQUASH(dev_priv))
> > >>> dg2_cdclk_squash_program(dev_priv, waveform);
> > >>>
> > >>> >
> > >>> > >
> > >>> > > I wonder if the misprogramming we're doing today is what requires the
> > >>> > > "HACK" at the bottom of intel_crtc_compute_min_cdclk for DG2?
> > >>> > >
> > >>> > >
> > >>> > > Matt
> > >>> > >
> > >>> > > >
> > >>> > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > >>> > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >>> > > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > >>> > > > ---
> > >>> > > > drivers/gpu/drm/i915/display/intel_cdclk.c | 269 ++++++++++-----------
> > >>> > > > 1 file changed, 134 insertions(+), 135 deletions(-)
> > >>> > > >
> > >>> > > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > >>> > > > index b93d1ad7936d..7f85a216ff5c 100644
> > >>> > > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > >>> > > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > >>> > > > @@ -1227,183 +1227,182 @@ struct intel_cdclk_vals {
> > >>> > > > u32 cdclk;
> > >>> > > > u16 refclk;
> > >>> > > > u16 waveform;
> > >>> > > > - u8 divider; /* CD2X divider * 2 */
> > >>> > > > u8 ratio;
> > >>> > > > };
> > >>> > > >
> > >>> > > > static const struct intel_cdclk_vals bxt_cdclk_table[] = {
> > >>> > > > - { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
> > >>> > > > - { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
> > >>> > > > - { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
> > >>> > > > - { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
> > >>> > > > - { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
> > >>> > > > + { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
> > >>> > > > + { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
> > >>> > > > + { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
> > >>> > > > + { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
> > >>> > > > + { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
> > >>> > > > {}
> > >>> > > > };
> > >>> > > >
> > >>> > > > static const struct intel_cdclk_vals glk_cdclk_table[] = {
> > >>> > > > - { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
> > >>> > > > - { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
> > >>> > > > - { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
> > >>> > > > + { .refclk = 19200, .cdclk = 79200, .ratio = 33 },
> > >>> > > > + { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
> > >>> > > > + { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
> > >>> > > > {}
> > >>> > > > };
> > >>> > > >
> > >>> > > > static const struct intel_cdclk_vals icl_cdclk_table[] = {
> > >>> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
> > >>> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > >>> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > >>> > > > - { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
> > >>> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > >>> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > >>> > > > -
> > >>> > > > - { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
> > >>> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > >>> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > >>> > > > - { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
> > >>> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > >>> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > >>> > > > -
> > >>> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
> > >>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > >>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > >>> > > > - { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
> > >>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > >>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > >>> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 18 },
> > >>> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> > >>> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > >>> > > > + { .refclk = 19200, .cdclk = 326400, .ratio = 68 },
> > >>> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > >>> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > >>> > > > +
> > >>> > > > + { .refclk = 24000, .cdclk = 180000, .ratio = 15 },
> > >>> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> > >>> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > >>> > > > + { .refclk = 24000, .cdclk = 324000, .ratio = 54 },
> > >>> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > >>> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> > >>> > > > +
> > >>> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 9 },
> > >>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> > >>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > >>> > > > + { .refclk = 38400, .cdclk = 326400, .ratio = 34 },
> > >>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > >>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > >>> > > > {}
> > >>> > > > };
> > >>> > > >
> > >>> > > > static const struct intel_cdclk_vals rkl_cdclk_table[] = {
> > >>> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 },
> > >>> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 },
> > >>> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 },
> > >>> > > > - { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
> > >>> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
> > >>> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },
> > >>> > > > -
> > >>> > > > - { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 },
> > >>> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 },
> > >>> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 },
> > >>> > > > - { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
> > >>> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 },
> > >>> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },
> > >>> > > > -
> > >>> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
> > >>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
> > >>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
> > >>> > > > - { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
> > >>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
> > >>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
> > >>> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 36 },
> > >>> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 40 },
> > >>> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 64 },
> > >>> > > > + { .refclk = 19200, .cdclk = 326400, .ratio = 136 },
> > >>> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 116 },
> > >>> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 136 },
> > >>> > > > +
> > >>> > > > + { .refclk = 24000, .cdclk = 180000, .ratio = 30 },
> > >>> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 32 },
> > >>> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 52 },
> > >>> > > > + { .refclk = 24000, .cdclk = 324000, .ratio = 108 },
> > >>> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 92 },
> > >>> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 108 },
> > >>> > > > +
> > >>> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 18 },
> > >>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 20 },
> > >>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 32 },
> > >>> > > > + { .refclk = 38400, .cdclk = 326400, .ratio = 68 },
> > >>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 58 },
> > >>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 68 },
> > >>> > > > {}
> > >>> > > > };
> > >>> > > >
> > >>> > > > static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
> > >>> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > >>> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > >>> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > >>> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > >>> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > >>> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > >>> > > >
> > >>> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > >>> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > >>> > > > - { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > >>> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > >>> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > >>> > > > + { .refclk = 24400, .cdclk = 648000, .ratio = 54 },
> > >>> > > >
> > >>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > >>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > >>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > >>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > >>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > >>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > >>> > > > {}
> > >>> > > > };
> > >>> > > >
> > >>> > > > static const struct intel_cdclk_vals adlp_cdclk_table[] = {
> > >>> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> > >>> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > >>> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > >>> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > >>> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > >>> > > > -
> > >>> > > > - { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> > >>> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > >>> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > >>> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > >>> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > >>> > > > -
> > >>> > > > - { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> > >>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > >>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > >>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > >>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > >>> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
> > >>> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> > >>> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > >>> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > >>> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > >>> > > > +
> > >>> > > > + { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
> > >>> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> > >>> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > >>> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > >>> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> > >>> > > > +
> > >>> > > > + { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
> > >>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> > >>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > >>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > >>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > >>> > > > {}
> > >>> > > > };
> > >>> > > >
> > >>> > > > static const struct intel_cdclk_vals rplu_cdclk_table[] = {
> > >>> > > > - { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> > >>> > > > - { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > >>> > > > - { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> > >>> > > > - { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
> > >>> > > > - { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > >>> > > > - { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > >>> > > > -
> > >>> > > > - { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> > >>> > > > - { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > >>> > > > - { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> > >>> > > > - { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
> > >>> > > > - { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > >>> > > > - { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > >>> > > > -
> > >>> > > > - { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> > >>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > >>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> > >>> > > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
> > >>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > >>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > >>> > > > + { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
> > >>> > > > + { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
> > >>> > > > + { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
> > >>> > > > + { .refclk = 19200, .cdclk = 480000, .ratio = 50 },
> > >>> > > > + { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
> > >>> > > > + { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
> > >>> > > > +
> > >>> > > > + { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
> > >>> > > > + { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
> > >>> > > > + { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
> > >>> > > > + { .refclk = 24000, .cdclk = 480000, .ratio = 40 },
> > >>> > > > + { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
> > >>> > > > + { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
> > >>> > > > +
> > >>> > > > + { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
> > >>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
> > >>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
> > >>> > > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25 },
> > >>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
> > >>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
> > >>> > > > {}
> > >>> > > > };
> > >>> > > >
> > >>> > > > static const struct intel_cdclk_vals dg2_cdclk_table[] = {
> > >>> > > > - { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
> > >>> > > > - { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
> > >>> > > > - { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 },
> > >>> > > > - { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a },
> > >>> > > > - { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa },
> > >>> > > > - { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a },
> > >>> > > > - { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 },
> > >>> > > > - { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 },
> > >>> > > > - { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee },
> > >>> > > > - { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de },
> > >>> > > > - { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
> > >>> > > > - { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
> > >>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
> > >>> > > > + { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
> > >>> > > > + { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
> > >>> > > > + { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
> > >>> > > > + { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
> > >>> > > > + { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
> > >>> > > > + { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
> > >>> > > > + { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
> > >>> > > > + { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
> > >>> > > > + { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
> > >>> > > > + { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
> > >>> > > > + { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
> > >>> > > > + { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
> > >>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
> > >>> > > > {}
> > >>> > > > };
> > >>> > > >
> > >>> > > > static const struct intel_cdclk_vals mtl_cdclk_table[] = {
> > >>> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> > >>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> > >>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
> > >>> > > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
> > >>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
> > >>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
> > >>> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
> > >>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
> > >>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
> > >>> > > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
> > >>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
> > >>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
> > >>> > > > {}
> > >>> > > > };
> > >>> > > >
> > >>> > > > static const struct intel_cdclk_vals lnl_cdclk_table[] = {
> > >>> > > > - { .refclk = 38400, .cdclk = 153600, .divider = 2, .ratio = 16, .waveform = 0xaaaa },
> > >>> > > > - { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
> > >>> > > > - { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
> > >>> > > > - { .refclk = 38400, .cdclk = 211200, .divider = 2, .ratio = 16, .waveform = 0xdbb6 },
> > >>> > > > - { .refclk = 38400, .cdclk = 230400, .divider = 2, .ratio = 16, .waveform = 0xeeee },
> > >>> > > > - { .refclk = 38400, .cdclk = 249600, .divider = 2, .ratio = 16, .waveform = 0xf7de },
> > >>> > > > - { .refclk = 38400, .cdclk = 268800, .divider = 2, .ratio = 16, .waveform = 0xfefe },
> > >>> > > > - { .refclk = 38400, .cdclk = 288000, .divider = 2, .ratio = 16, .waveform = 0xfffe },
> > >>> > > > - { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0xffff },
> > >>> > > > - { .refclk = 38400, .cdclk = 330000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 },
> > >>> > > > - { .refclk = 38400, .cdclk = 360000, .divider = 2, .ratio = 25, .waveform = 0xeeee },
> > >>> > > > - { .refclk = 38400, .cdclk = 390000, .divider = 2, .ratio = 25, .waveform = 0xf7de },
> > >>> > > > - { .refclk = 38400, .cdclk = 420000, .divider = 2, .ratio = 25, .waveform = 0xfefe },
> > >>> > > > - { .refclk = 38400, .cdclk = 450000, .divider = 2, .ratio = 25, .waveform = 0xfffe },
> > >>> > > > - { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0xffff },
> > >>> > > > - { .refclk = 38400, .cdclk = 487200, .divider = 2, .ratio = 29, .waveform = 0xfefe },
> > >>> > > > - { .refclk = 38400, .cdclk = 522000, .divider = 2, .ratio = 29, .waveform = 0xfffe },
> > >>> > > > - { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0xffff },
> > >>> > > > - { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
> > >>> > > > - { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
> > >>> > > > - { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
> > >>> > > > + { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
> > >>> > > > + { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
> > >>> > > > + { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
> > >>> > > > + { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
> > >>> > > > + { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
> > >>> > > > + { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
> > >>> > > > + { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
> > >>> > > > + { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
> > >>> > > > + { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
> > >>> > > > + { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
> > >>> > > > + { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
> > >>> > > > + { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
> > >>> > > > + { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
> > >>> > > > + { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
> > >>> > > > + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
> > >>> > > > + { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
> > >>> > > > + { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
> > >>> > > > + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
> > >>> > > > + { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
> > >>> > > > + { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
> > >>> > > > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
> > >>> > > > {}
> > >>> > > > };
> > >>> > > >
> > >>> > > > --
> > >>> > > > 2.42.1
> > >>> > > >
> > >>> > >
> > >>> > > --
> > >>> > > Matt Roper
> > >>> > > Graphics Software Engineer
> > >>> > > Linux GPU Platform Enablement
> > >>> > > Intel Corporation
> > >>> >
> > >>> > --
> > >>> > Ville Syrjälä
> > >>> > Intel
> > >>>
> > >>> --
> > >>> Ville Syrjälä
> > >>> Intel
> > >>
> > >>--
> > >>Matt Roper
> > >>Graphics Software Engineer
> > >>Linux GPU Platform Enablement
> > >>Intel Corporation
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2023-12-20 21:13 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-11-24 20:55 [Intel-gfx] [PATCH] drm/i915/cdclk: Remove divider field from tables Gustavo Sousa
2023-11-24 21:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2023-11-26 4:12 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-11-27 16:21 ` [Intel-gfx] [PATCH] " Matt Roper
2023-11-28 8:43 ` Ville Syrjälä
2023-11-28 8:53 ` Lisovskiy, Stanislav
2023-11-28 9:01 ` Ville Syrjälä
2023-11-28 9:51 ` Ville Syrjälä
2023-11-28 11:52 ` Ville Syrjälä
2023-12-01 23:07 ` Matt Roper
2023-12-04 14:04 ` Gustavo Sousa
2023-12-04 14:13 ` Gustavo Sousa
2023-12-14 0:07 ` Matt Roper
2023-12-20 21:13 ` Matt Roper
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