* [PATCH v2 0/3] arm64: dts: imx93: add i.Core MX93 EDIMM 2.0 board
@ 2024-04-18 13:39 ` Fabio Aiuto
0 siblings, 0 replies; 20+ messages in thread
From: Fabio Aiuto @ 2024-04-18 13:39 UTC (permalink / raw)
To: Shawn Guo, Sascha Hauer, Krzysztof Kozlowski, Rob Herring, Conor Dooley
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Fabio Aiuto
Hello all,
this patchset adds support for i.Core MX93 EDIMM 2.0 Starter Kit,
a SoM + Evaluation Board combination from Engicam.
The number of patch has diminished to 3, for I dropped the
patch introducing a change in nxp,pca9450 binding which has
been already submitted in regulator tree.
(Dropped also regulator tree maintainers as recipients for
they aren't anymore involved in this patchset)
Thanks in advance,
fabio
---
v1 ---> v2:
- dropped patch updating nxp,pca9450 binding
- fixed indentation issue
- fixed missing space issue
- improved naming of regulator nodes
- removed unneeded include
- fixed email recipients
Fabio Aiuto (3):
dt-bindings: arm: fsl: add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
arm64: dts: imx93: add Engicam i.Core MX93 SoM
arm64: dts: imx93: Add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
.../devicetree/bindings/arm/fsl.yaml | 7 +
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../dts/freescale/imx93-icore-mx93-edimm2.dts | 354 ++++++++++++++++++
.../boot/dts/freescale/imx93-icore-mx93.dtsi | 270 +++++++++++++
4 files changed, 632 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 0/3] arm64: dts: imx93: add i.Core MX93 EDIMM 2.0 board
@ 2024-04-18 13:39 ` Fabio Aiuto
0 siblings, 0 replies; 20+ messages in thread
From: Fabio Aiuto @ 2024-04-18 13:39 UTC (permalink / raw)
To: Shawn Guo, Sascha Hauer, Krzysztof Kozlowski, Rob Herring, Conor Dooley
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Fabio Aiuto
Hello all,
this patchset adds support for i.Core MX93 EDIMM 2.0 Starter Kit,
a SoM + Evaluation Board combination from Engicam.
The number of patch has diminished to 3, for I dropped the
patch introducing a change in nxp,pca9450 binding which has
been already submitted in regulator tree.
(Dropped also regulator tree maintainers as recipients for
they aren't anymore involved in this patchset)
Thanks in advance,
fabio
---
v1 ---> v2:
- dropped patch updating nxp,pca9450 binding
- fixed indentation issue
- fixed missing space issue
- improved naming of regulator nodes
- removed unneeded include
- fixed email recipients
Fabio Aiuto (3):
dt-bindings: arm: fsl: add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
arm64: dts: imx93: add Engicam i.Core MX93 SoM
arm64: dts: imx93: Add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
.../devicetree/bindings/arm/fsl.yaml | 7 +
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../dts/freescale/imx93-icore-mx93-edimm2.dts | 354 ++++++++++++++++++
.../boot/dts/freescale/imx93-icore-mx93.dtsi | 270 +++++++++++++
4 files changed, 632 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 1/3] dt-bindings: arm: fsl: add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
2024-04-18 13:39 ` Fabio Aiuto
@ 2024-04-18 13:39 ` Fabio Aiuto
-1 siblings, 0 replies; 20+ messages in thread
From: Fabio Aiuto @ 2024-04-18 13:39 UTC (permalink / raw)
To: Shawn Guo, Sascha Hauer, Krzysztof Kozlowski, Rob Herring, Conor Dooley
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Fabio Aiuto,
Matteo Lisi, Mirko Ardinghi
i.Core MX93 is a NXP i.MX93 based EDIMM SoM by Engicam.
EDIMM 2.0 Starter Kit is an EDIMM 2.0 Form Factor Capacitive
Evaluation Board by Engicam.
i.Core MX93 needs to be mounted on top of EDIMM 2.0 Starter Kit
to get the full i.Core MX93 EDIMM 2.0 Starter Kit board.
Add bindings for this board.
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Mirko Ardinghi <mirko.ardinghi@engicam.com>
Signed-off-by: Fabio Aiuto <fabio.aiuto@engicam.com>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 0027201e19f8..b497a01c7418 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1265,6 +1265,13 @@ properties:
- fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board
- const: fsl,imx93
+ - description: Engicam i.Core MX93 based Boards
+ items:
+ - enum:
+ - engicam,icore-mx93-edimm2 # i.MX93 Engicam i.Core MX93 EDIMM 2.0 Starter Kit
+ - const: engicam,icore-mx93 # i.MX93 Engicam i.Core MX93 Som
+ - const: fsl,imx93
+
- description: i.MXRT1050 based Boards
items:
- enum:
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 1/3] dt-bindings: arm: fsl: add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
@ 2024-04-18 13:39 ` Fabio Aiuto
0 siblings, 0 replies; 20+ messages in thread
From: Fabio Aiuto @ 2024-04-18 13:39 UTC (permalink / raw)
To: Shawn Guo, Sascha Hauer, Krzysztof Kozlowski, Rob Herring, Conor Dooley
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Fabio Aiuto,
Matteo Lisi, Mirko Ardinghi
i.Core MX93 is a NXP i.MX93 based EDIMM SoM by Engicam.
EDIMM 2.0 Starter Kit is an EDIMM 2.0 Form Factor Capacitive
Evaluation Board by Engicam.
i.Core MX93 needs to be mounted on top of EDIMM 2.0 Starter Kit
to get the full i.Core MX93 EDIMM 2.0 Starter Kit board.
Add bindings for this board.
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Mirko Ardinghi <mirko.ardinghi@engicam.com>
Signed-off-by: Fabio Aiuto <fabio.aiuto@engicam.com>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 0027201e19f8..b497a01c7418 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1265,6 +1265,13 @@ properties:
- fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board
- const: fsl,imx93
+ - description: Engicam i.Core MX93 based Boards
+ items:
+ - enum:
+ - engicam,icore-mx93-edimm2 # i.MX93 Engicam i.Core MX93 EDIMM 2.0 Starter Kit
+ - const: engicam,icore-mx93 # i.MX93 Engicam i.Core MX93 Som
+ - const: fsl,imx93
+
- description: i.MXRT1050 based Boards
items:
- enum:
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 2/3] arm64: dts: imx93: add Engicam i.Core MX93 SoM
2024-04-18 13:39 ` Fabio Aiuto
@ 2024-04-18 13:39 ` Fabio Aiuto
-1 siblings, 0 replies; 20+ messages in thread
From: Fabio Aiuto @ 2024-04-18 13:39 UTC (permalink / raw)
To: Shawn Guo, Sascha Hauer, Krzysztof Kozlowski, Rob Herring, Conor Dooley
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Fabio Aiuto,
Matteo Lisi, Mirko Ardinghi
i.Core MX93 is a NXP i.MX93 based EDIMM SoM
by Engicam.
Main features:
CPU: NXP i.MX 93
MEMORY: Up to 2GB LPDDR4
NETWORKING: 2x Gb Ethernet
USB: USB OTG 2.0, USB HOST 2.0
STORAGE: eMMC starting from 4GB
PERIPHERALS: UART, I2C, SPI, CAN, SDIO, GPIO
The i.Core MX93 needs to be mounted on top of
Engicam baseboards to work.
Add devicetree include file.
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Mirko Ardinghi <mirko.ardinghi@engicam.com>
Signed-off-by: Fabio Aiuto <fabio.aiuto@engicam.com>
---
.../boot/dts/freescale/imx93-icore-mx93.dtsi | 270 ++++++++++++++++++
1 file changed, 270 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi b/arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi
new file mode 100644
index 000000000000..c4bed6da389d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 NXP
+ * Copyright 2024 Engicam s.r.l.
+ */
+
+/dts-v1/;
+
+#include "imx93.dtsi"
+
+/ {
+ model = "Engicam i.Core MX93 SoM";
+ compatible = "engicam,icore-mx93", "fsl,imx93";
+
+ reg_vref_1v8: regulator-adc-vref {
+ compatible = "regulator-fixed";
+ regulator-name = "vref_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+};
+
+&adc1 {
+ vref-supply = <®_vref_1v8>;
+ status = "okay";
+};
+
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy1>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy2>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy2: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+ };
+};
+
+&lpi2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ pinctrl-1 = <&pinctrl_lpi2c2>;
+ status = "okay";
+
+ pmic@25 {
+ compatible = "nxp,pca9451a";
+ reg = <0x25>;
+
+ interrupt-parent = <&gpio2>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ buck1: BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4: BUCK4{
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5: BUCK5{
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6: BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1: LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2: LDO2 {
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3: LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4: LDO4 {
+ regulator-name = "LDO4";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5: LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1>;
+ pinctrl-2 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc2 {/*SD Card*/
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ no-1-8-v;
+ max-frequency = <25000000>;
+ status = "okay";
+};
+
+&iomuxc {
+
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x53e
+ MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x53e
+ MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x53e
+ MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x53e
+ MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x53e
+ MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x53e
+ MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x53e
+ MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x53e
+ MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x53e
+ MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x53e
+ MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x53e
+ MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x53e
+ MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x53e
+ MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x53e
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
+ MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
+ MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
+ MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
+ MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
+ MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
+ MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
+ MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
+ MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
+ MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
+ MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
+ MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
+ MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe
+ MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <
+ MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
+ MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x170e
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x130e
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x130e
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x130e
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x130e
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x130e
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
+ >;
+ };
+};
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 2/3] arm64: dts: imx93: add Engicam i.Core MX93 SoM
@ 2024-04-18 13:39 ` Fabio Aiuto
0 siblings, 0 replies; 20+ messages in thread
From: Fabio Aiuto @ 2024-04-18 13:39 UTC (permalink / raw)
To: Shawn Guo, Sascha Hauer, Krzysztof Kozlowski, Rob Herring, Conor Dooley
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Fabio Aiuto,
Matteo Lisi, Mirko Ardinghi
i.Core MX93 is a NXP i.MX93 based EDIMM SoM
by Engicam.
Main features:
CPU: NXP i.MX 93
MEMORY: Up to 2GB LPDDR4
NETWORKING: 2x Gb Ethernet
USB: USB OTG 2.0, USB HOST 2.0
STORAGE: eMMC starting from 4GB
PERIPHERALS: UART, I2C, SPI, CAN, SDIO, GPIO
The i.Core MX93 needs to be mounted on top of
Engicam baseboards to work.
Add devicetree include file.
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Mirko Ardinghi <mirko.ardinghi@engicam.com>
Signed-off-by: Fabio Aiuto <fabio.aiuto@engicam.com>
---
.../boot/dts/freescale/imx93-icore-mx93.dtsi | 270 ++++++++++++++++++
1 file changed, 270 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi b/arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi
new file mode 100644
index 000000000000..c4bed6da389d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 NXP
+ * Copyright 2024 Engicam s.r.l.
+ */
+
+/dts-v1/;
+
+#include "imx93.dtsi"
+
+/ {
+ model = "Engicam i.Core MX93 SoM";
+ compatible = "engicam,icore-mx93", "fsl,imx93";
+
+ reg_vref_1v8: regulator-adc-vref {
+ compatible = "regulator-fixed";
+ regulator-name = "vref_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+};
+
+&adc1 {
+ vref-supply = <®_vref_1v8>;
+ status = "okay";
+};
+
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy1>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy2>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy2: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+ };
+};
+
+&lpi2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ pinctrl-1 = <&pinctrl_lpi2c2>;
+ status = "okay";
+
+ pmic@25 {
+ compatible = "nxp,pca9451a";
+ reg = <0x25>;
+
+ interrupt-parent = <&gpio2>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ buck1: BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4: BUCK4{
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5: BUCK5{
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6: BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1: LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2: LDO2 {
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3: LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4: LDO4 {
+ regulator-name = "LDO4";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5: LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1>;
+ pinctrl-2 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc2 {/*SD Card*/
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ no-1-8-v;
+ max-frequency = <25000000>;
+ status = "okay";
+};
+
+&iomuxc {
+
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x53e
+ MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x53e
+ MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x53e
+ MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x53e
+ MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x53e
+ MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x53e
+ MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x53e
+ MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x53e
+ MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x53e
+ MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x53e
+ MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x53e
+ MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x53e
+ MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x53e
+ MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x53e
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
+ MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
+ MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
+ MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
+ MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
+ MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
+ MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
+ MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
+ MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
+ MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
+ MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
+ MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
+ MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe
+ MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <
+ MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
+ MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x170e
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x130e
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x130e
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x130e
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x130e
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x130e
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
+ >;
+ };
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 3/3] arm64: dts: imx93: Add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
2024-04-18 13:39 ` Fabio Aiuto
@ 2024-04-18 13:39 ` Fabio Aiuto
-1 siblings, 0 replies; 20+ messages in thread
From: Fabio Aiuto @ 2024-04-18 13:39 UTC (permalink / raw)
To: Shawn Guo, Sascha Hauer, Krzysztof Kozlowski, Rob Herring, Conor Dooley
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Fabio Aiuto,
Matteo Lisi, Mirko Ardinghi
i.Core MX93 is a NXP i.MX93 based SoM by Enigcam which
needs to be mounted on top of Engicam baseboards.
Add support for EDIMM 2.0 Starter Kit hosting
i.Core MX93.
Starter Kit main features:
2x LVDS interfaces
HDMI output
Audio out
Mic in
Micro SD card slot
USB 3.0 A port
3x USB 2.0 A port
Gb Ethernet
2x CAN bus, 3x UART interfaces
SIM card slot
M.2 KEY_B slot
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Mirko Ardinghi <mirko.ardinghi@engicam.com>
Signed-off-by: Fabio Aiuto <fabio.aiuto@engicam.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../dts/freescale/imx93-icore-mx93-edimm2.dts | 354 ++++++++++++++++++
2 files changed, 355 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 045250d0a040..d26c0a458a44 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -226,6 +226,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx93-icore-mx93-edimm2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts b/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
new file mode 100644
index 000000000000..8d57374eebdf
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
@@ -0,0 +1,354 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 NXP
+ * Copyright 2024 Engicam s.r.l.
+ */
+
+/dts-v1/;
+
+#include "imx93-icore-mx93.dtsi"
+
+/ {
+ model = "Engicam i.Core MX93 - EDIMM 2 Starterkit";
+ compatible = "engicam,icore-mx93-edimm2", "engicam,icore-mx93",
+ "fsl,imx93";
+
+ aliases {
+ rtc1 = &bbnsm_rtc;
+ };
+
+ bt_reg_on: regulator-btregon {
+ compatible = "regulator-gpio";
+ regulator-name = "BT_REG_ON";
+ pinctrl-names = "default";
+ regulator-min-microvolt = <100000>;
+ regulator-max-microvolt = <3300000>;
+ states = <3300000 0x1>, <100000 0x0>;
+ gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ };
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ reg_1v8_sgtl: regulator-1v8-sgtl {
+ compatible = "regulator-fixed";
+ regulator-name = "1v8_sgtl";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ always-on;
+ };
+
+ reg_3v3_avdd_sgtl: regulator-3v3-avdd-sgtl {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3_avdd_sgtl";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ always-on;
+ };
+
+ reg_3v3_sgtl: regulator-3v3-sgtl {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3_sgtl";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ always-on;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ alloc-ranges = <0 0x80000000 0 0x40000000>;
+ size = <0 0x10000000>;
+ linux,cma-default;
+ };
+
+ rsc_table: rsc-table@2021f000 {
+ reg = <0 0x2021f000 0 0x1000>;
+ no-map;
+ };
+
+ vdevbuffer: vdevbuffer@a4020000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xa4020000 0 0x100000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@a4000000 {
+ reg = <0 0xa4000000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@a4008000 {
+ reg = <0 0xa4008000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring0: vdev1vring0@a4000000 {
+ reg = <0 0xa4010000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring1: vdev1vring1@a4018000 {
+ reg = <0 0xa4018000 0 0x8000>;
+ no-map;
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "imx93-sgtl5000";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,frame-master = <&dailink_master>;
+ /*simple-audio-card,mclk-fs = <1>;*/
+ simple-audio-card,cpu {
+ sound-dai = <&sai3>;
+ };
+
+ dailink_master: simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ clocks = <&clk IMX93_CLK_SAI3_IPG>;
+ };
+ };
+
+ usdhc3_pwrseq: usdhc3-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ };
+
+ wl_reg_on: regulator-wlregon {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ regulator-name = "WL_REG_ON";
+ regulator-min-microvolt = <100000>;
+ regulator-max-microvolt = <3300000>;
+ states = <3300000 0x1>,
+ <100000 0x0>;
+ gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&bt_reg_on>;
+ };
+};
+
+&cm33 {
+ mbox-names = "tx", "rx", "rxdb";
+ mboxes = <&mu1 0 1>,
+ <&mu1 1 1>,
+ <&mu1 3 1>;
+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
+ <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
+ status = "okay";
+};
+
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ fsl,stop-mode = <&aonmix_ns_gpr 0x10 4>;
+ status = "okay";
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ fsl,stop-mode = <&aonmix_ns_gpr 0x10 4>;
+ status = "okay";
+};
+
+&lpi2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+ pinctrl-1 = <&pinctrl_lpi2c1>;
+ status = "okay";
+
+ pcf8523: rtc@68 {
+ compatible = "nxp,pcf8523";
+ reg = <0x68>;
+ };
+
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ status = "okay";
+ #sound-dai-cells = <0>;
+ reg = <0x0a>;
+ clocks = <&clk IMX93_CLK_SAI3_GATE>;
+ clock-names = "mclk";
+ assigned-clock-rates = <12000000>, <12000000>;
+ VDDA-supply = <®_3v3_avdd_sgtl>;
+ VDDIO-supply = <®_3v3_sgtl>;
+ VDDD-supply = <®_1v8_sgtl>;
+ };
+};
+
+&lpuart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&lpuart5 { /* RS485 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ status = "okay";
+};
+
+&lpuart8 { /* RS232 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart8>;
+ status = "okay";
+};
+
+&micfil {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ assigned-clocks = <&clk IMX93_CLK_PDM>;
+ assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
+ assigned-clock-rates = <196608000>;
+ status = "okay";
+};
+
+&mu1 {
+ status = "okay";
+};
+
+&mu2 {
+ status = "okay";
+};
+
+&sai1 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai1>;
+ assigned-clocks = <&clk IMX93_CLK_SAI1>;
+ assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
+ assigned-clock-rates = <12288000>;
+ status = "okay";
+};
+
+&sai3 {
+ pinctrl-names = "default";
+ #sound-dai-cells = <0>;
+ pinctrl-0 = <&pinctrl_sai3>;
+ assigned-clocks = <&clk IMX93_CLK_SAI3>;
+ assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
+ assigned-clock-rates = <24576000>;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
+&usdhc3 { /* WiFi */
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
+ pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
+ pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
+ vmmc-supply = <&wl_reg_on>;
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ max-frequency = <25000000>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+&wdog3 {
+ status = "okay";
+};
+
+&iomuxc {
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX93_PAD_PDM_CLK__CAN1_TX 0x139e
+ MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
+ MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
+ >;
+ };
+
+ pinctrl_laird: lairdgrp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e // WL_REG_ON
+ MX93_PAD_GPIO_IO19__GPIO2_IO19 0x31e // BT_REG_ON
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
+ MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_sai1: sai1grp {
+ fsl,pins = <
+ MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e
+ MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e
+ MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e
+ MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e
+ >;
+ };
+
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e
+ MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e
+ MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e
+ MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x31e
+ MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
+ MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO01__LPUART5_RX 0x31e
+ MX93_PAD_GPIO_IO00__LPUART5_TX 0x31e
+ MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x31e
+ MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x31e
+ >;
+ };
+
+ pinctrl_uart8: uart8grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO13__LPUART8_RX 0x31e
+ MX93_PAD_GPIO_IO12__LPUART8_TX 0x31e
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX93_PAD_SD3_CLK__USDHC3_CLK 0x17fe
+ MX93_PAD_SD3_CMD__USDHC3_CMD 0x13fe
+ MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
+ MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
+ MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
+ MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
+ >;
+ };
+};
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 3/3] arm64: dts: imx93: Add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
@ 2024-04-18 13:39 ` Fabio Aiuto
0 siblings, 0 replies; 20+ messages in thread
From: Fabio Aiuto @ 2024-04-18 13:39 UTC (permalink / raw)
To: Shawn Guo, Sascha Hauer, Krzysztof Kozlowski, Rob Herring, Conor Dooley
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Fabio Aiuto,
Matteo Lisi, Mirko Ardinghi
i.Core MX93 is a NXP i.MX93 based SoM by Enigcam which
needs to be mounted on top of Engicam baseboards.
Add support for EDIMM 2.0 Starter Kit hosting
i.Core MX93.
Starter Kit main features:
2x LVDS interfaces
HDMI output
Audio out
Mic in
Micro SD card slot
USB 3.0 A port
3x USB 2.0 A port
Gb Ethernet
2x CAN bus, 3x UART interfaces
SIM card slot
M.2 KEY_B slot
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Mirko Ardinghi <mirko.ardinghi@engicam.com>
Signed-off-by: Fabio Aiuto <fabio.aiuto@engicam.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../dts/freescale/imx93-icore-mx93-edimm2.dts | 354 ++++++++++++++++++
2 files changed, 355 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 045250d0a040..d26c0a458a44 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -226,6 +226,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx93-icore-mx93-edimm2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts b/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
new file mode 100644
index 000000000000..8d57374eebdf
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
@@ -0,0 +1,354 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 NXP
+ * Copyright 2024 Engicam s.r.l.
+ */
+
+/dts-v1/;
+
+#include "imx93-icore-mx93.dtsi"
+
+/ {
+ model = "Engicam i.Core MX93 - EDIMM 2 Starterkit";
+ compatible = "engicam,icore-mx93-edimm2", "engicam,icore-mx93",
+ "fsl,imx93";
+
+ aliases {
+ rtc1 = &bbnsm_rtc;
+ };
+
+ bt_reg_on: regulator-btregon {
+ compatible = "regulator-gpio";
+ regulator-name = "BT_REG_ON";
+ pinctrl-names = "default";
+ regulator-min-microvolt = <100000>;
+ regulator-max-microvolt = <3300000>;
+ states = <3300000 0x1>, <100000 0x0>;
+ gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ };
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ reg_1v8_sgtl: regulator-1v8-sgtl {
+ compatible = "regulator-fixed";
+ regulator-name = "1v8_sgtl";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ always-on;
+ };
+
+ reg_3v3_avdd_sgtl: regulator-3v3-avdd-sgtl {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3_avdd_sgtl";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ always-on;
+ };
+
+ reg_3v3_sgtl: regulator-3v3-sgtl {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3_sgtl";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ always-on;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ alloc-ranges = <0 0x80000000 0 0x40000000>;
+ size = <0 0x10000000>;
+ linux,cma-default;
+ };
+
+ rsc_table: rsc-table@2021f000 {
+ reg = <0 0x2021f000 0 0x1000>;
+ no-map;
+ };
+
+ vdevbuffer: vdevbuffer@a4020000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xa4020000 0 0x100000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@a4000000 {
+ reg = <0 0xa4000000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@a4008000 {
+ reg = <0 0xa4008000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring0: vdev1vring0@a4000000 {
+ reg = <0 0xa4010000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring1: vdev1vring1@a4018000 {
+ reg = <0 0xa4018000 0 0x8000>;
+ no-map;
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "imx93-sgtl5000";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,frame-master = <&dailink_master>;
+ /*simple-audio-card,mclk-fs = <1>;*/
+ simple-audio-card,cpu {
+ sound-dai = <&sai3>;
+ };
+
+ dailink_master: simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ clocks = <&clk IMX93_CLK_SAI3_IPG>;
+ };
+ };
+
+ usdhc3_pwrseq: usdhc3-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ };
+
+ wl_reg_on: regulator-wlregon {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ regulator-name = "WL_REG_ON";
+ regulator-min-microvolt = <100000>;
+ regulator-max-microvolt = <3300000>;
+ states = <3300000 0x1>,
+ <100000 0x0>;
+ gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <&bt_reg_on>;
+ };
+};
+
+&cm33 {
+ mbox-names = "tx", "rx", "rxdb";
+ mboxes = <&mu1 0 1>,
+ <&mu1 1 1>,
+ <&mu1 3 1>;
+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
+ <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
+ status = "okay";
+};
+
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ fsl,stop-mode = <&aonmix_ns_gpr 0x10 4>;
+ status = "okay";
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ fsl,stop-mode = <&aonmix_ns_gpr 0x10 4>;
+ status = "okay";
+};
+
+&lpi2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+ pinctrl-1 = <&pinctrl_lpi2c1>;
+ status = "okay";
+
+ pcf8523: rtc@68 {
+ compatible = "nxp,pcf8523";
+ reg = <0x68>;
+ };
+
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ status = "okay";
+ #sound-dai-cells = <0>;
+ reg = <0x0a>;
+ clocks = <&clk IMX93_CLK_SAI3_GATE>;
+ clock-names = "mclk";
+ assigned-clock-rates = <12000000>, <12000000>;
+ VDDA-supply = <®_3v3_avdd_sgtl>;
+ VDDIO-supply = <®_3v3_sgtl>;
+ VDDD-supply = <®_1v8_sgtl>;
+ };
+};
+
+&lpuart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&lpuart5 { /* RS485 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ status = "okay";
+};
+
+&lpuart8 { /* RS232 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart8>;
+ status = "okay";
+};
+
+&micfil {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ assigned-clocks = <&clk IMX93_CLK_PDM>;
+ assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
+ assigned-clock-rates = <196608000>;
+ status = "okay";
+};
+
+&mu1 {
+ status = "okay";
+};
+
+&mu2 {
+ status = "okay";
+};
+
+&sai1 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai1>;
+ assigned-clocks = <&clk IMX93_CLK_SAI1>;
+ assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
+ assigned-clock-rates = <12288000>;
+ status = "okay";
+};
+
+&sai3 {
+ pinctrl-names = "default";
+ #sound-dai-cells = <0>;
+ pinctrl-0 = <&pinctrl_sai3>;
+ assigned-clocks = <&clk IMX93_CLK_SAI3>;
+ assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
+ assigned-clock-rates = <24576000>;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
+&usdhc3 { /* WiFi */
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
+ pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
+ pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
+ vmmc-supply = <&wl_reg_on>;
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ max-frequency = <25000000>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
+
+&wdog3 {
+ status = "okay";
+};
+
+&iomuxc {
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX93_PAD_PDM_CLK__CAN1_TX 0x139e
+ MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
+ MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
+ >;
+ };
+
+ pinctrl_laird: lairdgrp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e // WL_REG_ON
+ MX93_PAD_GPIO_IO19__GPIO2_IO19 0x31e // BT_REG_ON
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
+ MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_sai1: sai1grp {
+ fsl,pins = <
+ MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e
+ MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e
+ MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e
+ MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e
+ >;
+ };
+
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e
+ MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e
+ MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e
+ MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x31e
+ MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
+ MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO01__LPUART5_RX 0x31e
+ MX93_PAD_GPIO_IO00__LPUART5_TX 0x31e
+ MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x31e
+ MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x31e
+ >;
+ };
+
+ pinctrl_uart8: uart8grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO13__LPUART8_RX 0x31e
+ MX93_PAD_GPIO_IO12__LPUART8_TX 0x31e
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX93_PAD_SD3_CLK__USDHC3_CLK 0x17fe
+ MX93_PAD_SD3_CMD__USDHC3_CMD 0x13fe
+ MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
+ MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
+ MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
+ MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
+ >;
+ };
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: arm: fsl: add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
2024-04-18 13:39 ` Fabio Aiuto
@ 2024-04-18 15:33 ` Conor Dooley
-1 siblings, 0 replies; 20+ messages in thread
From: Conor Dooley @ 2024-04-18 15:33 UTC (permalink / raw)
To: Fabio Aiuto
Cc: Shawn Guo, Sascha Hauer, Krzysztof Kozlowski, Rob Herring,
Conor Dooley, devicetree, imx, linux-arm-kernel, linux-kernel,
Matteo Lisi, Mirko Ardinghi
[-- Attachment #1: Type: text/plain, Size: 1584 bytes --]
On Thu, Apr 18, 2024 at 03:39:21PM +0200, Fabio Aiuto wrote:
> i.Core MX93 is a NXP i.MX93 based EDIMM SoM by Engicam.
>
> EDIMM 2.0 Starter Kit is an EDIMM 2.0 Form Factor Capacitive
> Evaluation Board by Engicam.
>
> i.Core MX93 needs to be mounted on top of EDIMM 2.0 Starter Kit
> to get the full i.Core MX93 EDIMM 2.0 Starter Kit board.
>
> Add bindings for this board.
>
> Cc: Matteo Lisi <matteo.lisi@engicam.com>
> Cc: Mirko Ardinghi <mirko.ardinghi@engicam.com>
> Signed-off-by: Fabio Aiuto <fabio.aiuto@engicam.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
> ---
> Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> index 0027201e19f8..b497a01c7418 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> @@ -1265,6 +1265,13 @@ properties:
> - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board
> - const: fsl,imx93
>
> + - description: Engicam i.Core MX93 based Boards
> + items:
> + - enum:
> + - engicam,icore-mx93-edimm2 # i.MX93 Engicam i.Core MX93 EDIMM 2.0 Starter Kit
> + - const: engicam,icore-mx93 # i.MX93 Engicam i.Core MX93 Som
> + - const: fsl,imx93
> +
> - description: i.MXRT1050 based Boards
> items:
> - enum:
> --
> 2.34.1
>
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: arm: fsl: add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
@ 2024-04-18 15:33 ` Conor Dooley
0 siblings, 0 replies; 20+ messages in thread
From: Conor Dooley @ 2024-04-18 15:33 UTC (permalink / raw)
To: Fabio Aiuto
Cc: Shawn Guo, Sascha Hauer, Krzysztof Kozlowski, Rob Herring,
Conor Dooley, devicetree, imx, linux-arm-kernel, linux-kernel,
Matteo Lisi, Mirko Ardinghi
[-- Attachment #1.1: Type: text/plain, Size: 1584 bytes --]
On Thu, Apr 18, 2024 at 03:39:21PM +0200, Fabio Aiuto wrote:
> i.Core MX93 is a NXP i.MX93 based EDIMM SoM by Engicam.
>
> EDIMM 2.0 Starter Kit is an EDIMM 2.0 Form Factor Capacitive
> Evaluation Board by Engicam.
>
> i.Core MX93 needs to be mounted on top of EDIMM 2.0 Starter Kit
> to get the full i.Core MX93 EDIMM 2.0 Starter Kit board.
>
> Add bindings for this board.
>
> Cc: Matteo Lisi <matteo.lisi@engicam.com>
> Cc: Mirko Ardinghi <mirko.ardinghi@engicam.com>
> Signed-off-by: Fabio Aiuto <fabio.aiuto@engicam.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
> ---
> Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> index 0027201e19f8..b497a01c7418 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> @@ -1265,6 +1265,13 @@ properties:
> - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board
> - const: fsl,imx93
>
> + - description: Engicam i.Core MX93 based Boards
> + items:
> + - enum:
> + - engicam,icore-mx93-edimm2 # i.MX93 Engicam i.Core MX93 EDIMM 2.0 Starter Kit
> + - const: engicam,icore-mx93 # i.MX93 Engicam i.Core MX93 Som
> + - const: fsl,imx93
> +
> - description: i.MXRT1050 based Boards
> items:
> - enum:
> --
> 2.34.1
>
[-- Attachment #1.2: signature.asc --]
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_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: arm: fsl: add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
2024-04-18 15:33 ` Conor Dooley
@ 2024-04-18 16:34 ` Conor Dooley
-1 siblings, 0 replies; 20+ messages in thread
From: Conor Dooley @ 2024-04-18 16:34 UTC (permalink / raw)
To: Fabio Aiuto
Cc: Shawn Guo, Sascha Hauer, Krzysztof Kozlowski, Rob Herring,
Conor Dooley, devicetree, imx, linux-arm-kernel, linux-kernel,
Matteo Lisi, Mirko Ardinghi
[-- Attachment #1: Type: text/plain, Size: 864 bytes --]
On Thu, Apr 18, 2024 at 04:33:21PM +0100, Conor Dooley wrote:
> On Thu, Apr 18, 2024 at 03:39:21PM +0200, Fabio Aiuto wrote:
> > i.Core MX93 is a NXP i.MX93 based EDIMM SoM by Engicam.
> >
> > EDIMM 2.0 Starter Kit is an EDIMM 2.0 Form Factor Capacitive
> > Evaluation Board by Engicam.
> >
> > i.Core MX93 needs to be mounted on top of EDIMM 2.0 Starter Kit
> > to get the full i.Core MX93 EDIMM 2.0 Starter Kit board.
> >
> > Add bindings for this board.
> >
> > Cc: Matteo Lisi <matteo.lisi@engicam.com>
> > Cc: Mirko Ardinghi <mirko.ardinghi@engicam.com>
> > Signed-off-by: Fabio Aiuto <fabio.aiuto@engicam.com>
>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
Looks like you might've already got an Ack from Krzysztof on a previous
version. Please make sure to pick up acks etc when you post new
versions.
Thanks,
Conor.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: arm: fsl: add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
@ 2024-04-18 16:34 ` Conor Dooley
0 siblings, 0 replies; 20+ messages in thread
From: Conor Dooley @ 2024-04-18 16:34 UTC (permalink / raw)
To: Fabio Aiuto
Cc: Shawn Guo, Sascha Hauer, Krzysztof Kozlowski, Rob Herring,
Conor Dooley, devicetree, imx, linux-arm-kernel, linux-kernel,
Matteo Lisi, Mirko Ardinghi
[-- Attachment #1.1: Type: text/plain, Size: 864 bytes --]
On Thu, Apr 18, 2024 at 04:33:21PM +0100, Conor Dooley wrote:
> On Thu, Apr 18, 2024 at 03:39:21PM +0200, Fabio Aiuto wrote:
> > i.Core MX93 is a NXP i.MX93 based EDIMM SoM by Engicam.
> >
> > EDIMM 2.0 Starter Kit is an EDIMM 2.0 Form Factor Capacitive
> > Evaluation Board by Engicam.
> >
> > i.Core MX93 needs to be mounted on top of EDIMM 2.0 Starter Kit
> > to get the full i.Core MX93 EDIMM 2.0 Starter Kit board.
> >
> > Add bindings for this board.
> >
> > Cc: Matteo Lisi <matteo.lisi@engicam.com>
> > Cc: Mirko Ardinghi <mirko.ardinghi@engicam.com>
> > Signed-off-by: Fabio Aiuto <fabio.aiuto@engicam.com>
>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
Looks like you might've already got an Ack from Krzysztof on a previous
version. Please make sure to pick up acks etc when you post new
versions.
Thanks,
Conor.
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 0/3] arm64: dts: imx93: add i.Core MX93 EDIMM 2.0 board
2024-04-18 13:39 ` Fabio Aiuto
@ 2024-04-18 18:29 ` Rob Herring
-1 siblings, 0 replies; 20+ messages in thread
From: Rob Herring @ 2024-04-18 18:29 UTC (permalink / raw)
To: Fabio Aiuto
Cc: Sascha Hauer, linux-kernel, Conor Dooley, linux-arm-kernel,
Krzysztof Kozlowski, devicetree, Shawn Guo, imx
On Thu, 18 Apr 2024 15:39:20 +0200, Fabio Aiuto wrote:
> Hello all,
>
> this patchset adds support for i.Core MX93 EDIMM 2.0 Starter Kit,
> a SoM + Evaluation Board combination from Engicam.
>
> The number of patch has diminished to 3, for I dropped the
> patch introducing a change in nxp,pca9450 binding which has
> been already submitted in regulator tree.
>
> (Dropped also regulator tree maintainers as recipients for
> they aren't anymore involved in this patchset)
>
> Thanks in advance,
>
> fabio
> ---
> v1 ---> v2:
> - dropped patch updating nxp,pca9450 binding
> - fixed indentation issue
> - fixed missing space issue
> - improved naming of regulator nodes
> - removed unneeded include
> - fixed email recipients
>
> Fabio Aiuto (3):
> dt-bindings: arm: fsl: add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
> arm64: dts: imx93: add Engicam i.Core MX93 SoM
> arm64: dts: imx93: Add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
>
> .../devicetree/bindings/arm/fsl.yaml | 7 +
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> .../dts/freescale/imx93-icore-mx93-edimm2.dts | 354 ++++++++++++++++++
> .../boot/dts/freescale/imx93-icore-mx93.dtsi | 270 +++++++++++++
> 4 files changed, 632 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
> create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi
>
> --
> 2.34.1
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y freescale/imx93-icore-mx93-edimm2.dtb' for 20240418133923.3705-1-fabio.aiuto@engicam.com:
arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dtb: codec@a: Unevaluated properties are not allowed ('clock-names' was unexpected)
from schema $id: http://devicetree.org/schemas/sound/sgtl5000.yaml#
arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dtb: codec@a: 'assigned-clocks' is a dependency of 'assigned-clock-rates'
from schema $id: http://devicetree.org/schemas/clock/clock.yaml#
arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dtb: micfil@44520000: 'pinctrl-0' is a dependency of 'pinctrl-names'
from schema $id: http://devicetree.org/schemas/pinctrl/pinctrl-consumer.yaml#
arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dtb: regulator-btregon: 'pinctrl-0' is a dependency of 'pinctrl-names'
from schema $id: http://devicetree.org/schemas/pinctrl/pinctrl-consumer.yaml#
arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dtb: regulator-1v8-sgtl: Unevaluated properties are not allowed ('always-on' was unexpected)
from schema $id: http://devicetree.org/schemas/regulator/fixed-regulator.yaml#
arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dtb: regulator-3v3-avdd-sgtl: Unevaluated properties are not allowed ('always-on' was unexpected)
from schema $id: http://devicetree.org/schemas/regulator/fixed-regulator.yaml#
arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dtb: regulator-3v3-sgtl: Unevaluated properties are not allowed ('always-on' was unexpected)
from schema $id: http://devicetree.org/schemas/regulator/fixed-regulator.yaml#
arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dtb: regulator-wlregon: 'pinctrl-0' is a dependency of 'pinctrl-names'
from schema $id: http://devicetree.org/schemas/pinctrl/pinctrl-consumer.yaml#
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 0/3] arm64: dts: imx93: add i.Core MX93 EDIMM 2.0 board
@ 2024-04-18 18:29 ` Rob Herring
0 siblings, 0 replies; 20+ messages in thread
From: Rob Herring @ 2024-04-18 18:29 UTC (permalink / raw)
To: Fabio Aiuto
Cc: Sascha Hauer, linux-kernel, Conor Dooley, linux-arm-kernel,
Krzysztof Kozlowski, devicetree, Shawn Guo, imx
On Thu, 18 Apr 2024 15:39:20 +0200, Fabio Aiuto wrote:
> Hello all,
>
> this patchset adds support for i.Core MX93 EDIMM 2.0 Starter Kit,
> a SoM + Evaluation Board combination from Engicam.
>
> The number of patch has diminished to 3, for I dropped the
> patch introducing a change in nxp,pca9450 binding which has
> been already submitted in regulator tree.
>
> (Dropped also regulator tree maintainers as recipients for
> they aren't anymore involved in this patchset)
>
> Thanks in advance,
>
> fabio
> ---
> v1 ---> v2:
> - dropped patch updating nxp,pca9450 binding
> - fixed indentation issue
> - fixed missing space issue
> - improved naming of regulator nodes
> - removed unneeded include
> - fixed email recipients
>
> Fabio Aiuto (3):
> dt-bindings: arm: fsl: add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
> arm64: dts: imx93: add Engicam i.Core MX93 SoM
> arm64: dts: imx93: Add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
>
> .../devicetree/bindings/arm/fsl.yaml | 7 +
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> .../dts/freescale/imx93-icore-mx93-edimm2.dts | 354 ++++++++++++++++++
> .../boot/dts/freescale/imx93-icore-mx93.dtsi | 270 +++++++++++++
> 4 files changed, 632 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
> create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi
>
> --
> 2.34.1
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y freescale/imx93-icore-mx93-edimm2.dtb' for 20240418133923.3705-1-fabio.aiuto@engicam.com:
arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dtb: codec@a: Unevaluated properties are not allowed ('clock-names' was unexpected)
from schema $id: http://devicetree.org/schemas/sound/sgtl5000.yaml#
arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dtb: codec@a: 'assigned-clocks' is a dependency of 'assigned-clock-rates'
from schema $id: http://devicetree.org/schemas/clock/clock.yaml#
arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dtb: micfil@44520000: 'pinctrl-0' is a dependency of 'pinctrl-names'
from schema $id: http://devicetree.org/schemas/pinctrl/pinctrl-consumer.yaml#
arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dtb: regulator-btregon: 'pinctrl-0' is a dependency of 'pinctrl-names'
from schema $id: http://devicetree.org/schemas/pinctrl/pinctrl-consumer.yaml#
arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dtb: regulator-1v8-sgtl: Unevaluated properties are not allowed ('always-on' was unexpected)
from schema $id: http://devicetree.org/schemas/regulator/fixed-regulator.yaml#
arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dtb: regulator-3v3-avdd-sgtl: Unevaluated properties are not allowed ('always-on' was unexpected)
from schema $id: http://devicetree.org/schemas/regulator/fixed-regulator.yaml#
arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dtb: regulator-3v3-sgtl: Unevaluated properties are not allowed ('always-on' was unexpected)
from schema $id: http://devicetree.org/schemas/regulator/fixed-regulator.yaml#
arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dtb: regulator-wlregon: 'pinctrl-0' is a dependency of 'pinctrl-names'
from schema $id: http://devicetree.org/schemas/pinctrl/pinctrl-consumer.yaml#
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: arm: fsl: add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
2024-04-18 16:34 ` Conor Dooley
@ 2024-04-19 7:20 ` Fabio Aiuto
-1 siblings, 0 replies; 20+ messages in thread
From: Fabio Aiuto @ 2024-04-19 7:20 UTC (permalink / raw)
To: Conor Dooley
Cc: Shawn Guo, Sascha Hauer, Krzysztof Kozlowski, Rob Herring,
Conor Dooley, devicetree, imx, linux-arm-kernel, linux-kernel,
Matteo Lisi, Mirko Ardinghi
Dear Conor,
Il Thu, Apr 18, 2024 at 05:34:07PM +0100, Conor Dooley ha scritto:
> On Thu, Apr 18, 2024 at 04:33:21PM +0100, Conor Dooley wrote:
> > On Thu, Apr 18, 2024 at 03:39:21PM +0200, Fabio Aiuto wrote:
> > > i.Core MX93 is a NXP i.MX93 based EDIMM SoM by Engicam.
> > >
> > > EDIMM 2.0 Starter Kit is an EDIMM 2.0 Form Factor Capacitive
> > > Evaluation Board by Engicam.
> > >
> > > i.Core MX93 needs to be mounted on top of EDIMM 2.0 Starter Kit
> > > to get the full i.Core MX93 EDIMM 2.0 Starter Kit board.
> > >
> > > Add bindings for this board.
> > >
> > > Cc: Matteo Lisi <matteo.lisi@engicam.com>
> > > Cc: Mirko Ardinghi <mirko.ardinghi@engicam.com>
> > > Signed-off-by: Fabio Aiuto <fabio.aiuto@engicam.com>
> >
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
>
> Looks like you might've already got an Ack from Krzysztof on a previous
> version. Please make sure to pick up acks etc when you post new
> versions.
thanks for your Ack, will send a v3 including both your Ack and Krzysztof's
one.
kr,
fabio
>
> Thanks,
> Conor.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: arm: fsl: add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
@ 2024-04-19 7:20 ` Fabio Aiuto
0 siblings, 0 replies; 20+ messages in thread
From: Fabio Aiuto @ 2024-04-19 7:20 UTC (permalink / raw)
To: Conor Dooley
Cc: Shawn Guo, Sascha Hauer, Krzysztof Kozlowski, Rob Herring,
Conor Dooley, devicetree, imx, linux-arm-kernel, linux-kernel,
Matteo Lisi, Mirko Ardinghi
Dear Conor,
Il Thu, Apr 18, 2024 at 05:34:07PM +0100, Conor Dooley ha scritto:
> On Thu, Apr 18, 2024 at 04:33:21PM +0100, Conor Dooley wrote:
> > On Thu, Apr 18, 2024 at 03:39:21PM +0200, Fabio Aiuto wrote:
> > > i.Core MX93 is a NXP i.MX93 based EDIMM SoM by Engicam.
> > >
> > > EDIMM 2.0 Starter Kit is an EDIMM 2.0 Form Factor Capacitive
> > > Evaluation Board by Engicam.
> > >
> > > i.Core MX93 needs to be mounted on top of EDIMM 2.0 Starter Kit
> > > to get the full i.Core MX93 EDIMM 2.0 Starter Kit board.
> > >
> > > Add bindings for this board.
> > >
> > > Cc: Matteo Lisi <matteo.lisi@engicam.com>
> > > Cc: Mirko Ardinghi <mirko.ardinghi@engicam.com>
> > > Signed-off-by: Fabio Aiuto <fabio.aiuto@engicam.com>
> >
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
>
> Looks like you might've already got an Ack from Krzysztof on a previous
> version. Please make sure to pick up acks etc when you post new
> versions.
thanks for your Ack, will send a v3 including both your Ack and Krzysztof's
one.
kr,
fabio
>
> Thanks,
> Conor.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: imx93: Add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
2024-04-18 13:39 ` Fabio Aiuto
@ 2024-04-19 7:29 ` Michael Nazzareno Trimarchi
-1 siblings, 0 replies; 20+ messages in thread
From: Michael Nazzareno Trimarchi @ 2024-04-19 7:29 UTC (permalink / raw)
To: Fabio Aiuto
Cc: Shawn Guo, Sascha Hauer, Krzysztof Kozlowski, Rob Herring,
Conor Dooley, devicetree, imx, linux-arm-kernel, linux-kernel,
Matteo Lisi, Mirko Ardinghi
Hi Fabio
On Thu, Apr 18, 2024 at 3:43 PM Fabio Aiuto <fabio.aiuto@engicam.com> wrote:
>
> i.Core MX93 is a NXP i.MX93 based SoM by Enigcam which
> needs to be mounted on top of Engicam baseboards.
>
> Add support for EDIMM 2.0 Starter Kit hosting
> i.Core MX93.
>
> Starter Kit main features:
>
> 2x LVDS interfaces
> HDMI output
> Audio out
> Mic in
> Micro SD card slot
> USB 3.0 A port
> 3x USB 2.0 A port
> Gb Ethernet
> 2x CAN bus, 3x UART interfaces
> SIM card slot
> M.2 KEY_B slot
>
> Cc: Matteo Lisi <matteo.lisi@engicam.com>
> Cc: Mirko Ardinghi <mirko.ardinghi@engicam.com>
> Signed-off-by: Fabio Aiuto <fabio.aiuto@engicam.com>
> ---
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> .../dts/freescale/imx93-icore-mx93-edimm2.dts | 354 ++++++++++++++++++
> 2 files changed, 355 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 045250d0a040..d26c0a458a44 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -226,6 +226,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx93-icore-mx93-edimm2.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb
> diff --git a/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts b/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
> new file mode 100644
> index 000000000000..8d57374eebdf
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
> @@ -0,0 +1,354 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2022 NXP
> + * Copyright 2024 Engicam s.r.l.
> + */
> +
> +/dts-v1/;
> +
> +#include "imx93-icore-mx93.dtsi"
> +
> +/ {
> + model = "Engicam i.Core MX93 - EDIMM 2 Starterkit";
> + compatible = "engicam,icore-mx93-edimm2", "engicam,icore-mx93",
> + "fsl,imx93";
> +
> + aliases {
> + rtc1 = &bbnsm_rtc;
> + };
> +
> + bt_reg_on: regulator-btregon {
> + compatible = "regulator-gpio";
> + regulator-name = "BT_REG_ON";
> + pinctrl-names = "default";
> + regulator-min-microvolt = <100000>;
> + regulator-max-microvolt = <3300000>;
> + states = <3300000 0x1>, <100000 0x0>;
> + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> + regulator-always-on;
> + };
> +
Are you sure about regulator always on? I have seen that you broadcom
wifi and bluetooth connected. Same comment for the other
patches where you have almost all the regulator boot on , always on. I
can not be sure that is really true
Please take a look here
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi
Michael
> + chosen {
> + stdout-path = &lpuart1;
> + };
> +
> + reg_1v8_sgtl: regulator-1v8-sgtl {
> + compatible = "regulator-fixed";
> + regulator-name = "1v8_sgtl";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + always-on;
> + };
> +
> + reg_3v3_avdd_sgtl: regulator-3v3-avdd-sgtl {
> + compatible = "regulator-fixed";
> + regulator-name = "3v3_avdd_sgtl";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + always-on;
> + };
> +
> + reg_3v3_sgtl: regulator-3v3-sgtl {
> + compatible = "regulator-fixed";
> + regulator-name = "3v3_sgtl";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + always-on;
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + linux,cma {
> + compatible = "shared-dma-pool";
> + reusable;
> + alloc-ranges = <0 0x80000000 0 0x40000000>;
> + size = <0 0x10000000>;
> + linux,cma-default;
> + };
> +
> + rsc_table: rsc-table@2021f000 {
> + reg = <0 0x2021f000 0 0x1000>;
> + no-map;
> + };
> +
> + vdevbuffer: vdevbuffer@a4020000 {
> + compatible = "shared-dma-pool";
> + reg = <0 0xa4020000 0 0x100000>;
> + no-map;
> + };
> +
> + vdev0vring0: vdev0vring0@a4000000 {
> + reg = <0 0xa4000000 0 0x8000>;
> + no-map;
> + };
> +
> + vdev0vring1: vdev0vring1@a4008000 {
> + reg = <0 0xa4008000 0 0x8000>;
> + no-map;
> + };
> +
> + vdev1vring0: vdev1vring0@a4000000 {
> + reg = <0 0xa4010000 0 0x8000>;
> + no-map;
> + };
> +
> + vdev1vring1: vdev1vring1@a4018000 {
> + reg = <0 0xa4018000 0 0x8000>;
> + no-map;
> + };
> + };
> +
> + sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,name = "imx93-sgtl5000";
> + simple-audio-card,format = "i2s";
> + simple-audio-card,bitclock-master = <&dailink_master>;
> + simple-audio-card,frame-master = <&dailink_master>;
> + /*simple-audio-card,mclk-fs = <1>;*/
> + simple-audio-card,cpu {
> + sound-dai = <&sai3>;
> + };
> +
> + dailink_master: simple-audio-card,codec {
> + sound-dai = <&sgtl5000>;
> + clocks = <&clk IMX93_CLK_SAI3_IPG>;
> + };
> + };
> +
> + usdhc3_pwrseq: usdhc3-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + };
> +
> + wl_reg_on: regulator-wlregon {
> + compatible = "regulator-gpio";
> + pinctrl-names = "default";
> + regulator-name = "WL_REG_ON";
> + regulator-min-microvolt = <100000>;
> + regulator-max-microvolt = <3300000>;
> + states = <3300000 0x1>,
> + <100000 0x0>;
> + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + vin-supply = <&bt_reg_on>;
> + };
> +};
> +
> +&cm33 {
> + mbox-names = "tx", "rx", "rxdb";
> + mboxes = <&mu1 0 1>,
> + <&mu1 1 1>,
> + <&mu1 3 1>;
> + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
> + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
> + status = "okay";
> +};
> +
> +&flexcan1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan1>;
> + fsl,stop-mode = <&aonmix_ns_gpr 0x10 4>;
> + status = "okay";
> +};
> +
> +&flexcan2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan2>;
> + fsl,stop-mode = <&aonmix_ns_gpr 0x10 4>;
> + status = "okay";
> +};
> +
> +&lpi2c1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-frequency = <400000>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&pinctrl_lpi2c1>;
> + pinctrl-1 = <&pinctrl_lpi2c1>;
> + status = "okay";
> +
> + pcf8523: rtc@68 {
> + compatible = "nxp,pcf8523";
> + reg = <0x68>;
> + };
> +
> + sgtl5000: codec@a {
> + compatible = "fsl,sgtl5000";
> + status = "okay";
> + #sound-dai-cells = <0>;
> + reg = <0x0a>;
> + clocks = <&clk IMX93_CLK_SAI3_GATE>;
> + clock-names = "mclk";
> + assigned-clock-rates = <12000000>, <12000000>;
> + VDDA-supply = <®_3v3_avdd_sgtl>;
> + VDDIO-supply = <®_3v3_sgtl>;
> + VDDD-supply = <®_1v8_sgtl>;
> + };
> +};
> +
> +&lpuart1 { /* console */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + status = "okay";
> +};
> +
> +&lpuart5 { /* RS485 */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart5>;
> + status = "okay";
> +};
> +
> +&lpuart8 { /* RS232 */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart8>;
> + status = "okay";
> +};
> +
> +&micfil {
> + #sound-dai-cells = <0>;
> + pinctrl-names = "default";
> + assigned-clocks = <&clk IMX93_CLK_PDM>;
> + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
> + assigned-clock-rates = <196608000>;
> + status = "okay";
> +};
> +
> +&mu1 {
> + status = "okay";
> +};
> +
> +&mu2 {
> + status = "okay";
> +};
> +
> +&sai1 {
> + #sound-dai-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_sai1>;
> + assigned-clocks = <&clk IMX93_CLK_SAI1>;
> + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
> + assigned-clock-rates = <12288000>;
> + status = "okay";
> +};
> +
> +&sai3 {
> + pinctrl-names = "default";
> + #sound-dai-cells = <0>;
> + pinctrl-0 = <&pinctrl_sai3>;
> + assigned-clocks = <&clk IMX93_CLK_SAI3>;
> + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
> + assigned-clock-rates = <24576000>;
> + fsl,sai-mclk-direction-output;
> + status = "okay";
> +};
> +
> +&usdhc3 { /* WiFi */
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
> + pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
> + pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
> + vmmc-supply = <&wl_reg_on>;
> + bus-width = <4>;
> + no-1-8-v;
> + non-removable;
> + max-frequency = <25000000>;
> + status = "okay";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + brcmf: bcrmf@1 {
> + reg = <1>;
> + compatible = "brcm,bcm4329-fmac";
> + };
> +};
> +
> +&wdog3 {
> + status = "okay";
> +};
> +
> +&iomuxc {
> +
> + pinctrl_flexcan1: flexcan1grp {
> + fsl,pins = <
> + MX93_PAD_PDM_CLK__CAN1_TX 0x139e
> + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
> + >;
> + };
> +
> + pinctrl_flexcan2: flexcan2grp {
> + fsl,pins = <
> + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
> + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
> + >;
> + };
> +
> + pinctrl_laird: lairdgrp {
> + fsl,pins = <
> + MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e // WL_REG_ON
> + MX93_PAD_GPIO_IO19__GPIO2_IO19 0x31e // BT_REG_ON
> + >;
> + };
> +
> + pinctrl_lpi2c1: lpi2c1grp {
> + fsl,pins = <
> + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
> + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
> + >;
> + };
> +
> + pinctrl_sai1: sai1grp {
> + fsl,pins = <
> + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e
> + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e
> + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e
> + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e
> + >;
> + };
> +
> + pinctrl_sai3: sai3grp {
> + fsl,pins = <
> + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e
> + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e
> + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e
> + MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x31e
> + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
> + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
> + >;
> + };
> +
> + pinctrl_uart5: uart5grp {
> + fsl,pins = <
> + MX93_PAD_GPIO_IO01__LPUART5_RX 0x31e
> + MX93_PAD_GPIO_IO00__LPUART5_TX 0x31e
> + MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x31e
> + MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x31e
> + >;
> + };
> +
> + pinctrl_uart8: uart8grp {
> + fsl,pins = <
> + MX93_PAD_GPIO_IO13__LPUART8_RX 0x31e
> + MX93_PAD_GPIO_IO12__LPUART8_TX 0x31e
> + >;
> + };
> +
> + pinctrl_usdhc3: usdhc3grp {
> + fsl,pins = <
> + MX93_PAD_SD3_CLK__USDHC3_CLK 0x17fe
> + MX93_PAD_SD3_CMD__USDHC3_CMD 0x13fe
> + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
> + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
> + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
> + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
> + >;
> + };
> +};
> --
> 2.34.1
>
>
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: imx93: Add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
@ 2024-04-19 7:29 ` Michael Nazzareno Trimarchi
0 siblings, 0 replies; 20+ messages in thread
From: Michael Nazzareno Trimarchi @ 2024-04-19 7:29 UTC (permalink / raw)
To: Fabio Aiuto
Cc: Shawn Guo, Sascha Hauer, Krzysztof Kozlowski, Rob Herring,
Conor Dooley, devicetree, imx, linux-arm-kernel, linux-kernel,
Matteo Lisi, Mirko Ardinghi
Hi Fabio
On Thu, Apr 18, 2024 at 3:43 PM Fabio Aiuto <fabio.aiuto@engicam.com> wrote:
>
> i.Core MX93 is a NXP i.MX93 based SoM by Enigcam which
> needs to be mounted on top of Engicam baseboards.
>
> Add support for EDIMM 2.0 Starter Kit hosting
> i.Core MX93.
>
> Starter Kit main features:
>
> 2x LVDS interfaces
> HDMI output
> Audio out
> Mic in
> Micro SD card slot
> USB 3.0 A port
> 3x USB 2.0 A port
> Gb Ethernet
> 2x CAN bus, 3x UART interfaces
> SIM card slot
> M.2 KEY_B slot
>
> Cc: Matteo Lisi <matteo.lisi@engicam.com>
> Cc: Mirko Ardinghi <mirko.ardinghi@engicam.com>
> Signed-off-by: Fabio Aiuto <fabio.aiuto@engicam.com>
> ---
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> .../dts/freescale/imx93-icore-mx93-edimm2.dts | 354 ++++++++++++++++++
> 2 files changed, 355 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 045250d0a040..d26c0a458a44 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -226,6 +226,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx93-icore-mx93-edimm2.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb
> diff --git a/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts b/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
> new file mode 100644
> index 000000000000..8d57374eebdf
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
> @@ -0,0 +1,354 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2022 NXP
> + * Copyright 2024 Engicam s.r.l.
> + */
> +
> +/dts-v1/;
> +
> +#include "imx93-icore-mx93.dtsi"
> +
> +/ {
> + model = "Engicam i.Core MX93 - EDIMM 2 Starterkit";
> + compatible = "engicam,icore-mx93-edimm2", "engicam,icore-mx93",
> + "fsl,imx93";
> +
> + aliases {
> + rtc1 = &bbnsm_rtc;
> + };
> +
> + bt_reg_on: regulator-btregon {
> + compatible = "regulator-gpio";
> + regulator-name = "BT_REG_ON";
> + pinctrl-names = "default";
> + regulator-min-microvolt = <100000>;
> + regulator-max-microvolt = <3300000>;
> + states = <3300000 0x1>, <100000 0x0>;
> + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> + regulator-always-on;
> + };
> +
Are you sure about regulator always on? I have seen that you broadcom
wifi and bluetooth connected. Same comment for the other
patches where you have almost all the regulator boot on , always on. I
can not be sure that is really true
Please take a look here
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi
Michael
> + chosen {
> + stdout-path = &lpuart1;
> + };
> +
> + reg_1v8_sgtl: regulator-1v8-sgtl {
> + compatible = "regulator-fixed";
> + regulator-name = "1v8_sgtl";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + always-on;
> + };
> +
> + reg_3v3_avdd_sgtl: regulator-3v3-avdd-sgtl {
> + compatible = "regulator-fixed";
> + regulator-name = "3v3_avdd_sgtl";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + always-on;
> + };
> +
> + reg_3v3_sgtl: regulator-3v3-sgtl {
> + compatible = "regulator-fixed";
> + regulator-name = "3v3_sgtl";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + always-on;
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + linux,cma {
> + compatible = "shared-dma-pool";
> + reusable;
> + alloc-ranges = <0 0x80000000 0 0x40000000>;
> + size = <0 0x10000000>;
> + linux,cma-default;
> + };
> +
> + rsc_table: rsc-table@2021f000 {
> + reg = <0 0x2021f000 0 0x1000>;
> + no-map;
> + };
> +
> + vdevbuffer: vdevbuffer@a4020000 {
> + compatible = "shared-dma-pool";
> + reg = <0 0xa4020000 0 0x100000>;
> + no-map;
> + };
> +
> + vdev0vring0: vdev0vring0@a4000000 {
> + reg = <0 0xa4000000 0 0x8000>;
> + no-map;
> + };
> +
> + vdev0vring1: vdev0vring1@a4008000 {
> + reg = <0 0xa4008000 0 0x8000>;
> + no-map;
> + };
> +
> + vdev1vring0: vdev1vring0@a4000000 {
> + reg = <0 0xa4010000 0 0x8000>;
> + no-map;
> + };
> +
> + vdev1vring1: vdev1vring1@a4018000 {
> + reg = <0 0xa4018000 0 0x8000>;
> + no-map;
> + };
> + };
> +
> + sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,name = "imx93-sgtl5000";
> + simple-audio-card,format = "i2s";
> + simple-audio-card,bitclock-master = <&dailink_master>;
> + simple-audio-card,frame-master = <&dailink_master>;
> + /*simple-audio-card,mclk-fs = <1>;*/
> + simple-audio-card,cpu {
> + sound-dai = <&sai3>;
> + };
> +
> + dailink_master: simple-audio-card,codec {
> + sound-dai = <&sgtl5000>;
> + clocks = <&clk IMX93_CLK_SAI3_IPG>;
> + };
> + };
> +
> + usdhc3_pwrseq: usdhc3-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + };
> +
> + wl_reg_on: regulator-wlregon {
> + compatible = "regulator-gpio";
> + pinctrl-names = "default";
> + regulator-name = "WL_REG_ON";
> + regulator-min-microvolt = <100000>;
> + regulator-max-microvolt = <3300000>;
> + states = <3300000 0x1>,
> + <100000 0x0>;
> + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + vin-supply = <&bt_reg_on>;
> + };
> +};
> +
> +&cm33 {
> + mbox-names = "tx", "rx", "rxdb";
> + mboxes = <&mu1 0 1>,
> + <&mu1 1 1>,
> + <&mu1 3 1>;
> + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
> + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
> + status = "okay";
> +};
> +
> +&flexcan1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan1>;
> + fsl,stop-mode = <&aonmix_ns_gpr 0x10 4>;
> + status = "okay";
> +};
> +
> +&flexcan2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan2>;
> + fsl,stop-mode = <&aonmix_ns_gpr 0x10 4>;
> + status = "okay";
> +};
> +
> +&lpi2c1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-frequency = <400000>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&pinctrl_lpi2c1>;
> + pinctrl-1 = <&pinctrl_lpi2c1>;
> + status = "okay";
> +
> + pcf8523: rtc@68 {
> + compatible = "nxp,pcf8523";
> + reg = <0x68>;
> + };
> +
> + sgtl5000: codec@a {
> + compatible = "fsl,sgtl5000";
> + status = "okay";
> + #sound-dai-cells = <0>;
> + reg = <0x0a>;
> + clocks = <&clk IMX93_CLK_SAI3_GATE>;
> + clock-names = "mclk";
> + assigned-clock-rates = <12000000>, <12000000>;
> + VDDA-supply = <®_3v3_avdd_sgtl>;
> + VDDIO-supply = <®_3v3_sgtl>;
> + VDDD-supply = <®_1v8_sgtl>;
> + };
> +};
> +
> +&lpuart1 { /* console */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + status = "okay";
> +};
> +
> +&lpuart5 { /* RS485 */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart5>;
> + status = "okay";
> +};
> +
> +&lpuart8 { /* RS232 */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart8>;
> + status = "okay";
> +};
> +
> +&micfil {
> + #sound-dai-cells = <0>;
> + pinctrl-names = "default";
> + assigned-clocks = <&clk IMX93_CLK_PDM>;
> + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
> + assigned-clock-rates = <196608000>;
> + status = "okay";
> +};
> +
> +&mu1 {
> + status = "okay";
> +};
> +
> +&mu2 {
> + status = "okay";
> +};
> +
> +&sai1 {
> + #sound-dai-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_sai1>;
> + assigned-clocks = <&clk IMX93_CLK_SAI1>;
> + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
> + assigned-clock-rates = <12288000>;
> + status = "okay";
> +};
> +
> +&sai3 {
> + pinctrl-names = "default";
> + #sound-dai-cells = <0>;
> + pinctrl-0 = <&pinctrl_sai3>;
> + assigned-clocks = <&clk IMX93_CLK_SAI3>;
> + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
> + assigned-clock-rates = <24576000>;
> + fsl,sai-mclk-direction-output;
> + status = "okay";
> +};
> +
> +&usdhc3 { /* WiFi */
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
> + pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
> + pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
> + vmmc-supply = <&wl_reg_on>;
> + bus-width = <4>;
> + no-1-8-v;
> + non-removable;
> + max-frequency = <25000000>;
> + status = "okay";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + brcmf: bcrmf@1 {
> + reg = <1>;
> + compatible = "brcm,bcm4329-fmac";
> + };
> +};
> +
> +&wdog3 {
> + status = "okay";
> +};
> +
> +&iomuxc {
> +
> + pinctrl_flexcan1: flexcan1grp {
> + fsl,pins = <
> + MX93_PAD_PDM_CLK__CAN1_TX 0x139e
> + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
> + >;
> + };
> +
> + pinctrl_flexcan2: flexcan2grp {
> + fsl,pins = <
> + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
> + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
> + >;
> + };
> +
> + pinctrl_laird: lairdgrp {
> + fsl,pins = <
> + MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e // WL_REG_ON
> + MX93_PAD_GPIO_IO19__GPIO2_IO19 0x31e // BT_REG_ON
> + >;
> + };
> +
> + pinctrl_lpi2c1: lpi2c1grp {
> + fsl,pins = <
> + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
> + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
> + >;
> + };
> +
> + pinctrl_sai1: sai1grp {
> + fsl,pins = <
> + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e
> + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e
> + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e
> + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e
> + >;
> + };
> +
> + pinctrl_sai3: sai3grp {
> + fsl,pins = <
> + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e
> + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e
> + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e
> + MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x31e
> + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
> + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
> + >;
> + };
> +
> + pinctrl_uart5: uart5grp {
> + fsl,pins = <
> + MX93_PAD_GPIO_IO01__LPUART5_RX 0x31e
> + MX93_PAD_GPIO_IO00__LPUART5_TX 0x31e
> + MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x31e
> + MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x31e
> + >;
> + };
> +
> + pinctrl_uart8: uart8grp {
> + fsl,pins = <
> + MX93_PAD_GPIO_IO13__LPUART8_RX 0x31e
> + MX93_PAD_GPIO_IO12__LPUART8_TX 0x31e
> + >;
> + };
> +
> + pinctrl_usdhc3: usdhc3grp {
> + fsl,pins = <
> + MX93_PAD_SD3_CLK__USDHC3_CLK 0x17fe
> + MX93_PAD_SD3_CMD__USDHC3_CMD 0x13fe
> + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
> + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
> + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
> + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
> + >;
> + };
> +};
> --
> 2.34.1
>
>
--
Michael Nazzareno Trimarchi
Co-Founder & Chief Executive Officer
M. +39 347 913 2170
michael@amarulasolutions.com
__________________________________
Amarula Solutions BV
Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
T. +31 (0)85 111 9172
info@amarulasolutions.com
www.amarulasolutions.com
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: imx93: Add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
2024-04-19 7:29 ` Michael Nazzareno Trimarchi
@ 2024-04-19 11:01 ` Fabio Aiuto
-1 siblings, 0 replies; 20+ messages in thread
From: Fabio Aiuto @ 2024-04-19 11:01 UTC (permalink / raw)
To: Michael Nazzareno Trimarchi
Cc: Shawn Guo, Sascha Hauer, Krzysztof Kozlowski, Rob Herring,
Conor Dooley, devicetree, imx, linux-arm-kernel, linux-kernel,
Matteo Lisi, Mirko Ardinghi
Hello Michael,
Il Fri, Apr 19, 2024 at 09:29:12AM +0200, Michael Nazzareno Trimarchi ha scritto:
> Hi Fabio
>
> On Thu, Apr 18, 2024 at 3:43 PM Fabio Aiuto <fabio.aiuto@engicam.com> wrote:
> >
> > i.Core MX93 is a NXP i.MX93 based SoM by Enigcam which
> > needs to be mounted on top of Engicam baseboards.
> >
> > Add support for EDIMM 2.0 Starter Kit hosting
> > i.Core MX93.
> >
> > Starter Kit main features:
> >
> > 2x LVDS interfaces
> > HDMI output
> > Audio out
> > Mic in
> > Micro SD card slot
> > USB 3.0 A port
> > 3x USB 2.0 A port
> > Gb Ethernet
> > 2x CAN bus, 3x UART interfaces
> > SIM card slot
> > M.2 KEY_B slot
> >
> > Cc: Matteo Lisi <matteo.lisi@engicam.com>
> > Cc: Mirko Ardinghi <mirko.ardinghi@engicam.com>
> > Signed-off-by: Fabio Aiuto <fabio.aiuto@engicam.com>
> > ---
> > arch/arm64/boot/dts/freescale/Makefile | 1 +
> > .../dts/freescale/imx93-icore-mx93-edimm2.dts | 354 ++++++++++++++++++
> > 2 files changed, 355 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
> >
> > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> > index 045250d0a040..d26c0a458a44 100644
> > --- a/arch/arm64/boot/dts/freescale/Makefile
> > +++ b/arch/arm64/boot/dts/freescale/Makefile
> > @@ -226,6 +226,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb
> > +dtb-$(CONFIG_ARCH_MXC) += imx93-icore-mx93-edimm2.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb
> > diff --git a/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts b/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
> > new file mode 100644
> > index 000000000000..8d57374eebdf
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
> > @@ -0,0 +1,354 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Copyright 2022 NXP
> > + * Copyright 2024 Engicam s.r.l.
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "imx93-icore-mx93.dtsi"
> > +
> > +/ {
> > + model = "Engicam i.Core MX93 - EDIMM 2 Starterkit";
> > + compatible = "engicam,icore-mx93-edimm2", "engicam,icore-mx93",
> > + "fsl,imx93";
> > +
> > + aliases {
> > + rtc1 = &bbnsm_rtc;
> > + };
> > +
> > + bt_reg_on: regulator-btregon {
> > + compatible = "regulator-gpio";
> > + regulator-name = "BT_REG_ON";
> > + pinctrl-names = "default";
> > + regulator-min-microvolt = <100000>;
> > + regulator-max-microvolt = <3300000>;
> > + states = <3300000 0x1>, <100000 0x0>;
> > + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> > + regulator-always-on;
> > + };
> > +
>
> Are you sure about regulator always on? I have seen that you broadcom
> wifi and bluetooth connected. Same comment for the other
> patches where you have almost all the regulator boot on , always on. I
> can not be sure that is really true
>
> Please take a look here
> arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi
thank you for your comment, for wifi/bt module is better to
remove regulator-always-on.
For other regulators (e.g. sgtl5000) they are fixed and always on
from an hardware design point of view.
Will remove regulator-always-on for bt_reg_on in the v3 patchset.
kr,
fabio
>
> Michael
>
> > + chosen {
> > + stdout-path = &lpuart1;
> > + };
> > +
> > + reg_1v8_sgtl: regulator-1v8-sgtl {
> > + compatible = "regulator-fixed";
> > + regulator-name = "1v8_sgtl";
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + always-on;
> > + };
> > +
> > + reg_3v3_avdd_sgtl: regulator-3v3-avdd-sgtl {
> > + compatible = "regulator-fixed";
> > + regulator-name = "3v3_avdd_sgtl";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + always-on;
> > + };
> > +
> > + reg_3v3_sgtl: regulator-3v3-sgtl {
> > + compatible = "regulator-fixed";
> > + regulator-name = "3v3_sgtl";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + always-on;
> > + };
> > +
> > + reserved-memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + linux,cma {
> > + compatible = "shared-dma-pool";
> > + reusable;
> > + alloc-ranges = <0 0x80000000 0 0x40000000>;
> > + size = <0 0x10000000>;
> > + linux,cma-default;
> > + };
> > +
> > + rsc_table: rsc-table@2021f000 {
> > + reg = <0 0x2021f000 0 0x1000>;
> > + no-map;
> > + };
> > +
> > + vdevbuffer: vdevbuffer@a4020000 {
> > + compatible = "shared-dma-pool";
> > + reg = <0 0xa4020000 0 0x100000>;
> > + no-map;
> > + };
> > +
> > + vdev0vring0: vdev0vring0@a4000000 {
> > + reg = <0 0xa4000000 0 0x8000>;
> > + no-map;
> > + };
> > +
> > + vdev0vring1: vdev0vring1@a4008000 {
> > + reg = <0 0xa4008000 0 0x8000>;
> > + no-map;
> > + };
> > +
> > + vdev1vring0: vdev1vring0@a4000000 {
> > + reg = <0 0xa4010000 0 0x8000>;
> > + no-map;
> > + };
> > +
> > + vdev1vring1: vdev1vring1@a4018000 {
> > + reg = <0 0xa4018000 0 0x8000>;
> > + no-map;
> > + };
> > + };
> > +
> > + sound {
> > + compatible = "simple-audio-card";
> > + simple-audio-card,name = "imx93-sgtl5000";
> > + simple-audio-card,format = "i2s";
> > + simple-audio-card,bitclock-master = <&dailink_master>;
> > + simple-audio-card,frame-master = <&dailink_master>;
> > + /*simple-audio-card,mclk-fs = <1>;*/
> > + simple-audio-card,cpu {
> > + sound-dai = <&sai3>;
> > + };
> > +
> > + dailink_master: simple-audio-card,codec {
> > + sound-dai = <&sgtl5000>;
> > + clocks = <&clk IMX93_CLK_SAI3_IPG>;
> > + };
> > + };
> > +
> > + usdhc3_pwrseq: usdhc3-pwrseq {
> > + compatible = "mmc-pwrseq-simple";
> > + };
> > +
> > + wl_reg_on: regulator-wlregon {
> > + compatible = "regulator-gpio";
> > + pinctrl-names = "default";
> > + regulator-name = "WL_REG_ON";
> > + regulator-min-microvolt = <100000>;
> > + regulator-max-microvolt = <3300000>;
> > + states = <3300000 0x1>,
> > + <100000 0x0>;
> > + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
> > + enable-active-high;
> > + vin-supply = <&bt_reg_on>;
> > + };
> > +};
> > +
> > +&cm33 {
> > + mbox-names = "tx", "rx", "rxdb";
> > + mboxes = <&mu1 0 1>,
> > + <&mu1 1 1>,
> > + <&mu1 3 1>;
> > + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
> > + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
> > + status = "okay";
> > +};
> > +
> > +&flexcan1 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_flexcan1>;
> > + fsl,stop-mode = <&aonmix_ns_gpr 0x10 4>;
> > + status = "okay";
> > +};
> > +
> > +&flexcan2 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_flexcan2>;
> > + fsl,stop-mode = <&aonmix_ns_gpr 0x10 4>;
> > + status = "okay";
> > +};
> > +
> > +&lpi2c1 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + clock-frequency = <400000>;
> > + pinctrl-names = "default", "sleep";
> > + pinctrl-0 = <&pinctrl_lpi2c1>;
> > + pinctrl-1 = <&pinctrl_lpi2c1>;
> > + status = "okay";
> > +
> > + pcf8523: rtc@68 {
> > + compatible = "nxp,pcf8523";
> > + reg = <0x68>;
> > + };
> > +
> > + sgtl5000: codec@a {
> > + compatible = "fsl,sgtl5000";
> > + status = "okay";
> > + #sound-dai-cells = <0>;
> > + reg = <0x0a>;
> > + clocks = <&clk IMX93_CLK_SAI3_GATE>;
> > + clock-names = "mclk";
> > + assigned-clock-rates = <12000000>, <12000000>;
> > + VDDA-supply = <®_3v3_avdd_sgtl>;
> > + VDDIO-supply = <®_3v3_sgtl>;
> > + VDDD-supply = <®_1v8_sgtl>;
> > + };
> > +};
> > +
> > +&lpuart1 { /* console */
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_uart1>;
> > + status = "okay";
> > +};
> > +
> > +&lpuart5 { /* RS485 */
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_uart5>;
> > + status = "okay";
> > +};
> > +
> > +&lpuart8 { /* RS232 */
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_uart8>;
> > + status = "okay";
> > +};
> > +
> > +&micfil {
> > + #sound-dai-cells = <0>;
> > + pinctrl-names = "default";
> > + assigned-clocks = <&clk IMX93_CLK_PDM>;
> > + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
> > + assigned-clock-rates = <196608000>;
> > + status = "okay";
> > +};
> > +
> > +&mu1 {
> > + status = "okay";
> > +};
> > +
> > +&mu2 {
> > + status = "okay";
> > +};
> > +
> > +&sai1 {
> > + #sound-dai-cells = <0>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_sai1>;
> > + assigned-clocks = <&clk IMX93_CLK_SAI1>;
> > + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
> > + assigned-clock-rates = <12288000>;
> > + status = "okay";
> > +};
> > +
> > +&sai3 {
> > + pinctrl-names = "default";
> > + #sound-dai-cells = <0>;
> > + pinctrl-0 = <&pinctrl_sai3>;
> > + assigned-clocks = <&clk IMX93_CLK_SAI3>;
> > + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
> > + assigned-clock-rates = <24576000>;
> > + fsl,sai-mclk-direction-output;
> > + status = "okay";
> > +};
> > +
> > +&usdhc3 { /* WiFi */
> > + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
> > + pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
> > + pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
> > + vmmc-supply = <&wl_reg_on>;
> > + bus-width = <4>;
> > + no-1-8-v;
> > + non-removable;
> > + max-frequency = <25000000>;
> > + status = "okay";
> > +
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + brcmf: bcrmf@1 {
> > + reg = <1>;
> > + compatible = "brcm,bcm4329-fmac";
> > + };
> > +};
> > +
> > +&wdog3 {
> > + status = "okay";
> > +};
> > +
> > +&iomuxc {
> > +
> > + pinctrl_flexcan1: flexcan1grp {
> > + fsl,pins = <
> > + MX93_PAD_PDM_CLK__CAN1_TX 0x139e
> > + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
> > + >;
> > + };
> > +
> > + pinctrl_flexcan2: flexcan2grp {
> > + fsl,pins = <
> > + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
> > + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
> > + >;
> > + };
> > +
> > + pinctrl_laird: lairdgrp {
> > + fsl,pins = <
> > + MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e // WL_REG_ON
> > + MX93_PAD_GPIO_IO19__GPIO2_IO19 0x31e // BT_REG_ON
> > + >;
> > + };
> > +
> > + pinctrl_lpi2c1: lpi2c1grp {
> > + fsl,pins = <
> > + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
> > + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
> > + >;
> > + };
> > +
> > + pinctrl_sai1: sai1grp {
> > + fsl,pins = <
> > + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e
> > + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e
> > + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e
> > + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e
> > + >;
> > + };
> > +
> > + pinctrl_sai3: sai3grp {
> > + fsl,pins = <
> > + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e
> > + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e
> > + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e
> > + MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x31e
> > + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e
> > + >;
> > + };
> > +
> > + pinctrl_uart1: uart1grp {
> > + fsl,pins = <
> > + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
> > + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
> > + >;
> > + };
> > +
> > + pinctrl_uart5: uart5grp {
> > + fsl,pins = <
> > + MX93_PAD_GPIO_IO01__LPUART5_RX 0x31e
> > + MX93_PAD_GPIO_IO00__LPUART5_TX 0x31e
> > + MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x31e
> > + MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x31e
> > + >;
> > + };
> > +
> > + pinctrl_uart8: uart8grp {
> > + fsl,pins = <
> > + MX93_PAD_GPIO_IO13__LPUART8_RX 0x31e
> > + MX93_PAD_GPIO_IO12__LPUART8_TX 0x31e
> > + >;
> > + };
> > +
> > + pinctrl_usdhc3: usdhc3grp {
> > + fsl,pins = <
> > + MX93_PAD_SD3_CLK__USDHC3_CLK 0x17fe
> > + MX93_PAD_SD3_CMD__USDHC3_CMD 0x13fe
> > + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
> > + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
> > + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
> > + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
> > + >;
> > + };
> > +};
> > --
> > 2.34.1
> >
> >
>
>
> --
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> michael@amarulasolutions.com
> __________________________________
>
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> T. +31 (0)85 111 9172
> info@amarulasolutions.com
> www.amarulasolutions.com
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: imx93: Add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
@ 2024-04-19 11:01 ` Fabio Aiuto
0 siblings, 0 replies; 20+ messages in thread
From: Fabio Aiuto @ 2024-04-19 11:01 UTC (permalink / raw)
To: Michael Nazzareno Trimarchi
Cc: Shawn Guo, Sascha Hauer, Krzysztof Kozlowski, Rob Herring,
Conor Dooley, devicetree, imx, linux-arm-kernel, linux-kernel,
Matteo Lisi, Mirko Ardinghi
Hello Michael,
Il Fri, Apr 19, 2024 at 09:29:12AM +0200, Michael Nazzareno Trimarchi ha scritto:
> Hi Fabio
>
> On Thu, Apr 18, 2024 at 3:43 PM Fabio Aiuto <fabio.aiuto@engicam.com> wrote:
> >
> > i.Core MX93 is a NXP i.MX93 based SoM by Enigcam which
> > needs to be mounted on top of Engicam baseboards.
> >
> > Add support for EDIMM 2.0 Starter Kit hosting
> > i.Core MX93.
> >
> > Starter Kit main features:
> >
> > 2x LVDS interfaces
> > HDMI output
> > Audio out
> > Mic in
> > Micro SD card slot
> > USB 3.0 A port
> > 3x USB 2.0 A port
> > Gb Ethernet
> > 2x CAN bus, 3x UART interfaces
> > SIM card slot
> > M.2 KEY_B slot
> >
> > Cc: Matteo Lisi <matteo.lisi@engicam.com>
> > Cc: Mirko Ardinghi <mirko.ardinghi@engicam.com>
> > Signed-off-by: Fabio Aiuto <fabio.aiuto@engicam.com>
> > ---
> > arch/arm64/boot/dts/freescale/Makefile | 1 +
> > .../dts/freescale/imx93-icore-mx93-edimm2.dts | 354 ++++++++++++++++++
> > 2 files changed, 355 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
> >
> > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> > index 045250d0a040..d26c0a458a44 100644
> > --- a/arch/arm64/boot/dts/freescale/Makefile
> > +++ b/arch/arm64/boot/dts/freescale/Makefile
> > @@ -226,6 +226,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb
> > +dtb-$(CONFIG_ARCH_MXC) += imx93-icore-mx93-edimm2.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb
> > diff --git a/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts b/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
> > new file mode 100644
> > index 000000000000..8d57374eebdf
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
> > @@ -0,0 +1,354 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Copyright 2022 NXP
> > + * Copyright 2024 Engicam s.r.l.
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "imx93-icore-mx93.dtsi"
> > +
> > +/ {
> > + model = "Engicam i.Core MX93 - EDIMM 2 Starterkit";
> > + compatible = "engicam,icore-mx93-edimm2", "engicam,icore-mx93",
> > + "fsl,imx93";
> > +
> > + aliases {
> > + rtc1 = &bbnsm_rtc;
> > + };
> > +
> > + bt_reg_on: regulator-btregon {
> > + compatible = "regulator-gpio";
> > + regulator-name = "BT_REG_ON";
> > + pinctrl-names = "default";
> > + regulator-min-microvolt = <100000>;
> > + regulator-max-microvolt = <3300000>;
> > + states = <3300000 0x1>, <100000 0x0>;
> > + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> > + regulator-always-on;
> > + };
> > +
>
> Are you sure about regulator always on? I have seen that you broadcom
> wifi and bluetooth connected. Same comment for the other
> patches where you have almost all the regulator boot on , always on. I
> can not be sure that is really true
>
> Please take a look here
> arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi
thank you for your comment, for wifi/bt module is better to
remove regulator-always-on.
For other regulators (e.g. sgtl5000) they are fixed and always on
from an hardware design point of view.
Will remove regulator-always-on for bt_reg_on in the v3 patchset.
kr,
fabio
>
> Michael
>
> > + chosen {
> > + stdout-path = &lpuart1;
> > + };
> > +
> > + reg_1v8_sgtl: regulator-1v8-sgtl {
> > + compatible = "regulator-fixed";
> > + regulator-name = "1v8_sgtl";
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + always-on;
> > + };
> > +
> > + reg_3v3_avdd_sgtl: regulator-3v3-avdd-sgtl {
> > + compatible = "regulator-fixed";
> > + regulator-name = "3v3_avdd_sgtl";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + always-on;
> > + };
> > +
> > + reg_3v3_sgtl: regulator-3v3-sgtl {
> > + compatible = "regulator-fixed";
> > + regulator-name = "3v3_sgtl";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + always-on;
> > + };
> > +
> > + reserved-memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + linux,cma {
> > + compatible = "shared-dma-pool";
> > + reusable;
> > + alloc-ranges = <0 0x80000000 0 0x40000000>;
> > + size = <0 0x10000000>;
> > + linux,cma-default;
> > + };
> > +
> > + rsc_table: rsc-table@2021f000 {
> > + reg = <0 0x2021f000 0 0x1000>;
> > + no-map;
> > + };
> > +
> > + vdevbuffer: vdevbuffer@a4020000 {
> > + compatible = "shared-dma-pool";
> > + reg = <0 0xa4020000 0 0x100000>;
> > + no-map;
> > + };
> > +
> > + vdev0vring0: vdev0vring0@a4000000 {
> > + reg = <0 0xa4000000 0 0x8000>;
> > + no-map;
> > + };
> > +
> > + vdev0vring1: vdev0vring1@a4008000 {
> > + reg = <0 0xa4008000 0 0x8000>;
> > + no-map;
> > + };
> > +
> > + vdev1vring0: vdev1vring0@a4000000 {
> > + reg = <0 0xa4010000 0 0x8000>;
> > + no-map;
> > + };
> > +
> > + vdev1vring1: vdev1vring1@a4018000 {
> > + reg = <0 0xa4018000 0 0x8000>;
> > + no-map;
> > + };
> > + };
> > +
> > + sound {
> > + compatible = "simple-audio-card";
> > + simple-audio-card,name = "imx93-sgtl5000";
> > + simple-audio-card,format = "i2s";
> > + simple-audio-card,bitclock-master = <&dailink_master>;
> > + simple-audio-card,frame-master = <&dailink_master>;
> > + /*simple-audio-card,mclk-fs = <1>;*/
> > + simple-audio-card,cpu {
> > + sound-dai = <&sai3>;
> > + };
> > +
> > + dailink_master: simple-audio-card,codec {
> > + sound-dai = <&sgtl5000>;
> > + clocks = <&clk IMX93_CLK_SAI3_IPG>;
> > + };
> > + };
> > +
> > + usdhc3_pwrseq: usdhc3-pwrseq {
> > + compatible = "mmc-pwrseq-simple";
> > + };
> > +
> > + wl_reg_on: regulator-wlregon {
> > + compatible = "regulator-gpio";
> > + pinctrl-names = "default";
> > + regulator-name = "WL_REG_ON";
> > + regulator-min-microvolt = <100000>;
> > + regulator-max-microvolt = <3300000>;
> > + states = <3300000 0x1>,
> > + <100000 0x0>;
> > + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
> > + enable-active-high;
> > + vin-supply = <&bt_reg_on>;
> > + };
> > +};
> > +
> > +&cm33 {
> > + mbox-names = "tx", "rx", "rxdb";
> > + mboxes = <&mu1 0 1>,
> > + <&mu1 1 1>,
> > + <&mu1 3 1>;
> > + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
> > + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
> > + status = "okay";
> > +};
> > +
> > +&flexcan1 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_flexcan1>;
> > + fsl,stop-mode = <&aonmix_ns_gpr 0x10 4>;
> > + status = "okay";
> > +};
> > +
> > +&flexcan2 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_flexcan2>;
> > + fsl,stop-mode = <&aonmix_ns_gpr 0x10 4>;
> > + status = "okay";
> > +};
> > +
> > +&lpi2c1 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + clock-frequency = <400000>;
> > + pinctrl-names = "default", "sleep";
> > + pinctrl-0 = <&pinctrl_lpi2c1>;
> > + pinctrl-1 = <&pinctrl_lpi2c1>;
> > + status = "okay";
> > +
> > + pcf8523: rtc@68 {
> > + compatible = "nxp,pcf8523";
> > + reg = <0x68>;
> > + };
> > +
> > + sgtl5000: codec@a {
> > + compatible = "fsl,sgtl5000";
> > + status = "okay";
> > + #sound-dai-cells = <0>;
> > + reg = <0x0a>;
> > + clocks = <&clk IMX93_CLK_SAI3_GATE>;
> > + clock-names = "mclk";
> > + assigned-clock-rates = <12000000>, <12000000>;
> > + VDDA-supply = <®_3v3_avdd_sgtl>;
> > + VDDIO-supply = <®_3v3_sgtl>;
> > + VDDD-supply = <®_1v8_sgtl>;
> > + };
> > +};
> > +
> > +&lpuart1 { /* console */
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_uart1>;
> > + status = "okay";
> > +};
> > +
> > +&lpuart5 { /* RS485 */
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_uart5>;
> > + status = "okay";
> > +};
> > +
> > +&lpuart8 { /* RS232 */
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_uart8>;
> > + status = "okay";
> > +};
> > +
> > +&micfil {
> > + #sound-dai-cells = <0>;
> > + pinctrl-names = "default";
> > + assigned-clocks = <&clk IMX93_CLK_PDM>;
> > + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
> > + assigned-clock-rates = <196608000>;
> > + status = "okay";
> > +};
> > +
> > +&mu1 {
> > + status = "okay";
> > +};
> > +
> > +&mu2 {
> > + status = "okay";
> > +};
> > +
> > +&sai1 {
> > + #sound-dai-cells = <0>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_sai1>;
> > + assigned-clocks = <&clk IMX93_CLK_SAI1>;
> > + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
> > + assigned-clock-rates = <12288000>;
> > + status = "okay";
> > +};
> > +
> > +&sai3 {
> > + pinctrl-names = "default";
> > + #sound-dai-cells = <0>;
> > + pinctrl-0 = <&pinctrl_sai3>;
> > + assigned-clocks = <&clk IMX93_CLK_SAI3>;
> > + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
> > + assigned-clock-rates = <24576000>;
> > + fsl,sai-mclk-direction-output;
> > + status = "okay";
> > +};
> > +
> > +&usdhc3 { /* WiFi */
> > + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
> > + pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
> > + pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
> > + vmmc-supply = <&wl_reg_on>;
> > + bus-width = <4>;
> > + no-1-8-v;
> > + non-removable;
> > + max-frequency = <25000000>;
> > + status = "okay";
> > +
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + brcmf: bcrmf@1 {
> > + reg = <1>;
> > + compatible = "brcm,bcm4329-fmac";
> > + };
> > +};
> > +
> > +&wdog3 {
> > + status = "okay";
> > +};
> > +
> > +&iomuxc {
> > +
> > + pinctrl_flexcan1: flexcan1grp {
> > + fsl,pins = <
> > + MX93_PAD_PDM_CLK__CAN1_TX 0x139e
> > + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
> > + >;
> > + };
> > +
> > + pinctrl_flexcan2: flexcan2grp {
> > + fsl,pins = <
> > + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
> > + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
> > + >;
> > + };
> > +
> > + pinctrl_laird: lairdgrp {
> > + fsl,pins = <
> > + MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e // WL_REG_ON
> > + MX93_PAD_GPIO_IO19__GPIO2_IO19 0x31e // BT_REG_ON
> > + >;
> > + };
> > +
> > + pinctrl_lpi2c1: lpi2c1grp {
> > + fsl,pins = <
> > + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
> > + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
> > + >;
> > + };
> > +
> > + pinctrl_sai1: sai1grp {
> > + fsl,pins = <
> > + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e
> > + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e
> > + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e
> > + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e
> > + >;
> > + };
> > +
> > + pinctrl_sai3: sai3grp {
> > + fsl,pins = <
> > + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e
> > + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e
> > + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e
> > + MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x31e
> > + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e
> > + >;
> > + };
> > +
> > + pinctrl_uart1: uart1grp {
> > + fsl,pins = <
> > + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
> > + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
> > + >;
> > + };
> > +
> > + pinctrl_uart5: uart5grp {
> > + fsl,pins = <
> > + MX93_PAD_GPIO_IO01__LPUART5_RX 0x31e
> > + MX93_PAD_GPIO_IO00__LPUART5_TX 0x31e
> > + MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x31e
> > + MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x31e
> > + >;
> > + };
> > +
> > + pinctrl_uart8: uart8grp {
> > + fsl,pins = <
> > + MX93_PAD_GPIO_IO13__LPUART8_RX 0x31e
> > + MX93_PAD_GPIO_IO12__LPUART8_TX 0x31e
> > + >;
> > + };
> > +
> > + pinctrl_usdhc3: usdhc3grp {
> > + fsl,pins = <
> > + MX93_PAD_SD3_CLK__USDHC3_CLK 0x17fe
> > + MX93_PAD_SD3_CMD__USDHC3_CMD 0x13fe
> > + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
> > + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
> > + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
> > + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
> > + >;
> > + };
> > +};
> > --
> > 2.34.1
> >
> >
>
>
> --
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> michael@amarulasolutions.com
> __________________________________
>
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> T. +31 (0)85 111 9172
> info@amarulasolutions.com
> www.amarulasolutions.com
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2024-04-19 11:04 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-04-18 13:39 [PATCH v2 0/3] arm64: dts: imx93: add i.Core MX93 EDIMM 2.0 board Fabio Aiuto
2024-04-18 13:39 ` Fabio Aiuto
2024-04-18 13:39 ` [PATCH v2 1/3] dt-bindings: arm: fsl: add Engicam i.Core MX93 EDIMM 2.0 Starter Kit Fabio Aiuto
2024-04-18 13:39 ` Fabio Aiuto
2024-04-18 15:33 ` Conor Dooley
2024-04-18 15:33 ` Conor Dooley
2024-04-18 16:34 ` Conor Dooley
2024-04-18 16:34 ` Conor Dooley
2024-04-19 7:20 ` Fabio Aiuto
2024-04-19 7:20 ` Fabio Aiuto
2024-04-18 13:39 ` [PATCH v2 2/3] arm64: dts: imx93: add Engicam i.Core MX93 SoM Fabio Aiuto
2024-04-18 13:39 ` Fabio Aiuto
2024-04-18 13:39 ` [PATCH v2 3/3] arm64: dts: imx93: Add Engicam i.Core MX93 EDIMM 2.0 Starter Kit Fabio Aiuto
2024-04-18 13:39 ` Fabio Aiuto
2024-04-19 7:29 ` Michael Nazzareno Trimarchi
2024-04-19 7:29 ` Michael Nazzareno Trimarchi
2024-04-19 11:01 ` Fabio Aiuto
2024-04-19 11:01 ` Fabio Aiuto
2024-04-18 18:29 ` [PATCH v2 0/3] arm64: dts: imx93: add i.Core MX93 EDIMM 2.0 board Rob Herring
2024-04-18 18:29 ` Rob Herring
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