[PATCH 00/15] Ambarella S6LM SoC bring-up

[PATCH 00/15] Ambarella S6LM SoC bring-up

[Li Chen]

This series brings up initial support for the Ambarella S6LM
SoC.

The following features are supported in this initial port:

- UART with console support
- Pinctrl with GPIO controller
- Nand flash controller
- Devicetree

Li Chen (15):
  debugfs: allow to use regmap for print regs
  dt-bindings: vendor-prefixes: add Ambarella prefix
  dt-bindings: arm: ambarella: Add binding for Ambarella ARM platforms
  dt-bindings: arm: add support for Ambarella SoC
  arm64: Kconfig: Introduce CONFIG_ARCH_AMBARELLA
  soc: add Ambarella driver
  dt-bindings: clock: Add Ambarella clock bindings
  clk: add support for Ambarella clocks
  dt-bindings: serial: add support for Ambarella
  serial: ambarella: add support for Ambarella uart_port
  dt-bindings: mtd: Add binding for Ambarella
  mtd: nand: add Ambarella nand support
  dt-bindings: pinctrl: add support for Ambarella
  pinctrl: Add pinctrl/GPIO for Ambarella SoCs
  arm64: dts: ambarella: introduce Ambarella s6lm SoC

 .../devicetree/bindings/arm/ambarella.yaml    |   22 +
 .../arm/ambarella/ambarella,cpuid.yaml        |   24 +
 .../bindings/arm/ambarella/ambarella,rct.yaml |   24 +
 .../arm/ambarella/ambarella,scratchpad.yaml   |   24 +
 .../bindings/arm/ambarella/ambarella.yaml     |   22 +
 .../clock/ambarella,composite-clock.yaml      |   52 +
 .../bindings/clock/ambarella,pll-clock.yaml   |   59 +
 .../bindings/mtd/ambarella,nand.yaml          |   77 +
 .../bindings/pinctrl/ambarella,pinctrl.yaml   |  160 ++
 .../bindings/serial/ambarella_uart.yaml       |   57 +
 .../devicetree/bindings/vendor-prefixes.yaml  |    2 +
 Documentation/filesystems/debugfs.rst         |    2 +
 MAINTAINERS                                   |   29 +
 arch/arm64/Kconfig.platforms                  |    9 +
 .../boot/dts/ambarella/ambarella-s6lm.dtsi    |  332 ++++
 .../boot/dts/ambarella/s6lm_pineapple.dts     |   29 +
 drivers/clk/Makefile                          |    1 +
 drivers/clk/ambarella/Makefile                |    5 +
 drivers/clk/ambarella/clk-composite.c         |  293 +++
 drivers/clk/ambarella/clk-pll-common.c        |  308 ++++
 drivers/clk/ambarella/clk-pll-common.h        |   96 +
 drivers/clk/ambarella/clk-pll-normal.c        |  328 ++++
 drivers/mtd/nand/raw/Kconfig                  |    8 +
 drivers/mtd/nand/raw/Makefile                 |    1 +
 drivers/mtd/nand/raw/ambarella_combo_nand.c   | 1519 ++++++++++++++++
 drivers/mtd/nand/raw/ambarella_combo_nand.h   |  370 ++++
 drivers/mtd/nand/raw/nand_ids.c               |    4 +
 drivers/pinctrl/Kconfig                       |    6 +
 drivers/pinctrl/Makefile                      |    1 +
 drivers/pinctrl/pinctrl-ambarella.c           | 1357 ++++++++++++++
 drivers/soc/Makefile                          |    1 +
 drivers/soc/ambarella/Makefile                |    3 +
 drivers/soc/ambarella/soc.c                   |  136 ++
 drivers/tty/serial/Kconfig                    |   16 +
 drivers/tty/serial/Makefile                   |    1 +
 drivers/tty/serial/ambarella_uart.c           | 1581 +++++++++++++++++
 drivers/tty/serial/ambarella_uart.h           |  120 ++
 fs/debugfs/file.c                             |   43 +-
 include/linux/debugfs.h                       |   11 +
 include/soc/ambarella/misc.h                  |   17 +
 40 files changed, 7149 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/arm/ambarella.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,scratchpad.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
 create mode 100644 Documentation/devicetree/bindings/mtd/ambarella,nand.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/ambarella,pinctrl.yaml
 create mode 100644 Documentation/devicetree/bindings/serial/ambarella_uart.yaml
 create mode 100644 arch/arm64/boot/dts/ambarella/ambarella-s6lm.dtsi
 create mode 100644 arch/arm64/boot/dts/ambarella/s6lm_pineapple.dts
 create mode 100644 drivers/clk/ambarella/Makefile
 create mode 100644 drivers/clk/ambarella/clk-composite.c
 create mode 100644 drivers/clk/ambarella/clk-pll-common.c
 create mode 100644 drivers/clk/ambarella/clk-pll-common.h
 create mode 100644 drivers/clk/ambarella/clk-pll-normal.c
 create mode 100644 drivers/mtd/nand/raw/ambarella_combo_nand.c
 create mode 100644 drivers/mtd/nand/raw/ambarella_combo_nand.h
 create mode 100644 drivers/pinctrl/pinctrl-ambarella.c
 create mode 100644 drivers/soc/ambarella/Makefile
 create mode 100644 drivers/soc/ambarella/soc.c
 create mode 100644 drivers/tty/serial/ambarella_uart.c
 create mode 100644 drivers/tty/serial/ambarella_uart.h
 create mode 100644 include/soc/ambarella/misc.h

-- 
2.34.1

[PATCH 00/15] Ambarella S6LM SoC bring-up

[Li Chen]

This series brings up initial support for the Ambarella S6LM
SoC.

The following features are supported in this initial port:

- UART with console support
- Pinctrl with GPIO controller
- Nand flash controller
- Devicetree

Li Chen (15):
  debugfs: allow to use regmap for print regs
  dt-bindings: vendor-prefixes: add Ambarella prefix
  dt-bindings: arm: ambarella: Add binding for Ambarella ARM platforms
  dt-bindings: arm: add support for Ambarella SoC
  arm64: Kconfig: Introduce CONFIG_ARCH_AMBARELLA
  soc: add Ambarella driver
  dt-bindings: clock: Add Ambarella clock bindings
  clk: add support for Ambarella clocks
  dt-bindings: serial: add support for Ambarella
  serial: ambarella: add support for Ambarella uart_port
  dt-bindings: mtd: Add binding for Ambarella
  mtd: nand: add Ambarella nand support
  dt-bindings: pinctrl: add support for Ambarella
  pinctrl: Add pinctrl/GPIO for Ambarella SoCs
  arm64: dts: ambarella: introduce Ambarella s6lm SoC

 .../devicetree/bindings/arm/ambarella.yaml    |   22 +
 .../arm/ambarella/ambarella,cpuid.yaml        |   24 +
 .../bindings/arm/ambarella/ambarella,rct.yaml |   24 +
 .../arm/ambarella/ambarella,scratchpad.yaml   |   24 +
 .../bindings/arm/ambarella/ambarella.yaml     |   22 +
 .../clock/ambarella,composite-clock.yaml      |   52 +
 .../bindings/clock/ambarella,pll-clock.yaml   |   59 +
 .../bindings/mtd/ambarella,nand.yaml          |   77 +
 .../bindings/pinctrl/ambarella,pinctrl.yaml   |  160 ++
 .../bindings/serial/ambarella_uart.yaml       |   57 +
 .../devicetree/bindings/vendor-prefixes.yaml  |    2 +
 Documentation/filesystems/debugfs.rst         |    2 +
 MAINTAINERS                                   |   29 +
 arch/arm64/Kconfig.platforms                  |    9 +
 .../boot/dts/ambarella/ambarella-s6lm.dtsi    |  332 ++++
 .../boot/dts/ambarella/s6lm_pineapple.dts     |   29 +
 drivers/clk/Makefile                          |    1 +
 drivers/clk/ambarella/Makefile                |    5 +
 drivers/clk/ambarella/clk-composite.c         |  293 +++
 drivers/clk/ambarella/clk-pll-common.c        |  308 ++++
 drivers/clk/ambarella/clk-pll-common.h        |   96 +
 drivers/clk/ambarella/clk-pll-normal.c        |  328 ++++
 drivers/mtd/nand/raw/Kconfig                  |    8 +
 drivers/mtd/nand/raw/Makefile                 |    1 +
 drivers/mtd/nand/raw/ambarella_combo_nand.c   | 1519 ++++++++++++++++
 drivers/mtd/nand/raw/ambarella_combo_nand.h   |  370 ++++
 drivers/mtd/nand/raw/nand_ids.c               |    4 +
 drivers/pinctrl/Kconfig                       |    6 +
 drivers/pinctrl/Makefile                      |    1 +
 drivers/pinctrl/pinctrl-ambarella.c           | 1357 ++++++++++++++
 drivers/soc/Makefile                          |    1 +
 drivers/soc/ambarella/Makefile                |    3 +
 drivers/soc/ambarella/soc.c                   |  136 ++
 drivers/tty/serial/Kconfig                    |   16 +
 drivers/tty/serial/Makefile                   |    1 +
 drivers/tty/serial/ambarella_uart.c           | 1581 +++++++++++++++++
 drivers/tty/serial/ambarella_uart.h           |  120 ++
 fs/debugfs/file.c                             |   43 +-
 include/linux/debugfs.h                       |   11 +
 include/soc/ambarella/misc.h                  |   17 +
 40 files changed, 7149 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/arm/ambarella.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,scratchpad.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
 create mode 100644 Documentation/devicetree/bindings/mtd/ambarella,nand.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/ambarella,pinctrl.yaml
 create mode 100644 Documentation/devicetree/bindings/serial/ambarella_uart.yaml
 create mode 100644 arch/arm64/boot/dts/ambarella/ambarella-s6lm.dtsi
 create mode 100644 arch/arm64/boot/dts/ambarella/s6lm_pineapple.dts
 create mode 100644 drivers/clk/ambarella/Makefile
 create mode 100644 drivers/clk/ambarella/clk-composite.c
 create mode 100644 drivers/clk/ambarella/clk-pll-common.c
 create mode 100644 drivers/clk/ambarella/clk-pll-common.h
 create mode 100644 drivers/clk/ambarella/clk-pll-normal.c
 create mode 100644 drivers/mtd/nand/raw/ambarella_combo_nand.c
 create mode 100644 drivers/mtd/nand/raw/ambarella_combo_nand.h
 create mode 100644 drivers/pinctrl/pinctrl-ambarella.c
 create mode 100644 drivers/soc/ambarella/Makefile
 create mode 100644 drivers/soc/ambarella/soc.c
 create mode 100644 drivers/tty/serial/ambarella_uart.c
 create mode 100644 drivers/tty/serial/ambarella_uart.h
 create mode 100644 include/soc/ambarella/misc.h

-- 
2.34.1


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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 00/15] Ambarella S6LM SoC bring-up

[Li Chen]

This series brings up initial support for the Ambarella S6LM
SoC.

The following features are supported in this initial port:

- UART with console support
- Pinctrl with GPIO controller
- Nand flash controller
- Devicetree

Li Chen (15):
  debugfs: allow to use regmap for print regs
  dt-bindings: vendor-prefixes: add Ambarella prefix
  dt-bindings: arm: ambarella: Add binding for Ambarella ARM platforms
  dt-bindings: arm: add support for Ambarella SoC
  arm64: Kconfig: Introduce CONFIG_ARCH_AMBARELLA
  soc: add Ambarella driver
  dt-bindings: clock: Add Ambarella clock bindings
  clk: add support for Ambarella clocks
  dt-bindings: serial: add support for Ambarella
  serial: ambarella: add support for Ambarella uart_port
  dt-bindings: mtd: Add binding for Ambarella
  mtd: nand: add Ambarella nand support
  dt-bindings: pinctrl: add support for Ambarella
  pinctrl: Add pinctrl/GPIO for Ambarella SoCs
  arm64: dts: ambarella: introduce Ambarella s6lm SoC

 .../devicetree/bindings/arm/ambarella.yaml    |   22 +
 .../arm/ambarella/ambarella,cpuid.yaml        |   24 +
 .../bindings/arm/ambarella/ambarella,rct.yaml |   24 +
 .../arm/ambarella/ambarella,scratchpad.yaml   |   24 +
 .../bindings/arm/ambarella/ambarella.yaml     |   22 +
 .../clock/ambarella,composite-clock.yaml      |   52 +
 .../bindings/clock/ambarella,pll-clock.yaml   |   59 +
 .../bindings/mtd/ambarella,nand.yaml          |   77 +
 .../bindings/pinctrl/ambarella,pinctrl.yaml   |  160 ++
 .../bindings/serial/ambarella_uart.yaml       |   57 +
 .../devicetree/bindings/vendor-prefixes.yaml  |    2 +
 Documentation/filesystems/debugfs.rst         |    2 +
 MAINTAINERS                                   |   29 +
 arch/arm64/Kconfig.platforms                  |    9 +
 .../boot/dts/ambarella/ambarella-s6lm.dtsi    |  332 ++++
 .../boot/dts/ambarella/s6lm_pineapple.dts     |   29 +
 drivers/clk/Makefile                          |    1 +
 drivers/clk/ambarella/Makefile                |    5 +
 drivers/clk/ambarella/clk-composite.c         |  293 +++
 drivers/clk/ambarella/clk-pll-common.c        |  308 ++++
 drivers/clk/ambarella/clk-pll-common.h        |   96 +
 drivers/clk/ambarella/clk-pll-normal.c        |  328 ++++
 drivers/mtd/nand/raw/Kconfig                  |    8 +
 drivers/mtd/nand/raw/Makefile                 |    1 +
 drivers/mtd/nand/raw/ambarella_combo_nand.c   | 1519 ++++++++++++++++
 drivers/mtd/nand/raw/ambarella_combo_nand.h   |  370 ++++
 drivers/mtd/nand/raw/nand_ids.c               |    4 +
 drivers/pinctrl/Kconfig                       |    6 +
 drivers/pinctrl/Makefile                      |    1 +
 drivers/pinctrl/pinctrl-ambarella.c           | 1357 ++++++++++++++
 drivers/soc/Makefile                          |    1 +
 drivers/soc/ambarella/Makefile                |    3 +
 drivers/soc/ambarella/soc.c                   |  136 ++
 drivers/tty/serial/Kconfig                    |   16 +
 drivers/tty/serial/Makefile                   |    1 +
 drivers/tty/serial/ambarella_uart.c           | 1581 +++++++++++++++++
 drivers/tty/serial/ambarella_uart.h           |  120 ++
 fs/debugfs/file.c                             |   43 +-
 include/linux/debugfs.h                       |   11 +
 include/soc/ambarella/misc.h                  |   17 +
 40 files changed, 7149 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/arm/ambarella.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,scratchpad.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
 create mode 100644 Documentation/devicetree/bindings/mtd/ambarella,nand.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/ambarella,pinctrl.yaml
 create mode 100644 Documentation/devicetree/bindings/serial/ambarella_uart.yaml
 create mode 100644 arch/arm64/boot/dts/ambarella/ambarella-s6lm.dtsi
 create mode 100644 arch/arm64/boot/dts/ambarella/s6lm_pineapple.dts
 create mode 100644 drivers/clk/ambarella/Makefile
 create mode 100644 drivers/clk/ambarella/clk-composite.c
 create mode 100644 drivers/clk/ambarella/clk-pll-common.c
 create mode 100644 drivers/clk/ambarella/clk-pll-common.h
 create mode 100644 drivers/clk/ambarella/clk-pll-normal.c
 create mode 100644 drivers/mtd/nand/raw/ambarella_combo_nand.c
 create mode 100644 drivers/mtd/nand/raw/ambarella_combo_nand.h
 create mode 100644 drivers/pinctrl/pinctrl-ambarella.c
 create mode 100644 drivers/soc/ambarella/Makefile
 create mode 100644 drivers/soc/ambarella/soc.c
 create mode 100644 drivers/tty/serial/ambarella_uart.c
 create mode 100644 drivers/tty/serial/ambarella_uart.h
 create mode 100644 include/soc/ambarella/misc.h

-- 
2.34.1


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH 02/15] dt-bindings: vendor-prefixes: add Ambarella prefix

[Li Chen]

Add vendor prefix for Ambarella, Inc.

Signed-off-by: Li Chen <lchen@ambarella.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 70ffb3780621..97bfd98fcae1 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -89,6 +89,8 @@ patternProperties:
     description: Amarula Solutions
   "^amazon,.*":
     description: Amazon.com, Inc.
+  "^ambarella,.*":
+    description: Ambarella, Inc.
   "^amcc,.*":
     description: Applied Micro Circuits Corporation (APM, formally AMCC)
   "^amd,.*":
-- 
2.34.1

Re: [PATCH 02/15] dt-bindings: vendor-prefixes: add Ambarella prefix

[Krzysztof Kozlowski]

On 23/01/2023 08:32, Li Chen wrote:
> Add vendor prefix for Ambarella, Inc.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH 05/15] arm64: Kconfig: Introduce CONFIG_ARCH_AMBARELLA

[Li Chen]

This adds a Kconfig option to toggle support
for Ambarella ARM SoCs.

Signed-off-by: Li Chen <lchen@ambarella.com>
Change-Id: I41345f5052b08023d399cb9db3faa228ca54d265
---
 arch/arm64/Kconfig.platforms | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index d1970adf80ab..8def8aaca0c4 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -8,6 +8,15 @@ config ARCH_ACTIONS
 	help
 	  This enables support for the Actions Semiconductor S900 SoC family.
 
+config ARCH_AMBARELLA
+	bool "Ambarella ARMv8 SoC Family"
+	select PINCTRL
+	select PINCTRL_AMB
+	select RATIONAL
+	help
+	  This enables support for Ambarella ARMv8 SoC Family starting
+          from s6lm.
+
 config ARCH_SUNXI
 	bool "Allwinner sunxi 64-bit SoC Family"
 	select ARCH_HAS_RESET_CONTROLLER
-- 
2.34.1

[PATCH 05/15] arm64: Kconfig: Introduce CONFIG_ARCH_AMBARELLA

[Li Chen]

This adds a Kconfig option to toggle support
for Ambarella ARM SoCs.

Signed-off-by: Li Chen <lchen@ambarella.com>
Change-Id: I41345f5052b08023d399cb9db3faa228ca54d265
---
 arch/arm64/Kconfig.platforms | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index d1970adf80ab..8def8aaca0c4 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -8,6 +8,15 @@ config ARCH_ACTIONS
 	help
 	  This enables support for the Actions Semiconductor S900 SoC family.
 
+config ARCH_AMBARELLA
+	bool "Ambarella ARMv8 SoC Family"
+	select PINCTRL
+	select PINCTRL_AMB
+	select RATIONAL
+	help
+	  This enables support for Ambarella ARMv8 SoC Family starting
+          from s6lm.
+
 config ARCH_SUNXI
 	bool "Allwinner sunxi 64-bit SoC Family"
 	select ARCH_HAS_RESET_CONTROLLER
-- 
2.34.1


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Re: [PATCH 05/15] arm64: Kconfig: Introduce CONFIG_ARCH_AMBARELLA

[Arnd Bergmann]

On Mon, Jan 23, 2023, at 08:32, Li Chen wrote:
> +config ARCH_AMBARELLA
> +	bool "Ambarella ARMv8 SoC Family"
> +	select PINCTRL
> +	select PINCTRL_AMB
> +	select RATIONAL
> +	help
> +	  This enables support for Ambarella ARMv8 SoC Family starting
> +          from s6lm.

The patch is ok, but drop the "ARMv8" from the "bool" prompt,
we are removing this from all the other entries as well.

     Arnd

Re: [PATCH 05/15] arm64: Kconfig: Introduce CONFIG_ARCH_AMBARELLA

[Arnd Bergmann]

On Mon, Jan 23, 2023, at 08:32, Li Chen wrote:
> +config ARCH_AMBARELLA
> +	bool "Ambarella ARMv8 SoC Family"
> +	select PINCTRL
> +	select PINCTRL_AMB
> +	select RATIONAL
> +	help
> +	  This enables support for Ambarella ARMv8 SoC Family starting
> +          from s6lm.

The patch is ok, but drop the "ARMv8" from the "bool" prompt,
we are removing this from all the other entries as well.

     Arnd

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[PATCH 10/15] serial: ambarella: add support for Ambarella uart_port

[Li Chen]

This driver add support for Ambarella's uart, which
can be used for console and etc.

Signed-off-by: Li Chen <lchen@ambarella.com>
Change-Id: Ie68af7ad2187e21853e58d52cd97fd7145303730
---
 MAINTAINERS                         |    1 +
 drivers/tty/serial/Kconfig          |   16 +
 drivers/tty/serial/Makefile         |    1 +
 drivers/tty/serial/ambarella_uart.c | 1581 +++++++++++++++++++++++++++
 drivers/tty/serial/ambarella_uart.h |  120 ++
 5 files changed, 1719 insertions(+)
 create mode 100644 drivers/tty/serial/ambarella_uart.c
 create mode 100644 drivers/tty/serial/ambarella_uart.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 080412535e26..ee1d201dd89a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1909,6 +1909,7 @@ F:	drivers/clk/ambarella/clk-pll-common.h
 F:	drivers/clk/ambarella/clk-pll-normal.c
 F:	drivers/soc/ambarella/Makefile
 F:	drivers/soc/ambarella/soc.c
+F:	drivers/tty/serial/ambarella_uart.c
 F:	include/soc/ambarella/misc.h
 
 ARM/Amlogic Meson SoC CLOCK FRAMEWORK
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index c55b947f3cdb..27216ecc3161 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -18,6 +18,22 @@ source "drivers/tty/serial/8250/Kconfig"
 
 comment "Non-8250 serial port support"
 
+config SERIAL_AMBARELLA
+	tristate "Ambarella Media Soc serial port support"
+	depends on ARCH_AMBARELLA
+	select SERIAL_CORE
+	help
+	  If you have a machine based on an Ambarella Media SoC you
+	  can enable its onboard serial ports by enabling this option.
+
+config SERIAL_AMBARELLA_CONSOLE
+	bool "Console on Ambarella Media SoC serial port"
+	depends on SERIAL_AMBARELLA=y
+	select SERIAL_CORE_CONSOLE
+	help
+	  If you have enabled the serial port on the Ambarella Media SoC
+	  you can make it the console by answering Y to this option.
+
 config SERIAL_AMBA_PL010
 	tristate "ARM AMBA PL010 serial port support"
 	depends on ARM_AMBA || COMPILE_TEST
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 238a9557b487..00e454e06976 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -3,6 +3,7 @@
 # Makefile for the kernel serial device drivers.
 #
 
+obj-$(CONFIG_SERIAL_AMBARELLA) += ambarella_uart.o
 obj-$(CONFIG_SERIAL_CORE) += serial_core.o
 
 obj-$(CONFIG_SERIAL_EARLYCON) += earlycon.o
diff --git a/drivers/tty/serial/ambarella_uart.c b/drivers/tty/serial/ambarella_uart.c
new file mode 100644
index 000000000000..54de84fbb623
--- /dev/null
+++ b/drivers/tty/serial/ambarella_uart.c
@@ -0,0 +1,1581 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Author: Anthony Ginger <hfjiang@ambarella.com>
+ *
+ * Copyright (C) 2023, Ambarella, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#if defined(CONFIG_SERIAL_AMBARELLA_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#include <asm-generic/types.h>
+#include "ambarella_uart.h"
+#include <asm-generic/errno-base.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/clk.h>
+#include <linux/syscore_ops.h>
+#include <linux/console.h>
+#include <linux/sysrq.h>
+#include <linux/slab.h>
+#include <linux/serial_reg.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/delay.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmapool.h>
+
+#define	AMBA_UART_MAX_NUM			8
+
+#define AMBA_UART_RX_DMA_BUFFER_SIZE PAGE_SIZE
+#define AMBA_UART_MIN_DMA			16
+#define AMBA_UART_LSR_ANY \
+	(UART_LSR_OE | UART_LSR_BI | UART_LSR_PE | UART_LSR_FE)
+
+#define AMBA_UART_RESET_FLAG			0 /* bit 0 */
+
+struct ambarella_uart_port {
+	struct uart_port port;
+	struct clk *uart_pll;
+	struct clk *parent_pll;
+	unsigned long flags;
+	u32 msr_used : 1;
+	u32 tx_fifo_fix : 1;
+	u32 less_reg : 1;
+	u32 txdma_used:1;
+	u32 rxdma_used:1;
+	u32 mcr;
+	u32 c_cflag;
+	/* following are for dma transfer */
+	struct dma_chan *rx_dma_chan;
+	struct dma_chan *tx_dma_chan;
+	unsigned char *rx_dma_buf_virt;
+	unsigned char *tx_dma_buf_virt;
+	dma_addr_t rx_dma_buf_phys;
+	dma_addr_t tx_dma_buf_phys;
+	struct dma_async_tx_descriptor *tx_dma_desc;
+	struct dma_async_tx_descriptor *rx_dma_desc;
+	dma_cookie_t tx_cookie;
+	dma_cookie_t rx_cookie;
+	int tx_bytes_requested;
+	int rx_bytes_requested;
+	bool tx_in_progress;
+	bool rx_in_progress;
+	bool ignore_fe;
+#ifdef CONFIG_PM
+	u32 clk_rate;
+#endif
+};
+
+static struct ambarella_uart_port ambarella_port[AMBA_UART_MAX_NUM];
+
+static void __serial_ambarella_stop_tx(struct uart_port *port, u32 tx_fifo_fix)
+{
+	struct ambarella_uart_port *amb_port;
+	struct circ_buf *xmit = &port->state->xmit;
+	struct dma_tx_state state;
+	u32 ier, iir;
+	int count;
+
+	amb_port = (struct ambarella_uart_port *)(port->private_data);
+
+	if (tx_fifo_fix) {
+		ier = readl_relaxed(port->membase + UART_IE_OFFSET);
+		if ((ier & UART_IE_PTIME) != UART_IE_PTIME)
+			writel_relaxed(ier | UART_IE_PTIME | UART_IE_ETBEI,
+					port->membase + UART_IE_OFFSET);
+
+		iir = readl_relaxed(port->membase + UART_II_OFFSET);
+		writel_relaxed(ier & ~(UART_IE_PTIME | UART_IE_ETBEI),
+				port->membase + UART_IE_OFFSET);
+		(void)(iir);
+	} else {
+		ier = readl_relaxed(port->membase + UART_IE_OFFSET);
+		writel_relaxed(ier & ~UART_IE_ETBEI, port->membase + UART_IE_OFFSET);
+	}
+
+	if (amb_port->txdma_used && amb_port->tx_in_progress) {
+		dmaengine_tx_status(amb_port->tx_dma_chan, amb_port->tx_cookie, &state);
+		dmaengine_terminate_all(amb_port->tx_dma_chan);
+		count = amb_port->tx_bytes_requested - state.residue;
+		xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
+		port->icount.tx += count;
+		amb_port->tx_in_progress = false;
+	}
+}
+
+static u32 __serial_ambarella_read_ms(struct uart_port *port, u32 tx_fifo_fix)
+{
+	u32 ier, ms;
+
+	if (tx_fifo_fix) {
+		ier = readl_relaxed(port->membase + UART_IE_OFFSET);
+		if ((ier & UART_IE_EDSSI) != UART_IE_EDSSI)
+			writel_relaxed(ier | UART_IE_EDSSI,
+					port->membase + UART_IE_OFFSET);
+
+		ms = readl_relaxed(port->membase + UART_MS_OFFSET);
+		if ((ier & UART_IE_EDSSI) != UART_IE_EDSSI)
+			writel_relaxed(ier, port->membase + UART_IE_OFFSET);
+	} else {
+		ms = readl_relaxed(port->membase + UART_MS_OFFSET);
+	}
+
+	return ms;
+}
+
+static void __serial_ambarella_enable_ms(struct uart_port *port)
+{
+	u32 ier = readl_relaxed(port->membase + UART_IE_OFFSET);
+
+	writel_relaxed(ier | UART_IE_EDSSI, port->membase + UART_IE_OFFSET);
+}
+
+static void __serial_ambarella_disable_ms(struct uart_port *port)
+{
+	u32 ier = readl_relaxed(port->membase + UART_IE_OFFSET);
+
+	writel_relaxed(ier & ~UART_IE_EDSSI, port->membase + UART_IE_OFFSET);
+}
+
+static inline void wait_for_tx(struct uart_port *port)
+{
+	u32 ls;
+
+	ls = readl_relaxed(port->membase + UART_LS_OFFSET);
+	while ((ls & UART_LS_TEMT) != UART_LS_TEMT) {
+		cpu_relax();
+		ls = readl_relaxed(port->membase + UART_LS_OFFSET);
+	}
+}
+
+static inline void wait_for_rx(struct uart_port *port)
+{
+	u32 ls;
+
+	ls = readl_relaxed(port->membase + UART_LS_OFFSET);
+	while ((ls & UART_LS_DR) != UART_LS_DR) {
+		cpu_relax();
+		ls = readl_relaxed(port->membase + UART_LS_OFFSET);
+	}
+}
+
+static inline int tx_fifo_is_full(struct uart_port *port)
+{
+	return !(readl_relaxed(port->membase + UART_US_OFFSET) & UART_US_TFNF);
+}
+
+/* ==========================================================================*/
+static void serial_ambarella_hw_setup(struct uart_port *port)
+{
+	struct ambarella_uart_port *amb_port;
+
+	amb_port = (struct ambarella_uart_port *)(port->private_data);
+
+	if (!test_and_set_bit(AMBA_UART_RESET_FLAG, &amb_port->flags)) {
+		port->uartclk = clk_get_rate(amb_port->uart_pll);
+		/* reset the whole UART only once */
+		writel_relaxed(0x01, port->membase + UART_SRR_OFFSET);
+		mdelay(1);
+		writel_relaxed(0x00, port->membase + UART_SRR_OFFSET);
+	}
+
+	writel_relaxed(DEFAULT_AMBARELLA_UART_IER | UART_IE_PTIME,
+			port->membase + UART_IE_OFFSET);
+	writel_relaxed(UART_FC_FIFOE | UART_FC_RX_2_TO_FULL | UART_FC_TX_EMPTY |
+			UART_FC_XMITR | UART_FC_RCVRR, port->membase + UART_FC_OFFSET);
+	writel_relaxed(DEFAULT_AMBARELLA_UART_IER, port->membase + UART_IE_OFFSET);
+
+	if (amb_port->txdma_used || amb_port->rxdma_used) {
+		/*
+		 * we must use 14bytes as trigger, because if we use 8bytes, FIFO may
+		 * be empty due to dma burst size is also set to 8bytes before dma complete,
+		 * in this case, if FIFO is empty, but no more data is received, timeout irq
+		 * can't be trigged after, we don't have chance to push the data that dma has
+		 * transferred any more.
+		 */
+		writel_relaxed(UART_FC_FIFOE | UART_FC_RX_2_TO_FULL |
+			UART_FC_TX_EMPTY | UART_FC_XMITR | UART_FC_RCVRR |
+			UART_FCR_DMA_SELECT, port->membase + UART_FC_OFFSET);
+		writel_relaxed((amb_port->txdma_used << 1) | amb_port->rxdma_used,
+			port->membase + UART_DMAE_OFFSET);
+
+		writel_relaxed(UART_IE_ETOI, port->membase + UART_IE_OFFSET);
+	}
+}
+
+static inline void serial_ambarella_receive_chars(struct uart_port *port,
+	u32 tmo)
+{
+	struct ambarella_uart_port *amb_port;
+	u32 ch, flag, ls;
+	int max_count;
+
+	amb_port = (struct ambarella_uart_port *)(port->private_data);
+
+	ls = readl_relaxed(port->membase + UART_LS_OFFSET);
+	max_count = port->fifosize;
+
+	do {
+		flag = TTY_NORMAL;
+		if (unlikely(ls & (UART_LS_BI | UART_LS_PE |
+					UART_LS_FE | UART_LS_OE))) {
+			if (ls & UART_LS_BI) {
+				ls &= ~(UART_LS_FE | UART_LS_PE);
+				port->icount.brk++;
+
+				if (uart_handle_break(port))
+					goto ignore_char;
+			}
+			if ((ls & UART_LS_FE) && !amb_port->ignore_fe)
+				port->icount.frame++;
+			if (ls & UART_LS_PE)
+				port->icount.parity++;
+			if (ls & UART_LS_OE)
+				port->icount.overrun++;
+
+			ls &= port->read_status_mask;
+
+			if (ls & UART_LS_BI)
+				flag = TTY_BREAK;
+			else if (ls & UART_LS_FE && !amb_port->ignore_fe)
+				flag = TTY_FRAME;
+			else if (ls & UART_LS_PE)
+				flag = TTY_PARITY;
+			else if (ls & UART_LS_OE)
+				flag = TTY_OVERRUN;
+
+			if (ls & UART_LS_OE)
+				pr_debug("%s: OVERFLOW\n", __func__);
+		}
+
+		if (likely(ls & UART_LS_DR)) {
+			ch = readl_relaxed(port->membase + UART_RB_OFFSET);
+			port->icount.rx++;
+			tmo = 0;
+
+			if (uart_handle_sysrq_char(port, ch))
+				goto ignore_char;
+
+			uart_insert_char(port, ls, UART_LS_OE, ch, flag);
+		} else {
+			if (tmo) {
+				ch = readl_relaxed(port->membase + UART_RB_OFFSET);
+				/* printk(KERN_DEBUG "False TMO get %d\n", ch); */
+			}
+		}
+
+ignore_char:
+		ls = readl_relaxed(port->membase + UART_LS_OFFSET);
+	} while ((ls & (UART_LS_DR | UART_LSR_BI)) && (max_count-- > 0));
+
+	tty_flip_buffer_push(&port->state->port);
+}
+
+static void serial_ambarella_transmit_chars(struct uart_port *port)
+{
+	struct circ_buf *xmit = &port->state->xmit;
+	struct ambarella_uart_port *amb_port;
+	int count;
+
+	amb_port = (struct ambarella_uart_port *)(port->private_data);
+
+	if (port->x_char) {
+		writel_relaxed(port->x_char, port->membase + UART_TH_OFFSET);
+		port->icount.tx++;
+		port->x_char = 0;
+		return;
+	}
+
+	if (uart_tx_stopped(port) || uart_circ_empty(xmit)) {
+		__serial_ambarella_stop_tx(port, amb_port->tx_fifo_fix);
+		return;
+	}
+
+	count = port->fifosize;
+	while (count-- > 0) {
+		if (!amb_port->less_reg && tx_fifo_is_full(port))
+			break;
+		writel_relaxed(xmit->buf[xmit->tail], port->membase + UART_TH_OFFSET);
+		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+		port->icount.tx++;
+		if (uart_circ_empty(xmit))
+			break;
+	}
+
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(port);
+	if (uart_circ_empty(xmit))
+		__serial_ambarella_stop_tx(port, amb_port->tx_fifo_fix);
+}
+
+static inline void serial_ambarella_check_modem_status(struct uart_port *port)
+{
+	struct ambarella_uart_port *amb_port;
+	u32 ms;
+
+	amb_port = (struct ambarella_uart_port *)(port->private_data);
+
+	if (amb_port->msr_used) {
+		ms = __serial_ambarella_read_ms(port, amb_port->tx_fifo_fix);
+
+		if (ms & UART_MS_RI)
+			port->icount.rng++;
+		if (ms & UART_MS_DSR)
+			port->icount.dsr++;
+		if (ms & UART_MS_DCTS)
+			uart_handle_cts_change(port, (ms & UART_MS_CTS));
+		if (ms & UART_MS_DDCD)
+			uart_handle_dcd_change(port, (ms & UART_MS_DCD));
+
+		wake_up_interruptible(&port->state->port.delta_msr_wait);
+	}
+}
+
+static char serial_ambarella_decode_rx_error(struct ambarella_uart_port *amb_port,
+			unsigned long lsr)
+{
+	char flag = TTY_NORMAL;
+
+	if (unlikely(lsr & AMBA_UART_LSR_ANY)) {
+		if (lsr & UART_LSR_OE) {
+			/* Overrun error */
+			flag |= TTY_OVERRUN;
+			amb_port->port.icount.overrun++;
+		}
+		if (lsr & UART_LSR_PE) {
+			/* Parity error */
+			flag |= TTY_PARITY;
+			amb_port->port.icount.parity++;
+		}
+		if ((lsr & UART_LSR_FE) && !amb_port->ignore_fe) {
+			flag |= TTY_FRAME;
+			amb_port->port.icount.frame++;
+		}
+		if (lsr & UART_LSR_BI) {
+			amb_port->port.icount.brk++;
+			/* If FIFO read error without any data, reset Rx FIFO */
+			if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
+				writel_relaxed(UART_FCR_CLEAR_RCVR,
+					amb_port->port.membase + UART_SRR_OFFSET);
+		}
+	}
+	return flag;
+}
+
+static void serial_ambarella_handle_rx_pio(struct ambarella_uart_port *amb_port,
+		struct tty_port *tty)
+{
+	int cnt;
+
+	for (cnt = 0; cnt < amb_port->port.fifosize; cnt++) {
+		char flag = TTY_NORMAL;
+		unsigned long lsr = 0;
+		unsigned char ch;
+
+		lsr = readl_relaxed(amb_port->port.membase + UART_LS_OFFSET);
+		if (!(lsr & UART_LS_DR))
+			break;
+
+		flag = serial_ambarella_decode_rx_error(amb_port, lsr);
+		ch = (unsigned char) readl_relaxed(amb_port->port.membase + UART_RB_OFFSET);
+		amb_port->port.icount.rx++;
+
+		if (!uart_handle_sysrq_char(&amb_port->port, ch) && tty)
+			tty_insert_flip_char(tty, ch, flag);
+	}
+
+	/* do a dummy read to clear interrupt */
+	if (!cnt)
+		readl_relaxed(amb_port->port.membase + UART_RB_OFFSET);
+}
+
+static void serial_ambarella_copy_rx_to_tty(struct ambarella_uart_port *amb_port,
+		struct tty_port *tty, int count);
+static int serial_ambarella_start_rx_dma(struct ambarella_uart_port *amb_port);
+
+static void serial_ambarella_dma_rx_irq(struct ambarella_uart_port *amb_port)
+{
+	struct tty_port *port = &amb_port->port.state->port;
+	struct dma_tx_state state;
+	size_t pending;
+	u32 value;
+
+	dmaengine_pause(amb_port->rx_dma_chan);
+	value = readl_relaxed(amb_port->port.membase + UART_DMAE_OFFSET);
+	writel_relaxed(value & ~0x1, amb_port->port.membase + UART_DMAE_OFFSET);
+
+	dmaengine_tx_status(amb_port->rx_dma_chan, amb_port->rx_cookie, &state);
+	dmaengine_terminate_async(amb_port->rx_dma_chan);
+
+	pending = amb_port->rx_bytes_requested - state.residue;
+	BUG_ON(pending > AMBA_UART_RX_DMA_BUFFER_SIZE);
+
+	serial_ambarella_copy_rx_to_tty(amb_port, port, pending);
+	serial_ambarella_handle_rx_pio(amb_port, port);
+
+	tty_flip_buffer_push(port);
+
+	writel_relaxed(value, amb_port->port.membase + UART_DMAE_OFFSET);
+	dmaengine_resume(amb_port->rx_dma_chan);
+
+	serial_ambarella_start_rx_dma(amb_port);
+}
+
+static irqreturn_t serial_ambarella_irq(int irq, void *dev_id)
+{
+	struct uart_port *port = dev_id;
+	struct ambarella_uart_port *amb_port;
+	int rval = IRQ_HANDLED;
+	unsigned long flags;
+	u32 ii;
+
+	amb_port = (struct ambarella_uart_port *)(port->private_data);
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	ii = readl_relaxed(port->membase + UART_II_OFFSET);
+	switch (ii & 0x0F) {
+	case UART_II_MODEM_STATUS_CHANGED:
+		serial_ambarella_check_modem_status(port);
+		break;
+
+	case UART_II_THR_EMPTY:
+		serial_ambarella_transmit_chars(port);
+		break;
+
+	case UART_II_RCV_STATUS:
+	case UART_II_RCV_DATA_AVAIL:
+		serial_ambarella_receive_chars(port, 0);
+		break;
+	case UART_II_CHAR_TIMEOUT:
+		if (amb_port->rxdma_used && amb_port->rx_dma_chan)
+			serial_ambarella_dma_rx_irq(amb_port);
+		else
+			serial_ambarella_receive_chars(port, 1);
+		break;
+
+	case UART_II_NO_INT_PENDING:
+		break;
+	default:
+		pr_debug("%s: 0x%x\n", __func__, ii);
+		break;
+	}
+
+	spin_unlock_irqrestore(&port->lock, flags);
+
+	return rval;
+}
+
+/* ==========================================================================*/
+static void serial_ambarella_enable_ms(struct uart_port *port)
+{
+	__serial_ambarella_enable_ms(port);
+}
+
+static void serial_ambarella_start_next_tx(struct ambarella_uart_port *amb_port);
+
+static void serial_ambarella_tx_dma_complete(void *args)
+{
+	struct ambarella_uart_port *amb_port = args;
+	struct circ_buf *xmit = &amb_port->port.state->xmit;
+	struct dma_tx_state state;
+	unsigned long flags;
+	int count;
+
+	dmaengine_tx_status(amb_port->tx_dma_chan, amb_port->tx_cookie, &state);
+	count = amb_port->tx_bytes_requested - state.residue;
+	spin_lock_irqsave(&amb_port->port.lock, flags);
+	xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
+	amb_port->tx_in_progress = false;
+	amb_port->port.icount.tx += count;
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(&amb_port->port);
+	serial_ambarella_start_next_tx(amb_port);
+	spin_unlock_irqrestore(&amb_port->port.lock, flags);
+}
+
+static int serial_ambarella_start_tx_dma(struct ambarella_uart_port *amb_port,
+		unsigned long count)
+{
+	struct circ_buf *xmit = &amb_port->port.state->xmit;
+	dma_addr_t tx_phys_addr;
+	int tx_bytes;
+
+	dma_sync_single_for_device(amb_port->port.dev, amb_port->tx_dma_buf_phys,
+				UART_XMIT_SIZE, DMA_TO_DEVICE);
+
+	tx_bytes = count & ~(0xF);
+	tx_phys_addr = amb_port->tx_dma_buf_phys + xmit->tail;
+	amb_port->tx_dma_desc = dmaengine_prep_slave_single(amb_port->tx_dma_chan,
+				tx_phys_addr, tx_bytes, DMA_MEM_TO_DEV,
+				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+	if (!amb_port->tx_dma_desc) {
+		dev_err(amb_port->port.dev, "Not able to get desc for Tx\n");
+		return -EIO;
+	}
+
+	amb_port->tx_dma_desc->callback = serial_ambarella_tx_dma_complete;
+	amb_port->tx_dma_desc->callback_param = amb_port;
+	amb_port->tx_bytes_requested = tx_bytes;
+	amb_port->tx_in_progress = true;
+	amb_port->tx_cookie = dmaengine_submit(amb_port->tx_dma_desc);
+	dma_async_issue_pending(amb_port->tx_dma_chan);
+
+	return 0;
+}
+
+static void serial_ambarella_start_next_tx(struct ambarella_uart_port *amb_port)
+{
+	struct circ_buf *xmit = &amb_port->port.state->xmit;
+	struct uart_port *port;
+	unsigned long tail, count;
+
+	port = &amb_port->port;
+
+	tail = (unsigned long)&xmit->buf[xmit->tail];
+	count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
+	if (!count)
+		return;
+
+	if (count < AMBA_UART_MIN_DMA) {
+		wait_for_tx(port);
+		serial_ambarella_transmit_chars(port);
+		serial_ambarella_start_next_tx(amb_port);
+	} else {
+		serial_ambarella_start_tx_dma(amb_port, count);
+	}
+}
+
+static void serial_ambarella_start_tx(struct uart_port *port)
+{
+	struct ambarella_uart_port *amb_port;
+	u32 ier;
+
+	amb_port = (struct ambarella_uart_port *)(port->private_data);
+
+	if (amb_port->txdma_used) {
+		if (uart_tx_stopped(port) || amb_port->tx_in_progress)
+			return;
+		serial_ambarella_start_next_tx(amb_port);
+	} else {
+		ier = readl_relaxed(port->membase + UART_IE_OFFSET);
+		writel_relaxed(ier | UART_IE_ETBEI, port->membase + UART_IE_OFFSET);
+
+		/*
+		 * if FIFO status register is not provided, we have no idea about
+		 * the Tx FIFO is full or not, so we need to wait for the Tx Empty
+		 * Interrupt coming, then we can start to transfer data.
+		 */
+		if (amb_port->less_reg)
+			return;
+
+		serial_ambarella_transmit_chars(port);
+	}
+}
+
+static void serial_ambarella_copy_rx_to_tty(struct ambarella_uart_port *amb_port,
+		struct tty_port *tty, int count)
+{
+	int copied;
+
+	amb_port->port.icount.rx += count;
+	if (!tty) {
+		dev_err(amb_port->port.dev, "No tty port\n");
+		return;
+	}
+
+	dma_sync_single_for_cpu(amb_port->port.dev, amb_port->rx_dma_buf_phys,
+		AMBA_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
+	copied = tty_insert_flip_string(tty, amb_port->rx_dma_buf_virt, count);
+	if (copied != count)
+		pr_warn_ratelimited("%s:Unable to push data ret %d_bytes %d\n",
+			__func__, copied, count);
+}
+
+static void serial_ambarella_rx_dma_complete(void *args)
+{
+	struct ambarella_uart_port *amb_port = args;
+	struct uart_port *u = &amb_port->port;
+	struct tty_port *port = &u->state->port;
+	int count = amb_port->rx_bytes_requested;
+	unsigned long flags;
+
+	spin_lock_irqsave(&u->lock, flags);
+	serial_ambarella_copy_rx_to_tty(amb_port, port, count);
+	tty_flip_buffer_push(port);
+	serial_ambarella_start_rx_dma(amb_port);
+	spin_unlock_irqrestore(&u->lock, flags);
+}
+
+static int serial_ambarella_start_rx_dma(struct ambarella_uart_port *amb_port)
+{
+	unsigned int count = AMBA_UART_RX_DMA_BUFFER_SIZE;
+
+	amb_port->rx_dma_desc = dmaengine_prep_slave_single(amb_port->rx_dma_chan,
+				amb_port->rx_dma_buf_phys, count, DMA_DEV_TO_MEM,
+				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+
+	if (!amb_port->rx_dma_desc) {
+		dev_err(amb_port->port.dev, "Not able to get desc for Rx\n");
+		return -EIO;
+	}
+
+	amb_port->rx_dma_desc->callback = serial_ambarella_rx_dma_complete;
+	amb_port->rx_dma_desc->callback_param = amb_port;
+	dma_sync_single_for_device(amb_port->port.dev, amb_port->rx_dma_buf_phys,
+		count, DMA_FROM_DEVICE);
+	amb_port->rx_bytes_requested = count;
+	amb_port->rx_cookie = dmaengine_submit(amb_port->rx_dma_desc);
+	dma_async_issue_pending(amb_port->rx_dma_chan);
+
+	return 0;
+}
+
+static void serial_ambarella_stop_tx(struct uart_port *port)
+{
+	struct ambarella_uart_port *amb_port;
+
+	amb_port = (struct ambarella_uart_port *)(port->private_data);
+	__serial_ambarella_stop_tx(port, amb_port->tx_fifo_fix);
+}
+
+static void serial_ambarella_stop_rx(struct uart_port *port)
+{
+	struct ambarella_uart_port *amb_port = (struct ambarella_uart_port *)(port->private_data);
+	struct tty_port *tty_port = &port->state->port;
+	struct dma_tx_state state;
+	size_t pending;
+	u32 ier;
+
+	if (amb_port->rxdma_used) {
+		if (!amb_port->rx_in_progress)
+			return;
+
+		ier = readl_relaxed(port->membase + UART_IE_OFFSET);
+		writel_relaxed(ier & ~UART_IE_ETOI, port->membase + UART_IE_OFFSET);
+
+		amb_port->rx_in_progress = false;
+		dmaengine_tx_status(amb_port->rx_dma_chan, amb_port->rx_cookie, &state);
+		dmaengine_terminate_async(amb_port->rx_dma_chan);
+
+		pending = amb_port->rx_bytes_requested - state.residue;
+		BUG_ON(pending > AMBA_UART_RX_DMA_BUFFER_SIZE);
+
+		serial_ambarella_copy_rx_to_tty(amb_port, tty_port, pending);
+		serial_ambarella_handle_rx_pio(amb_port, tty_port);
+
+		tty_flip_buffer_push(tty_port);
+	} else {
+		ier = readl_relaxed(port->membase + UART_IE_OFFSET);
+		writel_relaxed(ier & ~UART_IE_ERBFI, port->membase + UART_IE_OFFSET);
+	}
+
+}
+
+static unsigned int serial_ambarella_tx_empty(struct uart_port *port)
+{
+	unsigned int lsr;
+	unsigned long flags;
+
+	spin_lock_irqsave(&port->lock, flags);
+	lsr = readl_relaxed(port->membase + UART_LS_OFFSET);
+	spin_unlock_irqrestore(&port->lock, flags);
+
+	return ((lsr & (UART_LS_TEMT | UART_LS_THRE)) ==
+		(UART_LS_TEMT | UART_LS_THRE)) ? TIOCSER_TEMT : 0;
+}
+
+static unsigned int serial_ambarella_get_mctrl(struct uart_port *port)
+{
+	struct ambarella_uart_port *amb_port;
+	u32 ms, mctrl = 0;
+
+	amb_port = (struct ambarella_uart_port *)(port->private_data);
+
+	if (amb_port->msr_used) {
+		ms = __serial_ambarella_read_ms(port, amb_port->tx_fifo_fix);
+
+		if (ms & UART_MS_CTS)
+			mctrl |= TIOCM_CTS;
+		if (ms & UART_MS_DSR)
+			mctrl |= TIOCM_DSR;
+		if (ms & UART_MS_RI)
+			mctrl |= TIOCM_RI;
+		if (ms & UART_MS_DCD)
+			mctrl |= TIOCM_CD;
+	}
+
+	return mctrl;
+}
+
+static void serial_ambarella_set_mctrl(struct uart_port *port,
+	unsigned int mctrl)
+{
+	struct ambarella_uart_port *amb_port;
+	u32 mcr, mcr_new = 0;
+
+	amb_port = (struct ambarella_uart_port *)(port->private_data);
+
+	if (amb_port->msr_used) {
+		mcr = readl_relaxed(port->membase + UART_MC_OFFSET);
+
+		if (mctrl & TIOCM_DTR)
+			mcr_new |= UART_MC_DTR;
+		if (mctrl & TIOCM_RTS)
+			mcr_new |= UART_MC_RTS;
+		if (mctrl & TIOCM_OUT1)
+			mcr_new |= UART_MC_OUT1;
+		if (mctrl & TIOCM_OUT2)
+			mcr_new |= UART_MC_OUT2;
+		if (mctrl & TIOCM_LOOP)
+			mcr_new |= UART_MC_LB;
+
+		mcr_new |= amb_port->mcr;
+		if (mcr_new != mcr) {
+			if ((mcr & UART_MC_AFCE) == UART_MC_AFCE) {
+				mcr &= ~UART_MC_AFCE;
+				writel_relaxed(mcr, port->membase + UART_MC_OFFSET);
+			}
+			writel_relaxed(mcr_new, port->membase + UART_MC_OFFSET);
+		}
+	}
+}
+
+static void serial_ambarella_break_ctl(struct uart_port *port, int break_state)
+{
+	u32 lcr = readl_relaxed(port->membase + UART_LC_OFFSET);
+	unsigned long flags;
+
+	spin_lock_irqsave(&port->lock, flags);
+	if (break_state != 0)
+		writel_relaxed(lcr | UART_LC_BRK, port->membase + UART_LC_OFFSET);
+	else
+		writel_relaxed(lcr & ~UART_LC_BRK, port->membase + UART_LC_OFFSET);
+	spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static void serial_ambarella_dma_channel_free(struct ambarella_uart_port *amb_port,
+		bool dma_to_memory)
+{
+	struct dma_chan *dma_chan;
+
+	if (dma_to_memory) {
+		kfree(amb_port->rx_dma_buf_virt);
+
+		dma_chan = amb_port->rx_dma_chan;
+		amb_port->rx_dma_chan = NULL;
+		amb_port->rx_dma_buf_phys = 0;
+		amb_port->rx_dma_buf_virt = NULL;
+	} else {
+		dma_unmap_single(amb_port->port.dev, amb_port->tx_dma_buf_phys,
+			UART_XMIT_SIZE, DMA_TO_DEVICE);
+		dma_chan = amb_port->tx_dma_chan;
+		amb_port->tx_dma_chan = NULL;
+		amb_port->tx_dma_buf_phys = 0;
+		amb_port->tx_dma_buf_virt = NULL;
+	}
+	dma_release_channel(dma_chan);
+}
+
+static int serial_ambarella_dma_channel_allocate(struct ambarella_uart_port *amb_port,
+			bool dma_to_memory)
+{
+	struct dma_chan *dma_chan;
+	struct dma_slave_config dma_sconfig;
+	dma_addr_t dma_phys;
+	unsigned char *dma_buf;
+	int ret;
+
+	dma_chan = dma_request_slave_channel(amb_port->port.dev,
+		dma_to_memory ? "rx" : "tx");
+	if (!dma_chan) {
+		ret = PTR_ERR(dma_chan);
+		if (ret != -EPROBE_DEFER)
+			dev_err(amb_port->port.dev,
+				"Dma channel is not available: %d\n", ret);
+		return ret;
+	}
+
+	if (dma_to_memory) {
+		/* use double buffer to handle rx */
+		dma_buf = kmalloc(AMBA_UART_RX_DMA_BUFFER_SIZE, GFP_KERNEL);
+		if (!dma_buf) {
+			dma_release_channel(dma_chan);
+			return -ENOMEM;
+		}
+		dma_phys = dma_map_single(dma_chan->device->dev,
+			dma_buf, AMBA_UART_RX_DMA_BUFFER_SIZE,
+			DMA_FROM_DEVICE);
+		if (dma_mapping_error(dma_chan->device->dev, dma_phys)) {
+			dev_err(dma_chan->device->dev,
+				"failed mapping rx dma buffer\n");
+			dma_release_channel(dma_chan);
+			return -ENOMEM;
+		}
+	} else {
+		dma_phys = dma_map_single(dma_chan->device->dev,
+			amb_port->port.state->xmit.buf, UART_XMIT_SIZE,
+			DMA_TO_DEVICE);
+		if (dma_mapping_error(dma_chan->device->dev, dma_phys)) {
+			dev_err(dma_chan->device->dev,
+				"failed mapping tx dma buffer\n");
+			dma_release_channel(dma_chan);
+			return -ENOMEM;
+		}
+		dma_buf = amb_port->port.state->xmit.buf;
+	}
+
+	if (dma_to_memory) {
+		dma_sconfig.src_addr = amb_port->port.mapbase + UART_DMAF_OFFSET;
+		dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+		dma_sconfig.src_maxburst = 8;
+		dma_sconfig.direction = DMA_DEV_TO_MEM;
+	} else {
+		dma_sconfig.dst_addr = amb_port->port.mapbase + UART_DMAF_OFFSET;
+		dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+		dma_sconfig.dst_maxburst = 16;
+		dma_sconfig.direction = DMA_MEM_TO_DEV;
+	}
+
+	ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
+	if (ret < 0) {
+		dev_err(amb_port->port.dev,
+			"Dma slave config failed, err = %d\n", ret);
+		goto scrub;
+	}
+
+	if (dma_to_memory) {
+		amb_port->rx_dma_chan = dma_chan;
+		amb_port->rx_dma_buf_virt = dma_buf;
+		amb_port->rx_dma_buf_phys = dma_phys;
+	} else {
+		amb_port->tx_dma_chan = dma_chan;
+		amb_port->tx_dma_buf_virt = dma_buf;
+		amb_port->tx_dma_buf_phys = dma_phys;
+	}
+	return 0;
+
+scrub:
+	serial_ambarella_dma_channel_free(amb_port, dma_to_memory);
+	return ret;
+}
+
+static int serial_ambarella_startup(struct uart_port *port)
+{
+	int rval = 0;
+	struct ambarella_uart_port *amb_port;
+
+	amb_port = (struct ambarella_uart_port *)(port->private_data);
+
+	if (amb_port->txdma_used) {
+		rval = serial_ambarella_dma_channel_allocate(amb_port, false);
+		if (rval < 0) {
+			dev_err(amb_port->port.dev, "Tx Dma allocation failed, err = %d\n", rval);
+			return -EBUSY;
+		}
+	}
+
+	if (amb_port->rxdma_used) {
+		rval = serial_ambarella_dma_channel_allocate(amb_port, true);
+		if (rval < 0) {
+			dev_err(amb_port->port.dev, "Rx Dma allocation failed, err = %d\n", rval);
+			return -EBUSY;
+		}
+
+		rval = serial_ambarella_start_rx_dma(amb_port);
+		if (rval < 0) {
+			dev_err(amb_port->port.dev, "Not able to start Rx DMA\n");
+			return rval;
+		}
+		amb_port->rx_in_progress = true;
+	}
+
+	serial_ambarella_hw_setup(port);
+
+	return rval;
+}
+
+static void serial_ambarella_hw_deinit(struct ambarella_uart_port *amb_port)
+{
+	struct uart_port *port = &amb_port->port;
+
+	/* Disable interrupts */
+	writel_relaxed(0, port->membase + UART_IE_OFFSET);
+	/* Disable DMA */
+	writel_relaxed(0, port->membase + UART_DMAE_OFFSET);
+	/* Reset the Rx and Tx FIFOs */
+	writel_relaxed(UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR,
+			port->membase + UART_SRR_OFFSET);
+}
+
+static void serial_ambarella_shutdown(struct uart_port *port)
+{
+	struct ambarella_uart_port *amb_port;
+	u32 lcr;
+	unsigned long flags;
+
+	amb_port = (struct ambarella_uart_port *)(port->private_data);
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	if (amb_port->txdma_used || amb_port->rxdma_used) {
+		serial_ambarella_hw_deinit(amb_port);
+		spin_unlock_irqrestore(&port->lock, flags);
+
+		if (amb_port->txdma_used) {
+			dmaengine_terminate_all(amb_port->tx_dma_chan);
+			serial_ambarella_dma_channel_free(amb_port, false);
+			amb_port->tx_in_progress = false;
+		}
+		if (amb_port->rxdma_used) {
+			dmaengine_terminate_all(amb_port->rx_dma_chan);
+			serial_ambarella_dma_channel_free(amb_port, true);
+			amb_port->rx_in_progress = false;
+		}
+
+		spin_lock_irqsave(&port->lock, flags);
+	}
+
+	lcr = readl_relaxed(port->membase + UART_LC_OFFSET);
+	writel_relaxed(lcr & ~UART_LC_BRK, port->membase + UART_LC_OFFSET);
+	spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static void serial_ambarella_set_termios(struct uart_port *port,
+	struct ktermios *termios, const struct ktermios *old)
+{
+	struct ambarella_uart_port *amb_port;
+	unsigned int baud, quot;
+	u32 lc = 0x0;
+
+	amb_port = (struct ambarella_uart_port *)(port->private_data);
+	amb_port->c_cflag = termios->c_cflag;
+
+	port->uartclk = clk_get_rate(amb_port->uart_pll);
+	switch (termios->c_cflag & CSIZE) {
+	case CS5:
+		lc |= UART_LC_CLS_5_BITS;
+		break;
+	case CS6:
+		lc |= UART_LC_CLS_6_BITS;
+		break;
+	case CS7:
+		lc |= UART_LC_CLS_7_BITS;
+		break;
+	case CS8:
+	default:
+		lc |= UART_LC_CLS_8_BITS;
+		break;
+	}
+
+	if (termios->c_cflag & CSTOPB)
+		lc |= UART_LC_STOP_2BIT;
+	else
+		lc |= UART_LC_STOP_1BIT;
+
+	if (termios->c_cflag & PARENB) {
+		if (termios->c_cflag & PARODD)
+			lc |= (UART_LC_PEN | UART_LC_ODD_PARITY);
+		else
+			lc |= (UART_LC_PEN | UART_LC_EVEN_PARITY);
+	}
+
+	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
+	quot = uart_get_divisor(port, baud);
+
+	disable_irq(port->irq);
+	uart_update_timeout(port, termios->c_cflag, baud);
+
+	port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
+	if (termios->c_iflag & INPCK)
+		port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
+	if (termios->c_iflag & (BRKINT | PARMRK))
+		port->read_status_mask |= UART_LSR_BI;
+
+	port->ignore_status_mask = 0;
+	if (termios->c_iflag & IGNPAR)
+		port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
+	if (termios->c_iflag & IGNBRK) {
+		port->ignore_status_mask |= UART_LSR_BI;
+		if (termios->c_iflag & IGNPAR)
+			port->ignore_status_mask |= UART_LSR_OE;
+	}
+	if ((termios->c_cflag & CREAD) == 0)
+		port->ignore_status_mask |= UART_LSR_DR;
+
+	if ((termios->c_cflag & CRTSCTS) == 0) {
+		amb_port->mcr &= ~UART_MC_AFCE;
+		port->status &= ~UPSTAT_AUTOCTS;
+	} else {
+		amb_port->mcr |= UART_MC_AFCE;
+		port->status |= UPSTAT_AUTOCTS;
+	}
+
+	writel_relaxed(UART_LC_DLAB, port->membase + UART_LC_OFFSET);
+	writel_relaxed(quot & 0xff, port->membase + UART_DLL_OFFSET);
+	writel_relaxed((quot >> 8) & 0xff, port->membase + UART_DLH_OFFSET);
+	writel_relaxed(lc, port->membase + UART_LC_OFFSET);
+	if (UART_ENABLE_MS(port, termios->c_cflag))
+		__serial_ambarella_enable_ms(port);
+	else
+		__serial_ambarella_disable_ms(port);
+	serial_ambarella_set_mctrl(port, port->mctrl);
+
+	enable_irq(port->irq);
+}
+
+static void serial_ambarella_pm(struct uart_port *port,
+	unsigned int state, unsigned int oldstate)
+{
+}
+
+static void serial_ambarella_release_port(struct uart_port *port)
+{
+}
+
+static int serial_ambarella_request_port(struct uart_port *port)
+{
+	return 0;
+}
+
+static void serial_ambarella_config_port(struct uart_port *port, int flags)
+{
+}
+
+static int serial_ambarella_verify_port(struct uart_port *port,
+					struct serial_struct *ser)
+{
+	int rval = 0;
+
+	if (ser->type != PORT_UNKNOWN && ser->type != PORT_UART00)
+		rval = -EINVAL;
+	if (port->irq != ser->irq)
+		rval = -EINVAL;
+	if (ser->io_type != SERIAL_IO_MEM)
+		rval = -EINVAL;
+
+	return rval;
+}
+
+static const char *serial_ambarella_type(struct uart_port *port)
+{
+	return "ambuart";
+}
+
+#ifdef CONFIG_CONSOLE_POLL
+static void serial_ambarella_poll_put_char(struct uart_port *port,
+	unsigned char chr)
+{
+	struct ambarella_uart_port *amb_port;
+
+	amb_port = (struct ambarella_uart_port *)(port->private_data);
+	if (!port->suspended) {
+		wait_for_tx(port);
+		writel_relaxed(chr, port->membase + UART_TH_OFFSET);
+	}
+}
+
+static int serial_ambarella_poll_get_char(struct uart_port *port)
+{
+	struct ambarella_uart_port *amb_port;
+
+	amb_port = (struct ambarella_uart_port *)(port->private_data);
+	if (!port->suspended) {
+		wait_for_rx(port);
+		return readl_relaxed(port->membase + UART_RB_OFFSET);
+	}
+	return 0;
+}
+#endif
+
+static const struct uart_ops serial_ambarella_pops = {
+	.tx_empty	= serial_ambarella_tx_empty,
+	.set_mctrl	= serial_ambarella_set_mctrl,
+	.get_mctrl	= serial_ambarella_get_mctrl,
+	.stop_tx	= serial_ambarella_stop_tx,
+	.start_tx	= serial_ambarella_start_tx,
+	.stop_rx	= serial_ambarella_stop_rx,
+	.enable_ms	= serial_ambarella_enable_ms,
+	.break_ctl	= serial_ambarella_break_ctl,
+	.startup	= serial_ambarella_startup,
+	.shutdown	= serial_ambarella_shutdown,
+	.set_termios	= serial_ambarella_set_termios,
+	.pm		= serial_ambarella_pm,
+	.type		= serial_ambarella_type,
+	.release_port	= serial_ambarella_release_port,
+	.request_port	= serial_ambarella_request_port,
+	.config_port	= serial_ambarella_config_port,
+	.verify_port	= serial_ambarella_verify_port,
+#ifdef CONFIG_CONSOLE_POLL
+	.poll_put_char	= serial_ambarella_poll_put_char,
+	.poll_get_char	= serial_ambarella_poll_get_char,
+#endif
+};
+
+/* ==========================================================================*/
+#if defined(CONFIG_SERIAL_AMBARELLA_CONSOLE)
+
+static struct uart_driver serial_ambarella_reg;
+static void ambarella_uart_of_enumerate(void);
+
+static void serial_ambarella_console_putchar(struct uart_port *port, unsigned char ch)
+{
+	wait_for_tx(port);
+	writel_relaxed(ch, port->membase + UART_TH_OFFSET);
+}
+
+static void serial_ambarella_console_write(struct console *co,
+	const char *s, unsigned int count)
+{
+	struct uart_port *port;
+	int locked = 1;
+	unsigned long flags;
+
+	port = &ambarella_port[co->index].port;
+
+	if (!port->suspended) {
+		local_irq_save(flags);
+		if (port->sysrq) {
+			locked = 0;
+		} else if (oops_in_progress) {
+			locked = spin_trylock(&port->lock);
+		} else {
+			spin_lock(&port->lock);
+			locked = 1;
+		}
+
+		uart_console_write(port, s, count,
+			serial_ambarella_console_putchar);
+		wait_for_tx(port);
+
+		if (locked)
+			spin_unlock(&port->lock);
+		local_irq_restore(flags);
+	}
+}
+
+static int __init serial_ambarella_console_setup(struct console *co,
+	char *options)
+{
+	struct uart_port *port;
+	int baud = 115200, bits = 8, parity = 'n', flow = 'n';
+
+	if (co->index < 0 || co->index >= serial_ambarella_reg.nr)
+		co->index = 0;
+
+	port = &ambarella_port[co->index].port;
+	if (!port->membase) {
+		pr_err("No device available for serial console\n");
+		return -ENODEV;
+	}
+
+	port->ops = &serial_ambarella_pops;
+	port->private_data = &ambarella_port[co->index];
+	port->line = co->index;
+
+	serial_ambarella_hw_setup(port);
+
+	if (options)
+		uart_parse_options(options, &baud, &parity, &bits, &flow);
+
+	return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+static struct console serial_ambarella_console = {
+	.name		= "ttyS",
+	.write		= serial_ambarella_console_write,
+	.device		= uart_console_device,
+	.setup		= serial_ambarella_console_setup,
+	.flags		= CON_PRINTBUFFER | CON_ANYTIME,
+	.index		= -1,
+	.data		= &serial_ambarella_reg,
+};
+
+#ifdef CONFIG_PM
+/* when no_console_suspend is specified in cmdline, Linux thought the console
+ * would never suspend. But actually we may put system into STR and power off
+ * the SoC, so the console must be initialized when system exit STR.
+ *
+ * NOTE: We MUST ensure that no information will be output via UART until
+ * syscore_resume() is completed, otherwise the UART may be in deadloop.
+ */
+static void serial_ambarella_console_resume(void)
+{
+	struct console *co = &serial_ambarella_console;
+	struct ambarella_uart_port *amb_port;
+	struct uart_port *port;
+	struct ktermios termios;
+
+	if (console_suspend_enabled)
+		return;
+
+	if (co->index < 0 || co->index >= serial_ambarella_reg.nr)
+		return;
+
+	amb_port = &ambarella_port[co->index];
+
+	port = &ambarella_port[co->index].port;
+	if (!port->membase)
+		return;
+
+	clk_set_parent(amb_port->uart_pll, amb_port->parent_pll);
+	clk_set_rate(amb_port->uart_pll, amb_port->clk_rate);
+
+	clear_bit(AMBA_UART_RESET_FLAG, &amb_port->flags);
+	serial_ambarella_hw_setup(port);
+
+	memset(&termios, 0, sizeof(struct ktermios));
+	termios.c_cflag = amb_port->c_cflag;
+	port->ops->set_termios(port, &termios, NULL);
+}
+
+static int serial_ambarella_console_suspend(void)
+{
+	struct console *co = &serial_ambarella_console;
+	struct ambarella_uart_port *amb_port;
+
+	if (console_suspend_enabled)
+		return 0;
+
+	if (co->index < 0 || co->index >= serial_ambarella_reg.nr)
+		return 0;
+
+	amb_port = &ambarella_port[co->index];
+
+	clk_set_parent(amb_port->uart_pll, NULL);
+
+	return 0;
+}
+
+static struct syscore_ops ambarella_console_syscore_ops = {
+	.resume	 = serial_ambarella_console_resume,
+	.suspend = serial_ambarella_console_suspend,
+};
+#endif
+
+static int __init serial_ambarella_console_init(void)
+{
+	struct device_node *np;
+	const char *name;
+	int id;
+
+	ambarella_uart_of_enumerate();
+
+	name = of_get_property(of_chosen, "linux,stdout-path", NULL);
+	if (name == NULL)
+		return -ENODEV;
+
+	np = of_find_node_by_path(name);
+	if (!np)
+		return -ENODEV;
+
+	id = of_alias_get_id(np, "serial");
+	if (id < 0 || id >= serial_ambarella_reg.nr)
+		return -ENODEV;
+
+	ambarella_port[id].port.membase = of_iomap(np, 0);
+
+	ambarella_port[id].uart_pll = of_clk_get(np, 0);
+	if (IS_ERR(ambarella_port[id].uart_pll)) {
+		pr_err("No clock available for serial console\n");
+		return -ENODEV;
+	}
+	ambarella_port[id].parent_pll = clk_get_parent(ambarella_port[id].uart_pll);
+
+	register_console(&serial_ambarella_console);
+
+#ifdef CONFIG_PM
+	register_syscore_ops(&ambarella_console_syscore_ops);
+#endif
+
+	return 0;
+}
+
+console_initcall(serial_ambarella_console_init);
+
+static void serial_ambarella_console_early_write(struct console *con, const char *s,
+		unsigned int count)
+{
+	struct earlycon_device *dev = con->data;
+
+	uart_console_write(&dev->port, s, count, serial_ambarella_console_putchar);
+}
+
+static int __init serial_ambarella_console_early_setup(struct earlycon_device *dev,
+		const char *opt)
+{
+	if (!dev->port.membase)
+		return -ENODEV;
+
+	dev->con->write = serial_ambarella_console_early_write;
+
+	return 0;
+}
+OF_EARLYCON_DECLARE(ambarella_uart, "ambarella,uart", serial_ambarella_console_early_setup);
+
+#define AMBARELLA_CONSOLE	(&serial_ambarella_console)
+#else
+#define AMBARELLA_CONSOLE	NULL
+#endif
+
+/* ==========================================================================*/
+static struct uart_driver serial_ambarella_reg = {
+	.owner		= THIS_MODULE,
+	.driver_name	= "ambarella-uart",
+	.dev_name	= "ttyS",
+	.major		= TTY_MAJOR,
+	.minor		= 64,
+	.nr		= 0,
+	.cons		= AMBARELLA_CONSOLE,
+};
+
+static int serial_ambarella_probe(struct platform_device *pdev)
+{
+	struct ambarella_uart_port *amb_port;
+	struct resource *mem;
+	struct pinctrl *pinctrl;
+	int irq, id, rval = 0;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!mem) {
+		dev_err(&pdev->dev, "no mem resource!\n");
+		return -ENODEV;
+	}
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(&pdev->dev, "no irq resource!\n");
+		return -ENODEV;
+	}
+
+	id = of_alias_get_id(pdev->dev.of_node, "serial");
+	if (id < 0 || id >= serial_ambarella_reg.nr) {
+		dev_err(&pdev->dev, "Invalid uart ID %d!\n", id);
+		return -ENXIO;
+	}
+
+	pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+	if (IS_ERR(pinctrl)) {
+		dev_err(&pdev->dev, "Failed to request pinctrl\n");
+		return PTR_ERR(pinctrl);
+	}
+
+	amb_port = &ambarella_port[id];
+
+	amb_port->uart_pll = of_clk_get(pdev->dev.of_node, 0);
+	if (IS_ERR(amb_port->uart_pll)) {
+		dev_err(&pdev->dev, "Get uart clk failed!\n");
+		return PTR_ERR(amb_port->uart_pll);
+	}
+	amb_port->parent_pll = clk_get_parent(amb_port->uart_pll);
+
+	amb_port->mcr = DEFAULT_AMBARELLA_UART_MCR;
+	/* check if using modem status register,  available for non-uart0. */
+	if (of_find_property(pdev->dev.of_node, "amb,msr-used", NULL))
+		amb_port->msr_used = 1;
+	else
+		amb_port->msr_used = 0;
+	/* check if workaround for tx fifo is needed */
+	if (of_find_property(pdev->dev.of_node, "amb,tx-fifo-fix", NULL))
+		amb_port->tx_fifo_fix = 1;
+	else
+		amb_port->tx_fifo_fix = 0;
+	/* check if registers like FIFO status register are NOT provided. */
+	if (of_find_property(pdev->dev.of_node, "amb,less-reg", NULL))
+		amb_port->less_reg = 1;
+	else
+		amb_port->less_reg = 0;
+	/* check if using tx dma */
+	if (of_find_property(pdev->dev.of_node, "amb,txdma-used", NULL)) {
+		amb_port->txdma_used = 1;
+		dev_info(&pdev->dev, "Serial[%d] use txdma\n", id);
+	} else
+		amb_port->txdma_used = 0;
+	/* check if using rx dma */
+	if (of_find_property(pdev->dev.of_node, "amb,rxdma-used", NULL)) {
+		amb_port->rxdma_used = 1;
+		dev_info(&pdev->dev, "Serial[%d] use rxdma\n", id);
+	} else {
+		amb_port->rxdma_used = 0;
+	}
+	/* check if ignore frame error */
+	if (of_find_property(pdev->dev.of_node, "amb,ignore-fe", NULL)) {
+		amb_port->ignore_fe = 1;
+		dev_info(&pdev->dev, "Serial[%d] ignores FE\n", id);
+	} else {
+		amb_port->ignore_fe = 0;
+	}
+
+	amb_port->port.dev = &pdev->dev;
+	amb_port->port.type = PORT_UART00;
+	amb_port->port.iotype = UPIO_MEM;
+	amb_port->port.fifosize = UART_FIFO_SIZE;
+	amb_port->port.uartclk = clk_get_rate(amb_port->uart_pll);
+	amb_port->port.ops = &serial_ambarella_pops;
+	amb_port->port.private_data = amb_port;
+	amb_port->port.irq = irq;
+	amb_port->port.line = id;
+	amb_port->port.mapbase = mem->start;
+	amb_port->port.membase =
+		devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
+	if (!amb_port->port.membase) {
+		dev_err(&pdev->dev, "can't ioremap UART\n");
+		return -ENOMEM;
+	}
+
+	rval = uart_add_one_port(&serial_ambarella_reg, &amb_port->port);
+	if (rval < 0)
+		dev_err(&pdev->dev, "failed to add port: %d, %d!\n", id, rval);
+
+	rval = request_irq(irq, serial_ambarella_irq, IRQF_TRIGGER_HIGH,
+			dev_name(amb_port->port.dev), &amb_port->port);
+
+	platform_set_drvdata(pdev, amb_port);
+
+	return rval;
+}
+
+static int serial_ambarella_remove(struct platform_device *pdev)
+{
+	struct ambarella_uart_port *amb_port;
+	int rval = 0;
+
+	amb_port = platform_get_drvdata(pdev);
+	rval = uart_remove_one_port(&serial_ambarella_reg, &amb_port->port);
+	if (rval < 0)
+		dev_err(&pdev->dev, "uart_remove_one_port fail %d!\n",	rval);
+	free_irq(amb_port->port.irq, &amb_port->port);
+
+	dev_notice(&pdev->dev,
+		"Remove Ambarella Media Processor UART.\n");
+
+	return rval;
+}
+
+#ifdef CONFIG_PM
+static int serial_ambarella_suspend(struct platform_device *pdev,
+	pm_message_t state)
+{
+	struct ambarella_uart_port *amb_port;
+	int rval = 0;
+
+	amb_port = platform_get_drvdata(pdev);
+	rval = uart_suspend_port(&serial_ambarella_reg, &amb_port->port);
+
+	amb_port->clk_rate = clk_get_rate(amb_port->uart_pll);
+	clk_set_parent(amb_port->uart_pll, NULL);
+
+	dev_dbg(&pdev->dev, "%s exit with %d @ %d\n",
+		__func__, rval, state.event);
+
+	return rval;
+}
+
+static int serial_ambarella_resume(struct platform_device *pdev)
+{
+	struct ambarella_uart_port *amb_port;
+	int rval = 0;
+
+	amb_port = platform_get_drvdata(pdev);
+
+	clk_set_parent(amb_port->uart_pll, amb_port->parent_pll);
+	clk_set_rate(amb_port->uart_pll, amb_port->clk_rate);
+
+	clear_bit(AMBA_UART_RESET_FLAG, &amb_port->flags);
+	serial_ambarella_hw_setup(&amb_port->port);
+
+	rval = uart_resume_port(&serial_ambarella_reg, &amb_port->port);
+
+	dev_dbg(&pdev->dev, "%s exit with %d\n", __func__, rval);
+
+	return rval;
+}
+#endif
+
+static const struct of_device_id ambarella_serial_of_match[] = {
+	{ .compatible = "ambarella,uart" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, ambarella_serial_of_match);
+
+static void ambarella_uart_of_enumerate(void)
+{
+	struct device_node *np;
+	int nr = 0;
+
+	if (serial_ambarella_reg.nr <= 0) {
+		for_each_matching_node(np, ambarella_serial_of_match) {
+			nr++;
+		}
+
+		if (nr > AMBA_UART_MAX_NUM)
+			nr = AMBA_UART_MAX_NUM;
+
+		serial_ambarella_reg.nr = nr;
+	}
+}
+
+
+static struct platform_driver serial_ambarella_driver = {
+	.probe		= serial_ambarella_probe,
+	.remove		= serial_ambarella_remove,
+#ifdef CONFIG_PM
+	.suspend	= serial_ambarella_suspend,
+	.resume		= serial_ambarella_resume,
+#endif
+	.driver		= {
+		.name	= "ambarella-uart",
+		.of_match_table = ambarella_serial_of_match,
+	},
+};
+
+static int __init serial_ambarella_init(void)
+{
+	int rval;
+
+	ambarella_uart_of_enumerate();
+
+	rval = uart_register_driver(&serial_ambarella_reg);
+	if (rval < 0)
+		return rval;
+
+	rval = platform_driver_register(&serial_ambarella_driver);
+	if (rval < 0)
+		uart_unregister_driver(&serial_ambarella_reg);
+
+	return rval;
+}
+
+static void __exit serial_ambarella_exit(void)
+{
+	platform_driver_unregister(&serial_ambarella_driver);
+	uart_unregister_driver(&serial_ambarella_reg);
+}
+
+module_init(serial_ambarella_init);
+module_exit(serial_ambarella_exit);
+
+MODULE_AUTHOR("Anthony Ginger");
+MODULE_DESCRIPTION("Ambarella Media Processor UART driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:ambarella-uart");
diff --git a/drivers/tty/serial/ambarella_uart.h b/drivers/tty/serial/ambarella_uart.h
new file mode 100644
index 000000000000..991fee680e16
--- /dev/null
+++ b/drivers/tty/serial/ambarella_uart.h
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023, Ambarella, Inc.
+ */
+
+#ifndef __AMBARELLA_UART_H__
+#define __AMBARELLA_UART_H__
+
+/* ==========================================================================*/
+#define UART_RB_OFFSET			0x00
+#define UART_TH_OFFSET			0x00
+#define UART_DLL_OFFSET			0x00
+#define UART_IE_OFFSET			0x04
+#define UART_DLH_OFFSET			0x04
+#define UART_II_OFFSET			0x08
+#define UART_FC_OFFSET			0x08
+#define UART_LC_OFFSET			0x0c
+#define UART_MC_OFFSET			0x10
+#define UART_LS_OFFSET			0x14
+#define UART_MS_OFFSET			0x18
+#define UART_SC_OFFSET			0x1c	/* Byte */
+#define UART_DMAE_OFFSET		0x28
+#define UART_DMAF_OFFSET		0x40	/* DMA fifo */
+#define UART_US_OFFSET			0x7c
+#define UART_TFL_OFFSET			0x80
+#define UART_RFL_OFFSET			0x84
+#define UART_SRR_OFFSET			0x88
+#define UART_RTR_OFFSET			0xac
+#define UART_TTR_OFFSET			0xb0
+
+/* UART[x]_IE_REG */
+#define UART_IE_PTIME			0x80
+#define UART_IE_ETOI			0x20
+#define UART_IE_EBDI			0x10
+#define UART_IE_EDSSI			0x08
+#define UART_IE_ELSI			0x04
+#define UART_IE_ETBEI			0x02
+#define UART_IE_ERBFI			0x01
+
+/* UART[x]_II_REG */
+#define UART_II_MODEM_STATUS_CHANGED	0x00
+#define UART_II_NO_INT_PENDING		0x01
+#define UART_II_THR_EMPTY		0x02
+#define UART_II_RCV_DATA_AVAIL		0x04
+#define UART_II_RCV_STATUS		0x06
+#define UART_II_CHAR_TIMEOUT		0x0c
+
+/* UART[x]_FC_REG */
+#define UART_FC_RX_ONECHAR		0x00
+#define UART_FC_RX_QUARTER_FULL		0x40
+#define UART_FC_RX_HALF_FULL		0x80
+#define UART_FC_RX_2_TO_FULL		0xc0
+#define UART_FC_TX_EMPTY		0x00
+#define UART_FC_TX_2_IN_FIFO		0x10
+#define UART_FC_TX_QUATER_IN_FIFO	0x20
+#define UART_FC_TX_HALF_IN_FIFO		0x30
+#define UART_FC_DMA_SELECT		0x08
+#define UART_FC_XMITR			0x04
+#define UART_FC_RCVRR			0x02
+#define UART_FC_FIFOE			0x01
+
+/* UART[x]_LC_REG */
+#define UART_LC_DLAB			0x80
+#define UART_LC_BRK			0x40
+#define UART_LC_EVEN_PARITY		0x10
+#define UART_LC_ODD_PARITY		0x00
+#define UART_LC_PEN			0x08
+#define UART_LC_STOP_2BIT		0x04
+#define UART_LC_STOP_1BIT		0x00
+#define UART_LC_CLS_8_BITS		0x03
+#define UART_LC_CLS_7_BITS		0x02
+#define UART_LC_CLS_6_BITS		0x01
+#define UART_LC_CLS_5_BITS		0x00
+/*	quick defs */
+#define	UART_LC_8N1			0x03
+#define	UART_LC_7E1			0x0a
+
+/* UART[x]_MC_REG */
+#define UART_MC_SIRE			0x40
+#define UART_MC_AFCE			0x20
+#define UART_MC_LB			0x10
+#define UART_MC_OUT2			0x08
+#define UART_MC_OUT1			0x04
+#define UART_MC_RTS			0x02
+#define UART_MC_DTR			0x01
+
+/* UART[x]_LS_REG */
+#define UART_LS_FERR			0x80
+#define UART_LS_TEMT			0x40
+#define UART_LS_THRE			0x20
+#define UART_LS_BI			0x10
+#define UART_LS_FE			0x08
+#define UART_LS_PE			0x04
+#define UART_LS_OE			0x02
+#define UART_LS_DR			0x01
+
+/* UART[x]_MS_REG */
+#define UART_MS_DCD			0x80
+#define UART_MS_RI			0x40
+#define UART_MS_DSR			0x20
+#define UART_MS_CTS			0x10
+#define UART_MS_DDCD			0x08
+#define UART_MS_TERI			0x04
+#define UART_MS_DDSR			0x02
+#define UART_MS_DCTS			0x01
+
+/* UART[x]_US_REG */
+#define UART_US_RFF			0x10
+#define UART_US_RFNE			0x08
+#define UART_US_TFE			0x04
+#define UART_US_TFNF			0x02
+#define UART_US_BUSY			0x01
+
+/* ==========================================================================*/
+#define UART_FIFO_SIZE			(16)
+
+#define DEFAULT_AMBARELLA_UART_MCR	(0)
+#define DEFAULT_AMBARELLA_UART_IER	(UART_IE_ELSI | UART_IE_ERBFI | UART_IE_ETOI)
+
+#endif /* __AMBARELLA_UART_H__ */
-- 
2.34.1

Re: [PATCH 10/15] serial: ambarella: add support for Ambarella uart_port

[Greg Kroah-Hartman]

On Mon, Jan 23, 2023 at 03:32:25PM +0800, Li Chen wrote:
> This driver add support for Ambarella's uart, which
> can be used for console and etc.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: Ie68af7ad2187e21853e58d52cd97fd7145303730

Please always use scripts/checkpatch.pl so you don't get grumpy
maintainers asking you why you didn't run scripts/checkpatch.pl :(

Re: [PATCH 10/15] serial: ambarella: add support for Ambarella uart_port

[Greg Kroah-Hartman]

On Mon, Jan 23, 2023 at 03:32:25PM +0800, Li Chen wrote:
> This driver add support for Ambarella's uart, which
> can be used for console and etc.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: Ie68af7ad2187e21853e58d52cd97fd7145303730

Please always use scripts/checkpatch.pl so you don't get grumpy
maintainers asking you why you didn't run scripts/checkpatch.pl :(


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 10/15] serial: ambarella: add support for Ambarella uart_port

[Greg Kroah-Hartman]

On Mon, Jan 23, 2023 at 03:32:25PM +0800, Li Chen wrote:
> This driver add support for Ambarella's uart, which
> can be used for console and etc.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: Ie68af7ad2187e21853e58d52cd97fd7145303730

Please always use scripts/checkpatch.pl so you don't get grumpy
maintainers asking you why you didn't run scripts/checkpatch.pl :(

Re: [PATCH 10/15] serial: ambarella: add support for Ambarella uart_port

[Greg Kroah-Hartman]

On Mon, Jan 23, 2023 at 03:32:25PM +0800, Li Chen wrote:
> This driver add support for Ambarella's uart, which
> can be used for console and etc.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: Ie68af7ad2187e21853e58d52cd97fd7145303730
> ---
>  MAINTAINERS                         |    1 +
>  drivers/tty/serial/Kconfig          |   16 +
>  drivers/tty/serial/Makefile         |    1 +
>  drivers/tty/serial/ambarella_uart.c | 1581 +++++++++++++++++++++++++++
>  drivers/tty/serial/ambarella_uart.h |  120 ++

Why do you need a .h file for a single .c file?  They should all be in
one file please.

Also, no change-id, you know this...

thanks,

greg k-h

Re: [PATCH 10/15] serial: ambarella: add support for Ambarella uart_port

[Greg Kroah-Hartman]

On Mon, Jan 23, 2023 at 03:32:25PM +0800, Li Chen wrote:
> This driver add support for Ambarella's uart, which
> can be used for console and etc.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: Ie68af7ad2187e21853e58d52cd97fd7145303730
> ---
>  MAINTAINERS                         |    1 +
>  drivers/tty/serial/Kconfig          |   16 +
>  drivers/tty/serial/Makefile         |    1 +
>  drivers/tty/serial/ambarella_uart.c | 1581 +++++++++++++++++++++++++++
>  drivers/tty/serial/ambarella_uart.h |  120 ++

Why do you need a .h file for a single .c file?  They should all be in
one file please.

Also, no change-id, you know this...

thanks,

greg k-h

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Re: [PATCH 10/15] serial: ambarella: add support for Ambarella uart_port

[Greg Kroah-Hartman]

On Mon, Jan 23, 2023 at 03:32:25PM +0800, Li Chen wrote:
> This driver add support for Ambarella's uart, which
> can be used for console and etc.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: Ie68af7ad2187e21853e58d52cd97fd7145303730
> ---
>  MAINTAINERS                         |    1 +
>  drivers/tty/serial/Kconfig          |   16 +
>  drivers/tty/serial/Makefile         |    1 +
>  drivers/tty/serial/ambarella_uart.c | 1581 +++++++++++++++++++++++++++
>  drivers/tty/serial/ambarella_uart.h |  120 ++

Why do you need a .h file for a single .c file?  They should all be in
one file please.

Also, no change-id, you know this...

thanks,

greg k-h

Re: [PATCH 10/15] serial: ambarella: add support for Ambarella uart_port

[Li Chen]

On Mon, 23 Jan 2023 17:51:25 +0800,

Hi Greg,

Sorry for my late reply.

Greg Kroah-Hartman wrote:
> 
> On Mon, Jan 23, 2023 at 03:32:25PM +0800, Li Chen wrote:
> > This driver add support for Ambarella's uart, which
> > can be used for console and etc.
> > 
> > Signed-off-by: Li Chen <lchen@ambarella.com>
> > Change-Id: Ie68af7ad2187e21853e58d52cd97fd7145303730
> > ---
> >  MAINTAINERS                         |    1 +
> >  drivers/tty/serial/Kconfig          |   16 +
> >  drivers/tty/serial/Makefile         |    1 +
> >  drivers/tty/serial/ambarella_uart.c | 1581 +++++++++++++++++++++++++++
> >  drivers/tty/serial/ambarella_uart.h |  120 ++
> 
> Why do you need a .h file for a single .c file?  They should all be in
> one file please.

Ok, I will combine them into single source file.

> Also, no change-id, you know this...
> 
> thanks,
> 
> greg k-h

Regards,
Li

Re: [PATCH 10/15] serial: ambarella: add support for Ambarella uart_port

[Li Chen]

On Mon, 23 Jan 2023 17:51:25 +0800,

Hi Greg,

Sorry for my late reply.

Greg Kroah-Hartman wrote:
> 
> On Mon, Jan 23, 2023 at 03:32:25PM +0800, Li Chen wrote:
> > This driver add support for Ambarella's uart, which
> > can be used for console and etc.
> > 
> > Signed-off-by: Li Chen <lchen@ambarella.com>
> > Change-Id: Ie68af7ad2187e21853e58d52cd97fd7145303730
> > ---
> >  MAINTAINERS                         |    1 +
> >  drivers/tty/serial/Kconfig          |   16 +
> >  drivers/tty/serial/Makefile         |    1 +
> >  drivers/tty/serial/ambarella_uart.c | 1581 +++++++++++++++++++++++++++
> >  drivers/tty/serial/ambarella_uart.h |  120 ++
> 
> Why do you need a .h file for a single .c file?  They should all be in
> one file please.

Ok, I will combine them into single source file.

> Also, no change-id, you know this...
> 
> thanks,
> 
> greg k-h

Regards,
Li

Re: [PATCH 10/15] serial: ambarella: add support for Ambarella uart_port

[Li Chen]

On Mon, 23 Jan 2023 17:51:25 +0800,

Hi Greg,

Sorry for my late reply.

Greg Kroah-Hartman wrote:
> 
> On Mon, Jan 23, 2023 at 03:32:25PM +0800, Li Chen wrote:
> > This driver add support for Ambarella's uart, which
> > can be used for console and etc.
> > 
> > Signed-off-by: Li Chen <lchen@ambarella.com>
> > Change-Id: Ie68af7ad2187e21853e58d52cd97fd7145303730
> > ---
> >  MAINTAINERS                         |    1 +
> >  drivers/tty/serial/Kconfig          |   16 +
> >  drivers/tty/serial/Makefile         |    1 +
> >  drivers/tty/serial/ambarella_uart.c | 1581 +++++++++++++++++++++++++++
> >  drivers/tty/serial/ambarella_uart.h |  120 ++
> 
> Why do you need a .h file for a single .c file?  They should all be in
> one file please.

Ok, I will combine them into single source file.

> Also, no change-id, you know this...
> 
> thanks,
> 
> greg k-h

Regards,
Li

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Re: [PATCH 03/15] dt-bindings: arm: ambarella: Add binding for Ambarella ARM platforms

[Krzysztof Kozlowski]

On 23/01/2023 08:32, Li Chen wrote:
> This introduces binding for Ambarella s6lm SoC.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: Id95d91218625a1f0b3413aac101c2ca8831f0385

Please run scripts/checkpatch.pl and fix reported warnings.

> ---
>  .../devicetree/bindings/arm/ambarella.yaml    | 22 +++++++++++++++++++
>  MAINTAINERS                                   |  6 +++++
>  2 files changed, 28 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/ambarella.yaml
> 
> diff --git a/Documentation/devicetree/bindings/arm/ambarella.yaml b/Documentation/devicetree/bindings/arm/ambarella.yaml
> new file mode 100644
> index 000000000000..2c8ff75b57b9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/ambarella.yaml
> @@ -0,0 +1,22 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/ambarella.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella SoC Device Tree Bindings

Drop "Device Tree Bindings"

> +
> +maintainers:
> +  - Li Chen <lchen@ambarella.com>
> +
> +properties:
> +  $nodename:
> +    const: "/"
> +  compatible:
> +    oneOf:
> +      - description: Ambarella SoC based platforms
> +        items:
> +          - enum:
> +              - ambarella,s6lm


Best regards,
Krzysztof

Re: [PATCH 03/15] dt-bindings: arm: ambarella: Add binding for Ambarella ARM platforms

[Krzysztof Kozlowski]

On 23/01/2023 08:32, Li Chen wrote:
> This introduces binding for Ambarella s6lm SoC.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: Id95d91218625a1f0b3413aac101c2ca8831f0385

Please run scripts/checkpatch.pl and fix reported warnings.

> ---
>  .../devicetree/bindings/arm/ambarella.yaml    | 22 +++++++++++++++++++
>  MAINTAINERS                                   |  6 +++++
>  2 files changed, 28 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/ambarella.yaml
> 
> diff --git a/Documentation/devicetree/bindings/arm/ambarella.yaml b/Documentation/devicetree/bindings/arm/ambarella.yaml
> new file mode 100644
> index 000000000000..2c8ff75b57b9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/ambarella.yaml
> @@ -0,0 +1,22 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/ambarella.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella SoC Device Tree Bindings

Drop "Device Tree Bindings"

> +
> +maintainers:
> +  - Li Chen <lchen@ambarella.com>
> +
> +properties:
> +  $nodename:
> +    const: "/"
> +  compatible:
> +    oneOf:
> +      - description: Ambarella SoC based platforms
> +        items:
> +          - enum:
> +              - ambarella,s6lm


Best regards,
Krzysztof


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Re: [PATCH 03/15] dt-bindings: arm: ambarella: Add binding for Ambarella ARM platforms

[Li Chen]

On Mon, 23 Jan 2023 16:03:27 +0800,
Krzysztof Kozlowski wrote:
> 
> On 23/01/2023 08:32, Li Chen wrote:
> > This introduces binding for Ambarella s6lm SoC.
> > 
> > Signed-off-by: Li Chen <lchen@ambarella.com>
> > Change-Id: Id95d91218625a1f0b3413aac101c2ca8831f0385
> 
> Please run scripts/checkpatch.pl and fix reported warnings.

Sorry for it, I do run checkpatch & sparse and fix issues, but forget to remove the
Change-id finally, will remove it in v2.

> > ---
> >  .../devicetree/bindings/arm/ambarella.yaml    | 22 +++++++++++++++++++
> >  MAINTAINERS                                   |  6 +++++
> >  2 files changed, 28 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/arm/ambarella.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/ambarella.yaml b/Documentation/devicetree/bindings/arm/ambarella.yaml
> > new file mode 100644
> > index 000000000000..2c8ff75b57b9
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/ambarella.yaml
> > @@ -0,0 +1,22 @@
> > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/arm/ambarella.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Ambarella SoC Device Tree Bindings
> 
> Drop "Device Tree Bindings"

Well noted.

> > +
> > +maintainers:
> > +  - Li Chen <lchen@ambarella.com>
> > +
> > +properties:
> > +  $nodename:
> > +    const: "/"
> > +  compatible:
> > +    oneOf:
> > +      - description: Ambarella SoC based platforms
> > +        items:
> > +          - enum:
> > +              - ambarella,s6lm

Thanks for your review!

Regards,
Li

Re: [PATCH 03/15] dt-bindings: arm: ambarella: Add binding for Ambarella ARM platforms

[Li Chen]

On Mon, 23 Jan 2023 16:03:27 +0800,
Krzysztof Kozlowski wrote:
> 
> On 23/01/2023 08:32, Li Chen wrote:
> > This introduces binding for Ambarella s6lm SoC.
> > 
> > Signed-off-by: Li Chen <lchen@ambarella.com>
> > Change-Id: Id95d91218625a1f0b3413aac101c2ca8831f0385
> 
> Please run scripts/checkpatch.pl and fix reported warnings.

Sorry for it, I do run checkpatch & sparse and fix issues, but forget to remove the
Change-id finally, will remove it in v2.

> > ---
> >  .../devicetree/bindings/arm/ambarella.yaml    | 22 +++++++++++++++++++
> >  MAINTAINERS                                   |  6 +++++
> >  2 files changed, 28 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/arm/ambarella.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/ambarella.yaml b/Documentation/devicetree/bindings/arm/ambarella.yaml
> > new file mode 100644
> > index 000000000000..2c8ff75b57b9
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/ambarella.yaml
> > @@ -0,0 +1,22 @@
> > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/arm/ambarella.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Ambarella SoC Device Tree Bindings
> 
> Drop "Device Tree Bindings"

Well noted.

> > +
> > +maintainers:
> > +  - Li Chen <lchen@ambarella.com>
> > +
> > +properties:
> > +  $nodename:
> > +    const: "/"
> > +  compatible:
> > +    oneOf:
> > +      - description: Ambarella SoC based platforms
> > +        items:
> > +          - enum:
> > +              - ambarella,s6lm

Thanks for your review!

Regards,
Li

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Re: [PATCH 04/15] dt-bindings: arm: add support for Ambarella SoC

[Krzysztof Kozlowski]

On 23/01/2023 08:32, Li Chen wrote:
> Create a vendor directory for Ambarella, and add
> cpuid, rct, scratchpad documents.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: I2c29e45c08666489b0d9b588ac37d713f5b723d1

Please run scripts/checkpatch.pl and fix reported warnings.

Applies to all your patches. Also test them... I have doubts that you
tested if you actually ignored checkpatch :/

> ---
>  .../arm/ambarella/ambarella,cpuid.yaml        | 24 +++++++++++++++++++
>  .../bindings/arm/ambarella/ambarella,rct.yaml | 24 +++++++++++++++++++
>  .../arm/ambarella/ambarella,scratchpad.yaml   | 24 +++++++++++++++++++
>  .../bindings/arm/ambarella/ambarella.yaml     | 22 +++++++++++++++++
>  MAINTAINERS                                   |  4 ++++
>  5 files changed, 98 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml
>  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml
>  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,scratchpad.yaml
>  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella.yaml
> 
> diff --git a/Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml b/Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml
> new file mode 100644
> index 000000000000..1f4d9cec8f92
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml

This goes to soc

> @@ -0,0 +1,24 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/ambarella,cpuid.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella SoC ID
> +
> +maintainers:
> +  - Li Chen <lchen@ambarella.com>

Missing description.

> +
> +properties:
> +  compatible:
> +    const: "ambarella,cpuid", "syscon"

Drop quotes (applies to all your patches)

Missing SoC specific compatible.

> +
> +  reg:
> +    maxItems: 1

Missing additionalProperties. sorry, start from scratch from some
existing recent bindings or better example-schema.

> +
> +examples:
> +  - |
> +    cpuid_syscon: cpuid@e0000000 {
> +        compatible = "ambarella,cpuid", "syscon";
> +        reg = <0xe0000000 0x1000>;
> +    };
> diff --git a/Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml b/Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml
> new file mode 100644
> index 000000000000..7279bab17d9e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml
> @@ -0,0 +1,24 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/ambarella,rct.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella RCT module
> +
> +maintainers:
> +  - Li Chen <lchen@ambarella.com>
> +
> +properties:
> +  compatible:
> +    const: "ambarella,rct", "syscon"

All the same problems.

> +
> +  reg:
> +    maxItems: 1
> +
> +examples:
> +  - |
> +		rct_syscon: rct_syscon@ed080000 {

Really? Just take a look and you will see wrong indentation. Also drop
underscores in node names and "rct". Node names should be generic.


> +        compatible = "ambarella,rct", "syscon";
> +        reg = <0xed080000 0x1000>;
> +    };
> diff --git a/Documentation/devicetree/bindings/arm/ambarella/ambarella,scratchpad.yaml b/Documentation/devicetree/bindings/arm/ambarella/ambarella,scratchpad.yaml
> new file mode 100644
> index 000000000000..5d2bd243b5c9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/ambarella/ambarella,scratchpad.yaml
> @@ -0,0 +1,24 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/ambarella,scratchpad.yaml#

That's not a clock controller!


> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella Scratchpad
> +
> +maintainers:
> +  - Li Chen <lchen@ambarella.com>
> +
> +properties:
> +  compatible:
> +    const: "ambarella,scratchpad", "syscon"
> +
> +  reg:
> +    maxItems: 1
> +
> +examples:
> +  - |
> +    scratchpad_syscon: scratchpad_syscon@e0022000 {

All the same problems.

> +        compatible = "ambarella,scratchpad", "syscon";
> +        reg = <0xe0022000 0x100>;
> +    };
> diff --git a/Documentation/devicetree/bindings/arm/ambarella/ambarella.yaml b/Documentation/devicetree/bindings/arm/ambarella/ambarella.yaml
> new file mode 100644
> index 000000000000..5991bd745c05
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/ambarella/ambarella.yaml
> @@ -0,0 +1,22 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/ambarella.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella SoC Device Tree Bindings
> +
> +maintainers:
> +  - Li Chen <lchen@ambarella.com>
> +
> +properties:
> +  $nodename:
> +    const: "/"
> +  compatible:
> +    oneOf:
> +      - description: Ambarella SoC based platforms
> +        items:
> +          - enum:
> +              - ambarella,s6lm

What is this? How do you expect it to apply? Can you try by yourself?


Best regards,
Krzysztof

Re: [PATCH 04/15] dt-bindings: arm: add support for Ambarella SoC

[Krzysztof Kozlowski]

On 23/01/2023 08:32, Li Chen wrote:
> Create a vendor directory for Ambarella, and add
> cpuid, rct, scratchpad documents.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: I2c29e45c08666489b0d9b588ac37d713f5b723d1

Please run scripts/checkpatch.pl and fix reported warnings.

Applies to all your patches. Also test them... I have doubts that you
tested if you actually ignored checkpatch :/

> ---
>  .../arm/ambarella/ambarella,cpuid.yaml        | 24 +++++++++++++++++++
>  .../bindings/arm/ambarella/ambarella,rct.yaml | 24 +++++++++++++++++++
>  .../arm/ambarella/ambarella,scratchpad.yaml   | 24 +++++++++++++++++++
>  .../bindings/arm/ambarella/ambarella.yaml     | 22 +++++++++++++++++
>  MAINTAINERS                                   |  4 ++++
>  5 files changed, 98 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml
>  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml
>  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,scratchpad.yaml
>  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella.yaml
> 
> diff --git a/Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml b/Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml
> new file mode 100644
> index 000000000000..1f4d9cec8f92
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml

This goes to soc

> @@ -0,0 +1,24 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/ambarella,cpuid.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella SoC ID
> +
> +maintainers:
> +  - Li Chen <lchen@ambarella.com>

Missing description.

> +
> +properties:
> +  compatible:
> +    const: "ambarella,cpuid", "syscon"

Drop quotes (applies to all your patches)

Missing SoC specific compatible.

> +
> +  reg:
> +    maxItems: 1

Missing additionalProperties. sorry, start from scratch from some
existing recent bindings or better example-schema.

> +
> +examples:
> +  - |
> +    cpuid_syscon: cpuid@e0000000 {
> +        compatible = "ambarella,cpuid", "syscon";
> +        reg = <0xe0000000 0x1000>;
> +    };
> diff --git a/Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml b/Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml
> new file mode 100644
> index 000000000000..7279bab17d9e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml
> @@ -0,0 +1,24 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/ambarella,rct.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella RCT module
> +
> +maintainers:
> +  - Li Chen <lchen@ambarella.com>
> +
> +properties:
> +  compatible:
> +    const: "ambarella,rct", "syscon"

All the same problems.

> +
> +  reg:
> +    maxItems: 1
> +
> +examples:
> +  - |
> +		rct_syscon: rct_syscon@ed080000 {

Really? Just take a look and you will see wrong indentation. Also drop
underscores in node names and "rct". Node names should be generic.


> +        compatible = "ambarella,rct", "syscon";
> +        reg = <0xed080000 0x1000>;
> +    };
> diff --git a/Documentation/devicetree/bindings/arm/ambarella/ambarella,scratchpad.yaml b/Documentation/devicetree/bindings/arm/ambarella/ambarella,scratchpad.yaml
> new file mode 100644
> index 000000000000..5d2bd243b5c9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/ambarella/ambarella,scratchpad.yaml
> @@ -0,0 +1,24 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/ambarella,scratchpad.yaml#

That's not a clock controller!


> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella Scratchpad
> +
> +maintainers:
> +  - Li Chen <lchen@ambarella.com>
> +
> +properties:
> +  compatible:
> +    const: "ambarella,scratchpad", "syscon"
> +
> +  reg:
> +    maxItems: 1
> +
> +examples:
> +  - |
> +    scratchpad_syscon: scratchpad_syscon@e0022000 {

All the same problems.

> +        compatible = "ambarella,scratchpad", "syscon";
> +        reg = <0xe0022000 0x100>;
> +    };
> diff --git a/Documentation/devicetree/bindings/arm/ambarella/ambarella.yaml b/Documentation/devicetree/bindings/arm/ambarella/ambarella.yaml
> new file mode 100644
> index 000000000000..5991bd745c05
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/ambarella/ambarella.yaml
> @@ -0,0 +1,22 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/ambarella.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella SoC Device Tree Bindings
> +
> +maintainers:
> +  - Li Chen <lchen@ambarella.com>
> +
> +properties:
> +  $nodename:
> +    const: "/"
> +  compatible:
> +    oneOf:
> +      - description: Ambarella SoC based platforms
> +        items:
> +          - enum:
> +              - ambarella,s6lm

What is this? How do you expect it to apply? Can you try by yourself?


Best regards,
Krzysztof


_______________________________________________
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Re: [PATCH 04/15] dt-bindings: arm: add support for Ambarella SoC

[Li Chen]

On Mon, 23 Jan 2023 16:07:32 +0800,
Krzysztof Kozlowski wrote:
>
> On 23/01/2023 08:32, Li Chen wrote:
> > Create a vendor directory for Ambarella, and add
> > cpuid, rct, scratchpad documents.
> >
> > Signed-off-by: Li Chen <lchen@ambarella.com>
> > Change-Id: I2c29e45c08666489b0d9b588ac37d713f5b723d1
>
> Please run scripts/checkpatch.pl and fix reported warnings.
>
> Applies to all your patches. Also test them... I have doubts that you
> tested if you actually ignored checkpatch :/

Yeah, I checkpatch all patches, and have planned to fix Change-Id finally(manually),
but forget it before sending mails, my bad, sorry. I will remove it in v2.

> > ---
> >  .../arm/ambarella/ambarella,cpuid.yaml        | 24 +++++++++++++++++++
> >  .../bindings/arm/ambarella/ambarella,rct.yaml | 24 +++++++++++++++++++
> >  .../arm/ambarella/ambarella,scratchpad.yaml   | 24 +++++++++++++++++++
> >  .../bindings/arm/ambarella/ambarella.yaml     | 22 +++++++++++++++++
> >  MAINTAINERS                                   |  4 ++++
> >  5 files changed, 98 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml
> >  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml
> >  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,scratchpad.yaml
> >  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml b/Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml
> > new file mode 100644
> > index 000000000000..1f4d9cec8f92
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml
>
> This goes to soc

Thanks, I wasn't aware that there is a document dir named soc. I will move cpuid yaml
to bindings/soc/ambarella/, and leave other yaml still here.

> > @@ -0,0 +1,24 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/ambarella,cpuid.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Ambarella SoC ID
> > +
> > +maintainers:
> > +  - Li Chen <lchen@ambarella.com>
>
> Missing description.

Sorry, description will be added in v2. BTW, does other YAMLs in this patch
also need descriptions?

> > +
> > +properties:
> > +  compatible:
> > +    const: "ambarella,cpuid", "syscon"
>
> Drop quotes (applies to all your patches)

OK, thanks!

> Missing SoC specific compatible.
>
> > +
> > +  reg:
> > +    maxItems: 1
>
> Missing additionalProperties. sorry, start from scratch from some
> existing recent bindings or better example-schema.

Good to know that there is example-schema, thanks!
 
> > +
> > +examples:
> > +  - |
> > +    cpuid_syscon: cpuid@e0000000 {
> > +        compatible = "ambarella,cpuid", "syscon";
> > +        reg = <0xe0000000 0x1000>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml b/Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml
> > new file mode 100644
> > index 000000000000..7279bab17d9e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml
> > @@ -0,0 +1,24 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/ambarella,rct.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Ambarella RCT module
> > +
> > +maintainers:
> > +  - Li Chen <lchen@ambarella.com>
> > +
> > +properties:
> > +  compatible:
> > +    const: "ambarella,rct", "syscon"
>
> All the same problems.

Well noted.

> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +examples:
> > +  - |
> > +		rct_syscon: rct_syscon@ed080000 {
>
> Really? Just take a look and you will see wrong indentation. Also drop
> underscores in node names and "rct". Node names should be generic.

Sorry for the wrong indentation, will fix it in v2.

Is it ok to contain underscores in lable? if so, I will change it into

rct_syscon: syscon@ed080000 {

in v2.

>
> > +        compatible = "ambarella,rct", "syscon";
> > +        reg = <0xed080000 0x1000>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/arm/ambarella/ambarella,scratchpad.yaml b/Documentation/devicetree/bindings/arm/ambarella/ambarella,scratchpad.yaml
> > new file mode 100644
> > index 000000000000..5d2bd243b5c9
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/ambarella/ambarella,scratchpad.yaml
> > @@ -0,0 +1,24 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/ambarella,scratchpad.yaml#
>
> That's not a clock controller!

Sorry, will fix it in v2.

> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Ambarella Scratchpad
> > +
> > +maintainers:
> > +  - Li Chen <lchen@ambarella.com>
> > +
> > +properties:
> > +  compatible:
> > +    const: "ambarella,scratchpad", "syscon"
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +examples:
> > +  - |
> > +    scratchpad_syscon: scratchpad_syscon@e0022000 {
>
> All the same problems.

Well noted.

> > +        compatible = "ambarella,scratchpad", "syscon";
> > +        reg = <0xe0022000 0x100>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/arm/ambarella/ambarella.yaml b/Documentation/devicetree/bindings/arm/ambarella/ambarella.yaml
> > new file mode 100644
> > index 000000000000..5991bd745c05
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/ambarella/ambarella.yaml
> > @@ -0,0 +1,22 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/arm/ambarella.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Ambarella SoC Device Tree Bindings
> > +
> > +maintainers:
> > +  - Li Chen <lchen@ambarella.com>
> > +
> > +properties:
> > +  $nodename:
> > +    const: "/"
> > +  compatible:
> > +    oneOf:
> > +      - description: Ambarella SoC based platforms
> > +        items:
> > +          - enum:
> > +              - ambarella,s6lm
>
> What is this? How do you expect it to apply? Can you try by yourself?

Sorry, I didn't find this file is duplicited with outside ambarella.yaml.
I will remove it in v2.

Thanks for your review!

Regards,
Li

Re: [PATCH 04/15] dt-bindings: arm: add support for Ambarella SoC

[Li Chen]

On Mon, 23 Jan 2023 16:07:32 +0800,
Krzysztof Kozlowski wrote:
>
> On 23/01/2023 08:32, Li Chen wrote:
> > Create a vendor directory for Ambarella, and add
> > cpuid, rct, scratchpad documents.
> >
> > Signed-off-by: Li Chen <lchen@ambarella.com>
> > Change-Id: I2c29e45c08666489b0d9b588ac37d713f5b723d1
>
> Please run scripts/checkpatch.pl and fix reported warnings.
>
> Applies to all your patches. Also test them... I have doubts that you
> tested if you actually ignored checkpatch :/

Yeah, I checkpatch all patches, and have planned to fix Change-Id finally(manually),
but forget it before sending mails, my bad, sorry. I will remove it in v2.

> > ---
> >  .../arm/ambarella/ambarella,cpuid.yaml        | 24 +++++++++++++++++++
> >  .../bindings/arm/ambarella/ambarella,rct.yaml | 24 +++++++++++++++++++
> >  .../arm/ambarella/ambarella,scratchpad.yaml   | 24 +++++++++++++++++++
> >  .../bindings/arm/ambarella/ambarella.yaml     | 22 +++++++++++++++++
> >  MAINTAINERS                                   |  4 ++++
> >  5 files changed, 98 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml
> >  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml
> >  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,scratchpad.yaml
> >  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml b/Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml
> > new file mode 100644
> > index 000000000000..1f4d9cec8f92
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml
>
> This goes to soc

Thanks, I wasn't aware that there is a document dir named soc. I will move cpuid yaml
to bindings/soc/ambarella/, and leave other yaml still here.

> > @@ -0,0 +1,24 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/ambarella,cpuid.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Ambarella SoC ID
> > +
> > +maintainers:
> > +  - Li Chen <lchen@ambarella.com>
>
> Missing description.

Sorry, description will be added in v2. BTW, does other YAMLs in this patch
also need descriptions?

> > +
> > +properties:
> > +  compatible:
> > +    const: "ambarella,cpuid", "syscon"
>
> Drop quotes (applies to all your patches)

OK, thanks!

> Missing SoC specific compatible.
>
> > +
> > +  reg:
> > +    maxItems: 1
>
> Missing additionalProperties. sorry, start from scratch from some
> existing recent bindings or better example-schema.

Good to know that there is example-schema, thanks!
 
> > +
> > +examples:
> > +  - |
> > +    cpuid_syscon: cpuid@e0000000 {
> > +        compatible = "ambarella,cpuid", "syscon";
> > +        reg = <0xe0000000 0x1000>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml b/Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml
> > new file mode 100644
> > index 000000000000..7279bab17d9e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml
> > @@ -0,0 +1,24 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/ambarella,rct.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Ambarella RCT module
> > +
> > +maintainers:
> > +  - Li Chen <lchen@ambarella.com>
> > +
> > +properties:
> > +  compatible:
> > +    const: "ambarella,rct", "syscon"
>
> All the same problems.

Well noted.

> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +examples:
> > +  - |
> > +		rct_syscon: rct_syscon@ed080000 {
>
> Really? Just take a look and you will see wrong indentation. Also drop
> underscores in node names and "rct". Node names should be generic.

Sorry for the wrong indentation, will fix it in v2.

Is it ok to contain underscores in lable? if so, I will change it into

rct_syscon: syscon@ed080000 {

in v2.

>
> > +        compatible = "ambarella,rct", "syscon";
> > +        reg = <0xed080000 0x1000>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/arm/ambarella/ambarella,scratchpad.yaml b/Documentation/devicetree/bindings/arm/ambarella/ambarella,scratchpad.yaml
> > new file mode 100644
> > index 000000000000..5d2bd243b5c9
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/ambarella/ambarella,scratchpad.yaml
> > @@ -0,0 +1,24 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/ambarella,scratchpad.yaml#
>
> That's not a clock controller!

Sorry, will fix it in v2.

> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Ambarella Scratchpad
> > +
> > +maintainers:
> > +  - Li Chen <lchen@ambarella.com>
> > +
> > +properties:
> > +  compatible:
> > +    const: "ambarella,scratchpad", "syscon"
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +examples:
> > +  - |
> > +    scratchpad_syscon: scratchpad_syscon@e0022000 {
>
> All the same problems.

Well noted.

> > +        compatible = "ambarella,scratchpad", "syscon";
> > +        reg = <0xe0022000 0x100>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/arm/ambarella/ambarella.yaml b/Documentation/devicetree/bindings/arm/ambarella/ambarella.yaml
> > new file mode 100644
> > index 000000000000..5991bd745c05
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/ambarella/ambarella.yaml
> > @@ -0,0 +1,22 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/arm/ambarella.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Ambarella SoC Device Tree Bindings
> > +
> > +maintainers:
> > +  - Li Chen <lchen@ambarella.com>
> > +
> > +properties:
> > +  $nodename:
> > +    const: "/"
> > +  compatible:
> > +    oneOf:
> > +      - description: Ambarella SoC based platforms
> > +        items:
> > +          - enum:
> > +              - ambarella,s6lm
>
> What is this? How do you expect it to apply? Can you try by yourself?

Sorry, I didn't find this file is duplicited with outside ambarella.yaml.
I will remove it in v2.

Thanks for your review!

Regards,
Li

_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 04/15] dt-bindings: arm: add support for Ambarella SoC

[Krzysztof Kozlowski]

On 23/01/2023 16:09, Li Chen wrote:
> On Mon, 23 Jan 2023 16:07:32 +0800,
> Krzysztof Kozlowski wrote:
>>
>> On 23/01/2023 08:32, Li Chen wrote:
>>> Create a vendor directory for Ambarella, and add
>>> cpuid, rct, scratchpad documents.
>>>
>>> Signed-off-by: Li Chen <lchen@ambarella.com>
>>> Change-Id: I2c29e45c08666489b0d9b588ac37d713f5b723d1
>>
>> Please run scripts/checkpatch.pl and fix reported warnings.
>>
>> Applies to all your patches. Also test them... I have doubts that you
>> tested if you actually ignored checkpatch :/
> 
> Yeah, I checkpatch all patches, and have planned to fix Change-Id finally(manually),
> but forget it before sending mails, my bad, sorry. I will remove it in v2.
> 
>>> ---
>>>  .../arm/ambarella/ambarella,cpuid.yaml        | 24 +++++++++++++++++++
>>>  .../bindings/arm/ambarella/ambarella,rct.yaml | 24 +++++++++++++++++++
>>>  .../arm/ambarella/ambarella,scratchpad.yaml   | 24 +++++++++++++++++++
>>>  .../bindings/arm/ambarella/ambarella.yaml     | 22 +++++++++++++++++
>>>  MAINTAINERS                                   |  4 ++++
>>>  5 files changed, 98 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml
>>>  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml
>>>  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,scratchpad.yaml
>>>  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml b/Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml
>>> new file mode 100644
>>> index 000000000000..1f4d9cec8f92
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml
>>
>> This goes to soc
> 
> Thanks, I wasn't aware that there is a document dir named soc. I will move cpuid yaml
> to bindings/soc/ambarella/, and leave other yaml still here.

However if device has chip identification features (chipid), then the
location is "hwinfo".

> 
>>> @@ -0,0 +1,24 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/clock/ambarella,cpuid.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Ambarella SoC ID
>>> +
>>> +maintainers:
>>> +  - Li Chen <lchen@ambarella.com>
>>
>> Missing description.
> 
> Sorry, description will be added in v2. BTW, does other YAMLs in this patch
> also need descriptions?

In general yes - we want descriptions which will bring additional
information. Description should not repeat title, but add more data. For
trivial cases - maybe actually this one SoC ID - you can skip it.



> 
>>> +
>>> +properties:
>>> +  compatible:
>>> +    const: "ambarella,cpuid", "syscon"
>>
>> Drop quotes (applies to all your patches)
> 
> OK, thanks!
> 
>> Missing SoC specific compatible.
>>
>>> +
>>> +  reg:
>>> +    maxItems: 1
>>
>> Missing additionalProperties. sorry, start from scratch from some
>> existing recent bindings or better example-schema.
> 
> Good to know that there is example-schema, thanks!
>  
>>> +
>>> +examples:
>>> +  - |
>>> +    cpuid_syscon: cpuid@e0000000 {
>>> +        compatible = "ambarella,cpuid", "syscon";
>>> +        reg = <0xe0000000 0x1000>;
>>> +    };
>>> diff --git a/Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml b/Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml
>>> new file mode 100644
>>> index 000000000000..7279bab17d9e
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml
>>> @@ -0,0 +1,24 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/clock/ambarella,rct.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Ambarella RCT module
>>> +
>>> +maintainers:
>>> +  - Li Chen <lchen@ambarella.com>
>>> +
>>> +properties:
>>> +  compatible:
>>> +    const: "ambarella,rct", "syscon"
>>
>> All the same problems.
> 
> Well noted.
> 
>>> +
>>> +  reg:
>>> +    maxItems: 1
>>> +
>>> +examples:
>>> +  - |
>>> +		rct_syscon: rct_syscon@ed080000 {
>>
>> Really? Just take a look and you will see wrong indentation. Also drop
>> underscores in node names and "rct". Node names should be generic.
> 
> Sorry for the wrong indentation, will fix it in v2.
> 
> Is it ok to contain underscores in lable? if so, I will change it into
> 
> rct_syscon: syscon@ed080000 {

Yes, label can have it.

Best regards,
Krzysztof

Re: [PATCH 04/15] dt-bindings: arm: add support for Ambarella SoC

[Krzysztof Kozlowski]

On 23/01/2023 16:09, Li Chen wrote:
> On Mon, 23 Jan 2023 16:07:32 +0800,
> Krzysztof Kozlowski wrote:
>>
>> On 23/01/2023 08:32, Li Chen wrote:
>>> Create a vendor directory for Ambarella, and add
>>> cpuid, rct, scratchpad documents.
>>>
>>> Signed-off-by: Li Chen <lchen@ambarella.com>
>>> Change-Id: I2c29e45c08666489b0d9b588ac37d713f5b723d1
>>
>> Please run scripts/checkpatch.pl and fix reported warnings.
>>
>> Applies to all your patches. Also test them... I have doubts that you
>> tested if you actually ignored checkpatch :/
> 
> Yeah, I checkpatch all patches, and have planned to fix Change-Id finally(manually),
> but forget it before sending mails, my bad, sorry. I will remove it in v2.
> 
>>> ---
>>>  .../arm/ambarella/ambarella,cpuid.yaml        | 24 +++++++++++++++++++
>>>  .../bindings/arm/ambarella/ambarella,rct.yaml | 24 +++++++++++++++++++
>>>  .../arm/ambarella/ambarella,scratchpad.yaml   | 24 +++++++++++++++++++
>>>  .../bindings/arm/ambarella/ambarella.yaml     | 22 +++++++++++++++++
>>>  MAINTAINERS                                   |  4 ++++
>>>  5 files changed, 98 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml
>>>  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml
>>>  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella,scratchpad.yaml
>>>  create mode 100644 Documentation/devicetree/bindings/arm/ambarella/ambarella.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml b/Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml
>>> new file mode 100644
>>> index 000000000000..1f4d9cec8f92
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml
>>
>> This goes to soc
> 
> Thanks, I wasn't aware that there is a document dir named soc. I will move cpuid yaml
> to bindings/soc/ambarella/, and leave other yaml still here.

However if device has chip identification features (chipid), then the
location is "hwinfo".

> 
>>> @@ -0,0 +1,24 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/clock/ambarella,cpuid.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Ambarella SoC ID
>>> +
>>> +maintainers:
>>> +  - Li Chen <lchen@ambarella.com>
>>
>> Missing description.
> 
> Sorry, description will be added in v2. BTW, does other YAMLs in this patch
> also need descriptions?

In general yes - we want descriptions which will bring additional
information. Description should not repeat title, but add more data. For
trivial cases - maybe actually this one SoC ID - you can skip it.



> 
>>> +
>>> +properties:
>>> +  compatible:
>>> +    const: "ambarella,cpuid", "syscon"
>>
>> Drop quotes (applies to all your patches)
> 
> OK, thanks!
> 
>> Missing SoC specific compatible.
>>
>>> +
>>> +  reg:
>>> +    maxItems: 1
>>
>> Missing additionalProperties. sorry, start from scratch from some
>> existing recent bindings or better example-schema.
> 
> Good to know that there is example-schema, thanks!
>  
>>> +
>>> +examples:
>>> +  - |
>>> +    cpuid_syscon: cpuid@e0000000 {
>>> +        compatible = "ambarella,cpuid", "syscon";
>>> +        reg = <0xe0000000 0x1000>;
>>> +    };
>>> diff --git a/Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml b/Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml
>>> new file mode 100644
>>> index 000000000000..7279bab17d9e
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml
>>> @@ -0,0 +1,24 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/clock/ambarella,rct.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Ambarella RCT module
>>> +
>>> +maintainers:
>>> +  - Li Chen <lchen@ambarella.com>
>>> +
>>> +properties:
>>> +  compatible:
>>> +    const: "ambarella,rct", "syscon"
>>
>> All the same problems.
> 
> Well noted.
> 
>>> +
>>> +  reg:
>>> +    maxItems: 1
>>> +
>>> +examples:
>>> +  - |
>>> +		rct_syscon: rct_syscon@ed080000 {
>>
>> Really? Just take a look and you will see wrong indentation. Also drop
>> underscores in node names and "rct". Node names should be generic.
> 
> Sorry for the wrong indentation, will fix it in v2.
> 
> Is it ok to contain underscores in lable? if so, I will change it into
> 
> rct_syscon: syscon@ed080000 {

Yes, label can have it.

Best regards,
Krzysztof


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Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Krzysztof Kozlowski]

On 23/01/2023 08:32, Li Chen wrote:
> This patch introduce clock bindings for Ambarella.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: I29018a23ed3a5b79a1103e859a5c7ed7bb83a261

All the same problems plus new:

Subject: drop second/last, redundant "bindings". The "dt-bindings"
prefix is already stating that these are bindings.

> ---
>  .../clock/ambarella,composite-clock.yaml      | 52 ++++++++++++++++
>  .../bindings/clock/ambarella,pll-clock.yaml   | 59 +++++++++++++++++++
>  MAINTAINERS                                   |  2 +
>  3 files changed, 113 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
>  create mode 100644 Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
> 
> diff --git a/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml b/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
> new file mode 100644
> index 000000000000..fac1cb9379c4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
> @@ -0,0 +1,52 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/ambarella,composite-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella Composite Clock
> +
> +maintainers:
> +  - Li Chen <lchen@ambarella.com>
> +

Missing description.

> +properties:
> +  compatible:
> +    items:

Drop items.

> +      - const: ambarella,composite-clock

Missing SoC specific compatible. This is anyway not really correct
compatible...

> +
> +  clocks: true

No, needs constraints.

> +  assigned-clocks: true
> +  assigned-clock-parents: true
> +  assigned-clock-rates: true

Drop these three.

> +  clock-output-names: true

Missing constraints.

> +  amb,mux-regmap: true

NAK.

It's enough. The patches have very, very poor quality.

Missing description, missing type/$ref, wrong prefix.

> +  amb,div-regmap: true
> +  amb,div-width: true
> +  amb,div-shift: true

These two are arguments to phandle.

> +
> +  '#clock-cells':
> +    const: 0
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - '#clock-cells'
> +
> +additionalProperties: false

So why you decided to add it here and not in other places?
> +
> +examples:
> +  - |
> +      gclk_uart0: gclk-uart0 {

Wrong indentation.

> +        #clock-cells = <0>;
> +        compatible = "ambarella,composite-clock";
> +        clocks = <&osc>, <&gclk_core>, <&pll_out_enet>, <&pll_out_sd>;
> +        clock-output-names = "gclk_uart0";
> +        assigned-clocks = <&gclk_uart0>;
> +        assigned-clock-parents = <&osc>;
> +        assigned-clock-rates = <24000000>;
> +        amb,mux-regmap = <&rct_syscon 0x1c8>;
> +        amb,div-regmap = <&rct_syscon 0x038>;
> +        amb,div-width = <24>;
> +        amb,div-shift = <0>;
> +      };
> diff --git a/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml b/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
> new file mode 100644
> index 000000000000..65c1feb60041
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/ambarella,pll-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella PLL Clock
> +
> +maintainers:
> +  - Li Chen <lchen@ambarella.com>
> +
> +properties:
> +  compatible:
> +    enum:
> +      - ambarella,pll-clock
> +      - ambarella,clkpll-v0
> +
> +if:

No, this does not work like that. It sits under "allOf", located after
"required:".

> +  properties:
> +    compatible:
> +      const: ambarella,pll-clock
> +
> +then:
> +  properties:
> +    clocks:
> +      maxItems: 1
> +
> +    clock-output-names: true
> +    amb,clk-regmap: true
> +    amb,frac-mode: true
> +    assigned-clocks: true
> +    assigned-clock-rates: true

Same problems.

> +    gclk_axi: gclk-axi {
> +        #clock-cells = <0>;
> +        compatible = "fixed-factor-clock";

What is this example about? Not related at all. Provide real example.



Best regards,
Krzysztof

Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Krzysztof Kozlowski]

On 23/01/2023 08:32, Li Chen wrote:
> This patch introduce clock bindings for Ambarella.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: I29018a23ed3a5b79a1103e859a5c7ed7bb83a261

All the same problems plus new:

Subject: drop second/last, redundant "bindings". The "dt-bindings"
prefix is already stating that these are bindings.

> ---
>  .../clock/ambarella,composite-clock.yaml      | 52 ++++++++++++++++
>  .../bindings/clock/ambarella,pll-clock.yaml   | 59 +++++++++++++++++++
>  MAINTAINERS                                   |  2 +
>  3 files changed, 113 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
>  create mode 100644 Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
> 
> diff --git a/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml b/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
> new file mode 100644
> index 000000000000..fac1cb9379c4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
> @@ -0,0 +1,52 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/ambarella,composite-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella Composite Clock
> +
> +maintainers:
> +  - Li Chen <lchen@ambarella.com>
> +

Missing description.

> +properties:
> +  compatible:
> +    items:

Drop items.

> +      - const: ambarella,composite-clock

Missing SoC specific compatible. This is anyway not really correct
compatible...

> +
> +  clocks: true

No, needs constraints.

> +  assigned-clocks: true
> +  assigned-clock-parents: true
> +  assigned-clock-rates: true

Drop these three.

> +  clock-output-names: true

Missing constraints.

> +  amb,mux-regmap: true

NAK.

It's enough. The patches have very, very poor quality.

Missing description, missing type/$ref, wrong prefix.

> +  amb,div-regmap: true
> +  amb,div-width: true
> +  amb,div-shift: true

These two are arguments to phandle.

> +
> +  '#clock-cells':
> +    const: 0
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - '#clock-cells'
> +
> +additionalProperties: false

So why you decided to add it here and not in other places?
> +
> +examples:
> +  - |
> +      gclk_uart0: gclk-uart0 {

Wrong indentation.

> +        #clock-cells = <0>;
> +        compatible = "ambarella,composite-clock";
> +        clocks = <&osc>, <&gclk_core>, <&pll_out_enet>, <&pll_out_sd>;
> +        clock-output-names = "gclk_uart0";
> +        assigned-clocks = <&gclk_uart0>;
> +        assigned-clock-parents = <&osc>;
> +        assigned-clock-rates = <24000000>;
> +        amb,mux-regmap = <&rct_syscon 0x1c8>;
> +        amb,div-regmap = <&rct_syscon 0x038>;
> +        amb,div-width = <24>;
> +        amb,div-shift = <0>;
> +      };
> diff --git a/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml b/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
> new file mode 100644
> index 000000000000..65c1feb60041
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/ambarella,pll-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella PLL Clock
> +
> +maintainers:
> +  - Li Chen <lchen@ambarella.com>
> +
> +properties:
> +  compatible:
> +    enum:
> +      - ambarella,pll-clock
> +      - ambarella,clkpll-v0
> +
> +if:

No, this does not work like that. It sits under "allOf", located after
"required:".

> +  properties:
> +    compatible:
> +      const: ambarella,pll-clock
> +
> +then:
> +  properties:
> +    clocks:
> +      maxItems: 1
> +
> +    clock-output-names: true
> +    amb,clk-regmap: true
> +    amb,frac-mode: true
> +    assigned-clocks: true
> +    assigned-clock-rates: true

Same problems.

> +    gclk_axi: gclk-axi {
> +        #clock-cells = <0>;
> +        compatible = "fixed-factor-clock";

What is this example about? Not related at all. Provide real example.



Best regards,
Krzysztof


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Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Li Chen]

Hi Krzysztof,

Sorry for my late reply.

On Mon, 23 Jan 2023 16:11:08 +0800,
Krzysztof Kozlowski wrote:
>
> On 23/01/2023 08:32, Li Chen wrote:
> > This patch introduce clock bindings for Ambarella.
> >
> > Signed-off-by: Li Chen <lchen@ambarella.com>
> > Change-Id: I29018a23ed3a5b79a1103e859a5c7ed7bb83a261
>
> All the same problems plus new:
>
> Subject: drop second/last, redundant "bindings". The "dt-bindings"
> prefix is already stating that these are bindings.

Well noted.

> > ---
> >  .../clock/ambarella,composite-clock.yaml      | 52 ++++++++++++++++
> >  .../bindings/clock/ambarella,pll-clock.yaml   | 59 +++++++++++++++++++
> >  MAINTAINERS                                   |  2 +
> >  3 files changed, 113 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
> >  create mode 100644 Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml b/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
> > new file mode 100644
> > index 000000000000..fac1cb9379c4
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
> > @@ -0,0 +1,52 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/ambarella,composite-clock.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Ambarella Composite Clock
> > +
> > +maintainers:
> > +  - Li Chen <lchen@ambarella.com>
> > +
>
> Missing description.

Thanks, description as below will be added in v2:

"Ambarella SoCs integrates some composite clocks, like uart0, which aggrate the functionality
of the basic clock types, like mux and div."

> > +properties:
> > +  compatible:
> > +    items:
>
> Drop items.

Ok.

> > +      - const: ambarella,composite-clock
>
> Missing SoC specific compatible. This is anyway not really correct
> compatible...

Most Ambarella's compatibles don't contain SoC name, because we prefer
to use syscon + offsets in dts to tell driver the correct register offsets, or
ues struct soc_device and SoC identity stores in a given physical address.

So compatibles like "ambarella,composite-clock" and "ambarella,pinctrl" are
used widely in Ambarella kernels. Feel free to correct me if you think this
is not a good idea.

> > +
> > +  clocks: true
>
> No, needs constraints.

Ok. I will list all clocks name

> > +  assigned-clocks: true
> > +  assigned-clock-parents: true
> > +  assigned-clock-rates: true
>
> Drop these three.

Ok

> > +  clock-output-names: true
>
> Missing constraints.

Ok, I will add "maxItems: 1"

> > +  amb,mux-regmap: true
>
> NAK.
>
> It's enough. The patches have very, very poor quality.
>
> Missing description, missing type/$ref, wrong prefix.

Sorry, I forget to run dt_binding_check, I will spend some
time learning the binding and check, sorry for it.

> > +  amb,div-regmap: true
> > +  amb,div-width: true
> > +  amb,div-shift: true
>
> These two are arguments to phandle.

I will add description and $ref to regmap and width/shift.

> > +
> > +  '#clock-cells':
> > +    const: 0
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +  - '#clock-cells'
> > +
> > +additionalProperties: false
>
> So why you decided to add it here and not in other places?

I didn't understand it well. I will add it to other places in v2,
thanks for pointint out it.

> > +
> > +examples:
> > +  - |
> > +      gclk_uart0: gclk-uart0 {
>
> Wrong indentation.

Well noted.

> > +        #clock-cells = <0>;
> > +        compatible = "ambarella,composite-clock";
> > +        clocks = <&osc>, <&gclk_core>, <&pll_out_enet>, <&pll_out_sd>;
> > +        clock-output-names = "gclk_uart0";
> > +        assigned-clocks = <&gclk_uart0>;
> > +        assigned-clock-parents = <&osc>;
> > +        assigned-clock-rates = <24000000>;
> > +        amb,mux-regmap = <&rct_syscon 0x1c8>;
> > +        amb,div-regmap = <&rct_syscon 0x038>;
> > +        amb,div-width = <24>;
> > +        amb,div-shift = <0>;
> > +      };
> > diff --git a/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml b/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
> > new file mode 100644
> > index 000000000000..65c1feb60041
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
> > @@ -0,0 +1,59 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/ambarella,pll-clock.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Ambarella PLL Clock
> > +
> > +maintainers:
> > +  - Li Chen <lchen@ambarella.com>
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - ambarella,pll-clock
> > +      - ambarella,clkpll-v0
> > +
> > +if:
>
> No, this does not work like that. It sits under "allOf", located after
> "required:".

Thanks, I will learn "allOf" and use it in v2. BTW, we use the two compatibles as below:
clocks {
                compatible = "ambarella,clkpll-v0";
                ...
                gclk_core: gclk-core {
                        #clock-cells = <0>;
                        compatible = "ambarella,pll-clock";
                        clocks = <&osc>;
                        clock-output-names = "gclk_core";
                        amb,clk-regmap = <&rct_syscon 0x000 0x004 0x100 0x104 0x000 0x000>;
                };
                ...
}

I'm not sure can I describe the two compatibles in this single yaml, can you give some advice? thanks!

> > +  properties:
> > +    compatible:
> > +      const: ambarella,pll-clock
> > +
> > +then:
> > +  properties:
> > +    clocks:
> > +      maxItems: 1
> > +
> > +    clock-output-names: true
> > +    amb,clk-regmap: true
> > +    amb,frac-mode: true
> > +    assigned-clocks: true
> > +    assigned-clock-rates: true
>
> Same problems.

Ok.

> > +    gclk_axi: gclk-axi {
> > +        #clock-cells = <0>;
> > +        compatible = "fixed-factor-clock";
>
> What is this example about? Not related at all. Provide real example.

Sorry, I paste the wrong example, I will replace it with our gclk_core pll
instead.

Regards,
Li

Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Li Chen]

Hi Krzysztof,

Sorry for my late reply.

On Mon, 23 Jan 2023 16:11:08 +0800,
Krzysztof Kozlowski wrote:
>
> On 23/01/2023 08:32, Li Chen wrote:
> > This patch introduce clock bindings for Ambarella.
> >
> > Signed-off-by: Li Chen <lchen@ambarella.com>
> > Change-Id: I29018a23ed3a5b79a1103e859a5c7ed7bb83a261
>
> All the same problems plus new:
>
> Subject: drop second/last, redundant "bindings". The "dt-bindings"
> prefix is already stating that these are bindings.

Well noted.

> > ---
> >  .../clock/ambarella,composite-clock.yaml      | 52 ++++++++++++++++
> >  .../bindings/clock/ambarella,pll-clock.yaml   | 59 +++++++++++++++++++
> >  MAINTAINERS                                   |  2 +
> >  3 files changed, 113 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
> >  create mode 100644 Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml b/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
> > new file mode 100644
> > index 000000000000..fac1cb9379c4
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
> > @@ -0,0 +1,52 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/ambarella,composite-clock.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Ambarella Composite Clock
> > +
> > +maintainers:
> > +  - Li Chen <lchen@ambarella.com>
> > +
>
> Missing description.

Thanks, description as below will be added in v2:

"Ambarella SoCs integrates some composite clocks, like uart0, which aggrate the functionality
of the basic clock types, like mux and div."

> > +properties:
> > +  compatible:
> > +    items:
>
> Drop items.

Ok.

> > +      - const: ambarella,composite-clock
>
> Missing SoC specific compatible. This is anyway not really correct
> compatible...

Most Ambarella's compatibles don't contain SoC name, because we prefer
to use syscon + offsets in dts to tell driver the correct register offsets, or
ues struct soc_device and SoC identity stores in a given physical address.

So compatibles like "ambarella,composite-clock" and "ambarella,pinctrl" are
used widely in Ambarella kernels. Feel free to correct me if you think this
is not a good idea.

> > +
> > +  clocks: true
>
> No, needs constraints.

Ok. I will list all clocks name

> > +  assigned-clocks: true
> > +  assigned-clock-parents: true
> > +  assigned-clock-rates: true
>
> Drop these three.

Ok

> > +  clock-output-names: true
>
> Missing constraints.

Ok, I will add "maxItems: 1"

> > +  amb,mux-regmap: true
>
> NAK.
>
> It's enough. The patches have very, very poor quality.
>
> Missing description, missing type/$ref, wrong prefix.

Sorry, I forget to run dt_binding_check, I will spend some
time learning the binding and check, sorry for it.

> > +  amb,div-regmap: true
> > +  amb,div-width: true
> > +  amb,div-shift: true
>
> These two are arguments to phandle.

I will add description and $ref to regmap and width/shift.

> > +
> > +  '#clock-cells':
> > +    const: 0
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +  - '#clock-cells'
> > +
> > +additionalProperties: false
>
> So why you decided to add it here and not in other places?

I didn't understand it well. I will add it to other places in v2,
thanks for pointint out it.

> > +
> > +examples:
> > +  - |
> > +      gclk_uart0: gclk-uart0 {
>
> Wrong indentation.

Well noted.

> > +        #clock-cells = <0>;
> > +        compatible = "ambarella,composite-clock";
> > +        clocks = <&osc>, <&gclk_core>, <&pll_out_enet>, <&pll_out_sd>;
> > +        clock-output-names = "gclk_uart0";
> > +        assigned-clocks = <&gclk_uart0>;
> > +        assigned-clock-parents = <&osc>;
> > +        assigned-clock-rates = <24000000>;
> > +        amb,mux-regmap = <&rct_syscon 0x1c8>;
> > +        amb,div-regmap = <&rct_syscon 0x038>;
> > +        amb,div-width = <24>;
> > +        amb,div-shift = <0>;
> > +      };
> > diff --git a/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml b/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
> > new file mode 100644
> > index 000000000000..65c1feb60041
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
> > @@ -0,0 +1,59 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/ambarella,pll-clock.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Ambarella PLL Clock
> > +
> > +maintainers:
> > +  - Li Chen <lchen@ambarella.com>
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - ambarella,pll-clock
> > +      - ambarella,clkpll-v0
> > +
> > +if:
>
> No, this does not work like that. It sits under "allOf", located after
> "required:".

Thanks, I will learn "allOf" and use it in v2. BTW, we use the two compatibles as below:
clocks {
                compatible = "ambarella,clkpll-v0";
                ...
                gclk_core: gclk-core {
                        #clock-cells = <0>;
                        compatible = "ambarella,pll-clock";
                        clocks = <&osc>;
                        clock-output-names = "gclk_core";
                        amb,clk-regmap = <&rct_syscon 0x000 0x004 0x100 0x104 0x000 0x000>;
                };
                ...
}

I'm not sure can I describe the two compatibles in this single yaml, can you give some advice? thanks!

> > +  properties:
> > +    compatible:
> > +      const: ambarella,pll-clock
> > +
> > +then:
> > +  properties:
> > +    clocks:
> > +      maxItems: 1
> > +
> > +    clock-output-names: true
> > +    amb,clk-regmap: true
> > +    amb,frac-mode: true
> > +    assigned-clocks: true
> > +    assigned-clock-rates: true
>
> Same problems.

Ok.

> > +    gclk_axi: gclk-axi {
> > +        #clock-cells = <0>;
> > +        compatible = "fixed-factor-clock";
>
> What is this example about? Not related at all. Provide real example.

Sorry, I paste the wrong example, I will replace it with our gclk_core pll
instead.

Regards,
Li

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Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Krzysztof Kozlowski]

On 25/01/2023 10:28, Li Chen wrote:
> 
> Hi Krzysztof,
> 
> Sorry for my late reply.
> 
> On Mon, 23 Jan 2023 16:11:08 +0800,
> Krzysztof Kozlowski wrote:
>>
>> On 23/01/2023 08:32, Li Chen wrote:
>>> This patch introduce clock bindings for Ambarella.
>>>
>>> Signed-off-by: Li Chen <lchen@ambarella.com>
>>> Change-Id: I29018a23ed3a5b79a1103e859a5c7ed7bb83a261
>>
>> All the same problems plus new:
>>
>> Subject: drop second/last, redundant "bindings". The "dt-bindings"
>> prefix is already stating that these are bindings.
> 
> Well noted.
> 
>>> ---
>>>  .../clock/ambarella,composite-clock.yaml      | 52 ++++++++++++++++
>>>  .../bindings/clock/ambarella,pll-clock.yaml   | 59 +++++++++++++++++++
>>>  MAINTAINERS                                   |  2 +
>>>  3 files changed, 113 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
>>>  create mode 100644 Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml b/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
>>> new file mode 100644
>>> index 000000000000..fac1cb9379c4
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
>>> @@ -0,0 +1,52 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/clock/ambarella,composite-clock.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Ambarella Composite Clock
>>> +
>>> +maintainers:
>>> +  - Li Chen <lchen@ambarella.com>
>>> +
>>
>> Missing description.
> 
> Thanks, description as below will be added in v2:
> 
> "Ambarella SoCs integrates some composite clocks, like uart0, which aggrate the functionality
> of the basic clock types, like mux and div."
> 
>>> +properties:
>>> +  compatible:
>>> +    items:
>>
>> Drop items.
> 
> Ok.
> 
>>> +      - const: ambarella,composite-clock
>>
>> Missing SoC specific compatible. This is anyway not really correct
>> compatible...
> 
> Most Ambarella's compatibles don't contain SoC name, because we prefer
> to use syscon + offsets in dts to tell driver the correct register offsets, or
> ues struct soc_device and SoC identity stores in a given physical address.

That's not correct hardware description. Drop the syscon and offsets.

> 
> So compatibles like "ambarella,composite-clock" and "ambarella,pinctrl" are
> used widely in Ambarella kernels. 

What do you do downstream does not matter. You can invent any crazy idea
and it is not an argument that it should be done like that. Usually
downstream code is incorrect...

> Feel free to correct me if you think this
> is not a good idea.

This is bad idea. Compatibles should be specific. Devices should not use
syscons to poke other registers, unless strictly necessary, but have
strictly defined MMIO address space and use it.

> 
>>> +
>>> +  clocks: true
>>
>> No, needs constraints.
> 
> Ok. I will list all clocks name
> 
>>> +  assigned-clocks: true
>>> +  assigned-clock-parents: true
>>> +  assigned-clock-rates: true
>>
>> Drop these three.
> 
> Ok
> 
>>> +  clock-output-names: true
>>
>> Missing constraints.
> 
> Ok, I will add "maxItems: 1"
> 
>>> +  amb,mux-regmap: true
>>
>> NAK.
>>
>> It's enough. The patches have very, very poor quality.
>>
>> Missing description, missing type/$ref, wrong prefix.
> 
> Sorry, I forget to run dt_binding_check, I will spend some
> time learning the binding and check, sorry for it.
> 
>>> +  amb,div-regmap: true
>>> +  amb,div-width: true
>>> +  amb,div-shift: true
>>
>> These two are arguments to phandle.
> 
> I will add description and $ref to regmap and width/shift.

Drop all these syscon properties.

> 
>>> +
>>> +  '#clock-cells':
>>> +    const: 0
>>> +
>>> +required:
>>> +  - compatible
>>> +  - reg
>>> +  - clocks
>>> +  - '#clock-cells'
>>> +
>>> +additionalProperties: false
>>
>> So why you decided to add it here and not in other places?
> 
> I didn't understand it well. I will add it to other places in v2,
> thanks for pointint out it.
> 
>>> +
>>> +examples:
>>> +  - |
>>> +      gclk_uart0: gclk-uart0 {
>>
>> Wrong indentation.
> 
> Well noted.
> 
>>> +        #clock-cells = <0>;
>>> +        compatible = "ambarella,composite-clock";
>>> +        clocks = <&osc>, <&gclk_core>, <&pll_out_enet>, <&pll_out_sd>;
>>> +        clock-output-names = "gclk_uart0";
>>> +        assigned-clocks = <&gclk_uart0>;
>>> +        assigned-clock-parents = <&osc>;
>>> +        assigned-clock-rates = <24000000>;
>>> +        amb,mux-regmap = <&rct_syscon 0x1c8>;
>>> +        amb,div-regmap = <&rct_syscon 0x038>;
>>> +        amb,div-width = <24>;
>>> +        amb,div-shift = <0>;
>>> +      };
>>> diff --git a/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml b/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
>>> new file mode 100644
>>> index 000000000000..65c1feb60041
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
>>> @@ -0,0 +1,59 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/clock/ambarella,pll-clock.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Ambarella PLL Clock
>>> +
>>> +maintainers:
>>> +  - Li Chen <lchen@ambarella.com>
>>> +
>>> +properties:
>>> +  compatible:
>>> +    enum:
>>> +      - ambarella,pll-clock
>>> +      - ambarella,clkpll-v0
>>> +
>>> +if:
>>
>> No, this does not work like that. It sits under "allOf", located after
>> "required:".
> 
> Thanks, I will learn "allOf" and use it in v2. BTW, we use the two compatibles as below:
> clocks {
>                 compatible = "ambarella,clkpll-v0";

Nope.

>                 ...
>                 gclk_core: gclk-core {
>                         #clock-cells = <0>;
>                         compatible = "ambarella,pll-clock";

Also nope.

>                         clocks = <&osc>;
>                         clock-output-names = "gclk_core";
>                         amb,clk-regmap = <&rct_syscon 0x000 0x004 0x100 0x104 0x000 0x000>;

Nope, nope, nope.

You need proper clock-controller with its own MMIO address space.

>                 };
>                 ...
> }
> 
> I'm not sure can I describe the two compatibles in this single yaml, can you give some advice? thanks!

There are plenty of examples, including example-schema.

Best regards,
Krzysztof

Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Krzysztof Kozlowski]

On 25/01/2023 10:28, Li Chen wrote:
> 
> Hi Krzysztof,
> 
> Sorry for my late reply.
> 
> On Mon, 23 Jan 2023 16:11:08 +0800,
> Krzysztof Kozlowski wrote:
>>
>> On 23/01/2023 08:32, Li Chen wrote:
>>> This patch introduce clock bindings for Ambarella.
>>>
>>> Signed-off-by: Li Chen <lchen@ambarella.com>
>>> Change-Id: I29018a23ed3a5b79a1103e859a5c7ed7bb83a261
>>
>> All the same problems plus new:
>>
>> Subject: drop second/last, redundant "bindings". The "dt-bindings"
>> prefix is already stating that these are bindings.
> 
> Well noted.
> 
>>> ---
>>>  .../clock/ambarella,composite-clock.yaml      | 52 ++++++++++++++++
>>>  .../bindings/clock/ambarella,pll-clock.yaml   | 59 +++++++++++++++++++
>>>  MAINTAINERS                                   |  2 +
>>>  3 files changed, 113 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
>>>  create mode 100644 Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml b/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
>>> new file mode 100644
>>> index 000000000000..fac1cb9379c4
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
>>> @@ -0,0 +1,52 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/clock/ambarella,composite-clock.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Ambarella Composite Clock
>>> +
>>> +maintainers:
>>> +  - Li Chen <lchen@ambarella.com>
>>> +
>>
>> Missing description.
> 
> Thanks, description as below will be added in v2:
> 
> "Ambarella SoCs integrates some composite clocks, like uart0, which aggrate the functionality
> of the basic clock types, like mux and div."
> 
>>> +properties:
>>> +  compatible:
>>> +    items:
>>
>> Drop items.
> 
> Ok.
> 
>>> +      - const: ambarella,composite-clock
>>
>> Missing SoC specific compatible. This is anyway not really correct
>> compatible...
> 
> Most Ambarella's compatibles don't contain SoC name, because we prefer
> to use syscon + offsets in dts to tell driver the correct register offsets, or
> ues struct soc_device and SoC identity stores in a given physical address.

That's not correct hardware description. Drop the syscon and offsets.

> 
> So compatibles like "ambarella,composite-clock" and "ambarella,pinctrl" are
> used widely in Ambarella kernels. 

What do you do downstream does not matter. You can invent any crazy idea
and it is not an argument that it should be done like that. Usually
downstream code is incorrect...

> Feel free to correct me if you think this
> is not a good idea.

This is bad idea. Compatibles should be specific. Devices should not use
syscons to poke other registers, unless strictly necessary, but have
strictly defined MMIO address space and use it.

> 
>>> +
>>> +  clocks: true
>>
>> No, needs constraints.
> 
> Ok. I will list all clocks name
> 
>>> +  assigned-clocks: true
>>> +  assigned-clock-parents: true
>>> +  assigned-clock-rates: true
>>
>> Drop these three.
> 
> Ok
> 
>>> +  clock-output-names: true
>>
>> Missing constraints.
> 
> Ok, I will add "maxItems: 1"
> 
>>> +  amb,mux-regmap: true
>>
>> NAK.
>>
>> It's enough. The patches have very, very poor quality.
>>
>> Missing description, missing type/$ref, wrong prefix.
> 
> Sorry, I forget to run dt_binding_check, I will spend some
> time learning the binding and check, sorry for it.
> 
>>> +  amb,div-regmap: true
>>> +  amb,div-width: true
>>> +  amb,div-shift: true
>>
>> These two are arguments to phandle.
> 
> I will add description and $ref to regmap and width/shift.

Drop all these syscon properties.

> 
>>> +
>>> +  '#clock-cells':
>>> +    const: 0
>>> +
>>> +required:
>>> +  - compatible
>>> +  - reg
>>> +  - clocks
>>> +  - '#clock-cells'
>>> +
>>> +additionalProperties: false
>>
>> So why you decided to add it here and not in other places?
> 
> I didn't understand it well. I will add it to other places in v2,
> thanks for pointint out it.
> 
>>> +
>>> +examples:
>>> +  - |
>>> +      gclk_uart0: gclk-uart0 {
>>
>> Wrong indentation.
> 
> Well noted.
> 
>>> +        #clock-cells = <0>;
>>> +        compatible = "ambarella,composite-clock";
>>> +        clocks = <&osc>, <&gclk_core>, <&pll_out_enet>, <&pll_out_sd>;
>>> +        clock-output-names = "gclk_uart0";
>>> +        assigned-clocks = <&gclk_uart0>;
>>> +        assigned-clock-parents = <&osc>;
>>> +        assigned-clock-rates = <24000000>;
>>> +        amb,mux-regmap = <&rct_syscon 0x1c8>;
>>> +        amb,div-regmap = <&rct_syscon 0x038>;
>>> +        amb,div-width = <24>;
>>> +        amb,div-shift = <0>;
>>> +      };
>>> diff --git a/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml b/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
>>> new file mode 100644
>>> index 000000000000..65c1feb60041
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
>>> @@ -0,0 +1,59 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/clock/ambarella,pll-clock.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Ambarella PLL Clock
>>> +
>>> +maintainers:
>>> +  - Li Chen <lchen@ambarella.com>
>>> +
>>> +properties:
>>> +  compatible:
>>> +    enum:
>>> +      - ambarella,pll-clock
>>> +      - ambarella,clkpll-v0
>>> +
>>> +if:
>>
>> No, this does not work like that. It sits under "allOf", located after
>> "required:".
> 
> Thanks, I will learn "allOf" and use it in v2. BTW, we use the two compatibles as below:
> clocks {
>                 compatible = "ambarella,clkpll-v0";

Nope.

>                 ...
>                 gclk_core: gclk-core {
>                         #clock-cells = <0>;
>                         compatible = "ambarella,pll-clock";

Also nope.

>                         clocks = <&osc>;
>                         clock-output-names = "gclk_core";
>                         amb,clk-regmap = <&rct_syscon 0x000 0x004 0x100 0x104 0x000 0x000>;

Nope, nope, nope.

You need proper clock-controller with its own MMIO address space.

>                 };
>                 ...
> }
> 
> I'm not sure can I describe the two compatibles in this single yaml, can you give some advice? thanks!

There are plenty of examples, including example-schema.

Best regards,
Krzysztof


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Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Li Chen]

On Wed, 25 Jan 2023 17:55:34 +0800,
Hi Krzysztof,

Krzysztof Kozlowski wrote:
>
> On 25/01/2023 10:28, Li Chen wrote:
> >
> > Hi Krzysztof,
> >
> > Sorry for my late reply.
> >
> > On Mon, 23 Jan 2023 16:11:08 +0800,
> > Krzysztof Kozlowski wrote:
> >>
> >> On 23/01/2023 08:32, Li Chen wrote:
> >>> This patch introduce clock bindings for Ambarella.
> >>>
> >>> Signed-off-by: Li Chen <lchen@ambarella.com>
> >>> Change-Id: I29018a23ed3a5b79a1103e859a5c7ed7bb83a261
> >>
> >> All the same problems plus new:
> >>
> >> Subject: drop second/last, redundant "bindings". The "dt-bindings"
> >> prefix is already stating that these are bindings.
> >
> > Well noted.
> >
> >>> ---
> >>>  .../clock/ambarella,composite-clock.yaml      | 52 ++++++++++++++++
> >>>  .../bindings/clock/ambarella,pll-clock.yaml   | 59 +++++++++++++++++++
> >>>  MAINTAINERS                                   |  2 +
> >>>  3 files changed, 113 insertions(+)
> >>>  create mode 100644 Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
> >>>  create mode 100644 Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml b/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
> >>> new file mode 100644
> >>> index 000000000000..fac1cb9379c4
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
> >>> @@ -0,0 +1,52 @@
> >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >>> +%YAML 1.2
> >>> +---
> >>> +$id: http://devicetree.org/schemas/clock/ambarella,composite-clock.yaml#
> >>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>> +
> >>> +title: Ambarella Composite Clock
> >>> +
> >>> +maintainers:
> >>> +  - Li Chen <lchen@ambarella.com>
> >>> +
> >>
> >> Missing description.
> >
> > Thanks, description as below will be added in v2:
> >
> > "Ambarella SoCs integrates some composite clocks, like uart0, which aggrate the functionality
> > of the basic clock types, like mux and div."
> >
> >>> +properties:
> >>> +  compatible:
> >>> +    items:
> >>
> >> Drop items.
> >
> > Ok.
> >
> >>> +      - const: ambarella,composite-clock
> >>
> >> Missing SoC specific compatible. This is anyway not really correct
> >> compatible...
> >
> > Most Ambarella's compatibles don't contain SoC name, because we prefer
> > to use syscon + offsets in dts to tell driver the correct register offsets, or
> > ues struct soc_device and SoC identity stores in a given physical address.
>
> That's not correct hardware description. Drop the syscon and offsets.

Ok.

> > 
> > So compatibles like "ambarella,composite-clock" and "ambarella,pinctrl" are
> > used widely in Ambarella kernels.
>
> What do you do downstream does not matter. You can invent any crazy idea
> and it is not an argument that it should be done like that. Usually
> downstream code is incorrect...

Yeah, I understand it.
I really hope to learn the standard/right ways and
I am very grateful for your careful reviews.

> > Feel free to correct me if you think this
> > is not a good idea.
>
> This is bad idea. Compatibles should be specific. Devices should not use
> syscons to poke other registers, unless strictly necessary, but have
> strictly defined MMIO address space and use it.

Ok, I will convert syscon-based regmaps to SoC-specific compatibles and of_device_id->data.

But I have three questions:

0. why syscon + offsets is a bad idea copared to specific compatibles?
1. when would it be a good idea to use syscon in device tree?
2. syscon VS reg, which is preferred in device tree?

Thanks in advanced.

> >
> >>> +
> >>> +  clocks: true
> >>
> >> No, needs constraints.
> >
> > Ok. I will list all clocks name
> >
> >>> +  assigned-clocks: true
> >>> +  assigned-clock-parents: true
> >>> +  assigned-clock-rates: true
> >>
> >> Drop these three.
> >
> > Ok
> >
> >>> +  clock-output-names: true
> >>
> >> Missing constraints.
> >
> > Ok, I will add "maxItems: 1"
> >
> >>> +  amb,mux-regmap: true
> >>
> >> NAK.
> >>
> >> It's enough. The patches have very, very poor quality.
> >>
> >> Missing description, missing type/$ref, wrong prefix.
> >
> > Sorry, I forget to run dt_binding_check, I will spend some
> > time learning the binding and check, sorry for it.
> >
> >>> +  amb,div-regmap: true
> >>> +  amb,div-width: true
> >>> +  amb,div-shift: true
> >>
> >> These two are arguments to phandle.
> >
> > I will add description and $ref to regmap and width/shift.
>
> Drop all these syscon properties.

Ok, so I should replace these regmaps with reg, right?

> >
> >>> +
> >>> +  '#clock-cells':
> >>> +    const: 0
> >>> +
> >>> +required:
> >>> +  - compatible
> >>> +  - reg
> >>> +  - clocks
> >>> +  - '#clock-cells'
> >>> +
> >>> +additionalProperties: false
> >>
> >> So why you decided to add it here and not in other places?
> >
> > I didn't understand it well. I will add it to other places in v2,
> > thanks for pointint out it.
> >
> >>> +
> >>> +examples:
> >>> +  - |
> >>> +      gclk_uart0: gclk-uart0 {
> >>
> >> Wrong indentation.
> >
> > Well noted.
> >
> >>> +        #clock-cells = <0>;
> >>> +        compatible = "ambarella,composite-clock";
> >>> +        clocks = <&osc>, <&gclk_core>, <&pll_out_enet>, <&pll_out_sd>;
> >>> +        clock-output-names = "gclk_uart0";
> >>> +        assigned-clocks = <&gclk_uart0>;
> >>> +        assigned-clock-parents = <&osc>;
> >>> +        assigned-clock-rates = <24000000>;
> >>> +        amb,mux-regmap = <&rct_syscon 0x1c8>;
> >>> +        amb,div-regmap = <&rct_syscon 0x038>;
> >>> +        amb,div-width = <24>;
> >>> +        amb,div-shift = <0>;
> >>> +      };
> >>> diff --git a/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml b/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
> >>> new file mode 100644
> >>> index 000000000000..65c1feb60041
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
> >>> @@ -0,0 +1,59 @@
> >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >>> +%YAML 1.2
> >>> +---
> >>> +$id: http://devicetree.org/schemas/clock/ambarella,pll-clock.yaml#
> >>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>> +
> >>> +title: Ambarella PLL Clock
> >>> +
> >>> +maintainers:
> >>> +  - Li Chen <lchen@ambarella.com>
> >>> +
> >>> +properties:
> >>> +  compatible:
> >>> +    enum:
> >>> +      - ambarella,pll-clock
> >>> +      - ambarella,clkpll-v0
> >>> +
> >>> +if:
> >>
> >> No, this does not work like that. It sits under "allOf", located after
> >> "required:".
> >
> > Thanks, I will learn "allOf" and use it in v2. BTW, we use the two compatibles as below:
> > clocks {
> >                 compatible = "ambarella,clkpll-v0";
>
> Nope.
>
> >                 ...
> >                 gclk_core: gclk-core {
> >                         #clock-cells = <0>;
> >                         compatible = "ambarella,pll-clock";
>
> Also nope.
>
> >                         clocks = <&osc>;
> >                         clock-output-names = "gclk_core";
> >                         amb,clk-regmap = <&rct_syscon 0x000 0x004 0x100 0x104 0x000 0x000>;
>
> Nope, nope, nope.
>
> You need proper clock-controller with its own MMIO address space.
>
> >                 };
> >                 ...
> > }
> >
> > I'm not sure can I describe the two compatibles in this single yaml, can you give some advice? thanks!
>
> There are plenty of examples, including example-schema.

Ok, I will learn more and fix it.

Regards,
Li

Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Li Chen]

On Wed, 25 Jan 2023 17:55:34 +0800,
Hi Krzysztof,

Krzysztof Kozlowski wrote:
>
> On 25/01/2023 10:28, Li Chen wrote:
> >
> > Hi Krzysztof,
> >
> > Sorry for my late reply.
> >
> > On Mon, 23 Jan 2023 16:11:08 +0800,
> > Krzysztof Kozlowski wrote:
> >>
> >> On 23/01/2023 08:32, Li Chen wrote:
> >>> This patch introduce clock bindings for Ambarella.
> >>>
> >>> Signed-off-by: Li Chen <lchen@ambarella.com>
> >>> Change-Id: I29018a23ed3a5b79a1103e859a5c7ed7bb83a261
> >>
> >> All the same problems plus new:
> >>
> >> Subject: drop second/last, redundant "bindings". The "dt-bindings"
> >> prefix is already stating that these are bindings.
> >
> > Well noted.
> >
> >>> ---
> >>>  .../clock/ambarella,composite-clock.yaml      | 52 ++++++++++++++++
> >>>  .../bindings/clock/ambarella,pll-clock.yaml   | 59 +++++++++++++++++++
> >>>  MAINTAINERS                                   |  2 +
> >>>  3 files changed, 113 insertions(+)
> >>>  create mode 100644 Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
> >>>  create mode 100644 Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml b/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
> >>> new file mode 100644
> >>> index 000000000000..fac1cb9379c4
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/clock/ambarella,composite-clock.yaml
> >>> @@ -0,0 +1,52 @@
> >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >>> +%YAML 1.2
> >>> +---
> >>> +$id: http://devicetree.org/schemas/clock/ambarella,composite-clock.yaml#
> >>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>> +
> >>> +title: Ambarella Composite Clock
> >>> +
> >>> +maintainers:
> >>> +  - Li Chen <lchen@ambarella.com>
> >>> +
> >>
> >> Missing description.
> >
> > Thanks, description as below will be added in v2:
> >
> > "Ambarella SoCs integrates some composite clocks, like uart0, which aggrate the functionality
> > of the basic clock types, like mux and div."
> >
> >>> +properties:
> >>> +  compatible:
> >>> +    items:
> >>
> >> Drop items.
> >
> > Ok.
> >
> >>> +      - const: ambarella,composite-clock
> >>
> >> Missing SoC specific compatible. This is anyway not really correct
> >> compatible...
> >
> > Most Ambarella's compatibles don't contain SoC name, because we prefer
> > to use syscon + offsets in dts to tell driver the correct register offsets, or
> > ues struct soc_device and SoC identity stores in a given physical address.
>
> That's not correct hardware description. Drop the syscon and offsets.

Ok.

> > 
> > So compatibles like "ambarella,composite-clock" and "ambarella,pinctrl" are
> > used widely in Ambarella kernels.
>
> What do you do downstream does not matter. You can invent any crazy idea
> and it is not an argument that it should be done like that. Usually
> downstream code is incorrect...

Yeah, I understand it.
I really hope to learn the standard/right ways and
I am very grateful for your careful reviews.

> > Feel free to correct me if you think this
> > is not a good idea.
>
> This is bad idea. Compatibles should be specific. Devices should not use
> syscons to poke other registers, unless strictly necessary, but have
> strictly defined MMIO address space and use it.

Ok, I will convert syscon-based regmaps to SoC-specific compatibles and of_device_id->data.

But I have three questions:

0. why syscon + offsets is a bad idea copared to specific compatibles?
1. when would it be a good idea to use syscon in device tree?
2. syscon VS reg, which is preferred in device tree?

Thanks in advanced.

> >
> >>> +
> >>> +  clocks: true
> >>
> >> No, needs constraints.
> >
> > Ok. I will list all clocks name
> >
> >>> +  assigned-clocks: true
> >>> +  assigned-clock-parents: true
> >>> +  assigned-clock-rates: true
> >>
> >> Drop these three.
> >
> > Ok
> >
> >>> +  clock-output-names: true
> >>
> >> Missing constraints.
> >
> > Ok, I will add "maxItems: 1"
> >
> >>> +  amb,mux-regmap: true
> >>
> >> NAK.
> >>
> >> It's enough. The patches have very, very poor quality.
> >>
> >> Missing description, missing type/$ref, wrong prefix.
> >
> > Sorry, I forget to run dt_binding_check, I will spend some
> > time learning the binding and check, sorry for it.
> >
> >>> +  amb,div-regmap: true
> >>> +  amb,div-width: true
> >>> +  amb,div-shift: true
> >>
> >> These two are arguments to phandle.
> >
> > I will add description and $ref to regmap and width/shift.
>
> Drop all these syscon properties.

Ok, so I should replace these regmaps with reg, right?

> >
> >>> +
> >>> +  '#clock-cells':
> >>> +    const: 0
> >>> +
> >>> +required:
> >>> +  - compatible
> >>> +  - reg
> >>> +  - clocks
> >>> +  - '#clock-cells'
> >>> +
> >>> +additionalProperties: false
> >>
> >> So why you decided to add it here and not in other places?
> >
> > I didn't understand it well. I will add it to other places in v2,
> > thanks for pointint out it.
> >
> >>> +
> >>> +examples:
> >>> +  - |
> >>> +      gclk_uart0: gclk-uart0 {
> >>
> >> Wrong indentation.
> >
> > Well noted.
> >
> >>> +        #clock-cells = <0>;
> >>> +        compatible = "ambarella,composite-clock";
> >>> +        clocks = <&osc>, <&gclk_core>, <&pll_out_enet>, <&pll_out_sd>;
> >>> +        clock-output-names = "gclk_uart0";
> >>> +        assigned-clocks = <&gclk_uart0>;
> >>> +        assigned-clock-parents = <&osc>;
> >>> +        assigned-clock-rates = <24000000>;
> >>> +        amb,mux-regmap = <&rct_syscon 0x1c8>;
> >>> +        amb,div-regmap = <&rct_syscon 0x038>;
> >>> +        amb,div-width = <24>;
> >>> +        amb,div-shift = <0>;
> >>> +      };
> >>> diff --git a/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml b/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
> >>> new file mode 100644
> >>> index 000000000000..65c1feb60041
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/clock/ambarella,pll-clock.yaml
> >>> @@ -0,0 +1,59 @@
> >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >>> +%YAML 1.2
> >>> +---
> >>> +$id: http://devicetree.org/schemas/clock/ambarella,pll-clock.yaml#
> >>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >>> +
> >>> +title: Ambarella PLL Clock
> >>> +
> >>> +maintainers:
> >>> +  - Li Chen <lchen@ambarella.com>
> >>> +
> >>> +properties:
> >>> +  compatible:
> >>> +    enum:
> >>> +      - ambarella,pll-clock
> >>> +      - ambarella,clkpll-v0
> >>> +
> >>> +if:
> >>
> >> No, this does not work like that. It sits under "allOf", located after
> >> "required:".
> >
> > Thanks, I will learn "allOf" and use it in v2. BTW, we use the two compatibles as below:
> > clocks {
> >                 compatible = "ambarella,clkpll-v0";
>
> Nope.
>
> >                 ...
> >                 gclk_core: gclk-core {
> >                         #clock-cells = <0>;
> >                         compatible = "ambarella,pll-clock";
>
> Also nope.
>
> >                         clocks = <&osc>;
> >                         clock-output-names = "gclk_core";
> >                         amb,clk-regmap = <&rct_syscon 0x000 0x004 0x100 0x104 0x000 0x000>;
>
> Nope, nope, nope.
>
> You need proper clock-controller with its own MMIO address space.
>
> >                 };
> >                 ...
> > }
> >
> > I'm not sure can I describe the two compatibles in this single yaml, can you give some advice? thanks!
>
> There are plenty of examples, including example-schema.

Ok, I will learn more and fix it.

Regards,
Li

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Krzysztof Kozlowski]

On 25/01/2023 13:06, Li Chen wrote:
>>> Feel free to correct me if you think this
>>> is not a good idea.
>>
>> This is bad idea. Compatibles should be specific. Devices should not use
>> syscons to poke other registers, unless strictly necessary, but have
>> strictly defined MMIO address space and use it.
> 
> Ok, I will convert syscon-based regmaps to SoC-specific compatibles and of_device_id->data.
> 
> But I have three questions:
> 
> 0. why syscon + offsets is a bad idea copared to specific compatibles?

Specific compatibles are a requirement. They are needed to match device
in exact way, not some generic and unspecific. The same with every other
interface, it must be specific to allow only correct usage.

It's of course different with generic fallbacks, but we do not talk
about them here...

> 1. when would it be a good idea to use syscon in device tree?

When your device needs to poke one or few registers from some
system-controller block.

> 2. syscon VS reg, which is preferred in device tree?

There is no such choice. Your DTS *must* describe the hardware. The
hardware description is for example clock controller which has its own
address space. If you now do not add clock controller's address space to
the clock controller, it is not a proper hardware description. The same
with every other property. If your device has interrupts, but you do not
add them, it is not correct description.

Best regards,
Krzysztof

Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Krzysztof Kozlowski]

On 25/01/2023 13:06, Li Chen wrote:
>>> Feel free to correct me if you think this
>>> is not a good idea.
>>
>> This is bad idea. Compatibles should be specific. Devices should not use
>> syscons to poke other registers, unless strictly necessary, but have
>> strictly defined MMIO address space and use it.
> 
> Ok, I will convert syscon-based regmaps to SoC-specific compatibles and of_device_id->data.
> 
> But I have three questions:
> 
> 0. why syscon + offsets is a bad idea copared to specific compatibles?

Specific compatibles are a requirement. They are needed to match device
in exact way, not some generic and unspecific. The same with every other
interface, it must be specific to allow only correct usage.

It's of course different with generic fallbacks, but we do not talk
about them here...

> 1. when would it be a good idea to use syscon in device tree?

When your device needs to poke one or few registers from some
system-controller block.

> 2. syscon VS reg, which is preferred in device tree?

There is no such choice. Your DTS *must* describe the hardware. The
hardware description is for example clock controller which has its own
address space. If you now do not add clock controller's address space to
the clock controller, it is not a proper hardware description. The same
with every other property. If your device has interrupts, but you do not
add them, it is not correct description.

Best regards,
Krzysztof


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Li Chen]

On Wed, 25 Jan 2023 20:14:16 +0800,

Hi Krzysztof,

Krzysztof Kozlowski wrote:
>
> On 25/01/2023 13:06, Li Chen wrote:
> >>> Feel free to correct me if you think this
> >>> is not a good idea.
> >>
> >> This is bad idea. Compatibles should be specific. Devices should not use
> >> syscons to poke other registers, unless strictly necessary, but have
> >> strictly defined MMIO address space and use it.
> >
> > Ok, I will convert syscon-based regmaps to SoC-specific compatibles and of_device_id->data.
> >
> > But I have three questions:
> >
> > 0. why syscon + offsets is a bad idea copared to specific compatibles?
>
> Specific compatibles are a requirement. They are needed to match device
> in exact way, not some generic and unspecific. The same with every other
> interface, it must be specific to allow only correct usage.
>
> It's of course different with generic fallbacks, but we do not talk
> about them here...
>
> > 1. when would it be a good idea to use syscon in device tree?
>
> When your device needs to poke one or few registers from some
> system-controller block.
>
> > 2. syscon VS reg, which is preferred in device tree?
>
> There is no such choice. Your DTS *must* describe the hardware. The
> hardware description is for example clock controller which has its own
> address space. If you now do not add clock controller's address space to
> the clock controller, it is not a proper hardware description. The same
> with every other property. If your device has interrupts, but you do not
> add them, it is not correct description.

Got it. But Ambarella hardware design is kind of strange. I want to add mroe
expalaination about why Ambarella's downstream kernel
use so much syscon in device trees:

For most SoCs from other vendors, they have seperate address space regions
for different peripherals, like
axi address space A: ENET
axi address space B: PCIe
axi address space B: USB
...

Ambarella is somewhat **different**, its SoCs have two system controllers regions:
RCT and scratchpad, take RCT for example:
"The S6LM system software
interacts with PLLs, PHYs and several other low-level hardware blocks using APB reset clock and test (RCT)
registers with a system-layer application programming interface (API).
This includes the setting of clock frequencies."

There are so many peripherals registers located inside RCT and scratchpad
(like usb/phy, gpio, sd, dac, enet, rng), and some peripherals even have no their
own modules for register definitions.

So most time(for a peripheral driver), the only differences between different
Ambarella SoCs are just the syscon(rct or scratchpad) offsets get changed.

I don't think such lazy hardware design is common in vendors other than ambarella.

If I switch to SoC-specific compatibles, and remove these syscon from device tree,
of_device_id->data may only contain system controller(rct or scratchpad) offset for many Ambarella drivers,
and ioremap/devm_ioremap carefully.

The question is: can upstream kernel accept such codes?

If yes, I will switch to SoC-specific compatibles and remove syscon without hesitation.

Regards,
Li

Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Li Chen]

On Wed, 25 Jan 2023 20:14:16 +0800,

Hi Krzysztof,

Krzysztof Kozlowski wrote:
>
> On 25/01/2023 13:06, Li Chen wrote:
> >>> Feel free to correct me if you think this
> >>> is not a good idea.
> >>
> >> This is bad idea. Compatibles should be specific. Devices should not use
> >> syscons to poke other registers, unless strictly necessary, but have
> >> strictly defined MMIO address space and use it.
> >
> > Ok, I will convert syscon-based regmaps to SoC-specific compatibles and of_device_id->data.
> >
> > But I have three questions:
> >
> > 0. why syscon + offsets is a bad idea copared to specific compatibles?
>
> Specific compatibles are a requirement. They are needed to match device
> in exact way, not some generic and unspecific. The same with every other
> interface, it must be specific to allow only correct usage.
>
> It's of course different with generic fallbacks, but we do not talk
> about them here...
>
> > 1. when would it be a good idea to use syscon in device tree?
>
> When your device needs to poke one or few registers from some
> system-controller block.
>
> > 2. syscon VS reg, which is preferred in device tree?
>
> There is no such choice. Your DTS *must* describe the hardware. The
> hardware description is for example clock controller which has its own
> address space. If you now do not add clock controller's address space to
> the clock controller, it is not a proper hardware description. The same
> with every other property. If your device has interrupts, but you do not
> add them, it is not correct description.

Got it. But Ambarella hardware design is kind of strange. I want to add mroe
expalaination about why Ambarella's downstream kernel
use so much syscon in device trees:

For most SoCs from other vendors, they have seperate address space regions
for different peripherals, like
axi address space A: ENET
axi address space B: PCIe
axi address space B: USB
...

Ambarella is somewhat **different**, its SoCs have two system controllers regions:
RCT and scratchpad, take RCT for example:
"The S6LM system software
interacts with PLLs, PHYs and several other low-level hardware blocks using APB reset clock and test (RCT)
registers with a system-layer application programming interface (API).
This includes the setting of clock frequencies."

There are so many peripherals registers located inside RCT and scratchpad
(like usb/phy, gpio, sd, dac, enet, rng), and some peripherals even have no their
own modules for register definitions.

So most time(for a peripheral driver), the only differences between different
Ambarella SoCs are just the syscon(rct or scratchpad) offsets get changed.

I don't think such lazy hardware design is common in vendors other than ambarella.

If I switch to SoC-specific compatibles, and remove these syscon from device tree,
of_device_id->data may only contain system controller(rct or scratchpad) offset for many Ambarella drivers,
and ioremap/devm_ioremap carefully.

The question is: can upstream kernel accept such codes?

If yes, I will switch to SoC-specific compatibles and remove syscon without hesitation.

Regards,
Li

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Krzysztof Kozlowski]

On 25/01/2023 14:40, Li Chen wrote:
> On Wed, 25 Jan 2023 20:14:16 +0800,
> 
> Hi Krzysztof,
> 
> Krzysztof Kozlowski wrote:
>>
>> On 25/01/2023 13:06, Li Chen wrote:
>>>>> Feel free to correct me if you think this
>>>>> is not a good idea.
>>>>
>>>> This is bad idea. Compatibles should be specific. Devices should not use
>>>> syscons to poke other registers, unless strictly necessary, but have
>>>> strictly defined MMIO address space and use it.
>>>
>>> Ok, I will convert syscon-based regmaps to SoC-specific compatibles and of_device_id->data.
>>>
>>> But I have three questions:
>>>
>>> 0. why syscon + offsets is a bad idea copared to specific compatibles?
>>
>> Specific compatibles are a requirement. They are needed to match device
>> in exact way, not some generic and unspecific. The same with every other
>> interface, it must be specific to allow only correct usage.
>>
>> It's of course different with generic fallbacks, but we do not talk
>> about them here...
>>
>>> 1. when would it be a good idea to use syscon in device tree?
>>
>> When your device needs to poke one or few registers from some
>> system-controller block.
>>
>>> 2. syscon VS reg, which is preferred in device tree?
>>
>> There is no such choice. Your DTS *must* describe the hardware. The
>> hardware description is for example clock controller which has its own
>> address space. If you now do not add clock controller's address space to
>> the clock controller, it is not a proper hardware description. The same
>> with every other property. If your device has interrupts, but you do not
>> add them, it is not correct description.
> 
> Got it. But Ambarella hardware design is kind of strange. I want to add mroe
> expalaination about why Ambarella's downstream kernel
> use so much syscon in device trees:
> 
> For most SoCs from other vendors, they have seperate address space regions
> for different peripherals, like
> axi address space A: ENET
> axi address space B: PCIe
> axi address space B: USB
> ...
> 
> Ambarella is somewhat **different**, its SoCs have two system controllers regions:
> RCT and scratchpad, take RCT for example:
> "The S6LM system software
> interacts with PLLs, PHYs and several other low-level hardware blocks using APB reset clock and test (RCT)
> registers with a system-layer application programming interface (API).
> This includes the setting of clock frequencies."
> 
> There are so many peripherals registers located inside RCT and scratchpad
> (like usb/phy, gpio, sd, dac, enet, rng), and some peripherals even have no their
> own modules for register definitions.

Then the syscon is the parent device of these peripherals and clocks.
You did not represent them as children but as siblings which does not
look correct.

> 
> So most time(for a peripheral driver), the only differences between different
> Ambarella SoCs are just the syscon(rct or scratchpad) offsets get changed.
> 
> I don't think such lazy hardware design is common in vendors other than ambarella.
> 
> If I switch to SoC-specific compatibles, 

This is independent topic. SoC-specific compatibles are a requirement
but it does not affect your device hierarchy.

> and remove these syscon from device tree,
> of_device_id->data may only contain system controller(rct or scratchpad) offset for many Ambarella drivers,
> and ioremap/devm_ioremap carefully.

I don't understand the problem. Neither the solution.

> 
> The question is: can upstream kernel accept such codes?
> 
> If yes, I will switch to SoC-specific compatibles and remove syscon without hesitation.

Sorry, none of your explanations here match your DTS. Your DTS clearly
models (for some reason there is no soc which makes even bigger confusion):

rct_syscon
clocks
 |-gclk-core
 |-gclk-ddr

but what you are saying is that there is no separate clock controller
device with its own IO address but these clocks are part of rct_syscon.
Then model it that way in DTS. The rct_syscon is then your clock
controller and all these fake gclk-core and gclk-ddr nodes should be gone.

Best regards,
Krzysztof

Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Krzysztof Kozlowski]

On 25/01/2023 14:40, Li Chen wrote:
> On Wed, 25 Jan 2023 20:14:16 +0800,
> 
> Hi Krzysztof,
> 
> Krzysztof Kozlowski wrote:
>>
>> On 25/01/2023 13:06, Li Chen wrote:
>>>>> Feel free to correct me if you think this
>>>>> is not a good idea.
>>>>
>>>> This is bad idea. Compatibles should be specific. Devices should not use
>>>> syscons to poke other registers, unless strictly necessary, but have
>>>> strictly defined MMIO address space and use it.
>>>
>>> Ok, I will convert syscon-based regmaps to SoC-specific compatibles and of_device_id->data.
>>>
>>> But I have three questions:
>>>
>>> 0. why syscon + offsets is a bad idea copared to specific compatibles?
>>
>> Specific compatibles are a requirement. They are needed to match device
>> in exact way, not some generic and unspecific. The same with every other
>> interface, it must be specific to allow only correct usage.
>>
>> It's of course different with generic fallbacks, but we do not talk
>> about them here...
>>
>>> 1. when would it be a good idea to use syscon in device tree?
>>
>> When your device needs to poke one or few registers from some
>> system-controller block.
>>
>>> 2. syscon VS reg, which is preferred in device tree?
>>
>> There is no such choice. Your DTS *must* describe the hardware. The
>> hardware description is for example clock controller which has its own
>> address space. If you now do not add clock controller's address space to
>> the clock controller, it is not a proper hardware description. The same
>> with every other property. If your device has interrupts, but you do not
>> add them, it is not correct description.
> 
> Got it. But Ambarella hardware design is kind of strange. I want to add mroe
> expalaination about why Ambarella's downstream kernel
> use so much syscon in device trees:
> 
> For most SoCs from other vendors, they have seperate address space regions
> for different peripherals, like
> axi address space A: ENET
> axi address space B: PCIe
> axi address space B: USB
> ...
> 
> Ambarella is somewhat **different**, its SoCs have two system controllers regions:
> RCT and scratchpad, take RCT for example:
> "The S6LM system software
> interacts with PLLs, PHYs and several other low-level hardware blocks using APB reset clock and test (RCT)
> registers with a system-layer application programming interface (API).
> This includes the setting of clock frequencies."
> 
> There are so many peripherals registers located inside RCT and scratchpad
> (like usb/phy, gpio, sd, dac, enet, rng), and some peripherals even have no their
> own modules for register definitions.

Then the syscon is the parent device of these peripherals and clocks.
You did not represent them as children but as siblings which does not
look correct.

> 
> So most time(for a peripheral driver), the only differences between different
> Ambarella SoCs are just the syscon(rct or scratchpad) offsets get changed.
> 
> I don't think such lazy hardware design is common in vendors other than ambarella.
> 
> If I switch to SoC-specific compatibles, 

This is independent topic. SoC-specific compatibles are a requirement
but it does not affect your device hierarchy.

> and remove these syscon from device tree,
> of_device_id->data may only contain system controller(rct or scratchpad) offset for many Ambarella drivers,
> and ioremap/devm_ioremap carefully.

I don't understand the problem. Neither the solution.

> 
> The question is: can upstream kernel accept such codes?
> 
> If yes, I will switch to SoC-specific compatibles and remove syscon without hesitation.

Sorry, none of your explanations here match your DTS. Your DTS clearly
models (for some reason there is no soc which makes even bigger confusion):

rct_syscon
clocks
 |-gclk-core
 |-gclk-ddr

but what you are saying is that there is no separate clock controller
device with its own IO address but these clocks are part of rct_syscon.
Then model it that way in DTS. The rct_syscon is then your clock
controller and all these fake gclk-core and gclk-ddr nodes should be gone.

Best regards,
Krzysztof


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Li Chen]

Hi Krzysztof,
 ---- On Thu, 26 Jan 2023 19:29:05 +0800  Krzysztof Kozlowski  wrote --- 
 > On 25/01/2023 14:40, Li Chen wrote:
 > > On Wed, 25 Jan 2023 20:14:16 +0800,
 > > 
 > > Hi Krzysztof,
 > > 
 > > Krzysztof Kozlowski wrote:
 > >>
 > >> On 25/01/2023 13:06, Li Chen wrote:
 > >>>>> Feel free to correct me if you think this
 > >>>>> is not a good idea.
 > >>>>
 > >>>> This is bad idea. Compatibles should be specific. Devices should not use
 > >>>> syscons to poke other registers, unless strictly necessary, but have
 > >>>> strictly defined MMIO address space and use it.
 > >>>
 > >>> Ok, I will convert syscon-based regmaps to SoC-specific compatibles and of_device_id->data.
 > >>>
 > >>> But I have three questions:
 > >>>
 > >>> 0. why syscon + offsets is a bad idea copared to specific compatibles?
 > >>
 > >> Specific compatibles are a requirement. They are needed to match device
 > >> in exact way, not some generic and unspecific. The same with every other
 > >> interface, it must be specific to allow only correct usage.
 > >>
 > >> It's of course different with generic fallbacks, but we do not talk
 > >> about them here...
 > >>
 > >>> 1. when would it be a good idea to use syscon in device tree?
 > >>
 > >> When your device needs to poke one or few registers from some
 > >> system-controller block.
 > >>
 > >>> 2. syscon VS reg, which is preferred in device tree?
 > >>
 > >> There is no such choice. Your DTS *must* describe the hardware. The
 > >> hardware description is for example clock controller which has its own
 > >> address space. If you now do not add clock controller's address space to
 > >> the clock controller, it is not a proper hardware description. The same
 > >> with every other property. If your device has interrupts, but you do not
 > >> add them, it is not correct description.
 > > 
 > > Got it. But Ambarella hardware design is kind of strange. I want to add mroe
 > > expalaination about why Ambarella's downstream kernel
 > > use so much syscon in device trees:
 > > 
 > > For most SoCs from other vendors, they have seperate address space regions
 > > for different peripherals, like
 > > axi address space A: ENET
 > > axi address space B: PCIe
 > > axi address space B: USB
 > > ...
 > > 
 > > Ambarella is somewhat **different**, its SoCs have two system controllers regions:
 > > RCT and scratchpad, take RCT for example:
 > > "The S6LM system software
 > > interacts with PLLs, PHYs and several other low-level hardware blocks using APB reset clock and test (RCT)
 > > registers with a system-layer application programming interface (API).
 > > This includes the setting of clock frequencies."
 > > 
 > > There are so many peripherals registers located inside RCT and scratchpad
 > > (like usb/phy, gpio, sd, dac, enet, rng), and some peripherals even have no their
 > > own modules for register definitions.
 > 
 > Then the syscon is the parent device of these peripherals and clocks.
 > You did not represent them as children but as siblings which does not
 > look correct.
 
Ok, I will these syscon(RCT  and scratchpad) as the parent node of our clocks and related peripherals.

 > > 
 > > So most time(for a peripheral driver), the only differences between different
 > > Ambarella SoCs are just the syscon(rct or scratchpad) offsets get changed.
 > > 
 > > I don't think such lazy hardware design is common in vendors other than ambarella.
 > > 
 > > If I switch to SoC-specific compatibles, 
 > 
 > This is independent topic. SoC-specific compatibles are a requirement
 > but it does not affect your device hierarchy.
 
Thanks, "requirement" makes things much more clear. So I will always use SoC-specific compatibles even
if different Amarella SoCs may share the same reg offset and setting.

 > > and remove these syscon from device tree,
 > > of_device_id->data may only contain system controller(rct or scratchpad) offset for many Ambarella drivers,
 > > and ioremap/devm_ioremap carefully.
 > 
 > I don't understand the problem. Neither the solution.
 > 
 > > 
 > > The question is: can upstream kernel accept such codes?
 > > 
 > > If yes, I will switch to SoC-specific compatibles and remove syscon without hesitation.
 > 
 > Sorry, none of your explanations here match your DTS. Your DTS clearly
 > models (for some reason there is no soc which makes even bigger confusion):
 > 
 > rct_syscon
 > clocks
 >  |-gclk-core
 >  |-gclk-ddr
 > 
 > but what you are saying is that there is no separate clock controller
 > device with its own IO address but these clocks are part of rct_syscon.
 > Then model it that way in DTS. The rct_syscon is then your clock
 > controller and all these fake gclk-core and gclk-ddr nodes should be gone.

Ok, I will remove these fake nodes, and model the hardware as:

rct_syscon node
| clock node(pll, div, mux, composite  clocks live in the same driver)
| other periphal nodes

Regards,
Li

Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Li Chen]

Hi Krzysztof,
 ---- On Thu, 26 Jan 2023 19:29:05 +0800  Krzysztof Kozlowski  wrote --- 
 > On 25/01/2023 14:40, Li Chen wrote:
 > > On Wed, 25 Jan 2023 20:14:16 +0800,
 > > 
 > > Hi Krzysztof,
 > > 
 > > Krzysztof Kozlowski wrote:
 > >>
 > >> On 25/01/2023 13:06, Li Chen wrote:
 > >>>>> Feel free to correct me if you think this
 > >>>>> is not a good idea.
 > >>>>
 > >>>> This is bad idea. Compatibles should be specific. Devices should not use
 > >>>> syscons to poke other registers, unless strictly necessary, but have
 > >>>> strictly defined MMIO address space and use it.
 > >>>
 > >>> Ok, I will convert syscon-based regmaps to SoC-specific compatibles and of_device_id->data.
 > >>>
 > >>> But I have three questions:
 > >>>
 > >>> 0. why syscon + offsets is a bad idea copared to specific compatibles?
 > >>
 > >> Specific compatibles are a requirement. They are needed to match device
 > >> in exact way, not some generic and unspecific. The same with every other
 > >> interface, it must be specific to allow only correct usage.
 > >>
 > >> It's of course different with generic fallbacks, but we do not talk
 > >> about them here...
 > >>
 > >>> 1. when would it be a good idea to use syscon in device tree?
 > >>
 > >> When your device needs to poke one or few registers from some
 > >> system-controller block.
 > >>
 > >>> 2. syscon VS reg, which is preferred in device tree?
 > >>
 > >> There is no such choice. Your DTS *must* describe the hardware. The
 > >> hardware description is for example clock controller which has its own
 > >> address space. If you now do not add clock controller's address space to
 > >> the clock controller, it is not a proper hardware description. The same
 > >> with every other property. If your device has interrupts, but you do not
 > >> add them, it is not correct description.
 > > 
 > > Got it. But Ambarella hardware design is kind of strange. I want to add mroe
 > > expalaination about why Ambarella's downstream kernel
 > > use so much syscon in device trees:
 > > 
 > > For most SoCs from other vendors, they have seperate address space regions
 > > for different peripherals, like
 > > axi address space A: ENET
 > > axi address space B: PCIe
 > > axi address space B: USB
 > > ...
 > > 
 > > Ambarella is somewhat **different**, its SoCs have two system controllers regions:
 > > RCT and scratchpad, take RCT for example:
 > > "The S6LM system software
 > > interacts with PLLs, PHYs and several other low-level hardware blocks using APB reset clock and test (RCT)
 > > registers with a system-layer application programming interface (API).
 > > This includes the setting of clock frequencies."
 > > 
 > > There are so many peripherals registers located inside RCT and scratchpad
 > > (like usb/phy, gpio, sd, dac, enet, rng), and some peripherals even have no their
 > > own modules for register definitions.
 > 
 > Then the syscon is the parent device of these peripherals and clocks.
 > You did not represent them as children but as siblings which does not
 > look correct.
 
Ok, I will these syscon(RCT  and scratchpad) as the parent node of our clocks and related peripherals.

 > > 
 > > So most time(for a peripheral driver), the only differences between different
 > > Ambarella SoCs are just the syscon(rct or scratchpad) offsets get changed.
 > > 
 > > I don't think such lazy hardware design is common in vendors other than ambarella.
 > > 
 > > If I switch to SoC-specific compatibles, 
 > 
 > This is independent topic. SoC-specific compatibles are a requirement
 > but it does not affect your device hierarchy.
 
Thanks, "requirement" makes things much more clear. So I will always use SoC-specific compatibles even
if different Amarella SoCs may share the same reg offset and setting.

 > > and remove these syscon from device tree,
 > > of_device_id->data may only contain system controller(rct or scratchpad) offset for many Ambarella drivers,
 > > and ioremap/devm_ioremap carefully.
 > 
 > I don't understand the problem. Neither the solution.
 > 
 > > 
 > > The question is: can upstream kernel accept such codes?
 > > 
 > > If yes, I will switch to SoC-specific compatibles and remove syscon without hesitation.
 > 
 > Sorry, none of your explanations here match your DTS. Your DTS clearly
 > models (for some reason there is no soc which makes even bigger confusion):
 > 
 > rct_syscon
 > clocks
 >  |-gclk-core
 >  |-gclk-ddr
 > 
 > but what you are saying is that there is no separate clock controller
 > device with its own IO address but these clocks are part of rct_syscon.
 > Then model it that way in DTS. The rct_syscon is then your clock
 > controller and all these fake gclk-core and gclk-ddr nodes should be gone.

Ok, I will remove these fake nodes, and model the hardware as:

rct_syscon node
| clock node(pll, div, mux, composite  clocks live in the same driver)
| other periphal nodes

Regards,
Li

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Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Krzysztof Kozlowski]

On 27/01/2023 15:48, Li Chen wrote:
>  > 
>  > but what you are saying is that there is no separate clock controller
>  > device with its own IO address but these clocks are part of rct_syscon.
>  > Then model it that way in DTS. The rct_syscon is then your clock
>  > controller and all these fake gclk-core and gclk-ddr nodes should be gone.
> 
> Ok, I will remove these fake nodes, and model the hardware as:
> 
> rct_syscon node
> | clock node(pll, div, mux, composite  clocks live in the same driver)
> | other periphal nodes

You need clock node if it takes any resources. If it doesn't, you do not
need it.

Best regards,
Krzysztof

Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Krzysztof Kozlowski]

On 27/01/2023 15:48, Li Chen wrote:
>  > 
>  > but what you are saying is that there is no separate clock controller
>  > device with its own IO address but these clocks are part of rct_syscon.
>  > Then model it that way in DTS. The rct_syscon is then your clock
>  > controller and all these fake gclk-core and gclk-ddr nodes should be gone.
> 
> Ok, I will remove these fake nodes, and model the hardware as:
> 
> rct_syscon node
> | clock node(pll, div, mux, composite  clocks live in the same driver)
> | other periphal nodes

You need clock node if it takes any resources. If it doesn't, you do not
need it.

Best regards,
Krzysztof


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Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Li Chen]

Hi Krzysztof,

 ---- On Fri, 27 Jan 2023 23:08:09 +0800  Krzysztof Kozlowski  wrote --- 
 > On 27/01/2023 15:48, Li Chen wrote:
 > >  > 
 > >  > but what you are saying is that there is no separate clock controller
 > >  > device with its own IO address but these clocks are part of rct_syscon.
 > >  > Then model it that way in DTS. The rct_syscon is then your clock
 > >  > controller and all these fake gclk-core and gclk-ddr nodes should be gone.
 > > 
 > > Ok, I will remove these fake nodes, and model the hardware as:
 > > 
 > > rct_syscon node
 > > | clock node(pll, div, mux, composite  clocks live in the same driver)
 > > | other periphal nodes
 > 
 > You need clock node if it takes any resources. If it doesn't, you do not
 > need it.

Got it, I will model it as:

rct_syscon(compatible include "ambarella, <SoC>-clock"...)
| peripheral A
| peripheral B
| ...


One more question, two driver models:
a. compatible = "ambarella, <SoC>-clock", handle all clocks(pll, div, mux, composite) in single driver.
b. compatible = "ambarella, <SoC>-pll-clock", "ambarella, <SoC>-composite-clock", "ambarella, <SoC>-div-clock"...... 
    and implement a driver for each of them.

Which driver model is preferred?

Regards,
Li

Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Li Chen]

Hi Krzysztof,

 ---- On Fri, 27 Jan 2023 23:08:09 +0800  Krzysztof Kozlowski  wrote --- 
 > On 27/01/2023 15:48, Li Chen wrote:
 > >  > 
 > >  > but what you are saying is that there is no separate clock controller
 > >  > device with its own IO address but these clocks are part of rct_syscon.
 > >  > Then model it that way in DTS. The rct_syscon is then your clock
 > >  > controller and all these fake gclk-core and gclk-ddr nodes should be gone.
 > > 
 > > Ok, I will remove these fake nodes, and model the hardware as:
 > > 
 > > rct_syscon node
 > > | clock node(pll, div, mux, composite  clocks live in the same driver)
 > > | other periphal nodes
 > 
 > You need clock node if it takes any resources. If it doesn't, you do not
 > need it.

Got it, I will model it as:

rct_syscon(compatible include "ambarella, <SoC>-clock"...)
| peripheral A
| peripheral B
| ...


One more question, two driver models:
a. compatible = "ambarella, <SoC>-clock", handle all clocks(pll, div, mux, composite) in single driver.
b. compatible = "ambarella, <SoC>-pll-clock", "ambarella, <SoC>-composite-clock", "ambarella, <SoC>-div-clock"...... 
    and implement a driver for each of them.

Which driver model is preferred?

Regards,
Li

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Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Krzysztof Kozlowski]

On 28/01/2023 10:42, Li Chen wrote:
> Got it, I will model it as:
> 
> rct_syscon(compatible include "ambarella, <SoC>-clock"...)
> | peripheral A
> | peripheral B
> | ...
> 
> 
> One more question, two driver models:
> a. compatible = "ambarella, <SoC>-clock", handle all clocks(pll, div, mux, composite) in single driver.
> b. compatible = "ambarella, <SoC>-pll-clock", "ambarella, <SoC>-composite-clock", "ambarella, <SoC>-div-clock"...... 
>     and implement a driver for each of them.
> 
> Which driver model is preferred?

We do not talk here at all about drivers. This is independent and not
really related.

Anyway, independent features mostly have separate drivers. Each separate
driver should be located in respective subsystem. But again - we do not
talk here about drivers at all, so please do not bring them into the
problem. It will make everything more complicated...

Best regards,
Krzysztof

Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Krzysztof Kozlowski]

On 28/01/2023 10:42, Li Chen wrote:
> Got it, I will model it as:
> 
> rct_syscon(compatible include "ambarella, <SoC>-clock"...)
> | peripheral A
> | peripheral B
> | ...
> 
> 
> One more question, two driver models:
> a. compatible = "ambarella, <SoC>-clock", handle all clocks(pll, div, mux, composite) in single driver.
> b. compatible = "ambarella, <SoC>-pll-clock", "ambarella, <SoC>-composite-clock", "ambarella, <SoC>-div-clock"...... 
>     and implement a driver for each of them.
> 
> Which driver model is preferred?

We do not talk here at all about drivers. This is independent and not
really related.

Anyway, independent features mostly have separate drivers. Each separate
driver should be located in respective subsystem. But again - we do not
talk here about drivers at all, so please do not bring them into the
problem. It will make everything more complicated...

Best regards,
Krzysztof


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linux-arm-kernel@lists.infradead.org
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Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Li Chen]

Hi Krzysztof,

 ---- On Sat, 28 Jan 2023 18:08:00 +0800  Krzysztof Kozlowski  wrote --- 
 > On 28/01/2023 10:42, Li Chen wrote:
 > > Got it, I will model it as:
 > > 
 > > rct_syscon(compatible include "ambarella, -clock"...)
 > > | peripheral A
 > > | peripheral B
 > > | ...
 > > 
 > > 
 > > One more question, two driver models:
 > > a. compatible = "ambarella, -clock", handle all clocks(pll, div, mux, composite) in single driver.
 > > b. compatible = "ambarella, -pll-clock", "ambarella, -composite-clock", "ambarella, -div-clock"...... 
 > >     and implement a driver for each of them.
 > > 
 > > Which driver model is preferred?
 > 
 > We do not talk here at all about drivers. This is independent and not
 > really related.
 > 
 > Anyway, independent features mostly have separate drivers. Each separate
 > driver should be located in respective subsystem. But again - we do not
 > talk here about drivers at all, so please do not bring them into the
 > problem. It will make everything more complicated...
 
Ok, that makes sense. Sorry about that.

Regards,
Li

Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Li Chen]

Hi Krzysztof,

 ---- On Sat, 28 Jan 2023 18:08:00 +0800  Krzysztof Kozlowski  wrote --- 
 > On 28/01/2023 10:42, Li Chen wrote:
 > > Got it, I will model it as:
 > > 
 > > rct_syscon(compatible include "ambarella, -clock"...)
 > > | peripheral A
 > > | peripheral B
 > > | ...
 > > 
 > > 
 > > One more question, two driver models:
 > > a. compatible = "ambarella, -clock", handle all clocks(pll, div, mux, composite) in single driver.
 > > b. compatible = "ambarella, -pll-clock", "ambarella, -composite-clock", "ambarella, -div-clock"...... 
 > >     and implement a driver for each of them.
 > > 
 > > Which driver model is preferred?
 > 
 > We do not talk here at all about drivers. This is independent and not
 > really related.
 > 
 > Anyway, independent features mostly have separate drivers. Each separate
 > driver should be located in respective subsystem. But again - we do not
 > talk here about drivers at all, so please do not bring them into the
 > problem. It will make everything more complicated...
 
Ok, that makes sense. Sorry about that.

Regards,
Li

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Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Li Chen]

Hi Krzysztof ,

 ---- On Fri, 27 Jan 2023 23:08:09 +0800  Krzysztof Kozlowski  wrote --- 
 > On 27/01/2023 15:48, Li Chen wrote:
 > >  > 
 > >  > but what you are saying is that there is no separate clock controller
 > >  > device with its own IO address but these clocks are part of rct_syscon.
 > >  > Then model it that way in DTS. The rct_syscon is then your clock
 > >  > controller and all these fake gclk-core and gclk-ddr nodes should be gone.
 > > 
 > > Ok, I will remove these fake nodes, and model the hardware as:
 > > 
 > > rct_syscon node
 > > | clock node(pll, div, mux, composite  clocks live in the same driver)
 > > | other periphal nodes
 > 
 > You need clock node if it takes any resources. If it doesn't, you do not
 > need it.

If the only hardware resource the clock node can take is its parent clock(clocks = <&osc>;),
then can I have this clock node?

Regards,
Li

Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Li Chen]

Hi Krzysztof ,

 ---- On Fri, 27 Jan 2023 23:08:09 +0800  Krzysztof Kozlowski  wrote --- 
 > On 27/01/2023 15:48, Li Chen wrote:
 > >  > 
 > >  > but what you are saying is that there is no separate clock controller
 > >  > device with its own IO address but these clocks are part of rct_syscon.
 > >  > Then model it that way in DTS. The rct_syscon is then your clock
 > >  > controller and all these fake gclk-core and gclk-ddr nodes should be gone.
 > > 
 > > Ok, I will remove these fake nodes, and model the hardware as:
 > > 
 > > rct_syscon node
 > > | clock node(pll, div, mux, composite  clocks live in the same driver)
 > > | other periphal nodes
 > 
 > You need clock node if it takes any resources. If it doesn't, you do not
 > need it.

If the only hardware resource the clock node can take is its parent clock(clocks = <&osc>;),
then can I have this clock node?

Regards,
Li

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Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Krzysztof Kozlowski]

On 06/02/2023 12:28, Li Chen wrote:
> Hi Krzysztof ,
> 
>  ---- On Fri, 27 Jan 2023 23:08:09 +0800  Krzysztof Kozlowski  wrote --- 
>  > On 27/01/2023 15:48, Li Chen wrote:
>  > >  > 
>  > >  > but what you are saying is that there is no separate clock controller
>  > >  > device with its own IO address but these clocks are part of rct_syscon.
>  > >  > Then model it that way in DTS. The rct_syscon is then your clock
>  > >  > controller and all these fake gclk-core and gclk-ddr nodes should be gone.
>  > > 
>  > > Ok, I will remove these fake nodes, and model the hardware as:
>  > > 
>  > > rct_syscon node
>  > > | clock node(pll, div, mux, composite  clocks live in the same driver)
>  > > | other periphal nodes
>  > 
>  > You need clock node if it takes any resources. If it doesn't, you do not
>  > need it.
> 
> If the only hardware resource the clock node can take is its parent clock(clocks = <&osc>;),
> then can I have this clock node?

I am not sure if I understand. osc does not look like parent device, so
this part of comment confuses me.

Best regards,
Krzysztof

Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Krzysztof Kozlowski]

On 06/02/2023 12:28, Li Chen wrote:
> Hi Krzysztof ,
> 
>  ---- On Fri, 27 Jan 2023 23:08:09 +0800  Krzysztof Kozlowski  wrote --- 
>  > On 27/01/2023 15:48, Li Chen wrote:
>  > >  > 
>  > >  > but what you are saying is that there is no separate clock controller
>  > >  > device with its own IO address but these clocks are part of rct_syscon.
>  > >  > Then model it that way in DTS. The rct_syscon is then your clock
>  > >  > controller and all these fake gclk-core and gclk-ddr nodes should be gone.
>  > > 
>  > > Ok, I will remove these fake nodes, and model the hardware as:
>  > > 
>  > > rct_syscon node
>  > > | clock node(pll, div, mux, composite  clocks live in the same driver)
>  > > | other periphal nodes
>  > 
>  > You need clock node if it takes any resources. If it doesn't, you do not
>  > need it.
> 
> If the only hardware resource the clock node can take is its parent clock(clocks = <&osc>;),
> then can I have this clock node?

I am not sure if I understand. osc does not look like parent device, so
this part of comment confuses me.

Best regards,
Krzysztof


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Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Li Chen]

Hi Krzysztof,
 ---- On Mon, 06 Feb 2023 21:41:44 +0800  Krzysztof Kozlowski  wrote --- 
 > On 06/02/2023 12:28, Li Chen wrote:
 > > Hi Krzysztof ,
 > > 
 > >  ---- On Fri, 27 Jan 2023 23:08:09 +0800  Krzysztof Kozlowski  wrote --- 
 > >  > On 27/01/2023 15:48, Li Chen wrote:
 > >  > >  > 
 > >  > >  > but what you are saying is that there is no separate clock controller
 > >  > >  > device with its own IO address but these clocks are part of rct_syscon.
 > >  > >  > Then model it that way in DTS. The rct_syscon is then your clock
 > >  > >  > controller and all these fake gclk-core and gclk-ddr nodes should be gone.
 > >  > > 
 > >  > > Ok, I will remove these fake nodes, and model the hardware as:
 > >  > > 
 > >  > > rct_syscon node
 > >  > > | clock node(pll, div, mux, composite  clocks live in the same driver)
 > >  > > | other periphal nodes
 > >  > 
 > >  > You need clock node if it takes any resources. If it doesn't, you do not
 > >  > need it.
 > > 
 > > If the only hardware resource the clock node can take is its parent clock(clocks = &osc;),
 > > then can I have this clock node?
 > 
 > I am not sure if I understand. osc does not look like parent device, so
 > this part of comment confuses me.

Sorry for the confusion. I mean osc is the root of clock tree:

osc
  | pll A
  | pll B
  | ...

So if I have a clock node under rct_syscon node, I think it should take osc as the parent(node) clock:
rct_syscon {
    ......
    clock_controller {
          clocks = <&osc>;
          ......

You have said "You need clock node if it takes any resources. ", do you think osc here can be counted as a used resource?

Regards,
Li

Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Li Chen]

Hi Krzysztof,
 ---- On Mon, 06 Feb 2023 21:41:44 +0800  Krzysztof Kozlowski  wrote --- 
 > On 06/02/2023 12:28, Li Chen wrote:
 > > Hi Krzysztof ,
 > > 
 > >  ---- On Fri, 27 Jan 2023 23:08:09 +0800  Krzysztof Kozlowski  wrote --- 
 > >  > On 27/01/2023 15:48, Li Chen wrote:
 > >  > >  > 
 > >  > >  > but what you are saying is that there is no separate clock controller
 > >  > >  > device with its own IO address but these clocks are part of rct_syscon.
 > >  > >  > Then model it that way in DTS. The rct_syscon is then your clock
 > >  > >  > controller and all these fake gclk-core and gclk-ddr nodes should be gone.
 > >  > > 
 > >  > > Ok, I will remove these fake nodes, and model the hardware as:
 > >  > > 
 > >  > > rct_syscon node
 > >  > > | clock node(pll, div, mux, composite  clocks live in the same driver)
 > >  > > | other periphal nodes
 > >  > 
 > >  > You need clock node if it takes any resources. If it doesn't, you do not
 > >  > need it.
 > > 
 > > If the only hardware resource the clock node can take is its parent clock(clocks = &osc;),
 > > then can I have this clock node?
 > 
 > I am not sure if I understand. osc does not look like parent device, so
 > this part of comment confuses me.

Sorry for the confusion. I mean osc is the root of clock tree:

osc
  | pll A
  | pll B
  | ...

So if I have a clock node under rct_syscon node, I think it should take osc as the parent(node) clock:
rct_syscon {
    ......
    clock_controller {
          clocks = <&osc>;
          ......

You have said "You need clock node if it takes any resources. ", do you think osc here can be counted as a used resource?

Regards,
Li

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Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Krzysztof Kozlowski]

On 06/02/2023 15:57, Li Chen wrote:
> Hi Krzysztof,
>  ---- On Mon, 06 Feb 2023 21:41:44 +0800  Krzysztof Kozlowski  wrote --- 
>  > On 06/02/2023 12:28, Li Chen wrote:
>  > > Hi Krzysztof ,
>  > > 
>  > >  ---- On Fri, 27 Jan 2023 23:08:09 +0800  Krzysztof Kozlowski  wrote --- 
>  > >  > On 27/01/2023 15:48, Li Chen wrote:
>  > >  > >  > 
>  > >  > >  > but what you are saying is that there is no separate clock controller
>  > >  > >  > device with its own IO address but these clocks are part of rct_syscon.
>  > >  > >  > Then model it that way in DTS. The rct_syscon is then your clock
>  > >  > >  > controller and all these fake gclk-core and gclk-ddr nodes should be gone.
>  > >  > > 
>  > >  > > Ok, I will remove these fake nodes, and model the hardware as:
>  > >  > > 
>  > >  > > rct_syscon node
>  > >  > > | clock node(pll, div, mux, composite  clocks live in the same driver)
>  > >  > > | other periphal nodes
>  > >  > 
>  > >  > You need clock node if it takes any resources. If it doesn't, you do not
>  > >  > need it.
>  > > 
>  > > If the only hardware resource the clock node can take is its parent clock(clocks = &osc;),
>  > > then can I have this clock node?
>  > 
>  > I am not sure if I understand. osc does not look like parent device, so
>  > this part of comment confuses me.
> 
> Sorry for the confusion. I mean osc is the root of clock tree:
> 
> osc
>   | pll A
>   | pll B
>   | ...
> 
> So if I have a clock node under rct_syscon node, I think it should take osc as the parent(node) clock:
> rct_syscon {
>     ......
>     clock_controller {
>           clocks = <&osc>;
>           ......
> 
> You have said "You need clock node if it takes any resources. ", do you think osc here can be counted as a used resource?

Yes, in that matter osc should be the input to this clock controller.

Best regards,
Krzysztof

Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Krzysztof Kozlowski]

On 06/02/2023 15:57, Li Chen wrote:
> Hi Krzysztof,
>  ---- On Mon, 06 Feb 2023 21:41:44 +0800  Krzysztof Kozlowski  wrote --- 
>  > On 06/02/2023 12:28, Li Chen wrote:
>  > > Hi Krzysztof ,
>  > > 
>  > >  ---- On Fri, 27 Jan 2023 23:08:09 +0800  Krzysztof Kozlowski  wrote --- 
>  > >  > On 27/01/2023 15:48, Li Chen wrote:
>  > >  > >  > 
>  > >  > >  > but what you are saying is that there is no separate clock controller
>  > >  > >  > device with its own IO address but these clocks are part of rct_syscon.
>  > >  > >  > Then model it that way in DTS. The rct_syscon is then your clock
>  > >  > >  > controller and all these fake gclk-core and gclk-ddr nodes should be gone.
>  > >  > > 
>  > >  > > Ok, I will remove these fake nodes, and model the hardware as:
>  > >  > > 
>  > >  > > rct_syscon node
>  > >  > > | clock node(pll, div, mux, composite  clocks live in the same driver)
>  > >  > > | other periphal nodes
>  > >  > 
>  > >  > You need clock node if it takes any resources. If it doesn't, you do not
>  > >  > need it.
>  > > 
>  > > If the only hardware resource the clock node can take is its parent clock(clocks = &osc;),
>  > > then can I have this clock node?
>  > 
>  > I am not sure if I understand. osc does not look like parent device, so
>  > this part of comment confuses me.
> 
> Sorry for the confusion. I mean osc is the root of clock tree:
> 
> osc
>   | pll A
>   | pll B
>   | ...
> 
> So if I have a clock node under rct_syscon node, I think it should take osc as the parent(node) clock:
> rct_syscon {
>     ......
>     clock_controller {
>           clocks = <&osc>;
>           ......
> 
> You have said "You need clock node if it takes any resources. ", do you think osc here can be counted as a used resource?

Yes, in that matter osc should be the input to this clock controller.

Best regards,
Krzysztof


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Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Krzysztof Kozlowski]

On 27/01/2023 15:48, Li Chen wrote:
>  > This is independent topic. SoC-specific compatibles are a requirement
>  > but it does not affect your device hierarchy.
>  
> Thanks, "requirement" makes things much more clear. So I will always use SoC-specific compatibles even
> if different Amarella SoCs may share the same reg offset and setting.

Just please read before sending any new versions:
https://elixir.bootlin.com/linux/v6.1-rc1/source/Documentation/devicetree/bindings/writing-bindings.rst

Best regards,
Krzysztof

Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Krzysztof Kozlowski]

On 27/01/2023 15:48, Li Chen wrote:
>  > This is independent topic. SoC-specific compatibles are a requirement
>  > but it does not affect your device hierarchy.
>  
> Thanks, "requirement" makes things much more clear. So I will always use SoC-specific compatibles even
> if different Amarella SoCs may share the same reg offset and setting.

Just please read before sending any new versions:
https://elixir.bootlin.com/linux/v6.1-rc1/source/Documentation/devicetree/bindings/writing-bindings.rst

Best regards,
Krzysztof


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Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Li Chen]

Hi Krzysztof,

 ---- On Fri, 27 Jan 2023 23:11:26 +0800  Krzysztof Kozlowski  wrote --- 
 > On 27/01/2023 15:48, Li Chen wrote:
 > >  > This is independent topic. SoC-specific compatibles are a requirement
 > >  > but it does not affect your device hierarchy.
 > >  
 > > Thanks, "requirement" makes things much more clear. So I will always use SoC-specific compatibles even
 > > if different Amarella SoCs may share the same reg offset and setting.
 > 
 > Just please read before sending any new versions:
 > https://elixir.bootlin.com/linux/v6.1-rc1/source/Documentation/devicetree/bindings/writing-bindings.rst

Gotcha.

Regards,
Li

Re: [PATCH 07/15] dt-bindings: clock: Add Ambarella clock bindings

[Li Chen]

Hi Krzysztof,

 ---- On Fri, 27 Jan 2023 23:11:26 +0800  Krzysztof Kozlowski  wrote --- 
 > On 27/01/2023 15:48, Li Chen wrote:
 > >  > This is independent topic. SoC-specific compatibles are a requirement
 > >  > but it does not affect your device hierarchy.
 > >  
 > > Thanks, "requirement" makes things much more clear. So I will always use SoC-specific compatibles even
 > > if different Amarella SoCs may share the same reg offset and setting.
 > 
 > Just please read before sending any new versions:
 > https://elixir.bootlin.com/linux/v6.1-rc1/source/Documentation/devicetree/bindings/writing-bindings.rst

Gotcha.

Regards,
Li

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Re: [PATCH 09/15] dt-bindings: serial: add support for Ambarella

[Krzysztof Kozlowski]

On 23/01/2023 08:32, Li Chen wrote:
> Add compatible for Ambarella.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: I32513d98f52af0311dfb55dd5c4739a58f6b9fc1
> ---
>  .../bindings/serial/ambarella_uart.yaml       | 57 +++++++++++++++++++
>  MAINTAINERS                                   |  1 +
>  2 files changed, 58 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/serial/ambarella_uart.yaml
> 
> diff --git a/Documentation/devicetree/bindings/serial/ambarella_uart.yaml b/Documentation/devicetree/bindings/serial/ambarella_uart.yaml
> new file mode 100644
> index 000000000000..238d68078270
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/serial/ambarella_uart.yaml
> @@ -0,0 +1,57 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/serial/ambarella_uart.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella S6LM SoC UART Controller
> +
> +maintainers:
> +  - Li Chen <lchen@ambarella.com>
> +
> +properties:
> +  compatible:
> +    const: ambarella,uart
> +
> +  reg:
> +    maxItems: 1
> +
> +  amb,ignore-fe:
> +    description: |
> +      ignore frame error report for CV2/CV22/CV25/S6LM because it's
> +      checked too strict so that normal stop may be treated as frame error.

Missing type. I don't understand why this is property of DT.

Anyway several problems mentioned earlier, please fix.


Best regards,
Krzysztof

Re: [PATCH 09/15] dt-bindings: serial: add support for Ambarella

[Krzysztof Kozlowski]

On 23/01/2023 08:32, Li Chen wrote:
> Add compatible for Ambarella.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: I32513d98f52af0311dfb55dd5c4739a58f6b9fc1
> ---
>  .../bindings/serial/ambarella_uart.yaml       | 57 +++++++++++++++++++
>  MAINTAINERS                                   |  1 +
>  2 files changed, 58 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/serial/ambarella_uart.yaml
> 
> diff --git a/Documentation/devicetree/bindings/serial/ambarella_uart.yaml b/Documentation/devicetree/bindings/serial/ambarella_uart.yaml
> new file mode 100644
> index 000000000000..238d68078270
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/serial/ambarella_uart.yaml
> @@ -0,0 +1,57 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/serial/ambarella_uart.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella S6LM SoC UART Controller
> +
> +maintainers:
> +  - Li Chen <lchen@ambarella.com>
> +
> +properties:
> +  compatible:
> +    const: ambarella,uart
> +
> +  reg:
> +    maxItems: 1
> +
> +  amb,ignore-fe:
> +    description: |
> +      ignore frame error report for CV2/CV22/CV25/S6LM because it's
> +      checked too strict so that normal stop may be treated as frame error.

Missing type. I don't understand why this is property of DT.

Anyway several problems mentioned earlier, please fix.


Best regards,
Krzysztof


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Re: [PATCH 09/15] dt-bindings: serial: add support for Ambarella

[Li Chen]

Hi Krzysztof Kozlowski,

Sorry for my late reply.

On Mon, 23 Jan 2023 16:11:52 +0800,
Krzysztof Kozlowski wrote:
>
> On 23/01/2023 08:32, Li Chen wrote:
> > Add compatible for Ambarella.
> >
> > Signed-off-by: Li Chen <lchen@ambarella.com>
> > Change-Id: I32513d98f52af0311dfb55dd5c4739a58f6b9fc1
> > ---
> >  .../bindings/serial/ambarella_uart.yaml       | 57 +++++++++++++++++++
> >  MAINTAINERS                                   |  1 +
> >  2 files changed, 58 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/serial/ambarella_uart.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/serial/ambarella_uart.yaml b/Documentation/devicetree/bindings/serial/ambarella_uart.yaml
> > new file mode 100644
> > index 000000000000..238d68078270
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/serial/ambarella_uart.yaml
> > @@ -0,0 +1,57 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/serial/ambarella_uart.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Ambarella S6LM SoC UART Controller
> > +
> > +maintainers:
> > +  - Li Chen <lchen@ambarella.com>
> > +
> > +properties:
> > +  compatible:
> > +    const: ambarella,uart
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  amb,ignore-fe:
> > +    description: |
> > +      ignore frame error report for CV2/CV22/CV25/S6LM because it's
> > +      checked too strict so that normal stop may be treated as frame error.
>
> Missing type. I don't understand why this is property of DT.

Ok, I will add "type: boolean" to it.

> Anyway several problems mentioned earlier, please fix.

Well noted.

Regards,
Li

Re: [PATCH 09/15] dt-bindings: serial: add support for Ambarella

[Li Chen]

Hi Krzysztof Kozlowski,

Sorry for my late reply.

On Mon, 23 Jan 2023 16:11:52 +0800,
Krzysztof Kozlowski wrote:
>
> On 23/01/2023 08:32, Li Chen wrote:
> > Add compatible for Ambarella.
> >
> > Signed-off-by: Li Chen <lchen@ambarella.com>
> > Change-Id: I32513d98f52af0311dfb55dd5c4739a58f6b9fc1
> > ---
> >  .../bindings/serial/ambarella_uart.yaml       | 57 +++++++++++++++++++
> >  MAINTAINERS                                   |  1 +
> >  2 files changed, 58 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/serial/ambarella_uart.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/serial/ambarella_uart.yaml b/Documentation/devicetree/bindings/serial/ambarella_uart.yaml
> > new file mode 100644
> > index 000000000000..238d68078270
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/serial/ambarella_uart.yaml
> > @@ -0,0 +1,57 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/serial/ambarella_uart.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Ambarella S6LM SoC UART Controller
> > +
> > +maintainers:
> > +  - Li Chen <lchen@ambarella.com>
> > +
> > +properties:
> > +  compatible:
> > +    const: ambarella,uart
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  amb,ignore-fe:
> > +    description: |
> > +      ignore frame error report for CV2/CV22/CV25/S6LM because it's
> > +      checked too strict so that normal stop may be treated as frame error.
>
> Missing type. I don't understand why this is property of DT.

Ok, I will add "type: boolean" to it.

> Anyway several problems mentioned earlier, please fix.

Well noted.

Regards,
Li

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Re: [PATCH 09/15] dt-bindings: serial: add support for Ambarella

[Krzysztof Kozlowski]

On 25/01/2023 10:54, Li Chen wrote:
> 
> Hi Krzysztof Kozlowski,
> 
> Sorry for my late reply.
> 
> On Mon, 23 Jan 2023 16:11:52 +0800,
> Krzysztof Kozlowski wrote:
>>
>> On 23/01/2023 08:32, Li Chen wrote:
>>> Add compatible for Ambarella.
>>>
>>> Signed-off-by: Li Chen <lchen@ambarella.com>
>>> Change-Id: I32513d98f52af0311dfb55dd5c4739a58f6b9fc1
>>> ---
>>>  .../bindings/serial/ambarella_uart.yaml       | 57 +++++++++++++++++++
>>>  MAINTAINERS                                   |  1 +
>>>  2 files changed, 58 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/serial/ambarella_uart.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/serial/ambarella_uart.yaml b/Documentation/devicetree/bindings/serial/ambarella_uart.yaml
>>> new file mode 100644
>>> index 000000000000..238d68078270
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/serial/ambarella_uart.yaml
>>> @@ -0,0 +1,57 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/serial/ambarella_uart.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Ambarella S6LM SoC UART Controller
>>> +
>>> +maintainers:
>>> +  - Li Chen <lchen@ambarella.com>
>>> +
>>> +properties:
>>> +  compatible:
>>> +    const: ambarella,uart
>>> +
>>> +  reg:
>>> +    maxItems: 1
>>> +
>>> +  amb,ignore-fe:
>>> +    description: |
>>> +      ignore frame error report for CV2/CV22/CV25/S6LM because it's
>>> +      checked too strict so that normal stop may be treated as frame error.
>>
>> Missing type. I don't understand why this is property of DT.
> 
> Ok, I will add "type: boolean" to it.

I still do not understand why this is a property of DT. You need to
justify it.

Otherwise: No. drop it.

Best regards,
Krzysztof

Re: [PATCH 09/15] dt-bindings: serial: add support for Ambarella

[Krzysztof Kozlowski]

On 25/01/2023 10:54, Li Chen wrote:
> 
> Hi Krzysztof Kozlowski,
> 
> Sorry for my late reply.
> 
> On Mon, 23 Jan 2023 16:11:52 +0800,
> Krzysztof Kozlowski wrote:
>>
>> On 23/01/2023 08:32, Li Chen wrote:
>>> Add compatible for Ambarella.
>>>
>>> Signed-off-by: Li Chen <lchen@ambarella.com>
>>> Change-Id: I32513d98f52af0311dfb55dd5c4739a58f6b9fc1
>>> ---
>>>  .../bindings/serial/ambarella_uart.yaml       | 57 +++++++++++++++++++
>>>  MAINTAINERS                                   |  1 +
>>>  2 files changed, 58 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/serial/ambarella_uart.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/serial/ambarella_uart.yaml b/Documentation/devicetree/bindings/serial/ambarella_uart.yaml
>>> new file mode 100644
>>> index 000000000000..238d68078270
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/serial/ambarella_uart.yaml
>>> @@ -0,0 +1,57 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/serial/ambarella_uart.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Ambarella S6LM SoC UART Controller
>>> +
>>> +maintainers:
>>> +  - Li Chen <lchen@ambarella.com>
>>> +
>>> +properties:
>>> +  compatible:
>>> +    const: ambarella,uart
>>> +
>>> +  reg:
>>> +    maxItems: 1
>>> +
>>> +  amb,ignore-fe:
>>> +    description: |
>>> +      ignore frame error report for CV2/CV22/CV25/S6LM because it's
>>> +      checked too strict so that normal stop may be treated as frame error.
>>
>> Missing type. I don't understand why this is property of DT.
> 
> Ok, I will add "type: boolean" to it.

I still do not understand why this is a property of DT. You need to
justify it.

Otherwise: No. drop it.

Best regards,
Krzysztof


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Re: [PATCH 09/15] dt-bindings: serial: add support for Ambarella

[Li Chen]

Hi Krzysztof,

Sorry for my late reply.

 ---- On Wed, 25 Jan 2023 17:56:15 +0800  Krzysztof Kozlowski  wrote --- 
 > On 25/01/2023 10:54, Li Chen wrote:
 > > 
 > > Hi Krzysztof Kozlowski,
 > > 
 > > Sorry for my late reply.
 > > 
 > > On Mon, 23 Jan 2023 16:11:52 +0800,
 > > Krzysztof Kozlowski wrote:
 > >>
 > >> On 23/01/2023 08:32, Li Chen wrote:
 > >>> Add compatible for Ambarella.
 > >>>
 > >>> Signed-off-by: Li Chen lchen@ambarella.com>
 > >>> Change-Id: I32513d98f52af0311dfb55dd5c4739a58f6b9fc1
 > >>> ---
 > >>>  .../bindings/serial/ambarella_uart.yaml       | 57 +++++++++++++++++++
 > >>>  MAINTAINERS                                   |  1 +
 > >>>  2 files changed, 58 insertions(+)
 > >>>  create mode 100644 Documentation/devicetree/bindings/serial/ambarella_uart.yaml
 > >>>
 > >>> diff --git a/Documentation/devicetree/bindings/serial/ambarella_uart.yaml b/Documentation/devicetree/bindings/serial/ambarella_uart.yaml
 > >>> new file mode 100644
 > >>> index 000000000000..238d68078270
 > >>> --- /dev/null
 > >>> +++ b/Documentation/devicetree/bindings/serial/ambarella_uart.yaml
 > >>> @@ -0,0 +1,57 @@
 > >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 > >>> +%YAML 1.2
 > >>> +---
 > >>> +$id: http://devicetree.org/schemas/serial/ambarella_uart.yaml#
 > >>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
 > >>> +
 > >>> +title: Ambarella S6LM SoC UART Controller
 > >>> +
 > >>> +maintainers:
 > >>> +  - Li Chen lchen@ambarella.com>
 > >>> +
 > >>> +properties:
 > >>> +  compatible:
 > >>> +    const: ambarella,uart
 > >>> +
 > >>> +  reg:
 > >>> +    maxItems: 1
 > >>> +
 > >>> +  amb,ignore-fe:
 > >>> +    description: |
 > >>> +      ignore frame error report for CV2/CV22/CV25/S6LM because it's
 > >>> +      checked too strict so that normal stop may be treated as frame error.
 > >>
 > >> Missing type. I don't understand why this is property of DT.
 > > 
 > > Ok, I will add "type: boolean" to it.
 > 
 > I still do not understand why this is a property of DT. You need to
 > justify it.
 > 
 > Otherwise: No. drop it.

Yes, this property is not describing hardware. I will drop it from dts and handle it via soc_device_attribute->data
or of_device_id->data instead.

Regards,
Li

Re: [PATCH 09/15] dt-bindings: serial: add support for Ambarella

[Li Chen]

Hi Krzysztof,

Sorry for my late reply.

 ---- On Wed, 25 Jan 2023 17:56:15 +0800  Krzysztof Kozlowski  wrote --- 
 > On 25/01/2023 10:54, Li Chen wrote:
 > > 
 > > Hi Krzysztof Kozlowski,
 > > 
 > > Sorry for my late reply.
 > > 
 > > On Mon, 23 Jan 2023 16:11:52 +0800,
 > > Krzysztof Kozlowski wrote:
 > >>
 > >> On 23/01/2023 08:32, Li Chen wrote:
 > >>> Add compatible for Ambarella.
 > >>>
 > >>> Signed-off-by: Li Chen lchen@ambarella.com>
 > >>> Change-Id: I32513d98f52af0311dfb55dd5c4739a58f6b9fc1
 > >>> ---
 > >>>  .../bindings/serial/ambarella_uart.yaml       | 57 +++++++++++++++++++
 > >>>  MAINTAINERS                                   |  1 +
 > >>>  2 files changed, 58 insertions(+)
 > >>>  create mode 100644 Documentation/devicetree/bindings/serial/ambarella_uart.yaml
 > >>>
 > >>> diff --git a/Documentation/devicetree/bindings/serial/ambarella_uart.yaml b/Documentation/devicetree/bindings/serial/ambarella_uart.yaml
 > >>> new file mode 100644
 > >>> index 000000000000..238d68078270
 > >>> --- /dev/null
 > >>> +++ b/Documentation/devicetree/bindings/serial/ambarella_uart.yaml
 > >>> @@ -0,0 +1,57 @@
 > >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 > >>> +%YAML 1.2
 > >>> +---
 > >>> +$id: http://devicetree.org/schemas/serial/ambarella_uart.yaml#
 > >>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
 > >>> +
 > >>> +title: Ambarella S6LM SoC UART Controller
 > >>> +
 > >>> +maintainers:
 > >>> +  - Li Chen lchen@ambarella.com>
 > >>> +
 > >>> +properties:
 > >>> +  compatible:
 > >>> +    const: ambarella,uart
 > >>> +
 > >>> +  reg:
 > >>> +    maxItems: 1
 > >>> +
 > >>> +  amb,ignore-fe:
 > >>> +    description: |
 > >>> +      ignore frame error report for CV2/CV22/CV25/S6LM because it's
 > >>> +      checked too strict so that normal stop may be treated as frame error.
 > >>
 > >> Missing type. I don't understand why this is property of DT.
 > > 
 > > Ok, I will add "type: boolean" to it.
 > 
 > I still do not understand why this is a property of DT. You need to
 > justify it.
 > 
 > Otherwise: No. drop it.

Yes, this property is not describing hardware. I will drop it from dts and handle it via soc_device_attribute->data
or of_device_id->data instead.

Regards,
Li

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Re: [PATCH 11/15] dt-bindings: mtd: Add binding for Ambarella

[Krzysztof Kozlowski]

On 23/01/2023 08:32, Li Chen wrote:
> Ambarella SoC contains nand flash controller.
> Add compatible for it.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: I4108699a0678ba45e5d4347cbd860bc552dd91dd
> ---
>  .../bindings/mtd/ambarella,nand.yaml          | 77 +++++++++++++++++++
>  MAINTAINERS                                   |  1 +
>  2 files changed, 78 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mtd/ambarella,nand.yaml
> 
> diff --git a/Documentation/devicetree/bindings/mtd/ambarella,nand.yaml b/Documentation/devicetree/bindings/mtd/ambarella,nand.yaml
> new file mode 100644
> index 000000000000..7c2e7c2ebc7b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/ambarella,nand.yaml
> @@ -0,0 +1,77 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mtd/ambarella,nand.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella NAND Controller
> +
> +maintainers:
> +  - Li Chen <lchen@ambarella.com>
> +
> +properties:
> +  compatible:
> +    - const: ambarella,nand
> +
> +  reg:
> +    minItems: 1
> +    maxItems: 1

All your patches are weirder and weirder. Do you see such syntax in any
patches before?

Drop minItems.

> +
> +  interrupts:
> +    minItems: 1
> +    maxItems: 1

Drop both.

> +    items:
> +      - description: fio irq
> +
> +  clocks:
> +    maxItems: 1
> +    description: reference to the clock for the NAND controller
> +
> +  nand-on-flash-bbt:

OK, so this was for sure not tested.

Do not send untested patches.

Best regards,
Krzysztof

Re: [PATCH 11/15] dt-bindings: mtd: Add binding for Ambarella

[Krzysztof Kozlowski]

On 23/01/2023 08:32, Li Chen wrote:
> Ambarella SoC contains nand flash controller.
> Add compatible for it.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: I4108699a0678ba45e5d4347cbd860bc552dd91dd
> ---
>  .../bindings/mtd/ambarella,nand.yaml          | 77 +++++++++++++++++++
>  MAINTAINERS                                   |  1 +
>  2 files changed, 78 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mtd/ambarella,nand.yaml
> 
> diff --git a/Documentation/devicetree/bindings/mtd/ambarella,nand.yaml b/Documentation/devicetree/bindings/mtd/ambarella,nand.yaml
> new file mode 100644
> index 000000000000..7c2e7c2ebc7b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/ambarella,nand.yaml
> @@ -0,0 +1,77 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mtd/ambarella,nand.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella NAND Controller
> +
> +maintainers:
> +  - Li Chen <lchen@ambarella.com>
> +
> +properties:
> +  compatible:
> +    - const: ambarella,nand
> +
> +  reg:
> +    minItems: 1
> +    maxItems: 1

All your patches are weirder and weirder. Do you see such syntax in any
patches before?

Drop minItems.

> +
> +  interrupts:
> +    minItems: 1
> +    maxItems: 1

Drop both.

> +    items:
> +      - description: fio irq
> +
> +  clocks:
> +    maxItems: 1
> +    description: reference to the clock for the NAND controller
> +
> +  nand-on-flash-bbt:

OK, so this was for sure not tested.

Do not send untested patches.

Best regards,
Krzysztof


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Re: [PATCH 11/15] dt-bindings: mtd: Add binding for Ambarella

[Krzysztof Kozlowski]

On 23/01/2023 08:32, Li Chen wrote:
> Ambarella SoC contains nand flash controller.
> Add compatible for it.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: I4108699a0678ba45e5d4347cbd860bc552dd91dd
> ---
>  .../bindings/mtd/ambarella,nand.yaml          | 77 +++++++++++++++++++
>  MAINTAINERS                                   |  1 +
>  2 files changed, 78 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mtd/ambarella,nand.yaml
> 
> diff --git a/Documentation/devicetree/bindings/mtd/ambarella,nand.yaml b/Documentation/devicetree/bindings/mtd/ambarella,nand.yaml
> new file mode 100644
> index 000000000000..7c2e7c2ebc7b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/ambarella,nand.yaml
> @@ -0,0 +1,77 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mtd/ambarella,nand.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella NAND Controller
> +
> +maintainers:
> +  - Li Chen <lchen@ambarella.com>
> +
> +properties:
> +  compatible:
> +    - const: ambarella,nand
> +
> +  reg:
> +    minItems: 1
> +    maxItems: 1

All your patches are weirder and weirder. Do you see such syntax in any
patches before?

Drop minItems.

> +
> +  interrupts:
> +    minItems: 1
> +    maxItems: 1

Drop both.

> +    items:
> +      - description: fio irq
> +
> +  clocks:
> +    maxItems: 1
> +    description: reference to the clock for the NAND controller
> +
> +  nand-on-flash-bbt:

OK, so this was for sure not tested.

Do not send untested patches.

Best regards,
Krzysztof


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Re: [PATCH 13/15] dt-bindings: pinctrl: add support for Ambarella

[Krzysztof Kozlowski]

On 23/01/2023 08:32, Li Chen wrote:
> Add a Ambarella compatible.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: I8bcab3b763bdc7e400a04cc46589f0f694028a66
> ---
>  .../bindings/pinctrl/ambarella,pinctrl.yaml   | 160 ++++++++++++++++++
>  MAINTAINERS                                   |   1 +
>  2 files changed, 161 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/ambarella,pinctrl.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/ambarella,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ambarella,pinctrl.yaml
> new file mode 100644
> index 000000000000..51f5a9cc4714
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/ambarella,pinctrl.yaml
> @@ -0,0 +1,160 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/ambarella,pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella PIN controller
> +
> +maintainers:
> +  - Li Chen <lchen@ambarella.org>
> +
> +description: |
> +  The pins controlled by Ambarella SoC chip are organized in banks, each bank
> +  has 32 pins.  Each pin has at least 2 multiplexing functions, and generally,
> +  the first function is GPIO.
> +
> +  The PINCTRL node acts as a container for an arbitrary number of subnodes. And
> +  these subnodes will fall into two categories.
> +
> +  One is for GPIO, please see the "GPIO node" section for detail, and another one
> +  is to set up a group of pins for a function, both pin configurations and mux
> +  selection, and it's called group node in the binding document.
> +
> +properties:
> +  compatible:
> +    items:
> +      - const: ambarella,pinctrl
> +
> +  reg:
> +    minItems: 4
> +    maxItems: 4
> +

Same problems as with other patches. You need to fix all of my previous
comments.

Best regards,
Krzysztof

Re: [PATCH 13/15] dt-bindings: pinctrl: add support for Ambarella

[Krzysztof Kozlowski]

On 23/01/2023 08:32, Li Chen wrote:
> Add a Ambarella compatible.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: I8bcab3b763bdc7e400a04cc46589f0f694028a66
> ---
>  .../bindings/pinctrl/ambarella,pinctrl.yaml   | 160 ++++++++++++++++++
>  MAINTAINERS                                   |   1 +
>  2 files changed, 161 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/ambarella,pinctrl.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/ambarella,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ambarella,pinctrl.yaml
> new file mode 100644
> index 000000000000..51f5a9cc4714
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/ambarella,pinctrl.yaml
> @@ -0,0 +1,160 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/ambarella,pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ambarella PIN controller
> +
> +maintainers:
> +  - Li Chen <lchen@ambarella.org>
> +
> +description: |
> +  The pins controlled by Ambarella SoC chip are organized in banks, each bank
> +  has 32 pins.  Each pin has at least 2 multiplexing functions, and generally,
> +  the first function is GPIO.
> +
> +  The PINCTRL node acts as a container for an arbitrary number of subnodes. And
> +  these subnodes will fall into two categories.
> +
> +  One is for GPIO, please see the "GPIO node" section for detail, and another one
> +  is to set up a group of pins for a function, both pin configurations and mux
> +  selection, and it's called group node in the binding document.
> +
> +properties:
> +  compatible:
> +    items:
> +      - const: ambarella,pinctrl
> +
> +  reg:
> +    minItems: 4
> +    maxItems: 4
> +

Same problems as with other patches. You need to fix all of my previous
comments.

Best regards,
Krzysztof


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Re: [PATCH 13/15] dt-bindings: pinctrl: add support for Ambarella

[Linus Walleij]

Hi Li,

thanks for your patch!

It's nice to see Ambarella working with the kernel community.

On Mon, Jan 23, 2023 at 8:41 AM Li Chen <lchen@ambarella.com> wrote:

> +properties:
> +  compatible:
> +    items:
> +      - const: ambarella,pinctrl

I bet there will be more instances of pin controllers from Ambarella, so I would
use this only as a fallback, so the for should likely be:

compatible = "ambarella,<soc-name>-pinctrl", "ambarella,pinctrl";

we need to establish this already otherwise "ambarella,pinctrl" just becomes
the "weird name of the first ambarella SoC supported by standard DT bindings".

> +  amb,pull-regmap:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      maxItems: 1
> +
> +  amb,ds-regmap:
> +    items:
> +      maxItems: 1

Interesting that these registers are elsewhere, but I bet there is an
engineering
explanation for this :)

> +    properties:
> +      amb,pinmux-ids:
> +        description: |
> +          an integer array. Each integer in the array specifies a pin
> +          with given mux function, with pin id and mux packed as:
> +          mux << 12 | pin id
> +          Here mux means function of this pin, and pin id is identical to gpio id. For
> +          the SoC supporting IOMUX, like S2L, the maximal value of mux is 5. However,
> +          for the SoC not supporting IOMUX, like A5S, S2, the third or fourth function
> +          is selected by other "virtual pins" setting. Here the "virtual pins" means
> +          there is no real hardware pins mapping to the corresponding register address.
> +          So the registers for the "virtual pins" can be used for the selection of 3rd
> +          or 4th function for other real pins.

I think you can use the standard bindings for this if you insist on
using the "magic
numbers" scheme.

(I prefer function names and group names as strings, but I gave up on trying
to convince the world to use this because people have so strong opions about
it.)

From Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml:

  pinmux:
    description:
      The list of numeric pin ids and their mux settings that properties in the
      node apply to (either this, "pins" or "groups" have to be specified)
    $ref: /schemas/types.yaml#/definitions/uint32-array

> +      amb,pinconf-ids:
> +        description: |
> +          an integer array. Each integer in the array specifies a pin
> +          with given configuration, with pin id and config packed as:
> +            config << 16 | pin id
> +          Here config is used to configure pull up/down and drive strength of the pin,
> +          and it's orgnization is:
> +          bit1~0: 00: pull down, 01: pull up, 1x: clear pull up/down
> +          bit2:   reserved
> +          bit3:   0: leave pull up/down as default value, 1: config pull up/down
> +          bit5~4: drive strength value, 0: 2mA, 1: 4mA, 2: 8mA, 3: 12mA
> +          bit6:   reserved
> +          bit7:   0: leave drive strength as default value, 1: config drive strength

I would be very happy if I could convince you to use the standard (string)
bindings for this.
And from Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml

For each config node this means using strings such as
bias-high-impedance; etc in the device tree pin config node.

Following that scheme just makes life so much easier for maintainers and
reviewers: very few people reviewing or debugging the system will think
it is easy to read a magic number and then (in their head) mask out the
bits to see that "OK this is drive strength 8mA" and then have energy and
memory enough in their head to remember that "wait a minute, that is supposed
to be 12mA in this design", leading to long review and development
cycles.

By using:

drive-push-pull;
drive-strength = <8>;

you make the cognitive load on the people reading the device tree much
lower and easier to write, maintain and debug for humans.

The tendency to encode this info in terse bitfields appear to be done for either
of these reasons:

- Footprint / memory usage
- Adopt the users to the way the machine thinks instead of the other way around
- "We always did it this way"

Neither is a very good argument on a new 64bit platform.

Yours,
Linus Walleij

Re: [PATCH 13/15] dt-bindings: pinctrl: add support for Ambarella

[Linus Walleij]

Hi Li,

thanks for your patch!

It's nice to see Ambarella working with the kernel community.

On Mon, Jan 23, 2023 at 8:41 AM Li Chen <lchen@ambarella.com> wrote:

> +properties:
> +  compatible:
> +    items:
> +      - const: ambarella,pinctrl

I bet there will be more instances of pin controllers from Ambarella, so I would
use this only as a fallback, so the for should likely be:

compatible = "ambarella,<soc-name>-pinctrl", "ambarella,pinctrl";

we need to establish this already otherwise "ambarella,pinctrl" just becomes
the "weird name of the first ambarella SoC supported by standard DT bindings".

> +  amb,pull-regmap:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      maxItems: 1
> +
> +  amb,ds-regmap:
> +    items:
> +      maxItems: 1

Interesting that these registers are elsewhere, but I bet there is an
engineering
explanation for this :)

> +    properties:
> +      amb,pinmux-ids:
> +        description: |
> +          an integer array. Each integer in the array specifies a pin
> +          with given mux function, with pin id and mux packed as:
> +          mux << 12 | pin id
> +          Here mux means function of this pin, and pin id is identical to gpio id. For
> +          the SoC supporting IOMUX, like S2L, the maximal value of mux is 5. However,
> +          for the SoC not supporting IOMUX, like A5S, S2, the third or fourth function
> +          is selected by other "virtual pins" setting. Here the "virtual pins" means
> +          there is no real hardware pins mapping to the corresponding register address.
> +          So the registers for the "virtual pins" can be used for the selection of 3rd
> +          or 4th function for other real pins.

I think you can use the standard bindings for this if you insist on
using the "magic
numbers" scheme.

(I prefer function names and group names as strings, but I gave up on trying
to convince the world to use this because people have so strong opions about
it.)

From Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml:

  pinmux:
    description:
      The list of numeric pin ids and their mux settings that properties in the
      node apply to (either this, "pins" or "groups" have to be specified)
    $ref: /schemas/types.yaml#/definitions/uint32-array

> +      amb,pinconf-ids:
> +        description: |
> +          an integer array. Each integer in the array specifies a pin
> +          with given configuration, with pin id and config packed as:
> +            config << 16 | pin id
> +          Here config is used to configure pull up/down and drive strength of the pin,
> +          and it's orgnization is:
> +          bit1~0: 00: pull down, 01: pull up, 1x: clear pull up/down
> +          bit2:   reserved
> +          bit3:   0: leave pull up/down as default value, 1: config pull up/down
> +          bit5~4: drive strength value, 0: 2mA, 1: 4mA, 2: 8mA, 3: 12mA
> +          bit6:   reserved
> +          bit7:   0: leave drive strength as default value, 1: config drive strength

I would be very happy if I could convince you to use the standard (string)
bindings for this.
And from Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml

For each config node this means using strings such as
bias-high-impedance; etc in the device tree pin config node.

Following that scheme just makes life so much easier for maintainers and
reviewers: very few people reviewing or debugging the system will think
it is easy to read a magic number and then (in their head) mask out the
bits to see that "OK this is drive strength 8mA" and then have energy and
memory enough in their head to remember that "wait a minute, that is supposed
to be 12mA in this design", leading to long review and development
cycles.

By using:

drive-push-pull;
drive-strength = <8>;

you make the cognitive load on the people reading the device tree much
lower and easier to write, maintain and debug for humans.

The tendency to encode this info in terse bitfields appear to be done for either
of these reasons:

- Footprint / memory usage
- Adopt the users to the way the machine thinks instead of the other way around
- "We always did it this way"

Neither is a very good argument on a new 64bit platform.

Yours,
Linus Walleij

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 13/15] dt-bindings: pinctrl: add support for Ambarella

[Li Chen]

Hi Linus,

Sorry for my late reply.

 ---- On Mon, 23 Jan 2023 20:32:28 +0800  Linus Walleij  wrote --- 
 > Hi Li,
 > 
 > thanks for your patch!
 > 
 > It's nice to see Ambarella working with the kernel community.
 > 
 > On Mon, Jan 23, 2023 at 8:41 AM Li Chen lchen@ambarella.com> wrote:
 > 
 > > +properties:
 > > +  compatible:
 > > +    items:
 > > +      - const: ambarella,pinctrl
 > 
 > I bet there will be more instances of pin controllers from Ambarella, so I would
 > use this only as a fallback, so the for should likely be:
 > 
 > compatible = "ambarella,-pinctrl", "ambarella,pinctrl";
 > 
 > we need to establish this already otherwise "ambarella,pinctrl" just becomes
 > the "weird name of the first ambarella SoC supported by standard DT bindings".
 
There is only single "ambarella,pinctrl" in Ambarella downstream kernels, and we use soc_device_attribute->data
and soc_device_attribute->soc_id/family to get correct SoC-specific information like reg offset and etc.

Krzysztof has taught me that this way is wrong and
SoC is required in compatible: https://www.spinics.net/lists/arm-kernel/msg1043145.html

So I will update this property to "ambarella,s6lm-pinctrl" in the new version.

 > > +  amb,pull-regmap:
 > > +    $ref: /schemas/types.yaml#/definitions/phandle-array
 > > +    items:
 > > +      maxItems: 1
 > > +
 > > +  amb,ds-regmap:
 > > +    items:
 > > +      maxItems: 1
 > 
 > Interesting that these registers are elsewhere, but I bet there is an
 > engineering
 > explanation for this :)
 > 
 > > +    properties:
 > > +      amb,pinmux-ids:
 > > +        description: |
 > > +          an integer array. Each integer in the array specifies a pin
 > > +          with given mux function, with pin id and mux packed as:
 > > +          mux << 12 | pin id
 > > +          Here mux means function of this pin, and pin id is identical to gpio id. For
 > > +          the SoC supporting IOMUX, like S2L, the maximal value of mux is 5. However,
 > > +          for the SoC not supporting IOMUX, like A5S, S2, the third or fourth function
 > > +          is selected by other "virtual pins" setting. Here the "virtual pins" means
 > > +          there is no real hardware pins mapping to the corresponding register address.
 > > +          So the registers for the "virtual pins" can be used for the selection of 3rd
 > > +          or 4th function for other real pins.
 > 
 > I think you can use the standard bindings for this if you insist on
 > using the "magic
 > numbers" scheme.
 > 
 > (I prefer function names and group names as strings, but I gave up on trying
 > to convince the world to use this because people have so strong opions about
 > it.)
 > 
 > From Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml:
 > 
 >   pinmux:
 >     description:
 >       The list of numeric pin ids and their mux settings that properties in the
 >       node apply to (either this, "pins" or "groups" have to be specified)
 >     $ref: /schemas/types.yaml#/definitions/uint32-array
 > 

Well noted, I will switch to pinmux in v2.

 > > +      amb,pinconf-ids:
 > > +        description: |
 > > +          an integer array. Each integer in the array specifies a pin
 > > +          with given configuration, with pin id and config packed as:
 > > +            config << 16 | pin id
 > > +          Here config is used to configure pull up/down and drive strength of the pin,
 > > +          and it's orgnization is:
 > > +          bit1~0: 00: pull down, 01: pull up, 1x: clear pull up/down
 > > +          bit2:   reserved
 > > +          bit3:   0: leave pull up/down as default value, 1: config pull up/down
 > > +          bit5~4: drive strength value, 0: 2mA, 1: 4mA, 2: 8mA, 3: 12mA
 > > +          bit6:   reserved
 > > +          bit7:   0: leave drive strength as default value, 1: config drive strength
 > 
 > I would be very happy if I could convince you to use the standard (string)
 > bindings for this.
 > And from Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
 > 
 > For each config node this means using strings such as
 > bias-high-impedance; etc in the device tree pin config node.
 > 
 > Following that scheme just makes life so much easier for maintainers and
 > reviewers: very few people reviewing or debugging the system will think
 > it is easy to read a magic number and then (in their head) mask out the
 > bits to see that "OK this is drive strength 8mA" and then have energy and
 > memory enough in their head to remember that "wait a minute, that is supposed
 > to be 12mA in this design", leading to long review and development
 > cycles.
 > 
 > By using:
 > 
 > drive-push-pull;
 > drive-strength = ;
 > 
 > you make the cognitive load on the people reading the device tree much
 > lower and easier to write, maintain and debug for humans.
 > 
 > The tendency to encode this info in terse bitfields appear to be done for either
 > of these reasons:
 > 
 > - Footprint / memory usage
 > - Adopt the users to the way the machine thinks instead of the other way around
 > - "We always did it this way"
 > 
 > Neither is a very good argument on a new 64bit platform.

Thanks for your detailed explanation. I totally agree with you and I also really hate
magic number haha.

I will convert it to standard binding after convincing my manager.

Regards,
Li

Re: [PATCH 13/15] dt-bindings: pinctrl: add support for Ambarella

[Li Chen]

Hi Linus,

Sorry for my late reply.

 ---- On Mon, 23 Jan 2023 20:32:28 +0800  Linus Walleij  wrote --- 
 > Hi Li,
 > 
 > thanks for your patch!
 > 
 > It's nice to see Ambarella working with the kernel community.
 > 
 > On Mon, Jan 23, 2023 at 8:41 AM Li Chen lchen@ambarella.com> wrote:
 > 
 > > +properties:
 > > +  compatible:
 > > +    items:
 > > +      - const: ambarella,pinctrl
 > 
 > I bet there will be more instances of pin controllers from Ambarella, so I would
 > use this only as a fallback, so the for should likely be:
 > 
 > compatible = "ambarella,-pinctrl", "ambarella,pinctrl";
 > 
 > we need to establish this already otherwise "ambarella,pinctrl" just becomes
 > the "weird name of the first ambarella SoC supported by standard DT bindings".
 
There is only single "ambarella,pinctrl" in Ambarella downstream kernels, and we use soc_device_attribute->data
and soc_device_attribute->soc_id/family to get correct SoC-specific information like reg offset and etc.

Krzysztof has taught me that this way is wrong and
SoC is required in compatible: https://www.spinics.net/lists/arm-kernel/msg1043145.html

So I will update this property to "ambarella,s6lm-pinctrl" in the new version.

 > > +  amb,pull-regmap:
 > > +    $ref: /schemas/types.yaml#/definitions/phandle-array
 > > +    items:
 > > +      maxItems: 1
 > > +
 > > +  amb,ds-regmap:
 > > +    items:
 > > +      maxItems: 1
 > 
 > Interesting that these registers are elsewhere, but I bet there is an
 > engineering
 > explanation for this :)
 > 
 > > +    properties:
 > > +      amb,pinmux-ids:
 > > +        description: |
 > > +          an integer array. Each integer in the array specifies a pin
 > > +          with given mux function, with pin id and mux packed as:
 > > +          mux << 12 | pin id
 > > +          Here mux means function of this pin, and pin id is identical to gpio id. For
 > > +          the SoC supporting IOMUX, like S2L, the maximal value of mux is 5. However,
 > > +          for the SoC not supporting IOMUX, like A5S, S2, the third or fourth function
 > > +          is selected by other "virtual pins" setting. Here the "virtual pins" means
 > > +          there is no real hardware pins mapping to the corresponding register address.
 > > +          So the registers for the "virtual pins" can be used for the selection of 3rd
 > > +          or 4th function for other real pins.
 > 
 > I think you can use the standard bindings for this if you insist on
 > using the "magic
 > numbers" scheme.
 > 
 > (I prefer function names and group names as strings, but I gave up on trying
 > to convince the world to use this because people have so strong opions about
 > it.)
 > 
 > From Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml:
 > 
 >   pinmux:
 >     description:
 >       The list of numeric pin ids and their mux settings that properties in the
 >       node apply to (either this, "pins" or "groups" have to be specified)
 >     $ref: /schemas/types.yaml#/definitions/uint32-array
 > 

Well noted, I will switch to pinmux in v2.

 > > +      amb,pinconf-ids:
 > > +        description: |
 > > +          an integer array. Each integer in the array specifies a pin
 > > +          with given configuration, with pin id and config packed as:
 > > +            config << 16 | pin id
 > > +          Here config is used to configure pull up/down and drive strength of the pin,
 > > +          and it's orgnization is:
 > > +          bit1~0: 00: pull down, 01: pull up, 1x: clear pull up/down
 > > +          bit2:   reserved
 > > +          bit3:   0: leave pull up/down as default value, 1: config pull up/down
 > > +          bit5~4: drive strength value, 0: 2mA, 1: 4mA, 2: 8mA, 3: 12mA
 > > +          bit6:   reserved
 > > +          bit7:   0: leave drive strength as default value, 1: config drive strength
 > 
 > I would be very happy if I could convince you to use the standard (string)
 > bindings for this.
 > And from Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
 > 
 > For each config node this means using strings such as
 > bias-high-impedance; etc in the device tree pin config node.
 > 
 > Following that scheme just makes life so much easier for maintainers and
 > reviewers: very few people reviewing or debugging the system will think
 > it is easy to read a magic number and then (in their head) mask out the
 > bits to see that "OK this is drive strength 8mA" and then have energy and
 > memory enough in their head to remember that "wait a minute, that is supposed
 > to be 12mA in this design", leading to long review and development
 > cycles.
 > 
 > By using:
 > 
 > drive-push-pull;
 > drive-strength = ;
 > 
 > you make the cognitive load on the people reading the device tree much
 > lower and easier to write, maintain and debug for humans.
 > 
 > The tendency to encode this info in terse bitfields appear to be done for either
 > of these reasons:
 > 
 > - Footprint / memory usage
 > - Adopt the users to the way the machine thinks instead of the other way around
 > - "We always did it this way"
 > 
 > Neither is a very good argument on a new 64bit platform.

Thanks for your detailed explanation. I totally agree with you and I also really hate
magic number haha.

I will convert it to standard binding after convincing my manager.

Regards,
Li

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 15/15] arm64: dts: ambarella: introduce Ambarella s6lm SoC

[Krzysztof Kozlowski]

On 23/01/2023 08:32, Li Chen wrote:
> This patch adds s6lm's devicetree.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: Idc7a04cc64a53b3296bc9fcf9dd3cd648ebefeae
> ---
>  MAINTAINERS                                   |   2 +
>  .../boot/dts/ambarella/ambarella-s6lm.dtsi    | 332 ++++++++++++++++++
>  .../boot/dts/ambarella/s6lm_pineapple.dts     |  29 ++
>  3 files changed, 363 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/ambarella/ambarella-s6lm.dtsi
>  create mode 100644 arch/arm64/boot/dts/ambarella/s6lm_pineapple.dts
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1360fe2f4236..d9d1033b6452 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1894,6 +1894,8 @@ ARM/Ambarella SoC support
>  M:	Li Chen <me@linux.beauty>
>  L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
>  S:	Supported
> +F:	arch/arm64/boot/dts/ambarella/ambarella-s6lm.dts
> +F:	arch/arm64/boot/dts/ambarella/ambarella-s6lm.dtsi
>  F:	Documentation/devicetree/bindings/arm/ambarella.yaml
>  F:	Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml
>  F:	Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml
> diff --git a/arch/arm64/boot/dts/ambarella/ambarella-s6lm.dtsi b/arch/arm64/boot/dts/ambarella/ambarella-s6lm.dtsi
> new file mode 100644
> index 000000000000..c3fa77b33e04
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ambarella/ambarella-s6lm.dtsi
> @@ -0,0 +1,332 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2023 Ambarella,Inc. - http://www.ambarella.com/
> + * Author: Cao Rongrong <rrcao@ambarella.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.

Drop boilerplate.

> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	compatible = "ambarella,s6lm";
> +	interrupt-parent = <&gic>;
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	aliases {
> +		serial0 = &uart0;
> +		nand = &nand0;
> +	};
> +
> +	chosen {
> +		stdout-path = &uart0;
> +	};
> +
> +	/*
> +	 * the memory node will be overwritten in Amboot,
> +	 * here is just the default value.
> +	 */
> +	memory {
> +		device_type = "memory";
> +		reg = <0x00200000 0x07e00000>; /* 126M */
> +	};
> +
> +	reserved-memory {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-0.2";
> +		method = "smc";
> +	};
> +
> +	pmu {
> +		compatible = "arm,cortex-a53-pmu";
> +		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +			     <0 5 0x4>,

??? Just compare these two lines above...

> +			     <0 6 0x4>,
> +			     <0 7 0x4>;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		cpu@0 {
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <0x0>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu@1 {
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <0x1>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu@2 {
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <0x2>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu@3 {
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <0x3>;
> +			enable-method = "psci";
> +		};
> +	};
> +
> +	gic: interrupt-controller@f3000000 {
> +		compatible = "arm,gic-400";

reg should be second property.

> +		#interrupt-cells = <3>;
> +		#address-cells = <0>;
> +		interrupt-controller;
> +		reg = <0xf3001000 0x1000>,	/* GIC Dist */
> +		      <0xf3002000 0x2000>,	/* GIC CPU */
> +		      /* following are not used if no virtulization */
> +		      <0xf3004000 0x2000>,	/* GIC VCPU Control */
> +		      <0xf3006000 0x2000>;	/* GIC VCPU */
> +		interrupts = <GIC_PPI 9 0xf04>;	/* GIC Maintenence IRQ */
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13 0xf08>,	/* Secure Phys IRQ */
> +			     <1 14 0xf08>,	/* Non-secure Phys IRQ */

And you do not see here anything odd?

> +			     <1 11 0xf08>,	/* Virt IRQ */
> +			     <1 10 0xf08>;	/* Hyp IRQ */
> +	};
> +
> +	n_apb@e4000000 { /* Non-Secure APB, but configurable */

No underscores in node names. Generic node names, so just "bus"

> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0xe4000000 0x01000000>;
> +		ranges;
> +
> +		uart0: uart@e4000000 {

serial

> +			compatible = "ambarella,uart";
> +			reg = <0xe4000000 0x1000>;
> +			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&uart0_pins>;
> +			clocks = <&gclk_uart0>;
> +			amb,ignore-fe;
> +			status = "ok";
> +		};
> +	};
> +
> +	s_apb@ec000000 { /* Secure APB, but configurable */

bus

> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0xec000000 0x01000000>;

reg is second property

> +		ranges;
> +
> +		pinctrl: pinctrl@0xec003000 {
> +			compatible = "ambarella,pinctrl";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0xec003000 0x1000>,
> +			      <0xec004000 0x1000>,
> +			      <0xec005000 0x1000>,
> +			      <0xec000000 0x1000>;

reg is second
> +			reg-names = "gpio0", "gpio1", "gpio2", "iomux";
> +			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> +			amb,pull-regmap = <&scratchpad_syscon 0x14 0x30>;
> +			amb,ds-regmap = <&rct_syscon>;
> +
> +			gpio: gpio@0 {
> +				reg = <0>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				gpio-ranges = <&pinctrl 0 0 86>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			uart0_pins: uart0@0 {
> +				reg = <0>;

Why do you have unit addresses here? What is this?

> +				amb,pinmux-ids = <0x100a 0x100b>;

This will need more explanation... your bindings are not ready for
review, so we will get to this later when you rewrite your bindings and
test them before sending.

> +			};
> +
> +			snand0_pins_a: snand0@0 {
> +				reg = <0>;
> +				amb,pinmux-ids = <0x2024 0x2025 0x202a 0x202b
> +						  0x202c 0x202d>;
> +			};
> +
> +			snand0_pins_b: snand0@1 {
> +				reg = <1>;
> +				amb,pinmux-ids = <0x4036 0x4037 0x4038 0x4039
> +						  0x403a 0x403b>;
> +			};
> +		};
> +	};
> +
> +	n_ahb@e0000000 { /* Non-Secure AHB, but configurable */

bus

> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0xe0000000 0x01000000>;

reg is a second property.

> +		ranges;
> +
> +		cpuid_syscon: cpuid@e0000000 {
> +			compatible = "ambarella,cpuid", "syscon";
> +			reg = <0xe0000000 0x1000>;
> +		};
> +
> +		nand0: nand@e0002000 {
> +			compatible = "ambarella,nand";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0xe0002000 0x1000>;

ditto

> +			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;	/* fio_irq */
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&snand0_pins_a>;
> +			clocks = <&pll_out_enet>;
> +			nand-on-flash-bbt;
> +			/* amb,soft-ecc = <6>; */

Drop dead code

> +		};
> +
> +		scratchpad_syscon: scratchpad_syscon@e0022000 {
> +			compatible = "ambarella,scratchpad", "syscon";
> +			reg = <0xe0022000 0x100>;
> +		};
> +	};
> +
> +	rct@ed080000 {

bus

> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0xed080000 0x1000>;
> +		ranges;
> +
> +		rct_syscon: rct_syscon@ed080000 {

syscon
(no underscores in node names, generic node names)

> +			compatible = "ambarella,rct", "syscon";
> +			reg = <0xed080000 0x1000>;
> +		};
> +	};
> +
> +	clocks {
> +		compatible = "ambarella,clkpll-v0";

Nope, nope. Register proper clock controller.


> +		#address-cells = <1>;
> +		#size-cells = <1>;

Why? You do not have any children with unit addresses.
> +
> +		/*
> +		 * This is a dummy clock, to be used as placeholder on other
> +		 * mux clocks when corresponding bits in register don't
> +		 * represent real parent clock.
> +		 */
> +		gclk_dummy: gclk_dummy {

NAK. Register proper clock controller.

> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +			clock-frequency = <0>;
> +		};
> +
> +		/*
> +		 * Fixed 24MHz oscillator inputs to SoC
> +		 */
> +		osc: oscillator {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <24000000>;

This is actually the only clock which makes sense, but it is not a
property of SoC. Put it with the board DTS. At least frequency goes
there to note it.

> +			clock-output-names = "osc";
> +		};
> +
> +		gclk_core: gclk-core {

NAK here and for all other weird nodes below

> +			#clock-cells = <0>;
> +			compatible = "ambarella,pll-clock";
> +			clocks = <&osc>;
> +			clock-output-names = "gclk_core";
> +			amb,clk-regmap = <&rct_syscon 0x000 0x004 0x100 0x104 0x000 0x000>;
> +		};
> +
> +		gclk_ddr: gclk-ddr {
> +			#clock-cells = <0>;
> +			compatible = "ambarella,pll-clock";
> +			clocks = <&osc>;
> +			clock-output-names = "gclk_ddr";
> +			amb,clk-regmap = <&rct_syscon 0x0dc 0x0e0 0x110 0x114 0x000 0x000>;
> +			amb,fix-divider = <2>;
> +		};
> +
> +		gclk_cortex: gclk-cortex {
> +			#clock-cells = <0>;
> +			compatible = "ambarella,pll-clock";
> +			clocks = <&osc>;
> +			clock-output-names = "gclk_cortex";
> +			amb,clk-regmap = <&rct_syscon 0x264 0x268 0x26c 0x270 0x000 0x000>;
> +		};
> +
> +		gclk_axi: gclk-axi {
> +			#clock-cells = <0>;
> +			compatible = "fixed-factor-clock";
> +			clocks = <&gclk_cortex>;
> +			clock-output-names = "gclk_axi";
> +			clock-mult = <1>;
> +			clock-div = <3>;
> +		};
> +
> +		gclk_so: gclk-so {
> +			#clock-cells = <0>;
> +			compatible = "ambarella,pll-clock";
> +			clocks = <&osc>;
> +			clock-output-names = "gclk_so";
> +			assigned-clocks = <&gclk_so>;
> +			assigned-clock-rates = <24000000>;
> +			amb,clk-regmap = <&rct_syscon 0x024 0x028 0x11c 0x120 0x04c 0x030>;
> +			amb,frac-mode;
> +		};
> +
> +		pll_out_vo2: pll-out-vo2 {
> +			#clock-cells = <0>;
> +			compatible = "ambarella,pll-clock";
> +			clocks = <&osc>;
> +			clock-output-names = "pll_out_vo2";
> +			assigned-clocks = <&pll_out_vo2>;
> +			assigned-clock-rates = <24000000>;
> +			amb,clk-regmap = <&rct_syscon 0x0c0 0x0c4 0x13c 0x140 0x0c8 0x000>;
> +			amb,frac-mode;
> +		};
> +
> +		pll_out_sd: pll-out-sd {
> +			#clock-cells = <0>;
> +			compatible = "ambarella,pll-clock";
> +			clocks = <&osc>;
> +			clock-output-names = "pll_out_sd";
> +			amb,clk-regmap = <&rct_syscon 0x4ac 0x4b0 0x4b4 0x4b8 0x000 0x000>;
> +		};
> +		pll_out_enet: pll-out-enet {
> +			#clock-cells = <0>;
> +			compatible = "ambarella,pll-clock";
> +			clocks = <&osc>;
> +			clock-output-names = "pll_out_enet";
> +			amb,clk-regmap = <&rct_syscon 0x520 0x524 0x528 0x52c 0x000 0x000>;
> +		};
> +		gclk_uart0: gclk-uart0 {
> +			#clock-cells = <0>;
> +			compatible = "ambarella,composite-clock";
> +			clocks = <&osc>, <&gclk_core>, <&pll_out_enet>, <&pll_out_sd>;
> +			clock-output-names = "gclk_uart0";
> +			assigned-clocks = <&gclk_uart0>;
> +			assigned-clock-parents = <&osc>;
> +			assigned-clock-rates = <24000000>;
> +			amb,mux-regmap = <&rct_syscon 0x1c8>;
> +			amb,div-regmap = <&rct_syscon 0x038>;
> +			amb,div-width = <24>;
> +			amb,div-shift = <0>;
> +		};
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/ambarella/s6lm_pineapple.dts b/arch/arm64/boot/dts/ambarella/s6lm_pineapple.dts
> new file mode 100644
> index 000000000000..2d5d6d18e738
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ambarella/s6lm_pineapple.dts
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2023 Ambarella,Inc. - http://www.ambarella.com/
> + * Author: Cao Rongrong <rrcao@ambarella.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +/dts-v1/;
> +
> +#include "ambarella-s6lm.dtsi"
> +
> +/ {
> +	model = "Ambarella S6LM Pineapple Board";
> +	compatible = "ambarella,s6lm";

Missing board compatible.

> +
> +	chosen {
> +		bootargs = "console=ttyS0 ubi.mtd=lnx root=ubi0:rootfs rw
> +			rootfstype=ubifs init=/linuxrc";

Drop bootargs. These should not be needed in DTS. Otherwise - why do you
need them? Why bootloader cannot provide these?

> +	};
> +
> +	n_apb@e4000000 {
> +		i2c1: i2c@e4009000 {

No, use override by phandle/label.

> +			status = "ok";
> +		};
> +	};
> +};

Best regards,
Krzysztof

Re: [PATCH 15/15] arm64: dts: ambarella: introduce Ambarella s6lm SoC

[Krzysztof Kozlowski]

On 23/01/2023 08:32, Li Chen wrote:
> This patch adds s6lm's devicetree.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: Idc7a04cc64a53b3296bc9fcf9dd3cd648ebefeae
> ---
>  MAINTAINERS                                   |   2 +
>  .../boot/dts/ambarella/ambarella-s6lm.dtsi    | 332 ++++++++++++++++++
>  .../boot/dts/ambarella/s6lm_pineapple.dts     |  29 ++
>  3 files changed, 363 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/ambarella/ambarella-s6lm.dtsi
>  create mode 100644 arch/arm64/boot/dts/ambarella/s6lm_pineapple.dts
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1360fe2f4236..d9d1033b6452 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1894,6 +1894,8 @@ ARM/Ambarella SoC support
>  M:	Li Chen <me@linux.beauty>
>  L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
>  S:	Supported
> +F:	arch/arm64/boot/dts/ambarella/ambarella-s6lm.dts
> +F:	arch/arm64/boot/dts/ambarella/ambarella-s6lm.dtsi
>  F:	Documentation/devicetree/bindings/arm/ambarella.yaml
>  F:	Documentation/devicetree/bindings/arm/ambarella/ambarella,cpuid.yaml
>  F:	Documentation/devicetree/bindings/arm/ambarella/ambarella,rct.yaml
> diff --git a/arch/arm64/boot/dts/ambarella/ambarella-s6lm.dtsi b/arch/arm64/boot/dts/ambarella/ambarella-s6lm.dtsi
> new file mode 100644
> index 000000000000..c3fa77b33e04
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ambarella/ambarella-s6lm.dtsi
> @@ -0,0 +1,332 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2023 Ambarella,Inc. - http://www.ambarella.com/
> + * Author: Cao Rongrong <rrcao@ambarella.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.

Drop boilerplate.

> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	compatible = "ambarella,s6lm";
> +	interrupt-parent = <&gic>;
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	aliases {
> +		serial0 = &uart0;
> +		nand = &nand0;
> +	};
> +
> +	chosen {
> +		stdout-path = &uart0;
> +	};
> +
> +	/*
> +	 * the memory node will be overwritten in Amboot,
> +	 * here is just the default value.
> +	 */
> +	memory {
> +		device_type = "memory";
> +		reg = <0x00200000 0x07e00000>; /* 126M */
> +	};
> +
> +	reserved-memory {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-0.2";
> +		method = "smc";
> +	};
> +
> +	pmu {
> +		compatible = "arm,cortex-a53-pmu";
> +		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +			     <0 5 0x4>,

??? Just compare these two lines above...

> +			     <0 6 0x4>,
> +			     <0 7 0x4>;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		cpu@0 {
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <0x0>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu@1 {
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <0x1>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu@2 {
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <0x2>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu@3 {
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <0x3>;
> +			enable-method = "psci";
> +		};
> +	};
> +
> +	gic: interrupt-controller@f3000000 {
> +		compatible = "arm,gic-400";

reg should be second property.

> +		#interrupt-cells = <3>;
> +		#address-cells = <0>;
> +		interrupt-controller;
> +		reg = <0xf3001000 0x1000>,	/* GIC Dist */
> +		      <0xf3002000 0x2000>,	/* GIC CPU */
> +		      /* following are not used if no virtulization */
> +		      <0xf3004000 0x2000>,	/* GIC VCPU Control */
> +		      <0xf3006000 0x2000>;	/* GIC VCPU */
> +		interrupts = <GIC_PPI 9 0xf04>;	/* GIC Maintenence IRQ */
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13 0xf08>,	/* Secure Phys IRQ */
> +			     <1 14 0xf08>,	/* Non-secure Phys IRQ */

And you do not see here anything odd?

> +			     <1 11 0xf08>,	/* Virt IRQ */
> +			     <1 10 0xf08>;	/* Hyp IRQ */
> +	};
> +
> +	n_apb@e4000000 { /* Non-Secure APB, but configurable */

No underscores in node names. Generic node names, so just "bus"

> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0xe4000000 0x01000000>;
> +		ranges;
> +
> +		uart0: uart@e4000000 {

serial

> +			compatible = "ambarella,uart";
> +			reg = <0xe4000000 0x1000>;
> +			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&uart0_pins>;
> +			clocks = <&gclk_uart0>;
> +			amb,ignore-fe;
> +			status = "ok";
> +		};
> +	};
> +
> +	s_apb@ec000000 { /* Secure APB, but configurable */

bus

> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0xec000000 0x01000000>;

reg is second property

> +		ranges;
> +
> +		pinctrl: pinctrl@0xec003000 {
> +			compatible = "ambarella,pinctrl";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0xec003000 0x1000>,
> +			      <0xec004000 0x1000>,
> +			      <0xec005000 0x1000>,
> +			      <0xec000000 0x1000>;

reg is second
> +			reg-names = "gpio0", "gpio1", "gpio2", "iomux";
> +			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> +			amb,pull-regmap = <&scratchpad_syscon 0x14 0x30>;
> +			amb,ds-regmap = <&rct_syscon>;
> +
> +			gpio: gpio@0 {
> +				reg = <0>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				gpio-ranges = <&pinctrl 0 0 86>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			uart0_pins: uart0@0 {
> +				reg = <0>;

Why do you have unit addresses here? What is this?

> +				amb,pinmux-ids = <0x100a 0x100b>;

This will need more explanation... your bindings are not ready for
review, so we will get to this later when you rewrite your bindings and
test them before sending.

> +			};
> +
> +			snand0_pins_a: snand0@0 {
> +				reg = <0>;
> +				amb,pinmux-ids = <0x2024 0x2025 0x202a 0x202b
> +						  0x202c 0x202d>;
> +			};
> +
> +			snand0_pins_b: snand0@1 {
> +				reg = <1>;
> +				amb,pinmux-ids = <0x4036 0x4037 0x4038 0x4039
> +						  0x403a 0x403b>;
> +			};
> +		};
> +	};
> +
> +	n_ahb@e0000000 { /* Non-Secure AHB, but configurable */

bus

> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0xe0000000 0x01000000>;

reg is a second property.

> +		ranges;
> +
> +		cpuid_syscon: cpuid@e0000000 {
> +			compatible = "ambarella,cpuid", "syscon";
> +			reg = <0xe0000000 0x1000>;
> +		};
> +
> +		nand0: nand@e0002000 {
> +			compatible = "ambarella,nand";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0xe0002000 0x1000>;

ditto

> +			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;	/* fio_irq */
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&snand0_pins_a>;
> +			clocks = <&pll_out_enet>;
> +			nand-on-flash-bbt;
> +			/* amb,soft-ecc = <6>; */

Drop dead code

> +		};
> +
> +		scratchpad_syscon: scratchpad_syscon@e0022000 {
> +			compatible = "ambarella,scratchpad", "syscon";
> +			reg = <0xe0022000 0x100>;
> +		};
> +	};
> +
> +	rct@ed080000 {

bus

> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0xed080000 0x1000>;
> +		ranges;
> +
> +		rct_syscon: rct_syscon@ed080000 {

syscon
(no underscores in node names, generic node names)

> +			compatible = "ambarella,rct", "syscon";
> +			reg = <0xed080000 0x1000>;
> +		};
> +	};
> +
> +	clocks {
> +		compatible = "ambarella,clkpll-v0";

Nope, nope. Register proper clock controller.


> +		#address-cells = <1>;
> +		#size-cells = <1>;

Why? You do not have any children with unit addresses.
> +
> +		/*
> +		 * This is a dummy clock, to be used as placeholder on other
> +		 * mux clocks when corresponding bits in register don't
> +		 * represent real parent clock.
> +		 */
> +		gclk_dummy: gclk_dummy {

NAK. Register proper clock controller.

> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +			clock-frequency = <0>;
> +		};
> +
> +		/*
> +		 * Fixed 24MHz oscillator inputs to SoC
> +		 */
> +		osc: oscillator {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <24000000>;

This is actually the only clock which makes sense, but it is not a
property of SoC. Put it with the board DTS. At least frequency goes
there to note it.

> +			clock-output-names = "osc";
> +		};
> +
> +		gclk_core: gclk-core {

NAK here and for all other weird nodes below

> +			#clock-cells = <0>;
> +			compatible = "ambarella,pll-clock";
> +			clocks = <&osc>;
> +			clock-output-names = "gclk_core";
> +			amb,clk-regmap = <&rct_syscon 0x000 0x004 0x100 0x104 0x000 0x000>;
> +		};
> +
> +		gclk_ddr: gclk-ddr {
> +			#clock-cells = <0>;
> +			compatible = "ambarella,pll-clock";
> +			clocks = <&osc>;
> +			clock-output-names = "gclk_ddr";
> +			amb,clk-regmap = <&rct_syscon 0x0dc 0x0e0 0x110 0x114 0x000 0x000>;
> +			amb,fix-divider = <2>;
> +		};
> +
> +		gclk_cortex: gclk-cortex {
> +			#clock-cells = <0>;
> +			compatible = "ambarella,pll-clock";
> +			clocks = <&osc>;
> +			clock-output-names = "gclk_cortex";
> +			amb,clk-regmap = <&rct_syscon 0x264 0x268 0x26c 0x270 0x000 0x000>;
> +		};
> +
> +		gclk_axi: gclk-axi {
> +			#clock-cells = <0>;
> +			compatible = "fixed-factor-clock";
> +			clocks = <&gclk_cortex>;
> +			clock-output-names = "gclk_axi";
> +			clock-mult = <1>;
> +			clock-div = <3>;
> +		};
> +
> +		gclk_so: gclk-so {
> +			#clock-cells = <0>;
> +			compatible = "ambarella,pll-clock";
> +			clocks = <&osc>;
> +			clock-output-names = "gclk_so";
> +			assigned-clocks = <&gclk_so>;
> +			assigned-clock-rates = <24000000>;
> +			amb,clk-regmap = <&rct_syscon 0x024 0x028 0x11c 0x120 0x04c 0x030>;
> +			amb,frac-mode;
> +		};
> +
> +		pll_out_vo2: pll-out-vo2 {
> +			#clock-cells = <0>;
> +			compatible = "ambarella,pll-clock";
> +			clocks = <&osc>;
> +			clock-output-names = "pll_out_vo2";
> +			assigned-clocks = <&pll_out_vo2>;
> +			assigned-clock-rates = <24000000>;
> +			amb,clk-regmap = <&rct_syscon 0x0c0 0x0c4 0x13c 0x140 0x0c8 0x000>;
> +			amb,frac-mode;
> +		};
> +
> +		pll_out_sd: pll-out-sd {
> +			#clock-cells = <0>;
> +			compatible = "ambarella,pll-clock";
> +			clocks = <&osc>;
> +			clock-output-names = "pll_out_sd";
> +			amb,clk-regmap = <&rct_syscon 0x4ac 0x4b0 0x4b4 0x4b8 0x000 0x000>;
> +		};
> +		pll_out_enet: pll-out-enet {
> +			#clock-cells = <0>;
> +			compatible = "ambarella,pll-clock";
> +			clocks = <&osc>;
> +			clock-output-names = "pll_out_enet";
> +			amb,clk-regmap = <&rct_syscon 0x520 0x524 0x528 0x52c 0x000 0x000>;
> +		};
> +		gclk_uart0: gclk-uart0 {
> +			#clock-cells = <0>;
> +			compatible = "ambarella,composite-clock";
> +			clocks = <&osc>, <&gclk_core>, <&pll_out_enet>, <&pll_out_sd>;
> +			clock-output-names = "gclk_uart0";
> +			assigned-clocks = <&gclk_uart0>;
> +			assigned-clock-parents = <&osc>;
> +			assigned-clock-rates = <24000000>;
> +			amb,mux-regmap = <&rct_syscon 0x1c8>;
> +			amb,div-regmap = <&rct_syscon 0x038>;
> +			amb,div-width = <24>;
> +			amb,div-shift = <0>;
> +		};
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/ambarella/s6lm_pineapple.dts b/arch/arm64/boot/dts/ambarella/s6lm_pineapple.dts
> new file mode 100644
> index 000000000000..2d5d6d18e738
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ambarella/s6lm_pineapple.dts
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2023 Ambarella,Inc. - http://www.ambarella.com/
> + * Author: Cao Rongrong <rrcao@ambarella.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +/dts-v1/;
> +
> +#include "ambarella-s6lm.dtsi"
> +
> +/ {
> +	model = "Ambarella S6LM Pineapple Board";
> +	compatible = "ambarella,s6lm";

Missing board compatible.

> +
> +	chosen {
> +		bootargs = "console=ttyS0 ubi.mtd=lnx root=ubi0:rootfs rw
> +			rootfstype=ubifs init=/linuxrc";

Drop bootargs. These should not be needed in DTS. Otherwise - why do you
need them? Why bootloader cannot provide these?

> +	};
> +
> +	n_apb@e4000000 {
> +		i2c1: i2c@e4009000 {

No, use override by phandle/label.

> +			status = "ok";
> +		};
> +	};
> +};

Best regards,
Krzysztof


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Re: [PATCH 06/15] soc: add Ambarella driver

[Arnd Bergmann]

On Mon, Jan 23, 2023, at 08:32, Li Chen wrote:
> This driver add soc_id support for Ambarella,
> which is stored inside "cpuid" AXI address mapping.
>
> Also provide sys_config(POC, aka power on configuration)
> for other drivers.
>
> Signed-off-by: Li Chen <lchen@ambarella.com>

The soc_id support looks ok

> Change-Id: I4869a3497366ac7779e792835f8e0309239036a8

Please drop these lines in the submission, the IDs are
not reachable outside of your own git, so we don't want
these to show up in the public history.

> +static struct ambarella_soc_id {
> +	unsigned int id;
> +	const char *name;
> +	const char *family;
> +} soc_ids[] = {
> +	{ 0x00483245, "s6lm",  "10nm", },
> +};

I would suggest something more descriptive in the "family"
field to let users know they are on an Ambarella SoC.

Maybe just "Ambarella 10nm".

> +static int __init ambarella_socinfo_init(void)
> +{
> +	struct soc_device_attribute *soc_dev_attr;
> +	struct soc_device *soc_dev;
> +	struct device_node *np;
> +	struct regmap *cpuid_regmap;
> +	unsigned int soc_id;
> +
> +	cpuid_regmap = syscon_regmap_lookup_by_compatible("ambarella,cpuid");
> +	if (IS_ERR(cpuid_regmap))
> +		return PTR_ERR(cpuid_regmap);

Is there anything else in this syscon node? If the block
of registers only contains the identification bits, you
could just make this file a platform_driver that binds to
the node instead of using a syscon.

If there are other unrelated registers in there, the compatible
string should probably be changed to better describe the
entire area based on the name in the datasheet.

> +static unsigned int ambsys_config;
> +
> +unsigned int ambarella_sys_config(void)
> +{
> +	return ambsys_config;
> +}
> +EXPORT_SYMBOL(ambarella_sys_config);

Which drivers use this bit? Can they be changed to 
use soc_device_match() instead to avoid the export?

> +static int __init ambarella_soc_init(void)
> +{
> +	struct regmap *rct_regmap;
> +	int ret;
> +
> +	rct_regmap = syscon_regmap_lookup_by_compatible("ambarella,rct");
> +	if (IS_ERR(rct_regmap)) {
> +		pr_err("failed to get ambarella rct regmap\n");
> +		return PTR_ERR(rct_regmap);
> +	}
...
> +arch_initcall(ambarella_soc_init);

It is not an error to use a chip from another manufacturer,
please drop the pr_err() and return success here.

> +#ifndef __SOC_AMBARELLA_MISC_H__
> +#define __SOC_AMBARELLA_MISC_H__
> +
> +extern unsigned int ambarella_sys_config(void);
> +extern struct proc_dir_entry *ambarella_proc_dir(void);
> +

The ambarella_proc_dir looks like a stale entry that should be
removed. Ideally you should not need a private header at all.

    Arnd

Re: [PATCH 06/15] soc: add Ambarella driver

[Arnd Bergmann]

On Mon, Jan 23, 2023, at 08:32, Li Chen wrote:
> This driver add soc_id support for Ambarella,
> which is stored inside "cpuid" AXI address mapping.
>
> Also provide sys_config(POC, aka power on configuration)
> for other drivers.
>
> Signed-off-by: Li Chen <lchen@ambarella.com>

The soc_id support looks ok

> Change-Id: I4869a3497366ac7779e792835f8e0309239036a8

Please drop these lines in the submission, the IDs are
not reachable outside of your own git, so we don't want
these to show up in the public history.

> +static struct ambarella_soc_id {
> +	unsigned int id;
> +	const char *name;
> +	const char *family;
> +} soc_ids[] = {
> +	{ 0x00483245, "s6lm",  "10nm", },
> +};

I would suggest something more descriptive in the "family"
field to let users know they are on an Ambarella SoC.

Maybe just "Ambarella 10nm".

> +static int __init ambarella_socinfo_init(void)
> +{
> +	struct soc_device_attribute *soc_dev_attr;
> +	struct soc_device *soc_dev;
> +	struct device_node *np;
> +	struct regmap *cpuid_regmap;
> +	unsigned int soc_id;
> +
> +	cpuid_regmap = syscon_regmap_lookup_by_compatible("ambarella,cpuid");
> +	if (IS_ERR(cpuid_regmap))
> +		return PTR_ERR(cpuid_regmap);

Is there anything else in this syscon node? If the block
of registers only contains the identification bits, you
could just make this file a platform_driver that binds to
the node instead of using a syscon.

If there are other unrelated registers in there, the compatible
string should probably be changed to better describe the
entire area based on the name in the datasheet.

> +static unsigned int ambsys_config;
> +
> +unsigned int ambarella_sys_config(void)
> +{
> +	return ambsys_config;
> +}
> +EXPORT_SYMBOL(ambarella_sys_config);

Which drivers use this bit? Can they be changed to 
use soc_device_match() instead to avoid the export?

> +static int __init ambarella_soc_init(void)
> +{
> +	struct regmap *rct_regmap;
> +	int ret;
> +
> +	rct_regmap = syscon_regmap_lookup_by_compatible("ambarella,rct");
> +	if (IS_ERR(rct_regmap)) {
> +		pr_err("failed to get ambarella rct regmap\n");
> +		return PTR_ERR(rct_regmap);
> +	}
...
> +arch_initcall(ambarella_soc_init);

It is not an error to use a chip from another manufacturer,
please drop the pr_err() and return success here.

> +#ifndef __SOC_AMBARELLA_MISC_H__
> +#define __SOC_AMBARELLA_MISC_H__
> +
> +extern unsigned int ambarella_sys_config(void);
> +extern struct proc_dir_entry *ambarella_proc_dir(void);
> +

The ambarella_proc_dir looks like a stale entry that should be
removed. Ideally you should not need a private header at all.

    Arnd

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Re: [PATCH 06/15] soc: add Ambarella driver

[Li Chen]

Hi Arnd,

On Mon, 23 Jan 2023 16:29:06 +0800,
Arnd Bergmann wrote:
>
> On Mon, Jan 23, 2023, at 08:32, Li Chen wrote:
> > This driver add soc_id support for Ambarella,
> > which is stored inside "cpuid" AXI address mapping.
> >
> > Also provide sys_config(POC, aka power on configuration)
> > for other drivers.
> >
> > Signed-off-by: Li Chen <lchen@ambarella.com>
>
> The soc_id support looks ok
>
> > Change-Id: I4869a3497366ac7779e792835f8e0309239036a8
>
> Please drop these lines in the submission, the IDs are
> not reachable outside of your own git, so we don't want
> these to show up in the public history.

Sorry, I forgot to remove this.

> > +static struct ambarella_soc_id {
> > +	unsigned int id;
> > +	const char *name;
> > +	const char *family;
> > +} soc_ids[] = {
> > +	{ 0x00483245, "s6lm",  "10nm", },
> > +};
>
> I would suggest something more descriptive in the "family"
> field to let users know they are on an Ambarella SoC.
>
> Maybe just "Ambarella 10nm".

There is a "pr_info("Ambarella SoC %s detected\n", soc_dev_attr->soc_id);" in this file,
I think this should be enough, right?

> > +static int __init ambarella_socinfo_init(void)
> > +{
> > +	struct soc_device_attribute *soc_dev_attr;
> > +	struct soc_device *soc_dev;
> > +	struct device_node *np;
> > +	struct regmap *cpuid_regmap;
> > +	unsigned int soc_id;
> > +
> > +	cpuid_regmap = syscon_regmap_lookup_by_compatible("ambarella,cpuid");
> > +	if (IS_ERR(cpuid_regmap))
> > +		return PTR_ERR(cpuid_regmap);
>
> Is there anything else in this syscon node? If the block
> of registers only contains the identification bits, you
> could just make this file a platform_driver that binds to
> the node instead of using a syscon.
>
> If there are other unrelated registers in there, the compatible
> string should probably be changed to better describe the
> entire area based on the name in the datasheet.

Yeah, this block is only used for identification bits. In datasheet,
it is also named "CPU ID".

Other than cpuid_regmap, this driver also looks for "model" name as soc machine name:
of_property_read_string(np, "model", &soc_dev_attr->machine);

So I think it is not a good idea to conver it to into a platform driver.

As for "syscon", I think it is still very helpful to get regmap easily. Generally speaking,
I prefer regmap over void*, because it has debugfs support, so I can get its value more easily.

> > +static unsigned int ambsys_config;
> > +
> > +unsigned int ambarella_sys_config(void)
> > +{
> > +	return ambsys_config;
> > +}
> > +EXPORT_SYMBOL(ambarella_sys_config);
>
> Which drivers use this bit? Can they be changed to
> use soc_device_match() instead to avoid the export?

sys_config is used by our nand and sd drivers. I also don't want to export,
but struct soc_device_attribute/soc_device don't have private data to store it,
I think there is no better way.

> > +static int __init ambarella_soc_init(void)
> > +{
> > +	struct regmap *rct_regmap;
> > +	int ret;
> > +
> > +	rct_regmap = syscon_regmap_lookup_by_compatible("ambarella,rct");
> > +	if (IS_ERR(rct_regmap)) {
> > +		pr_err("failed to get ambarella rct regmap\n");
> > +		return PTR_ERR(rct_regmap);
> > +	}
> ...
> > +arch_initcall(ambarella_soc_init);
>
> It is not an error to use a chip from another manufacturer,
> please drop the pr_err() and return success here.

Ok, good to know, thanks. But we don't have other manufacturers at least for now,
and rct_regmap is need to be updated here, like sys_config and soft reboot. So I think
this rct regmap is still needed.

> > +#ifndef __SOC_AMBARELLA_MISC_H__
> > +#define __SOC_AMBARELLA_MISC_H__
> > +
> > +extern unsigned int ambarella_sys_config(void);
> > +extern struct proc_dir_entry *ambarella_proc_dir(void);
> > +
>
> The ambarella_proc_dir looks like a stale entry that should be
> removed. Ideally you should not need a private header at all.

Oops, my bad. I will remove proc dir in v2.

Regards,
Li

Re: [PATCH 06/15] soc: add Ambarella driver

[Li Chen]

Hi Arnd,

On Mon, 23 Jan 2023 16:29:06 +0800,
Arnd Bergmann wrote:
>
> On Mon, Jan 23, 2023, at 08:32, Li Chen wrote:
> > This driver add soc_id support for Ambarella,
> > which is stored inside "cpuid" AXI address mapping.
> >
> > Also provide sys_config(POC, aka power on configuration)
> > for other drivers.
> >
> > Signed-off-by: Li Chen <lchen@ambarella.com>
>
> The soc_id support looks ok
>
> > Change-Id: I4869a3497366ac7779e792835f8e0309239036a8
>
> Please drop these lines in the submission, the IDs are
> not reachable outside of your own git, so we don't want
> these to show up in the public history.

Sorry, I forgot to remove this.

> > +static struct ambarella_soc_id {
> > +	unsigned int id;
> > +	const char *name;
> > +	const char *family;
> > +} soc_ids[] = {
> > +	{ 0x00483245, "s6lm",  "10nm", },
> > +};
>
> I would suggest something more descriptive in the "family"
> field to let users know they are on an Ambarella SoC.
>
> Maybe just "Ambarella 10nm".

There is a "pr_info("Ambarella SoC %s detected\n", soc_dev_attr->soc_id);" in this file,
I think this should be enough, right?

> > +static int __init ambarella_socinfo_init(void)
> > +{
> > +	struct soc_device_attribute *soc_dev_attr;
> > +	struct soc_device *soc_dev;
> > +	struct device_node *np;
> > +	struct regmap *cpuid_regmap;
> > +	unsigned int soc_id;
> > +
> > +	cpuid_regmap = syscon_regmap_lookup_by_compatible("ambarella,cpuid");
> > +	if (IS_ERR(cpuid_regmap))
> > +		return PTR_ERR(cpuid_regmap);
>
> Is there anything else in this syscon node? If the block
> of registers only contains the identification bits, you
> could just make this file a platform_driver that binds to
> the node instead of using a syscon.
>
> If there are other unrelated registers in there, the compatible
> string should probably be changed to better describe the
> entire area based on the name in the datasheet.

Yeah, this block is only used for identification bits. In datasheet,
it is also named "CPU ID".

Other than cpuid_regmap, this driver also looks for "model" name as soc machine name:
of_property_read_string(np, "model", &soc_dev_attr->machine);

So I think it is not a good idea to conver it to into a platform driver.

As for "syscon", I think it is still very helpful to get regmap easily. Generally speaking,
I prefer regmap over void*, because it has debugfs support, so I can get its value more easily.

> > +static unsigned int ambsys_config;
> > +
> > +unsigned int ambarella_sys_config(void)
> > +{
> > +	return ambsys_config;
> > +}
> > +EXPORT_SYMBOL(ambarella_sys_config);
>
> Which drivers use this bit? Can they be changed to
> use soc_device_match() instead to avoid the export?

sys_config is used by our nand and sd drivers. I also don't want to export,
but struct soc_device_attribute/soc_device don't have private data to store it,
I think there is no better way.

> > +static int __init ambarella_soc_init(void)
> > +{
> > +	struct regmap *rct_regmap;
> > +	int ret;
> > +
> > +	rct_regmap = syscon_regmap_lookup_by_compatible("ambarella,rct");
> > +	if (IS_ERR(rct_regmap)) {
> > +		pr_err("failed to get ambarella rct regmap\n");
> > +		return PTR_ERR(rct_regmap);
> > +	}
> ...
> > +arch_initcall(ambarella_soc_init);
>
> It is not an error to use a chip from another manufacturer,
> please drop the pr_err() and return success here.

Ok, good to know, thanks. But we don't have other manufacturers at least for now,
and rct_regmap is need to be updated here, like sys_config and soft reboot. So I think
this rct regmap is still needed.

> > +#ifndef __SOC_AMBARELLA_MISC_H__
> > +#define __SOC_AMBARELLA_MISC_H__
> > +
> > +extern unsigned int ambarella_sys_config(void);
> > +extern struct proc_dir_entry *ambarella_proc_dir(void);
> > +
>
> The ambarella_proc_dir looks like a stale entry that should be
> removed. Ideally you should not need a private header at all.

Oops, my bad. I will remove proc dir in v2.

Regards,
Li

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Re: [PATCH 06/15] soc: add Ambarella driver

[Arnd Bergmann]

On Tue, Jan 24, 2023, at 08:58, Li Chen wrote:
> On Mon, 23 Jan 2023 16:29:06 +0800,
> Arnd Bergmann wrote:
>> On Mon, Jan 23, 2023, at 08:32, Li Chen wrote:
>> > +static struct ambarella_soc_id {
>> > +	unsigned int id;
>> > +	const char *name;
>> > +	const char *family;
>> > +} soc_ids[] = {
>> > +	{ 0x00483245, "s6lm",  "10nm", },
>> > +};
>>
>> I would suggest something more descriptive in the "family"
>> field to let users know they are on an Ambarella SoC.
>>
>> Maybe just "Ambarella 10nm".
>
> There is a "pr_info("Ambarella SoC %s detected\n", 
> soc_dev_attr->soc_id);" in this file,
> I think this should be enough, right?

The pr_info() can probably be removed here, or reworded
based on the changed contents, those are just meant for
humans reading through the log rather than parsed by
software.

The soc_id fields on the other hand need to be parsable
by scripts looking at the sysfs files, in a way that lets
them identify the system. Usually the script would look
at the "family" as the primary key before looking up the
"name", so you have to make sure that the family uniquely
identifies this as one of yours rather than a 10nm chip
from some other company.

>> If there are other unrelated registers in there, the compatible
>> string should probably be changed to better describe the
>> entire area based on the name in the datasheet.
>
> Yeah, this block is only used for identification bits. In datasheet,
> it is also named "CPU ID".

ok.

> Other than cpuid_regmap, this driver also looks for "model" name as soc 
> machine name:
> of_property_read_string(np, "model", &soc_dev_attr->machine);
>
> So I think it is not a good idea to conver it to into a platform driver.

I don't understand what you mean. A lot of soc_id drivers put
the model string into soc_dev_attr->machine, this makes no
difference here.

> As for "syscon", I think it is still very helpful to get regmap easily. 
> Generally speaking,
> I prefer regmap over void*, because it has debugfs support, so I can 
> get its value more easily.

What value would you get through debugfs that is not already in
the soc_device?

>> > +static unsigned int ambsys_config;
>> > +
>> > +unsigned int ambarella_sys_config(void)
>> > +{
>> > +	return ambsys_config;
>> > +}
>> > +EXPORT_SYMBOL(ambarella_sys_config);
>>
>> Which drivers use this bit? Can they be changed to
>> use soc_device_match() instead to avoid the export?
>
> sys_config is used by our nand and sd drivers. I also don't want to export,
> but struct soc_device_attribute/soc_device don't have private data to store it,
> I think there is no better way.

The nand and sd drivers should not rely on any private data
from another driver. What information do they actually
need here that is not already in their own DT nodes or
in the soc_device_attributes?

>> > +static int __init ambarella_soc_init(void)
>> > +{
>> > +	struct regmap *rct_regmap;
>> > +	int ret;
>> > +
>> > +	rct_regmap = syscon_regmap_lookup_by_compatible("ambarella,rct");
>> > +	if (IS_ERR(rct_regmap)) {
>> > +		pr_err("failed to get ambarella rct regmap\n");
>> > +		return PTR_ERR(rct_regmap);
>> > +	}
>> ...
>> > +arch_initcall(ambarella_soc_init);
>>
>> It is not an error to use a chip from another manufacturer,
>> please drop the pr_err() and return success here.
>
> Ok, good to know, thanks. But we don't have other manufacturers at 
> least for now,

I care a lot about supporting multiple SoC vendors, it would seem
very rude to assume that we stop supporting everything else after
merging Ambarella support.

> and rct_regmap is need to be updated here, like sys_config and soft 
> reboot. So I think this rct regmap is still needed.

It is certainly only needed on Ambarella SoCs, no other one
has this device at the moment.

      Arnd

Re: [PATCH 06/15] soc: add Ambarella driver

[Arnd Bergmann]

On Tue, Jan 24, 2023, at 08:58, Li Chen wrote:
> On Mon, 23 Jan 2023 16:29:06 +0800,
> Arnd Bergmann wrote:
>> On Mon, Jan 23, 2023, at 08:32, Li Chen wrote:
>> > +static struct ambarella_soc_id {
>> > +	unsigned int id;
>> > +	const char *name;
>> > +	const char *family;
>> > +} soc_ids[] = {
>> > +	{ 0x00483245, "s6lm",  "10nm", },
>> > +};
>>
>> I would suggest something more descriptive in the "family"
>> field to let users know they are on an Ambarella SoC.
>>
>> Maybe just "Ambarella 10nm".
>
> There is a "pr_info("Ambarella SoC %s detected\n", 
> soc_dev_attr->soc_id);" in this file,
> I think this should be enough, right?

The pr_info() can probably be removed here, or reworded
based on the changed contents, those are just meant for
humans reading through the log rather than parsed by
software.

The soc_id fields on the other hand need to be parsable
by scripts looking at the sysfs files, in a way that lets
them identify the system. Usually the script would look
at the "family" as the primary key before looking up the
"name", so you have to make sure that the family uniquely
identifies this as one of yours rather than a 10nm chip
from some other company.

>> If there are other unrelated registers in there, the compatible
>> string should probably be changed to better describe the
>> entire area based on the name in the datasheet.
>
> Yeah, this block is only used for identification bits. In datasheet,
> it is also named "CPU ID".

ok.

> Other than cpuid_regmap, this driver also looks for "model" name as soc 
> machine name:
> of_property_read_string(np, "model", &soc_dev_attr->machine);
>
> So I think it is not a good idea to conver it to into a platform driver.

I don't understand what you mean. A lot of soc_id drivers put
the model string into soc_dev_attr->machine, this makes no
difference here.

> As for "syscon", I think it is still very helpful to get regmap easily. 
> Generally speaking,
> I prefer regmap over void*, because it has debugfs support, so I can 
> get its value more easily.

What value would you get through debugfs that is not already in
the soc_device?

>> > +static unsigned int ambsys_config;
>> > +
>> > +unsigned int ambarella_sys_config(void)
>> > +{
>> > +	return ambsys_config;
>> > +}
>> > +EXPORT_SYMBOL(ambarella_sys_config);
>>
>> Which drivers use this bit? Can they be changed to
>> use soc_device_match() instead to avoid the export?
>
> sys_config is used by our nand and sd drivers. I also don't want to export,
> but struct soc_device_attribute/soc_device don't have private data to store it,
> I think there is no better way.

The nand and sd drivers should not rely on any private data
from another driver. What information do they actually
need here that is not already in their own DT nodes or
in the soc_device_attributes?

>> > +static int __init ambarella_soc_init(void)
>> > +{
>> > +	struct regmap *rct_regmap;
>> > +	int ret;
>> > +
>> > +	rct_regmap = syscon_regmap_lookup_by_compatible("ambarella,rct");
>> > +	if (IS_ERR(rct_regmap)) {
>> > +		pr_err("failed to get ambarella rct regmap\n");
>> > +		return PTR_ERR(rct_regmap);
>> > +	}
>> ...
>> > +arch_initcall(ambarella_soc_init);
>>
>> It is not an error to use a chip from another manufacturer,
>> please drop the pr_err() and return success here.
>
> Ok, good to know, thanks. But we don't have other manufacturers at 
> least for now,

I care a lot about supporting multiple SoC vendors, it would seem
very rude to assume that we stop supporting everything else after
merging Ambarella support.

> and rct_regmap is need to be updated here, like sys_config and soft 
> reboot. So I think this rct regmap is still needed.

It is certainly only needed on Ambarella SoCs, no other one
has this device at the moment.

      Arnd

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Re: [PATCH 06/15] soc: add Ambarella driver

[Li Chen]

Hi Arnd,

Sorry for late reply.

On Tue, 24 Jan 2023 23:46:06 +0800,
Arnd Bergmann wrote:
>
> On Tue, Jan 24, 2023, at 08:58, Li Chen wrote:
> > On Mon, 23 Jan 2023 16:29:06 +0800,
> > Arnd Bergmann wrote:
> >> On Mon, Jan 23, 2023, at 08:32, Li Chen wrote:
> >> > +static struct ambarella_soc_id {
> >> > +	unsigned int id;
> >> > +	const char *name;
> >> > +	const char *family;
> >> > +} soc_ids[] = {
> >> > +	{ 0x00483245, "s6lm",  "10nm", },
> >> > +};
> >>
> >> I would suggest something more descriptive in the "family"
> >> field to let users know they are on an Ambarella SoC.
> >>
> >> Maybe just "Ambarella 10nm".
> >
> > There is a "pr_info("Ambarella SoC %s detected\n",
> > soc_dev_attr->soc_id);" in this file,
> > I think this should be enough, right?
>
> The pr_info() can probably be removed here, or reworded
> based on the changed contents, those are just meant for
> humans reading through the log rather than parsed by
> software.
>
> The soc_id fields on the other hand need to be parsable
> by scripts looking at the sysfs files, in a way that lets
> them identify the system. Usually the script would look
> at the "family" as the primary key before looking up the
> "name", so you have to make sure that the family uniquely
> identifies this as one of yours rather than a 10nm chip
> from some other company.

Ok, I will add "Ambarella" prefix to ->family.

> >> If there are other unrelated registers in there, the compatible
> >> string should probably be changed to better describe the
> >> entire area based on the name in the datasheet.
> >
> > Yeah, this block is only used for identification bits. In datasheet,
> > it is also named "CPU ID".
>
> ok.
>
> > Other than cpuid_regmap, this driver also looks for "model" name as soc
> > machine name:
> > of_property_read_string(np, "model", &soc_dev_attr->machine);
> >
> > So I think it is not a good idea to conver it to into a platform driver.
> I don't understand what you mean. A lot of soc_id drivers put
> the model string into soc_dev_attr->machine, this makes no
> difference here.

Ok, I will switch to builtin platform driver. Which compatible do you prefer?

compatible = "ambarella,cpuid"
or
compatible = "ambarella,<SoC>-cpuid"

> > As for "syscon", I think it is still very helpful to get regmap easily.
> > Generally speaking,
> > I prefer regmap over void*, because it has debugfs support, so I can
> > get its value more easily.
>
> What value would you get through debugfs that is not already in
> the soc_device?

Agree with you.

> >> > +static unsigned int ambsys_config;
> >> > +
> >> > +unsigned int ambarella_sys_config(void)
> >> > +{
> >> > +	return ambsys_config;
> >> > +}
> >> > +EXPORT_SYMBOL(ambarella_sys_config);
> >>
> >> Which drivers use this bit? Can they be changed to
> >> use soc_device_match() instead to avoid the export?
> >
> > sys_config is used by our nand and sd drivers. I also don't want to export,
> > but struct soc_device_attribute/soc_device don't have private data to store it,
> > I think there is no better way.
>
> The nand and sd drivers should not rely on any private data
> from another driver.

Agree.

> What information do they actually
> need here that is not already in their own DT nodes or
> in the soc_device_attributes?

sys_config from rct_regmap is not available for sd/nand node neither soc_device_attribute.

But given that I will switch dts model to(see https://www.spinics.net/lists/arm-kernel/msg1043684.html):

rct
| nand
| sd
| ...

Then I can easily and naturally get sys_config via syscon_node_to_regmap(of_get_parent(nand_np/sd_np)).

So this is not a problem anymore and I will switch to builtin platform driver in v2.

> >> > +static int __init ambarella_soc_init(void)
> >> > +{
> >> > +	struct regmap *rct_regmap;
> >> > +	int ret;
> >> > +
> >> > +	rct_regmap = syscon_regmap_lookup_by_compatible("ambarella,rct");
> >> > +	if (IS_ERR(rct_regmap)) {
> >> > +		pr_err("failed to get ambarella rct regmap\n");
> >> > +		return PTR_ERR(rct_regmap);
> >> > +	}
> >> ...
> >> > +arch_initcall(ambarella_soc_init);
> >>
> >> It is not an error to use a chip from another manufacturer,
> >> please drop the pr_err() and return success here.
> >
> > Ok, good to know, thanks. But we don't have other manufacturers at
> > least for now,
>
> I care a lot about supporting multiple SoC vendors, it would seem
> very rude to assume that we stop supporting everything else after
> merging Ambarella support.
>
> > and rct_regmap is need to be updated here, like sys_config and soft
> > reboot. So I think this rct regmap is still needed.
>
> It is certainly only needed on Ambarella SoCs, no other one
> has this device at the moment.

I'm really sorry that I forgot that this builtin arch_initcall code would run on SoCs
other than Ambarella.

I will remove the err output in v2.

Regards,
Li

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Re: [PATCH 06/15] soc: add Ambarella driver

[Li Chen]

Hi Arnd,

Sorry for late reply.

On Tue, 24 Jan 2023 23:46:06 +0800,
Arnd Bergmann wrote:
>
> On Tue, Jan 24, 2023, at 08:58, Li Chen wrote:
> > On Mon, 23 Jan 2023 16:29:06 +0800,
> > Arnd Bergmann wrote:
> >> On Mon, Jan 23, 2023, at 08:32, Li Chen wrote:
> >> > +static struct ambarella_soc_id {
> >> > +	unsigned int id;
> >> > +	const char *name;
> >> > +	const char *family;
> >> > +} soc_ids[] = {
> >> > +	{ 0x00483245, "s6lm",  "10nm", },
> >> > +};
> >>
> >> I would suggest something more descriptive in the "family"
> >> field to let users know they are on an Ambarella SoC.
> >>
> >> Maybe just "Ambarella 10nm".
> >
> > There is a "pr_info("Ambarella SoC %s detected\n",
> > soc_dev_attr->soc_id);" in this file,
> > I think this should be enough, right?
>
> The pr_info() can probably be removed here, or reworded
> based on the changed contents, those are just meant for
> humans reading through the log rather than parsed by
> software.
>
> The soc_id fields on the other hand need to be parsable
> by scripts looking at the sysfs files, in a way that lets
> them identify the system. Usually the script would look
> at the "family" as the primary key before looking up the
> "name", so you have to make sure that the family uniquely
> identifies this as one of yours rather than a 10nm chip
> from some other company.

Ok, I will add "Ambarella" prefix to ->family.

> >> If there are other unrelated registers in there, the compatible
> >> string should probably be changed to better describe the
> >> entire area based on the name in the datasheet.
> >
> > Yeah, this block is only used for identification bits. In datasheet,
> > it is also named "CPU ID".
>
> ok.
>
> > Other than cpuid_regmap, this driver also looks for "model" name as soc
> > machine name:
> > of_property_read_string(np, "model", &soc_dev_attr->machine);
> >
> > So I think it is not a good idea to conver it to into a platform driver.
> I don't understand what you mean. A lot of soc_id drivers put
> the model string into soc_dev_attr->machine, this makes no
> difference here.

Ok, I will switch to builtin platform driver. Which compatible do you prefer?

compatible = "ambarella,cpuid"
or
compatible = "ambarella,<SoC>-cpuid"

> > As for "syscon", I think it is still very helpful to get regmap easily.
> > Generally speaking,
> > I prefer regmap over void*, because it has debugfs support, so I can
> > get its value more easily.
>
> What value would you get through debugfs that is not already in
> the soc_device?

Agree with you.

> >> > +static unsigned int ambsys_config;
> >> > +
> >> > +unsigned int ambarella_sys_config(void)
> >> > +{
> >> > +	return ambsys_config;
> >> > +}
> >> > +EXPORT_SYMBOL(ambarella_sys_config);
> >>
> >> Which drivers use this bit? Can they be changed to
> >> use soc_device_match() instead to avoid the export?
> >
> > sys_config is used by our nand and sd drivers. I also don't want to export,
> > but struct soc_device_attribute/soc_device don't have private data to store it,
> > I think there is no better way.
>
> The nand and sd drivers should not rely on any private data
> from another driver.

Agree.

> What information do they actually
> need here that is not already in their own DT nodes or
> in the soc_device_attributes?

sys_config from rct_regmap is not available for sd/nand node neither soc_device_attribute.

But given that I will switch dts model to(see https://www.spinics.net/lists/arm-kernel/msg1043684.html):

rct
| nand
| sd
| ...

Then I can easily and naturally get sys_config via syscon_node_to_regmap(of_get_parent(nand_np/sd_np)).

So this is not a problem anymore and I will switch to builtin platform driver in v2.

> >> > +static int __init ambarella_soc_init(void)
> >> > +{
> >> > +	struct regmap *rct_regmap;
> >> > +	int ret;
> >> > +
> >> > +	rct_regmap = syscon_regmap_lookup_by_compatible("ambarella,rct");
> >> > +	if (IS_ERR(rct_regmap)) {
> >> > +		pr_err("failed to get ambarella rct regmap\n");
> >> > +		return PTR_ERR(rct_regmap);
> >> > +	}
> >> ...
> >> > +arch_initcall(ambarella_soc_init);
> >>
> >> It is not an error to use a chip from another manufacturer,
> >> please drop the pr_err() and return success here.
> >
> > Ok, good to know, thanks. But we don't have other manufacturers at
> > least for now,
>
> I care a lot about supporting multiple SoC vendors, it would seem
> very rude to assume that we stop supporting everything else after
> merging Ambarella support.
>
> > and rct_regmap is need to be updated here, like sys_config and soft
> > reboot. So I think this rct regmap is still needed.
>
> It is certainly only needed on Ambarella SoCs, no other one
> has this device at the moment.

I'm really sorry that I forgot that this builtin arch_initcall code would run on SoCs
other than Ambarella.

I will remove the err output in v2.

Regards,
Li

Re: [PATCH 06/15] soc: add Ambarella driver

[Conor.Dooley]

Hey Li Chen,

Since you've already got a bunch of other comments, I have
two minor ones for you.

On 23/01/2023 07:32, Li Chen wrote:
> 
> This driver add soc_id support for Ambarella,
> which is stored inside "cpuid" AXI address mapping.
> 
> Also provide sys_config(POC, aka power on configuration)
> for other drivers.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: I4869a3497366ac7779e792835f8e0309239036a8
> ---

> diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> index fff513bd522d..e3e270aa32a4 100644
> --- a/drivers/soc/Makefile
> +++ b/drivers/soc/Makefile
> @@ -8,6 +8,7 @@ obj-y                           += apple/
>   obj-y                          += aspeed/
>   obj-$(CONFIG_ARCH_AT91)                += atmel/
>   obj-y                          += bcm/
> +obj-$(CONFIG_ARCH_AMBARELLA)   += ambarella/
>   obj-$(CONFIG_SOC_CANAAN)       += canaan/

If you could follow the existing (by directory) alphabetical
order that'd be great.

>   obj-$(CONFIG_ARCH_DOVE)                += dove/
>   obj-$(CONFIG_MACH_DOVE)                += dove/
> diff --git a/drivers/soc/ambarella/Makefile b/drivers/soc/ambarella/Makefile
> new file mode 100644
> index 000000000000..384276c046ca
> --- /dev/null
> +++ b/drivers/soc/ambarella/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +
> +obj-$(CONFIG_ARCH_AMBARELLA) += soc.o

The subdirectory is already gated by this symbol, so is there much point
gating it on the same one again?

Re: [PATCH 06/15] soc: add Ambarella driver

[Conor.Dooley]

Hey Li Chen,

Since you've already got a bunch of other comments, I have
two minor ones for you.

On 23/01/2023 07:32, Li Chen wrote:
> 
> This driver add soc_id support for Ambarella,
> which is stored inside "cpuid" AXI address mapping.
> 
> Also provide sys_config(POC, aka power on configuration)
> for other drivers.
> 
> Signed-off-by: Li Chen <lchen@ambarella.com>
> Change-Id: I4869a3497366ac7779e792835f8e0309239036a8
> ---

> diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> index fff513bd522d..e3e270aa32a4 100644
> --- a/drivers/soc/Makefile
> +++ b/drivers/soc/Makefile
> @@ -8,6 +8,7 @@ obj-y                           += apple/
>   obj-y                          += aspeed/
>   obj-$(CONFIG_ARCH_AT91)                += atmel/
>   obj-y                          += bcm/
> +obj-$(CONFIG_ARCH_AMBARELLA)   += ambarella/
>   obj-$(CONFIG_SOC_CANAAN)       += canaan/

If you could follow the existing (by directory) alphabetical
order that'd be great.

>   obj-$(CONFIG_ARCH_DOVE)                += dove/
>   obj-$(CONFIG_MACH_DOVE)                += dove/
> diff --git a/drivers/soc/ambarella/Makefile b/drivers/soc/ambarella/Makefile
> new file mode 100644
> index 000000000000..384276c046ca
> --- /dev/null
> +++ b/drivers/soc/ambarella/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +
> +obj-$(CONFIG_ARCH_AMBARELLA) += soc.o

The subdirectory is already gated by this symbol, so is there much point
gating it on the same one again?


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Re: [PATCH 06/15] soc: add Ambarella driver

[Li Chen]

On Mon, 23 Jan 2023 19:48:42 +0800,

Hi Conor.Dooley

<Conor.Dooley@microchip.com> wrote:
>
> Hey Li Chen,
>
> Since you've already got a bunch of other comments, I have
> two minor ones for you.
>
> On 23/01/2023 07:32, Li Chen wrote:
> >
> > This driver add soc_id support for Ambarella,
> > which is stored inside "cpuid" AXI address mapping.
> >
> > Also provide sys_config(POC, aka power on configuration)
> > for other drivers.
> >
> > Signed-off-by: Li Chen <lchen@ambarella.com>
> > Change-Id: I4869a3497366ac7779e792835f8e0309239036a8
> > ---
>
> > diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> > index fff513bd522d..e3e270aa32a4 100644
> > --- a/drivers/soc/Makefile
> > +++ b/drivers/soc/Makefile
> > @@ -8,6 +8,7 @@ obj-y                           += apple/
> >   obj-y                          += aspeed/
> >   obj-$(CONFIG_ARCH_AT91)                += atmel/
> >   obj-y                          += bcm/
> > +obj-$(CONFIG_ARCH_AMBARELLA)   += ambarella/
> >   obj-$(CONFIG_SOC_CANAAN)       += canaan/
>
> If you could follow the existing (by directory) alphabetical
> order that'd be great.

Well noted. I will fix it in v2.

> >   obj-$(CONFIG_ARCH_DOVE)                += dove/
> >   obj-$(CONFIG_MACH_DOVE)                += dove/
> > diff --git a/drivers/soc/ambarella/Makefile b/drivers/soc/ambarella/Makefile
> > new file mode 100644
> > index 000000000000..384276c046ca
> > --- /dev/null
> > +++ b/drivers/soc/ambarella/Makefile
> > @@ -0,0 +1,3 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +
> > +obj-$(CONFIG_ARCH_AMBARELLA) += soc.o
>
> The subdirectory is already gated by this symbol, so is there much point
> gating it on the same one again?

Yeah, it lookgs kind of redundant now, but I will upstream other drivers after
this series get merged, which are not gated by this symbol.

Regards,
Li

Re: [PATCH 06/15] soc: add Ambarella driver

[Li Chen]

On Mon, 23 Jan 2023 19:48:42 +0800,

Hi Conor.Dooley

<Conor.Dooley@microchip.com> wrote:
>
> Hey Li Chen,
>
> Since you've already got a bunch of other comments, I have
> two minor ones for you.
>
> On 23/01/2023 07:32, Li Chen wrote:
> >
> > This driver add soc_id support for Ambarella,
> > which is stored inside "cpuid" AXI address mapping.
> >
> > Also provide sys_config(POC, aka power on configuration)
> > for other drivers.
> >
> > Signed-off-by: Li Chen <lchen@ambarella.com>
> > Change-Id: I4869a3497366ac7779e792835f8e0309239036a8
> > ---
>
> > diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> > index fff513bd522d..e3e270aa32a4 100644
> > --- a/drivers/soc/Makefile
> > +++ b/drivers/soc/Makefile
> > @@ -8,6 +8,7 @@ obj-y                           += apple/
> >   obj-y                          += aspeed/
> >   obj-$(CONFIG_ARCH_AT91)                += atmel/
> >   obj-y                          += bcm/
> > +obj-$(CONFIG_ARCH_AMBARELLA)   += ambarella/
> >   obj-$(CONFIG_SOC_CANAAN)       += canaan/
>
> If you could follow the existing (by directory) alphabetical
> order that'd be great.

Well noted. I will fix it in v2.

> >   obj-$(CONFIG_ARCH_DOVE)                += dove/
> >   obj-$(CONFIG_MACH_DOVE)                += dove/
> > diff --git a/drivers/soc/ambarella/Makefile b/drivers/soc/ambarella/Makefile
> > new file mode 100644
> > index 000000000000..384276c046ca
> > --- /dev/null
> > +++ b/drivers/soc/ambarella/Makefile
> > @@ -0,0 +1,3 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +
> > +obj-$(CONFIG_ARCH_AMBARELLA) += soc.o
>
> The subdirectory is already gated by this symbol, so is there much point
> gating it on the same one again?

Yeah, it lookgs kind of redundant now, but I will upstream other drivers after
this series get merged, which are not gated by this symbol.

Regards,
Li

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Re: [PATCH 06/15] soc: add Ambarella driver

[Conor.Dooley]

Hey,

>>> +++ b/drivers/soc/ambarella/Makefile
>>> @@ -0,0 +1,3 @@
>>> +# SPDX-License-Identifier: GPL-2.0-only
>>> +
>>> +obj-$(CONFIG_ARCH_AMBARELLA) += soc.o
>>
>> The subdirectory is already gated by this symbol, so is there much point
>> gating it on the same one again?
> 
> Yeah, it lookgs kind of redundant now, but I will upstream other drivers after
> this series get merged, which are not gated by this symbol.

You could make the directory by obj-y, and therefore always included,
and have various drivers controlled by their own Kconfig symbols.

Or else, you could leave the directory controlled by ARCH_AMBARELLA
and make the above `obj-y += soc.o` instead, since it's always
going to be built if the directory is included.

Thanks,
Conor.

Re: [PATCH 06/15] soc: add Ambarella driver

[Conor.Dooley]

Hey,

>>> +++ b/drivers/soc/ambarella/Makefile
>>> @@ -0,0 +1,3 @@
>>> +# SPDX-License-Identifier: GPL-2.0-only
>>> +
>>> +obj-$(CONFIG_ARCH_AMBARELLA) += soc.o
>>
>> The subdirectory is already gated by this symbol, so is there much point
>> gating it on the same one again?
> 
> Yeah, it lookgs kind of redundant now, but I will upstream other drivers after
> this series get merged, which are not gated by this symbol.

You could make the directory by obj-y, and therefore always included,
and have various drivers controlled by their own Kconfig symbols.

Or else, you could leave the directory controlled by ARCH_AMBARELLA
and make the above `obj-y += soc.o` instead, since it's always
going to be built if the directory is included.

Thanks,
Conor.


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Re: [PATCH 06/15] soc: add Ambarella driver

[Li Chen]

Hi Conor.Dooley,

On Tue, 24 Jan 2023 16:46:41 +0800,
<Conor.Dooley@microchip.com> wrote:
> 
> Hey,
> 
> >>> +++ b/drivers/soc/ambarella/Makefile
> >>> @@ -0,0 +1,3 @@
> >>> +# SPDX-License-Identifier: GPL-2.0-only
> >>> +
> >>> +obj-$(CONFIG_ARCH_AMBARELLA) += soc.o
> >>
> >> The subdirectory is already gated by this symbol, so is there much point
> >> gating it on the same one again?
> > 
> > Yeah, it lookgs kind of redundant now, but I will upstream other drivers after
> > this series get merged, which are not gated by this symbol.
> 
> You could make the directory by obj-y, and therefore always included,
> and have various drivers controlled by their own Kconfig symbols.
> 
> Or else, you could leave the directory controlled by ARCH_AMBARELLA
> and make the above `obj-y += soc.o` instead, since it's always
> going to be built if the directory is included.

Gotcha, I will fix it in v2. Thanks for your kindness!

Regards,
Li

Re: [PATCH 06/15] soc: add Ambarella driver

[Li Chen]

Hi Conor.Dooley,

On Tue, 24 Jan 2023 16:46:41 +0800,
<Conor.Dooley@microchip.com> wrote:
> 
> Hey,
> 
> >>> +++ b/drivers/soc/ambarella/Makefile
> >>> @@ -0,0 +1,3 @@
> >>> +# SPDX-License-Identifier: GPL-2.0-only
> >>> +
> >>> +obj-$(CONFIG_ARCH_AMBARELLA) += soc.o
> >>
> >> The subdirectory is already gated by this symbol, so is there much point
> >> gating it on the same one again?
> > 
> > Yeah, it lookgs kind of redundant now, but I will upstream other drivers after
> > this series get merged, which are not gated by this symbol.
> 
> You could make the directory by obj-y, and therefore always included,
> and have various drivers controlled by their own Kconfig symbols.
> 
> Or else, you could leave the directory controlled by ARCH_AMBARELLA
> and make the above `obj-y += soc.o` instead, since it's always
> going to be built if the directory is included.

Gotcha, I will fix it in v2. Thanks for your kindness!

Regards,
Li

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Re: [PATCH 12/15] mtd: nand: add Ambarella nand support

[Miquel Raynal]

Hi Li,

I'm sorry, this is not going to work at all.

> +	ambarella_nand_init(host);
> +
> +	mtd = nand_to_mtd(&host->chip);
> +	mtd->name = "amba_nand";
> +
> +	nand_controller_init(&host->controller);
> +	nand_set_controller_data(&host->chip, host);
> +	nand_set_flash_node(&host->chip, dev->of_node);
> +
> +	host->chip.controller = &host->controller;
> +	host->chip.controller->ops = &ambarella_controller_ops;
> +	host->chip.legacy.chip_delay = 0;
> +	host->chip.legacy.read_byte = ambarella_nand_read_byte;
> +	host->chip.legacy.write_buf = ambarella_nand_write_buf;
> +	host->chip.legacy.read_buf = ambarella_nand_read_buf;
> +	host->chip.legacy.select_chip = ambarella_nand_select_chip;
> +	host->chip.legacy.cmd_ctrl = ambarella_nand_cmd_ctrl;
> +	host->chip.legacy.dev_ready = ambarella_nand_dev_ready;
> +	host->chip.legacy.waitfunc = ambarella_nand_waitfunc;
> +	host->chip.legacy.cmdfunc = ambarella_nand_cmdfunc;
> +	host->chip.legacy.set_features = nand_get_set_features_notsupp;
> +	host->chip.legacy.get_features = nand_get_set_features_notsupp;

Please be aware that we no longer accept legacy introductions upstream.

You can look for ->exec_op() conversions using git-log.

> +	host->chip.options |= NAND_NO_SUBPAGE_WRITE | NAND_USES_DMA;
> +
> +	rval = nand_scan(&host->chip, 1);
> +	if (rval < 0)
> +		return rval;
> +
> +	rval = mtd_device_register(mtd, NULL, 0);
> +	if (rval < 0)
> +		nand_cleanup(&host->chip);
> +
> +	return rval;
> +}

[...]

> diff --git a/drivers/mtd/nand/raw/nand_ids.c
b/drivers/mtd/nand/raw/nand_ids.c
> index dacc5529b3df..9f264e2a6484 100644
> --- a/drivers/mtd/nand/raw/nand_ids.c
> +++ b/drivers/mtd/nand/raw/nand_ids.c
> @@ -62,6 +62,10 @@ struct nand_flash_dev nand_flash_ids[] = {
>  		{ .id = {0x98, 0xd3, 0x91, 0x26, 0x76} },
>  		  SZ_4K, SZ_1K, SZ_256K, 0, 5, 256, NAND_ECC_INFO(8, SZ_512)},
>  
> +	{"MT29F2G01ABAGD SPINAND 2G 3.3V 8-bit",
> +		{ .id = {0x2c, 0x24, 0x00, 0x00, 0x00} },
> +		  SZ_2K, SZ_256, SZ_128K, 0, 2, 128},
> +

Raw NAND != SPI-NAND. I don't get what you're doing here but either you
want to drive SPI-NANDs and this is a SPI controller driver that
implements spi-mem ops and should be located under drivers/spi/, or
this is a plain raw NAND controller which is wired to a parallel NAND
and this should be under drivers/mtd/nand/raw/.

ECC controllers can be shared with the ECC engine abstraction though.

>  	LEGACY_ID_NAND("NAND 4MiB 5V 8-bit",   0x6B, 4, SZ_8K, SP_OPTIONS),
>  	LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
>  	LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 4, SZ_8K, SP_OPTIONS),


Thanks,
Miquèl

Re: [PATCH 12/15] mtd: nand: add Ambarella nand support

[Miquel Raynal]

Hi Li,

I'm sorry, this is not going to work at all.

> +	ambarella_nand_init(host);
> +
> +	mtd = nand_to_mtd(&host->chip);
> +	mtd->name = "amba_nand";
> +
> +	nand_controller_init(&host->controller);
> +	nand_set_controller_data(&host->chip, host);
> +	nand_set_flash_node(&host->chip, dev->of_node);
> +
> +	host->chip.controller = &host->controller;
> +	host->chip.controller->ops = &ambarella_controller_ops;
> +	host->chip.legacy.chip_delay = 0;
> +	host->chip.legacy.read_byte = ambarella_nand_read_byte;
> +	host->chip.legacy.write_buf = ambarella_nand_write_buf;
> +	host->chip.legacy.read_buf = ambarella_nand_read_buf;
> +	host->chip.legacy.select_chip = ambarella_nand_select_chip;
> +	host->chip.legacy.cmd_ctrl = ambarella_nand_cmd_ctrl;
> +	host->chip.legacy.dev_ready = ambarella_nand_dev_ready;
> +	host->chip.legacy.waitfunc = ambarella_nand_waitfunc;
> +	host->chip.legacy.cmdfunc = ambarella_nand_cmdfunc;
> +	host->chip.legacy.set_features = nand_get_set_features_notsupp;
> +	host->chip.legacy.get_features = nand_get_set_features_notsupp;

Please be aware that we no longer accept legacy introductions upstream.

You can look for ->exec_op() conversions using git-log.

> +	host->chip.options |= NAND_NO_SUBPAGE_WRITE | NAND_USES_DMA;
> +
> +	rval = nand_scan(&host->chip, 1);
> +	if (rval < 0)
> +		return rval;
> +
> +	rval = mtd_device_register(mtd, NULL, 0);
> +	if (rval < 0)
> +		nand_cleanup(&host->chip);
> +
> +	return rval;
> +}

[...]

> diff --git a/drivers/mtd/nand/raw/nand_ids.c
b/drivers/mtd/nand/raw/nand_ids.c
> index dacc5529b3df..9f264e2a6484 100644
> --- a/drivers/mtd/nand/raw/nand_ids.c
> +++ b/drivers/mtd/nand/raw/nand_ids.c
> @@ -62,6 +62,10 @@ struct nand_flash_dev nand_flash_ids[] = {
>  		{ .id = {0x98, 0xd3, 0x91, 0x26, 0x76} },
>  		  SZ_4K, SZ_1K, SZ_256K, 0, 5, 256, NAND_ECC_INFO(8, SZ_512)},
>  
> +	{"MT29F2G01ABAGD SPINAND 2G 3.3V 8-bit",
> +		{ .id = {0x2c, 0x24, 0x00, 0x00, 0x00} },
> +		  SZ_2K, SZ_256, SZ_128K, 0, 2, 128},
> +

Raw NAND != SPI-NAND. I don't get what you're doing here but either you
want to drive SPI-NANDs and this is a SPI controller driver that
implements spi-mem ops and should be located under drivers/spi/, or
this is a plain raw NAND controller which is wired to a parallel NAND
and this should be under drivers/mtd/nand/raw/.

ECC controllers can be shared with the ECC engine abstraction though.

>  	LEGACY_ID_NAND("NAND 4MiB 5V 8-bit",   0x6B, 4, SZ_8K, SP_OPTIONS),
>  	LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
>  	LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 4, SZ_8K, SP_OPTIONS),


Thanks,
Miquèl

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Re: [PATCH 12/15] mtd: nand: add Ambarella nand support

[Miquel Raynal]

Hi Li,

I'm sorry, this is not going to work at all.

> +	ambarella_nand_init(host);
> +
> +	mtd = nand_to_mtd(&host->chip);
> +	mtd->name = "amba_nand";
> +
> +	nand_controller_init(&host->controller);
> +	nand_set_controller_data(&host->chip, host);
> +	nand_set_flash_node(&host->chip, dev->of_node);
> +
> +	host->chip.controller = &host->controller;
> +	host->chip.controller->ops = &ambarella_controller_ops;
> +	host->chip.legacy.chip_delay = 0;
> +	host->chip.legacy.read_byte = ambarella_nand_read_byte;
> +	host->chip.legacy.write_buf = ambarella_nand_write_buf;
> +	host->chip.legacy.read_buf = ambarella_nand_read_buf;
> +	host->chip.legacy.select_chip = ambarella_nand_select_chip;
> +	host->chip.legacy.cmd_ctrl = ambarella_nand_cmd_ctrl;
> +	host->chip.legacy.dev_ready = ambarella_nand_dev_ready;
> +	host->chip.legacy.waitfunc = ambarella_nand_waitfunc;
> +	host->chip.legacy.cmdfunc = ambarella_nand_cmdfunc;
> +	host->chip.legacy.set_features = nand_get_set_features_notsupp;
> +	host->chip.legacy.get_features = nand_get_set_features_notsupp;

Please be aware that we no longer accept legacy introductions upstream.

You can look for ->exec_op() conversions using git-log.

> +	host->chip.options |= NAND_NO_SUBPAGE_WRITE | NAND_USES_DMA;
> +
> +	rval = nand_scan(&host->chip, 1);
> +	if (rval < 0)
> +		return rval;
> +
> +	rval = mtd_device_register(mtd, NULL, 0);
> +	if (rval < 0)
> +		nand_cleanup(&host->chip);
> +
> +	return rval;
> +}

[...]

> diff --git a/drivers/mtd/nand/raw/nand_ids.c
b/drivers/mtd/nand/raw/nand_ids.c
> index dacc5529b3df..9f264e2a6484 100644
> --- a/drivers/mtd/nand/raw/nand_ids.c
> +++ b/drivers/mtd/nand/raw/nand_ids.c
> @@ -62,6 +62,10 @@ struct nand_flash_dev nand_flash_ids[] = {
>  		{ .id = {0x98, 0xd3, 0x91, 0x26, 0x76} },
>  		  SZ_4K, SZ_1K, SZ_256K, 0, 5, 256, NAND_ECC_INFO(8, SZ_512)},
>  
> +	{"MT29F2G01ABAGD SPINAND 2G 3.3V 8-bit",
> +		{ .id = {0x2c, 0x24, 0x00, 0x00, 0x00} },
> +		  SZ_2K, SZ_256, SZ_128K, 0, 2, 128},
> +

Raw NAND != SPI-NAND. I don't get what you're doing here but either you
want to drive SPI-NANDs and this is a SPI controller driver that
implements spi-mem ops and should be located under drivers/spi/, or
this is a plain raw NAND controller which is wired to a parallel NAND
and this should be under drivers/mtd/nand/raw/.

ECC controllers can be shared with the ECC engine abstraction though.

>  	LEGACY_ID_NAND("NAND 4MiB 5V 8-bit",   0x6B, 4, SZ_8K, SP_OPTIONS),
>  	LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
>  	LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 4, SZ_8K, SP_OPTIONS),


Thanks,
Miquèl

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http://lists.infradead.org/mailman/listinfo/linux-mtd/

Re: [PATCH 00/15] Ambarella S6LM SoC bring-up

[Arnd Bergmann]

On Mon, Jan 23, 2023, at 08:32, Li Chen wrote:
> This series brings up initial support for the Ambarella S6LM
> SoC.
>
> The following features are supported in this initial port:
>
> - UART with console support
> - Pinctrl with GPIO controller
> - Nand flash controller
> - Devicetree

I seem to only have part of the series, please add both me and
the linux-arm-kernel mailing list to each part of the initial
submission.

It's possible that some patches were already Cc'd to
linux-arm-kernel but did not make it through because the Cc list
was too long (it has to fit within 1024 characters for many lists).
I think you too the Cc list from get_maintainers.pl, but when
sending new drivers this does not work well because it picks
up everyone that recently touched the Makefile/Kconfig.

     Arnd

Re: [PATCH 00/15] Ambarella S6LM SoC bring-up

[Arnd Bergmann]

On Mon, Jan 23, 2023, at 08:32, Li Chen wrote:
> This series brings up initial support for the Ambarella S6LM
> SoC.
>
> The following features are supported in this initial port:
>
> - UART with console support
> - Pinctrl with GPIO controller
> - Nand flash controller
> - Devicetree

I seem to only have part of the series, please add both me and
the linux-arm-kernel mailing list to each part of the initial
submission.

It's possible that some patches were already Cc'd to
linux-arm-kernel but did not make it through because the Cc list
was too long (it has to fit within 1024 characters for many lists).
I think you too the Cc list from get_maintainers.pl, but when
sending new drivers this does not work well because it picks
up everyone that recently touched the Makefile/Kconfig.

     Arnd

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 00/15] Ambarella S6LM SoC bring-up

[Arnd Bergmann]

On Mon, Jan 23, 2023, at 08:32, Li Chen wrote:
> This series brings up initial support for the Ambarella S6LM
> SoC.
>
> The following features are supported in this initial port:
>
> - UART with console support
> - Pinctrl with GPIO controller
> - Nand flash controller
> - Devicetree

I seem to only have part of the series, please add both me and
the linux-arm-kernel mailing list to each part of the initial
submission.

It's possible that some patches were already Cc'd to
linux-arm-kernel but did not make it through because the Cc list
was too long (it has to fit within 1024 characters for many lists).
I think you too the Cc list from get_maintainers.pl, but when
sending new drivers this does not work well because it picks
up everyone that recently touched the Makefile/Kconfig.

     Arnd

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

Re: [PATCH 00/15] Ambarella S6LM SoC bring-up

[Bagas Sanjaya]

On 1/23/23 15:39, Arnd Bergmann wrote:
> I seem to only have part of the series, please add both me and
> the linux-arm-kernel mailing list to each part of the initial
> submission.
> 
> It's possible that some patches were already Cc'd to
> linux-arm-kernel but did not make it through because the Cc list
> was too long (it has to fit within 1024 characters for many lists).
> I think you too the Cc list from get_maintainers.pl, but when
> sending new drivers this does not work well because it picks
> up everyone that recently touched the Makefile/Kconfig.

Hi Arnd,

It is possible (and common) that people who recently touched these
files, when given new drivers patches, aren't interested in reviewing
them for many reasons.

In that case, you may want to see Alison's trick posted on kernel
outreachy list [1]. In summary, pass `--no-gitfallback` (don't give
addresses of recent commit authors) and `--norolestats` (only name and
email are printed; MLs don't get open list:-generated names). Also,
another trick that I use is to condense the list by passing
`--separator , ` so that it can be easily copy-pasted to
git-send-email(1).

Thanks.

[1]: https://lore.kernel.org/outreachy/20211015171331.GA431883@alison-desk/

-- 
An old man doll... just what I always wanted! - Clara

Re: [PATCH 00/15] Ambarella S6LM SoC bring-up

[Bagas Sanjaya]

On 1/23/23 15:39, Arnd Bergmann wrote:
> I seem to only have part of the series, please add both me and
> the linux-arm-kernel mailing list to each part of the initial
> submission.
> 
> It's possible that some patches were already Cc'd to
> linux-arm-kernel but did not make it through because the Cc list
> was too long (it has to fit within 1024 characters for many lists).
> I think you too the Cc list from get_maintainers.pl, but when
> sending new drivers this does not work well because it picks
> up everyone that recently touched the Makefile/Kconfig.

Hi Arnd,

It is possible (and common) that people who recently touched these
files, when given new drivers patches, aren't interested in reviewing
them for many reasons.

In that case, you may want to see Alison's trick posted on kernel
outreachy list [1]. In summary, pass `--no-gitfallback` (don't give
addresses of recent commit authors) and `--norolestats` (only name and
email are printed; MLs don't get open list:-generated names). Also,
another trick that I use is to condense the list by passing
`--separator , ` so that it can be easily copy-pasted to
git-send-email(1).

Thanks.

[1]: https://lore.kernel.org/outreachy/20211015171331.GA431883@alison-desk/

-- 
An old man doll... just what I always wanted! - Clara


_______________________________________________
linux-arm-kernel mailing list
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 00/15] Ambarella S6LM SoC bring-up

[Bagas Sanjaya]

On 1/23/23 15:39, Arnd Bergmann wrote:
> I seem to only have part of the series, please add both me and
> the linux-arm-kernel mailing list to each part of the initial
> submission.
> 
> It's possible that some patches were already Cc'd to
> linux-arm-kernel but did not make it through because the Cc list
> was too long (it has to fit within 1024 characters for many lists).
> I think you too the Cc list from get_maintainers.pl, but when
> sending new drivers this does not work well because it picks
> up everyone that recently touched the Makefile/Kconfig.

Hi Arnd,

It is possible (and common) that people who recently touched these
files, when given new drivers patches, aren't interested in reviewing
them for many reasons.

In that case, you may want to see Alison's trick posted on kernel
outreachy list [1]. In summary, pass `--no-gitfallback` (don't give
addresses of recent commit authors) and `--norolestats` (only name and
email are printed; MLs don't get open list:-generated names). Also,
another trick that I use is to condense the list by passing
`--separator , ` so that it can be easily copy-pasted to
git-send-email(1).

Thanks.

[1]: https://lore.kernel.org/outreachy/20211015171331.GA431883@alison-desk/

-- 
An old man doll... just what I always wanted! - Clara


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

Re: [PATCH 00/15] Ambarella S6LM SoC bring-up

[Li Chen]

Hi Arnd,

I've been on vacation recently (January 17-January 31), so please forgive me if I'm sometimes late in responding.

My outlook email (lchen@ambarella) is not suitable for replying on lkml, so I use my personal email.
Please reply to my personal email (me@linux.beauty) instead of my outlook email, thanks in advance.

> From: Arnd Bergmann <arnd@arndb.de>
> Sent: Monday, January 23, 2023 4:39 PM
> On Mon, Jan 23, 2023, at 08:32, Li Chen wrote:
> > This series brings up initial support for the Ambarella S6LM
> > SoC.
> >
> > The following features are supported in this initial port:
> >
> > - UART with console support
> > - Pinctrl with GPIO controller
> > - Nand flash controller
> > - Devicetree
>
> I seem to only have part of the series, please add both me and
> the linux-arm-kernel mailing list to each part of the initial
> submission.
>
> It's possible that some patches were already Cc'd to
> linux-arm-kernel but did not make it through because the Cc list
> was too long (it has to fit within 1024 characters for many lists).
> I think you too the Cc list from get_maintainers.pl, but when
> sending new drivers this does not work well because it picks
> up everyone that recently touched the Makefile/Kconfig.

Sorry for inconvenience caused, I will double check since v2, thanks for
your kindness.

Regards,
Li

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

Re: [PATCH 00/15] Ambarella S6LM SoC bring-up

[Li Chen]

Hi Arnd,

I've been on vacation recently (January 17-January 31), so please forgive me if I'm sometimes late in responding.

My outlook email (lchen@ambarella) is not suitable for replying on lkml, so I use my personal email.
Please reply to my personal email (me@linux.beauty) instead of my outlook email, thanks in advance.

> From: Arnd Bergmann <arnd@arndb.de>
> Sent: Monday, January 23, 2023 4:39 PM
> On Mon, Jan 23, 2023, at 08:32, Li Chen wrote:
> > This series brings up initial support for the Ambarella S6LM
> > SoC.
> >
> > The following features are supported in this initial port:
> >
> > - UART with console support
> > - Pinctrl with GPIO controller
> > - Nand flash controller
> > - Devicetree
>
> I seem to only have part of the series, please add both me and
> the linux-arm-kernel mailing list to each part of the initial
> submission.
>
> It's possible that some patches were already Cc'd to
> linux-arm-kernel but did not make it through because the Cc list
> was too long (it has to fit within 1024 characters for many lists).
> I think you too the Cc list from get_maintainers.pl, but when
> sending new drivers this does not work well because it picks
> up everyone that recently touched the Makefile/Kconfig.

Sorry for inconvenience caused, I will double check since v2, thanks for
your kindness.

Regards,
Li

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 01/15] debugfs: allow to use regmap for print regs

[Greg Kroah-Hartman]

On Mon, Jan 23, 2023 at 03:32:16PM +0800, Li Chen wrote:
> Currently, debugfs_regset32 only contains void __iomem *base,
> and it is not friendly to regmap user.
> 
> Let's add regmap to debugfs_regset32, and add regmap
> support to debugfs_print_reg32.
> 
> Signed-off-by: Li Chen <me@linux.beauty>
> Change-Id: I8ef015ed0906a4ad85b7592f771dcf64c23f7832

No change-id please.

> ---
>  Documentation/filesystems/debugfs.rst |  2 ++
>  fs/debugfs/file.c                     | 43 ++++++++++++++++++++++++++-
>  include/linux/debugfs.h               | 11 +++++++
>  3 files changed, 55 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/filesystems/debugfs.rst b/Documentation/filesystems/debugfs.rst
> index dc35da8b8792..b2c76ac3a333 100644
> --- a/Documentation/filesystems/debugfs.rst
> +++ b/Documentation/filesystems/debugfs.rst
> @@ -178,6 +178,8 @@ file::
>  
>      void debugfs_print_regs32(struct seq_file *s, const struct debugfs_reg32 *regs,
>  			 int nregs, void __iomem *base, char *prefix);
> +    void debugfs_print_regmap_regs32(struct seq_file *s, const struct debugfs_reg32 *regs,
> +			 int nregs, struct regmap *regmap*, char *prefix);

One too many "*" characters on that last line, right?

>  
>  The "base" argument may be 0, but you may want to build the reg32 array
>  using __stringify, and a number of register names (macros) are actually
> diff --git a/fs/debugfs/file.c b/fs/debugfs/file.c
> index b54f470e0d03..2fb792843b30 100644
> --- a/fs/debugfs/file.c
> +++ b/fs/debugfs/file.c
> @@ -1137,14 +1137,55 @@ void debugfs_print_regs32(struct seq_file *s, const struct debugfs_reg32 *regs,
>  }
>  EXPORT_SYMBOL_GPL(debugfs_print_regs32);
>  
> +/**
> + * debugfs_print_regmap_regs32 - use seq_print to describe a set of registers
> + * @s: the seq_file structure being used to generate output
> + * @regs: an array if struct debugfs_reg32 structures
> + * @nregs: the length of the above array
> + * @regmap: regmap to be used in reading the registers
> + * @prefix: a string to be prefixed to every output line
> + *
> + * This function outputs a text block describing the current values of
> + * some 32-bit hardware registers. It is meant to be used within debugfs
> + * files based on seq_file that need to show registers, intermixed with other
> + * information. The prefix argument may be used to specify a leading string,
> + * because some peripherals have several blocks of identical registers,
> + * for example configuration of dma channels
> + */
> +void debugfs_print_regmap_regs32(struct seq_file *s, const struct debugfs_reg32 *regs,
> +			  int nregs, struct regmap *regmap, char *prefix)
> +{
> +	int i;
> +	u32 val;
> +
> +	for (i = 0; i < nregs; i++, regs++) {
> +		if (prefix)
> +			seq_printf(s, "%s", prefix);
> +		regmap_read(regmap, regs->offset, &val);
> +		seq_printf(s, "%s = 0x%08x\n", regs->name, val);
> +		if (seq_has_overflowed(s))
> +			break;
> +	}
> +}
> +EXPORT_SYMBOL_GPL(debugfs_print_regmap_regs32);
> +
>  static int debugfs_regset32_show(struct seq_file *s, void *data)
>  {
>  	struct debugfs_regset32 *regset = s->private;
>  
> +	void __iomem *base = regset->base;
> +	struct regmap *regmap = regset->regmap;

Why the extra blank line?  Did you run checkpatch?

And it's generally not considered a good idea to dereference a pointer
_before_ it is checked.  It will not crash, but static checkers will
have a field day with it.


> +
> +	if ((regmap && base) || (!regmap && !base))
> +		return -EINVAL;
> +
>  	if (regset->dev)
>  		pm_runtime_get_sync(regset->dev);
>  
> -	debugfs_print_regs32(s, regset->regs, regset->nregs, regset->base, "");
> +	if (base)
> +		debugfs_print_regs32(s, regset->regs, regset->nregs, base, "");
> +	else
> +		debugfs_print_regmap_regs32(s, regset->regs, regset->nregs, regmap, "");
>  
>  	if (regset->dev)
>  		pm_runtime_put(regset->dev);
> diff --git a/include/linux/debugfs.h b/include/linux/debugfs.h
> index ea2d919fd9c7..87dfea6a25a0 100644
> --- a/include/linux/debugfs.h
> +++ b/include/linux/debugfs.h
> @@ -17,6 +17,7 @@
>  
>  #include <linux/types.h>
>  #include <linux/compiler.h>
> +#include <linux/regmap.h>

No need to include this here, just provide a prototype for "struct
regmap" and all will be fine.

thanks,

greg k-h

Re: [PATCH 01/15] debugfs: allow to use regmap for print regs

[Li Chen]

Hi Greg,

On Mon, 23 Jan 2023 19:52:45 +0800,
Greg Kroah-Hartman wrote:
>
> On Mon, Jan 23, 2023 at 03:32:16PM +0800, Li Chen wrote:
> > Currently, debugfs_regset32 only contains void __iomem *base,
> > and it is not friendly to regmap user.
> >
> > Let's add regmap to debugfs_regset32, and add regmap
> > support to debugfs_print_reg32.
> >
> > Signed-off-by: Li Chen <me@linux.beauty>
> > Change-Id: I8ef015ed0906a4ad85b7592f771dcf64c23f7832
>
> No change-id please.

Sorry, my bad, will remove it in v2.

> > ---
> >  Documentation/filesystems/debugfs.rst |  2 ++
> >  fs/debugfs/file.c                     | 43 ++++++++++++++++++++++++++-
> >  include/linux/debugfs.h               | 11 +++++++
> >  3 files changed, 55 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/filesystems/debugfs.rst b/Documentation/filesystems/debugfs.rst
> > index dc35da8b8792..b2c76ac3a333 100644
> > --- a/Documentation/filesystems/debugfs.rst
> > +++ b/Documentation/filesystems/debugfs.rst
> > @@ -178,6 +178,8 @@ file::
> >
> >      void debugfs_print_regs32(struct seq_file *s, const struct debugfs_reg32 *regs,
> >  			 int nregs, void __iomem *base, char *prefix);
> > +    void debugfs_print_regmap_regs32(struct seq_file *s, const struct debugfs_reg32 *regs,
> > +			 int nregs, struct regmap *regmap*, char *prefix);
>
> One too many "*" characters on that last line, right?

Good catch! I will remove it in V2.

> >
> >  The "base" argument may be 0, but you may want to build the reg32 array
> >  using __stringify, and a number of register names (macros) are actually
> > diff --git a/fs/debugfs/file.c b/fs/debugfs/file.c
> > index b54f470e0d03..2fb792843b30 100644
> > --- a/fs/debugfs/file.c
> > +++ b/fs/debugfs/file.c
> > @@ -1137,14 +1137,55 @@ void debugfs_print_regs32(struct seq_file *s, const struct debugfs_reg32 *regs,
> >  }
> >  EXPORT_SYMBOL_GPL(debugfs_print_regs32);
> >
> > +/**
> > + * debugfs_print_regmap_regs32 - use seq_print to describe a set of registers
> > + * @s: the seq_file structure being used to generate output
> > + * @regs: an array if struct debugfs_reg32 structures
> > + * @nregs: the length of the above array
> > + * @regmap: regmap to be used in reading the registers
> > + * @prefix: a string to be prefixed to every output line
> > + *
> > + * This function outputs a text block describing the current values of
> > + * some 32-bit hardware registers. It is meant to be used within debugfs
> > + * files based on seq_file that need to show registers, intermixed with other
> > + * information. The prefix argument may be used to specify a leading string,
> > + * because some peripherals have several blocks of identical registers,
> > + * for example configuration of dma channels
> > + */
> > +void debugfs_print_regmap_regs32(struct seq_file *s, const struct debugfs_reg32 *regs,
> > +			  int nregs, struct regmap *regmap, char *prefix)
> > +{
> > +	int i;
> > +	u32 val;
> > +
> > +	for (i = 0; i < nregs; i++, regs++) {
> > +		if (prefix)
> > +			seq_printf(s, "%s", prefix);
> > +		regmap_read(regmap, regs->offset, &val);
> > +		seq_printf(s, "%s = 0x%08x\n", regs->name, val);
> > +		if (seq_has_overflowed(s))
> > +			break;
> > +	}
> > +}
> > +EXPORT_SYMBOL_GPL(debugfs_print_regmap_regs32);
> > +
> >  static int debugfs_regset32_show(struct seq_file *s, void *data)
> >  {
> >  	struct debugfs_regset32 *regset = s->private;
> >
> > +	void __iomem *base = regset->base;
> > +	struct regmap *regmap = regset->regmap;
>
> Why the extra blank line?  Did you run checkpatch?

Yeah, I do checkpatch & sparse(coccinelle crash somehow)
for all my patches(but forget to remove gerrit's Change-ID finally, sorry).

checkpatch didn't find this extra blank line.

I will remove it in v2, thanks!

> And it's generally not considered a good idea to dereference a pointer
> _before_ it is checked.  It will not crash, but static checkers will
> have a field day with it.

Ok, will check regset before access in v2.

> > +
> > +	if ((regmap && base) || (!regmap && !base))
> > +		return -EINVAL;
> > +
> >  	if (regset->dev)
> >  		pm_runtime_get_sync(regset->dev);
> >
> > -	debugfs_print_regs32(s, regset->regs, regset->nregs, regset->base, "");
> > +	if (base)
> > +		debugfs_print_regs32(s, regset->regs, regset->nregs, base, "");
> > +	else
> > +		debugfs_print_regmap_regs32(s, regset->regs, regset->nregs, regmap, "");
> >
> >  	if (regset->dev)
> >  		pm_runtime_put(regset->dev);
> > diff --git a/include/linux/debugfs.h b/include/linux/debugfs.h
> > index ea2d919fd9c7..87dfea6a25a0 100644
> > --- a/include/linux/debugfs.h
> > +++ b/include/linux/debugfs.h
> > @@ -17,6 +17,7 @@
> >
> >  #include <linux/types.h>
> >  #include <linux/compiler.h>
> > +#include <linux/regmap.h>
>
> No need to include this here, just provide a prototype for "struct
> regmap" and all will be fine.

Well noted, I will forward declare "struct regmap" in debugfs.h,
and move regmap.h to debugfs.c(regmap_read is used here).

Thanks for your review.

Regards,
Li