* [PATCH u-boot-marvell] arm64: a37xx: pinctrl: Fix PWM pins indexes
@ 2022-02-28 14:59 Marek Behún
2022-02-28 20:18 ` Pali Rohár
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Marek Behún @ 2022-02-28 14:59 UTC (permalink / raw)
To: Stefan Roese; +Cc: pali, u-boot, Marek Behún
From: Marek Behún <marek.behun@nic.cz>
Commit 5534fb4f4833 ("arm64: a37xx: pinctrl: Correct PWM pins
definitions") introduced bogus definitions os PWM pins: all 4 pins have
index 11, instead of having indexes 11, 12, 13, 14.
Fix this.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 1cf1f06f10..e76ef153e6 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -162,11 +162,11 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3),
"pwm", "led"),
- PIN_GRP_GPIO_3("pwm1", 11, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4),
+ PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4),
"pwm", "led"),
- PIN_GRP_GPIO_3("pwm2", 11, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5),
+ PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5),
"pwm", "led"),
- PIN_GRP_GPIO_3("pwm3", 11, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
+ PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
"pwm", "led"),
PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH u-boot-marvell] arm64: a37xx: pinctrl: Fix PWM pins indexes
2022-02-28 14:59 [PATCH u-boot-marvell] arm64: a37xx: pinctrl: Fix PWM pins indexes Marek Behún
@ 2022-02-28 20:18 ` Pali Rohár
2022-03-04 7:29 ` Stefan Roese
2022-03-04 12:23 ` Stefan Roese
2 siblings, 0 replies; 4+ messages in thread
From: Pali Rohár @ 2022-02-28 20:18 UTC (permalink / raw)
To: Marek Behún; +Cc: Stefan Roese, u-boot, Marek Behún
On Monday 28 February 2022 15:59:37 Marek Behún wrote:
> From: Marek Behún <marek.behun@nic.cz>
>
> Commit 5534fb4f4833 ("arm64: a37xx: pinctrl: Correct PWM pins
> definitions") introduced bogus definitions os PWM pins: all 4 pins have
> index 11, instead of having indexes 11, 12, 13, 14.
>
> Fix this.
>
> Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Pali Rohár <pali@kernel.org>
Fixes: 5534fb4f4833 ("arm64: a37xx: pinctrl: Correct PWM pins definitions")
> ---
> drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> index 1cf1f06f10..e76ef153e6 100644
> --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> @@ -162,11 +162,11 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
> PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
> PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3),
> "pwm", "led"),
> - PIN_GRP_GPIO_3("pwm1", 11, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4),
> + PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4),
> "pwm", "led"),
> - PIN_GRP_GPIO_3("pwm2", 11, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5),
> + PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5),
> "pwm", "led"),
> - PIN_GRP_GPIO_3("pwm3", 11, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
> + PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
> "pwm", "led"),
> PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
> PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH u-boot-marvell] arm64: a37xx: pinctrl: Fix PWM pins indexes
2022-02-28 14:59 [PATCH u-boot-marvell] arm64: a37xx: pinctrl: Fix PWM pins indexes Marek Behún
2022-02-28 20:18 ` Pali Rohár
@ 2022-03-04 7:29 ` Stefan Roese
2022-03-04 12:23 ` Stefan Roese
2 siblings, 0 replies; 4+ messages in thread
From: Stefan Roese @ 2022-03-04 7:29 UTC (permalink / raw)
To: Marek Behún; +Cc: pali, u-boot, Marek Behún
On 2/28/22 15:59, Marek Behún wrote:
> From: Marek Behún <marek.behun@nic.cz>
>
> Commit 5534fb4f4833 ("arm64: a37xx: pinctrl: Correct PWM pins
> definitions") introduced bogus definitions os PWM pins: all 4 pins have
> index 11, instead of having indexes 11, 12, 13, 14.
>
> Fix this.
>
> Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Thanks,
Stefan
> ---
> drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> index 1cf1f06f10..e76ef153e6 100644
> --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> @@ -162,11 +162,11 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
> PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
> PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3),
> "pwm", "led"),
> - PIN_GRP_GPIO_3("pwm1", 11, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4),
> + PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4),
> "pwm", "led"),
> - PIN_GRP_GPIO_3("pwm2", 11, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5),
> + PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5),
> "pwm", "led"),
> - PIN_GRP_GPIO_3("pwm3", 11, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
> + PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
> "pwm", "led"),
> PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
> PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
Viele Grüße,
Stefan Roese
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH u-boot-marvell] arm64: a37xx: pinctrl: Fix PWM pins indexes
2022-02-28 14:59 [PATCH u-boot-marvell] arm64: a37xx: pinctrl: Fix PWM pins indexes Marek Behún
2022-02-28 20:18 ` Pali Rohár
2022-03-04 7:29 ` Stefan Roese
@ 2022-03-04 12:23 ` Stefan Roese
2 siblings, 0 replies; 4+ messages in thread
From: Stefan Roese @ 2022-03-04 12:23 UTC (permalink / raw)
To: Marek Behún; +Cc: pali, u-boot, Marek Behún
On 2/28/22 15:59, Marek Behún wrote:
> From: Marek Behún <marek.behun@nic.cz>
>
> Commit 5534fb4f4833 ("arm64: a37xx: pinctrl: Correct PWM pins
> definitions") introduced bogus definitions os PWM pins: all 4 pins have
> index 11, instead of having indexes 11, 12, 13, 14.
>
> Fix this.
>
> Signed-off-by: Marek Behún <marek.behun@nic.cz>
Applied to u-boot-marvell/master
Thanks,
Stefan
> ---
> drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> index 1cf1f06f10..e76ef153e6 100644
> --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> @@ -162,11 +162,11 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
> PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
> PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3),
> "pwm", "led"),
> - PIN_GRP_GPIO_3("pwm1", 11, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4),
> + PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4),
> "pwm", "led"),
> - PIN_GRP_GPIO_3("pwm2", 11, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5),
> + PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5),
> "pwm", "led"),
> - PIN_GRP_GPIO_3("pwm3", 11, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
> + PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
> "pwm", "led"),
> PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
> PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
Viele Grüße,
Stefan Roese
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de
^ permalink raw reply [flat|nested] 4+ messages in thread
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2022-02-28 14:59 [PATCH u-boot-marvell] arm64: a37xx: pinctrl: Fix PWM pins indexes Marek Behún
2022-02-28 20:18 ` Pali Rohár
2022-03-04 7:29 ` Stefan Roese
2022-03-04 12:23 ` Stefan Roese
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