* [PATCH 00/15] Adding NV12 support
@ 2018-01-04 10:44 Vidya Srinivas
2018-01-04 10:44 ` [PATCH 01/15] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values Vidya Srinivas
` (15 more replies)
0 siblings, 16 replies; 26+ messages in thread
From: Vidya Srinivas @ 2018-01-04 10:44 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
This patch series is adding NV12 support for Broxton display after rebasing on
latest drm-tip.
Initial series of the patches can be found here:
https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html
Previous revision history:
The first version of patches were reviewed when floated by Chandra in 2015
but currently there was a design change with respect to
- the way fb offset is handled
- the way rotation is handled
Current NV12 patch series has been ported as per the
current changes on drm-tip
Review comments from Ville (12th June 2017) have been addressed Review
comments from Clinton A Taylor (7th July 2017) have been addressed
Review comments from Clinton A Taylor (10th July 2017)
have been addressed. Had missed out tested-by/reviewed-by in the patches.
Fixed that error in this series.
Review comments from Ville (11th July 2017) addressed.
Review comments from Paauwe, Bob (29th July 2017) addressed.
Update from rev 28 Aug 2017
Rebased the series.
Tested with IGT for rotation, sprite and tiling combinations.
IGT Links:
https://patchwork.kernel.org/patch/9995943/
https://patchwork.kernel.org/patch/9995945/
Update from last rev (31 July 2017)
Rebased the series.
Patches are tested (dependent on) watermark necessary changes
https://patchwork.freedesktop.org/series/33439/
Chandra Konduru (6):
drm/i915: Set scaler mode for NV12
drm/i915: Update format_is_yuv() to include NV12
drm/i915: Upscale scaler max scale for NV12
drm/i915: Add NV12 as supported format for primary plane
drm/i915: Add NV12 as supported format for sprite plane
drm/i915: Add NV12 support to intel_framebuffer_init
Mahesh Kumar (9):
drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
drm/i915/skl+: refactore WM calculation for NV12
drm/i915/skl+: add NV12 in skl_format_to_fourcc
drm/i915/skl+: support varification of DDB HW state for NV12
drm/i915/skl+: NV12 related changes for WM
drm/i915/skl+: pass skl_wm_level struct to wm compute func
drm/i915/skl+: make sure higher latency level has higher wm value
drm/i915/skl+: nv12 workaround disable WM level 1-7
drm/i915/skl: split skl_compute_ddb function
drivers/gpu/drm/i915/i915_drv.h | 7 +-
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_atomic.c | 8 +-
drivers/gpu/drm/i915/intel_display.c | 71 ++++--
drivers/gpu/drm/i915/intel_drv.h | 8 +-
drivers/gpu/drm/i915/intel_pm.c | 431 ++++++++++++++++++++++-------------
drivers/gpu/drm/i915/intel_sprite.c | 34 ++-
7 files changed, 372 insertions(+), 188 deletions(-)
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 01/15] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
2018-01-04 10:44 [PATCH 00/15] Adding NV12 support Vidya Srinivas
@ 2018-01-04 10:44 ` Vidya Srinivas
2018-01-04 10:44 ` [PATCH 02/15] drm/i915/skl+: refactore WM calculation for NV12 Vidya Srinivas
` (14 subsequent siblings)
15 siblings, 0 replies; 26+ messages in thread
From: Vidya Srinivas @ 2018-01-04 10:44 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
skl_wm_values struct contains values os pipe/plane DDB only.
so rename it for better readability of code.
s/skl_wm_values/skl_ddb_values
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 12 ++++++------
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index caebd58..56047f8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1437,7 +1437,7 @@ struct skl_ddb_allocation {
struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
};
-struct skl_wm_values {
+struct skl_ddb_values {
unsigned dirty_pipes;
struct skl_ddb_allocation ddb;
};
@@ -2131,7 +2131,7 @@ struct drm_i915_private {
/* current hardware state */
union {
struct ilk_wm_values hw;
- struct skl_wm_values skl_hw;
+ struct skl_ddb_values skl_hw;
struct vlv_wm_values vlv;
struct g4x_wm_values g4x;
};
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 30f791f..9c8aef9 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -397,7 +397,7 @@ struct intel_atomic_state {
bool skip_intermediate_wm;
/* Gen9+ only */
- struct skl_wm_values wm_results;
+ struct skl_ddb_values wm_results;
struct i915_sw_fence commit_ready;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1db79a8..e2598cf 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4997,8 +4997,8 @@ skl_compute_ddb(struct drm_atomic_state *state)
}
static void
-skl_copy_wm_for_pipe(struct skl_wm_values *dst,
- struct skl_wm_values *src,
+skl_copy_wm_for_pipe(struct skl_ddb_values *dst,
+ struct skl_ddb_values *src,
enum pipe pipe)
{
memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
@@ -5050,7 +5050,7 @@ skl_compute_wm(struct drm_atomic_state *state)
struct drm_crtc *crtc;
struct drm_crtc_state *cstate;
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
- struct skl_wm_values *results = &intel_state->wm_results;
+ struct skl_ddb_values *results = &intel_state->wm_results;
struct drm_device *dev = state->dev;
struct skl_pipe_wm *pipe_wm;
bool changed = false;
@@ -5152,8 +5152,8 @@ static void skl_initial_wm(struct intel_atomic_state *state,
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_device *dev = intel_crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct skl_wm_values *results = &state->wm_results;
- struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
+ struct skl_ddb_values *results = &state->wm_results;
+ struct skl_ddb_values *hw_vals = &dev_priv->wm.skl_hw;
enum pipe pipe = intel_crtc->pipe;
if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
@@ -5296,7 +5296,7 @@ void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
void skl_wm_get_hw_state(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
+ struct skl_ddb_values *hw = &dev_priv->wm.skl_hw;
struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
struct drm_crtc *crtc;
struct intel_crtc *intel_crtc;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 02/15] drm/i915/skl+: refactore WM calculation for NV12
2018-01-04 10:44 [PATCH 00/15] Adding NV12 support Vidya Srinivas
2018-01-04 10:44 ` [PATCH 01/15] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values Vidya Srinivas
@ 2018-01-04 10:44 ` Vidya Srinivas
2018-01-04 16:19 ` Maarten Lankhorst
2018-01-04 10:44 ` [PATCH 03/15] drm/i915/skl+: add NV12 in skl_format_to_fourcc Vidya Srinivas
` (13 subsequent siblings)
15 siblings, 1 reply; 26+ messages in thread
From: Vidya Srinivas @ 2018-01-04 10:44 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
Current code calculates DDB for planar formats in such a way that we
store DDB of plane-0 in plane 1 & vice-versa.
In order to make this clean this patch refactors WM/DDB calculation for
NV12 planar formats.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 120 +++++++++++++++++++--------------------
3 files changed, 62 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 56047f8..962717d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1434,7 +1434,7 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
struct skl_ddb_allocation {
struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
- struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
+ struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
};
struct skl_ddb_values {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9c8aef9..5f5e070 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -513,6 +513,7 @@ struct intel_pipe_wm {
struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level trans_wm;
+ bool is_nv12;
};
struct skl_pipe_wm {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e2598cf..15edb9a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4004,9 +4004,9 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
static unsigned int
skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
const struct drm_plane_state *pstate,
- int y)
+ const int plane)
{
- struct intel_plane *plane = to_intel_plane(pstate->plane);
+ struct intel_plane *intel_plane = to_intel_plane(pstate->plane);
struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
uint32_t data_rate;
uint32_t width = 0, height = 0;
@@ -4020,9 +4020,9 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
fb = pstate->fb;
format = fb->format->format;
- if (plane->id == PLANE_CURSOR)
+ if (intel_plane->id == PLANE_CURSOR)
return 0;
- if (y && format != DRM_FORMAT_NV12)
+ if (plane == 1 && format != DRM_FORMAT_NV12)
return 0;
/*
@@ -4033,19 +4033,14 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
width = drm_rect_width(&intel_pstate->base.src) >> 16;
height = drm_rect_height(&intel_pstate->base.src) >> 16;
- /* for planar format */
- if (format == DRM_FORMAT_NV12) {
- if (y) /* y-plane data rate */
- data_rate = width * height *
- fb->format->cpp[0];
- else /* uv-plane data rate */
- data_rate = (width / 2) * (height / 2) *
- fb->format->cpp[1];
- } else {
- /* for packed formats */
- data_rate = width * height * fb->format->cpp[0];
+ /* UV plane does 1/2 pixel sub-sampling */
+ if (plane == 1 && format == DRM_FORMAT_NV12) {
+ width /= 2;
+ height /= 2;
}
+ data_rate = width * height * fb->format->cpp[plane];
+
down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
return mul_round_up_u32_fixed16(data_rate, down_scale_amount);
@@ -4058,8 +4053,8 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
*/
static unsigned int
skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
- unsigned *plane_data_rate,
- unsigned *plane_y_data_rate)
+ unsigned int *plane_data_rate,
+ unsigned int *uv_plane_data_rate)
{
struct drm_crtc_state *cstate = &intel_cstate->base;
struct drm_atomic_state *state = cstate->state;
@@ -4075,17 +4070,16 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
enum plane_id plane_id = to_intel_plane(plane)->id;
unsigned int rate;
- /* packed/uv */
rate = skl_plane_relative_data_rate(intel_cstate,
pstate, 0);
plane_data_rate[plane_id] = rate;
total_data_rate += rate;
- /* y-plane */
+ /* uv-plane */
rate = skl_plane_relative_data_rate(intel_cstate,
pstate, 1);
- plane_y_data_rate[plane_id] = rate;
+ uv_plane_data_rate[plane_id] = rate;
total_data_rate += rate;
}
@@ -4094,8 +4088,7 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
}
static uint16_t
-skl_ddb_min_alloc(const struct drm_plane_state *pstate,
- const int y)
+skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
{
struct drm_framebuffer *fb = pstate->fb;
struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
@@ -4106,8 +4099,8 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate,
if (WARN_ON(!fb))
return 0;
- /* For packed formats, no y-plane, return 0 */
- if (y && fb->format->format != DRM_FORMAT_NV12)
+ /* For packed formats, and uv-plane, return 0 */
+ if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
return 0;
/* For Non Y-tile return 8-blocks */
@@ -4126,15 +4119,12 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate,
src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
/* Halve UV plane width and height for NV12 */
- if (fb->format->format == DRM_FORMAT_NV12 && !y) {
+ if (plane == 1) {
src_w /= 2;
src_h /= 2;
}
- if (fb->format->format == DRM_FORMAT_NV12 && !y)
- plane_bpp = fb->format->cpp[1];
- else
- plane_bpp = fb->format->cpp[0];
+ plane_bpp = fb->format->cpp[plane];
if (drm_rotation_90_or_270(pstate->rotation)) {
switch (plane_bpp) {
@@ -4162,7 +4152,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate,
static void
skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
- uint16_t *minimum, uint16_t *y_minimum)
+ uint16_t *minimum, uint16_t *uv_minimum)
{
const struct drm_plane_state *pstate;
struct drm_plane *plane;
@@ -4177,7 +4167,7 @@ skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
continue;
minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
- y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
+ uv_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
}
minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
@@ -4195,17 +4185,17 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
uint16_t alloc_size, start;
uint16_t minimum[I915_MAX_PLANES] = {};
- uint16_t y_minimum[I915_MAX_PLANES] = {};
+ uint16_t uv_minimum[I915_MAX_PLANES] = {};
unsigned int total_data_rate;
enum plane_id plane_id;
int num_active;
- unsigned plane_data_rate[I915_MAX_PLANES] = {};
- unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
+ unsigned int plane_data_rate[I915_MAX_PLANES] = {};
+ unsigned int uv_plane_data_rate[I915_MAX_PLANES] = {};
uint16_t total_min_blocks = 0;
/* Clear the partitioning for disabled planes. */
memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
- memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
+ memset(ddb->uv_plane[pipe], 0, sizeof(ddb->uv_plane[pipe]));
if (WARN_ON(!state))
return 0;
@@ -4220,7 +4210,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
if (alloc_size == 0)
return 0;
- skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
+ skl_ddb_calc_min(cstate, num_active, minimum, uv_minimum);
/*
* 1. Allocate the mininum required blocks for each active plane
@@ -4230,7 +4220,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
for_each_plane_id_on_crtc(intel_crtc, plane_id) {
total_min_blocks += minimum[plane_id];
- total_min_blocks += y_minimum[plane_id];
+ total_min_blocks += uv_minimum[plane_id];
}
if (total_min_blocks > alloc_size) {
@@ -4252,14 +4242,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
*/
total_data_rate = skl_get_total_relative_data_rate(cstate,
plane_data_rate,
- plane_y_data_rate);
+ uv_plane_data_rate);
if (total_data_rate == 0)
return 0;
start = alloc->start;
for_each_plane_id_on_crtc(intel_crtc, plane_id) {
- unsigned int data_rate, y_data_rate;
- uint16_t plane_blocks, y_plane_blocks = 0;
+ unsigned int data_rate, uv_data_rate;
+ uint16_t plane_blocks, uv_plane_blocks;
if (plane_id == PLANE_CURSOR)
continue;
@@ -4283,21 +4273,20 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
start += plane_blocks;
- /*
- * allocation for y_plane part of planar format:
- */
- y_data_rate = plane_y_data_rate[plane_id];
+ /* Allocate DDB for UV plane for planar format/NV12 */
+ uv_data_rate = uv_plane_data_rate[plane_id];
- y_plane_blocks = y_minimum[plane_id];
- y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
+ uv_plane_blocks = uv_minimum[plane_id];
+ uv_plane_blocks += div_u64((uint64_t)alloc_size * uv_data_rate,
total_data_rate);
- if (y_data_rate) {
- ddb->y_plane[pipe][plane_id].start = start;
- ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks;
+ if (uv_data_rate) {
+ ddb->uv_plane[pipe][plane_id].start = start;
+ ddb->uv_plane[pipe][plane_id].end = start +
+ uv_plane_blocks;
}
- start += y_plane_blocks;
+ start += uv_plane_blocks;
}
return 0;
@@ -4425,8 +4414,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
wp->width = drm_rect_width(&intel_pstate->base.src) >> 16;
}
- wp->cpp = (fb->format->format == DRM_FORMAT_NV12) ? fb->format->cpp[1] :
- fb->format->cpp[0];
+ wp->cpp = fb->format->cpp[0];
wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
intel_pstate);
@@ -4618,6 +4606,9 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
return ret;
}
+ if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
+ wm->is_nv12 = true;
+
return 0;
}
@@ -4788,10 +4779,19 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
&wm->trans_wm);
- skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
- &ddb->plane[pipe][plane_id]);
- skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
- &ddb->y_plane[pipe][plane_id]);
+ if (wm->is_nv12) {
+ skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
+ &ddb->uv_plane[pipe][plane_id]);
+ skl_ddb_entry_write(dev_priv,
+ PLANE_NV12_BUF_CFG(pipe, plane_id),
+ &ddb->plane[pipe][plane_id]);
+ } else {
+ skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
+ &ddb->plane[pipe][plane_id]);
+ skl_ddb_entry_write(dev_priv,
+ PLANE_NV12_BUF_CFG(pipe, plane_id),
+ &ddb->uv_plane[pipe][plane_id]);
+ }
}
static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
@@ -4906,8 +4906,8 @@ skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
&new_ddb->plane[pipe][plane_id]) &&
- skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id],
- &new_ddb->y_plane[pipe][plane_id]))
+ skl_ddb_entry_equal(&cur_ddb->uv_plane[pipe][plane_id],
+ &new_ddb->uv_plane[pipe][plane_id]))
continue;
plane_state = drm_atomic_get_plane_state(state, plane);
@@ -5001,8 +5001,8 @@ skl_copy_wm_for_pipe(struct skl_ddb_values *dst,
struct skl_ddb_values *src,
enum pipe pipe)
{
- memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
- sizeof(dst->ddb.y_plane[pipe]));
+ memcpy(dst->ddb.uv_plane[pipe], src->ddb.uv_plane[pipe],
+ sizeof(dst->ddb.uv_plane[pipe]));
memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
sizeof(dst->ddb.plane[pipe]));
}
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 03/15] drm/i915/skl+: add NV12 in skl_format_to_fourcc
2018-01-04 10:44 [PATCH 00/15] Adding NV12 support Vidya Srinivas
2018-01-04 10:44 ` [PATCH 01/15] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values Vidya Srinivas
2018-01-04 10:44 ` [PATCH 02/15] drm/i915/skl+: refactore WM calculation for NV12 Vidya Srinivas
@ 2018-01-04 10:44 ` Vidya Srinivas
2018-01-04 10:44 ` [PATCH 06/15] drm/i915/skl+: pass skl_wm_level struct to wm compute func Vidya Srinivas
` (12 subsequent siblings)
15 siblings, 0 replies; 26+ messages in thread
From: Vidya Srinivas @ 2018-01-04 10:44 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
Add support of recognizing DRM_FORMAT_NV12 from plane_format
register value.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0cd3559..81aa5f1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2612,6 +2612,8 @@ static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
switch (format) {
case PLANE_CTL_FORMAT_RGB_565:
return DRM_FORMAT_RGB565;
+ case PLANE_CTL_FORMAT_NV12:
+ return DRM_FORMAT_NV12;
default:
case PLANE_CTL_FORMAT_XRGB_8888:
if (rgb_order) {
--
2.7.4
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 06/15] drm/i915/skl+: pass skl_wm_level struct to wm compute func
2018-01-04 10:44 [PATCH 00/15] Adding NV12 support Vidya Srinivas
` (2 preceding siblings ...)
2018-01-04 10:44 ` [PATCH 03/15] drm/i915/skl+: add NV12 in skl_format_to_fourcc Vidya Srinivas
@ 2018-01-04 10:44 ` Vidya Srinivas
2018-01-04 10:44 ` [PATCH 05/15] drm/i915/skl+: NV12 related changes for WM Vidya Srinivas
` (11 subsequent siblings)
15 siblings, 0 replies; 26+ messages in thread
From: Vidya Srinivas @ 2018-01-04 10:44 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
This will reduce number of arguments required to be pass in
skl_compute_plane_wm function.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 18 +++++++-----------
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1aabe44..5e646c5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4513,9 +4513,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
uint16_t ddb_allocation,
int level,
const struct skl_wm_params *wp,
- uint16_t *out_blocks, /* out */
- uint8_t *out_lines, /* out */
- bool *enabled /* out */)
+ struct skl_wm_level *result /* out */)
{
const struct drm_plane_state *pstate = &intel_pstate->base;
uint32_t latency = dev_priv->wm.skl_latency[level];
@@ -4528,7 +4526,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
if (latency == 0 ||
!intel_wm_plane_visible(cstate, intel_pstate)) {
- *enabled = false;
+ result->plane_en = false;
return 0;
}
@@ -4583,7 +4581,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
}
if (res_blocks >= ddb_allocation || res_lines > 31) {
- *enabled = false;
+ result->plane_en = false;
/*
* If there are no valid level 0 watermarks, then we can't
@@ -4602,9 +4600,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
}
}
- *out_blocks = res_blocks;
- *out_lines = res_lines;
- *enabled = true;
+ result->plane_res_b = res_blocks;
+ result->plane_res_l = res_lines;
+ result->plane_en = true;
return 0;
}
@@ -4645,9 +4643,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
ddb_blocks,
level,
wm_params,
- &result->plane_res_b,
- &result->plane_res_l,
- &result->plane_en);
+ result);
if (ret)
return ret;
}
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 05/15] drm/i915/skl+: NV12 related changes for WM
2018-01-04 10:44 [PATCH 00/15] Adding NV12 support Vidya Srinivas
` (3 preceding siblings ...)
2018-01-04 10:44 ` [PATCH 06/15] drm/i915/skl+: pass skl_wm_level struct to wm compute func Vidya Srinivas
@ 2018-01-04 10:44 ` Vidya Srinivas
2018-01-04 10:44 ` [PATCH 04/15] drm/i915/skl+: support varification of DDB HW state for NV12 Vidya Srinivas
` (10 subsequent siblings)
15 siblings, 0 replies; 26+ messages in thread
From: Vidya Srinivas @ 2018-01-04 10:44 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
NV12 require WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 54 ++++++++++++++++++++++++++++++++--------
3 files changed, 45 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 962717d..bb104ec 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1452,6 +1452,7 @@ struct skl_wm_level {
struct skl_wm_params {
bool x_tiled, y_tiled;
bool rc_surface;
+ bool is_nv12;
uint32_t width;
uint8_t cpp;
uint32_t plane_pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d245481..5e13ad5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -512,6 +512,7 @@ struct intel_pipe_wm {
struct skl_plane_wm {
struct skl_wm_level wm[8];
+ struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
bool is_nv12;
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5c268b9..1aabe44 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4412,7 +4412,7 @@ static int
skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
struct intel_crtc_state *cstate,
const struct intel_plane_state *intel_pstate,
- struct skl_wm_params *wp)
+ struct skl_wm_params *wp, int plane_num)
{
struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
const struct drm_plane_state *pstate = &intel_pstate->base;
@@ -4425,6 +4425,12 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
if (!intel_wm_plane_visible(cstate, intel_pstate))
return 0;
+ /* only NV12 format has two planes */
+ if (plane_num == 1 && fb->format->format != DRM_FORMAT_NV12) {
+ DRM_DEBUG_KMS("Non NV12 format have single plane\n");
+ return -EINVAL;
+ }
+
wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
@@ -4432,6 +4438,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+ wp->is_nv12 = fb->format->format == DRM_FORMAT_NV12;
if (plane->id == PLANE_CURSOR) {
wp->width = intel_pstate->base.crtc_w;
@@ -4444,7 +4451,10 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
wp->width = drm_rect_width(&intel_pstate->base.src) >> 16;
}
- wp->cpp = fb->format->cpp[0];
+ if (plane_num == 1 && wp->is_nv12)
+ wp->width /= 2;
+
+ wp->cpp = fb->format->cpp[plane_num];
wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
intel_pstate);
@@ -4605,7 +4615,8 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
struct intel_crtc_state *cstate,
const struct intel_plane_state *intel_pstate,
const struct skl_wm_params *wm_params,
- struct skl_plane_wm *wm)
+ struct skl_plane_wm *wm,
+ int plane_num)
{
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_plane *plane = intel_pstate->base.plane;
@@ -4613,15 +4624,20 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
uint16_t ddb_blocks;
enum pipe pipe = intel_crtc->pipe;
int level, max_level = ilk_wm_max_level(dev_priv);
+ enum plane_id plane_id = intel_plane->id;
int ret;
if (WARN_ON(!intel_pstate->base.fb))
return -EINVAL;
- ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
+ if (plane_num == 0)
+ ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
+ else
+ ddb_blocks = skl_ddb_entry_size(&ddb->uv_plane[pipe][plane_id]);
for (level = 0; level <= max_level; level++) {
- struct skl_wm_level *result = &wm->wm[level];
+ struct skl_wm_level *result = plane_num ? &wm->uv_wm[level] :
+ &wm->wm[level];
ret = skl_compute_plane_wm(dev_priv,
cstate,
@@ -4636,9 +4652,6 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
return ret;
}
- if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
- wm->is_nv12 = true;
-
return 0;
}
@@ -4747,20 +4760,39 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
wm = &pipe_wm->planes[plane_id];
ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
- memset(&wm_params, 0, sizeof(struct skl_wm_params));
ret = skl_compute_plane_wm_params(dev_priv, cstate,
- intel_pstate, &wm_params);
+ intel_pstate, &wm_params, 0);
if (ret)
return ret;
ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
- intel_pstate, &wm_params, wm);
+ intel_pstate, &wm_params, wm, 0);
if (ret)
return ret;
+
skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0],
ddb_blocks, &wm->trans_wm);
+
+ /* uv plane watermarks must also be validated for NV12 */
+ if (wm_params.is_nv12) {
+ memset(&wm_params, 0, sizeof(struct skl_wm_params));
+ wm->is_nv12 = true;
+
+ ret = skl_compute_plane_wm_params(dev_priv, cstate,
+ intel_pstate,
+ &wm_params, 1);
+ if (ret)
+ return ret;
+
+ ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
+ intel_pstate, &wm_params,
+ wm, 1);
+ if (ret)
+ return ret;
+ }
}
+
pipe_wm->linetime = skl_compute_linetime_wm(cstate);
return 0;
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 04/15] drm/i915/skl+: support varification of DDB HW state for NV12
2018-01-04 10:44 [PATCH 00/15] Adding NV12 support Vidya Srinivas
` (4 preceding siblings ...)
2018-01-04 10:44 ` [PATCH 05/15] drm/i915/skl+: NV12 related changes for WM Vidya Srinivas
@ 2018-01-04 10:44 ` Vidya Srinivas
2018-01-05 12:16 ` Maarten Lankhorst
2018-01-04 10:44 ` [PATCH 07/15] drm/i915/skl+: make sure higher latency level has higher wm value Vidya Srinivas
` (9 subsequent siblings)
15 siblings, 1 reply; 26+ messages in thread
From: Vidya Srinivas @ 2018-01-04 10:44 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
NV12 formats have two registers for DDB. verify both the registers for
NV12 during verify_wm_state.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 50 ++++++++++++++++++++++++++++--------
3 files changed, 42 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 81aa5f1..af3144d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2607,7 +2607,7 @@ static int i9xx_format_to_fourcc(int format)
}
}
-static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
+int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
{
switch (format) {
case PLANE_CTL_FORMAT_RGB_565:
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5f5e070..d245481 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1510,6 +1510,7 @@ u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
unsigned int rotation);
int skl_check_plane_surface(struct intel_plane_state *plane_state);
int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
+int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
/* intel_csr.c */
void intel_csr_ucode_init(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 15edb9a..5c268b9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3820,6 +3820,43 @@ static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
entry->end += 1;
}
+static void
+skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
+ const enum pipe pipe,
+ const enum plane_id plane_id,
+ struct skl_ddb_allocation *ddb /* out */)
+{
+ u32 val, val2 = 0;
+ int fourcc, pixel_format;
+
+ /* Cursor doesn't support NV12, so no extra calculation needed */
+ if (plane_id == PLANE_CURSOR) {
+ val = I915_READ(CUR_BUF_CFG(pipe));
+ skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
+ return;
+ }
+
+ val = I915_READ(PLANE_CTL(pipe, plane_id));
+
+ /* No DDB allocated for disabled planes */
+ if (!(val & PLANE_CTL_ENABLE))
+ return;
+
+ pixel_format = val & PLANE_CTL_FORMAT_MASK;
+ fourcc = skl_format_to_fourcc(pixel_format,
+ val & PLANE_CTL_ORDER_RGBX,
+ val & PLANE_CTL_ALPHA_MASK);
+
+ val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
+ val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
+
+ if (fourcc == DRM_FORMAT_NV12) {
+ skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val2);
+ skl_ddb_entry_init_from_hw(&ddb->uv_plane[pipe][plane_id], val);
+ } else
+ skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
+}
+
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
struct skl_ddb_allocation *ddb /* out */)
{
@@ -3836,16 +3873,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
continue;
- for_each_plane_id_on_crtc(crtc, plane_id) {
- u32 val;
-
- if (plane_id != PLANE_CURSOR)
- val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
- else
- val = I915_READ(CUR_BUF_CFG(pipe));
-
- skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
- }
+ for_each_plane_id_on_crtc(crtc, plane_id)
+ skl_ddb_get_hw_plane_state(dev_priv, pipe,
+ plane_id, ddb);
intel_display_power_put(dev_priv, power_domain);
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 07/15] drm/i915/skl+: make sure higher latency level has higher wm value
2018-01-04 10:44 [PATCH 00/15] Adding NV12 support Vidya Srinivas
` (5 preceding siblings ...)
2018-01-04 10:44 ` [PATCH 04/15] drm/i915/skl+: support varification of DDB HW state for NV12 Vidya Srinivas
@ 2018-01-04 10:44 ` Vidya Srinivas
2018-01-04 10:44 ` [PATCH 11/15] drm/i915: Update format_is_yuv() to include NV12 Vidya Srinivas
` (8 subsequent siblings)
15 siblings, 0 replies; 26+ messages in thread
From: Vidya Srinivas @ 2018-01-04 10:44 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
DDB allocation optimization algorithm require/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below.
Render decompression require level WM to be as high as wm level-0.
This patch fulfils both the requirements.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5e646c5..d75fd3b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4513,6 +4513,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
uint16_t ddb_allocation,
int level,
const struct skl_wm_params *wp,
+ const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */)
{
const struct drm_plane_state *pstate = &intel_pstate->base;
@@ -4578,6 +4579,15 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
} else {
res_blocks++;
}
+
+ /*
+ * Make sure result blocks for higher latency levels are atleast
+ * as high as level below.
+ * Assumption in DDB algorithm optimization for special cases.
+ * Also covers Display WA #1125 for RC.
+ */
+ if (result_prev->plane_res_b > res_blocks)
+ res_blocks = result_prev->plane_res_b;
}
if (res_blocks >= ddb_allocation || res_lines > 31) {
@@ -4636,6 +4646,13 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = plane_num ? &wm->uv_wm[level] :
&wm->wm[level];
+ struct skl_wm_level *result_prev;
+
+ if (level)
+ result_prev = plane_num ? &wm->uv_wm[level - 1] :
+ &wm->wm[level - 1];
+ else
+ result_prev = plane_num ? &wm->uv_wm[0] : &wm->wm[0];
ret = skl_compute_plane_wm(dev_priv,
cstate,
@@ -4643,6 +4660,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
ddb_blocks,
level,
wm_params,
+ result_prev,
result);
if (ret)
return ret;
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 11/15] drm/i915: Update format_is_yuv() to include NV12
2018-01-04 10:44 [PATCH 00/15] Adding NV12 support Vidya Srinivas
` (6 preceding siblings ...)
2018-01-04 10:44 ` [PATCH 07/15] drm/i915/skl+: make sure higher latency level has higher wm value Vidya Srinivas
@ 2018-01-04 10:44 ` Vidya Srinivas
2018-01-04 10:44 ` [PATCH 09/15] drm/i915/skl: split skl_compute_ddb function Vidya Srinivas
` (7 subsequent siblings)
15 siblings, 0 replies; 26+ messages in thread
From: Vidya Srinivas @ 2018-01-04 10:44 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
From: Chandra Konduru <chandra.konduru@intel.com>
This patch adds NV12 to format_is_yuv() function
for sprite planes.
v2:
-Use intel_ prefix for format_is_yuv (Ville)
v3: Rebased (me)
v4: Rebased and addressed review comments from Clinton A Taylor.
"static function in intel_sprite.c is not available
to the primary plane functions".
Changed commit message - function modified for
sprite planes.
v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v6: Rebased (me)
v7: Rebased (me)
v8: Rebased (me)
v9: Rebased (me)
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/intel_sprite.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index dd485f5..58f56de 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -42,13 +42,14 @@
#include "i915_drv.h"
static bool
-format_is_yuv(uint32_t format)
+intel_format_is_yuv(uint32_t format)
{
switch (format) {
case DRM_FORMAT_YUYV:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_YVYU:
+ case DRM_FORMAT_NV12:
return true;
default:
return false;
@@ -352,7 +353,7 @@ chv_update_csc(struct intel_plane *plane, uint32_t format)
enum plane_id plane_id = plane->id;
/* Seems RGB data bypasses the CSC always */
- if (!format_is_yuv(format))
+ if (!intel_format_is_yuv(format))
return;
/*
@@ -974,7 +975,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
src_y = src->y1 >> 16;
src_h = drm_rect_height(src) >> 16;
- if (format_is_yuv(fb->format->format)) {
+ if (intel_format_is_yuv(fb->format->format)) {
src_x &= ~1;
src_w &= ~1;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 09/15] drm/i915/skl: split skl_compute_ddb function
2018-01-04 10:44 [PATCH 00/15] Adding NV12 support Vidya Srinivas
` (7 preceding siblings ...)
2018-01-04 10:44 ` [PATCH 11/15] drm/i915: Update format_is_yuv() to include NV12 Vidya Srinivas
@ 2018-01-04 10:44 ` Vidya Srinivas
2018-01-04 10:44 ` [PATCH 08/15] drm/i915/skl+: nv12 workaround disable WM level 1-7 Vidya Srinivas
` (6 subsequent siblings)
15 siblings, 0 replies; 26+ messages in thread
From: Vidya Srinivas @ 2018-01-04 10:44 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
This patch split skl_compute_wm/ddb functions into two parts.
One adds all affected pipes after the commit to atomic_state structure
and second part does compute the DDB.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 158 ++++++++++++++++++++++------------------
1 file changed, 89 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 90aa216..2c49311 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5008,69 +5008,16 @@ skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
static int
skl_compute_ddb(struct drm_atomic_state *state)
{
- struct drm_device *dev = state->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ const struct drm_i915_private *dev_priv = to_i915(state->dev);
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
- struct intel_crtc *intel_crtc;
struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
- uint32_t realloc_pipes = pipes_modified(state);
- int ret;
-
- /*
- * If this is our first atomic update following hardware readout,
- * we can't trust the DDB that the BIOS programmed for us. Let's
- * pretend that all pipes switched active status so that we'll
- * ensure a full DDB recompute.
- */
- if (dev_priv->wm.distrust_bios_wm) {
- ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
- state->acquire_ctx);
- if (ret)
- return ret;
-
- intel_state->active_pipe_changes = ~0;
-
- /*
- * We usually only initialize intel_state->active_crtcs if we
- * we're doing a modeset; make sure this field is always
- * initialized during the sanitization process that happens
- * on the first commit too.
- */
- if (!intel_state->modeset)
- intel_state->active_crtcs = dev_priv->active_crtcs;
- }
-
- /*
- * If the modeset changes which CRTC's are active, we need to
- * recompute the DDB allocation for *all* active pipes, even
- * those that weren't otherwise being modified in any way by this
- * atomic commit. Due to the shrinking of the per-pipe allocations
- * when new active CRTC's are added, it's possible for a pipe that
- * we were already using and aren't changing at all here to suddenly
- * become invalid if its DDB needs exceeds its new allocation.
- *
- * Note that if we wind up doing a full DDB recompute, we can't let
- * any other display updates race with this transaction, so we need
- * to grab the lock on *all* CRTC's.
- */
- if (intel_state->active_pipe_changes) {
- realloc_pipes = ~0;
- intel_state->wm_results.dirty_pipes = ~0;
- }
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *cstate;
+ int ret, i;
- /*
- * We're not recomputing for the pipes not included in the commit, so
- * make sure we start with the current state.
- */
memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
- for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
- struct intel_crtc_state *cstate;
-
- cstate = intel_atomic_get_crtc_state(state, intel_crtc);
- if (IS_ERR(cstate))
- return PTR_ERR(cstate);
-
+ for_each_new_intel_crtc_in_state(intel_state, crtc, cstate, i) {
ret = skl_allocate_pipe_ddb(cstate, ddb);
if (ret)
return ret;
@@ -5132,23 +5079,23 @@ skl_print_wm_changes(const struct drm_atomic_state *state)
}
static int
-skl_compute_wm(struct drm_atomic_state *state)
+skl_ddb_add_affected_pipes(struct drm_atomic_state *state, bool *changed)
{
- struct drm_crtc *crtc;
- struct drm_crtc_state *cstate;
- struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
- struct skl_ddb_values *results = &intel_state->wm_results;
struct drm_device *dev = state->dev;
- struct skl_pipe_wm *pipe_wm;
- bool changed = false;
+ const struct drm_i915_private *dev_priv = to_i915(dev);
+ const struct drm_crtc *crtc;
+ const struct drm_crtc_state *cstate;
+ struct intel_crtc *intel_crtc;
+ struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+ uint32_t realloc_pipes = pipes_modified(state);
int ret, i;
/*
* When we distrust bios wm we always need to recompute to set the
* expected DDB allocations for each CRTC.
*/
- if (to_i915(dev)->wm.distrust_bios_wm)
- changed = true;
+ if (dev_priv->wm.distrust_bios_wm)
+ *changed = true;
/*
* If this transaction isn't actually touching any CRTC's, don't
@@ -5159,14 +5106,87 @@ skl_compute_wm(struct drm_atomic_state *state)
* hold _all_ CRTC state mutexes.
*/
for_each_new_crtc_in_state(state, crtc, cstate, i)
- changed = true;
+ *changed = true;
- if (!changed)
+ if (!*changed)
return 0;
+ /*
+ * If this is our first atomic update following hardware readout,
+ * we can't trust the DDB that the BIOS programmed for us. Let's
+ * pretend that all pipes switched active status so that we'll
+ * ensure a full DDB recompute.
+ */
+ if (dev_priv->wm.distrust_bios_wm) {
+ ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
+ state->acquire_ctx);
+ if (ret)
+ return ret;
+
+ intel_state->active_pipe_changes = ~0;
+
+ /*
+ * We usually only initialize intel_state->active_crtcs if we
+ * we're doing a modeset; make sure this field is always
+ * initialized during the sanitization process that happens
+ * on the first commit too.
+ */
+ if (!intel_state->modeset)
+ intel_state->active_crtcs = dev_priv->active_crtcs;
+ }
+
+ /*
+ * If the modeset changes which CRTC's are active, we need to
+ * recompute the DDB allocation for *all* active pipes, even
+ * those that weren't otherwise being modified in any way by this
+ * atomic commit. Due to the shrinking of the per-pipe allocations
+ * when new active CRTC's are added, it's possible for a pipe that
+ * we were already using and aren't changing at all here to suddenly
+ * become invalid if its DDB needs exceeds its new allocation.
+ *
+ * Note that if we wind up doing a full DDB recompute, we can't let
+ * any other display updates race with this transaction, so we need
+ * to grab the lock on *all* CRTC's.
+ */
+ if (intel_state->active_pipe_changes) {
+ realloc_pipes = ~0;
+ intel_state->wm_results.dirty_pipes = ~0;
+ }
+
+ /*
+ * We're not recomputing for the pipes not included in the commit, so
+ * make sure we start with the current state.
+ */
+ for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
+ struct intel_crtc_state *cstate;
+
+ cstate = intel_atomic_get_crtc_state(state, intel_crtc);
+ if (IS_ERR(cstate))
+ return PTR_ERR(cstate);
+ }
+
+ return 0;
+}
+
+
+static int
+skl_compute_wm(struct drm_atomic_state *state)
+{
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *cstate;
+ struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+ struct skl_ddb_values *results = &intel_state->wm_results;
+ struct skl_pipe_wm *pipe_wm;
+ bool changed = false;
+ int ret, i;
+
/* Clear all dirty flags */
results->dirty_pipes = 0;
+ ret = skl_ddb_add_affected_pipes(state, &changed);
+ if (ret || !changed)
+ return ret;
+
ret = skl_compute_ddb(state);
if (ret)
return ret;
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 08/15] drm/i915/skl+: nv12 workaround disable WM level 1-7
2018-01-04 10:44 [PATCH 00/15] Adding NV12 support Vidya Srinivas
` (8 preceding siblings ...)
2018-01-04 10:44 ` [PATCH 09/15] drm/i915/skl: split skl_compute_ddb function Vidya Srinivas
@ 2018-01-04 10:44 ` Vidya Srinivas
2018-01-08 12:07 ` Maarten Lankhorst
2018-01-04 10:44 ` [PATCH 12/15] drm/i915: Upscale scaler max scale for NV12 Vidya Srinivas
` (5 subsequent siblings)
15 siblings, 1 reply; 26+ messages in thread
From: Vidya Srinivas @ 2018-01-04 10:44 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A)
Hardware sometimes fails to wake memory from pkg C states fetching the
last few lines of planar YUV 420 (NV12) planes. This causes
intermittent underflow and corruption.
WA: Disable package C states or do not enable latency levels 1 through 7
(WM1 - WM7) on NV12 planes.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d75fd3b..90aa216 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4610,6 +4610,17 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
}
}
+ /*
+ * Display WA #826 (SKL:ALL, BXT:ALL) & #1059 (CNL:A)
+ * disable wm level 1-7 on NV12 planes
+ */
+ if (wp->is_nv12 && level && (IS_SKYLAKE(dev_priv) ||
+ IS_BROXTON(dev_priv) ||
+ IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {
+ result->plane_en = false;
+ return 0;
+ }
+
result->plane_res_b = res_blocks;
result->plane_res_l = res_lines;
result->plane_en = true;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 12/15] drm/i915: Upscale scaler max scale for NV12
2018-01-04 10:44 [PATCH 00/15] Adding NV12 support Vidya Srinivas
` (9 preceding siblings ...)
2018-01-04 10:44 ` [PATCH 08/15] drm/i915/skl+: nv12 workaround disable WM level 1-7 Vidya Srinivas
@ 2018-01-04 10:44 ` Vidya Srinivas
2018-01-04 10:44 ` [PATCH 13/15] drm/i915: Add NV12 as supported format for primary plane Vidya Srinivas
` (4 subsequent siblings)
15 siblings, 0 replies; 26+ messages in thread
From: Vidya Srinivas @ 2018-01-04 10:44 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
From: Chandra Konduru <chandra.konduru@intel.com>
This patch updates scaler max limit support for NV12
v2: Rebased (me)
v3: Rebased (me)
v4: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v5: Addressed review comments from Ville and rebased
- calculation of max_scale to be made
less convoluted by splitting it up a bit
- Indentation errors to be fixed in the series
v6: Rebased (me)
Fixed review comments from Paauwe, Bob J
Previous version, where a split of calculation
was done, was wrong. Fixed that issue here.
v7: Rebased (me)
v8: Rebased (me)
v9: Rebased (me)
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 33 +++++++++++++++++++++++----------
drivers/gpu/drm/i915/intel_drv.h | 3 ++-
drivers/gpu/drm/i915/intel_sprite.c | 3 ++-
3 files changed, 27 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index af3144d..d05890b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3405,6 +3405,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
case DRM_FORMAT_VYUY:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
+ case DRM_FORMAT_NV12:
+ return PLANE_CTL_FORMAT_NV12;
default:
MISSING_CASE(pixel_format);
}
@@ -4628,7 +4630,8 @@ static void cpt_verify_modeset(struct drm_device *dev, int pipe)
static int
skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
unsigned int scaler_user, int *scaler_id,
- int src_w, int src_h, int dst_w, int dst_h)
+ int src_w, int src_h, int dst_w, int dst_h,
+ uint32_t pixel_format)
{
struct intel_crtc_scaler_state *scaler_state =
&crtc_state->scaler_state;
@@ -4644,7 +4647,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
* the 90/270 degree plane rotation cases (to match the
* GTT mapping), hence no need to account for rotation here.
*/
- need_scaling = src_w != dst_w || src_h != dst_h;
+ need_scaling = src_w != dst_w || src_h != dst_h ||
+ (pixel_format == DRM_FORMAT_NV12);
if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
need_scaling = true;
@@ -4723,7 +4727,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state)
return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
&state->scaler_state.scaler_id,
state->pipe_src_w, state->pipe_src_h,
- adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
+ adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay, 0);
}
/**
@@ -4753,7 +4757,8 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
drm_rect_width(&plane_state->base.src) >> 16,
drm_rect_height(&plane_state->base.src) >> 16,
drm_rect_width(&plane_state->base.dst),
- drm_rect_height(&plane_state->base.dst));
+ drm_rect_height(&plane_state->base.dst),
+ fb ? fb->format->format : 0);
if (ret || plane_state->scaler_id < 0)
return ret;
@@ -4779,6 +4784,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+ case DRM_FORMAT_NV12:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
@@ -12703,11 +12709,12 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
}
int
-skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
+skl_max_scale(struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *crtc_state, uint32_t pixel_format)
{
struct drm_i915_private *dev_priv;
- int max_scale;
- int crtc_clock, max_dotclk;
+ int max_scale, mult;
+ int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
if (!intel_crtc || !crtc_state->base.enable)
return DRM_PLANE_HELPER_NO_SCALING;
@@ -12729,8 +12736,10 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state
* or
* cdclk/crtc_clock
*/
- max_scale = min((1 << 16) * 3 - 1,
- (1 << 8) * ((max_dotclk << 8) / crtc_clock));
+ mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
+ tmpclk1 = (1 << 16) * mult - 1;
+ tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
+ max_scale = min(tmpclk1, tmpclk2);
return max_scale;
}
@@ -12751,7 +12760,11 @@ intel_check_primary_plane(struct intel_plane *plane,
/* use scaler when colorkey is not required */
if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
min_scale = 1;
- max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
+ max_scale = skl_max_scale(to_intel_crtc(crtc),
+ crtc_state,
+ state->base.fb ?
+ state->base.fb->format->format :
+ 0);
}
can_position = true;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5e13ad5..485690d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1496,7 +1496,8 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
struct intel_crtc_state *pipe_config);
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
-int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
+int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
+ uint32_t pixel_format);
static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
{
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 58f56de..09732ae 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -897,7 +897,8 @@ intel_check_sprite_plane(struct intel_plane *plane,
if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
can_scale = 1;
min_scale = 1;
- max_scale = skl_max_scale(crtc, crtc_state);
+ max_scale = skl_max_scale(crtc, crtc_state,
+ fb->format->format);
} else {
can_scale = 0;
min_scale = DRM_PLANE_HELPER_NO_SCALING;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 10/15] drm/i915: Set scaler mode for NV12
2018-01-04 10:44 [PATCH 00/15] Adding NV12 support Vidya Srinivas
` (11 preceding siblings ...)
2018-01-04 10:44 ` [PATCH 13/15] drm/i915: Add NV12 as supported format for primary plane Vidya Srinivas
@ 2018-01-04 10:44 ` Vidya Srinivas
2018-01-04 10:44 ` [PATCH 14/15] drm/i915: Add NV12 as supported format for sprite plane Vidya Srinivas
` (2 subsequent siblings)
15 siblings, 0 replies; 26+ messages in thread
From: Vidya Srinivas @ 2018-01-04 10:44 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
From: Chandra Konduru <chandra.konduru@intel.com>
This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling
v2: Review comments from Ville addressed
NV12 case to be checked first for setting
the scaler
v3: Rebased (me)
v4: Rebased (me)
v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v6: Rebased (me)
v7: Rebased (me)
v8: Rebased (me)
Restricting the NV12 change for scaler to BXT and KBL
in this series.
v9: Rebased (me)
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_atomic.c | 8 +++++++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 966e4df..c29282f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6655,6 +6655,7 @@ enum {
#define PS_SCALER_MODE_MASK (3 << 28)
#define PS_SCALER_MODE_DYN (0 << 28)
#define PS_SCALER_MODE_HQ (1 << 28)
+#define PS_SCALER_MODE_NV12 (2 << 28)
#define PS_PLANE_SEL_MASK (7 << 25)
#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
#define PS_FILTER_MASK (3 << 23)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index 36d4e63..606b5e3 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -325,7 +325,13 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
}
/* set scaler mode */
- if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+ if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
+ plane_state && plane_state->base.fb &&
+ plane_state->base.fb->format->format ==
+ DRM_FORMAT_NV12) {
+ scaler_state->scalers[*scaler_id].mode =
+ PS_SCALER_MODE_NV12;
+ } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
scaler_state->scalers[*scaler_id].mode = 0;
} else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
/*
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 13/15] drm/i915: Add NV12 as supported format for primary plane
2018-01-04 10:44 [PATCH 00/15] Adding NV12 support Vidya Srinivas
` (10 preceding siblings ...)
2018-01-04 10:44 ` [PATCH 12/15] drm/i915: Upscale scaler max scale for NV12 Vidya Srinivas
@ 2018-01-04 10:44 ` Vidya Srinivas
2018-01-08 12:31 ` Maarten Lankhorst
2018-01-04 10:44 ` [PATCH 10/15] drm/i915: Set scaler mode for NV12 Vidya Srinivas
` (3 subsequent siblings)
15 siblings, 1 reply; 26+ messages in thread
From: Vidya Srinivas @ 2018-01-04 10:44 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
From: Chandra Konduru <chandra.konduru@intel.com>
This patch adds NV12 to list of supported formats for
primary plane
v2: Rebased (Chandra Konduru)
v3: Rebased (me)
v4: Review comments by Ville addressed
Removed the skl_primary_formats_with_nv12 and
added NV12 case in existing skl_primary_formats
v5: Rebased (me)
v6: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v7: Review comments by Ville addressed
Restricting the NV12 for BXT and on PIPE A and B
Rebased (me)
v8: Rebased (me)
Modified restricting the NV12 support for both BXT and KBL.
v9: Rebased (me)
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 26 ++++++++++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d05890b..4b92e41 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -106,6 +106,22 @@ static const uint64_t skl_format_modifiers_ccs[] = {
DRM_FORMAT_MOD_INVALID
};
+static const uint32_t nv12_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+};
+
/* Cursor formats */
static const uint32_t intel_cursor_formats[] = {
DRM_FORMAT_ARGB8888,
@@ -13180,8 +13196,14 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
primary->disable_plane = skl_disable_plane;
primary->get_hw_state = skl_plane_get_hw_state;
} else if (INTEL_GEN(dev_priv) >= 9) {
- intel_primary_formats = skl_primary_formats;
- num_formats = ARRAY_SIZE(skl_primary_formats);
+ if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
+ ((pipe == PIPE_A || pipe == PIPE_B))) {
+ intel_primary_formats = nv12_primary_formats;
+ num_formats = ARRAY_SIZE(nv12_primary_formats);
+ } else {
+ intel_primary_formats = skl_primary_formats;
+ num_formats = ARRAY_SIZE(skl_primary_formats);
+ }
if (pipe < PIPE_C)
modifiers = skl_format_modifiers_ccs;
else
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 14/15] drm/i915: Add NV12 as supported format for sprite plane
2018-01-04 10:44 [PATCH 00/15] Adding NV12 support Vidya Srinivas
` (12 preceding siblings ...)
2018-01-04 10:44 ` [PATCH 10/15] drm/i915: Set scaler mode for NV12 Vidya Srinivas
@ 2018-01-04 10:44 ` Vidya Srinivas
2018-01-08 12:33 ` Maarten Lankhorst
2018-01-04 10:44 ` [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init Vidya Srinivas
2018-01-04 11:12 ` ✓ Fi.CI.BAT: success for Adding NV12 support (rev4) Patchwork
15 siblings, 1 reply; 26+ messages in thread
From: Vidya Srinivas @ 2018-01-04 10:44 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
From: Chandra Konduru <chandra.konduru@intel.com>
This patch adds NV12 to list of supported formats for sprite plane.
v2: Rebased (me)
v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_formats
- Added the 10bpc RGB formats
v4: Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Removed 10bit RGB formats added previously with NV12 series
v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Previous version has 10bit RGB format removed from VLV formats
by mistake. Fixing that in this version.
Removed 10bit RGB formats added previously with NV12 series
for SKL.
v6: Addressed review comments by Ville
Restricting the NV12 to BXT and PIPE A and B
v7: Rebased (me)
v8: Rebased (me)
Restricting NV12 changes to BXT and KBL
Restricting NV12 changes for plane 0 (overlay)
v9: Rebased (me)
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/intel_sprite.c | 24 +++++++++++++++++++++---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 09732ae..1d35a18 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1279,6 +1279,19 @@ static const struct drm_plane_funcs intel_sprite_plane_funcs = {
.format_mod_supported = intel_sprite_plane_format_mod_supported,
};
+static uint32_t nv12_plane_formats[] = {
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+};
+
struct intel_plane *
intel_sprite_plane_create(struct drm_i915_private *dev_priv,
enum pipe pipe, int plane)
@@ -1323,9 +1336,14 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
intel_plane->update_plane = skl_update_plane;
intel_plane->disable_plane = skl_disable_plane;
intel_plane->get_hw_state = skl_plane_get_hw_state;
-
- plane_formats = skl_plane_formats;
- num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+ if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
+ (pipe == PIPE_A || pipe == PIPE_B) && plane == 0) {
+ plane_formats = nv12_plane_formats;
+ num_plane_formats = ARRAY_SIZE(nv12_plane_formats);
+ } else {
+ plane_formats = skl_plane_formats;
+ num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+ }
modifiers = skl_plane_format_modifiers;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
intel_plane->can_scale = false;
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init
2018-01-04 10:44 [PATCH 00/15] Adding NV12 support Vidya Srinivas
` (13 preceding siblings ...)
2018-01-04 10:44 ` [PATCH 14/15] drm/i915: Add NV12 as supported format for sprite plane Vidya Srinivas
@ 2018-01-04 10:44 ` Vidya Srinivas
2018-01-04 11:12 ` ✓ Fi.CI.BAT: success for Adding NV12 support (rev4) Patchwork
15 siblings, 0 replies; 26+ messages in thread
From: Vidya Srinivas @ 2018-01-04 10:44 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
From: Chandra Konduru <chandra.konduru@intel.com>
This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (Chandra Konduru)
v3: rebased (me)
v4: Review comments by Ville addressed
Added platform check for NV12 in intel_framebuffer_init
Removed offset checks for NV12 case
v5: Addressed review comments by Clinton A Taylor
This NV12 support only correctly works on SKL.
Plane color space conversion is different on GLK and later platforms
causing the colors to display incorrectly.
Ville's plane color space property patch series
in review will fix this issue.
- Restricted the NV12 case in intel_framebuffer_init to
SKL and BXT only.
v6: Rebased (me)
v7: Addressed review comments by Ville
Restricting the NV12 to BXT for now.
v8: Rebased (me)
Restricting the NV12 changes to BXT and KBL for now.
v9: Rebased (me)
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4b92e41..30c6da5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14005,6 +14005,14 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
goto err;
}
break;
+ case DRM_FORMAT_NV12:
+ if (!IS_BROXTON(dev_priv) && !IS_KABYLAKE(dev_priv)) {
+ DRM_DEBUG_KMS("unsupported pixel format: %s\n",
+ drm_get_format_name(mode_cmd->pixel_format,
+ &format_name));
+ goto err;
+ }
+ break;
default:
DRM_DEBUG_KMS("unsupported pixel format: %s\n",
drm_get_format_name(mode_cmd->pixel_format, &format_name));
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* ✓ Fi.CI.BAT: success for Adding NV12 support (rev4)
2018-01-04 10:44 [PATCH 00/15] Adding NV12 support Vidya Srinivas
` (14 preceding siblings ...)
2018-01-04 10:44 ` [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init Vidya Srinivas
@ 2018-01-04 11:12 ` Patchwork
15 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2018-01-04 11:12 UTC (permalink / raw)
To: Vidya Srinivas; +Cc: intel-gfx
== Series Details ==
Series: Adding NV12 support (rev4)
URL : https://patchwork.freedesktop.org/series/28103/
State : success
== Summary ==
Series 28103v4 Adding NV12 support
https://patchwork.freedesktop.org/api/1.0/series/28103/revisions/4/mbox/
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS (fi-kbl-r) fdo#104172 +1
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:434s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:383s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:497s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:276s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:497s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:500s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:485s
fi-elk-e7500 total:224 pass:168 dwarn:10 dfail:0 fail:0 skip:45
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:265s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:523s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:404s
fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:412s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:428s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:470s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:429s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:479s
fi-kbl-7560u total:288 pass:268 dwarn:1 dfail:0 fail:0 skip:19 time:513s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:466s
fi-kbl-r total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:510s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:581s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:455s
fi-skl-6600u total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:520s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:542s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:510s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:495s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:448s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:542s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:412s
Blacklisted hosts:
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:584s
fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:621s
fi-glk-dsi total:146 pass:132 dwarn:0 dfail:0 fail:0 skip:13
5f40895798adb2b511014d4bc7167845b179f8da drm-tip: 2018y-01m-04d-00h-29m-57s UTC integration manifest
0082abb5961f drm/i915: Add NV12 support to intel_framebuffer_init
4780dca7aad1 drm/i915: Add NV12 as supported format for sprite plane
ba5c1a3c01c4 drm/i915: Add NV12 as supported format for primary plane
a773f517ac31 drm/i915: Upscale scaler max scale for NV12
d346d416f4e9 drm/i915: Update format_is_yuv() to include NV12
f67b28c9a864 drm/i915: Set scaler mode for NV12
06931660493f drm/i915/skl: split skl_compute_ddb function
b86faabdbaa5 drm/i915/skl+: nv12 workaround disable WM level 1-7
2b317c27143a drm/i915/skl+: make sure higher latency level has higher wm value
3592b28607f1 drm/i915/skl+: pass skl_wm_level struct to wm compute func
8fb89e8729c5 drm/i915/skl+: NV12 related changes for WM
6203d1bf0e72 drm/i915/skl+: support varification of DDB HW state for NV12
507bd85af33f drm/i915/skl+: add NV12 in skl_format_to_fourcc
2f52e0672785 drm/i915/skl+: refactore WM calculation for NV12
4929c23ea698 drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7606/issues.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 02/15] drm/i915/skl+: refactore WM calculation for NV12
2018-01-04 10:44 ` [PATCH 02/15] drm/i915/skl+: refactore WM calculation for NV12 Vidya Srinivas
@ 2018-01-04 16:19 ` Maarten Lankhorst
0 siblings, 0 replies; 26+ messages in thread
From: Maarten Lankhorst @ 2018-01-04 16:19 UTC (permalink / raw)
To: Vidya Srinivas, intel-gfx
Op 07-01-18 om 10:59 schreef Vidya Srinivas:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> Current code calculates DDB for planar formats in such a way that we
> store DDB of plane-0 in plane 1 & vice-versa.
> In order to make this clean this patch refactors WM/DDB calculation for
> NV12 planar formats.
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 120 +++++++++++++++++++--------------------
> 3 files changed, 62 insertions(+), 61 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 56047f8..962717d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1434,7 +1434,7 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
>
> struct skl_ddb_allocation {
> struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
^Should this be changed to packed/y?
> - struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
> + struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
> };
>
> struct skl_ddb_values {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 9c8aef9..5f5e070 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -513,6 +513,7 @@ struct intel_pipe_wm {
> struct skl_plane_wm {
> struct skl_wm_level wm[8];
> struct skl_wm_level trans_wm;
> + bool is_nv12;
> };
>
> struct skl_pipe_wm {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e2598cf..15edb9a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4004,9 +4004,9 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
> static unsigned int
> skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
> const struct drm_plane_state *pstate,
> - int y)
> + const int plane)
> {
> - struct intel_plane *plane = to_intel_plane(pstate->plane);
> + struct intel_plane *intel_plane = to_intel_plane(pstate->plane);
> struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
> uint32_t data_rate;
> uint32_t width = 0, height = 0;
> @@ -4020,9 +4020,9 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
> fb = pstate->fb;
> format = fb->format->format;
>
> - if (plane->id == PLANE_CURSOR)
> + if (intel_plane->id == PLANE_CURSOR)
> return 0;
> - if (y && format != DRM_FORMAT_NV12)
> + if (plane == 1 && format != DRM_FORMAT_NV12)
> return 0;
>
> /*
> @@ -4033,19 +4033,14 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
> width = drm_rect_width(&intel_pstate->base.src) >> 16;
> height = drm_rect_height(&intel_pstate->base.src) >> 16;
>
> - /* for planar format */
> - if (format == DRM_FORMAT_NV12) {
> - if (y) /* y-plane data rate */
> - data_rate = width * height *
> - fb->format->cpp[0];
> - else /* uv-plane data rate */
> - data_rate = (width / 2) * (height / 2) *
> - fb->format->cpp[1];
> - } else {
> - /* for packed formats */
> - data_rate = width * height * fb->format->cpp[0];
> + /* UV plane does 1/2 pixel sub-sampling */
> + if (plane == 1 && format == DRM_FORMAT_NV12) {
> + width /= 2;
> + height /= 2;
> }
>
> + data_rate = width * height * fb->format->cpp[plane];
> +
> down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
>
> return mul_round_up_u32_fixed16(data_rate, down_scale_amount);
> @@ -4058,8 +4053,8 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
> */
> static unsigned int
> skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
> - unsigned *plane_data_rate,
> - unsigned *plane_y_data_rate)
> + unsigned int *plane_data_rate,
> + unsigned int *uv_plane_data_rate)
> {
> struct drm_crtc_state *cstate = &intel_cstate->base;
> struct drm_atomic_state *state = cstate->state;
> @@ -4075,17 +4070,16 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
> enum plane_id plane_id = to_intel_plane(plane)->id;
> unsigned int rate;
>
> - /* packed/uv */
packed/y?
> rate = skl_plane_relative_data_rate(intel_cstate,
> pstate, 0);
> plane_data_rate[plane_id] = rate;
>
> total_data_rate += rate;
>
> - /* y-plane */
> + /* uv-plane */
> rate = skl_plane_relative_data_rate(intel_cstate,
> pstate, 1);
> - plane_y_data_rate[plane_id] = rate;
> + uv_plane_data_rate[plane_id] = rate;
>
> total_data_rate += rate;
> }
> @@ -4094,8 +4088,7 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
> }
>
> static uint16_t
> -skl_ddb_min_alloc(const struct drm_plane_state *pstate,
> - const int y)
> +skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
> {
> struct drm_framebuffer *fb = pstate->fb;
> struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
> @@ -4106,8 +4099,8 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate,
> if (WARN_ON(!fb))
> return 0;
>
> - /* For packed formats, no y-plane, return 0 */
> - if (y && fb->format->format != DRM_FORMAT_NV12)
> + /* For packed formats, and uv-plane, return 0 */
> + if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
> return 0;
>
> /* For Non Y-tile return 8-blocks */
> @@ -4126,15 +4119,12 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate,
> src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
>
> /* Halve UV plane width and height for NV12 */
> - if (fb->format->format == DRM_FORMAT_NV12 && !y) {
> + if (plane == 1) {
> src_w /= 2;
> src_h /= 2;
> }
>
> - if (fb->format->format == DRM_FORMAT_NV12 && !y)
> - plane_bpp = fb->format->cpp[1];
> - else
> - plane_bpp = fb->format->cpp[0];
> + plane_bpp = fb->format->cpp[plane];
>
> if (drm_rotation_90_or_270(pstate->rotation)) {
> switch (plane_bpp) {
> @@ -4162,7 +4152,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate,
>
> static void
> skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
> - uint16_t *minimum, uint16_t *y_minimum)
> + uint16_t *minimum, uint16_t *uv_minimum)
> {
> const struct drm_plane_state *pstate;
> struct drm_plane *plane;
> @@ -4177,7 +4167,7 @@ skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
> continue;
>
> minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
> - y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
> + uv_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
> }
>
> minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
> @@ -4195,17 +4185,17 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
> uint16_t alloc_size, start;
> uint16_t minimum[I915_MAX_PLANES] = {};
> - uint16_t y_minimum[I915_MAX_PLANES] = {};
> + uint16_t uv_minimum[I915_MAX_PLANES] = {};
> unsigned int total_data_rate;
> enum plane_id plane_id;
> int num_active;
> - unsigned plane_data_rate[I915_MAX_PLANES] = {};
> - unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
> + unsigned int plane_data_rate[I915_MAX_PLANES] = {};
> + unsigned int uv_plane_data_rate[I915_MAX_PLANES] = {};
> uint16_t total_min_blocks = 0;
>
> /* Clear the partitioning for disabled planes. */
> memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
> - memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
> + memset(ddb->uv_plane[pipe], 0, sizeof(ddb->uv_plane[pipe]));
>
> if (WARN_ON(!state))
> return 0;
> @@ -4220,7 +4210,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> if (alloc_size == 0)
> return 0;
>
> - skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
> + skl_ddb_calc_min(cstate, num_active, minimum, uv_minimum);
>
> /*
> * 1. Allocate the mininum required blocks for each active plane
> @@ -4230,7 +4220,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
>
> for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> total_min_blocks += minimum[plane_id];
> - total_min_blocks += y_minimum[plane_id];
> + total_min_blocks += uv_minimum[plane_id];
> }
>
> if (total_min_blocks > alloc_size) {
> @@ -4252,14 +4242,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> */
> total_data_rate = skl_get_total_relative_data_rate(cstate,
> plane_data_rate,
> - plane_y_data_rate);
> + uv_plane_data_rate);
> if (total_data_rate == 0)
> return 0;
>
> start = alloc->start;
> for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> - unsigned int data_rate, y_data_rate;
> - uint16_t plane_blocks, y_plane_blocks = 0;
> + unsigned int data_rate, uv_data_rate;
> + uint16_t plane_blocks, uv_plane_blocks;
>
> if (plane_id == PLANE_CURSOR)
> continue;
> @@ -4283,21 +4273,20 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
>
> start += plane_blocks;
>
> - /*
> - * allocation for y_plane part of planar format:
> - */
> - y_data_rate = plane_y_data_rate[plane_id];
> + /* Allocate DDB for UV plane for planar format/NV12 */
> + uv_data_rate = uv_plane_data_rate[plane_id];
>
> - y_plane_blocks = y_minimum[plane_id];
> - y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
> + uv_plane_blocks = uv_minimum[plane_id];
> + uv_plane_blocks += div_u64((uint64_t)alloc_size * uv_data_rate,
> total_data_rate);
>
> - if (y_data_rate) {
> - ddb->y_plane[pipe][plane_id].start = start;
> - ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks;
> + if (uv_data_rate) {
> + ddb->uv_plane[pipe][plane_id].start = start;
> + ddb->uv_plane[pipe][plane_id].end = start +
> + uv_plane_blocks;
> }
>
> - start += y_plane_blocks;
> + start += uv_plane_blocks;
> }
>
> return 0;
> @@ -4425,8 +4414,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
> wp->width = drm_rect_width(&intel_pstate->base.src) >> 16;
> }
>
> - wp->cpp = (fb->format->format == DRM_FORMAT_NV12) ? fb->format->cpp[1] :
> - fb->format->cpp[0];
> + wp->cpp = fb->format->cpp[0];
> wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
> intel_pstate);
>
> @@ -4618,6 +4606,9 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
> return ret;
> }
>
> + if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
> + wm->is_nv12 = true;
> +
> return 0;
> }
>
> @@ -4788,10 +4779,19 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
> skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
> &wm->trans_wm);
>
> - skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
> - &ddb->plane[pipe][plane_id]);
> - skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
> - &ddb->y_plane[pipe][plane_id]);
> + if (wm->is_nv12) {
> + skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
> + &ddb->uv_plane[pipe][plane_id]);
> + skl_ddb_entry_write(dev_priv,
> + PLANE_NV12_BUF_CFG(pipe, plane_id),
> + &ddb->plane[pipe][plane_id]);
> + } else {
> + skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
> + &ddb->plane[pipe][plane_id]);
> + skl_ddb_entry_write(dev_priv,
> + PLANE_NV12_BUF_CFG(pipe, plane_id),
> + &ddb->uv_plane[pipe][plane_id]);
It's probably better to always write 0 here to avoid confusion. :)
Writing something else here is probably a bad idea..
> + }
> }
>
> static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
> @@ -4906,8 +4906,8 @@ skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
>
> if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
> &new_ddb->plane[pipe][plane_id]) &&
> - skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id],
> - &new_ddb->y_plane[pipe][plane_id]))
> + skl_ddb_entry_equal(&cur_ddb->uv_plane[pipe][plane_id],
> + &new_ddb->uv_plane[pipe][plane_id]))
> continue;
>
> plane_state = drm_atomic_get_plane_state(state, plane);
> @@ -5001,8 +5001,8 @@ skl_copy_wm_for_pipe(struct skl_ddb_values *dst,
> struct skl_ddb_values *src,
> enum pipe pipe)
> {
> - memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
> - sizeof(dst->ddb.y_plane[pipe]));
> + memcpy(dst->ddb.uv_plane[pipe], src->ddb.uv_plane[pipe],
> + sizeof(dst->ddb.uv_plane[pipe]));
> memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
> sizeof(dst->ddb.plane[pipe]));
> }
With that fixed for this and patch 1:
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 04/15] drm/i915/skl+: support varification of DDB HW state for NV12
2018-01-04 10:44 ` [PATCH 04/15] drm/i915/skl+: support varification of DDB HW state for NV12 Vidya Srinivas
@ 2018-01-05 12:16 ` Maarten Lankhorst
0 siblings, 0 replies; 26+ messages in thread
From: Maarten Lankhorst @ 2018-01-05 12:16 UTC (permalink / raw)
To: Vidya Srinivas, intel-gfx
In subject: s/varification/verification/
Op 07-01-18 om 10:59 schreef Vidya Srinivas:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> NV12 formats have two registers for DDB. verify both the registers for
> NV12 during verify_wm_state.
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 50 ++++++++++++++++++++++++++++--------
> 3 files changed, 42 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 81aa5f1..af3144d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2607,7 +2607,7 @@ static int i9xx_format_to_fourcc(int format)
> }
> }
>
> -static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> +int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> {
> switch (format) {
> case PLANE_CTL_FORMAT_RGB_565:
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 5f5e070..d245481 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1510,6 +1510,7 @@ u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
> unsigned int rotation);
> int skl_check_plane_surface(struct intel_plane_state *plane_state);
> int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
> +int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
>
> /* intel_csr.c */
> void intel_csr_ucode_init(struct drm_i915_private *);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 15edb9a..5c268b9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3820,6 +3820,43 @@ static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
> entry->end += 1;
> }
>
> +static void
> +skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
> + const enum pipe pipe,
> + const enum plane_id plane_id,
> + struct skl_ddb_allocation *ddb /* out */)
> +{
> + u32 val, val2 = 0;
> + int fourcc, pixel_format;
> +
> + /* Cursor doesn't support NV12, so no extra calculation needed */
> + if (plane_id == PLANE_CURSOR) {
> + val = I915_READ(CUR_BUF_CFG(pipe));
> + skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
> + return;
> + }
> +
> + val = I915_READ(PLANE_CTL(pipe, plane_id));
> +
> + /* No DDB allocated for disabled planes */
> + if (!(val & PLANE_CTL_ENABLE))
> + return;
> +
> + pixel_format = val & PLANE_CTL_FORMAT_MASK;
> + fourcc = skl_format_to_fourcc(pixel_format,
> + val & PLANE_CTL_ORDER_RGBX,
> + val & PLANE_CTL_ALPHA_MASK);
> +
> + val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
> + val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
> +
> + if (fourcc == DRM_FORMAT_NV12) {
> + skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val2);
> + skl_ddb_entry_init_from_hw(&ddb->uv_plane[pipe][plane_id], val);
> + } else
> + skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
> +}
> +
> void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
> struct skl_ddb_allocation *ddb /* out */)
> {
> @@ -3836,16 +3873,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
> if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
> continue;
>
> - for_each_plane_id_on_crtc(crtc, plane_id) {
> - u32 val;
> -
> - if (plane_id != PLANE_CURSOR)
> - val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
> - else
> - val = I915_READ(CUR_BUF_CFG(pipe));
> -
> - skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
> - }
> + for_each_plane_id_on_crtc(crtc, plane_id)
> + skl_ddb_get_hw_plane_state(dev_priv, pipe,
> + plane_id, ddb);
>
> intel_display_power_put(dev_priv, power_domain);
> }
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^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 08/15] drm/i915/skl+: nv12 workaround disable WM level 1-7
2018-01-04 10:44 ` [PATCH 08/15] drm/i915/skl+: nv12 workaround disable WM level 1-7 Vidya Srinivas
@ 2018-01-08 12:07 ` Maarten Lankhorst
0 siblings, 0 replies; 26+ messages in thread
From: Maarten Lankhorst @ 2018-01-08 12:07 UTC (permalink / raw)
To: Vidya Srinivas, intel-gfx
Op 07-01-18 om 10:59 schreef Vidya Srinivas:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A)
> Hardware sometimes fails to wake memory from pkg C states fetching the
> last few lines of planar YUV 420 (NV12) planes. This causes
> intermittent underflow and corruption.
> WA: Disable package C states or do not enable latency levels 1 through 7
> (WM1 - WM7) on NV12 planes.
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d75fd3b..90aa216 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4610,6 +4610,17 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> }
> }
>
> + /*
> + * Display WA #826 (SKL:ALL, BXT:ALL) & #1059 (CNL:A)
> + * disable wm level 1-7 on NV12 planes
> + */
> + if (wp->is_nv12 && level && (IS_SKYLAKE(dev_priv) ||
For clarity, might be better to do explicitly level >= 1 here, and move IS_SKYLAKE to a newline for better indent. :)
Otherwise looks good, so with that fixed you can add my r-b..
> + IS_BROXTON(dev_priv) ||
> + IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {
> + result->plane_en = false;
> + return 0;
> + }
> +
> result->plane_res_b = res_blocks;
> result->plane_res_l = res_lines;
> result->plane_en = true;
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^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 13/15] drm/i915: Add NV12 as supported format for primary plane
2018-01-04 10:44 ` [PATCH 13/15] drm/i915: Add NV12 as supported format for primary plane Vidya Srinivas
@ 2018-01-08 12:31 ` Maarten Lankhorst
0 siblings, 0 replies; 26+ messages in thread
From: Maarten Lankhorst @ 2018-01-08 12:31 UTC (permalink / raw)
To: Vidya Srinivas, intel-gfx
Op 07-01-18 om 10:59 schreef Vidya Srinivas:
> From: Chandra Konduru <chandra.konduru@intel.com>
>
> This patch adds NV12 to list of supported formats for
> primary plane
>
> v2: Rebased (Chandra Konduru)
>
> v3: Rebased (me)
>
> v4: Review comments by Ville addressed
> Removed the skl_primary_formats_with_nv12 and
> added NV12 case in existing skl_primary_formats
>
> v5: Rebased (me)
>
> v6: Missed the Tested-by/Reviewed-by in the previous series
> Adding the same to commit message in this version.
>
> v7: Review comments by Ville addressed
> Restricting the NV12 for BXT and on PIPE A and B
> Rebased (me)
>
> v8: Rebased (me)
> Modified restricting the NV12 support for both BXT and KBL.
>
> v9: Rebased (me)
>
> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 26 ++++++++++++++++++++++++--
> 1 file changed, 24 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d05890b..4b92e41 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -106,6 +106,22 @@ static const uint64_t skl_format_modifiers_ccs[] = {
> DRM_FORMAT_MOD_INVALID
> };
>
> +static const uint32_t nv12_primary_formats[] = {
> + DRM_FORMAT_C8,
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_ABGR8888,
> + DRM_FORMAT_XRGB2101010,
> + DRM_FORMAT_XBGR2101010,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_YVYU,
> + DRM_FORMAT_UYVY,
> + DRM_FORMAT_VYUY,
> + DRM_FORMAT_NV12,
> +};
> +
> /* Cursor formats */
> static const uint32_t intel_cursor_formats[] = {
> DRM_FORMAT_ARGB8888,
> @@ -13180,8 +13196,14 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> primary->disable_plane = skl_disable_plane;
> primary->get_hw_state = skl_plane_get_hw_state;
> } else if (INTEL_GEN(dev_priv) >= 9) {
> - intel_primary_formats = skl_primary_formats;
> - num_formats = ARRAY_SIZE(skl_primary_formats);
> + if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> + ((pipe == PIPE_A || pipe == PIPE_B))) {
> + intel_primary_formats = nv12_primary_formats;
> + num_formats = ARRAY_SIZE(nv12_primary_formats);
> + } else {
> + intel_primary_formats = skl_primary_formats;
> + num_formats = ARRAY_SIZE(skl_primary_formats);
> + }
Both format arrays are nearly the same and could probably end up being a source of bugs, could DRM_FORMAT_NV12 be added to skl_primary_formats, with a comment it should be the last member, and decrease num_formats by 1 if NV12 is not supported? And what about gen10+, shouldn't that also have nv12 support?
~Maarten
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^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 14/15] drm/i915: Add NV12 as supported format for sprite plane
2018-01-04 10:44 ` [PATCH 14/15] drm/i915: Add NV12 as supported format for sprite plane Vidya Srinivas
@ 2018-01-08 12:33 ` Maarten Lankhorst
2018-01-09 2:19 ` Srinivas, Vidya
0 siblings, 1 reply; 26+ messages in thread
From: Maarten Lankhorst @ 2018-01-08 12:33 UTC (permalink / raw)
To: Vidya Srinivas, intel-gfx
Op 07-01-18 om 10:59 schreef Vidya Srinivas:
> From: Chandra Konduru <chandra.konduru@intel.com>
>
> This patch adds NV12 to list of supported formats for sprite plane.
>
> v2: Rebased (me)
>
> v3: Review comments by Ville addressed
> - Removed skl_plane_formats_with_nv12 and added
> NV12 case in existing skl_plane_formats
> - Added the 10bpc RGB formats
>
> v4: Addressed review comments from Clinton A Taylor
> "Why are we adding 10 bit RGB formats with the NV12 series patches?
> Trying to set XR30 or AB30 results in error returned even though
> the modes are advertised for the planes"
> - Removed 10bit RGB formats added previously with NV12 series
>
> v5: Missed the Tested-by/Reviewed-by in the previous series
> Adding the same to commit message in this version.
> Addressed review comments from Clinton A Taylor
> "Why are we adding 10 bit RGB formats with the NV12 series patches?
> Trying to set XR30 or AB30 results in error returned even though
> the modes are advertised for the planes"
> - Previous version has 10bit RGB format removed from VLV formats
> by mistake. Fixing that in this version.
> Removed 10bit RGB formats added previously with NV12 series
> for SKL.
>
> v6: Addressed review comments by Ville
> Restricting the NV12 to BXT and PIPE A and B
>
> v7: Rebased (me)
>
> v8: Rebased (me)
> Restricting NV12 changes to BXT and KBL
> Restricting NV12 changes for plane 0 (overlay)
>
> v9: Rebased (me)
>
> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
> drivers/gpu/drm/i915/intel_sprite.c | 24 +++++++++++++++++++++---
> 1 file changed, 21 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 09732ae..1d35a18 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1279,6 +1279,19 @@ static const struct drm_plane_funcs intel_sprite_plane_funcs = {
> .format_mod_supported = intel_sprite_plane_format_mod_supported,
> };
>
> +static uint32_t nv12_plane_formats[] = {
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_ABGR8888,
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_YVYU,
> + DRM_FORMAT_UYVY,
> + DRM_FORMAT_VYUY,
> + DRM_FORMAT_NV12,
> +};
> +
> struct intel_plane *
> intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> enum pipe pipe, int plane)
> @@ -1323,9 +1336,14 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> intel_plane->update_plane = skl_update_plane;
> intel_plane->disable_plane = skl_disable_plane;
> intel_plane->get_hw_state = skl_plane_get_hw_state;
> -
> - plane_formats = skl_plane_formats;
> - num_plane_formats = ARRAY_SIZE(skl_plane_formats);
> + if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> + (pipe == PIPE_A || pipe == PIPE_B) && plane == 0) {
> + plane_formats = nv12_plane_formats;
> + num_plane_formats = ARRAY_SIZE(nv12_plane_formats);
> + } else {
> + plane_formats = skl_plane_formats;
> + num_plane_formats = ARRAY_SIZE(skl_plane_formats);
> + }
I understand we don't have enough scalers, but is there something wrong with allowing nv12 on any plane?
~Maarten
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 14/15] drm/i915: Add NV12 as supported format for sprite plane
2018-01-08 12:33 ` Maarten Lankhorst
@ 2018-01-09 2:19 ` Srinivas, Vidya
2018-01-09 10:02 ` Maarten Lankhorst
0 siblings, 1 reply; 26+ messages in thread
From: Srinivas, Vidya @ 2018-01-09 2:19 UTC (permalink / raw)
To: Maarten Lankhorst, intel-gfx
> -----Original Message-----
> From: Maarten Lankhorst [mailto:maarten.lankhorst@linux.intel.com]
> Sent: Monday, January 8, 2018 6:04 PM
> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 14/15] drm/i915: Add NV12 as supported
> format for sprite plane
>
> Op 07-01-18 om 10:59 schreef Vidya Srinivas:
> > From: Chandra Konduru <chandra.konduru@intel.com>
> >
> > This patch adds NV12 to list of supported formats for sprite plane.
> >
> > v2: Rebased (me)
> >
> > v3: Review comments by Ville addressed
> > - Removed skl_plane_formats_with_nv12 and added
> > NV12 case in existing skl_plane_formats
> > - Added the 10bpc RGB formats
> >
> > v4: Addressed review comments from Clinton A Taylor "Why are we
> adding
> > 10 bit RGB formats with the NV12 series patches?
> > Trying to set XR30 or AB30 results in error returned even though the
> > modes are advertised for the planes"
> > - Removed 10bit RGB formats added previously with NV12 series
> >
> > v5: Missed the Tested-by/Reviewed-by in the previous series Adding the
> > same to commit message in this version.
> > Addressed review comments from Clinton A Taylor "Why are we adding 10
> > bit RGB formats with the NV12 series patches?
> > Trying to set XR30 or AB30 results in error returned even though the
> > modes are advertised for the planes"
> > - Previous version has 10bit RGB format removed from VLV formats by
> > mistake. Fixing that in this version.
> > Removed 10bit RGB formats added previously with NV12 series for SKL.
> >
> > v6: Addressed review comments by Ville Restricting the NV12 to BXT and
> > PIPE A and B
> >
> > v7: Rebased (me)
> >
> > v8: Rebased (me)
> > Restricting NV12 changes to BXT and KBL Restricting NV12 changes for
> > plane 0 (overlay)
> >
> > v9: Rebased (me)
> >
> > Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> > Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> > Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> > Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> > Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_sprite.c | 24 +++++++++++++++++++++---
> > 1 file changed, 21 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > b/drivers/gpu/drm/i915/intel_sprite.c
> > index 09732ae..1d35a18 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -1279,6 +1279,19 @@ static const struct drm_plane_funcs
> intel_sprite_plane_funcs = {
> > .format_mod_supported =
> > intel_sprite_plane_format_mod_supported,
> > };
> >
> > +static uint32_t nv12_plane_formats[] = {
> > + DRM_FORMAT_RGB565,
> > + DRM_FORMAT_ABGR8888,
> > + DRM_FORMAT_ARGB8888,
> > + DRM_FORMAT_XBGR8888,
> > + DRM_FORMAT_XRGB8888,
> > + DRM_FORMAT_YUYV,
> > + DRM_FORMAT_YVYU,
> > + DRM_FORMAT_UYVY,
> > + DRM_FORMAT_VYUY,
> > + DRM_FORMAT_NV12,
> > +};
> > +
> > struct intel_plane *
> > intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> > enum pipe pipe, int plane)
> > @@ -1323,9 +1336,14 @@ intel_sprite_plane_create(struct
> drm_i915_private *dev_priv,
> > intel_plane->update_plane = skl_update_plane;
> > intel_plane->disable_plane = skl_disable_plane;
> > intel_plane->get_hw_state = skl_plane_get_hw_state;
> > -
> > - plane_formats = skl_plane_formats;
> > - num_plane_formats = ARRAY_SIZE(skl_plane_formats);
> > + if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> > + (pipe == PIPE_A || pipe == PIPE_B) && plane == 0) {
> > + plane_formats = nv12_plane_formats;
> > + num_plane_formats =
> ARRAY_SIZE(nv12_plane_formats);
> > + } else {
> > + plane_formats = skl_plane_formats;
> > + num_plane_formats =
> ARRAY_SIZE(skl_plane_formats);
> > + }
> I understand we don't have enough scalers, but is there something wrong
> with allowing nv12 on any plane?
>
On BXT (Gen9), NV12 is supported only on primary and sprite 0.
Regards
Vidya
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 14/15] drm/i915: Add NV12 as supported format for sprite plane
2018-01-09 2:19 ` Srinivas, Vidya
@ 2018-01-09 10:02 ` Maarten Lankhorst
2018-01-09 10:06 ` Srinivas, Vidya
2018-01-11 9:57 ` Srinivas, Vidya
0 siblings, 2 replies; 26+ messages in thread
From: Maarten Lankhorst @ 2018-01-09 10:02 UTC (permalink / raw)
To: Srinivas, Vidya, intel-gfx
Op 09-01-18 om 03:19 schreef Srinivas, Vidya:
>
>> -----Original Message-----
>> From: Maarten Lankhorst [mailto:maarten.lankhorst@linux.intel.com]
>> Sent: Monday, January 8, 2018 6:04 PM
>> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
>> gfx@lists.freedesktop.org
>> Subject: Re: [Intel-gfx] [PATCH 14/15] drm/i915: Add NV12 as supported
>> format for sprite plane
>>
>> Op 07-01-18 om 10:59 schreef Vidya Srinivas:
>>> From: Chandra Konduru <chandra.konduru@intel.com>
>>>
>>> This patch adds NV12 to list of supported formats for sprite plane.
>>>
>>> v2: Rebased (me)
>>>
>>> v3: Review comments by Ville addressed
>>> - Removed skl_plane_formats_with_nv12 and added
>>> NV12 case in existing skl_plane_formats
>>> - Added the 10bpc RGB formats
>>>
>>> v4: Addressed review comments from Clinton A Taylor "Why are we
>> adding
>>> 10 bit RGB formats with the NV12 series patches?
>>> Trying to set XR30 or AB30 results in error returned even though the
>>> modes are advertised for the planes"
>>> - Removed 10bit RGB formats added previously with NV12 series
>>>
>>> v5: Missed the Tested-by/Reviewed-by in the previous series Adding the
>>> same to commit message in this version.
>>> Addressed review comments from Clinton A Taylor "Why are we adding 10
>>> bit RGB formats with the NV12 series patches?
>>> Trying to set XR30 or AB30 results in error returned even though the
>>> modes are advertised for the planes"
>>> - Previous version has 10bit RGB format removed from VLV formats by
>>> mistake. Fixing that in this version.
>>> Removed 10bit RGB formats added previously with NV12 series for SKL.
>>>
>>> v6: Addressed review comments by Ville Restricting the NV12 to BXT and
>>> PIPE A and B
>>>
>>> v7: Rebased (me)
>>>
>>> v8: Rebased (me)
>>> Restricting NV12 changes to BXT and KBL Restricting NV12 changes for
>>> plane 0 (overlay)
>>>
>>> v9: Rebased (me)
>>>
>>> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
>>> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
>>> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
>>> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
>>> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/intel_sprite.c | 24 +++++++++++++++++++++---
>>> 1 file changed, 21 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
>>> b/drivers/gpu/drm/i915/intel_sprite.c
>>> index 09732ae..1d35a18 100644
>>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>>> @@ -1279,6 +1279,19 @@ static const struct drm_plane_funcs
>> intel_sprite_plane_funcs = {
>>> .format_mod_supported =
>>> intel_sprite_plane_format_mod_supported,
>>> };
>>>
>>> +static uint32_t nv12_plane_formats[] = {
>>> + DRM_FORMAT_RGB565,
>>> + DRM_FORMAT_ABGR8888,
>>> + DRM_FORMAT_ARGB8888,
>>> + DRM_FORMAT_XBGR8888,
>>> + DRM_FORMAT_XRGB8888,
>>> + DRM_FORMAT_YUYV,
>>> + DRM_FORMAT_YVYU,
>>> + DRM_FORMAT_UYVY,
>>> + DRM_FORMAT_VYUY,
>>> + DRM_FORMAT_NV12,
>>> +};
>>> +
>>> struct intel_plane *
>>> intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>>> enum pipe pipe, int plane)
>>> @@ -1323,9 +1336,14 @@ intel_sprite_plane_create(struct
>> drm_i915_private *dev_priv,
>>> intel_plane->update_plane = skl_update_plane;
>>> intel_plane->disable_plane = skl_disable_plane;
>>> intel_plane->get_hw_state = skl_plane_get_hw_state;
>>> -
>>> - plane_formats = skl_plane_formats;
>>> - num_plane_formats = ARRAY_SIZE(skl_plane_formats);
>>> + if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
>>> + (pipe == PIPE_A || pipe == PIPE_B) && plane == 0) {
>>> + plane_formats = nv12_plane_formats;
>>> + num_plane_formats =
>> ARRAY_SIZE(nv12_plane_formats);
>>> + } else {
>>> + plane_formats = skl_plane_formats;
>>> + num_plane_formats =
>> ARRAY_SIZE(skl_plane_formats);
>>> + }
>> I understand we don't have enough scalers, but is there something wrong
>> with allowing nv12 on any plane?
>>
> On BXT (Gen9), NV12 is supported only on primary and sprite 0.
Ah ok, nm that comment then. :)
Same comment applies as for the other patch that adds it to the primary plane, would be better to have a single array and tinker with num_plane_formats, should gen10 also have NV12 support here btw?
I can't r-b the series right now, there are no tests. Judging from the comments this is what the kms_plane_scaling is about, so I started looking at it.
~Maarten
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 14/15] drm/i915: Add NV12 as supported format for sprite plane
2018-01-09 10:02 ` Maarten Lankhorst
@ 2018-01-09 10:06 ` Srinivas, Vidya
2018-01-11 9:57 ` Srinivas, Vidya
1 sibling, 0 replies; 26+ messages in thread
From: Srinivas, Vidya @ 2018-01-09 10:06 UTC (permalink / raw)
To: Maarten Lankhorst, intel-gfx
> -----Original Message-----
> From: Maarten Lankhorst [mailto:maarten.lankhorst@linux.intel.com]
> Sent: Tuesday, January 9, 2018 3:32 PM
> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 14/15] drm/i915: Add NV12 as supported
> format for sprite plane
>
> Op 09-01-18 om 03:19 schreef Srinivas, Vidya:
> >
> >> -----Original Message-----
> >> From: Maarten Lankhorst [mailto:maarten.lankhorst@linux.intel.com]
> >> Sent: Monday, January 8, 2018 6:04 PM
> >> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> >> gfx@lists.freedesktop.org
> >> Subject: Re: [Intel-gfx] [PATCH 14/15] drm/i915: Add NV12 as
> >> supported format for sprite plane
> >>
> >> Op 07-01-18 om 10:59 schreef Vidya Srinivas:
> >>> From: Chandra Konduru <chandra.konduru@intel.com>
> >>>
> >>> This patch adds NV12 to list of supported formats for sprite plane.
> >>>
> >>> v2: Rebased (me)
> >>>
> >>> v3: Review comments by Ville addressed
> >>> - Removed skl_plane_formats_with_nv12 and added
> >>> NV12 case in existing skl_plane_formats
> >>> - Added the 10bpc RGB formats
> >>>
> >>> v4: Addressed review comments from Clinton A Taylor "Why are we
> >> adding
> >>> 10 bit RGB formats with the NV12 series patches?
> >>> Trying to set XR30 or AB30 results in error returned even though the
> >>> modes are advertised for the planes"
> >>> - Removed 10bit RGB formats added previously with NV12 series
> >>>
> >>> v5: Missed the Tested-by/Reviewed-by in the previous series Adding
> >>> the same to commit message in this version.
> >>> Addressed review comments from Clinton A Taylor "Why are we adding
> >>> 10 bit RGB formats with the NV12 series patches?
> >>> Trying to set XR30 or AB30 results in error returned even though the
> >>> modes are advertised for the planes"
> >>> - Previous version has 10bit RGB format removed from VLV formats by
> >>> mistake. Fixing that in this version.
> >>> Removed 10bit RGB formats added previously with NV12 series for SKL.
> >>>
> >>> v6: Addressed review comments by Ville Restricting the NV12 to BXT
> >>> and PIPE A and B
> >>>
> >>> v7: Rebased (me)
> >>>
> >>> v8: Rebased (me)
> >>> Restricting NV12 changes to BXT and KBL Restricting NV12 changes for
> >>> plane 0 (overlay)
> >>>
> >>> v9: Rebased (me)
> >>>
> >>> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> >>> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> >>> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> >>> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> >>> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> >>> ---
> >>> drivers/gpu/drm/i915/intel_sprite.c | 24 +++++++++++++++++++++---
> >>> 1 file changed, 21 insertions(+), 3 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> >>> b/drivers/gpu/drm/i915/intel_sprite.c
> >>> index 09732ae..1d35a18 100644
> >>> --- a/drivers/gpu/drm/i915/intel_sprite.c
> >>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> >>> @@ -1279,6 +1279,19 @@ static const struct drm_plane_funcs
> >> intel_sprite_plane_funcs = {
> >>> .format_mod_supported =
> >>> intel_sprite_plane_format_mod_supported,
> >>> };
> >>>
> >>> +static uint32_t nv12_plane_formats[] = {
> >>> + DRM_FORMAT_RGB565,
> >>> + DRM_FORMAT_ABGR8888,
> >>> + DRM_FORMAT_ARGB8888,
> >>> + DRM_FORMAT_XBGR8888,
> >>> + DRM_FORMAT_XRGB8888,
> >>> + DRM_FORMAT_YUYV,
> >>> + DRM_FORMAT_YVYU,
> >>> + DRM_FORMAT_UYVY,
> >>> + DRM_FORMAT_VYUY,
> >>> + DRM_FORMAT_NV12,
> >>> +};
> >>> +
> >>> struct intel_plane *
> >>> intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> >>> enum pipe pipe, int plane)
> >>> @@ -1323,9 +1336,14 @@ intel_sprite_plane_create(struct
> >> drm_i915_private *dev_priv,
> >>> intel_plane->update_plane = skl_update_plane;
> >>> intel_plane->disable_plane = skl_disable_plane;
> >>> intel_plane->get_hw_state = skl_plane_get_hw_state;
> >>> -
> >>> - plane_formats = skl_plane_formats;
> >>> - num_plane_formats = ARRAY_SIZE(skl_plane_formats);
> >>> + if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> >>> + (pipe == PIPE_A || pipe == PIPE_B) && plane == 0) {
> >>> + plane_formats = nv12_plane_formats;
> >>> + num_plane_formats =
> >> ARRAY_SIZE(nv12_plane_formats);
> >>> + } else {
> >>> + plane_formats = skl_plane_formats;
> >>> + num_plane_formats =
> >> ARRAY_SIZE(skl_plane_formats);
> >>> + }
> >> I understand we don't have enough scalers, but is there something
> >> wrong with allowing nv12 on any plane?
> >>
> > On BXT (Gen9), NV12 is supported only on primary and sprite 0.
> Ah ok, nm that comment then. :)
>
> Same comment applies as for the other patch that adds it to the primary
> plane, would be better to have a single array and tinker with
> num_plane_formats, should gen10 also have NV12 support here btw?
>
> I can't r-b the series right now, there are no tests. Judging from the
> comments this is what the kms_plane_scaling is about, so I started looking
> at it.
>
Thank you. We need to add NV12 support for Gen10 also but for now
we are trying to get the base framework in. We have tested it on
APL board for now.Just for reference,
in case you need you can see this igt which was floated to cover
nv12 testing.
https://patchwork.kernel.org/patch/9995943/
https://patchwork.kernel.org/patch/9995945/
Regards
Vidya
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 14/15] drm/i915: Add NV12 as supported format for sprite plane
2018-01-09 10:02 ` Maarten Lankhorst
2018-01-09 10:06 ` Srinivas, Vidya
@ 2018-01-11 9:57 ` Srinivas, Vidya
1 sibling, 0 replies; 26+ messages in thread
From: Srinivas, Vidya @ 2018-01-11 9:57 UTC (permalink / raw)
To: Maarten Lankhorst, intel-gfx
> -----Original Message-----
> From: Maarten Lankhorst [mailto:maarten.lankhorst@linux.intel.com]
> Sent: Tuesday, January 9, 2018 3:32 PM
> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 14/15] drm/i915: Add NV12 as supported
> format for sprite plane
>
> Op 09-01-18 om 03:19 schreef Srinivas, Vidya:
> >
> >> -----Original Message-----
> >> From: Maarten Lankhorst [mailto:maarten.lankhorst@linux.intel.com]
> >> Sent: Monday, January 8, 2018 6:04 PM
> >> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> >> gfx@lists.freedesktop.org
> >> Subject: Re: [Intel-gfx] [PATCH 14/15] drm/i915: Add NV12 as
> >> supported format for sprite plane
> >>
> >> Op 07-01-18 om 10:59 schreef Vidya Srinivas:
> >>> From: Chandra Konduru <chandra.konduru@intel.com>
> >>>
> >>> This patch adds NV12 to list of supported formats for sprite plane.
> >>>
> >>> v2: Rebased (me)
> >>>
> >>> v3: Review comments by Ville addressed
> >>> - Removed skl_plane_formats_with_nv12 and added
> >>> NV12 case in existing skl_plane_formats
> >>> - Added the 10bpc RGB formats
> >>>
> >>> v4: Addressed review comments from Clinton A Taylor "Why are we
> >> adding
> >>> 10 bit RGB formats with the NV12 series patches?
> >>> Trying to set XR30 or AB30 results in error returned even though the
> >>> modes are advertised for the planes"
> >>> - Removed 10bit RGB formats added previously with NV12 series
> >>>
> >>> v5: Missed the Tested-by/Reviewed-by in the previous series Adding
> >>> the same to commit message in this version.
> >>> Addressed review comments from Clinton A Taylor "Why are we adding
> >>> 10 bit RGB formats with the NV12 series patches?
> >>> Trying to set XR30 or AB30 results in error returned even though the
> >>> modes are advertised for the planes"
> >>> - Previous version has 10bit RGB format removed from VLV formats by
> >>> mistake. Fixing that in this version.
> >>> Removed 10bit RGB formats added previously with NV12 series for SKL.
> >>>
> >>> v6: Addressed review comments by Ville Restricting the NV12 to BXT
> >>> and PIPE A and B
> >>>
> >>> v7: Rebased (me)
> >>>
> >>> v8: Rebased (me)
> >>> Restricting NV12 changes to BXT and KBL Restricting NV12 changes for
> >>> plane 0 (overlay)
> >>>
> >>> v9: Rebased (me)
> >>>
> >>> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> >>> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> >>> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> >>> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> >>> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> >>> ---
> >>> drivers/gpu/drm/i915/intel_sprite.c | 24 +++++++++++++++++++++---
> >>> 1 file changed, 21 insertions(+), 3 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> >>> b/drivers/gpu/drm/i915/intel_sprite.c
> >>> index 09732ae..1d35a18 100644
> >>> --- a/drivers/gpu/drm/i915/intel_sprite.c
> >>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> >>> @@ -1279,6 +1279,19 @@ static const struct drm_plane_funcs
> >> intel_sprite_plane_funcs = {
> >>> .format_mod_supported =
> >>> intel_sprite_plane_format_mod_supported,
> >>> };
> >>>
> >>> +static uint32_t nv12_plane_formats[] = {
> >>> + DRM_FORMAT_RGB565,
> >>> + DRM_FORMAT_ABGR8888,
> >>> + DRM_FORMAT_ARGB8888,
> >>> + DRM_FORMAT_XBGR8888,
> >>> + DRM_FORMAT_XRGB8888,
> >>> + DRM_FORMAT_YUYV,
> >>> + DRM_FORMAT_YVYU,
> >>> + DRM_FORMAT_UYVY,
> >>> + DRM_FORMAT_VYUY,
> >>> + DRM_FORMAT_NV12,
> >>> +};
> >>> +
> >>> struct intel_plane *
> >>> intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> >>> enum pipe pipe, int plane)
> >>> @@ -1323,9 +1336,14 @@ intel_sprite_plane_create(struct
> >> drm_i915_private *dev_priv,
> >>> intel_plane->update_plane = skl_update_plane;
> >>> intel_plane->disable_plane = skl_disable_plane;
> >>> intel_plane->get_hw_state = skl_plane_get_hw_state;
> >>> -
> >>> - plane_formats = skl_plane_formats;
> >>> - num_plane_formats = ARRAY_SIZE(skl_plane_formats);
> >>> + if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> >>> + (pipe == PIPE_A || pipe == PIPE_B) && plane == 0) {
> >>> + plane_formats = nv12_plane_formats;
> >>> + num_plane_formats =
> >> ARRAY_SIZE(nv12_plane_formats);
> >>> + } else {
> >>> + plane_formats = skl_plane_formats;
> >>> + num_plane_formats =
> >> ARRAY_SIZE(skl_plane_formats);
> >>> + }
> >> I understand we don't have enough scalers, but is there something
> >> wrong with allowing nv12 on any plane?
> >>
> > On BXT (Gen9), NV12 is supported only on primary and sprite 0.
> Ah ok, nm that comment then. :)
>
> Same comment applies as for the other patch that adds it to the primary
> plane, would be better to have a single array and tinker with
> num_plane_formats, should gen10 also have NV12 support here btw?
>
> I can't r-b the series right now, there are no tests. Judging from the
> comments this is what the kms_plane_scaling is about, so I started looking
> at it.
>
Thank you. I could add support for Gen10 also. Only difference in plane capability will be,
NV12 is supported on sprite 0 even on Pipe C. Will try keeping the single array.
Had tried it once, but ran into some issue which I can't recollect :(
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^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2018-01-11 9:57 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-01-04 10:44 [PATCH 00/15] Adding NV12 support Vidya Srinivas
2018-01-04 10:44 ` [PATCH 01/15] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values Vidya Srinivas
2018-01-04 10:44 ` [PATCH 02/15] drm/i915/skl+: refactore WM calculation for NV12 Vidya Srinivas
2018-01-04 16:19 ` Maarten Lankhorst
2018-01-04 10:44 ` [PATCH 03/15] drm/i915/skl+: add NV12 in skl_format_to_fourcc Vidya Srinivas
2018-01-04 10:44 ` [PATCH 06/15] drm/i915/skl+: pass skl_wm_level struct to wm compute func Vidya Srinivas
2018-01-04 10:44 ` [PATCH 05/15] drm/i915/skl+: NV12 related changes for WM Vidya Srinivas
2018-01-04 10:44 ` [PATCH 04/15] drm/i915/skl+: support varification of DDB HW state for NV12 Vidya Srinivas
2018-01-05 12:16 ` Maarten Lankhorst
2018-01-04 10:44 ` [PATCH 07/15] drm/i915/skl+: make sure higher latency level has higher wm value Vidya Srinivas
2018-01-04 10:44 ` [PATCH 11/15] drm/i915: Update format_is_yuv() to include NV12 Vidya Srinivas
2018-01-04 10:44 ` [PATCH 09/15] drm/i915/skl: split skl_compute_ddb function Vidya Srinivas
2018-01-04 10:44 ` [PATCH 08/15] drm/i915/skl+: nv12 workaround disable WM level 1-7 Vidya Srinivas
2018-01-08 12:07 ` Maarten Lankhorst
2018-01-04 10:44 ` [PATCH 12/15] drm/i915: Upscale scaler max scale for NV12 Vidya Srinivas
2018-01-04 10:44 ` [PATCH 13/15] drm/i915: Add NV12 as supported format for primary plane Vidya Srinivas
2018-01-08 12:31 ` Maarten Lankhorst
2018-01-04 10:44 ` [PATCH 10/15] drm/i915: Set scaler mode for NV12 Vidya Srinivas
2018-01-04 10:44 ` [PATCH 14/15] drm/i915: Add NV12 as supported format for sprite plane Vidya Srinivas
2018-01-08 12:33 ` Maarten Lankhorst
2018-01-09 2:19 ` Srinivas, Vidya
2018-01-09 10:02 ` Maarten Lankhorst
2018-01-09 10:06 ` Srinivas, Vidya
2018-01-11 9:57 ` Srinivas, Vidya
2018-01-04 10:44 ` [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init Vidya Srinivas
2018-01-04 11:12 ` ✓ Fi.CI.BAT: success for Adding NV12 support (rev4) Patchwork
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