* [PATCH] drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too
@ 2017-11-14 13:05 Valtteri Rantala
2017-11-14 13:18 ` ✗ Fi.CI.BAT: failure for " Patchwork
2017-11-15 17:52 ` [PATCH] " David Weinehall
0 siblings, 2 replies; 5+ messages in thread
From: Valtteri Rantala @ 2017-11-14 13:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Altug Koker
Testing the texture read performance shows that the same tuning for the
SQ credits is needed on GLK as on BXT/APL. This has been also confirmed
by Altug from the HW team.
Cc: Altug Koker <altug.koker@intel.com>
Signed-off-by: Valtteri Rantala <valtteri.rantala@intel.com>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 70bbe8e..11fc0bd 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1093,6 +1093,15 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
+ /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
+ if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER) ||
+ IS_GEMINILAKE(dev_priv)) {
+ u32 val = I915_READ(GEN8_L3SQCREG1);
+ val &= ~L3_PRIO_CREDITS_MASK;
+ val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2);
+ I915_WRITE(GEN8_L3SQCREG1, val);
+ }
+
/* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES));
@@ -1258,14 +1267,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
return ret;
}
- /* WaProgramL3SqcReg1DefaultForPerf:bxt */
- if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
- u32 val = I915_READ(GEN8_L3SQCREG1);
- val &= ~L3_PRIO_CREDITS_MASK;
- val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2);
- I915_WRITE(GEN8_L3SQCREG1, val);
- }
-
/* WaToEnableHwFixForPushConstHWBug:bxt */
if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
--
2.7.4
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too
2017-11-14 13:05 [PATCH] drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too Valtteri Rantala
@ 2017-11-14 13:18 ` Patchwork
2017-11-15 17:52 ` [PATCH] " David Weinehall
1 sibling, 0 replies; 5+ messages in thread
From: Patchwork @ 2017-11-14 13:18 UTC (permalink / raw)
To: Valtteri Rantala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too
URL : https://patchwork.freedesktop.org/series/33772/
State : failure
== Summary ==
Series 33772v1 drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too
https://patchwork.freedesktop.org/api/1.0/series/33772/revisions/1/mbox/
Test chamelium:
Subgroup dp-crc-fast:
fail -> PASS (fi-kbl-7500u) fdo#102514
Test gem_exec_reloc:
Subgroup basic-write-gtt:
pass -> INCOMPLETE (fi-byt-j1900)
Test kms_frontbuffer_tracking:
Subgroup basic:
pass -> FAIL (fi-skl-6600u)
fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:443s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:456s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:389s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:532s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:276s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:503s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:505s
fi-byt-j1900 total:88 pass:69 dwarn:0 dfail:0 fail:0 skip:18
fi-byt-n2820 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:486s
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:425s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:264s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:543s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:429s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:439s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:428s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:488s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:458s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:482s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:525s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:480s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:528s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:566s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:455s
fi-skl-6600u total:289 pass:261 dwarn:0 dfail:0 fail:1 skip:27 time:537s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:564s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:518s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:500s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:464s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:563s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:422s
Blacklisted hosts:
fi-cfl-s total:289 pass:254 dwarn:3 dfail:0 fail:0 skip:32 time:526s
fi-cnl-y total:289 pass:261 dwarn:0 dfail:0 fail:1 skip:27 time:578s
fi-glk-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:506s
150c0315ce448d88e22e7e675eed6e55abbe04cd drm-tip: 2017y-11m-14d-10h-02m-23s UTC integration manifest
3d37cc771ce0 drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7113/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too
2017-11-14 13:05 [PATCH] drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too Valtteri Rantala
2017-11-14 13:18 ` ✗ Fi.CI.BAT: failure for " Patchwork
@ 2017-11-15 17:52 ` David Weinehall
2017-11-22 12:23 ` Imre Deak
1 sibling, 1 reply; 5+ messages in thread
From: David Weinehall @ 2017-11-15 17:52 UTC (permalink / raw)
To: Valtteri Rantala; +Cc: intel-gfx, Altug Koker
On Tue, Nov 14, 2017 at 03:05:03PM +0200, Valtteri Rantala wrote:
> Testing the texture read performance shows that the same tuning for the
> SQ credits is needed on GLK as on BXT/APL. This has been also confirmed
> by Altug from the HW team.
>
> Cc: Altug Koker <altug.koker@intel.com>
> Signed-off-by: Valtteri Rantala <valtteri.rantala@intel.com>
With comments below, and unless Altug has objections:
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_engine_cs.c | 17 +++++++++--------
> 1 file changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 70bbe8e..11fc0bd 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1093,6 +1093,15 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
> /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
> WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
>
> + /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
> + if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER) ||
> + IS_GEMINILAKE(dev_priv)) {
Since we've dropped workarounds for pre-production Broxtons,
I think this could/should be simplified to:
if (IS_BROXTON(dev_priv) || IS_GEMINILAKE(dev_priv)) {
or even
if (IS_GEN9_LP(dev_priv)) {
But that's just nitpicking. The fix is sound from a performance
perspective.
> + u32 val = I915_READ(GEN8_L3SQCREG1);
> + val &= ~L3_PRIO_CREDITS_MASK;
> + val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2);
> + I915_WRITE(GEN8_L3SQCREG1, val);
> + }
> +
> /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
> I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
> GEN8_LQSC_FLUSH_COHERENT_LINES));
> @@ -1258,14 +1267,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
> return ret;
> }
>
> - /* WaProgramL3SqcReg1DefaultForPerf:bxt */
> - if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
> - u32 val = I915_READ(GEN8_L3SQCREG1);
> - val &= ~L3_PRIO_CREDITS_MASK;
> - val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2);
> - I915_WRITE(GEN8_L3SQCREG1, val);
> - }
> -
> /* WaToEnableHwFixForPushConstHWBug:bxt */
> if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
> WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
> --
> 2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too
2017-11-15 17:52 ` [PATCH] " David Weinehall
@ 2017-11-22 12:23 ` Imre Deak
2017-11-22 12:37 ` Rantala, Valtteri
0 siblings, 1 reply; 5+ messages in thread
From: Imre Deak @ 2017-11-22 12:23 UTC (permalink / raw)
To: Valtteri Rantala, intel-gfx, Altug Koker, David Weinehall
On Wed, Nov 15, 2017 at 07:52:05PM +0200, David Weinehall wrote:
> On Tue, Nov 14, 2017 at 03:05:03PM +0200, Valtteri Rantala wrote:
> > Testing the texture read performance shows that the same tuning for the
> > SQ credits is needed on GLK as on BXT/APL. This has been also confirmed
> > by Altug from the HW team.
> >
> > Cc: Altug Koker <altug.koker@intel.com>
> > Signed-off-by: Valtteri Rantala <valtteri.rantala@intel.com>
>
> With comments below, and unless Altug has objections:
>
> Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_engine_cs.c | 17 +++++++++--------
> > 1 file changed, 9 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index 70bbe8e..11fc0bd 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -1093,6 +1093,15 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
> > /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
> > WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
> >
> > + /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
> > + if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER) ||
> > + IS_GEMINILAKE(dev_priv)) {
>
> Since we've dropped workarounds for pre-production Broxtons,
> I think this could/should be simplified to:
>
> if (IS_BROXTON(dev_priv) || IS_GEMINILAKE(dev_priv)) {
>
> or even
>
> if (IS_GEN9_LP(dev_priv)) {
>
> But that's just nitpicking. The fix is sound from a performance
> perspective.
Yes, meanwhile
commit 70a84f3c6075031dbf004a1610ca2471f4c528aa
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Tue Nov 14 13:43:40 2017 +0000
drm/i915: Unconditionally apply the Broxton register workaround set
was merged, so we should use IS_GEN9_LP() above. Valtteri, could you
rebase/resend the patch?
>
> > + u32 val = I915_READ(GEN8_L3SQCREG1);
> > + val &= ~L3_PRIO_CREDITS_MASK;
> > + val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2);
> > + I915_WRITE(GEN8_L3SQCREG1, val);
> > + }
> > +
> > /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
> > I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
> > GEN8_LQSC_FLUSH_COHERENT_LINES));
> > @@ -1258,14 +1267,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
> > return ret;
> > }
> >
> > - /* WaProgramL3SqcReg1DefaultForPerf:bxt */
> > - if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
> > - u32 val = I915_READ(GEN8_L3SQCREG1);
> > - val &= ~L3_PRIO_CREDITS_MASK;
> > - val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2);
> > - I915_WRITE(GEN8_L3SQCREG1, val);
> > - }
> > -
> > /* WaToEnableHwFixForPushConstHWBug:bxt */
> > if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
> > WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
> > --
> > 2.7.4
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too
2017-11-22 12:23 ` Imre Deak
@ 2017-11-22 12:37 ` Rantala, Valtteri
0 siblings, 0 replies; 5+ messages in thread
From: Rantala, Valtteri @ 2017-11-22 12:37 UTC (permalink / raw)
To: Deak, Imre, intel-gfx, Koker, Altug, David Weinehall
> -----Original Message-----
> From: Deak, Imre
> Sent: Wednesday, November 22, 2017 2:24 PM
> To: Rantala, Valtteri <valtteri.rantala@intel.com>; intel-
> gfx@lists.freedesktop.org; Koker, Altug <altug.koker@intel.com>; David
> Weinehall <david.weinehall@linux.intel.com>
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/glk: Apply
> WaProgramL3SqcReg1DefaultForPerf for GLK too
>
> On Wed, Nov 15, 2017 at 07:52:05PM +0200, David Weinehall wrote:
> > On Tue, Nov 14, 2017 at 03:05:03PM +0200, Valtteri Rantala wrote:
> > > Testing the texture read performance shows that the same tuning for
> > > the SQ credits is needed on GLK as on BXT/APL. This has been also
> > > confirmed by Altug from the HW team.
> > >
> > > Cc: Altug Koker <altug.koker@intel.com>
> > > Signed-off-by: Valtteri Rantala <valtteri.rantala@intel.com>
> >
> > With comments below, and unless Altug has objections:
> >
> > Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_engine_cs.c | 17 +++++++++--------
> > > 1 file changed, 9 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
> > > b/drivers/gpu/drm/i915/intel_engine_cs.c
> > > index 70bbe8e..11fc0bd 100644
> > > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > > @@ -1093,6 +1093,15 @@ static int gen9_init_workarounds(struct
> intel_engine_cs *engine)
> > > /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
> > > WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
> > >
> > > + /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
> > > + if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER) ||
> > > + IS_GEMINILAKE(dev_priv)) {
> >
> > Since we've dropped workarounds for pre-production Broxtons, I think
> > this could/should be simplified to:
> >
> > if (IS_BROXTON(dev_priv) || IS_GEMINILAKE(dev_priv)) {
> >
> > or even
> >
> > if (IS_GEN9_LP(dev_priv)) {
> >
> > But that's just nitpicking. The fix is sound from a performance
> > perspective.
>
> Yes, meanwhile
>
> commit 70a84f3c6075031dbf004a1610ca2471f4c528aa
> Author: Chris Wilson <chris@chris-wilson.co.uk>
> Date: Tue Nov 14 13:43:40 2017 +0000
>
> drm/i915: Unconditionally apply the Broxton register workaround set
>
> was merged, so we should use IS_GEN9_LP() above. Valtteri, could you
> rebase/resend the patch?
Yes, I'll rebase/resend the patch. I'll use IS_GEN9_LP().
>
> >
> > > + u32 val = I915_READ(GEN8_L3SQCREG1);
> > > + val &= ~L3_PRIO_CREDITS_MASK;
> > > + val |= L3_GENERAL_PRIO_CREDITS(62) |
> L3_HIGH_PRIO_CREDITS(2);
> > > + I915_WRITE(GEN8_L3SQCREG1, val);
> > > + }
> > > +
> > > /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
> > > I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
> > > GEN8_LQSC_FLUSH_COHERENT_LINES));
> @@ -1258,14 +1267,6 @@
> > > static int bxt_init_workarounds(struct intel_engine_cs *engine)
> > > return ret;
> > > }
> > >
> > > - /* WaProgramL3SqcReg1DefaultForPerf:bxt */
> > > - if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
> > > - u32 val = I915_READ(GEN8_L3SQCREG1);
> > > - val &= ~L3_PRIO_CREDITS_MASK;
> > > - val |= L3_GENERAL_PRIO_CREDITS(62) |
> L3_HIGH_PRIO_CREDITS(2);
> > > - I915_WRITE(GEN8_L3SQCREG1, val);
> > > - }
> > > -
> > > /* WaToEnableHwFixForPushConstHWBug:bxt */
> > > if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
> > > WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
> > > --
> > > 2.7.4
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-11-22 12:37 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-11-14 13:05 [PATCH] drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too Valtteri Rantala
2017-11-14 13:18 ` ✗ Fi.CI.BAT: failure for " Patchwork
2017-11-15 17:52 ` [PATCH] " David Weinehall
2017-11-22 12:23 ` Imre Deak
2017-11-22 12:37 ` Rantala, Valtteri
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