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From: Andrei Kartashev <a.kartashev@yadro.com>
To: Chia-Wei Wang <chiawei_wang@aspeedtech.com>, <robh+dt@kernel.org>,
	<joel@jms.id.au>, <andrew@aj.id.au>,
	<linux-aspeed@lists.ozlabs.org>, <openbmc@lists.ozlabs.org>,
	<devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Cc: <ryan_chen@aspeedtech.com>
Subject: Re: [PATCH v4 4/4] ARM: dts: aspeed: Add eSPI node
Date: Wed, 10 Nov 2021 14:21:23 +0300	[thread overview]
Message-ID: <1a063a1797fd9247dae3660cd04d1f19b0fc32b8.camel@yadro.com> (raw)
In-Reply-To: <20210901033015.910-5-chiawei_wang@aspeedtech.com>

Hi Chia-Wei,

How is it about g5? Why did you add definition only for g6 here?


On Wed, 2021-09-01 at 11:30 +0800, Chia-Wei Wang wrote:
> Add eSPI to the device tree for Aspeed 5/6th generation SoCs.
> 
> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> ---
>  arch/arm/boot/dts/aspeed-g6.dtsi | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi
> b/arch/arm/boot/dts/aspeed-g6.dtsi
> index f96607b7b4e2..47dc0b3993d1 100644
> --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> @@ -364,6 +364,23 @@
>                                 status = "disabled";
>                         };
>  
> +                       espi: espi@1e6ee000 {
> +                               compatible = "aspeed,ast2600-espi",
> "simple-mfd", "syscon";
> +                               reg = <0x1e6ee000 0x1000>;
> +
> +                               #address-cells = <1>;
> +                               #size-cells = <1>;
> +                               ranges = <0x0 0x1e6ee000 0x1000>;
> +
> +                               espi_ctrl: espi-ctrl@0 {
> +                                       compatible = "aspeed,ast2600-
> espi-ctrl";
> +                                       reg = <0x0 0x800>;
> +                                       interrupts = <GIC_SPI 42
> IRQ_TYPE_LEVEL_HIGH>;
> +                                       clocks = <&syscon
> ASPEED_CLK_GATE_ESPICLK>;
> +                                       status = "disabled";
> +                               };
> +                       };
> +
>                         gpio0: gpio@1e780000 {
>                                 #gpio-cells = <2>;
>                                 gpio-controller;

-- 
Best regards,
Andrei Kartashev



WARNING: multiple messages have this Message-ID (diff)
From: Andrei Kartashev <a.kartashev@yadro.com>
To: Chia-Wei Wang <chiawei_wang@aspeedtech.com>, <robh+dt@kernel.org>,
	<joel@jms.id.au>, <andrew@aj.id.au>,
	<linux-aspeed@lists.ozlabs.org>, <openbmc@lists.ozlabs.org>,
	<devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Cc: ryan_chen@aspeedtech.com
Subject: Re: [PATCH v4 4/4] ARM: dts: aspeed: Add eSPI node
Date: Wed, 10 Nov 2021 14:21:23 +0300	[thread overview]
Message-ID: <1a063a1797fd9247dae3660cd04d1f19b0fc32b8.camel@yadro.com> (raw)
In-Reply-To: <20210901033015.910-5-chiawei_wang@aspeedtech.com>

Hi Chia-Wei,

How is it about g5? Why did you add definition only for g6 here?


On Wed, 2021-09-01 at 11:30 +0800, Chia-Wei Wang wrote:
> Add eSPI to the device tree for Aspeed 5/6th generation SoCs.
> 
> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> ---
>  arch/arm/boot/dts/aspeed-g6.dtsi | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi
> b/arch/arm/boot/dts/aspeed-g6.dtsi
> index f96607b7b4e2..47dc0b3993d1 100644
> --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> @@ -364,6 +364,23 @@
>                                 status = "disabled";
>                         };
>  
> +                       espi: espi@1e6ee000 {
> +                               compatible = "aspeed,ast2600-espi",
> "simple-mfd", "syscon";
> +                               reg = <0x1e6ee000 0x1000>;
> +
> +                               #address-cells = <1>;
> +                               #size-cells = <1>;
> +                               ranges = <0x0 0x1e6ee000 0x1000>;
> +
> +                               espi_ctrl: espi-ctrl@0 {
> +                                       compatible = "aspeed,ast2600-
> espi-ctrl";
> +                                       reg = <0x0 0x800>;
> +                                       interrupts = <GIC_SPI 42
> IRQ_TYPE_LEVEL_HIGH>;
> +                                       clocks = <&syscon
> ASPEED_CLK_GATE_ESPICLK>;
> +                                       status = "disabled";
> +                               };
> +                       };
> +
>                         gpio0: gpio@1e780000 {
>                                 #gpio-cells = <2>;
>                                 gpio-controller;

-- 
Best regards,
Andrei Kartashev



WARNING: multiple messages have this Message-ID (diff)
From: Andrei Kartashev <a.kartashev@yadro.com>
To: Chia-Wei Wang <chiawei_wang@aspeedtech.com>, <robh+dt@kernel.org>,
	<joel@jms.id.au>, <andrew@aj.id.au>,
	<linux-aspeed@lists.ozlabs.org>, <openbmc@lists.ozlabs.org>,
	<devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Cc: <ryan_chen@aspeedtech.com>
Subject: Re: [PATCH v4 4/4] ARM: dts: aspeed: Add eSPI node
Date: Wed, 10 Nov 2021 14:21:23 +0300	[thread overview]
Message-ID: <1a063a1797fd9247dae3660cd04d1f19b0fc32b8.camel@yadro.com> (raw)
In-Reply-To: <20210901033015.910-5-chiawei_wang@aspeedtech.com>

Hi Chia-Wei,

How is it about g5? Why did you add definition only for g6 here?


On Wed, 2021-09-01 at 11:30 +0800, Chia-Wei Wang wrote:
> Add eSPI to the device tree for Aspeed 5/6th generation SoCs.
> 
> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> ---
>  arch/arm/boot/dts/aspeed-g6.dtsi | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi
> b/arch/arm/boot/dts/aspeed-g6.dtsi
> index f96607b7b4e2..47dc0b3993d1 100644
> --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> @@ -364,6 +364,23 @@
>                                 status = "disabled";
>                         };
>  
> +                       espi: espi@1e6ee000 {
> +                               compatible = "aspeed,ast2600-espi",
> "simple-mfd", "syscon";
> +                               reg = <0x1e6ee000 0x1000>;
> +
> +                               #address-cells = <1>;
> +                               #size-cells = <1>;
> +                               ranges = <0x0 0x1e6ee000 0x1000>;
> +
> +                               espi_ctrl: espi-ctrl@0 {
> +                                       compatible = "aspeed,ast2600-
> espi-ctrl";
> +                                       reg = <0x0 0x800>;
> +                                       interrupts = <GIC_SPI 42
> IRQ_TYPE_LEVEL_HIGH>;
> +                                       clocks = <&syscon
> ASPEED_CLK_GATE_ESPICLK>;
> +                                       status = "disabled";
> +                               };
> +                       };
> +
>                         gpio0: gpio@1e780000 {
>                                 #gpio-cells = <2>;
>                                 gpio-controller;

-- 
Best regards,
Andrei Kartashev



_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-11-10 11:21 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-01  3:30 [PATCH v4 0/4] arm: aspeed: Add eSPI support Chia-Wei Wang
2021-09-01  3:30 ` Chia-Wei Wang
2021-09-01  3:30 ` Chia-Wei Wang
2021-09-01  3:30 ` [PATCH v4 1/4] dt-bindings: aspeed: Add eSPI controller Chia-Wei Wang
2021-09-01  3:30   ` Chia-Wei Wang
2021-09-01  3:30   ` Chia-Wei Wang
2021-09-01  3:30 ` [PATCH v4 2/4] MAINTAINER: Add ASPEED eSPI driver entry Chia-Wei Wang
2021-09-01  3:30   ` Chia-Wei Wang
2021-09-01  3:30   ` Chia-Wei Wang
2021-09-01  3:30 ` [PATCH v4 3/4] soc: aspeed: Add eSPI driver Chia-Wei Wang
2021-09-01  3:30   ` Chia-Wei Wang
2021-09-01  3:30   ` Chia-Wei Wang
2021-09-02  3:29   ` Jeremy Kerr
2021-09-02  3:29     ` Jeremy Kerr
2021-09-02  3:29     ` Jeremy Kerr
2021-09-02  6:44     ` ChiaWei Wang
2021-09-02  6:44       ` ChiaWei Wang
2021-09-02  6:44       ` ChiaWei Wang
2021-09-02  7:04       ` Jeremy Kerr
2021-09-02  7:04         ` Jeremy Kerr
2021-09-02  7:04         ` Jeremy Kerr
2021-09-06  1:19         ` ChiaWei Wang
2021-09-06  1:19           ` ChiaWei Wang
2021-09-06  1:19           ` ChiaWei Wang
2021-09-06  3:16           ` Jeremy Kerr
2021-09-06  3:16             ` Jeremy Kerr
2021-09-06  3:16             ` Jeremy Kerr
2021-09-08  9:16             ` ChiaWei Wang
2021-09-08  9:16               ` ChiaWei Wang
2021-09-08  9:16               ` ChiaWei Wang
2021-09-09  1:52               ` Jeremy Kerr
2021-09-09  1:52                 ` Jeremy Kerr
2021-09-09  1:52                 ` Jeremy Kerr
2021-09-10  3:23                 ` ChiaWei Wang
2021-09-10  3:23                   ` ChiaWei Wang
2021-09-10  3:23                   ` ChiaWei Wang
2021-09-01  3:30 ` [PATCH v4 4/4] ARM: dts: aspeed: Add eSPI node Chia-Wei Wang
2021-09-01  3:30   ` Chia-Wei Wang
2021-09-01  3:30   ` Chia-Wei Wang
2021-11-10 11:21   ` Andrei Kartashev [this message]
2021-11-10 11:21     ` Andrei Kartashev
2021-11-10 11:21     ` Andrei Kartashev
2021-11-11  1:55     ` ChiaWei Wang
2021-11-11  1:55       ` ChiaWei Wang

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